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authorAkshay <[email protected]>2022-04-10 12:13:40 +0100
committerAkshay <[email protected]>2022-04-10 12:13:40 +0100
commitdc90387ce7d8ba7b607d9c48540bf6d8b560f14d (patch)
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1/*
2** ###################################################################
3** Processor: LPC832M101FDH20
4** Compilers: GNU C Compiler
5** IAR ANSI C/C++ Compiler for ARM
6** Keil ARM C/C++ Compiler
7** MCUXpresso Compiler
8**
9** Reference manual: LPC83x User manual Rev.1.1 5 October 2016
10** Version: rev. 1.1, 2018-02-25
11** Build: b200509
12**
13** Abstract:
14** CMSIS Peripheral Access Layer for LPC832
15**
16** Copyright 1997-2016 Freescale Semiconductor, Inc.
17** Copyright 2016-2020 NXP
18** All rights reserved.
19**
20** SPDX-License-Identifier: BSD-3-Clause
21**
22** http: www.nxp.com
23** mail: [email protected]
24**
25** Revisions:
26** - rev. 1.0 (2018-02-09)
27** Initial version.
28** - rev. 1.1 (2018-02-25)
29** Update some registers according to UM rev 1.2
30**
31** ###################################################################
32*/
33
34/*!
35 * @file LPC832.h
36 * @version 1.1
37 * @date 2018-02-25
38 * @brief CMSIS Peripheral Access Layer for LPC832
39 *
40 * CMSIS Peripheral Access Layer for LPC832
41 */
42
43#ifndef _LPC832_H_
44#define _LPC832_H_ /**< Symbol preventing repeated inclusion */
45
46/** Memory map major version (memory maps with equal major version number are
47 * compatible) */
48#define MCU_MEM_MAP_VERSION 0x0100U
49/** Memory map minor version */
50#define MCU_MEM_MAP_VERSION_MINOR 0x0001U
51
52
53/* ----------------------------------------------------------------------------
54 -- Interrupt vector numbers
55 ---------------------------------------------------------------------------- */
56
57/*!
58 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
59 * @{
60 */
61
62/** Interrupt Number Definitions */
63#define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */
64
65typedef enum IRQn {
66 /* Auxiliary constants */
67 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
68
69 /* Core interrupts */
70 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
71 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
72 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
73 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
74 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
75
76 /* Device specific interrupts */
77 SPI0_IRQn = 0, /**< SPI0 interrupt */
78 SPI1_IRQn = 1, /**< SPI1 interrupt */
79 Reserved18_IRQn = 2, /**< Reserved interrupt */
80 USART0_IRQn = 3, /**< USART0 interrupt */
81 Reserved20_IRQn = 4, /**< Reserved interrupt */
82 Reserved21_IRQn = 5, /**< Reserved interrupt */
83 Reserved22_IRQn = 6, /**< Reserved interrupt */
84 Reserved23_IRQn = 7, /**< Reserved interrupt */
85 I2C0_IRQn = 8, /**< I2C0 interrupt */
86 SCT0_IRQn = 9, /**< State configurable timer interrupt */
87 MRT0_IRQn = 10, /**< Multi-rate timer interrupt */
88 Reserved27_IRQn = 11, /**< Reserved interrupt */
89 WDT_IRQn = 12, /**< Windowed watchdog timer interrupt */
90 BOD_IRQn = 13, /**< BOD interrupts */
91 FLASH_IRQn = 14, /**< flash interrupt */
92 WKT_IRQn = 15, /**< Self-wake-up timer interrupt */
93 ADC0_SEQA_IRQn = 16, /**< ADC0 sequence A completion. */
94 ADC0_SEQB_IRQn = 17, /**< ADC0 sequence B completion. */
95 ADC0_THCMP_IRQn = 18, /**< ADC0 threshold compare and error. */
96 ADC0_OVR_IRQn = 19, /**< ADC0 overrun */
97 DMA0_IRQn = 20, /**< DMA0 interrupt */
98 Reserved37_IRQn = 21, /**< Reserved interrupt */
99 Reserved38_IRQn = 22, /**< Reserved interrupt */
100 Reserved39_IRQn = 23, /**< Reserved interrupt */
101 PIN_INT0_IRQn = 24, /**< Pin interrupt 0 or pattern match engine slice 0 interrupt */
102 PIN_INT1_IRQn = 25, /**< Pin interrupt 1 or pattern match engine slice 1 interrupt */
103 PIN_INT2_IRQn = 26, /**< Pin interrupt 2 or pattern match engine slice 2 interrupt */
104 PIN_INT3_IRQn = 27, /**< Pin interrupt 3 or pattern match engine slice 3 interrupt */
105 PIN_INT4_IRQn = 28, /**< Pin interrupt 4 or pattern match engine slice 4 interrupt */
106 PIN_INT5_IRQn = 29, /**< Pin interrupt 5 or pattern match engine slice 5 interrupt */
107 PIN_INT6_IRQn = 30, /**< Pin interrupt 6 or pattern match engine slice 6 interrupt */
108 PIN_INT7_IRQn = 31 /**< Pin interrupt 7 or pattern match engine slice 7 interrupt */
109} IRQn_Type;
110
111/*!
112 * @}
113 */ /* end of group Interrupt_vector_numbers */
114
115
116/* ----------------------------------------------------------------------------
117 -- Cortex M0 Core Configuration
118 ---------------------------------------------------------------------------- */
119
120/*!
121 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
122 * @{
123 */
124
125#define __CM0PLUS_REV 0x0000 /**< Core revision r0p1 */
126#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
127#define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */
128#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
129#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
130
131#include "core_cm0plus.h" /* Core Peripheral Access Layer */
132#include "system_LPC832.h" /* Device specific configuration file */
133
134/*!
135 * @}
136 */ /* end of group Cortex_Core_Configuration */
137
138
139/* ----------------------------------------------------------------------------
140 -- Mapping Information
141 ---------------------------------------------------------------------------- */
142
143/*!
144 * @addtogroup Mapping_Information Mapping Information
145 * @{
146 */
147
148/** Mapping Information */
149/*!
150 * @addtogroup dma_request
151 * @{
152 */
153
154/*******************************************************************************
155 * Definitions
156 ******************************************************************************/
157
158/*!
159 * @brief Structure for the DMA hardware request
160 *
161 * Defines the structure for the DMA hardware request collections. The user can configure the
162 * hardware request to trigger the DMA transfer accordingly. The index
163 * of the hardware request varies according to the to SoC.
164 */
165typedef enum _dma_request_source
166{
167 kDmaRequestUSART0_RX_DMA = 0U, /**< USART0 RX DMA */
168 kDmaRequestUSART0_TX_DMA = 1U, /**< USART0 TX DMA */
169 kDmaRequestUSART1_RX_DMA = 2U, /**< USART1 RX DMA */
170 kDmaRequestUSART1_TX_DMA = 3U, /**< USART1 TX DMA */
171 kDmaRequestUSART2_RX_DMA = 4U, /**< USART2 RX DMA */
172 kDmaRequestUSART2_TX_DMA = 5U, /**< USART2 TX DMA */
173 kDmaRequestSPI0_RX_DMA = 6U, /**< SPI0 RX DMA */
174 kDmaRequestSPI0_TX_DMA = 7U, /**< SPI0 TX DMA */
175 kDmaRequestSPI1_RX_DMA = 8U, /**< SPI1 RX DMA */
176 kDmaRequestSPI1_TX_DMA = 9U, /**< SPI1 TX DMA */
177 kDmaRequestI2C0_SLV_DMA = 10U, /**< I2C0 SLAVE DMA */
178 kDmaRequestI2C0_MST_DMA = 11U, /**< I2C0 MASTER DMA */
179 kDmaRequestI2C1_SLV_DMA = 12U, /**< I2C1 SLAVE DMA */
180 kDmaRequestI2C1_MST_DMA = 13U, /**< I2C1 MASTER DMA */
181 kDmaRequestI2C2_SLV_DMA = 14U, /**< I2C2 SLAVE DMA */
182 kDmaRequestI2C2_MST_DMA = 15U, /**< I2C2 MASTER DMA */
183 kDmaRequestI2C3_SLV_DMA = 16U, /**< I2C3 SLAVE DMA */
184 kDmaRequestI2C3_MST_DMA = 17U, /**< I2C3 MASTER DMA */
185} dma_request_source_t;
186
187/* @} */
188
189
190/*!
191 * @}
192 */ /* end of group Mapping_Information */
193
194
195/* ----------------------------------------------------------------------------
196 -- Device Peripheral Access Layer
197 ---------------------------------------------------------------------------- */
198
199/*!
200 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
201 * @{
202 */
203
204
205/*
206** Start of section using anonymous unions
207*/
208
209#if defined(__ARMCC_VERSION)
210 #if (__ARMCC_VERSION >= 6010050)
211 #pragma clang diagnostic push
212 #else
213 #pragma push
214 #pragma anon_unions
215 #endif
216#elif defined(__GNUC__)
217 /* anonymous unions are enabled by default */
218#elif defined(__IAR_SYSTEMS_ICC__)
219 #pragma language=extended
220#else
221 #error Not supported compiler type
222#endif
223
224/* ----------------------------------------------------------------------------
225 -- ADC Peripheral Access Layer
226 ---------------------------------------------------------------------------- */
227
228/*!
229 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
230 * @{
231 */
232
233/** ADC - Register Layout Typedef */
234typedef struct {
235 __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */
236 uint8_t RESERVED_0[4];
237 __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */
238 __IO uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */
239 uint8_t RESERVED_1[8];
240 __I uint32_t DAT[12]; /**< ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N., array offset: 0x20, array step: 0x4 */
241 __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */
242 __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */
243 __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */
244 __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */
245 __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */
246 __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */
247 __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */
248 __IO uint32_t TRM; /**< ADC Startup register., offset: 0x6C */
249} ADC_Type;
250
251/* ----------------------------------------------------------------------------
252 -- ADC Register Masks
253 ---------------------------------------------------------------------------- */
254
255/*!
256 * @addtogroup ADC_Register_Masks ADC Register Masks
257 * @{
258 */
259
260/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */
261/*! @{ */
262#define ADC_CTRL_CLKDIV_MASK (0xFFU)
263#define ADC_CTRL_CLKDIV_SHIFT (0U)
264/*! CLKDIV - In synchronous mode only, the system clock is divided by this value plus one to produce
265 * the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically,
266 * software should program the smallest value in this field that yields this maximum clock rate or
267 * slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may
268 * be desirable. This field is ignored in the asynchronous operating mode.
269 */
270#define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)
271#define ADC_CTRL_LPWRMODE_MASK (0x400U)
272#define ADC_CTRL_LPWRMODE_SHIFT (10U)
273/*! LPWRMODE - The low-power ADC mode
274 * 0b0..The low-power ADC mode is disabled. The analog circuitry remains activated even when no conversions are requested.
275 * 0b1..The low-power ADC mode is enabled. The analog circuitry is automatically powered-down when no conversions
276 * are taking place. When any (hardware or software) triggering event is detected, the analog circuitry is
277 * enabled. After the required start-up time, the requested conversion will be launched. Once the conversion
278 * completes, the analog-circuitry will again be powered-down provided no further conversions are pending.
279 * Using this mode can save an appreciable amount of current (approximately 2.5 mA) when conversions are
280 * required relatively infrequently. The penalty for using this mode is an approximately FIFTEEN ADC CLOCK delay (30
281 * clocks in 10-bit mode), based on the frequency specified in the CLKDIV field, from the time the trigger
282 * event occurs until sampling of the A/D input commences. Note: This mode will NOT power-up the A/D if the
283 * ADC_ENA bit is low.
284 */
285#define ADC_CTRL_LPWRMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_LPWRMODE_SHIFT)) & ADC_CTRL_LPWRMODE_MASK)
286#define ADC_CTRL_CALMODE_MASK (0x40000000U)
287#define ADC_CTRL_CALMODE_SHIFT (30U)
288/*! CALMODE - Writing a '1' to this bit will initiate a sef-calibration cycle. This bit will be
289 * automatically cleared by hardware after the calibration cycle is complete. Note: Other bits of
290 * this register may be written to concurrently with setting this bit, however once this bit has
291 * been set no further writes to this register are permitted unitl the full calibration cycle has
292 * ended.
293 */
294#define ADC_CTRL_CALMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALMODE_SHIFT)) & ADC_CTRL_CALMODE_MASK)
295/*! @} */
296
297/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */
298/*! @{ */
299#define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU)
300#define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U)
301/*! CHANNELS - Selects which one or more of the ADC channels will be sampled and converted when this
302 * sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be
303 * included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1
304 * and so forth. When this conversion sequence is triggered, either by a hardware trigger or via
305 * software command, ADC conversions will be performed on each enabled channel, in sequence,
306 * beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31)
307 * is LOW. It is allowed to change this field and set bit 31 in the same write.
308 */
309#define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)
310#define ADC_SEQ_CTRL_TRIGGER_MASK (0x7000U)
311#define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U)
312/*! TRIGGER - Selects which of the available hardware trigger sources will cause this conversion
313 * sequence to be initiated. Program the trigger input number in this field. See Table 476. In order
314 * to avoid generating a spurious trigger, it is recommended writing to this field only when
315 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
316 */
317#define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)
318#define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U)
319#define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U)
320/*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In
321 * order to avoid generating a spurious trigger, it is recommended writing to this field only when
322 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.
323 * 0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input.
324 * 0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input.
325 */
326#define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)
327#define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U)
328#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U)
329/*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization
330 * flip-flop stages and therefore shorten the time between the trigger input signal and the start of a
331 * conversion. There are slightly different criteria for whether or not this bit can be set
332 * depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0):
333 * Synchronization may be bypassed (this bit may be set) if the selected trigger source is already
334 * synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer).
335 * Whether this bit is set or not, a trigger pulse must be maintained for at least one system
336 * clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be
337 * bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse
338 * will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and
339 * on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be
340 * maintained for one system clock period.
341 * 0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled.
342 * 0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled.
343 */
344#define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)
345#define ADC_SEQ_CTRL_START_MASK (0x4000000U)
346#define ADC_SEQ_CTRL_START_SHIFT (26U)
347/*! START - Writing a 1 to this field will launch one pass through this conversion sequence. The
348 * behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this
349 * bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a
350 * conversion sequence. It will consequently always read back as a zero.
351 */
352#define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)
353#define ADC_SEQ_CTRL_BURST_MASK (0x8000000U)
354#define ADC_SEQ_CTRL_BURST_SHIFT (27U)
355/*! BURST - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled
356 * through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions
357 * can be halted by clearing this bit. The sequence currently in progress will be completed before
358 * conversions are terminated. Note that a new sequence could begin just before BURST is cleared.
359 */
360#define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)
361#define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U)
362#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U)
363/*! SINGLESTEP - When this bit is set, a hardware trigger or a write to the START bit will launch a
364 * single conversion on the next channel in the sequence instead of the default response of
365 * launching an entire sequence of conversions. Once all of the channels comprising a sequence have
366 * been converted, a subsequent trigger will repeat the sequence beginning with the first enabled
367 * channel. Interrupt generation will still occur either after each individual conversion or at
368 * the end of the entire sequence, depending on the state of the MODE bit.
369 */
370#define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)
371#define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U)
372#define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U)
373/*! LOWPRIO - Set priority for sequence A.
374 * 0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost.
375 * 0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence
376 * software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion
377 * currently in progress will be terminated. The A sequence that was interrupted will automatically resume
378 * after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the
379 * conversion sequence will resume from that point.
380 */
381#define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)
382#define ADC_SEQ_CTRL_MODE_MASK (0x40000000U)
383#define ADC_SEQ_CTRL_MODE_SHIFT (30U)
384/*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence
385 * will be accomplished via reading the global data register (SEQA_GDAT) at the end of each
386 * conversion, or the individual channel result registers at the end of the entire sequence. Impacts
387 * when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which
388 * overrun conditions contribute to an overrun interrupt as described below.
389 * 0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC
390 * conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The
391 * OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger
392 * if enabled.
393 * 0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A
394 * conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in
395 * this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun
396 * interrupt/DMA trigger since it is assumed this register may not be utilized in this mode.
397 */
398#define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)
399#define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U)
400#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U)
401/*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be
402 * taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state
403 * (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered
404 * immediately upon being enabled. In order to avoid spuriously triggering the sequence, care
405 * should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE
406 * state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be
407 * triggered immediately upon being enabled.
408 * 0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence
409 * n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is
410 * re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel.
411 * 0b1..Enabled. Sequence n is enabled.
412 */
413#define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)
414/*! @} */
415
416/* The count of ADC_SEQ_CTRL */
417#define ADC_SEQ_CTRL_COUNT (2U)
418
419/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */
420/*! @{ */
421#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U)
422#define ADC_SEQ_GDAT_RESULT_SHIFT (4U)
423/*! RESULT - This field contains the 12-bit ADC conversion result from the most recent conversion
424 * performed under conversion sequence associated with this register. The result is a binary
425 * fraction representing the voltage on the currently-selected input channel as it falls within the
426 * range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less
427 * than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input
428 * was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this
429 * result has not yet been read.
430 */
431#define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)
432#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U)
433#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U)
434/*! THCMPRANGE - Indicates whether the result of the last conversion performed was above, below or
435 * within the range established by the designated threshold comparison registers (THRn_LOW and
436 * THRn_HIGH).
437 */
438#define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)
439#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U)
440#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U)
441/*! THCMPCROSS - Indicates whether the result of the last conversion performed represented a
442 * crossing of the threshold level established by the designated LOW threshold comparison register
443 * (THRn_LOW) and, if so, in what direction the crossing occurred.
444 */
445#define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)
446#define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U)
447#define ADC_SEQ_GDAT_CHN_SHIFT (26U)
448/*! CHN - These bits contain the channel from which the RESULT bits were converted (e.g. 0000
449 * identifies channel 0, 0001 channel 1, etc.).
450 */
451#define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)
452#define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U)
453#define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U)
454/*! OVERRUN - This bit is set if a new conversion result is loaded into the RESULT field before a
455 * previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along
456 * with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun
457 * interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set
458 * to '0' (and if the overrun interrupt is enabled).
459 */
460#define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)
461#define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U)
462#define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U)
463/*! DATAVALID - This bit is set to '1' at the end of each conversion when a new result is loaded
464 * into the RESULT field. It is cleared whenever this register is read. This bit will cause a
465 * conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that
466 * sequence is set to 0 (and if the interrupt is enabled).
467 */
468#define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)
469/*! @} */
470
471/* The count of ADC_SEQ_GDAT */
472#define ADC_SEQ_GDAT_COUNT (2U)
473
474/*! @name DAT - ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N. */
475/*! @{ */
476#define ADC_DAT_RESULT_MASK (0xFFF0U)
477#define ADC_DAT_RESULT_SHIFT (4U)
478/*! RESULT - This field contains the 12-bit ADC conversion result from the last conversion performed
479 * on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin,
480 * as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on
481 * the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that
482 * the voltage on the input was close to, equal to, or greater than that on VREFP.
483 */
484#define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)
485#define ADC_DAT_THCMPRANGE_MASK (0x30000U)
486#define ADC_DAT_THCMPRANGE_SHIFT (16U)
487/*! THCMPRANGE - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion
488 * was greater than or equal to the value programmed into the designated LOW threshold register
489 * (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold
490 * register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value
491 * programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last
492 * completed conversion was greater than the value programmed into the designated HIGH threshold
493 * register (THRn_HIGH). 0x3 = Reserved.
494 */
495#define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)
496#define ADC_DAT_THCMPCROSS_MASK (0xC0000U)
497#define ADC_DAT_THCMPCROSS_SHIFT (18U)
498/*! THCMPCROSS - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The
499 * most recent completed conversion on this channel had the same relationship (above or below) to
500 * the threshold value established by the designated LOW threshold register (THRn_LOW) as did the
501 * previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing
502 * Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the
503 * previous sample on this channel was above the threshold value established by the designated LOW
504 * threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward
505 * Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred
506 * - i.e. the previous sample on this channel was below the threshold value established by the
507 * designated LOW threshold register (THRn_LOW) and the current sample is above that threshold.
508 */
509#define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)
510#define ADC_DAT_CHANNEL_MASK (0x3C000000U)
511#define ADC_DAT_CHANNEL_SHIFT (26U)
512/*! CHANNEL - This field is hard-coded to contain the channel number that this particular register
513 * relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1
514 * register, etc)
515 */
516#define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)
517#define ADC_DAT_OVERRUN_MASK (0x40000000U)
518#define ADC_DAT_OVERRUN_SHIFT (30U)
519/*! OVERRUN - This bit will be set to a 1 if a new conversion on this channel completes and
520 * overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit
521 * is set. This bit is cleared, along with the DONE bit, whenever this register is read or when
522 * the data related to this channel is read from either of the global SEQn_GDAT registers. This
523 * bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if
524 * the overrun interrupt is enabled. While it is allowed to include the same channels in both
525 * conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the
526 * data registers associated with any of the channels that are shared between the two sequences. Any
527 * erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
528 */
529#define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)
530#define ADC_DAT_DATAVALID_MASK (0x80000000U)
531#define ADC_DAT_DATAVALID_SHIFT (31U)
532/*! DATAVALID - This bit is set to 1 when an ADC conversion on this channel completes. This bit is
533 * cleared whenever this register is read or when the data related to this channel is read from
534 * either of the global SEQn_GDAT registers. While it is allowed to include the same channels in
535 * both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in
536 * the data registers associated with any of the channels that are shared between the two
537 * sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled.
538 */
539#define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)
540/*! @} */
541
542/* The count of ADC_DAT */
543#define ADC_DAT_COUNT (12U)
544
545/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
546/*! @{ */
547#define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U)
548#define ADC_THR0_LOW_THRLOW_SHIFT (4U)
549/*! THRLOW - Low threshold value against which ADC results will be compared
550 */
551#define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)
552/*! @} */
553
554/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
555/*! @{ */
556#define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U)
557#define ADC_THR1_LOW_THRLOW_SHIFT (4U)
558/*! THRLOW - Low threshold value against which ADC results will be compared
559 */
560#define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)
561/*! @} */
562
563/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
564/*! @{ */
565#define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U)
566#define ADC_THR0_HIGH_THRHIGH_SHIFT (4U)
567/*! THRHIGH - High threshold value against which ADC results will be compared
568 */
569#define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)
570/*! @} */
571
572/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
573/*! @{ */
574#define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U)
575#define ADC_THR1_HIGH_THRHIGH_SHIFT (4U)
576/*! THRHIGH - High threshold value against which ADC results will be compared
577 */
578#define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)
579/*! @} */
580
581/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */
582/*! @{ */
583#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U)
584#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U)
585/*! CH0_THRSEL - Threshold select for channel 0.
586 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
587 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
588 */
589#define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)
590#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U)
591#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U)
592/*! CH1_THRSEL - Threshold select for channel 1
593 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
594 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
595 */
596#define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)
597#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U)
598#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U)
599/*! CH2_THRSEL - Threshold select for channel 2.
600 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
601 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
602 */
603#define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)
604#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U)
605#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U)
606/*! CH3_THRSEL - Threshold select for channel 3.
607 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
608 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
609 */
610#define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)
611#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U)
612#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U)
613/*! CH4_THRSEL - Threshold select for channel 4.
614 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
615 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
616 */
617#define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)
618#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U)
619#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U)
620/*! CH5_THRSEL - Threshold select for channel 5.
621 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
622 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
623 */
624#define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)
625#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U)
626#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U)
627/*! CH6_THRSEL - Threshold select for channel 6.
628 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
629 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
630 */
631#define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)
632#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U)
633#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U)
634/*! CH7_THRSEL - Threshold select for channel 7.
635 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
636 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
637 */
638#define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)
639#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U)
640#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U)
641/*! CH8_THRSEL - Threshold select for channel 8.
642 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
643 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
644 */
645#define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)
646#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U)
647#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U)
648/*! CH9_THRSEL - Threshold select for channel 9.
649 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
650 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
651 */
652#define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)
653#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U)
654#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U)
655/*! CH10_THRSEL - Threshold select for channel 10.
656 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
657 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
658 */
659#define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)
660#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U)
661#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U)
662/*! CH11_THRSEL - Threshold select for channel 11.
663 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers.
664 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers.
665 */
666#define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)
667/*! @} */
668
669/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */
670/*! @{ */
671#define ADC_INTEN_SEQA_INTEN_MASK (0x1U)
672#define ADC_INTEN_SEQA_INTEN_SHIFT (0U)
673/*! SEQA_INTEN - Sequence A interrupt enable.
674 * 0b0..Disabled. The sequence A interrupt/DMA trigger is disabled.
675 * 0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of
676 * each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of
677 * conversions, depending on the MODE bit in the SEQA_CTRL register.
678 */
679#define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)
680#define ADC_INTEN_SEQB_INTEN_MASK (0x2U)
681#define ADC_INTEN_SEQB_INTEN_SHIFT (1U)
682/*! SEQB_INTEN - Sequence B interrupt enable.
683 * 0b0..Disabled. The sequence B interrupt/DMA trigger is disabled.
684 * 0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of
685 * each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of
686 * conversions, depending on the MODE bit in the SEQB_CTRL register.
687 */
688#define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)
689#define ADC_INTEN_OVR_INTEN_MASK (0x4U)
690#define ADC_INTEN_OVR_INTEN_SHIFT (2U)
691/*! OVR_INTEN - Overrun interrupt enable.
692 * 0b0..Disabled. The overrun interrupt is disabled.
693 * 0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel
694 * data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular
695 * sequence is 0, then an overrun in the global data register for that sequence will also cause this
696 * interrupt/DMA trigger to be asserted.
697 */
698#define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)
699#define ADC_INTEN_ADCMPINTEN0_MASK (0x18U)
700#define ADC_INTEN_ADCMPINTEN0_SHIFT (3U)
701/*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0.
702 * 0b00..Disabled.
703 * 0b01..Outside threshold.
704 * 0b10..Crossing threshold.
705 * 0b11..Reserved
706 */
707#define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)
708#define ADC_INTEN_ADCMPINTEN1_MASK (0x60U)
709#define ADC_INTEN_ADCMPINTEN1_SHIFT (5U)
710/*! ADCMPINTEN1 - Channel 1 threshold comparison interrupt enable.
711 * 0b00..Disabled.
712 * 0b01..Outside threshold.
713 * 0b10..Crossing threshold.
714 * 0b11..Reserved
715 */
716#define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)
717#define ADC_INTEN_ADCMPINTEN2_MASK (0x180U)
718#define ADC_INTEN_ADCMPINTEN2_SHIFT (7U)
719/*! ADCMPINTEN2 - Channel 2 threshold comparison interrupt enable.
720 * 0b00..Disabled.
721 * 0b01..Outside threshold.
722 * 0b10..Crossing threshold.
723 * 0b11..Reserved
724 */
725#define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)
726#define ADC_INTEN_ADCMPINTEN3_MASK (0x600U)
727#define ADC_INTEN_ADCMPINTEN3_SHIFT (9U)
728/*! ADCMPINTEN3 - Channel 3 threshold comparison interrupt enable.
729 * 0b00..Disabled.
730 * 0b01..Outside threshold.
731 * 0b10..Crossing threshold.
732 * 0b11..Reserved
733 */
734#define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)
735#define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U)
736#define ADC_INTEN_ADCMPINTEN4_SHIFT (11U)
737/*! ADCMPINTEN4 - Channel 4 threshold comparison interrupt enable.
738 * 0b00..Disabled.
739 * 0b01..Outside threshold.
740 * 0b10..Crossing threshold.
741 * 0b11..Reserved
742 */
743#define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)
744#define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U)
745#define ADC_INTEN_ADCMPINTEN5_SHIFT (13U)
746/*! ADCMPINTEN5 - Channel 5 threshold comparison interrupt enable.
747 * 0b00..Disabled.
748 * 0b01..Outside threshold.
749 * 0b10..Crossing threshold.
750 * 0b11..Reserved
751 */
752#define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)
753#define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U)
754#define ADC_INTEN_ADCMPINTEN6_SHIFT (15U)
755/*! ADCMPINTEN6 - Channel 6 threshold comparison interrupt enable.
756 * 0b00..Disabled.
757 * 0b01..Outside threshold.
758 * 0b10..Crossing threshold.
759 * 0b11..Reserved
760 */
761#define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)
762#define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U)
763#define ADC_INTEN_ADCMPINTEN7_SHIFT (17U)
764/*! ADCMPINTEN7 - Channel 7 threshold comparison interrupt enable.
765 * 0b00..Disabled.
766 * 0b01..Outside threshold.
767 * 0b10..Crossing threshold.
768 * 0b11..Reserved
769 */
770#define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)
771#define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U)
772#define ADC_INTEN_ADCMPINTEN8_SHIFT (19U)
773/*! ADCMPINTEN8 - Channel 8 threshold comparison interrupt enable.
774 * 0b00..Disabled.
775 * 0b01..Outside threshold.
776 * 0b10..Crossing threshold.
777 * 0b11..Reserved
778 */
779#define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)
780#define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U)
781#define ADC_INTEN_ADCMPINTEN9_SHIFT (21U)
782/*! ADCMPINTEN9 - Channel 9 threshold comparison interrupt enable.
783 * 0b00..Disabled.
784 * 0b01..Outside threshold.
785 * 0b10..Crossing threshold.
786 * 0b11..Reserved
787 */
788#define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)
789#define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U)
790#define ADC_INTEN_ADCMPINTEN10_SHIFT (23U)
791/*! ADCMPINTEN10 - Channel 10 threshold comparison interrupt enable.
792 * 0b00..Disabled.
793 * 0b01..Outside threshold.
794 * 0b10..Crossing threshold.
795 * 0b11..Reserved
796 */
797#define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)
798#define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U)
799#define ADC_INTEN_ADCMPINTEN11_SHIFT (25U)
800/*! ADCMPINTEN11 - Channel 11 threshold comparison interrupt enable.
801 * 0b00..Disabled.
802 * 0b01..Outside threshold.
803 * 0b10..Crossing threshold.
804 * 0b11..Reserved
805 */
806#define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)
807/*! @} */
808
809/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */
810/*! @{ */
811#define ADC_FLAGS_THCMP0_MASK (0x1U)
812#define ADC_FLAGS_THCMP0_SHIFT (0U)
813/*! THCMP0 - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or
814 * a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by
815 * writing a 1.
816 */
817#define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)
818#define ADC_FLAGS_THCMP1_MASK (0x2U)
819#define ADC_FLAGS_THCMP1_SHIFT (1U)
820/*! THCMP1 - Threshold comparison event on Channel 1. See description for channel 0.
821 */
822#define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)
823#define ADC_FLAGS_THCMP2_MASK (0x4U)
824#define ADC_FLAGS_THCMP2_SHIFT (2U)
825/*! THCMP2 - Threshold comparison event on Channel 2. See description for channel 0.
826 */
827#define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)
828#define ADC_FLAGS_THCMP3_MASK (0x8U)
829#define ADC_FLAGS_THCMP3_SHIFT (3U)
830/*! THCMP3 - Threshold comparison event on Channel 3. See description for channel 0.
831 */
832#define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)
833#define ADC_FLAGS_THCMP4_MASK (0x10U)
834#define ADC_FLAGS_THCMP4_SHIFT (4U)
835/*! THCMP4 - Threshold comparison event on Channel 4. See description for channel 0.
836 */
837#define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)
838#define ADC_FLAGS_THCMP5_MASK (0x20U)
839#define ADC_FLAGS_THCMP5_SHIFT (5U)
840/*! THCMP5 - Threshold comparison event on Channel 5. See description for channel 0.
841 */
842#define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)
843#define ADC_FLAGS_THCMP6_MASK (0x40U)
844#define ADC_FLAGS_THCMP6_SHIFT (6U)
845/*! THCMP6 - Threshold comparison event on Channel 6. See description for channel 0.
846 */
847#define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)
848#define ADC_FLAGS_THCMP7_MASK (0x80U)
849#define ADC_FLAGS_THCMP7_SHIFT (7U)
850/*! THCMP7 - Threshold comparison event on Channel 7. See description for channel 0.
851 */
852#define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)
853#define ADC_FLAGS_THCMP8_MASK (0x100U)
854#define ADC_FLAGS_THCMP8_SHIFT (8U)
855/*! THCMP8 - Threshold comparison event on Channel 8. See description for channel 0.
856 */
857#define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)
858#define ADC_FLAGS_THCMP9_MASK (0x200U)
859#define ADC_FLAGS_THCMP9_SHIFT (9U)
860/*! THCMP9 - Threshold comparison event on Channel 9. See description for channel 0.
861 */
862#define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)
863#define ADC_FLAGS_THCMP10_MASK (0x400U)
864#define ADC_FLAGS_THCMP10_SHIFT (10U)
865/*! THCMP10 - Threshold comparison event on Channel 10. See description for channel 0.
866 */
867#define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)
868#define ADC_FLAGS_THCMP11_MASK (0x800U)
869#define ADC_FLAGS_THCMP11_SHIFT (11U)
870/*! THCMP11 - Threshold comparison event on Channel 11. See description for channel 0.
871 */
872#define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)
873#define ADC_FLAGS_OVERRUN0_MASK (0x1000U)
874#define ADC_FLAGS_OVERRUN0_SHIFT (12U)
875/*! OVERRUN0 - Mirrors the OVERRRUN status flag from the result register for ADC channel 0
876 */
877#define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)
878#define ADC_FLAGS_OVERRUN1_MASK (0x2000U)
879#define ADC_FLAGS_OVERRUN1_SHIFT (13U)
880/*! OVERRUN1 - Mirrors the OVERRRUN status flag from the result register for ADC channel 1
881 */
882#define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)
883#define ADC_FLAGS_OVERRUN2_MASK (0x4000U)
884#define ADC_FLAGS_OVERRUN2_SHIFT (14U)
885/*! OVERRUN2 - Mirrors the OVERRRUN status flag from the result register for ADC channel 2
886 */
887#define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)
888#define ADC_FLAGS_OVERRUN3_MASK (0x8000U)
889#define ADC_FLAGS_OVERRUN3_SHIFT (15U)
890/*! OVERRUN3 - Mirrors the OVERRRUN status flag from the result register for ADC channel 3
891 */
892#define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)
893#define ADC_FLAGS_OVERRUN4_MASK (0x10000U)
894#define ADC_FLAGS_OVERRUN4_SHIFT (16U)
895/*! OVERRUN4 - Mirrors the OVERRRUN status flag from the result register for ADC channel 4
896 */
897#define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)
898#define ADC_FLAGS_OVERRUN5_MASK (0x20000U)
899#define ADC_FLAGS_OVERRUN5_SHIFT (17U)
900/*! OVERRUN5 - Mirrors the OVERRRUN status flag from the result register for ADC channel 5
901 */
902#define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)
903#define ADC_FLAGS_OVERRUN6_MASK (0x40000U)
904#define ADC_FLAGS_OVERRUN6_SHIFT (18U)
905/*! OVERRUN6 - Mirrors the OVERRRUN status flag from the result register for ADC channel 6
906 */
907#define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)
908#define ADC_FLAGS_OVERRUN7_MASK (0x80000U)
909#define ADC_FLAGS_OVERRUN7_SHIFT (19U)
910/*! OVERRUN7 - Mirrors the OVERRRUN status flag from the result register for ADC channel 7
911 */
912#define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)
913#define ADC_FLAGS_OVERRUN8_MASK (0x100000U)
914#define ADC_FLAGS_OVERRUN8_SHIFT (20U)
915/*! OVERRUN8 - Mirrors the OVERRRUN status flag from the result register for ADC channel 8
916 */
917#define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)
918#define ADC_FLAGS_OVERRUN9_MASK (0x200000U)
919#define ADC_FLAGS_OVERRUN9_SHIFT (21U)
920/*! OVERRUN9 - Mirrors the OVERRRUN status flag from the result register for ADC channel 9
921 */
922#define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)
923#define ADC_FLAGS_OVERRUN10_MASK (0x400000U)
924#define ADC_FLAGS_OVERRUN10_SHIFT (22U)
925/*! OVERRUN10 - Mirrors the OVERRRUN status flag from the result register for ADC channel 10
926 */
927#define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)
928#define ADC_FLAGS_OVERRUN11_MASK (0x800000U)
929#define ADC_FLAGS_OVERRUN11_SHIFT (23U)
930/*! OVERRUN11 - Mirrors the OVERRRUN status flag from the result register for ADC channel 11
931 */
932#define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)
933#define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U)
934#define ADC_FLAGS_SEQA_OVR_SHIFT (24U)
935/*! SEQA_OVR - Mirrors the global OVERRUN status flag in the SEQA_GDAT register
936 */
937#define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)
938#define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U)
939#define ADC_FLAGS_SEQB_OVR_SHIFT (25U)
940/*! SEQB_OVR - Mirrors the global OVERRUN status flag in the SEQB_GDAT register
941 */
942#define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)
943#define ADC_FLAGS_SEQA_INT_MASK (0x10000000U)
944#define ADC_FLAGS_SEQA_INT_SHIFT (28U)
945/*! SEQA_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0,
946 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which
947 * is set at the end of every ADC conversion performed as part of sequence A. It will be cleared
948 * automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register
949 * is 1, this flag will be set upon completion of an entire A sequence. In this case it must be
950 * cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN
951 * register.
952 */
953#define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)
954#define ADC_FLAGS_SEQB_INT_MASK (0x20000000U)
955#define ADC_FLAGS_SEQB_INT_SHIFT (29U)
956/*! SEQB_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0,
957 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which
958 * is set at the end of every ADC conversion performed as part of sequence B. It will be cleared
959 * automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register
960 * is 1, this flag will be set upon completion of an entire B sequence. In this case it must be
961 * cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN
962 * register.
963 */
964#define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)
965#define ADC_FLAGS_THCMP_INT_MASK (0x40000000U)
966#define ADC_FLAGS_THCMP_INT_SHIFT (30U)
967/*! THCMP_INT - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in
968 * the lower bits of this register are set to 1 (due to an enabled out-of-range or
969 * threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be
970 * individually enabled in the INTEN register to cause this interrupt. This bit will be cleared
971 * when all of the individual threshold flags are cleared via writing 1s to those bits.
972 */
973#define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)
974#define ADC_FLAGS_OVR_INT_MASK (0x80000000U)
975#define ADC_FLAGS_OVR_INT_SHIFT (31U)
976/*! OVR_INT - Overrun Interrupt flag. Any overrun bit in any of the individual channel data
977 * registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers
978 * is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this
979 * interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all
980 * of the individual overrun bits have been cleared via reading the corresponding data registers.
981 */
982#define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)
983/*! @} */
984
985/*! @name TRM - ADC Startup register. */
986/*! @{ */
987#define ADC_TRM_VRANGE_MASK (0x20U)
988#define ADC_TRM_VRANGE_SHIFT (5U)
989/*! VRANGE - 2.4V to 3.6V Vdd range: This bit MUST be set to '1' if operation below 2.7V is to be
990 * used. Failure to set this bit will result in invalid ADC results. Note: This bit will not be
991 * spec'd on parts that do not support operation below 2.7V
992 * 0b0..High voltage
993 * 0b1..Low voltage
994 */
995#define ADC_TRM_VRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_TRM_VRANGE_SHIFT)) & ADC_TRM_VRANGE_MASK)
996/*! @} */
997
998
999/*!
1000 * @}
1001 */ /* end of group ADC_Register_Masks */
1002
1003
1004/* ADC - Peripheral instance base addresses */
1005/** Peripheral ADC0 base address */
1006#define ADC0_BASE (0x4001C000u)
1007/** Peripheral ADC0 base pointer */
1008#define ADC0 ((ADC_Type *)ADC0_BASE)
1009/** Array initializer of ADC peripheral base addresses */
1010#define ADC_BASE_ADDRS { ADC0_BASE }
1011/** Array initializer of ADC peripheral base pointers */
1012#define ADC_BASE_PTRS { ADC0 }
1013/** Interrupt vectors for the ADC peripheral type */
1014#define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }
1015#define ADC_THCMP_IRQS { ADC0_THCMP_IRQn }
1016
1017/*!
1018 * @}
1019 */ /* end of group ADC_Peripheral_Access_Layer */
1020
1021
1022/* ----------------------------------------------------------------------------
1023 -- CRC Peripheral Access Layer
1024 ---------------------------------------------------------------------------- */
1025
1026/*!
1027 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
1028 * @{
1029 */
1030
1031/** CRC - Register Layout Typedef */
1032typedef struct {
1033 __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */
1034 __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */
1035 union { /* offset: 0x8 */
1036 __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */
1037 __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
1038 };
1039} CRC_Type;
1040
1041/* ----------------------------------------------------------------------------
1042 -- CRC Register Masks
1043 ---------------------------------------------------------------------------- */
1044
1045/*!
1046 * @addtogroup CRC_Register_Masks CRC Register Masks
1047 * @{
1048 */
1049
1050/*! @name MODE - CRC mode register */
1051/*! @{ */
1052#define CRC_MODE_CRC_POLY_MASK (0x3U)
1053#define CRC_MODE_CRC_POLY_SHIFT (0U)
1054/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial
1055 */
1056#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
1057#define CRC_MODE_BIT_RVS_WR_MASK (0x4U)
1058#define CRC_MODE_BIT_RVS_WR_SHIFT (2U)
1059/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte)
1060 */
1061#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
1062#define CRC_MODE_CMPL_WR_MASK (0x8U)
1063#define CRC_MODE_CMPL_WR_SHIFT (3U)
1064/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA
1065 */
1066#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
1067#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)
1068#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)
1069/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM
1070 */
1071#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
1072#define CRC_MODE_CMPL_SUM_MASK (0x20U)
1073#define CRC_MODE_CMPL_SUM_SHIFT (5U)
1074/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM
1075 */
1076#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
1077/*! @} */
1078
1079/*! @name SEED - CRC seed register */
1080/*! @{ */
1081#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)
1082#define CRC_SEED_CRC_SEED_SHIFT (0U)
1083/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with
1084 * selected bit order and 1's complement pre-processes. A write access to this register will
1085 * overrule the CRC calculation in progresses.
1086 */
1087#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
1088/*! @} */
1089
1090/*! @name SUM - CRC checksum register */
1091/*! @{ */
1092#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)
1093#define CRC_SUM_CRC_SUM_SHIFT (0U)
1094/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes.
1095 */
1096#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
1097/*! @} */
1098
1099/*! @name WR_DATA - CRC data register */
1100/*! @{ */
1101#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)
1102#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)
1103/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with
1104 * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and
1105 * accept back-to-back transactions.
1106 */
1107#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
1108/*! @} */
1109
1110
1111/*!
1112 * @}
1113 */ /* end of group CRC_Register_Masks */
1114
1115
1116/* CRC - Peripheral instance base addresses */
1117/** Peripheral CRC base address */
1118#define CRC_BASE (0x50000000u)
1119/** Peripheral CRC base pointer */
1120#define CRC ((CRC_Type *)CRC_BASE)
1121/** Array initializer of CRC peripheral base addresses */
1122#define CRC_BASE_ADDRS { CRC_BASE }
1123/** Array initializer of CRC peripheral base pointers */
1124#define CRC_BASE_PTRS { CRC }
1125
1126/*!
1127 * @}
1128 */ /* end of group CRC_Peripheral_Access_Layer */
1129
1130
1131/* ----------------------------------------------------------------------------
1132 -- DMA Peripheral Access Layer
1133 ---------------------------------------------------------------------------- */
1134
1135/*!
1136 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
1137 * @{
1138 */
1139
1140/** DMA - Register Layout Typedef */
1141typedef struct {
1142 __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */
1143 __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */
1144 __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */
1145 uint8_t RESERVED_0[20];
1146 struct { /* offset: 0x20, array step: 0x5C */
1147 __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
1148 uint8_t RESERVED_0[4];
1149 __IO uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
1150 uint8_t RESERVED_1[4];
1151 __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
1152 uint8_t RESERVED_2[4];
1153 __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
1154 uint8_t RESERVED_3[4];
1155 __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
1156 uint8_t RESERVED_4[4];
1157 __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
1158 uint8_t RESERVED_5[4];
1159 __IO uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
1160 uint8_t RESERVED_6[4];
1161 __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
1162 uint8_t RESERVED_7[4];
1163 __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
1164 uint8_t RESERVED_8[4];
1165 __IO uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
1166 uint8_t RESERVED_9[4];
1167 __IO uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
1168 uint8_t RESERVED_10[4];
1169 __IO uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
1170 } COMMON[1];
1171 uint8_t RESERVED_1[900];
1172 struct { /* offset: 0x400, array step: 0x10 */
1173 __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
1174 __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
1175 __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
1176 uint8_t RESERVED_0[4];
1177 } CHANNEL[18];
1178} DMA_Type;
1179
1180/* ----------------------------------------------------------------------------
1181 -- DMA Register Masks
1182 ---------------------------------------------------------------------------- */
1183
1184/*!
1185 * @addtogroup DMA_Register_Masks DMA Register Masks
1186 * @{
1187 */
1188
1189/*! @name CTRL - DMA control. */
1190/*! @{ */
1191#define DMA_CTRL_ENABLE_MASK (0x1U)
1192#define DMA_CTRL_ENABLE_SHIFT (0U)
1193/*! ENABLE - DMA controller master enable.
1194 * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when
1195 * disabled, but does not prevent re-triggering when the DMA controller is re-enabled.
1196 * 0b1..Enabled. The DMA controller is enabled.
1197 */
1198#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
1199/*! @} */
1200
1201/*! @name INTSTAT - Interrupt status. */
1202/*! @{ */
1203#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U)
1204#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U)
1205/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending.
1206 * 0b0..Not pending. No enabled interrupts are pending.
1207 * 0b1..Pending. At least one enabled interrupt is pending.
1208 */
1209#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
1210#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U)
1211#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U)
1212/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending.
1213 * 0b0..Not pending. No error interrupts are pending.
1214 * 0b1..Pending. At least one error interrupt is pending.
1215 */
1216#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
1217/*! @} */
1218
1219/*! @name SRAMBASE - SRAM address of the channel configuration table. */
1220/*! @{ */
1221#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U)
1222#define DMA_SRAMBASE_OFFSET_SHIFT (9U)
1223/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the
1224 * table must begin on a 512 byte boundary.
1225 */
1226#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
1227/*! @} */
1228
1229/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
1230/*! @{ */
1231#define DMA_COMMON_ENABLESET_ENA_MASK (0x3FFFFU)
1232#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U)
1233/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits =
1234 * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled.
1235 */
1236#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
1237/*! @} */
1238
1239/* The count of DMA_COMMON_ENABLESET */
1240#define DMA_COMMON_ENABLESET_COUNT (1U)
1241
1242/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
1243/*! @{ */
1244#define DMA_COMMON_ENABLECLR_CLR_MASK (0x3FFFFU)
1245#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U)
1246/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears
1247 * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits
1248 * are reserved.
1249 */
1250#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
1251/*! @} */
1252
1253/* The count of DMA_COMMON_ENABLECLR */
1254#define DMA_COMMON_ENABLECLR_COUNT (1U)
1255
1256/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
1257/*! @{ */
1258#define DMA_COMMON_ACTIVE_ACT_MASK (0x3FFFFU)
1259#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U)
1260/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
1261 * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active.
1262 */
1263#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
1264/*! @} */
1265
1266/* The count of DMA_COMMON_ACTIVE */
1267#define DMA_COMMON_ACTIVE_COUNT (1U)
1268
1269/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
1270/*! @{ */
1271#define DMA_COMMON_BUSY_BSY_MASK (0x3FFFFU)
1272#define DMA_COMMON_BUSY_BSY_SHIFT (0U)
1273/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits =
1274 * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy.
1275 */
1276#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
1277/*! @} */
1278
1279/* The count of DMA_COMMON_BUSY */
1280#define DMA_COMMON_BUSY_COUNT (1U)
1281
1282/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
1283/*! @{ */
1284#define DMA_COMMON_ERRINT_ERR_MASK (0x3FFFFU)
1285#define DMA_COMMON_ERRINT_ERR_SHIFT (0U)
1286/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of
1287 * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is
1288 * not active. 1 = error interrupt is active.
1289 */
1290#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
1291/*! @} */
1292
1293/* The count of DMA_COMMON_ERRINT */
1294#define DMA_COMMON_ERRINT_COUNT (1U)
1295
1296/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
1297/*! @{ */
1298#define DMA_COMMON_INTENSET_INTEN_MASK (0x3FFFFU)
1299#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U)
1300/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The
1301 * number of bits = number of DMA channels in this device. Other bits are reserved. 0 =
1302 * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled.
1303 */
1304#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
1305/*! @} */
1306
1307/* The count of DMA_COMMON_INTENSET */
1308#define DMA_COMMON_INTENSET_COUNT (1U)
1309
1310/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
1311/*! @{ */
1312#define DMA_COMMON_INTENCLR_CLR_MASK (0x3FFFFU)
1313#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U)
1314/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n
1315 * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are
1316 * reserved.
1317 */
1318#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
1319/*! @} */
1320
1321/* The count of DMA_COMMON_INTENCLR */
1322#define DMA_COMMON_INTENCLR_COUNT (1U)
1323
1324/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
1325/*! @{ */
1326#define DMA_COMMON_INTA_IA_MASK (0x3FFFFU)
1327#define DMA_COMMON_INTA_IA_SHIFT (0U)
1328/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of
1329 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
1330 * interrupt A is not active. 1 = the DMA channel interrupt A is active.
1331 */
1332#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
1333/*! @} */
1334
1335/* The count of DMA_COMMON_INTA */
1336#define DMA_COMMON_INTA_COUNT (1U)
1337
1338/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
1339/*! @{ */
1340#define DMA_COMMON_INTB_IB_MASK (0x3FFFFU)
1341#define DMA_COMMON_INTB_IB_SHIFT (0U)
1342/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of
1343 * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel
1344 * interrupt B is not active. 1 = the DMA channel interrupt B is active.
1345 */
1346#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
1347/*! @} */
1348
1349/* The count of DMA_COMMON_INTB */
1350#define DMA_COMMON_INTB_COUNT (1U)
1351
1352/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
1353/*! @{ */
1354#define DMA_COMMON_SETVALID_SV_MASK (0x3FFFFU)
1355#define DMA_COMMON_SETVALID_SV_SHIFT (0U)
1356/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits
1357 * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the
1358 * VALIDPENDING control bit for DMA channel n
1359 */
1360#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
1361/*! @} */
1362
1363/* The count of DMA_COMMON_SETVALID */
1364#define DMA_COMMON_SETVALID_COUNT (1U)
1365
1366/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
1367/*! @{ */
1368#define DMA_COMMON_SETTRIG_TRIG_MASK (0x3FFFFU)
1369#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U)
1370/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number
1371 * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 =
1372 * sets the TRIG bit for DMA channel n.
1373 */
1374#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
1375/*! @} */
1376
1377/* The count of DMA_COMMON_SETTRIG */
1378#define DMA_COMMON_SETTRIG_COUNT (1U)
1379
1380/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
1381/*! @{ */
1382#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0x3FFFFU)
1383#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U)
1384/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect.
1385 * 1 = aborts DMA operations on channel n.
1386 */
1387#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
1388/*! @} */
1389
1390/* The count of DMA_COMMON_ABORT */
1391#define DMA_COMMON_ABORT_COUNT (1U)
1392
1393/*! @name CHANNEL_CFG - Configuration register for DMA channel . */
1394/*! @{ */
1395#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U)
1396#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U)
1397/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory
1398 * move, any peripheral DMA request associated with that channel can be disabled to prevent any
1399 * interaction between the peripheral and the DMA controller.
1400 * 0b0..Disabled. Peripheral DMA requests are disabled.
1401 * 0b1..Enabled. Peripheral DMA requests are enabled.
1402 */
1403#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
1404#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U)
1405#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U)
1406/*! HWTRIGEN - Hardware Triggering Enable for this channel.
1407 * 0b0..Disabled. Hardware triggering is not used.
1408 * 0b1..Enabled. Use hardware triggering.
1409 */
1410#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
1411#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U)
1412#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U)
1413/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel.
1414 * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.
1415 * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.
1416 */
1417#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
1418#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U)
1419#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U)
1420/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered.
1421 * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.
1422 * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER =
1423 * 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the
1424 * trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger
1425 * is, again, asserted. However, the transfer will not be paused until any remaining transfers within the
1426 * current BURSTPOWER length are completed.
1427 */
1428#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
1429#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U)
1430#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U)
1431/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.
1432 * 0b0..Single transfer. Hardware trigger causes a single transfer.
1433 * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a
1434 * burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a
1435 * hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is
1436 * complete.
1437 */
1438#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
1439#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U)
1440#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U)
1441/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when
1442 * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register).
1443 * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many
1444 * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that
1445 * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000:
1446 * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size =
1447 * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The
1448 * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even
1449 * multiple of the burst size.
1450 */
1451#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
1452#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U)
1453#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U)
1454/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is
1455 * 'wrapped', meaning that the source address range for each burst will be the same. As an example, this
1456 * could be used to read several sequential registers from a peripheral for each DMA burst,
1457 * reading the same registers again for each burst.
1458 * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel.
1459 * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel.
1460 */
1461#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
1462#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U)
1463#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U)
1464/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is
1465 * 'wrapped', meaning that the destination address range for each burst will be the same. As an
1466 * example, this could be used to write several sequential registers to a peripheral for each DMA
1467 * burst, writing the same registers again for each burst.
1468 * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel.
1469 * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel.
1470 */
1471#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
1472#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U)
1473#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U)
1474/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority
1475 * levels are supported: 0x0 = highest priority. 0x7 = lowest priority.
1476 */
1477#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
1478/*! @} */
1479
1480/* The count of DMA_CHANNEL_CFG */
1481#define DMA_CHANNEL_CFG_COUNT (18U)
1482
1483/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
1484/*! @{ */
1485#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U)
1486#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U)
1487/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the
1488 * corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.
1489 * 0b0..No effect. No effect on DMA operation.
1490 * 0b1..Valid pending.
1491 */
1492#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
1493#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U)
1494#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U)
1495/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is
1496 * cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.
1497 * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.
1498 * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
1499 */
1500#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
1501/*! @} */
1502
1503/* The count of DMA_CHANNEL_CTLSTAT */
1504#define DMA_CHANNEL_CTLSTAT_COUNT (18U)
1505
1506/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
1507/*! @{ */
1508#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U)
1509#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U)
1510/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor
1511 * is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
1512 * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.
1513 * 0b1..Valid. The current channel descriptor is considered valid.
1514 */
1515#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
1516#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U)
1517#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U)
1518/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current
1519 * descriptor is exhausted. Reloading allows ping-pong and linked transfers.
1520 * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.
1521 * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted.
1522 */
1523#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
1524#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U)
1525#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U)
1526/*! SWTRIG - Software Trigger.
1527 * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by
1528 * the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.
1529 * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not
1530 * be used with level triggering when TRIGBURST = 0.
1531 */
1532#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
1533#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U)
1534#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U)
1535/*! CLRTRIG - Clear Trigger.
1536 * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.
1537 * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted
1538 */
1539#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
1540#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U)
1541#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U)
1542/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between
1543 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
1544 * convention, interrupt A may be used when only one interrupt flag is needed.
1545 * 0b0..No effect.
1546 * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted.
1547 */
1548#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
1549#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U)
1550#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U)
1551/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between
1552 * interrupt A and B. They can be used by software to assist with more complex descriptor usage. By
1553 * convention, interrupt A may be used when only one interrupt flag is needed.
1554 * 0b0..No effect.
1555 * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted.
1556 */
1557#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
1558#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U)
1559#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U)
1560/*! WIDTH - Transfer width used for this DMA channel.
1561 * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).
1562 * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).
1563 * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).
1564 * 0b11..Reserved. Reserved setting, do not use.
1565 */
1566#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
1567#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U)
1568#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U)
1569/*! SRCINC - Determines whether the source address is incremented for each DMA transfer.
1570 * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.
1571 * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is
1572 * the usual case when the source is memory.
1573 * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.
1574 * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.
1575 */
1576#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
1577#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U)
1578#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U)
1579/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer.
1580 * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when
1581 * the destination is a peripheral device.
1582 * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer.
1583 * This is the usual case when the destination is memory.
1584 * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.
1585 * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.
1586 */
1587#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
1588#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U)
1589#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U)
1590/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes
1591 * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller
1592 * uses this bit field during transfer to count down. Hence, it cannot be used by software to read
1593 * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1
1594 * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of
1595 * 1,024 transfers will be performed.
1596 */
1597#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
1598/*! @} */
1599
1600/* The count of DMA_CHANNEL_XFERCFG */
1601#define DMA_CHANNEL_XFERCFG_COUNT (18U)
1602
1603
1604/*!
1605 * @}
1606 */ /* end of group DMA_Register_Masks */
1607
1608
1609/* DMA - Peripheral instance base addresses */
1610/** Peripheral DMA0 base address */
1611#define DMA0_BASE (0x50008000u)
1612/** Peripheral DMA0 base pointer */
1613#define DMA0 ((DMA_Type *)DMA0_BASE)
1614/** Array initializer of DMA peripheral base addresses */
1615#define DMA_BASE_ADDRS { DMA0_BASE }
1616/** Array initializer of DMA peripheral base pointers */
1617#define DMA_BASE_PTRS { DMA0 }
1618/** Interrupt vectors for the DMA peripheral type */
1619#define DMA_IRQS { DMA0_IRQn }
1620
1621/*!
1622 * @}
1623 */ /* end of group DMA_Peripheral_Access_Layer */
1624
1625
1626/* ----------------------------------------------------------------------------
1627 -- FLASH_CTRL Peripheral Access Layer
1628 ---------------------------------------------------------------------------- */
1629
1630/*!
1631 * @addtogroup FLASH_CTRL_Peripheral_Access_Layer FLASH_CTRL Peripheral Access Layer
1632 * @{
1633 */
1634
1635/** FLASH_CTRL - Register Layout Typedef */
1636typedef struct {
1637 uint8_t RESERVED_0[16];
1638 __IO uint32_t FLASHCFG; /**< Flash configuration register, offset: 0x10 */
1639 uint8_t RESERVED_1[12];
1640 __IO uint32_t FMSSTART; /**< Flash signature start address register, offset: 0x20 */
1641 __IO uint32_t FMSSTOP; /**< Flash signaure stop address register, offset: 0x24 */
1642 uint8_t RESERVED_2[4];
1643 __I uint32_t FMSW0; /**< Flash signature generation result register returns the flash signature produced by the embedded signature generator.., offset: 0x2C */
1644 uint8_t RESERVED_3[4016];
1645 __I uint32_t FMSTAT; /**< Flash signature generation status bit, offset: 0xFE0 */
1646 uint8_t RESERVED_4[4];
1647 __O uint32_t FMSTATCLR; /**< Clear FLASH signature generation status bit, offset: 0xFE8 */
1648} FLASH_CTRL_Type;
1649
1650/* ----------------------------------------------------------------------------
1651 -- FLASH_CTRL Register Masks
1652 ---------------------------------------------------------------------------- */
1653
1654/*!
1655 * @addtogroup FLASH_CTRL_Register_Masks FLASH_CTRL Register Masks
1656 * @{
1657 */
1658
1659/*! @name FLASHCFG - Flash configuration register */
1660/*! @{ */
1661#define FLASH_CTRL_FLASHCFG_FLASHTIM_MASK (0x3U)
1662#define FLASH_CTRL_FLASHCFG_FLASHTIM_SHIFT (0U)
1663/*! FLASHTIM - Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.
1664 * 0b00..1 system clock flash access time.
1665 * 0b01..2 system clock flash access time.
1666 * 0b10-0b11..Reserved.
1667 */
1668#define FLASH_CTRL_FLASHCFG_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FLASHCFG_FLASHTIM_SHIFT)) & FLASH_CTRL_FLASHCFG_FLASHTIM_MASK)
1669/*! @} */
1670
1671/*! @name FMSSTART - Flash signature start address register */
1672/*! @{ */
1673#define FLASH_CTRL_FMSSTART_START_MASK (0x1FFFFU)
1674#define FLASH_CTRL_FMSSTART_START_SHIFT (0U)
1675/*! START - Signature generation start address (corresponds to AHB byte address bits[18:2]).
1676 */
1677#define FLASH_CTRL_FMSSTART_START(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSSTART_START_SHIFT)) & FLASH_CTRL_FMSSTART_START_MASK)
1678/*! @} */
1679
1680/*! @name FMSSTOP - Flash signaure stop address register */
1681/*! @{ */
1682#define FLASH_CTRL_FMSSTOP_STOPA_MASK (0x1FFFFU)
1683#define FLASH_CTRL_FMSSTOP_STOPA_SHIFT (0U)
1684/*! STOPA - Stop address for signature generation (the word specified by STOP is included in the
1685 * address range). The address is in units of memory words, not bytes.
1686 */
1687#define FLASH_CTRL_FMSSTOP_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSSTOP_STOPA_SHIFT)) & FLASH_CTRL_FMSSTOP_STOPA_MASK)
1688#define FLASH_CTRL_FMSSTOP_STRTBIST_MASK (0x80000000U)
1689#define FLASH_CTRL_FMSSTOP_STRTBIST_SHIFT (31U)
1690/*! STRTBIST - When this bit is written to 1, signature generation starts. At the end of signature
1691 * generation, this bit is automatically cleared.
1692 */
1693#define FLASH_CTRL_FMSSTOP_STRTBIST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSSTOP_STRTBIST_SHIFT)) & FLASH_CTRL_FMSSTOP_STRTBIST_MASK)
1694/*! @} */
1695
1696/*! @name FMSW0 - Flash signature generation result register returns the flash signature produced by the embedded signature generator.. */
1697/*! @{ */
1698#define FLASH_CTRL_FMSW0_SIG_MASK (0xFFFFFFFFU)
1699#define FLASH_CTRL_FMSW0_SIG_SHIFT (0U)
1700/*! SIG - 32-bit signature.
1701 */
1702#define FLASH_CTRL_FMSW0_SIG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSW0_SIG_SHIFT)) & FLASH_CTRL_FMSW0_SIG_MASK)
1703/*! @} */
1704
1705/*! @name FMSTAT - Flash signature generation status bit */
1706/*! @{ */
1707#define FLASH_CTRL_FMSTAT_SIGNATURE_DONE_MASK (0x2U)
1708#define FLASH_CTRL_FMSTAT_SIGNATURE_DONE_SHIFT (1U)
1709/*! SIGNATURE_DONE - This status bit is set at the end of signature computation
1710 */
1711#define FLASH_CTRL_FMSTAT_SIGNATURE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSTAT_SIGNATURE_DONE_SHIFT)) & FLASH_CTRL_FMSTAT_SIGNATURE_DONE_MASK)
1712/*! @} */
1713
1714/*! @name FMSTATCLR - Clear FLASH signature generation status bit */
1715/*! @{ */
1716#define FLASH_CTRL_FMSTATCLR_SIGNATURE_DONE_CLR_MASK (0x2U)
1717#define FLASH_CTRL_FMSTATCLR_SIGNATURE_DONE_CLR_SHIFT (1U)
1718/*! SIGNATURE_DONE_CLR - When the bit is written to 1, the SIGNATURE_DONE bit is cleared.
1719 */
1720#define FLASH_CTRL_FMSTATCLR_SIGNATURE_DONE_CLR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CTRL_FMSTATCLR_SIGNATURE_DONE_CLR_SHIFT)) & FLASH_CTRL_FMSTATCLR_SIGNATURE_DONE_CLR_MASK)
1721/*! @} */
1722
1723
1724/*!
1725 * @}
1726 */ /* end of group FLASH_CTRL_Register_Masks */
1727
1728
1729/* FLASH_CTRL - Peripheral instance base addresses */
1730/** Peripheral FLASH_CTRL base address */
1731#define FLASH_CTRL_BASE (0x40040000u)
1732/** Peripheral FLASH_CTRL base pointer */
1733#define FLASH_CTRL ((FLASH_CTRL_Type *)FLASH_CTRL_BASE)
1734/** Array initializer of FLASH_CTRL peripheral base addresses */
1735#define FLASH_CTRL_BASE_ADDRS { FLASH_CTRL_BASE }
1736/** Array initializer of FLASH_CTRL peripheral base pointers */
1737#define FLASH_CTRL_BASE_PTRS { FLASH_CTRL }
1738/** Interrupt vectors for the FLASH_CTRL peripheral type */
1739#define FLASH_CTRL_IRQS { FLASH_IRQn }
1740
1741/*!
1742 * @}
1743 */ /* end of group FLASH_CTRL_Peripheral_Access_Layer */
1744
1745
1746/* ----------------------------------------------------------------------------
1747 -- GPIO Peripheral Access Layer
1748 ---------------------------------------------------------------------------- */
1749
1750/*!
1751 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
1752 * @{
1753 */
1754
1755/** GPIO - Register Layout Typedef */
1756typedef struct {
1757 __IO uint8_t B[1][29]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x1D, index2*0x1 */
1758 uint8_t RESERVED_0[4067];
1759 __IO uint32_t W[1][29]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x74, index2*0x4 */
1760 uint8_t RESERVED_1[3980];
1761 __IO uint32_t DIR[1]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */
1762 uint8_t RESERVED_2[124];
1763 __IO uint32_t MASK[1]; /**< Mask register, array offset: 0x2080, array step: 0x4 */
1764 uint8_t RESERVED_3[124];
1765 __IO uint32_t PIN[1]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */
1766 uint8_t RESERVED_4[124];
1767 __IO uint32_t MPIN[1]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */
1768 uint8_t RESERVED_5[124];
1769 __IO uint32_t SET[1]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */
1770 uint8_t RESERVED_6[124];
1771 __O uint32_t CLR[1]; /**< Clear port, array offset: 0x2280, array step: 0x4 */
1772 uint8_t RESERVED_7[124];
1773 __O uint32_t NOT[1]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */
1774 uint8_t RESERVED_8[124];
1775 __O uint32_t DIRSET[1]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */
1776 uint8_t RESERVED_9[124];
1777 __O uint32_t DIRCLR[1]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */
1778 uint8_t RESERVED_10[124];
1779 __O uint32_t DIRNOT[1]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */
1780} GPIO_Type;
1781
1782/* ----------------------------------------------------------------------------
1783 -- GPIO Register Masks
1784 ---------------------------------------------------------------------------- */
1785
1786/*!
1787 * @addtogroup GPIO_Register_Masks GPIO Register Masks
1788 * @{
1789 */
1790
1791/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */
1792/*! @{ */
1793#define GPIO_B_PBYTE_MASK (0x1U)
1794#define GPIO_B_PBYTE_SHIFT (0U)
1795/*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function,
1796 * except that pins configured as analog I/O always read as 0. One register for each port pin.
1797 * Supported pins depends on the specific device and package. Write: loads the pin's output bit.
1798 * One register for each port pin. Supported pins depends on the specific device and package.
1799 */
1800#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)
1801/*! @} */
1802
1803/* The count of GPIO_B */
1804#define GPIO_B_COUNT (1U)
1805
1806/* The count of GPIO_B */
1807#define GPIO_B_COUNT2 (29U)
1808
1809/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */
1810/*! @{ */
1811#define GPIO_W_PWORD_MASK (0xFFFFFFFFU)
1812#define GPIO_W_PWORD_SHIFT (0U)
1813/*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is
1814 * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be
1815 * read. Writing any value other than 0 will set the output bit. One register for each port pin.
1816 * Supported pins depends on the specific device and package.
1817 */
1818#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)
1819/*! @} */
1820
1821/* The count of GPIO_W */
1822#define GPIO_W_COUNT (1U)
1823
1824/* The count of GPIO_W */
1825#define GPIO_W_COUNT2 (29U)
1826
1827/*! @name DIR - Direction registers */
1828/*! @{ */
1829#define GPIO_DIR_DIRP_MASK (0x1FFFFFFFU)
1830#define GPIO_DIR_DIRP_SHIFT (0U)
1831/*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
1832 * pins depends on the specific device and package. 0 = input. 1 = output.
1833 */
1834#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK)
1835/*! @} */
1836
1837/* The count of GPIO_DIR */
1838#define GPIO_DIR_COUNT (1U)
1839
1840/*! @name MASK - Mask register */
1841/*! @{ */
1842#define GPIO_MASK_MASKP_MASK (0x1FFFFFFFU)
1843#define GPIO_MASK_MASKP_SHIFT (0U)
1844/*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 =
1845 * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 =
1846 * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit
1847 * not affected.
1848 */
1849#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK)
1850/*! @} */
1851
1852/* The count of GPIO_MASK */
1853#define GPIO_MASK_COUNT (1U)
1854
1855/*! @name PIN - Port pin register */
1856/*! @{ */
1857#define GPIO_PIN_PORT_MASK (0x1FFFFFFFU)
1858#define GPIO_PIN_PORT_SHIFT (0U)
1859/*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported
1860 * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit.
1861 * 1 = Read: pin is high; write: set output bit.
1862 */
1863#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK)
1864/*! @} */
1865
1866/* The count of GPIO_PIN */
1867#define GPIO_PIN_COUNT (1U)
1868
1869/*! @name MPIN - Masked port register */
1870/*! @{ */
1871#define GPIO_MPIN_MPORTP_MASK (0x1FFFFFFFU)
1872#define GPIO_MPIN_MPORTP_SHIFT (0U)
1873/*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
1874 * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK
1875 * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1
1876 * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit
1877 * if the corresponding bit in the MASK register is 0.
1878 */
1879#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK)
1880/*! @} */
1881
1882/* The count of GPIO_MPIN */
1883#define GPIO_MPIN_COUNT (1U)
1884
1885/*! @name SET - Write: Set register for port Read: output bits for port */
1886/*! @{ */
1887#define GPIO_SET_SETP_MASK (0x1FFFFFFFU)
1888#define GPIO_SET_SETP_SHIFT (0U)
1889/*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
1890 * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output
1891 * bit; write: set output bit.
1892 */
1893#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
1894/*! @} */
1895
1896/* The count of GPIO_SET */
1897#define GPIO_SET_COUNT (1U)
1898
1899/*! @name CLR - Clear port */
1900/*! @{ */
1901#define GPIO_CLR_CLRP_MASK (0x1FFFFFFFU)
1902#define GPIO_CLR_CLRP_SHIFT (0U)
1903/*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
1904 * specific device and package. 0 = No operation. 1 = Clear output bit.
1905 */
1906#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK)
1907/*! @} */
1908
1909/* The count of GPIO_CLR */
1910#define GPIO_CLR_COUNT (1U)
1911
1912/*! @name NOT - Toggle port */
1913/*! @{ */
1914#define GPIO_NOT_NOTP_MASK (0x1FFFFFFFU)
1915#define GPIO_NOT_NOTP_SHIFT (0U)
1916/*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the
1917 * specific device and package. 0 = no operation. 1 = Toggle output bit.
1918 */
1919#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK)
1920/*! @} */
1921
1922/* The count of GPIO_NOT */
1923#define GPIO_NOT_COUNT (1U)
1924
1925/*! @name DIRSET - Set pin direction bits for port */
1926/*! @{ */
1927#define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU)
1928#define GPIO_DIRSET_DIRSETP_SHIFT (0U)
1929/*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
1930 * the specific device and package. 0 = No operation. 1 = Set direction bit.
1931 */
1932#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK)
1933/*! @} */
1934
1935/* The count of GPIO_DIRSET */
1936#define GPIO_DIRSET_COUNT (1U)
1937
1938/*! @name DIRCLR - Clear pin direction bits for port */
1939/*! @{ */
1940#define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU)
1941#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U)
1942/*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on
1943 * the specific device and package. 0 = No operation. 1 = Clear direction bit.
1944 */
1945#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK)
1946/*! @} */
1947
1948/* The count of GPIO_DIRCLR */
1949#define GPIO_DIRCLR_COUNT (1U)
1950
1951/*! @name DIRNOT - Toggle pin direction bits for port */
1952/*! @{ */
1953#define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU)
1954#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U)
1955/*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends
1956 * on the specific device and package. 0 = no operation. 1 = Toggle direction bit.
1957 */
1958#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)
1959/*! @} */
1960
1961/* The count of GPIO_DIRNOT */
1962#define GPIO_DIRNOT_COUNT (1U)
1963
1964
1965/*!
1966 * @}
1967 */ /* end of group GPIO_Register_Masks */
1968
1969
1970/* GPIO - Peripheral instance base addresses */
1971/** Peripheral GPIO base address */
1972#define GPIO_BASE (0xA0000000u)
1973/** Peripheral GPIO base pointer */
1974#define GPIO ((GPIO_Type *)GPIO_BASE)
1975/** Array initializer of GPIO peripheral base addresses */
1976#define GPIO_BASE_ADDRS { GPIO_BASE }
1977/** Array initializer of GPIO peripheral base pointers */
1978#define GPIO_BASE_PTRS { GPIO }
1979
1980/*!
1981 * @}
1982 */ /* end of group GPIO_Peripheral_Access_Layer */
1983
1984
1985/* ----------------------------------------------------------------------------
1986 -- I2C Peripheral Access Layer
1987 ---------------------------------------------------------------------------- */
1988
1989/*!
1990 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
1991 * @{
1992 */
1993
1994/** I2C - Register Layout Typedef */
1995typedef struct {
1996 __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x0 */
1997 __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x4 */
1998 __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x8 */
1999 __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0xC */
2000 __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x10 */
2001 __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x14 */
2002 __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x18 */
2003 uint8_t RESERVED_0[4];
2004 __IO uint32_t MSTCTL; /**< Master control register., offset: 0x20 */
2005 __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x24 */
2006 __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x28 */
2007 uint8_t RESERVED_1[20];
2008 __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x40 */
2009 __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x44 */
2010 __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x48, array step: 0x4 */
2011 __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x58 */
2012 uint8_t RESERVED_2[36];
2013 __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x80 */
2014} I2C_Type;
2015
2016/* ----------------------------------------------------------------------------
2017 -- I2C Register Masks
2018 ---------------------------------------------------------------------------- */
2019
2020/*!
2021 * @addtogroup I2C_Register_Masks I2C Register Masks
2022 * @{
2023 */
2024
2025/*! @name CFG - Configuration for shared functions. */
2026/*! @{ */
2027#define I2C_CFG_MSTEN_MASK (0x1U)
2028#define I2C_CFG_MSTEN_SHIFT (0U)
2029/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not
2030 * changed, but the Master function is internally reset.
2031 * 0b0..Disabled. The I2C Master function is disabled.
2032 * 0b1..Enabled. The I2C Master function is enabled.
2033 */
2034#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
2035#define I2C_CFG_SLVEN_MASK (0x2U)
2036#define I2C_CFG_SLVEN_SHIFT (1U)
2037/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not
2038 * changed, but the Slave function is internally reset.
2039 * 0b0..Disabled. The I2C slave function is disabled.
2040 * 0b1..Enabled. The I2C slave function is enabled.
2041 */
2042#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
2043#define I2C_CFG_MONEN_MASK (0x4U)
2044#define I2C_CFG_MONEN_SHIFT (2U)
2045/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not
2046 * changed, but the Monitor function is internally reset.
2047 * 0b0..Disabled. The I2C Monitor function is disabled.
2048 * 0b1..Enabled. The I2C Monitor function is enabled.
2049 */
2050#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
2051#define I2C_CFG_TIMEOUTEN_MASK (0x8U)
2052#define I2C_CFG_TIMEOUTEN_SHIFT (3U)
2053/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset.
2054 * 0b0..Disabled. Time-out function is disabled.
2055 * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause
2056 * interrupts if they are enabled. Typically, only one time-out will be used in a system.
2057 */
2058#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)
2059#define I2C_CFG_MONCLKSTR_MASK (0x10U)
2060#define I2C_CFG_MONCLKSTR_SHIFT (4U)
2061/*! MONCLKSTR - Monitor function Clock Stretching.
2062 * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able
2063 * to read data provided by the Monitor function before it is overwritten. This mode may be used when
2064 * non-invasive monitoring is critical.
2065 * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can
2066 * read all incoming data supplied by the Monitor function.
2067 */
2068#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)
2069/*! @} */
2070
2071/*! @name STAT - Status register for Master, Slave, and Monitor functions. */
2072/*! @{ */
2073#define I2C_STAT_MSTPENDING_MASK (0x1U)
2074#define I2C_STAT_MSTPENDING_SHIFT (0U)
2075/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on
2076 * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what
2077 * type of software service if any the master expects. This flag will cause an interrupt when set
2078 * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling
2079 * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle
2080 * state, and no communication is needed, mask this interrupt.
2081 * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.
2082 * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the
2083 * idle state, it is waiting to receive or transmit data or the NACK bit.
2084 */
2085#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)
2086#define I2C_STAT_MSTSTATE_MASK (0xEU)
2087#define I2C_STAT_MSTSTATE_SHIFT (1U)
2088/*! MSTSTATE - Master State code. The master state code reflects the master state when the
2089 * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field
2090 * indicates a specific required service for the Master function. All other values are reserved. See
2091 * Table 400 for details of state values and appropriate responses.
2092 * 0b000..Idle. The Master function is available to be used for a new transaction.
2093 * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.
2094 * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.
2095 * 0b011..NACK Address. Slave NACKed address.
2096 * 0b100..NACK Data. Slave NACKed transmitted data.
2097 */
2098#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)
2099#define I2C_STAT_MSTARBLOSS_MASK (0x10U)
2100#define I2C_STAT_MSTARBLOSS_SHIFT (4U)
2101/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to
2102 * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
2103 * 0b0..No Arbitration Loss has occurred.
2104 * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master
2105 * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing,
2106 * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.
2107 */
2108#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)
2109#define I2C_STAT_MSTSTSTPERR_MASK (0x40U)
2110#define I2C_STAT_MSTSTSTPERR_SHIFT (6U)
2111/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to
2112 * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.
2113 * 0b0..No Start/Stop Error has occurred.
2114 * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is
2115 * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an
2116 * idle state, no action is required. A request for a Start could be made, or software could attempt to insure
2117 * that the bus has not stalled.
2118 */
2119#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)
2120#define I2C_STAT_SLVPENDING_MASK (0x100U)
2121#define I2C_STAT_SLVPENDING_SHIFT (8U)
2122/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue
2123 * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if
2124 * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the
2125 * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is
2126 * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time
2127 * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section
2128 * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are
2129 * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must
2130 * also be detected automatically, since the address must be acknowledged before the clock can be
2131 * stretched.
2132 * 0b0..In progress. The Slave function does not currently need service.
2133 * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.
2134 */
2135#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)
2136#define I2C_STAT_SLVSTATE_MASK (0x600U)
2137#define I2C_STAT_SLVSTATE_SHIFT (9U)
2138/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for
2139 * the Slave function. All other values are reserved. See Table 401 for state values and actions.
2140 * note that the occurrence of some states and how they are handled are affected by DMA mode and
2141 * Automatic Operation modes.
2142 * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.
2143 * 0b01..Slave receive. Received data is available (Slave Receiver mode).
2144 * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode).
2145 */
2146#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)
2147#define I2C_STAT_SLVNOTSTR_MASK (0x800U)
2148#define I2C_STAT_SLVNOTSTR_SHIFT (11U)
2149/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock.
2150 * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave
2151 * operation. This read-only flag reflects the slave function status in real time.
2152 * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.
2153 * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or
2154 * Power-down mode could be entered at this time.
2155 */
2156#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)
2157#define I2C_STAT_SLVIDX_MASK (0x3000U)
2158#define I2C_STAT_SLVIDX_SHIFT (12U)
2159/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been
2160 * selected by receiving an address that matches one of the slave addresses defined by any enabled
2161 * slave address registers, and provides an identification of the address that was matched. It is
2162 * possible that more than one address could be matched, but only one match can be reported here.
2163 * 0b00..Address 0. Slave address 0 was matched.
2164 * 0b01..Address 1. Slave address 1 was matched.
2165 * 0b10..Address 2. Slave address 2 was matched.
2166 * 0b11..Address 3. Slave address 3 was matched.
2167 */
2168#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)
2169#define I2C_STAT_SLVSEL_MASK (0x4000U)
2170#define I2C_STAT_SLVSEL_SHIFT (14U)
2171/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave
2172 * function to acknowledge the address, or when the address has been automatically acknowledged.
2173 * It is cleared when another address cycle presents an address that does not match an enabled
2174 * address on the Slave function, when slave software decides to NACK a matched address, when
2175 * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of
2176 * Automatic Operation. SLVSEL is not cleared if software NACKs data.
2177 * 0b0..Not selected. The Slave function is not currently selected.
2178 * 0b1..Selected. The Slave function is currently selected.
2179 */
2180#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)
2181#define I2C_STAT_SLVDESEL_MASK (0x8000U)
2182#define I2C_STAT_SLVDESEL_SHIFT (15U)
2183/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via
2184 * INTENSET. This flag can be cleared by writing a 1 to this bit.
2185 * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently
2186 * selected. That information can be found in the SLVSEL flag.
2187 * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag
2188 * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.
2189 */
2190#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)
2191#define I2C_STAT_MONRDY_MASK (0x10000U)
2192#define I2C_STAT_MONRDY_SHIFT (16U)
2193/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read.
2194 * 0b0..No data. The Monitor function does not currently have data available.
2195 * 0b1..Data waiting. The Monitor function has data waiting to be read.
2196 */
2197#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)
2198#define I2C_STAT_MONOV_MASK (0x20000U)
2199#define I2C_STAT_MONOV_SHIFT (17U)
2200/*! MONOV - Monitor Overflow flag.
2201 * 0b0..No overrun. Monitor data has not overrun.
2202 * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not
2203 * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.
2204 */
2205#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)
2206#define I2C_STAT_MONACTIVE_MASK (0x40000U)
2207#define I2C_STAT_MONACTIVE_SHIFT (18U)
2208/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to
2209 * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred
2210 * more recently than a bus Stop.
2211 * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive.
2212 * 0b1..Active. The Monitor function considers the I2C bus to be active.
2213 */
2214#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)
2215#define I2C_STAT_MONIDLE_MASK (0x80000U)
2216#define I2C_STAT_MONIDLE_SHIFT (19U)
2217/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change
2218 * from active to inactive. This can be used by software to decide when to process data
2219 * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the
2220 * INTENSET register. The flag can be cleared by writing a 1 to this bit.
2221 * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software.
2222 * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.
2223 */
2224#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)
2225#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U)
2226#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U)
2227/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been
2228 * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock
2229 * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus
2230 * is idle.
2231 * 0b0..No time-out. I2C bus events have not caused a time-out.
2232 * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.
2233 */
2234#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)
2235#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U)
2236#define I2C_STAT_SCLTIMEOUT_SHIFT (25U)
2237/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the
2238 * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.
2239 * 0b0..No time-out. SCL low time has not caused a time-out.
2240 * 0b1..Time-out. SCL low time has caused a time-out.
2241 */
2242#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)
2243/*! @} */
2244
2245/*! @name INTENSET - Interrupt Enable Set and read register. */
2246/*! @{ */
2247#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U)
2248#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U)
2249/*! MSTPENDINGEN - Master Pending interrupt Enable.
2250 * 0b0..Disabled. The MstPending interrupt is disabled.
2251 * 0b1..Enabled. The MstPending interrupt is enabled.
2252 */
2253#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)
2254#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U)
2255#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U)
2256/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable.
2257 * 0b0..Disabled. The MstArbLoss interrupt is disabled.
2258 * 0b1..Enabled. The MstArbLoss interrupt is enabled.
2259 */
2260#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)
2261#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U)
2262#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U)
2263/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable.
2264 * 0b0..Disabled. The MstStStpErr interrupt is disabled.
2265 * 0b1..Enabled. The MstStStpErr interrupt is enabled.
2266 */
2267#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)
2268#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U)
2269#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U)
2270/*! SLVPENDINGEN - Slave Pending interrupt Enable.
2271 * 0b0..Disabled. The SlvPending interrupt is disabled.
2272 * 0b1..Enabled. The SlvPending interrupt is enabled.
2273 */
2274#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)
2275#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U)
2276#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U)
2277/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable.
2278 * 0b0..Disabled. The SlvNotStr interrupt is disabled.
2279 * 0b1..Enabled. The SlvNotStr interrupt is enabled.
2280 */
2281#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)
2282#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U)
2283#define I2C_INTENSET_SLVDESELEN_SHIFT (15U)
2284/*! SLVDESELEN - Slave Deselect interrupt Enable.
2285 * 0b0..Disabled. The SlvDeSel interrupt is disabled.
2286 * 0b1..Enabled. The SlvDeSel interrupt is enabled.
2287 */
2288#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)
2289#define I2C_INTENSET_MONRDYEN_MASK (0x10000U)
2290#define I2C_INTENSET_MONRDYEN_SHIFT (16U)
2291/*! MONRDYEN - Monitor data Ready interrupt Enable.
2292 * 0b0..Disabled. The MonRdy interrupt is disabled.
2293 * 0b1..Enabled. The MonRdy interrupt is enabled.
2294 */
2295#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)
2296#define I2C_INTENSET_MONOVEN_MASK (0x20000U)
2297#define I2C_INTENSET_MONOVEN_SHIFT (17U)
2298/*! MONOVEN - Monitor Overrun interrupt Enable.
2299 * 0b0..Disabled. The MonOv interrupt is disabled.
2300 * 0b1..Enabled. The MonOv interrupt is enabled.
2301 */
2302#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)
2303#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U)
2304#define I2C_INTENSET_MONIDLEEN_SHIFT (19U)
2305/*! MONIDLEEN - Monitor Idle interrupt Enable.
2306 * 0b0..Disabled. The MonIdle interrupt is disabled.
2307 * 0b1..Enabled. The MonIdle interrupt is enabled.
2308 */
2309#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)
2310#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U)
2311#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U)
2312/*! EVENTTIMEOUTEN - Event time-out interrupt Enable.
2313 * 0b0..Disabled. The Event time-out interrupt is disabled.
2314 * 0b1..Enabled. The Event time-out interrupt is enabled.
2315 */
2316#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)
2317#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U)
2318#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U)
2319/*! SCLTIMEOUTEN - SCL time-out interrupt Enable.
2320 * 0b0..Disabled. The SCL time-out interrupt is disabled.
2321 * 0b1..Enabled. The SCL time-out interrupt is enabled.
2322 */
2323#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)
2324/*! @} */
2325
2326/*! @name INTENCLR - Interrupt Enable Clear register. */
2327/*! @{ */
2328#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U)
2329#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U)
2330/*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding
2331 * bit in the INTENSET register if implemented.
2332 */
2333#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)
2334#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U)
2335#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U)
2336/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear.
2337 */
2338#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)
2339#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U)
2340#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U)
2341/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear.
2342 */
2343#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)
2344#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U)
2345#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U)
2346/*! SLVPENDINGCLR - Slave Pending interrupt clear.
2347 */
2348#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)
2349#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U)
2350#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U)
2351/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear.
2352 */
2353#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)
2354#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U)
2355#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U)
2356/*! SLVDESELCLR - Slave Deselect interrupt clear.
2357 */
2358#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)
2359#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U)
2360#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U)
2361/*! MONRDYCLR - Monitor data Ready interrupt clear.
2362 */
2363#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)
2364#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U)
2365#define I2C_INTENCLR_MONOVCLR_SHIFT (17U)
2366/*! MONOVCLR - Monitor Overrun interrupt clear.
2367 */
2368#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)
2369#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U)
2370#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U)
2371/*! MONIDLECLR - Monitor Idle interrupt clear.
2372 */
2373#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)
2374#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U)
2375#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U)
2376/*! EVENTTIMEOUTCLR - Event time-out interrupt clear.
2377 */
2378#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)
2379#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U)
2380#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U)
2381/*! SCLTIMEOUTCLR - SCL time-out interrupt clear.
2382 */
2383#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)
2384/*! @} */
2385
2386/*! @name TIMEOUT - Time-out value register. */
2387/*! @{ */
2388#define I2C_TIMEOUT_TOMIN_MASK (0xFU)
2389#define I2C_TIMEOUT_TOMIN_SHIFT (0U)
2390/*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum
2391 * time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks.
2392 */
2393#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)
2394#define I2C_TIMEOUT_TO_MASK (0xFFF0U)
2395#define I2C_TIMEOUT_TO_SHIFT (4U)
2396/*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C
2397 * function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation,
2398 * disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A
2399 * time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after
2400 * 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the
2401 * I2C function clock.
2402 */
2403#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)
2404/*! @} */
2405
2406/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */
2407/*! @{ */
2408#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU)
2409#define I2C_CLKDIV_DIVVAL_SHIFT (0U)
2410/*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that
2411 * need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 =
2412 * FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is
2413 * divided by 65,536 before use.
2414 */
2415#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)
2416/*! @} */
2417
2418/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */
2419/*! @{ */
2420#define I2C_INTSTAT_MSTPENDING_MASK (0x1U)
2421#define I2C_INTSTAT_MSTPENDING_SHIFT (0U)
2422/*! MSTPENDING - Master Pending.
2423 */
2424#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)
2425#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U)
2426#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U)
2427/*! MSTARBLOSS - Master Arbitration Loss flag.
2428 */
2429#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)
2430#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U)
2431#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U)
2432/*! MSTSTSTPERR - Master Start/Stop Error flag.
2433 */
2434#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)
2435#define I2C_INTSTAT_SLVPENDING_MASK (0x100U)
2436#define I2C_INTSTAT_SLVPENDING_SHIFT (8U)
2437/*! SLVPENDING - Slave Pending.
2438 */
2439#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)
2440#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U)
2441#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U)
2442/*! SLVNOTSTR - Slave Not Stretching status.
2443 */
2444#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)
2445#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U)
2446#define I2C_INTSTAT_SLVDESEL_SHIFT (15U)
2447/*! SLVDESEL - Slave Deselected flag.
2448 */
2449#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)
2450#define I2C_INTSTAT_MONRDY_MASK (0x10000U)
2451#define I2C_INTSTAT_MONRDY_SHIFT (16U)
2452/*! MONRDY - Monitor Ready.
2453 */
2454#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)
2455#define I2C_INTSTAT_MONOV_MASK (0x20000U)
2456#define I2C_INTSTAT_MONOV_SHIFT (17U)
2457/*! MONOV - Monitor Overflow flag.
2458 */
2459#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)
2460#define I2C_INTSTAT_MONIDLE_MASK (0x80000U)
2461#define I2C_INTSTAT_MONIDLE_SHIFT (19U)
2462/*! MONIDLE - Monitor Idle flag.
2463 */
2464#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)
2465#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U)
2466#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U)
2467/*! EVENTTIMEOUT - Event time-out Interrupt flag.
2468 */
2469#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)
2470#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U)
2471#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U)
2472/*! SCLTIMEOUT - SCL time-out Interrupt flag.
2473 */
2474#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)
2475/*! @} */
2476
2477/*! @name MSTCTL - Master control register. */
2478/*! @{ */
2479#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U)
2480#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U)
2481/*! MSTCONTINUE - Master Continue.
2482 * 0b0..No effect.
2483 * 0b1..Informs the Master function to continue to the next operation.
2484 */
2485#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)
2486#define I2C_MSTCTL_MSTSTART_MASK (0x2U)
2487#define I2C_MSTCTL_MSTSTART_SHIFT (1U)
2488/*! MSTSTART - Master Start control.
2489 * 0b0..No effect.
2490 * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time.
2491 */
2492#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)
2493#define I2C_MSTCTL_MSTSTOP_MASK (0x4U)
2494#define I2C_MSTCTL_MSTSTOP_SHIFT (2U)
2495/*! MSTSTOP - Master Stop control.
2496 * 0b0..No effect.
2497 * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave
2498 * if the master is receiving data from the slave (Master Receiver mode).
2499 */
2500#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)
2501#define I2C_MSTCTL_MSTDMA_MASK (0x8U)
2502#define I2C_MSTCTL_MSTDMA_SHIFT (3U)
2503/*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type
2504 * operations such as Start, address, Stop, and address match must always be done with software,
2505 * typically via an interrupt. Address acknowledgement must also be done by software except when
2506 * the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by
2507 * hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA
2508 * must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is
2509 * read/write.
2510 * 0b0..Disable. No DMA requests are generated for master operation.
2511 * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating
2512 * Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.
2513 */
2514#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK)
2515/*! @} */
2516
2517/*! @name MSTTIME - Master timing configuration. */
2518/*! @{ */
2519#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U)
2520#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U)
2521/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this
2522 * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This
2523 * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters
2524 * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW.
2525 * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.
2526 * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.
2527 * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.
2528 * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.
2529 * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.
2530 * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.
2531 * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.
2532 * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.
2533 */
2534#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)
2535#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U)
2536#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U)
2537/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this
2538 * master on SCL. Other masters in a multi-master system could shorten this time. This
2539 * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters
2540 * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.
2541 * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.
2542 * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .
2543 * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.
2544 * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.
2545 * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.
2546 * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.
2547 * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.
2548 * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.
2549 */
2550#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)
2551/*! @} */
2552
2553/*! @name MSTDAT - Combined Master receiver and transmitter data register. */
2554/*! @{ */
2555#define I2C_MSTDAT_DATA_MASK (0xFFU)
2556#define I2C_MSTDAT_DATA_SHIFT (0U)
2557/*! DATA - Master function data register. Read: read the most recently received data for the Master
2558 * function. Write: transmit data using the Master function.
2559 */
2560#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)
2561/*! @} */
2562
2563/*! @name SLVCTL - Slave control register. */
2564/*! @{ */
2565#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U)
2566#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U)
2567/*! SLVCONTINUE - Slave Continue.
2568 * 0b0..No effect.
2569 * 0b1..Informs the Slave function to continue to the next operation.
2570 */
2571#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)
2572#define I2C_SLVCTL_SLVNACK_MASK (0x2U)
2573#define I2C_SLVCTL_SLVNACK_SHIFT (1U)
2574/*! SLVNACK - Slave NACK.
2575 * 0b0..No effect.
2576 * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode).
2577 */
2578#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)
2579#define I2C_SLVCTL_SLVDMA_MASK (0x8U)
2580#define I2C_SLVCTL_SLVDMA_SHIFT (3U)
2581/*! SLVDMA - Slave DMA enable.
2582 * 0b0..Disabled. No DMA requests are issued for Slave mode operation.
2583 * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception.
2584 */
2585#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK)
2586/*! @} */
2587
2588/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */
2589/*! @{ */
2590#define I2C_SLVDAT_DATA_MASK (0xFFU)
2591#define I2C_SLVDAT_DATA_SHIFT (0U)
2592/*! DATA - Slave function data register. Read: read the most recently received data for the Slave
2593 * function. Write: transmit data using the Slave function.
2594 */
2595#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)
2596/*! @} */
2597
2598/*! @name SLVADR - Slave address register. */
2599/*! @{ */
2600#define I2C_SLVADR_SADISABLE_MASK (0x1U)
2601#define I2C_SLVADR_SADISABLE_SHIFT (0U)
2602/*! SADISABLE - Slave Address n Disable.
2603 * 0b0..Enabled. Slave Address n is enabled.
2604 * 0b1..Ignored Slave Address n is ignored.
2605 */
2606#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)
2607#define I2C_SLVADR_SLVADR_MASK (0xFEU)
2608#define I2C_SLVADR_SLVADR_SHIFT (1U)
2609/*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled.
2610 */
2611#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)
2612/*! @} */
2613
2614/* The count of I2C_SLVADR */
2615#define I2C_SLVADR_COUNT (4U)
2616
2617/*! @name SLVQUAL0 - Slave Qualification for address 0. */
2618/*! @{ */
2619#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U)
2620#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U)
2621/*! QUALMODE0 - Qualify mode for slave address 0.
2622 * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.
2623 * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.
2624 */
2625#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)
2626#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU)
2627#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U)
2628/*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to
2629 * be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is
2630 * set to 1 will cause an automatic match of the corresponding bit of the received address when it
2631 * is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for
2632 * address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0
2633 * (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]).
2634 */
2635#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)
2636/*! @} */
2637
2638/*! @name MONRXDAT - Monitor receiver data register. */
2639/*! @{ */
2640#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU)
2641#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U)
2642/*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins.
2643 */
2644#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)
2645#define I2C_MONRXDAT_MONSTART_MASK (0x100U)
2646#define I2C_MONRXDAT_MONSTART_SHIFT (8U)
2647/*! MONSTART - Monitor Received Start.
2648 * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus.
2649 * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus.
2650 */
2651#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)
2652#define I2C_MONRXDAT_MONRESTART_MASK (0x200U)
2653#define I2C_MONRXDAT_MONRESTART_SHIFT (9U)
2654/*! MONRESTART - Monitor Received Repeated Start.
2655 * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.
2656 * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.
2657 */
2658#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)
2659#define I2C_MONRXDAT_MONNACK_MASK (0x400U)
2660#define I2C_MONRXDAT_MONNACK_SHIFT (10U)
2661/*! MONNACK - Monitor Received NACK.
2662 * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.
2663 * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.
2664 */
2665#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)
2666/*! @} */
2667
2668
2669/*!
2670 * @}
2671 */ /* end of group I2C_Register_Masks */
2672
2673
2674/* I2C - Peripheral instance base addresses */
2675/** Peripheral I2C0 base address */
2676#define I2C0_BASE (0x40050000u)
2677/** Peripheral I2C0 base pointer */
2678#define I2C0 ((I2C_Type *)I2C0_BASE)
2679/** Array initializer of I2C peripheral base addresses */
2680#define I2C_BASE_ADDRS { I2C0_BASE }
2681/** Array initializer of I2C peripheral base pointers */
2682#define I2C_BASE_PTRS { I2C0 }
2683/** Interrupt vectors for the I2C peripheral type */
2684#define I2C_IRQS { I2C0_IRQn }
2685
2686/*!
2687 * @}
2688 */ /* end of group I2C_Peripheral_Access_Layer */
2689
2690
2691/* ----------------------------------------------------------------------------
2692 -- INPUTMUX Peripheral Access Layer
2693 ---------------------------------------------------------------------------- */
2694
2695/*!
2696 * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer
2697 * @{
2698 */
2699
2700/** INPUTMUX - Register Layout Typedef */
2701typedef struct {
2702 __IO uint32_t DMA_ITRIG_INMUX[18]; /**< Trigger select register for DMA channel, array offset: 0x0, array step: 0x4 */
2703 uint8_t RESERVED_0[16312];
2704 __IO uint32_t DMA_INMUX_INMUX[2]; /**< DMA output trigger selection to become DMA trigger 7 and DMA trigger 8, array offset: 0x4000, array step: 0x4 */
2705 uint8_t RESERVED_1[24];
2706 __IO uint32_t SCT0_INMUX[4]; /**< input select register for SCT, array offset: 0x4020, array step: 0x4 */
2707} INPUTMUX_Type;
2708
2709/* ----------------------------------------------------------------------------
2710 -- INPUTMUX Register Masks
2711 ---------------------------------------------------------------------------- */
2712
2713/*!
2714 * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks
2715 * @{
2716 */
2717
2718/*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */
2719/*! @{ */
2720#define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK (0xFU)
2721#define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT (0U)
2722/*! INP - Input mux register for trigger inputs 0 to 23 connected to DMA channel 0. Selects from
2723 * ADC, SCT, ACMP, pin interrupts, and DMA requests.
2724 * 0b0000..ADC_SEQA_IRQ
2725 * 0b0001..ADC_SEQB_IRQ
2726 * 0b0010..SCT_DMA0
2727 * 0b0011..SCT_DMA1
2728 * 0b0100..ACMP_O
2729 * 0b0101..PININT0
2730 * 0b0110..PININT1
2731 * 0b0111..DMA trigger mux 0
2732 * 0b1000..DMA trigger mux 1
2733 * 0b1001-0b1111..None
2734 */
2735#define INPUTMUX_DMA_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK)
2736/*! @} */
2737
2738/* The count of INPUTMUX_DMA_ITRIG_INMUX */
2739#define INPUTMUX_DMA_ITRIG_INMUX_COUNT (18U)
2740
2741/*! @name DMA_INMUX_INMUX - DMA output trigger selection to become DMA trigger 7 and DMA trigger 8 */
2742/*! @{ */
2743#define INPUTMUX_DMA_INMUX_INMUX_INP_MASK (0x1FU)
2744#define INPUTMUX_DMA_INMUX_INMUX_INP_SHIFT (0U)
2745/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 17).
2746 */
2747#define INPUTMUX_DMA_INMUX_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_INMUX_INMUX_INP_SHIFT)) & INPUTMUX_DMA_INMUX_INMUX_INP_MASK)
2748/*! @} */
2749
2750/* The count of INPUTMUX_DMA_INMUX_INMUX */
2751#define INPUTMUX_DMA_INMUX_INMUX_COUNT (2U)
2752
2753/*! @name SCT0_INMUX - input select register for SCT */
2754/*! @{ */
2755#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0xFU)
2756#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U)
2757/*! INP_N - Input mux register for SCT input n (n = 0 to 3). 0 = sct input 0 1=sct input 1 2= sct
2758 * input 2 3= sct input 3 4= adc_thcmp_irq 5 = comparator out 6=arm_txev 7=debug_halted
2759 * 0b0000..SCT_PIN0
2760 * 0b0001..SCT_PIN1
2761 * 0b0010..SCT_PIN2
2762 * 0b0011..SCT_PIN3
2763 * 0b0100..ADC_THCMP_IRQ
2764 * 0b0101..ACMP_O
2765 * 0b0110..ARM_TXEV
2766 * 0b0111..DEBUG_HALTED
2767 * 0b1000-0b1111..None
2768 */
2769#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK)
2770/*! @} */
2771
2772/* The count of INPUTMUX_SCT0_INMUX */
2773#define INPUTMUX_SCT0_INMUX_COUNT (4U)
2774
2775
2776/*!
2777 * @}
2778 */ /* end of group INPUTMUX_Register_Masks */
2779
2780
2781/* INPUTMUX - Peripheral instance base addresses */
2782/** Peripheral INPUTMUX base address */
2783#define INPUTMUX_BASE (0x40028000u)
2784/** Peripheral INPUTMUX base pointer */
2785#define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE)
2786/** Array initializer of INPUTMUX peripheral base addresses */
2787#define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE }
2788/** Array initializer of INPUTMUX peripheral base pointers */
2789#define INPUTMUX_BASE_PTRS { INPUTMUX }
2790
2791/*!
2792 * @}
2793 */ /* end of group INPUTMUX_Peripheral_Access_Layer */
2794
2795
2796/* ----------------------------------------------------------------------------
2797 -- IOCON Peripheral Access Layer
2798 ---------------------------------------------------------------------------- */
2799
2800/*!
2801 * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer
2802 * @{
2803 */
2804
2805/** IOCON - Register Layout Typedef */
2806typedef struct {
2807 __IO uint32_t PIO[31]; /**< Digital I/O control for pins PIO0_17..Digital I/O control for pins PIO0_18, array offset: 0x0, array step: 0x4 */
2808} IOCON_Type;
2809
2810/* ----------------------------------------------------------------------------
2811 -- IOCON Register Masks
2812 ---------------------------------------------------------------------------- */
2813
2814/*!
2815 * @addtogroup IOCON_Register_Masks IOCON Register Masks
2816 * @{
2817 */
2818
2819/*! @name PIO - Digital I/O control for pins PIO0_17..Digital I/O control for pins PIO0_18 */
2820/*! @{ */
2821#define IOCON_PIO_MODE_MASK (0x18U)
2822#define IOCON_PIO_MODE_SHIFT (3U)
2823/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control).
2824 * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled).
2825 * 0b01..Pull-down. Pull-down resistor enabled.
2826 * 0b10..Pull-up. Pull-up resistor enabled.
2827 * 0b11..Repeater. Repeater mode.
2828 */
2829#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK)
2830#define IOCON_PIO_HYS_MASK (0x20U)
2831#define IOCON_PIO_HYS_SHIFT (5U)
2832/*! HYS - Hysteresis.
2833 * 0b0..Disable
2834 * 0b1..Enable
2835 */
2836#define IOCON_PIO_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_HYS_SHIFT)) & IOCON_PIO_HYS_MASK)
2837#define IOCON_PIO_INV_MASK (0x40U)
2838#define IOCON_PIO_INV_SHIFT (6U)
2839/*! INV - Invert input
2840 * 0b0..Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).
2841 * 0b1..Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).
2842 */
2843#define IOCON_PIO_INV(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INV_SHIFT)) & IOCON_PIO_INV_MASK)
2844#define IOCON_PIO_I2CMODE_MASK (0x300U)
2845#define IOCON_PIO_I2CMODE_SHIFT (8U)
2846/*! I2CMODE - Selects I2C mode.
2847 * 0b00..Standard mode/ Fast-mode I2C.
2848 * 0b01..Standard GPIO functionality. Requires external pull-up for GPIO output function.
2849 * 0b10..Fast-mode Plus I2C
2850 * 0b11..Reserved
2851 */
2852#define IOCON_PIO_I2CMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CMODE_SHIFT)) & IOCON_PIO_I2CMODE_MASK)
2853#define IOCON_PIO_OD_MASK (0x400U)
2854#define IOCON_PIO_OD_SHIFT (10U)
2855/*! OD - Open-drain mode.
2856 * 0b0..Disable.
2857 * 0b1..Open-drain mode enabled. Remark: This is not a true open-drain mode.
2858 */
2859#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK)
2860#define IOCON_PIO_S_MODE_MASK (0x1800U)
2861#define IOCON_PIO_S_MODE_SHIFT (11U)
2862/*! S_MODE - Digital filter sample mode.
2863 * 0b00..Bypass input filter.
2864 * 0b01..1 clock cycle. Input pulses shorter than one filter clock are rejected.
2865 * 0b10..2 clock cycles. Input pulses shorter than two filter clocks are rejected.
2866 * 0b11..3 clock cycles. Input pulses shorter than three filter clocks are rejected.
2867 */
2868#define IOCON_PIO_S_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_S_MODE_SHIFT)) & IOCON_PIO_S_MODE_MASK)
2869#define IOCON_PIO_CLK_DIV_MASK (0xE000U)
2870#define IOCON_PIO_CLK_DIV_SHIFT (13U)
2871/*! CLK_DIV - Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
2872 * 0b000..IOCONCLKDIV0
2873 * 0b001..IOCONCLKDIV1
2874 * 0b010..IOCONCLKDIV2
2875 * 0b011..IOCONCLKDIV3
2876 * 0b100..IOCONCLKDIV4
2877 * 0b101..IOCONCLKDIV5
2878 * 0b110..IOCONCLKDIV6
2879 */
2880#define IOCON_PIO_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_CLK_DIV_SHIFT)) & IOCON_PIO_CLK_DIV_MASK)
2881/*! @} */
2882
2883/* The count of IOCON_PIO */
2884#define IOCON_PIO_COUNT (31U)
2885
2886
2887/*!
2888 * @}
2889 */ /* end of group IOCON_Register_Masks */
2890
2891
2892/* IOCON - Peripheral instance base addresses */
2893/** Peripheral IOCON base address */
2894#define IOCON_BASE (0x40044000u)
2895/** Peripheral IOCON base pointer */
2896#define IOCON ((IOCON_Type *)IOCON_BASE)
2897/** Array initializer of IOCON peripheral base addresses */
2898#define IOCON_BASE_ADDRS { IOCON_BASE }
2899/** Array initializer of IOCON peripheral base pointers */
2900#define IOCON_BASE_PTRS { IOCON }
2901
2902#define IOCON_INDEX_PIO0_17 (0 )
2903#define IOCON_INDEX_PIO0_13 (1 )
2904#define IOCON_INDEX_PIO0_12 (2 )
2905#define IOCON_INDEX_PIO0_5 (3 )
2906#define IOCON_INDEX_PIO0_4 (4 )
2907#define IOCON_INDEX_PIO0_3 (5 )
2908#define IOCON_INDEX_PIO0_2 (6 )
2909#define IOCON_INDEX_PIO0_11 (7 )
2910#define IOCON_INDEX_PIO0_10 (8 )
2911#define IOCON_INDEX_PIO0_16 (9 )
2912#define IOCON_INDEX_PIO0_15 (10)
2913#define IOCON_INDEX_PIO0_1 (11)
2914#define IOCON_INDEX_PIO0_9 (13)
2915#define IOCON_INDEX_PIO0_8 (14)
2916#define IOCON_INDEX_PIO0_7 (15)
2917#define IOCON_INDEX_PIO0_6 (16)
2918#define IOCON_INDEX_PIO0_0 (17)
2919#define IOCON_INDEX_PIO0_14 (18)
2920#define IOCON_INDEX_PIO0_28 (20)
2921#define IOCON_INDEX_PIO0_27 (21)
2922#define IOCON_INDEX_PIO0_26 (22)
2923#define IOCON_INDEX_PIO0_25 (23)
2924#define IOCON_INDEX_PIO0_24 (24)
2925#define IOCON_INDEX_PIO0_23 (25)
2926#define IOCON_INDEX_PIO0_22 (26)
2927#define IOCON_INDEX_PIO0_21 (27)
2928#define IOCON_INDEX_PIO0_20 (28)
2929#define IOCON_INDEX_PIO0_19 (29)
2930#define IOCON_INDEX_PIO0_18 (30)
2931
2932
2933/*!
2934 * @}
2935 */ /* end of group IOCON_Peripheral_Access_Layer */
2936
2937
2938/* ----------------------------------------------------------------------------
2939 -- MRT Peripheral Access Layer
2940 ---------------------------------------------------------------------------- */
2941
2942/*!
2943 * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer
2944 * @{
2945 */
2946
2947/** MRT - Register Layout Typedef */
2948typedef struct {
2949 struct { /* offset: 0x0, array step: 0x10 */
2950 __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */
2951 __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */
2952 __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */
2953 __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */
2954 } CHANNEL[4];
2955 uint8_t RESERVED_0[176];
2956 __I uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance., offset: 0xF0 */
2957 __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */
2958 __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */
2959} MRT_Type;
2960
2961/* ----------------------------------------------------------------------------
2962 -- MRT Register Masks
2963 ---------------------------------------------------------------------------- */
2964
2965/*!
2966 * @addtogroup MRT_Register_Masks MRT Register Masks
2967 * @{
2968 */
2969
2970/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */
2971/*! @{ */
2972#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0x7FFFFFFFU)
2973#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U)
2974/*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT
2975 * channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to
2976 * this bit field starts the timer immediately. If the timer is running, writing a zero to this
2977 * bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer
2978 * stops at the end of the time interval.
2979 */
2980#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)
2981#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U)
2982#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U)
2983/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register.
2984 * This bit is write-only. Reading this bit always returns 0.
2985 * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the
2986 * time interval if the repeat mode is selected.
2987 * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.
2988 */
2989#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
2990/*! @} */
2991
2992/* The count of MRT_CHANNEL_INTVAL */
2993#define MRT_CHANNEL_INTVAL_COUNT (4U)
2994
2995/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */
2996/*! @{ */
2997#define MRT_CHANNEL_TIMER_VALUE_MASK (0x7FFFFFFFU)
2998#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U)
2999/*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn
3000 * register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval
3001 * or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn
3002 * register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields
3003 * returns -1 (0x00FF FFFF).
3004 */
3005#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
3006/*! @} */
3007
3008/* The count of MRT_CHANNEL_TIMER */
3009#define MRT_CHANNEL_TIMER_COUNT (4U)
3010
3011/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */
3012/*! @{ */
3013#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U)
3014#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U)
3015/*! INTEN - Enable the TIMERn interrupt.
3016 * 0b0..Disabled. TIMERn interrupt is disabled.
3017 * 0b1..Enabled. TIMERn interrupt is enabled.
3018 */
3019#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)
3020#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U)
3021#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U)
3022/*! MODE - Selects timer mode.
3023 * 0b00..Repeat interrupt mode.
3024 * 0b01..One-shot interrupt mode.
3025 * 0b10..One-shot stall mode.
3026 * 0b11..Reserved.
3027 */
3028#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
3029/*! @} */
3030
3031/* The count of MRT_CHANNEL_CTRL */
3032#define MRT_CHANNEL_CTRL_COUNT (4U)
3033
3034/*! @name CHANNEL_STAT - MRT Status register. */
3035/*! @{ */
3036#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U)
3037#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U)
3038/*! INTFLAG - Monitors the interrupt flag.
3039 * 0b0..No pending interrupt. Writing a zero is equivalent to no operation.
3040 * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If
3041 * the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt
3042 * are raised. Writing a 1 to this bit clears the interrupt request.
3043 */
3044#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)
3045#define MRT_CHANNEL_STAT_RUN_MASK (0x2U)
3046#define MRT_CHANNEL_STAT_RUN_SHIFT (1U)
3047/*! RUN - Indicates the state of TIMERn. This bit is read-only.
3048 * 0b0..Idle state. TIMERn is stopped.
3049 * 0b1..Running. TIMERn is running.
3050 */
3051#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)
3052/*! @} */
3053
3054/* The count of MRT_CHANNEL_STAT */
3055#define MRT_CHANNEL_STAT_COUNT (4U)
3056
3057/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance. */
3058/*! @{ */
3059#define MRT_MODCFG_NOC_MASK (0xFU)
3060#define MRT_MODCFG_NOC_SHIFT (0U)
3061/*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.)
3062 */
3063#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)
3064#define MRT_MODCFG_NOB_MASK (0x1F0U)
3065#define MRT_MODCFG_NOB_SHIFT (4U)
3066/*! NOB - Identifies the number of timer bits in this MRT. (31 bits wide on this device.)
3067 */
3068#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)
3069/*! @} */
3070
3071/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */
3072/*! @{ */
3073#define MRT_IDLE_CH_CHAN_MASK (0xF0U)
3074#define MRT_IDLE_CH_CHAN_SHIFT (4U)
3075/*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is
3076 * positioned such that it can be used as an offset from the MRT base address in order to access
3077 * the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See
3078 * text above for more details.
3079 */
3080#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
3081/*! @} */
3082
3083/*! @name IRQ_FLAG - Global interrupt flag register */
3084/*! @{ */
3085#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U)
3086#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U)
3087/*! GFLAG0 - Monitors the interrupt flag of TIMER0.
3088 * 0b0..No pending interrupt. Writing a zero is equivalent to no operation.
3089 * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If
3090 * the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global
3091 * interrupt are raised. Writing a 1 to this bit clears the interrupt request.
3092 */
3093#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)
3094#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U)
3095#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U)
3096/*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0.
3097 */
3098#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)
3099#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U)
3100#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U)
3101/*! GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0.
3102 */
3103#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)
3104#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U)
3105#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U)
3106/*! GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0.
3107 */
3108#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)
3109/*! @} */
3110
3111
3112/*!
3113 * @}
3114 */ /* end of group MRT_Register_Masks */
3115
3116
3117/* MRT - Peripheral instance base addresses */
3118/** Peripheral MRT0 base address */
3119#define MRT0_BASE (0x40004000u)
3120/** Peripheral MRT0 base pointer */
3121#define MRT0 ((MRT_Type *)MRT0_BASE)
3122/** Array initializer of MRT peripheral base addresses */
3123#define MRT_BASE_ADDRS { MRT0_BASE }
3124/** Array initializer of MRT peripheral base pointers */
3125#define MRT_BASE_PTRS { MRT0 }
3126/** Interrupt vectors for the MRT peripheral type */
3127#define MRT_IRQS { MRT0_IRQn }
3128
3129/*!
3130 * @}
3131 */ /* end of group MRT_Peripheral_Access_Layer */
3132
3133
3134/* ----------------------------------------------------------------------------
3135 -- MTB Peripheral Access Layer
3136 ---------------------------------------------------------------------------- */
3137
3138/*!
3139 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
3140 * @{
3141 */
3142
3143/** MTB - Register Layout Typedef */
3144typedef struct {
3145 __IO uint32_t POSITION; /**< POSITION Register, offset: 0x0 */
3146 __IO uint32_t MASTER; /**< MASTER Register, offset: 0x4 */
3147 __IO uint32_t FLOW; /**< FLOW Register, offset: 0x8 */
3148 __I uint32_t BASE; /**< Indicates where the SRAM is located in the processor memory map. This register is provided to enable auto discovery of the MTB SRAM location, by a debug agent., offset: 0xC */
3149} MTB_Type;
3150
3151/* ----------------------------------------------------------------------------
3152 -- MTB Register Masks
3153 ---------------------------------------------------------------------------- */
3154
3155/*!
3156 * @addtogroup MTB_Register_Masks MTB Register Masks
3157 * @{
3158 */
3159
3160/*! @name POSITION - POSITION Register */
3161/*! @{ */
3162#define MTB_POSITION_WRAP_MASK (0x4U)
3163#define MTB_POSITION_WRAP_SHIFT (2U)
3164/*! WRAP - This bit is set to 1 automatically when the POINTER value wraps as determined by the
3165 * MASTER.MASK field in the MASTER Trace Control Register.
3166 */
3167#define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK)
3168#define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U)
3169#define MTB_POSITION_POINTER_SHIFT (3U)
3170/*! POINTER - Trace packet location pointer. Because a packet consists of two words, the POINTER
3171 * field is the location of the first word of a packet. This field contains bits [31:3] of the
3172 * address, in the SRAM, where the next trace packet will be written. The field points to an unused
3173 * location and is automatically incremented. A debug agent can calculate the system address, on
3174 * the AHB-Lite bus, of the SRAM location pointed to by the POSITION register using the following
3175 * equation: system address = BASE + ((P + (2AWIDTH - (BASE MOD 2AWIDTH))) MOD 2AWIDTH). Where P =
3176 * POSITION AND 0xFFFF_FFF8. Where BASE is the BASE register value
3177 */
3178#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK)
3179/*! @} */
3180
3181/*! @name MASTER - MASTER Register */
3182/*! @{ */
3183#define MTB_MASTER_MASK_MASK (0x1FU)
3184#define MTB_MASTER_MASK_SHIFT (0U)
3185/*! MASK - This value determines the maximum size of the trace buffer in SRAM. It specifies the
3186 * most-significant bit of the POSITION.POINTER field that can be updated by automatic increment. If
3187 * the trace tries to advance past this power of two, the POSITION.WRAP bit is set to 1, the
3188 * POSITION.POINTER[MASK:0] bits are set to zero, and the POSITION.POINTER[AWIDTH-4:MASK+1] bits
3189 * remain unchanged. This field causes the trace packet information to be stored in a circular buffer
3190 * of size 2(MASK+4) bytes, that can be positioned in memory at multiples of this size. Valid
3191 * values of this field are zero to AWIDTH-4. Values greater than the maximum have the same effect
3192 * as the maximum.
3193 */
3194#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK)
3195#define MTB_MASTER_TSTARTEN_MASK (0x20U)
3196#define MTB_MASTER_TSTARTEN_SHIFT (5U)
3197/*! TSTARTEN - Trace start input enable. If this bit is 1 and the TSTART signal is HIGH, then the EN
3198 * bit is set to 1. Tracing continues until a stop condition occurs.
3199 */
3200#define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK)
3201#define MTB_MASTER_TSTOPEN_MASK (0x40U)
3202#define MTB_MASTER_TSTOPEN_SHIFT (6U)
3203/*! TSTOPEN - Trace stop input enable. If this bit is 1 and the TSTOP signal is HIGH, then the EN
3204 * bit is set to 0. If a trace packet is being written to memory, the write is completed before
3205 * tracing is stopped.
3206 */
3207#define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK)
3208#define MTB_MASTER_SFRWPRIV_MASK (0x80U)
3209#define MTB_MASTER_SFRWPRIV_SHIFT (7U)
3210/*! SFRWPRIV - Special Function Register Write Privilege bit. If this bit is 0, then User or
3211 * Privileged AHB-Lite read and write accesses to the Special Function Registers are permitted. If this
3212 * bit is 1, then only Privileged write accesses are permitted and User write accesses are
3213 * ignored. The HPROT[1] signal determines if an access is User or Privileged.
3214 */
3215#define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK)
3216#define MTB_MASTER_RAMPRIV_MASK (0x100U)
3217#define MTB_MASTER_RAMPRIV_SHIFT (8U)
3218/*! RAMPRIV - SRAM Privilege bit. If this bit is 0, then User or Privileged AHB-Lite read and write
3219 * accesses to the SRAM are permitted. If this bit is 1, then only Privileged AHB-Lite read and
3220 * write accesses to the SRAM are permitted and User accesses are RAZ/WI. The HPROT[1] signal
3221 * determines if an access is User or Privileged.
3222 */
3223#define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK)
3224#define MTB_MASTER_HALTREQ_MASK (0x200U)
3225#define MTB_MASTER_HALTREQ_SHIFT (9U)
3226/*! HALTREQ - Halt request bit. This bit is connected to the halt request signal of the trace logic,
3227 * EDBGRQ. When HALTREQ is set to 1, EDBGRQ is asserted if DBGEN is also HIGH. The HALTREQ bit
3228 * can be automatically set to 1 using the FLOW.WATERMARK field.
3229 */
3230#define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK)
3231#define MTB_MASTER_EN_MASK (0x80000000U)
3232#define MTB_MASTER_EN_SHIFT (31U)
3233/*! EN - Main trace enable bit. When this bit is 1 trace data is written into the SRAM memory
3234 * location addressed by POSITION.POINTER. The POSITION.POINTER value auto increments after the trace
3235 * data packet is written. The EN bit can be automatically set to 0 using the FLOW.WATERMARK field
3236 * and the FLOW.AUTOSTOP bit. The EN bit is automatically set to 1 if the TSTARTEN bit is 1 and
3237 * the TSTART signal is HIGH. The EN bit is automatically set to 0 if TSTOPEN bit is 1 and the
3238 * TSTOP signal is HIGH.
3239 */
3240#define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK)
3241/*! @} */
3242
3243/*! @name FLOW - FLOW Register */
3244/*! @{ */
3245#define MTB_FLOW_AUTOSTOP_MASK (0x1U)
3246#define MTB_FLOW_AUTOSTOP_SHIFT (0U)
3247/*! AUTOSTOP - If this bit is 1 and WATERMARK is equal to POSITION.POINTER, then the MASTER.EN bit
3248 * is automatically set to 0. This stops tracing.
3249 */
3250#define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK)
3251#define MTB_FLOW_AUTOHALT_MASK (0x2U)
3252#define MTB_FLOW_AUTOHALT_SHIFT (1U)
3253/*! AUTOHALT - If this bit is 1 and WATERMARK is equal to POSITION.POINTER, then the MASTER.HALTREQ
3254 * bit is automatically set to 1. If the DBGEN signal is HIGH, the MTB asserts this halt request
3255 * to the Cortex-M0+ processor by asserting the EDBGRQ signal.
3256 */
3257#define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK)
3258#define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U)
3259#define MTB_FLOW_WATERMARK_SHIFT (3U)
3260/*! WATERMARK - WATERMARK value. This field contains an address in the same format as the
3261 * POSITION.POINTER field. When the POSITION.POINTER matches the WATERMARK field value, actions defined by
3262 * the AUTOHALT and AUTOSTOP bits are performed.
3263 */
3264#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK)
3265/*! @} */
3266
3267/*! @name BASE - Indicates where the SRAM is located in the processor memory map. This register is provided to enable auto discovery of the MTB SRAM location, by a debug agent. */
3268/*! @{ */
3269#define MTB_BASE_BASE_MASK