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authorAkshay <[email protected]>2022-04-10 12:13:40 +0100
committerAkshay <[email protected]>2022-04-10 12:13:40 +0100
commitdc90387ce7d8ba7b607d9c48540bf6d8b560f14d (patch)
tree4ccb8fa5886b66fa9d480edef74236c27f035e16 /lib/chibios/os/common/ext/ST/STM32F7xx/stm32f767xx.h
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1/**
2 ******************************************************************************
3 * @file stm32f767xx.h
4 * @author MCD Application Team
5 * @version V1.2.0
6 * @date 30-December-2016
7 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
8 *
9 * This file contains:
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral�s registers hardware
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
18 *
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ******************************************************************************
42 */
43
44/** @addtogroup CMSIS_Device
45 * @{
46 */
47
48/** @addtogroup stm32f767xx
49 * @{
50 */
51
52#ifndef __STM32F767xx_H
53#define __STM32F767xx_H
54
55#ifdef __cplusplus
56 extern "C" {
57#endif /* __cplusplus */
58
59/** @addtogroup Configuration_section_for_CMSIS
60 * @{
61 */
62
63/**
64 * @brief STM32F7xx Interrupt Number Definition, according to the selected device
65 * in @ref Library_configuration_section
66 */
67typedef enum
68{
69/****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
70 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
71 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */
72 BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */
73 UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */
74 SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */
75 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */
76 PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */
77 SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */
78/****** STM32 specific Interrupt Numbers **********************************************************************/
79 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
80 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
81 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
82 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
83 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
84 RCC_IRQn = 5, /*!< RCC global Interrupt */
85 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
86 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
87 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
88 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
89 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
90 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
91 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
92 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
93 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
94 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
95 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
96 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
97 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
98 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
99 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
100 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
101 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
102 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
103 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
104 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
105 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
106 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
107 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
108 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
109 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
110 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
111 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
112 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
113 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
114 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
115 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
116 USART1_IRQn = 37, /*!< USART1 global Interrupt */
117 USART2_IRQn = 38, /*!< USART2 global Interrupt */
118 USART3_IRQn = 39, /*!< USART3 global Interrupt */
119 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
120 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
121 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
122 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
123 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
124 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
125 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
126 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
127 FMC_IRQn = 48, /*!< FMC global Interrupt */
128 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
129 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
130 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
131 UART4_IRQn = 52, /*!< UART4 global Interrupt */
132 UART5_IRQn = 53, /*!< UART5 global Interrupt */
133 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
134 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
135 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
136 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
137 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
138 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
139 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
140 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
141 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
142 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
143 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
144 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
145 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
146 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
147 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
148 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
149 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
150 USART6_IRQn = 71, /*!< USART6 global interrupt */
151 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
152 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
153 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
154 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
155 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
156 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
157 DCMI_IRQn = 78, /*!< DCMI global interrupt */
158 RNG_IRQn = 80, /*!< RNG global interrupt */
159 FPU_IRQn = 81, /*!< FPU global interrupt */
160 UART7_IRQn = 82, /*!< UART7 global interrupt */
161 UART8_IRQn = 83, /*!< UART8 global interrupt */
162 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
163 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
164 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
165 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
166 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
167 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
168 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
169 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
170 QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
171 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
172 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
173 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
174 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
175 SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
176 DFSDM1_FLT0_IRQn = 99, /*!< DFSDM1 Filter 0 global Interrupt */
177 DFSDM1_FLT1_IRQn = 100, /*!< DFSDM1 Filter 1 global Interrupt */
178 DFSDM1_FLT2_IRQn = 101, /*!< DFSDM1 Filter 2 global Interrupt */
179 DFSDM1_FLT3_IRQn = 102, /*!< DFSDM1 Filter 3 global Interrupt */
180 SDMMC2_IRQn = 103, /*!< SDMMC2 global Interrupt */
181 CAN3_TX_IRQn = 104, /*!< CAN3 TX Interrupt */
182 CAN3_RX0_IRQn = 105, /*!< CAN3 RX0 Interrupt */
183 CAN3_RX1_IRQn = 106, /*!< CAN3 RX1 Interrupt */
184 CAN3_SCE_IRQn = 107, /*!< CAN3 SCE Interrupt */
185 JPEG_IRQn = 108, /*!< JPEG global Interrupt */
186 MDIOS_IRQn = 109 /*!< MDIO Slave global Interrupt */
187} IRQn_Type;
188
189/**
190 * @}
191 */
192
193/**
194 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
195 */
196#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
197#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
198#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
199#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
200#define __FPU_PRESENT 1 /*!< FPU present */
201#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
202#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
203#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
204
205
206#include "system_stm32f7xx.h"
207#include <stdint.h>
208
209/** @addtogroup Peripheral_registers_structures
210 * @{
211 */
212
213/**
214 * @brief Analog to Digital Converter
215 */
216
217typedef struct
218{
219 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
220 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
221 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
222 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
223 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
224 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
225 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
226 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
227 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
228 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
229 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
230 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
231 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
232 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
233 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
234 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
235 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
236 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
237 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
238 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
239} ADC_TypeDef;
240
241typedef struct
242{
243 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
244 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
245 __IO uint32_t CDR; /*!< ADC common regular data register for dual
246 AND triple modes, Address offset: ADC1 base address + 0x308 */
247} ADC_Common_TypeDef;
248
249
250/**
251 * @brief Controller Area Network TxMailBox
252 */
253
254typedef struct
255{
256 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
257 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
258 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
259 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
260} CAN_TxMailBox_TypeDef;
261
262/**
263 * @brief Controller Area Network FIFOMailBox
264 */
265
266typedef struct
267{
268 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
269 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
270 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
271 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
272} CAN_FIFOMailBox_TypeDef;
273
274/**
275 * @brief Controller Area Network FilterRegister
276 */
277
278typedef struct
279{
280 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
281 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
282} CAN_FilterRegister_TypeDef;
283
284/**
285 * @brief Controller Area Network
286 */
287
288typedef struct
289{
290 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
291 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
292 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
293 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
294 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
295 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
296 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
297 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
298 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
299 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
300 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
301 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
302 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
303 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
304 uint32_t RESERVED2; /*!< Reserved, 0x208 */
305 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
306 uint32_t RESERVED3; /*!< Reserved, 0x210 */
307 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
308 uint32_t RESERVED4; /*!< Reserved, 0x218 */
309 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
310 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
311 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
312} CAN_TypeDef;
313
314/**
315 * @brief HDMI-CEC
316 */
317
318typedef struct
319{
320 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
321 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
322 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
323 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
324 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
325 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
326}CEC_TypeDef;
327
328/**
329 * @brief CRC calculation unit
330 */
331
332typedef struct
333{
334 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
335 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
336 uint8_t RESERVED0; /*!< Reserved, 0x05 */
337 uint16_t RESERVED1; /*!< Reserved, 0x06 */
338 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
339 uint32_t RESERVED2; /*!< Reserved, 0x0C */
340 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
341 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
342} CRC_TypeDef;
343
344/**
345 * @brief Digital to Analog Converter
346 */
347
348typedef struct
349{
350 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
351 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
352 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
353 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
354 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
355 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
356 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
357 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
358 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
359 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
360 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
361 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
362 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
363 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
364} DAC_TypeDef;
365
366/**
367 * @brief DFSDM module registers
368 */
369typedef struct
370{
371 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
372 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
373 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
374 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
375 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
376 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
377 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
378 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
379 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
380 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
381 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
382 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
383 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
384 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
385 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
386} DFSDM_Filter_TypeDef;
387
388/**
389 * @brief DFSDM channel configuration registers
390 */
391typedef struct
392{
393 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
394 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
395 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
396 short circuit detector register, Address offset: 0x08 */
397 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
398 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
399} DFSDM_Channel_TypeDef;
400
401/**
402 * @brief Debug MCU
403 */
404
405typedef struct
406{
407 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
408 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
409 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
410 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
411}DBGMCU_TypeDef;
412
413/**
414 * @brief DCMI
415 */
416
417typedef struct
418{
419 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
420 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
421 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
422 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
423 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
424 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
425 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
426 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
427 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
428 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
429 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
430} DCMI_TypeDef;
431
432/**
433 * @brief DMA Controller
434 */
435
436typedef struct
437{
438 __IO uint32_t CR; /*!< DMA stream x configuration register */
439 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
440 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
441 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
442 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
443 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
444} DMA_Stream_TypeDef;
445
446typedef struct
447{
448 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
449 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
450 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
451 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
452} DMA_TypeDef;
453
454/**
455 * @brief DMA2D Controller
456 */
457
458typedef struct
459{
460 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
461 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
462 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
463 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
464 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
465 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
466 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
467 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
468 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
469 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
470 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
471 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
472 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
473 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
474 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
475 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
476 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
477 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
478 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
479 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
480 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
481 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
482 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
483} DMA2D_TypeDef;
484
485
486/**
487 * @brief Ethernet MAC
488 */
489
490typedef struct
491{
492 __IO uint32_t MACCR;
493 __IO uint32_t MACFFR;
494 __IO uint32_t MACHTHR;
495 __IO uint32_t MACHTLR;
496 __IO uint32_t MACMIIAR;
497 __IO uint32_t MACMIIDR;
498 __IO uint32_t MACFCR;
499 __IO uint32_t MACVLANTR; /* 8 */
500 uint32_t RESERVED0[2];
501 __IO uint32_t MACRWUFFR; /* 11 */
502 __IO uint32_t MACPMTCSR;
503 uint32_t RESERVED1;
504 __IO uint32_t MACDBGR;
505 __IO uint32_t MACSR; /* 15 */
506 __IO uint32_t MACIMR;
507 __IO uint32_t MACA0HR;
508 __IO uint32_t MACA0LR;
509 __IO uint32_t MACA1HR;
510 __IO uint32_t MACA1LR;
511 __IO uint32_t MACA2HR;
512 __IO uint32_t MACA2LR;
513 __IO uint32_t MACA3HR;
514 __IO uint32_t MACA3LR; /* 24 */
515 uint32_t RESERVED2[40];
516 __IO uint32_t MMCCR; /* 65 */
517 __IO uint32_t MMCRIR;
518 __IO uint32_t MMCTIR;
519 __IO uint32_t MMCRIMR;
520 __IO uint32_t MMCTIMR; /* 69 */
521 uint32_t RESERVED3[14];
522 __IO uint32_t MMCTGFSCCR; /* 84 */
523 __IO uint32_t MMCTGFMSCCR;
524 uint32_t RESERVED4[5];
525 __IO uint32_t MMCTGFCR;
526 uint32_t RESERVED5[10];
527 __IO uint32_t MMCRFCECR;
528 __IO uint32_t MMCRFAECR;
529 uint32_t RESERVED6[10];
530 __IO uint32_t MMCRGUFCR;
531 uint32_t RESERVED7[334];
532 __IO uint32_t PTPTSCR;
533 __IO uint32_t PTPSSIR;
534 __IO uint32_t PTPTSHR;
535 __IO uint32_t PTPTSLR;
536 __IO uint32_t PTPTSHUR;
537 __IO uint32_t PTPTSLUR;
538 __IO uint32_t PTPTSAR;
539 __IO uint32_t PTPTTHR;
540 __IO uint32_t PTPTTLR;
541 __IO uint32_t RESERVED8;
542 __IO uint32_t PTPTSSR;
543 uint32_t RESERVED9[565];
544 __IO uint32_t DMABMR;
545 __IO uint32_t DMATPDR;
546 __IO uint32_t DMARPDR;
547 __IO uint32_t DMARDLAR;
548 __IO uint32_t DMATDLAR;
549 __IO uint32_t DMASR;
550 __IO uint32_t DMAOMR;
551 __IO uint32_t DMAIER;
552 __IO uint32_t DMAMFBOCR;
553 __IO uint32_t DMARSWTR;
554 uint32_t RESERVED10[8];
555 __IO uint32_t DMACHTDR;
556 __IO uint32_t DMACHRDR;
557 __IO uint32_t DMACHTBAR;
558 __IO uint32_t DMACHRBAR;
559} ETH_TypeDef;
560
561/**
562 * @brief External Interrupt/Event Controller
563 */
564
565typedef struct
566{
567 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
568 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
569 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
570 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
571 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
572 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
573} EXTI_TypeDef;
574
575/**
576 * @brief FLASH Registers
577 */
578
579typedef struct
580{
581 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
582 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
583 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
584 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
585 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
586 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
587 __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */
588} FLASH_TypeDef;
589
590
591
592/**
593 * @brief Flexible Memory Controller
594 */
595
596typedef struct
597{
598 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
599} FMC_Bank1_TypeDef;
600
601/**
602 * @brief Flexible Memory Controller Bank1E
603 */
604
605typedef struct
606{
607 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
608} FMC_Bank1E_TypeDef;
609
610/**
611 * @brief Flexible Memory Controller Bank3
612 */
613
614typedef struct
615{
616 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
617 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
618 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
619 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
620 uint32_t RESERVED0; /*!< Reserved, 0x90 */
621 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
622} FMC_Bank3_TypeDef;
623
624/**
625 * @brief Flexible Memory Controller Bank5_6
626 */
627
628typedef struct
629{
630 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
631 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
632 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
633 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
634 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
635} FMC_Bank5_6_TypeDef;
636
637
638/**
639 * @brief General Purpose I/O
640 */
641
642typedef struct
643{
644 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
645 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
646 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
647 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
648 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
649 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
650 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
651 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
652 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
653} GPIO_TypeDef;
654
655/**
656 * @brief System configuration controller
657 */
658
659typedef struct
660{
661 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
662 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
663 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
664 uint32_t RESERVED; /*!< Reserved, 0x18 */
665 __IO uint32_t CBR; /*!< SYSCFG Class B register, Address offset: 0x1C */
666 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
667} SYSCFG_TypeDef;
668
669/**
670 * @brief Inter-integrated Circuit Interface
671 */
672
673typedef struct
674{
675 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
676 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
677 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
678 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
679 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
680 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
681 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
682 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
683 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
684 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
685 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
686} I2C_TypeDef;
687
688/**
689 * @brief Independent WATCHDOG
690 */
691
692typedef struct
693{
694 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
695 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
696 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
697 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
698 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
699} IWDG_TypeDef;
700
701
702/**
703 * @brief LCD-TFT Display Controller
704 */
705
706typedef struct
707{
708 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
709 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
710 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
711 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
712 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
713 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
714 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
715 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
716 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
717 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
718 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
719 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
720 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
721 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
722 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
723 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
724 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
725} LTDC_TypeDef;
726
727/**
728 * @brief LCD-TFT Display layer x Controller
729 */
730
731typedef struct
732{
733 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
734 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
735 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
736 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
737 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
738 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
739 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
740 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
741 uint32_t RESERVED0[2]; /*!< Reserved */
742 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
743 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
744 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
745 uint32_t RESERVED1[3]; /*!< Reserved */
746 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
747
748} LTDC_Layer_TypeDef;
749
750/**
751 * @brief Power Control
752 */
753
754typedef struct
755{
756 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
757 __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */
758 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
759 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */
760} PWR_TypeDef;
761
762
763/**
764 * @brief Reset and Clock Control
765 */
766
767typedef struct
768{
769 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
770 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
771 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
772 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
773 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
774 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
775 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
776 uint32_t RESERVED0; /*!< Reserved, 0x1C */
777 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
778 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
779 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
780 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
781 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
782 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
783 uint32_t RESERVED2; /*!< Reserved, 0x3C */
784 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
785 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
786 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
787 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
788 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
789 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
790 uint32_t RESERVED4; /*!< Reserved, 0x5C */
791 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
792 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
793 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
794 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
795 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
796 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
797 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
798 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
799 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
800 __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */
801 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */
802
803} RCC_TypeDef;
804
805/**
806 * @brief Real-Time Clock
807 */
808
809typedef struct
810{
811 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
812 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
813 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
814 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
815 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
816 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
817 uint32_t reserved; /*!< Reserved */
818 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
819 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
820 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
821 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
822 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
823 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
824 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
825 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
826 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
827 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
828 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
829 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
830 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
831 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
832 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
833 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
834 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
835 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
836 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
837 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
838 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
839 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
840 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
841 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
842 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
843 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
844 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
845 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
846 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
847 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
848 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
849 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
850 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
851 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
852 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
853 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
854 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
855 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
856 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
857 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
858 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
859 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
860 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
861 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
862 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
863} RTC_TypeDef;
864
865
866/**
867 * @brief Serial Audio Interface
868 */
869
870typedef struct
871{
872 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
873} SAI_TypeDef;
874
875typedef struct
876{
877 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
878 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
879 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
880 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
881 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
882 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
883 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
884 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
885} SAI_Block_TypeDef;
886
887/**
888 * @brief SPDIF-RX Interface
889 */
890
891typedef struct
892{
893 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
894 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
895 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
896 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
897 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
898 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
899 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
900} SPDIFRX_TypeDef;
901
902/**
903 * @brief SD host Interface
904 */
905
906typedef struct
907{
908 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
909 __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */
910 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
911 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
912 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
913 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
914 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
915 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
916 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
917 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
918 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
919 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
920 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
921 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
922 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
923 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
924 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
925 __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
926 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
927 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
928} SDMMC_TypeDef;
929
930/**
931 * @brief Serial Peripheral Interface
932 */
933
934typedef struct
935{
936 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
937 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
938 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
939 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
940 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
941 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
942 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
943 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
944 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
945} SPI_TypeDef;
946
947/**
948 * @brief QUAD Serial Peripheral Interface
949 */
950
951typedef struct
952{
953 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
954 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
955 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
956 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
957 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
958 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
959 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
960 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
961 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
962 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
963 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
964 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
965 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
966} QUADSPI_TypeDef;
967
968/**
969 * @brief TIM
970 */
971
972typedef struct
973{
974 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
975 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
976 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
977 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
978 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
979 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
980 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
981 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
982 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
983 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
984 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
985 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
986 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
987 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
988 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
989 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
990 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
991 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
992 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
993 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
994 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
995 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
996 __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */
997 __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */
998 __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */
999 __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */
1000
1001} TIM_TypeDef;
1002
1003/**
1004 * @brief LPTIMIMER
1005 */
1006typedef struct
1007{
1008 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
1009 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
1010 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
1011 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
1012 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
1013 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
1014 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
1015 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
1016} LPTIM_TypeDef;
1017
1018
1019/**
1020 * @brief Universal Synchronous Asynchronous Receiver Transmitter
1021 */
1022
1023typedef struct
1024{
1025 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
1026 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
1027 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
1028 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
1029 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
1030 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
1031 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
1032 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
1033 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
1034 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
1035 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
1036} USART_TypeDef;
1037
1038
1039/**
1040 * @brief Window WATCHDOG
1041 */
1042
1043typedef struct
1044{
1045 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
1046 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
1047 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
1048} WWDG_TypeDef;
1049
1050
1051/**
1052 * @brief RNG
1053 */
1054
1055typedef struct
1056{
1057 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
1058 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
1059 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
1060} RNG_TypeDef;
1061
1062/**
1063 * @}
1064 */
1065
1066/**
1067 * @brief USB_OTG_Core_Registers
1068 */
1069typedef struct
1070{
1071 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
1072 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
1073 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
1074 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
1075 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
1076 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
1077 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
1078 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
1079 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
1080 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
1081 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
1082 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
1083 uint32_t Reserved30[2]; /*!< Reserved 030h */
1084 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
1085 __IO uint32_t CID; /*!< User ID Register 03Ch */
1086 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
1087 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
1088 uint32_t Reserved6; /*!< Reserved 050h */
1089 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
1090 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
1091 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
1092 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
1093 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
1094 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
1095 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
1096} USB_OTG_GlobalTypeDef;
1097
1098
1099/**
1100 * @brief USB_OTG_device_Registers
1101 */
1102typedef struct
1103{
1104 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
1105 __IO uint32_t DCTL; /*!< dev Control Register 804h */
1106 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
1107 uint32_t Reserved0C; /*!< Reserved 80Ch */
1108 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
1109 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
1110 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
1111 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
1112 uint32_t Reserved20; /*!< Reserved 820h */
1113 uint32_t Reserved9; /*!< Reserved 824h */
1114 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
1115 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
1116 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
1117 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
1118 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
1119 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
1120 uint32_t Reserved40; /*!< dedicated EP mask 840h */
1121 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
1122 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
1123 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
1124} USB_OTG_DeviceTypeDef;
1125
1126
1127/**
1128 * @brief USB_OTG_IN_Endpoint-Specific_Register
1129 */
1130typedef struct
1131{
1132 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
1133 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
1134 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
1135 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
1136 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
1137 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
1138 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
1139 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
1140} USB_OTG_INEndpointTypeDef;
1141
1142
1143/**
1144 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1145 */
1146typedef struct
1147{
1148 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
1149 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
1150 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
1151 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
1152 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
1153 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
1154 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
1155} USB_OTG_OUTEndpointTypeDef;
1156
1157
1158/**
1159 * @brief USB_OTG_Host_Mode_Register_Structures
1160 */
1161typedef struct
1162{
1163 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
1164 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
1165 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
1166 uint32_t Reserved40C; /*!< Reserved 40Ch */
1167 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
1168 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
1169 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
1170} USB_OTG_HostTypeDef;
1171
1172/**
1173 * @brief USB_OTG_Host_Channel_Specific_Registers
1174 */
1175typedef struct
1176{
1177 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
1178 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
1179 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
1180 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
1181 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
1182 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
1183 uint32_t Reserved[2]; /*!< Reserved */
1184} USB_OTG_HostChannelTypeDef;
1185/**
1186 * @}
1187 */
1188
1189/**
1190 * @brief JPEG Codec
1191 */
1192typedef struct
1193{
1194 __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
1195 __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
1196 __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
1197 __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
1198 __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
1199 __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
1200 __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
1201 __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
1202 uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
1203 __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
1204 __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
1205 __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
1206 uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
1207 __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
1208 __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
1209 uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
1210 __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
1211 __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
1212 __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
1213 __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
1214 __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
1215 __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
1216 __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
1217 __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
1218 uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
1219 __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encoder, AC Huffman table 0, Address offset: 500h-65Ch */
1220 __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encoder, AC Huffman table 1, Address offset: 660h-7BCh */
1221 __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encoder, DC Huffman table 0, Address offset: 7C0h-7DCh */
1222 __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encoder, DC Huffman table 1, Address offset: 7E0h-7FCh */
1223
1224} JPEG_TypeDef;
1225
1226/**
1227 * @brief MDIOS
1228 */
1229
1230typedef struct
1231{
1232 __IO uint32_t CR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 00h */
1233 __IO uint32_t WRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 04h */
1234 __IO uint32_t CWRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 08h */
1235 __IO uint32_t RDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 0Ch */
1236 __IO uint32_t CRDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 10h */
1237 __IO uint32_t SR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 14h */
1238 __IO uint32_t CLRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 18h */
1239 uint32_t RESERVED0[57]; /* Reserved Address offset: 1Ch */
1240 __IO uint32_t DINR0; /*!< MDIOS Input Data Register (MDIOS_DINR0), Address offset: 100h */
1241 __IO uint32_t DINR1; /*!< MDIOS Input Data Register (MDIOS_DINR1), Address offset: 104h */
1242 __IO uint32_t DINR2; /*!< MDIOS Input Data Register (MDIOS_DINR2), Address offset: 108h */
1243 __IO uint32_t DINR3; /*!< MDIOS Input Data Register (MDIOS_DINR3), Address offset: 10Ch */
1244 __IO uint32_t DINR4; /*!< MDIOS Input Data Register (MDIOS_DINR4), Address offset: 110h */
1245 __IO uint32_t DINR5; /*!< MDIOS Input Data Register (MDIOS_DINR5), Address offset: 114h */
1246 __IO uint32_t DINR6; /*!< MDIOS Input Data Register (MDIOS_DINR6), Address offset: 118h */
1247 __IO uint32_t DINR7; /*!< MDIOS Input Data Register (MDIOS_DINR7), Address offset: 11Ch */
1248 __IO uint32_t DINR8; /*!< MDIOS Input Data Register (MDIOS_DINR8), Address offset: 120h */
1249 __IO uint32_t DINR9; /*!< MDIOS Input Data Register (MDIOS_DINR9), Address offset: 124h */
1250 __IO uint32_t DINR10; /*!< MDIOS Input Data Register (MDIOS_DINR10), Address offset: 128h */
1251 __IO uint32_t DINR11; /*!< MDIOS Input Data Register (MDIOS_DINR11), Address offset: 12Ch */
1252 __IO uint32_t DINR12; /*!< MDIOS Input Data Register (MDIOS_DINR12), Address offset: 130h */
1253 __IO uint32_t DINR13; /*!< MDIOS Input Data Register (MDIOS_DINR13), Address offset: 134h */
1254 __IO uint32_t DINR14; /*!< MDIOS Input Data Register (MDIOS_DINR14), Address offset: 138h */
1255 __IO uint32_t DINR15; /*!< MDIOS Input Data Register (MDIOS_DINR15), Address offset: 13Ch */
1256 __IO uint32_t DINR16; /*!< MDIOS Input Data Register (MDIOS_DINR16), Address offset: 140h */
1257 __IO uint32_t DINR17; /*!< MDIOS Input Data Register (MDIOS_DINR17), Address offset: 144h */
1258 __IO uint32_t DINR18; /*!< MDIOS Input Data Register (MDIOS_DINR18), Address offset: 148h */
1259 __IO uint32_t DINR19; /*!< MDIOS Input Data Register (MDIOS_DINR19), Address offset: 14Ch */
1260 __IO uint32_t DINR20; /*!< MDIOS Input Data Register (MDIOS_DINR20), Address offset: 150h */
1261 __IO uint32_t DINR21; /*!< MDIOS Input Data Register (MDIOS_DINR21), Address offset: 154h */
1262 __IO uint32_t DINR22; /*!< MDIOS Input Data Register (MDIOS_DINR22), Address offset: 158h */
1263 __IO uint32_t DINR23; /*!< MDIOS Input Data Register (MDIOS_DINR23), Address offset: 15Ch */
1264 __IO uint32_t DINR24; /*!< MDIOS Input Data Register (MDIOS_DINR24), Address offset: 160h */
1265 __IO uint32_t DINR25; /*!< MDIOS Input Data Register (MDIOS_DINR25), Address offset: 164h */
1266 __IO uint32_t DINR26; /*!< MDIOS Input Data Register (MDIOS_DINR26), Address offset: 168h */
1267 __IO uint32_t DINR27; /*!< MDIOS Input Data Register (MDIOS_DINR27), Address offset: 16Ch */
1268 __IO uint32_t DINR28; /*!< MDIOS Input Data Register (MDIOS_DINR28), Address offset: 170h */
1269 __IO uint32_t DINR29; /*!< MDIOS Input Data Register (MDIOS_DINR29), Address offset: 174h */
1270 __IO uint32_t DINR30; /*!< MDIOS Input Data Register (MDIOS_DINR30), Address offset: 178h */
1271 __IO uint32_t DINR31; /*!< MDIOS Input Data Register (MDIOS_DINR31), Address offset: 17Ch */
1272 __IO uint32_t DOUTR0; /*!< MDIOS Output Data Register (MDIOS_DOUTR0), Address offset: 180h */
1273 __IO uint32_t DOUTR1; /*!< MDIOS Output Data Register (MDIOS_DOUTR1), Address offset: 184h */
1274 __IO uint32_t DOUTR2; /*!< MDIOS Output Data Register (MDIOS_DOUTR2), Address offset: 188h */
1275 __IO uint32_t DOUTR3; /*!< MDIOS Output Data Register (MDIOS_DOUTR3), Address offset: 18Ch */
1276 __IO uint32_t DOUTR4; /*!< MDIOS Output Data Register (MDIOS_DOUTR4), Address offset: 190h */
1277 __IO uint32_t DOUTR5; /*!< MDIOS Output Data Register (MDIOS_DOUTR5), Address offset: 194h */
1278 __IO uint32_t DOUTR6; /*!< MDIOS Output Data Register (MDIOS_DOUTR6), Address offset: 198h */
1279 __IO uint32_t DOUTR7; /*!< MDIOS Output Data Register (MDIOS_DOUTR7), Address offset: 19Ch */
1280 __IO uint32_t DOUTR8; /*!< MDIOS Output Data Register (MDIOS_DOUTR8), Address offset: 1A0h */
1281 __IO uint32_t DOUTR9; /*!< MDIOS Output Data Register (MDIOS_DOUTR9), Address offset: 1A4h */
1282 __IO uint32_t DOUTR10; /*!< MDIOS Output Data Register (MDIOS_DOUTR10), Address offset: 1A8h */
1283 __IO uint32_t DOUTR11; /*!< MDIOS Output Data Register (MDIOS_DOUTR11), Address offset: 1ACh */
1284 __IO uint32_t DOUTR12; /*!< MDIOS Output Data Register (MDIOS_DOUTR12), Address offset: 1B0h */
1285 __IO uint32_t DOUTR13; /*!< MDIOS Output Data Register (MDIOS_DOUTR13), Address offset: 1B4h */
1286 __IO uint32_t DOUTR14; /*!< MDIOS Output Data Register (MDIOS_DOUTR14), Address offset: 1B8h */
1287 __IO uint32_t DOUTR15; /*!< MDIOS Output Data Register (MDIOS_DOUTR15), Address offset: 1BCh */
1288 __IO uint32_t DOUTR16; /*!< MDIOS Output Data Register (MDIOS_DOUTR16), Address offset: 1C0h */
1289 __IO uint32_t DOUTR17; /*!< MDIOS Output Data Register (MDIOS_DOUTR17), Address offset: 1C4h */
1290 __IO uint32_t DOUTR18; /*!< MDIOS Output Data Register (MDIOS_DOUTR18), Address offset: 1C8h */
1291 __IO uint32_t DOUTR19; /*!< MDIOS Output Data Register (MDIOS_DOUTR19), Address offset: 1CCh */
1292 __IO uint32_t DOUTR20; /*!< MDIOS Output Data Register (MDIOS_DOUTR20), Address offset: 1D0h */
1293 __IO uint32_t DOUTR21; /*!< MDIOS Output Data Register (MDIOS_DOUTR21), Address offset: 1D4h */
1294 __IO uint32_t DOUTR22; /*!< MDIOS Output Data Register (MDIOS_DOUTR22), Address offset: 1D8h */
1295 __IO uint32_t DOUTR23; /*!< MDIOS Output Data Register (MDIOS_DOUTR23), Address offset: 1DCh */
1296 __IO uint32_t DOUTR24; /*!< MDIOS Output Data Register (MDIOS_DOUTR24), Address offset: 1E0h */
1297 __IO uint32_t DOUTR25; /*!< MDIOS Output Data Register (MDIOS_DOUTR25), Address offset: 1E4h */
1298 __IO uint32_t DOUTR26; /*!< MDIOS Output Data Register (MDIOS_DOUTR26), Address offset: 1E8h */
1299 __IO uint32_t DOUTR27; /*!< MDIOS Output Data Register (MDIOS_DOUTR27), Address offset: 1ECh */
1300 __IO uint32_t DOUTR28; /*!< MDIOS Output Data Register (MDIOS_DOUTR28), Address offset: 1F0h */
1301 __IO uint32_t DOUTR29; /*!< MDIOS Output Data Register (MDIOS_DOUTR29), Address offset: 1F4h */
1302 __IO uint32_t DOUTR30; /*!< MDIOS Output Data Register (MDIOS_DOUTR30), Address offset: 1F8h */
1303 __IO uint32_t DOUTR31; /*!< MDIOS Output Data Register (MDIOS_DOUTR31), Address offset: 1FCh */
1304} MDIOS_TypeDef;
1305
1306
1307/** @addtogroup Peripheral_memory_map
1308 * @{
1309 */
1310#define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */
1311#define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM */
1312#define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
1313#define RAMDTCM_BASE 0x20000000U /*!< Base address of : 128KB system data RAM accessible over DTCM */
1314#define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */
1315#define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */
1316#define QSPI_BASE 0x90000000U /*!< Base address of : QSPI memories accessible over AXI */
1317#define FMC_R_BASE 0xA0000000U /*!< Base address of : FMC Control registers */
1318#define QSPI_R_BASE 0xA0001000U /*!< Base address of : QSPI Control registers */
1319#define SRAM1_BASE 0x20020000U /*!< Base address of : 368KB RAM1 accessible over AXI/AHB */
1320#define SRAM2_BASE 0x2007C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
1321#define FLASH_END 0x081FFFFFU /*!< FLASH end address */
1322#define FLASH_OTP_BASE 0x1FF0F000U /*!< Base address of : (up to 1024 Bytes) embedded FLASH OTP Area */
1323#define FLASH_OTP_END 0x1FF0F41FU /*!< End address of : (up to 1024 Bytes) embedded FLASH OTP Area */
1324
1325/* Legacy define */
1326#define FLASH_BASE FLASHAXI_BASE
1327
1328/*!< Peripheral memory map */
1329#define APB1PERIPH_BASE PERIPH_BASE
1330#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1331#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1332#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
1333
1334/*!< APB1 peripherals */
1335#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1336#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1337#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1338#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1339#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1340#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1341#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
1342#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
1343#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
1344#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
1345#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1346#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1347#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1348#define CAN3_BASE (APB1PERIPH_BASE + 0x3400U)
1349#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1350#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1351#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)
1352#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1353#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1354#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1355#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1356#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1357#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1358#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1359#define I2C4_BASE (APB1PERIPH_BASE + 0x6000U)
1360#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1361#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
1362#define CEC_BASE (APB1PERIPH_BASE + 0x6C00U)
1363#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1364#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1365#define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
1366#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
1367
1368/*!< APB2 peripherals */
1369#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
1370#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
1371#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
1372#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
1373#define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00U)
1374#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
1375#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
1376#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
1377#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
1378#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U)
1379#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1380#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
1381#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
1382#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
1383#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
1384#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
1385#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
1386#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
1387#define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
1388#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
1389#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
1390#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
1391#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
1392#define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
1393#define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
1394#define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
1395#define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
1396#define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
1397#define DFSDM1_BASE (APB2PERIPH_BASE + 0x7400U)
1398#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)
1399#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)
1400#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)
1401#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)
1402#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80U)
1403#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0U)
1404#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0U)
1405#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0U)
1406#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)
1407#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)
1408#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200U)
1409#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280U)
1410#define MDIOS_BASE (APB2PERIPH_BASE + 0x7800U)
1411/*!< AHB1 peripherals */
1412#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
1413#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1414#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1415#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1416#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1417#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1418#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1419#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1420#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
1421#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
1422#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
1423#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1424#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1425#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1426#define UID_BASE 0x1FF0F420U /*!< Unique device ID register base address */
1427#define FLASHSIZE_BASE 0x1FF0F442U /*!< FLASH Size register base address */
1428#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
1429/* Legacy define */
1430#define PACKAGESIZE_BASE PACKAGE_BASE
1431
1432#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1433#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1434#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1435#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1436#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1437#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1438#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1439#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1440#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1441#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1442#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1443#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1444#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1445#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1446#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1447#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1448#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1449#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1450#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
1451#define ETH_MAC_BASE (ETH_BASE)
1452#define ETH_MMC_BASE (ETH_BASE + 0x0100U)
1453#define ETH_PTP_BASE (ETH_BASE + 0x0700U)
1454#define ETH_DMA_BASE (ETH_BASE + 0x1000U)
1455#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
1456/*!< AHB2 peripherals */
1457#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
1458#define JPEG_BASE (AHB2PERIPH_BASE + 0x51000U)
1459#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1460/*!< FMC Bankx registers base address */
1461#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1462#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1463#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
1464#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
1465
1466/* Debug MCU registers base address */
1467#define DBGMCU_BASE 0xE0042000U
1468
1469/*!< USB registers base address */
1470#define USB_OTG_HS_PERIPH_BASE 0x40040000U
1471#define USB_OTG_FS_PERIPH_BASE 0x50000000U
1472
1473#define USB_OTG_GLOBAL_BASE 0x000U
1474#define USB_OTG_DEVICE_BASE 0x800U
1475#define USB_OTG_IN_ENDPOINT_BASE 0x900U
1476#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1477#define USB_OTG_EP_REG_SIZE 0x20U
1478#define USB_OTG_HOST_BASE 0x400U
1479#define USB_OTG_HOST_PORT_BASE 0x440U
1480#define USB_OTG_HOST_CHANNEL_BASE 0x500U
1481#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1482#define USB_OTG_PCGCCTL_BASE 0xE00U
1483#define USB_OTG_FIFO_BASE 0x1000U
1484#define USB_OTG_FIFO_SIZE 0x1000U
1485
1486/**
1487 * @}
1488 */
1489
1490/** @addtogroup Peripheral_declaration
1491 * @{
1492 */
1493#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1494#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1495#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1496#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1497#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1498#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1499#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1500#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1501#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1502#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1503#define RTC ((RTC_TypeDef *) RTC_BASE)
1504#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1505#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1506#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1507#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1508#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
1509#define USART2 ((USART_TypeDef *) USART2_BASE)
1510#define USART3 ((USART_TypeDef *) USART3_BASE)
1511#define UART4 ((USART_TypeDef *) UART4_BASE)
1512#define UART5 ((USART_TypeDef *) UART5_BASE)
1513#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1514#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1515#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1516#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
1517#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1518#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1519#define CEC ((CEC_TypeDef *) CEC_BASE)
1520#define PWR ((PWR_TypeDef *) PWR_BASE)
1521#define DAC1 ((DAC_TypeDef *) DAC_BASE)
1522#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1523#define UART7 ((USART_TypeDef *) UART7_BASE)
1524#define UART8 ((USART_TypeDef *) UART8_BASE)
1525#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1526#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1527#define USART1 ((USART_TypeDef *) USART1_BASE)
1528#define USART6 ((USART_TypeDef *) USART6_BASE)
1529#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1530#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1531#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1532#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1533#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
1534#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1535#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1536#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1537#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1538#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1539#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1540#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1541#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1542#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1543#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1544#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1545#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1546#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1547#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1548#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1549#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1550#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
1551#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1552#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1553#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1554#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1555#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1556#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1557#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1558#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1559#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1560#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1561#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1562#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1563#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1564#define CRC ((CRC_TypeDef *) CRC_BASE)
1565#define RCC ((RCC_TypeDef *) RCC_BASE)
1566#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1567#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1568#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1569#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1570#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1571#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1572#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1573#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1574#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1575#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1576#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1577#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1578#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1579#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1580#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1581#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1582#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1583#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1584#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1585#define ETH ((ETH_TypeDef *) ETH_BASE)
1586#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1587#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1588#define RNG ((RNG_TypeDef *) RNG_BASE)
1589#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1590#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1591#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1592#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1593#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1594#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1595#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1596#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1597#define CAN3 ((CAN_TypeDef *) CAN3_BASE)
1598#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
1599#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
1600#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
1601#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
1602#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
1603#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
1604#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
1605#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
1606#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
1607#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
1608#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
1609#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
1610#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
1611#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
1612#define JPEG ((JPEG_TypeDef *) JPEG_BASE)
1613
1614/**
1615 * @}
1616 */
1617
1618/** @addtogroup Exported_constants
1619 * @{
1620 */
1621
1622 /** @addtogroup Peripheral_Registers_Bits_Definition
1623 * @{
1624 */
1625
1626/******************************************************************************/
1627/* Peripheral Registers_Bits_Definition */
1628/******************************************************************************/
1629
1630/******************************************************************************/
1631/* */
1632/* Analog to Digital Converter */
1633/* */
1634/******************************************************************************/
1635/******************** Bit definition for ADC_SR register ********************/
1636#define ADC_SR_AWD_Pos (0U)
1637#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
1638#define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
1639#define ADC_SR_EOC_Pos (1U)
1640#define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
1641#define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
1642#define ADC_SR_JEOC_Pos (2U)
1643#define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
1644#define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
1645#define ADC_SR_JSTRT_Pos (3U)
1646#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
1647#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
1648#define ADC_SR_STRT_Pos (4U)
1649#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
1650#define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
1651#define ADC_SR_OVR_Pos (5U)
1652#define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
1653#define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
1654
1655/******************* Bit definition for ADC_CR1 register ********************/
1656#define ADC_CR1_AWDCH_Pos (0U)
1657#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
1658#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1659#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
1660#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
1661#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
1662#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
1663#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
1664#define ADC_CR1_EOCIE_Pos (5U)
1665#define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
1666#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
1667#define ADC_CR1_AWDIE_Pos (6U)
1668#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
1669#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
1670#define ADC_CR1_JEOCIE_Pos (7U)
1671#define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
1672#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
1673#define ADC_CR1_SCAN_Pos (8U)
1674#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
1675#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
1676#define ADC_CR1_AWDSGL_Pos (9U)
1677#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
1678#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
1679#define ADC_CR1_JAUTO_Pos (10U)
1680#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
1681#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
1682#define ADC_CR1_DISCEN_Pos (11U)
1683#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
1684#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
1685#define ADC_CR1_JDISCEN_Pos (12U)
1686#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
1687#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
1688#define ADC_CR1_DISCNUM_Pos (13U)
1689#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
1690#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1691#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
1692#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
1693#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
1694#define ADC_CR1_JAWDEN_Pos (22U)
1695#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
1696#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
1697#define ADC_CR1_AWDEN_Pos (23U)
1698#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
1699#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
1700#define ADC_CR1_RES_Pos (24U)
1701#define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
1702#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
1703#define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
1704#define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
1705#define ADC_CR1_OVRIE_Pos (26U)
1706#define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
1707#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
1708
1709/******************* Bit definition for ADC_CR2 register ********************/
1710#define ADC_CR2_ADON_Pos (0U)
1711#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
1712#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
1713#define ADC_CR2_CONT_Pos (1U)
1714#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
1715#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
1716#define ADC_CR2_DMA_Pos (8U)
1717#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
1718#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
1719#define ADC_CR2_DDS_Pos (9U)
1720#define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
1721#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
1722#define ADC_CR2_EOCS_Pos (10U)
1723#define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
1724#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
1725#define ADC_CR2_ALIGN_Pos (11U)
1726#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
1727#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
1728#define ADC_CR2_JEXTSEL_Pos (16U)
1729#define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
1730#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1731#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
1732#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
1733#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
1734#define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
1735#define ADC_CR2_JEXTEN_Pos (20U)
1736#define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
1737#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1738#define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
1739#define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
1740#define ADC_CR2_JSWSTART_Pos (22U)
1741#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
1742#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
1743#define ADC_CR2_EXTSEL_Pos (24U)
1744#define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
1745#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1746#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
1747#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
1748#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
1749#define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
1750#define ADC_CR2_EXTEN_Pos (28U)
1751#define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
1752#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1753#define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
1754#define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
1755#define ADC_CR2_SWSTART_Pos (30U)
1756#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
1757#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
1758
1759/****************** Bit definition for ADC_SMPR1 register *******************/
1760#define ADC_SMPR1_SMP10_Pos (0U)
1761#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
1762#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1763#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
1764#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
1765#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
1766#define ADC_SMPR1_SMP11_Pos (3U)
1767#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
1768#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1769#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
1770#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
1771#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
1772#define ADC_SMPR1_SMP12_Pos (6U)
1773#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
1774#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1775#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
1776#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
1777#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
1778#define ADC_SMPR1_SMP13_Pos (9U)
1779#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
1780#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1781#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
1782#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
1783#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
1784#define ADC_SMPR1_SMP14_Pos (12U)
1785#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
1786#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1787#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
1788#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
1789#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
1790#define ADC_SMPR1_SMP15_Pos (15U)
1791#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
1792#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1793#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
1794#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
1795#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
1796#define ADC_SMPR1_SMP16_Pos (18U)
1797#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
1798#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1799#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
1800#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
1801#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
1802#define ADC_SMPR1_SMP17_Pos (21U)
1803#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
1804#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1805#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
1806#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
1807#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
1808#define ADC_SMPR1_SMP18_Pos (24U)
1809#define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
1810#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1811#define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
1812#define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
1813#define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
1814
1815/****************** Bit definition for ADC_SMPR2 register *******************/
1816#define ADC_SMPR2_SMP0_Pos (0U)
1817#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
1818#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1819#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
1820#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
1821#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
1822#define ADC_SMPR2_SMP1_Pos (3U)
1823#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
1824#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1825#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
1826#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
1827#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
1828#define ADC_SMPR2_SMP2_Pos (6U)
1829#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
1830#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1831#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
1832#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
1833#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
1834#define ADC_SMPR2_SMP3_Pos (9U)
1835#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
1836#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1837#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
1838#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
1839#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
1840#define ADC_SMPR2_SMP4_Pos (12U)
1841#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
1842#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1843#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
1844#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
1845#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
1846#define ADC_SMPR2_SMP5_Pos (15U)
1847#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
1848#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1849#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
1850#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
1851#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
1852#define ADC_SMPR2_SMP6_Pos (18U)
1853#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
1854#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1855#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
1856#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
1857#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
1858#define ADC_SMPR2_SMP7_Pos (21U)
1859#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
1860#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1861#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
1862#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
1863#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
1864#define ADC_SMPR2_SMP8_Pos (24U)
1865#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
1866#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1867#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
1868#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
1869#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
1870#define ADC_SMPR2_SMP9_Pos (27U)
1871#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
1872#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1873#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
1874#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
1875#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
1876
1877/****************** Bit definition for ADC_JOFR1 register *******************/
1878#define ADC_JOFR1_JOFFSET1_Pos (0U)
1879#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
1880#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
1881
1882/****************** Bit definition for ADC_JOFR2 register *******************/
1883#define ADC_JOFR2_JOFFSET2_Pos (0U)
1884#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
1885#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
1886
1887/****************** Bit definition for ADC_JOFR3 register *******************/
1888#define ADC_JOFR3_JOFFSET3_Pos (0U)
1889#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
1890#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
1891
1892/****************** Bit definition for ADC_JOFR4 register *******************/
1893#define ADC_JOFR4_JOFFSET4_Pos (0U)
1894#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
1895#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
1896
1897/******************* Bit definition for ADC_HTR register ********************/
1898#define ADC_HTR_HT_Pos (0U)
1899#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
1900#define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
1901
1902/******************* Bit definition for ADC_LTR register ********************/
1903#define ADC_LTR_LT_Pos (0U)
1904#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
1905#define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
1906
1907/******************* Bit definition for ADC_SQR1 register *******************/
1908#define ADC_SQR1_SQ13_Pos (0U)
1909#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
1910#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1911#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
1912#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
1913#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
1914#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
1915#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
1916#define ADC_SQR1_SQ14_Pos (5U)
1917#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
1918#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1919#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
1920#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
1921#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
1922#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
1923#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
1924#define ADC_SQR1_SQ15_Pos (10U)
1925#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
1926#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1927#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
1928#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
1929#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
1930#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
1931#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
1932#define ADC_SQR1_SQ16_Pos (15U)
1933#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
1934#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1935#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
1936#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
1937#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
1938#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
1939#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
1940#define ADC_SQR1_L_Pos (20U)
1941#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
1942#define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
1943#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
1944#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
1945#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
1946#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
1947
1948/******************* Bit definition for ADC_SQR2 register *******************/
1949#define ADC_SQR2_SQ7_Pos (0U)
1950#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
1951#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1952#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
1953#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
1954#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
1955#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
1956#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
1957#define ADC_SQR2_SQ8_Pos (5U)
1958#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
1959#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1960#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
1961#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
1962#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
1963#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
1964#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
1965#define ADC_SQR2_SQ9_Pos (10U)
1966#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
1967#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1968#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
1969#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
1970#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
1971#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
1972#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
1973#define ADC_SQR2_SQ10_Pos (15U)
1974#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
1975#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1976#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
1977#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
1978#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
1979#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
1980#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
1981#define ADC_SQR2_SQ11_Pos (20U)
1982#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
1983#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1984#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
1985#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
1986#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
1987#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
1988#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
1989#define ADC_SQR2_SQ12_Pos (25U)
1990#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
1991#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1992#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
1993#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
1994#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
1995#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
1996#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
1997
1998/******************* Bit definition for ADC_SQR3 register *******************/
1999#define ADC_SQR3_SQ1_Pos (0U)
2000#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
2001#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
2002#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
2003#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
2004#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
2005#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
2006#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
2007#define ADC_SQR3_SQ2_Pos (5U)
2008#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
2009#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
2010#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
2011#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
2012#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
2013#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
2014#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
2015#define ADC_SQR3_SQ3_Pos (10U)
2016#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
2017#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
2018#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
2019#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
2020#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
2021#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
2022#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
2023#define ADC_SQR3_SQ4_Pos (15U)
2024#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
2025#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
2026#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
2027#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
2028#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
2029#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
2030#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
2031#define ADC_SQR3_SQ5_Pos (20U)
2032#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
2033#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
2034#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
2035#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
2036#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
2037#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
2038#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
2039#define ADC_SQR3_SQ6_Pos (25U)
2040#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
2041#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
2042#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
2043#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
2044#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
2045#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
2046#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
2047
2048/******************* Bit definition for ADC_JSQR register *******************/
2049#define ADC_JSQR_JSQ1_Pos (0U)
2050#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
2051#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
2052#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
2053#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
2054#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
2055#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
2056#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
2057#define ADC_JSQR_JSQ2_Pos (5U)
2058#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
2059#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
2060#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
2061#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
2062#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
2063#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
2064#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
2065#define ADC_JSQR_JSQ3_Pos (10U)
2066#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
2067#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
2068#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
2069#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
2070#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
2071#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
2072#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
2073#define ADC_JSQR_JSQ4_Pos (15U)
2074#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
2075#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
2076#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
2077#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
2078#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
2079#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
2080#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
2081#define ADC_JSQR_JL_Pos (20U)
2082#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
2083#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
2084#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
2085#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
2086
2087/******************* Bit definition for ADC_JDR1 register *******************/
2088#define ADC_JDR1_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
2089
2090/******************* Bit definition for ADC_JDR2 register *******************/
2091#define ADC_JDR2_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
2092
2093/******************* Bit definition for ADC_JDR3 register *******************/
2094#define ADC_JDR3_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
2095
2096/******************* Bit definition for ADC_JDR4 register *******************/
2097#define ADC_JDR4_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
2098
2099/******************** Bit definition for ADC_DR register ********************/
2100#define ADC_DR_DATA_Pos (0U)
2101#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
2102#define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
2103#define ADC_DR_ADC2DATA_Pos (16U)
2104#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
2105#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
2106
2107/******************* Bit definition for ADC_CSR register ********************/
2108#define ADC_CSR_AWD1_Pos (0U)
2109#define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
2110#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
2111#define ADC_CSR_EOC1_Pos (1U)
2112#define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
2113#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
2114#define ADC_CSR_JEOC1_Pos (2U)
2115#define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
2116#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
2117#define ADC_CSR_JSTRT1_Pos (3U)
2118#define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
2119#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
2120#define ADC_CSR_STRT1_Pos (4U)
2121#define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
2122#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
2123#define ADC_CSR_OVR1_Pos (5U)
2124#define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
2125#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 Overrun flag */
2126#define ADC_CSR_AWD2_Pos (8U)
2127#define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
2128#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
2129#define ADC_CSR_EOC2_Pos (9U)
2130#define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
2131#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
2132#define ADC_CSR_JEOC2_Pos (10U)
2133#define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
2134#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
2135#define ADC_CSR_JSTRT2_Pos (11U)
2136#define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
2137#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
2138#define ADC_CSR_STRT2_Pos (12U)
2139#define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
2140#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
2141#define ADC_CSR_OVR2_Pos (13U)
2142#define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
2143#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 Overrun flag */
2144#define ADC_CSR_AWD3_Pos (16U)
2145#define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
2146#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
2147#define ADC_CSR_EOC3_Pos (17U)
2148#define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
2149#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
2150#define ADC_CSR_JEOC3_Pos (18U)
2151#define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
2152#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
2153#define ADC_CSR_JSTRT3_Pos (19U)
2154#define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
2155#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
2156#define ADC_CSR_STRT3_Pos (20U)
2157#define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
2158#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
2159#define ADC_CSR_OVR3_Pos (21U)
2160#define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
2161#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 Overrun flag */
2162
2163/* Legacy defines */
2164#define ADC_CSR_DOVR1 ADC_CSR_OVR1
2165#define ADC_CSR_DOVR2 ADC_CSR_OVR2
2166#define ADC_CSR_DOVR3 ADC_CSR_OVR3
2167
2168
2169/******************* Bit definition for ADC_CCR register ********************/
2170#define ADC_CCR_MULTI_Pos (0U)
2171#define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
2172#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
2173#define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
2174#define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
2175#define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
2176#define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
2177#define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
2178#define ADC_CCR_DELAY_Pos (8U)
2179#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
2180#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
2181#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
2182#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
2183#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
2184#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
2185#define ADC_CCR_DDS_Pos (13U)
2186#define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
2187#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
2188#define ADC_CCR_DMA_Pos (14U)
2189#define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
2190#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
2191#define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
2192#define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
2193#define ADC_CCR_ADCPRE_Pos (16U)
2194#define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
2195#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
2196#define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
2197#define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
2198#define ADC_CCR_VBATE_Pos (22U)
2199#define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
2200#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
2201#define ADC_CCR_TSVREFE_Pos (23U)
2202#define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
2203#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
2204
2205/******************* Bit definition for ADC_CDR register ********************/
2206#define ADC_CDR_DATA1_Pos (0U)
2207#define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
2208#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
2209#define ADC_CDR_DATA2_Pos (16U)
2210#define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
2211#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
2212
2213/* Legacy defines */
2214#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
2215#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
2216
2217/******************************************************************************/
2218/* */
2219/* Controller Area Network */
2220/* */
2221/******************************************************************************/
2222/*!<CAN control and status registers */
2223/******************* Bit definition for CAN_MCR register ********************/
2224#define CAN_MCR_INRQ_Pos (0U)
2225#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
2226#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
2227#define CAN_MCR_SLEEP_Pos (1U)
2228#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
2229#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
2230#define CAN_MCR_TXFP_Pos (2U)
2231#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
2232#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
2233#define CAN_MCR_RFLM_Pos (3U)
2234#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
2235#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
2236#define CAN_MCR_NART_Pos (4U)
2237#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
2238#define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
2239#define CAN_MCR_AWUM_Pos (5U)
2240#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
2241#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
2242#define CAN_MCR_ABOM_Pos (6U)
2243#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
2244#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
2245#define CAN_MCR_TTCM_Pos (7U)
2246#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
2247#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
2248#define CAN_MCR_RESET_Pos (15U)
2249#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
2250#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
2251
2252/******************* Bit definition for CAN_MSR register ********************/
2253#define CAN_MSR_INAK_Pos (0U)
2254#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
2255#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
2256#define CAN_MSR_SLAK_Pos (1U)
2257#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
2258#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
2259#define CAN_MSR_ERRI_Pos (2U)
2260#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
2261#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
2262#define CAN_MSR_WKUI_Pos (3U)
2263#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
2264#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
2265#define CAN_MSR_SLAKI_Pos (4U)
2266#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
2267#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
2268#define CAN_MSR_TXM_Pos (8U)
2269#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
2270#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
2271#define CAN_MSR_RXM_Pos (9U)
2272#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
2273#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
2274#define CAN_MSR_SAMP_Pos (10U)
2275#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
2276#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
2277#define CAN_MSR_RX_Pos (11U)
2278#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
2279#define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
2280
2281/******************* Bit definition for CAN_TSR register ********************/
2282#define CAN_TSR_RQCP0_Pos (0U)
2283#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
2284#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
2285#define CAN_TSR_TXOK0_Pos (1U)
2286#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
2287#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
2288#define CAN_TSR_ALST0_Pos (2U)
2289#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
2290#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
2291#define CAN_TSR_TERR0_Pos (3U)
2292#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
2293#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
2294#define CAN_TSR_ABRQ0_Pos (7U)
2295#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
2296#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
2297#define CAN_TSR_RQCP1_Pos (8U)
2298#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
2299#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
2300#define CAN_TSR_TXOK1_Pos (9U)
2301#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
2302#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
2303#define CAN_TSR_ALST1_Pos (10U)
2304#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
2305#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
2306#define CAN_TSR_TERR1_Pos (11U)
2307#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
2308#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
2309#define CAN_TSR_ABRQ1_Pos (15U)
2310#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
2311#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
2312#define CAN_TSR_RQCP2_Pos (16U)
2313#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
2314#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
2315#define CAN_TSR_TXOK2_Pos (17U)
2316#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
2317#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
2318#define CAN_TSR_ALST2_Pos (18U)
2319#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
2320#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
2321#define CAN_TSR_TERR2_Pos (19U)
2322#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
2323#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
2324#define CAN_TSR_ABRQ2_Pos (23U)
2325#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
2326#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
2327#define CAN_TSR_CODE_Pos (24U)
2328#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
2329#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
2330
2331#define CAN_TSR_TME_Pos (26U)
2332#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
2333#define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
2334#define CAN_TSR_TME0_Pos (26U)
2335#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
2336#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
2337#define CAN_TSR_TME1_Pos (27U)
2338#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
2339#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
2340#define CAN_TSR_TME2_Pos (28U)
2341#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
2342#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
2343
2344#define CAN_TSR_LOW_Pos (29U)
2345#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
2346#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
2347#define CAN_TSR_LOW0_Pos (29U)
2348#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
2349#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
2350#define CAN_TSR_LOW1_Pos (30U)
2351#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
2352#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
2353#define CAN_TSR_LOW2_Pos (31U)
2354#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
2355#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
2356
2357/******************* Bit definition for CAN_RF0R register *******************/
2358#define CAN_RF0R_FMP0_Pos (0U)
2359#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
2360#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
2361#define CAN_RF0R_FULL0_Pos (3U)
2362#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
2363#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
2364#define CAN_RF0R_FOVR0_Pos (4U)
2365#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
2366#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
2367#define CAN_RF0R_RFOM0_Pos (5U)
2368#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
2369#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
2370
2371/******************* Bit definition for CAN_RF1R register *******************/
2372#define CAN_RF1R_FMP1_Pos (0U)
2373#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
2374#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
2375#define CAN_RF1R_FULL1_Pos (3U)
2376#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
2377#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
2378#define CAN_RF1R_FOVR1_Pos (4U)
2379#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
2380#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
2381#define CAN_RF1R_RFOM1_Pos (5U)
2382#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
2383#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
2384
2385/******************** Bit definition for CAN_IER register *******************/
2386#define CAN_IER_TMEIE_Pos (0U)
2387#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
2388#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
2389#define CAN_IER_FMPIE0_Pos (1U)
2390#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
2391#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
2392#define CAN_IER_FFIE0_Pos (2U)
2393#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
2394#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
2395#define CAN_IER_FOVIE0_Pos (3U)
2396#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
2397#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
2398#define CAN_IER_FMPIE1_Pos (4U)
2399#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
2400#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
2401#define CAN_IER_FFIE1_Pos (5U)
2402#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
2403#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
2404#define CAN_IER_FOVIE1_Pos (6U)
2405#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
2406#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
2407#define CAN_IER_EWGIE_Pos (8U)
2408#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
2409#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
2410#define CAN_IER_EPVIE_Pos (9U)
2411#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
2412#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
2413#define CAN_IER_BOFIE_Pos (10U)
2414#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
2415#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
2416#define CAN_IER_LECIE_Pos (11U)
2417#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
2418#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
2419#define CAN_IER_ERRIE_Pos (15U)
2420#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
2421#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
2422#define CAN_IER_WKUIE_Pos (16U)
2423#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
2424#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
2425#define CAN_IER_SLKIE_Pos (17U)
2426#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
2427#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
2428
2429/******************** Bit definition for CAN_ESR register *******************/
2430#define CAN_ESR_EWGF_Pos (0U)
2431#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
2432#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
2433#define CAN_ESR_EPVF_Pos (1U)
2434#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
2435#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
2436#define CAN_ESR_BOFF_Pos (2U)
2437#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
2438#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
2439
2440#define CAN_ESR_LEC_Pos (4U)
2441#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
2442#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
2443#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
2444#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
2445#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
2446
2447#define CAN_ESR_TEC_Pos (16U)
2448#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
2449#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
2450#define CAN_ESR_REC_Pos (24U)
2451#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
2452#define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
2453
2454/******************* Bit definition for CAN_BTR register ********************/
2455#define CAN_BTR_BRP_Pos (0U)
2456#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
2457#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
2458#define CAN_BTR_TS1_Pos (16U)
2459#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
2460#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
2461#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
2462#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
2463#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
2464#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
2465#define CAN_BTR_TS2_Pos (20U)
2466#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
2467#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
2468#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
2469#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
2470#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
2471#define CAN_BTR_SJW_Pos (24U)
2472#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
2473#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
2474#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
2475#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
2476#define CAN_BTR_LBKM_Pos (30U)
2477#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
2478#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
2479#define CAN_BTR_SILM_Pos (31U)
2480#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
2481#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
2482
2483/*!<Mailbox registers */
2484/****************** Bit definition for CAN_TI0R register ********************/
2485#define CAN_TI0R_TXRQ_Pos (0U)
2486#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
2487#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
2488#define CAN_TI0R_RTR_Pos (1U)
2489#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
2490#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
2491#define CAN_TI0R_IDE_Pos (2U)
2492#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
2493#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
2494#define CAN_TI0R_EXID_Pos (3U)
2495#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
2496#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
2497#define CAN_TI0R_STID_Pos (21U)
2498#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
2499#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2500
2501/****************** Bit definition for CAN_TDT0R register *******************/
2502#define CAN_TDT0R_DLC_Pos (0U)
2503#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
2504#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
2505#define CAN_TDT0R_TGT_Pos (8U)
2506#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
2507#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
2508#define CAN_TDT0R_TIME_Pos (16U)
2509#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2510#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
2511
2512/****************** Bit definition for CAN_TDL0R register *******************/
2513#define CAN_TDL0R_DATA0_Pos (0U)
2514#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
2515#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
2516#define CAN_TDL0R_DATA1_Pos (8U)
2517#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2518#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
2519#define CAN_TDL0R_DATA2_Pos (16U)
2520#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2521#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
2522#define CAN_TDL0R_DATA3_Pos (24U)
2523#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
2524#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
2525
2526/****************** Bit definition for CAN_TDH0R register *******************/
2527#define CAN_TDH0R_DATA4_Pos (0U)
2528#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
2529#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
2530#define CAN_TDH0R_DATA5_Pos (8U)
2531#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2532#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
2533#define CAN_TDH0R_DATA6_Pos (16U)
2534#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2535#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
2536#define CAN_TDH0R_DATA7_Pos (24U)
2537#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
2538#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
2539
2540/******************* Bit definition for CAN_TI1R register *******************/
2541#define CAN_TI1R_TXRQ_Pos (0U)
2542#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
2543#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
2544#define CAN_TI1R_RTR_Pos (1U)
2545#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
2546#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
2547#define CAN_TI1R_IDE_Pos (2U)
2548#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
2549#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
2550#define CAN_TI1R_EXID_Pos (3U)
2551#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
2552#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
2553#define CAN_TI1R_STID_Pos (21U)
2554#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
2555#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2556
2557/******************* Bit definition for CAN_TDT1R register ******************/
2558#define CAN_TDT1R_DLC_Pos (0U)
2559#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
2560#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
2561#define CAN_TDT1R_TGT_Pos (8U)
2562#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
2563#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
2564#define CAN_TDT1R_TIME_Pos (16U)
2565#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2566#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
2567
2568/******************* Bit definition for CAN_TDL1R register ******************/
2569#define CAN_TDL1R_DATA0_Pos (0U)
2570#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
2571#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
2572#define CAN_TDL1R_DATA1_Pos (8U)
2573#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2574#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
2575#define CAN_TDL1R_DATA2_Pos (16U)
2576#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2577#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
2578#define CAN_TDL1R_DATA3_Pos (24U)
2579#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
2580#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
2581
2582/******************* Bit definition for CAN_TDH1R register ******************/
2583#define CAN_TDH1R_DATA4_Pos (0U)
2584#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
2585#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
2586#define CAN_TDH1R_DATA5_Pos (8U)
2587#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2588#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
2589#define CAN_TDH1R_DATA6_Pos (16U)
2590#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2591#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
2592#define CAN_TDH1R_DATA7_Pos (24U)
2593#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
2594#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
2595
2596/******************* Bit definition for CAN_TI2R register *******************/
2597#define CAN_TI2R_TXRQ_Pos (0U)
2598#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
2599#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
2600#define CAN_TI2R_RTR_Pos (1U)
2601#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
2602#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
2603#define CAN_TI2R_IDE_Pos (2U)
2604#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
2605#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
2606#define CAN_TI2R_EXID_Pos (3U)
2607#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
2608#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
2609#define CAN_TI2R_STID_Pos (21U)
2610#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
2611#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2612
2613/******************* Bit definition for CAN_TDT2R register ******************/
2614#define CAN_TDT2R_DLC_Pos (0U)
2615#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
2616#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
2617#define CAN_TDT2R_TGT_Pos (8U)
2618#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
2619#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
2620#define CAN_TDT2R_TIME_Pos (16U)
2621#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
2622#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
2623
2624/******************* Bit definition for CAN_TDL2R register ******************/
2625#define CAN_TDL2R_DATA0_Pos (0U)
2626#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
2627#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
2628#define CAN_TDL2R_DATA1_Pos (8U)
2629#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
2630#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
2631#define CAN_TDL2R_DATA2_Pos (16U)
2632#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
2633#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
2634#define CAN_TDL2R_DATA3_Pos (24U)
2635#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
2636#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
2637
2638/******************* Bit definition for CAN_TDH2R register ******************/
2639#define CAN_TDH2R_DATA4_Pos (0U)
2640#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
2641#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
2642#define CAN_TDH2R_DATA5_Pos (8U)
2643#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
2644#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
2645#define CAN_TDH2R_DATA6_Pos (16U)
2646#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
2647#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
2648#define CAN_TDH2R_DATA7_Pos (24U)
2649#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
2650#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
2651
2652/******************* Bit definition for CAN_RI0R register *******************/
2653#define CAN_RI0R_RTR_Pos (1U)
2654#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
2655#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
2656#define CAN_RI0R_IDE_Pos (2U)
2657#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
2658#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
2659#define CAN_RI0R_EXID_Pos (3U)
2660#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
2661#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
2662#define CAN_RI0R_STID_Pos (21U)
2663#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
2664#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2665
2666/******************* Bit definition for CAN_RDT0R register ******************/
2667#define CAN_RDT0R_DLC_Pos (0U)
2668#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
2669#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
2670#define CAN_RDT0R_FMI_Pos (8U)
2671#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
2672#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
2673#define CAN_RDT0R_TIME_Pos (16U)
2674#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2675#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
2676
2677/******************* Bit definition for CAN_RDL0R register ******************/
2678#define CAN_RDL0R_DATA0_Pos (0U)
2679#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
2680#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
2681#define CAN_RDL0R_DATA1_Pos (8U)
2682#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2683#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
2684#define CAN_RDL0R_DATA2_Pos (16U)
2685#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2686#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
2687#define CAN_RDL0R_DATA3_Pos (24U)
2688#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
2689#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
2690
2691/******************* Bit definition for CAN_RDH0R register ******************/
2692#define CAN_RDH0R_DATA4_Pos (0U)
2693#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
2694#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
2695#define CAN_RDH0R_DATA5_Pos (8U)
2696#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2697#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
2698#define CAN_RDH0R_DATA6_Pos (16U)
2699#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2700#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
2701#define CAN_RDH0R_DATA7_Pos (24U)
2702#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
2703#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
2704
2705/******************* Bit definition for CAN_RI1R register *******************/
2706#define CAN_RI1R_RTR_Pos (1U)
2707#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
2708#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
2709#define CAN_RI1R_IDE_Pos (2U)
2710#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
2711#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
2712#define CAN_RI1R_EXID_Pos (3U)
2713#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
2714#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
2715#define CAN_RI1R_STID_Pos (21U)
2716#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
2717#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2718
2719/******************* Bit definition for CAN_RDT1R register ******************/
2720#define CAN_RDT1R_DLC_Pos (0U)
2721#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
2722#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
2723#define CAN_RDT1R_FMI_Pos (8U)
2724#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
2725#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
2726#define CAN_RDT1R_TIME_Pos (16U)
2727#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2728#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
2729
2730/******************* Bit definition for CAN_RDL1R register ******************/
2731#define CAN_RDL1R_DATA0_Pos (0U)
2732#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
2733#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
2734#define CAN_RDL1R_DATA1_Pos (8U)
2735#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2736#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
2737#define CAN_RDL1R_DATA2_Pos (16U)
2738#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2739#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
2740#define CAN_RDL1R_DATA3_Pos (24U)
2741#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
2742#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
2743
2744/******************* Bit definition for CAN_RDH1R register ******************/
2745#define CAN_RDH1R_DATA4_Pos (0U)
2746#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
2747#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
2748#define CAN_RDH1R_DATA5_Pos (8U)
2749#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2750#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
2751#define CAN_RDH1R_DATA6_Pos (16U)
2752#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2753#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
2754#define CAN_RDH1R_DATA7_Pos (24U)
2755#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
2756#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
2757
2758/*!<CAN filter registers */
2759/******************* Bit definition for CAN_FMR register ********************/
2760#define CAN_FMR_FINIT ((uint8_t)0x01U) /*!<Filter Init Mode */
2761#define CAN_FMR_CAN2SB_Pos (8U)
2762#define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
2763#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
2764
2765/******************* Bit definition for CAN_FM1R register *******************/
2766#define CAN_FM1R_FBM_Pos (0U)
2767#define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
2768#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
2769#define CAN_FM1R_FBM0_Pos (0U)
2770#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
2771#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
2772#define CAN_FM1R_FBM1_Pos (1U)
2773#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
2774#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
2775#define CAN_FM1R_FBM2_Pos (2U)
2776#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
2777#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
2778#define CAN_FM1R_FBM3_Pos (3U)
2779#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
2780#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
2781#define CAN_FM1R_FBM4_Pos (4U)
2782#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
2783#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
2784#define CAN_FM1R_FBM5_Pos (5U)
2785#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
2786#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
2787#define CAN_FM1R_FBM6_Pos (6U)
2788#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
2789#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
2790#define CAN_FM1R_FBM7_Pos (7U)
2791#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
2792#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
2793#define CAN_FM1R_FBM8_Pos (8U)
2794#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
2795#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
2796#define CAN_FM1R_FBM9_Pos (9U)
2797#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
2798#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
2799#define CAN_FM1R_FBM10_Pos (10U)
2800#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
2801#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
2802#define CAN_FM1R_FBM11_Pos (11U)
2803#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
2804#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
2805#define CAN_FM1R_FBM12_Pos (12U)
2806#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
2807#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
2808#define CAN_FM1R_FBM13_Pos (13U)
2809#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
2810#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
2811
2812/******************* Bit definition for CAN_FS1R register *******************/
2813#define CAN_FS1R_FSC_Pos (0U)
2814#define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
2815#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
2816#define CAN_FS1R_FSC0_Pos (0U)
2817#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
2818#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
2819#define CAN_FS1R_FSC1_Pos (1U)
2820#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
2821#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
2822#define CAN_FS1R_FSC2_Pos (2U)
2823#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
2824#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
2825#define CAN_FS1R_FSC3_Pos (3U)
2826#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
2827#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
2828#define CAN_FS1R_FSC4_Pos (4U)
2829#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
2830#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
2831#define CAN_FS1R_FSC5_Pos (5U)
2832#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
2833#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
2834#define CAN_FS1R_FSC6_Pos (6U)
2835#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
2836#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
2837#define CAN_FS1R_FSC7_Pos (7U)
2838#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
2839#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
2840#define CAN_FS1R_FSC8_Pos (8U)
2841#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
2842#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
2843#define CAN_FS1R_FSC9_Pos (9U)
2844#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
2845#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
2846#define CAN_FS1R_FSC10_Pos (10U)
2847#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
2848#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
2849#define CAN_FS1R_FSC11_Pos (11U)
2850#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
2851#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
2852#define CAN_FS1R_FSC12_Pos (12U)
2853#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
2854#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
2855#define CAN_FS1R_FSC13_Pos (13U)
2856#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
2857#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
2858
2859/****************** Bit definition for CAN_FFA1R register *******************/
2860#define CAN_FFA1R_FFA_Pos (0U)
2861#define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
2862#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
2863#define CAN_FFA1R_FFA0_Pos (0U)
2864#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
2865#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
2866#define CAN_FFA1R_FFA1_Pos (1U)
2867#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
2868#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
2869#define CAN_FFA1R_FFA2_Pos (2U)
2870#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
2871#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
2872#define CAN_FFA1R_FFA3_Pos (3U)
2873#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
2874#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
2875#define CAN_FFA1R_FFA4_Pos (4U)
2876#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
2877#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
2878#define CAN_FFA1R_FFA5_Pos (5U)
2879#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
2880#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
2881#define CAN_FFA1R_FFA6_Pos (6U)
2882#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
2883#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
2884#define CAN_FFA1R_FFA7_Pos (7U)
2885#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
2886#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
2887#define CAN_FFA1R_FFA8_Pos (8U)
2888#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
2889#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
2890#define CAN_FFA1R_FFA9_Pos (9U)
2891#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
2892#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
2893#define CAN_FFA1R_FFA10_Pos (10U)
2894#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
2895#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
2896#define CAN_FFA1R_FFA11_Pos (11U)
2897#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
2898#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
2899#define CAN_FFA1R_FFA12_Pos (12U)
2900#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
2901#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
2902#define CAN_FFA1R_FFA13_Pos (13U)
2903#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
2904#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
2905
2906/******************* Bit definition for CAN_FA1R register *******************/
2907#define CAN_FA1R_FACT_Pos (0U)
2908#define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
2909#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
2910#define CAN_FA1R_FACT0_Pos (0U)
2911#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
2912#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
2913#define CAN_FA1R_FACT1_Pos (1U)
2914#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
2915#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
2916#define CAN_FA1R_FACT2_Pos (2U)
2917#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
2918#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
2919#define CAN_FA1R_FACT3_Pos (3U)
2920#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
2921#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
2922#define CAN_FA1R_FACT4_Pos (4U)
2923#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
2924#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
2925#define CAN_FA1R_FACT5_Pos (5U)
2926#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
2927#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
2928#define CAN_FA1R_FACT6_Pos (6U)
2929#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
2930#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
2931#define CAN_FA1R_FACT7_Pos (7U)
2932#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
2933#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
2934#define CAN_FA1R_FACT8_Pos (8U)
2935#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
2936#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
2937#define CAN_FA1R_FACT9_Pos (9U)
2938#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
2939#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
2940#define CAN_FA1R_FACT10_Pos (10U)
2941#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
2942#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
2943#define CAN_FA1R_FACT11_Pos (11U)
2944#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
2945#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
2946#define CAN_FA1R_FACT12_Pos (12U)
2947#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
2948#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
2949#define CAN_FA1R_FACT13_Pos (13U)
2950#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
2951#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
2952
2953/******************* Bit definition for CAN_F0R1 register *******************/
2954#define CAN_F0R1_FB0_Pos (0U)
2955#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
2956#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
2957#define CAN_F0R1_FB1_Pos (1U)
2958#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
2959#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
2960#define CAN_F0R1_FB2_Pos (2U)
2961#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
2962#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
2963#define CAN_F0R1_FB3_Pos (3U)
2964#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
2965#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
2966#define CAN_F0R1_FB4_Pos (4U)
2967#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
2968#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
2969#define CAN_F0R1_FB5_Pos (5U)
2970#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
2971#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
2972#define CAN_F0R1_FB6_Pos (6U)
2973#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
2974#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
2975#define CAN_F0R1_FB7_Pos (7U)
2976#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
2977#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
2978#define CAN_F0R1_FB8_Pos (8U)
2979#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
2980#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
2981#define CAN_F0R1_FB9_Pos (9U)
2982#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
2983#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
2984#define CAN_F0R1_FB10_Pos (10U)
2985#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
2986#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
2987#define CAN_F0R1_FB11_Pos (11U)
2988#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
2989#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
2990#define CAN_F0R1_FB12_Pos (12U)
2991#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
2992#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
2993#define CAN_F0R1_FB13_Pos (13U)
2994#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
2995#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
2996#define CAN_F0R1_FB14_Pos (14U)
2997#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
2998#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
2999#define CAN_F0R1_FB15_Pos (15U)
3000#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
3001#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
3002#define CAN_F0R1_FB16_Pos (16U)
3003#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
3004#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
3005#define CAN_F0R1_FB17_Pos (17U)
3006#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
3007#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
3008#define CAN_F0R1_FB18_Pos (18U)
3009#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
3010#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
3011#define CAN_F0R1_FB19_Pos (19U)
3012#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
3013#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
3014#define CAN_F0R1_FB20_Pos (20U)
3015#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
3016#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
3017#define CAN_F0R1_FB21_Pos (21U)
3018#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
3019#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
3020#define CAN_F0R1_FB22_Pos (22U)
3021#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
3022#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
3023#define CAN_F0R1_FB23_Pos (23U)
3024#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
3025#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
3026#define CAN_F0R1_FB24_Pos (24U)
3027#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
3028#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
3029#define CAN_F0R1_FB25_Pos (25U)
3030#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
3031#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
3032#define CAN_F0R1_FB26_Pos (26U)
3033#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
3034#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
3035#define CAN_F0R1_FB27_Pos (27U)
3036#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
3037#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
3038#define CAN_F0R1_FB28_Pos (28U)
3039#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
3040#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
3041#define CAN_F0R1_FB29_Pos (29U)
3042#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
3043#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
3044#define CAN_F0R1_FB30_Pos (30U)
3045#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
3046#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
3047#define CAN_F0R1_FB31_Pos (31U)
3048#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
3049#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
3050
3051/******************* Bit definition for CAN_F1R1 register *******************/
3052#define CAN_F1R1_FB0_Pos (0U)
3053#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
3054#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
3055#define CAN_F1R1_FB1_Pos (1U)
3056#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
3057#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
3058#define CAN_F1R1_FB2_Pos (2U)
3059#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
3060#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
3061#define CAN_F1R1_FB3_Pos (3U)
3062#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
3063#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
3064#define CAN_F1R1_FB4_Pos (4U)
3065#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
3066#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
3067#define CAN_F1R1_FB5_Pos (5U)
3068#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
3069#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
3070#define CAN_F1R1_FB6_Pos (6U)
3071#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
3072#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
3073#define CAN_F1R1_FB7_Pos (7U)
3074#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
3075#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
3076#define CAN_F1R1_FB8_Pos (8U)
3077#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
3078#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
3079#define CAN_F1R1_FB9_Pos (9U)
3080#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
3081#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
3082#define CAN_F1R1_FB10_Pos (10U)
3083#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
3084#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
3085#define CAN_F1R1_FB11_Pos (11U)
3086#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
3087#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
3088#define CAN_F1R1_FB12_Pos (12U)
3089#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
3090#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
3091#define CAN_F1R1_FB13_Pos (13U)
3092#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
3093#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
3094#define CAN_F1R1_FB14_Pos (14U)
3095#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
3096#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
3097#define CAN_F1R1_FB15_Pos (15U)
3098#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
3099#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
3100#define CAN_F1R1_FB16_Pos (16U)
3101#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
3102#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
3103#define CAN_F1R1_FB17_Pos (17U)
3104#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
3105#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
3106#define CAN_F1R1_FB18_Pos (18U)
3107#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
3108#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
3109#define CAN_F1R1_FB19_Pos (19U)
3110#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
3111#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
3112#define CAN_F1R1_FB20_Pos (20U)
3113#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
3114#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
3115#define CAN_F1R1_FB21_Pos (21U)
3116#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
3117#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
3118#define CAN_F1R1_FB22_Pos (22U)
3119#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
3120#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
3121#define CAN_F1R1_FB23_Pos (23U)
3122#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
3123#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
3124#define CAN_F1R1_FB24_Pos (24U)
3125#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
3126#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
3127#define CAN_F1R1_FB25_Pos (25U)
3128#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
3129#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
3130#define CAN_F1R1_FB26_Pos (26U)
3131#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
3132#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
3133#define CAN_F1R1_FB27_Pos (27U)
3134#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
3135#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
3136#define CAN_F1R1_FB28_Pos (28U)
3137#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
3138#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
3139#define CAN_F1R1_FB29_Pos (29U)
3140#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
3141#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
3142#define CAN_F1R1_FB30_Pos (30U)
3143#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
3144#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
3145#define CAN_F1R1_FB31_Pos (31U)
3146#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
3147#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
3148
3149/******************* Bit definition for CAN_F2R1 register *******************/
3150#define CAN_F2R1_FB0_Pos (0U)
3151#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
3152#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
3153#define CAN_F2R1_FB1_Pos (1U)
3154#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
3155#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
3156#define CAN_F2R1_FB2_Pos (2U)
3157#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
3158#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
3159#define CAN_F2R1_FB3_Pos (3U)
3160#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
3161#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
3162#define CAN_F2R1_FB4_Pos (4U)
3163#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
3164#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
3165#define CAN_F2R1_FB5_Pos (5U)
3166#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
3167#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
3168#define CAN_F2R1_FB6_Pos (6U)
3169#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
3170#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
3171#define CAN_F2R1_FB7_Pos (7U)
3172#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
3173#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
3174#define CAN_F2R1_FB8_Pos (8U)
3175#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
3176#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
3177#define CAN_F2R1_FB9_Pos (9U)
3178#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
3179#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
3180#define CAN_F2R1_FB10_Pos (10U)
3181#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
3182#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
3183#define CAN_F2R1_FB11_Pos (11U)
3184#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
3185#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
3186#define CAN_F2R1_FB12_Pos (12U)
3187#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
3188#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
3189#define CAN_F2R1_FB13_Pos (13U)
3190#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
3191#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
3192#define CAN_F2R1_FB14_Pos (14U)
3193#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
3194#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
3195#define CAN_F2R1_FB15_Pos (15U)
3196#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
3197#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
3198#define CAN_F2R1_FB16_Pos (16U)
3199#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
3200#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
3201#define CAN_F2R1_FB17_Pos (17U)
3202#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
3203#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
3204#define CAN_F2R1_FB18_Pos (18U)
3205#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
3206#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
3207#define CAN_F2R1_FB19_Pos (19U)
3208#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
3209#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
3210#define CAN_F2R1_FB20_Pos (20U)
3211#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
3212#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
3213#define CAN_F2R1_FB21_Pos (21U)
3214#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
3215#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
3216#define CAN_F2R1_FB22_Pos (22U)
3217#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
3218#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
3219#define CAN_F2R1_FB23_Pos (23U)
3220#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
3221#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
3222#define CAN_F2R1_FB24_Pos (24U)
3223#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
3224#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
3225#define CAN_F2R1_FB25_Pos (25U)
3226#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
3227#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
3228#define CAN_F2R1_FB26_Pos (26U)
3229#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
3230#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
3231#define CAN_F2R1_FB27_Pos (27U)
3232#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
3233#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
3234#define CAN_F2R1_FB28_Pos (28U)
3235#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
3236#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
3237#define CAN_F2R1_FB29_Pos (29U)
3238#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
3239#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
3240#define CAN_F2R1_FB30_Pos (30U)
3241#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
3242#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
3243#define CAN_F2R1_FB31_Pos (31U)
3244#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
3245#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
3246
3247/******************* Bit definition for CAN_F3R1 register *******************/
3248#define CAN_F3R1_FB0_Pos (0U)
3249#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
3250#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
3251#define CAN_F3R1_FB1_Pos (1U)
3252#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
3253#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
3254#define CAN_F3R1_FB2_Pos (2U)
3255#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
3256#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
3257#define CAN_F3R1_FB3_Pos (3U)
3258#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
3259#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
3260#define CAN_F3R1_FB4_Pos (4U)
3261#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
3262#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
3263#define CAN_F3R1_FB5_Pos (5U)
3264#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
3265#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
3266#define CAN_F3R1_FB6_Pos (6U)
3267#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
3268#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
3269#define CAN_F3R1_FB7_Pos (7U)
3270#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
3271#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
3272#define CAN_F3R1_FB8_Pos (8U)
3273#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
3274#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
3275#define CAN_F3R1_FB9_Pos (9U)
3276#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
3277#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
3278#define CAN_F3R1_FB10_Pos (10U)
3279#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
3280#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
3281#define CAN_F3R1_FB11_Pos (11U)
3282#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
3283#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
3284#define CAN_F3R1_FB12_Pos (12U)
3285#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
3286#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
3287#define CAN_F3R1_FB13_Pos (13U)
3288#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
3289#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
3290#define CAN_F3R1_FB14_Pos (14U)
3291#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
3292#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
3293#define CAN_F3R1_FB15_Pos (15U)
3294#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
3295#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
3296#define CAN_F3R1_FB16_Pos (16U)
3297#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
3298#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
3299#define CAN_F3R1_FB17_Pos (17U)
3300#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
3301#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
3302#define CAN_F3R1_FB18_Pos (18U)
3303#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
3304#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
3305#define CAN_F3R1_FB19_Pos (19U)
3306#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
3307#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
3308#define CAN_F3R1_FB20_Pos (20U)
3309#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
3310#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
3311#define CAN_F3R1_FB21_Pos (21U)
3312#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
3313#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
3314#define CAN_F3R1_FB22_Pos (22U)
3315#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
3316#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
3317#define CAN_F3R1_FB23_Pos (23U)
3318#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
3319#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
3320#define CAN_F3R1_FB24_Pos (24U)
3321#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
3322#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
3323#define CAN_F3R1_FB25_Pos (25U)
3324#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
3325#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
3326#define CAN_F3R1_FB26_Pos (26U)
3327#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
3328#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
3329#define CAN_F3R1_FB27_Pos (27U)
3330#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
3331#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
3332#define CAN_F3R1_FB28_Pos (28U)
3333#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
3334#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
3335#define CAN_F3R1_FB29_Pos (29U)
3336#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
3337#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
3338#define CAN_F3R1_FB30_Pos (30U)
3339#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
3340#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
3341#define CAN_F3R1_FB31_Pos (31U)
3342#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
3343#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
3344
3345/******************* Bit definition for CAN_F4R1 register *******************/
3346#define CAN_F4R1_FB0_Pos (0U)
3347#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
3348#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
3349#define CAN_F4R1_FB1_Pos (1U)
3350#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
3351#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
3352#define CAN_F4R1_FB2_Pos (2U)
3353#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
3354#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
3355#define CAN_F4R1_FB3_Pos (3U)
3356#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
3357#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
3358#define CAN_F4R1_FB4_Pos (4U)
3359#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
3360#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
3361#define CAN_F4R1_FB5_Pos (5U)
3362#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
3363#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
3364#define CAN_F4R1_FB6_Pos (6U)
3365#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
3366#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
3367#define CAN_F4R1_FB7_Pos (7U)
3368#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
3369#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
3370#define CAN_F4R1_FB8_Pos (8U)
3371#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
3372#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
3373#define CAN_F4R1_FB9_Pos (9U)
3374#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
3375#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
3376#define CAN_F4R1_FB10_Pos (10U)
3377#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
3378#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
3379#define CAN_F4R1_FB11_Pos (11U)
3380#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
3381#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
3382#define CAN_F4R1_FB12_Pos (12U)
3383#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
3384#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
3385#define CAN_F4R1_FB13_Pos (13U)
3386#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
3387#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
3388#define CAN_F4R1_FB14_Pos (14U)
3389#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
3390#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
3391#define CAN_F4R1_FB15_Pos (15U)
3392#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
3393#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
3394#define CAN_F4R1_FB16_Pos (16U)
3395#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
3396#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
3397#define CAN_F4R1_FB17_Pos (17U)
3398#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
3399#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
3400#define CAN_F4R1_FB18_Pos (18U)
3401#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
3402#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
3403#define CAN_F4R1_FB19_Pos (19U)
3404#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
3405#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
3406#define CAN_F4R1_FB20_Pos (20U)
3407#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
3408#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
3409#define CAN_F4R1_FB21_Pos (21U)
3410#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
3411#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
3412#define CAN_F4R1_FB22_Pos (22U)
3413#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
3414#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
3415#define CAN_F4R1_FB23_Pos (23U)
3416#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
3417#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
3418#define CAN_F4R1_FB24_Pos (24U)
3419#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
3420#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
3421#define CAN_F4R1_FB25_Pos (25U)
3422#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
3423#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
3424#define CAN_F4R1_FB26_Pos (26U)
3425#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
3426#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
3427#define CAN_F4R1_FB27_Pos (27U)
3428#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
3429#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
3430#define CAN_F4R1_FB28_Pos (28U)
3431#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
3432#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
3433#define CAN_F4R1_FB29_Pos (29U)
3434#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
3435#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
3436#define CAN_F4R1_FB30_Pos (30U)
3437#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
3438#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
3439#define CAN_F4R1_FB31_Pos (31U)
3440#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
3441#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
3442
3443/******************* Bit definition for CAN_F5R1 register *******************/
3444#define CAN_F5R1_FB0_Pos (0U)
3445#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
3446#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
3447#define CAN_F5R1_FB1_Pos (1U)
3448#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
3449#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
3450#define CAN_F5R1_FB2_Pos (2U)
3451#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
3452#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
3453#define CAN_F5R1_FB3_Pos (3U)
3454#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
3455#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
3456#define CAN_F5R1_FB4_Pos (4U)
3457#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
3458#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
3459#define CAN_F5R1_FB5_Pos (5U)
3460#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
3461#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
3462#define CAN_F5R1_FB6_Pos (6U)
3463#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
3464#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
3465#define CAN_F5R1_FB7_Pos (7U)
3466#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
3467#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
3468#define CAN_F5R1_FB8_Pos (8U)
3469#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
3470#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
3471#define CAN_F5R1_FB9_Pos (9U)
3472#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
3473#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
3474#define CAN_F5R1_FB10_Pos (10U)
3475#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
3476#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
3477#define CAN_F5R1_FB11_Pos (11U)
3478#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
3479#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
3480#define CAN_F5R1_FB12_Pos (12U)
3481#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
3482#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
3483#define CAN_F5R1_FB13_Pos (13U)
3484#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
3485#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
3486#define CAN_F5R1_FB14_Pos (14U)
3487#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
3488#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
3489#define CAN_F5R1_FB15_Pos (15U)
3490#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
3491#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
3492#define CAN_F5R1_FB16_Pos (16U)
3493#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
3494#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
3495#define CAN_F5R1_FB17_Pos (17U)
3496#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
3497#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
3498#define CAN_F5R1_FB18_Pos (18U)
3499#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
3500#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
3501#define CAN_F5R1_FB19_Pos (19U)
3502#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
3503#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
3504#define CAN_F5R1_FB20_Pos (20U)
3505#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
3506#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
3507#define CAN_F5R1_FB21_Pos (21U)
3508#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
3509#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
3510#define CAN_F5R1_FB22_Pos (22U)
3511#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
3512#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
3513#define CAN_F5R1_FB23_Pos (23U)
3514#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
3515#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
3516#define CAN_F5R1_FB24_Pos (24U)
3517#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
3518#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
3519#define CAN_F5R1_FB25_Pos (25U)
3520#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
3521#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
3522#define CAN_F5R1_FB26_Pos (26U)
3523#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
3524#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
3525#define CAN_F5R1_FB27_Pos (27U)
3526#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
3527#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
3528#define CAN_F5R1_FB28_Pos (28U)
3529#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
3530#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
3531#define CAN_F5R1_FB29_Pos (29U)
3532#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
3533#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
3534#define CAN_F5R1_FB30_Pos (30U)
3535#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
3536#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
3537#define CAN_F5R1_FB31_Pos (31U)
3538#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
3539#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
3540
3541/******************* Bit definition for CAN_F6R1 register *******************/
3542#define CAN_F6R1_FB0_Pos (0U)
3543#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
3544#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
3545#define CAN_F6R1_FB1_Pos (1U)
3546#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
3547#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
3548#define CAN_F6R1_FB2_Pos (2U)
3549#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
3550#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
3551#define CAN_F6R1_FB3_Pos (3U)
3552#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
3553#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
3554#define CAN_F6R1_FB4_Pos (4U)
3555#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
3556#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
3557#define CAN_F6R1_FB5_Pos (5U)
3558#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
3559#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
3560#define CAN_F6R1_FB6_Pos (6U)
3561#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
3562#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
3563#define CAN_F6R1_FB7_Pos (7U)
3564#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
3565#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
3566#define CAN_F6R1_FB8_Pos (8U)
3567#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
3568#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
3569#define CAN_F6R1_FB9_Pos (9U)
3570#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
3571#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
3572#define CAN_F6R1_FB10_Pos (10U)
3573#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
3574#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
3575#define CAN_F6R1_FB11_Pos (11U)
3576#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
3577#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
3578#define CAN_F6R1_FB12_Pos (12U)
3579#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
3580#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
3581#define CAN_F6R1_FB13_Pos (13U)
3582#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
3583#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
3584#define CAN_F6R1_FB14_Pos (14U)
3585#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
3586#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
3587#define CAN_F6R1_FB15_Pos (15U)
3588#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
3589#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
3590#define CAN_F6R1_FB16_Pos (16U)
3591#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
3592#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
3593#define CAN_F6R1_FB17_Pos (17U)
3594#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
3595#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
3596#define CAN_F6R1_FB18_Pos (18U)
3597#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
3598#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
3599#define CAN_F6R1_FB19_Pos (19U)
3600#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
3601#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
3602#define CAN_F6R1_FB20_Pos (20U)
3603#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
3604#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
3605#define CAN_F6R1_FB21_Pos (21U)
3606#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
3607#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
3608#define CAN_F6R1_FB22_Pos (22U)
3609#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
3610#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
3611#define CAN_F6R1_FB23_Pos (23U)
3612#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
3613#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
3614#define CAN_F6R1_FB24_Pos (24U)
3615#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
3616#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
3617#define CAN_F6R1_FB25_Pos (25U)
3618#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
3619#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
3620#define CAN_F6R1_FB26_Pos (26U)
3621#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
3622#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
3623#define CAN_F6R1_FB27_Pos (27U)
3624#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
3625#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
3626#define CAN_F6R1_FB28_Pos (28U)
3627#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
3628#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
3629#define CAN_F6R1_FB29_Pos (29U)
3630#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
3631#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
3632#define CAN_F6R1_FB30_Pos (30U)
3633#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
3634#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
3635#define CAN_F6R1_FB31_Pos (31U)
3636#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
3637#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
3638
3639/******************* Bit definition for CAN_F7R1 register *******************/
3640#define CAN_F7R1_FB0_Pos (0U)
3641#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
3642#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
3643#define CAN_F7R1_FB1_Pos (1U)
3644#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
3645#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
3646#define CAN_F7R1_FB2_Pos (2U)
3647#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
3648#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
3649#define CAN_F7R1_FB3_Pos (3U)
3650#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
3651#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
3652#define CAN_F7R1_FB4_Pos (4U)
3653#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
3654#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
3655#define CAN_F7R1_FB5_Pos (5U)
3656#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
3657#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
3658#define CAN_F7R1_FB6_Pos (6U)
3659#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
3660#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
3661#define CAN_F7R1_FB7_Pos (7U)
3662#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
3663#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
3664#define CAN_F7R1_FB8_Pos (8U)
3665#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
3666#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
3667#define CAN_F7R1_FB9_Pos (9U)
3668#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
3669#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
3670#define CAN_F7R1_FB10_Pos (10U)
3671#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
3672#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
3673#define CAN_F7R1_FB11_Pos (11U)
3674#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
3675#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
3676#define CAN_F7R1_FB12_Pos (12U)
3677#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
3678#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
3679#define CAN_F7R1_FB13_Pos (13U)
3680#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
3681#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
3682#define CAN_F7R1_FB14_Pos (14U)
3683#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
3684#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
3685#define CAN_F7R1_FB15_Pos (15U)
3686#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
3687#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
3688#define CAN_F7R1_FB16_Pos (16U)
3689#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
3690#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
3691#define CAN_F7R1_FB17_Pos (17U)
3692#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
3693#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
3694#define CAN_F7R1_FB18_Pos (18U)
3695#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
3696#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
3697#define CAN_F7R1_FB19_Pos (19U)
3698#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
3699#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
3700#define CAN_F7R1_FB20_Pos (20U)
3701#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
3702#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
3703#define CAN_F7R1_FB21_Pos (21U)
3704#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
3705#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
3706#define CAN_F7R1_FB22_Pos (22U)
3707#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
3708#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
3709#define CAN_F7R1_FB23_Pos (23U)
3710#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
3711#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
3712#define CAN_F7R1_FB24_Pos (24U)
3713#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
3714#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
3715#define CAN_F7R1_FB25_Pos (25U)
3716#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
3717#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
3718#define CAN_F7R1_FB26_Pos (26U)
3719#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
3720#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
3721#define CAN_F7R1_FB27_Pos (27U)
3722#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
3723#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
3724#define CAN_F7R1_FB28_Pos (28U)
3725#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
3726#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
3727#define CAN_F7R1_FB29_Pos (29U)
3728#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
3729#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
3730#define CAN_F7R1_FB30_Pos (30U)
3731#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
3732#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
3733#define CAN_F7R1_FB31_Pos (31U)
3734#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
3735#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
3736
3737/******************* Bit definition for CAN_F8R1 register *******************/
3738#define CAN_F8R1_FB0_Pos (0U)
3739#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
3740#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
3741#define CAN_F8R1_FB1_Pos (1U)
3742#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
3743#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
3744#define CAN_F8R1_FB2_Pos (2U)
3745#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
3746#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
3747#define CAN_F8R1_FB3_Pos (3U)
3748#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
3749#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
3750#define CAN_F8R1_FB4_Pos (4U)
3751#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
3752#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
3753#define CAN_F8R1_FB5_Pos (5U)
3754#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
3755#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
3756#define CAN_F8R1_FB6_Pos (6U)
3757#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
3758#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
3759#define CAN_F8R1_FB7_Pos (7U)
3760#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
3761#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
3762#define CAN_F8R1_FB8_Pos (8U)
3763#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
3764#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
3765#define CAN_F8R1_FB9_Pos (9U)
3766#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
3767#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
3768#define CAN_F8R1_FB10_Pos (10U)
3769#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
3770#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
3771#define CAN_F8R1_FB11_Pos (11U)
3772#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
3773#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
3774#define CAN_F8R1_FB12_Pos (12U)
3775#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
3776#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
3777#define CAN_F8R1_FB13_Pos (13U)
3778#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
3779#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
3780#define CAN_F8R1_FB14_Pos (14U)
3781#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
3782#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
3783#define CAN_F8R1_FB15_Pos (15U)
3784#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
3785#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
3786#define CAN_F8R1_FB16_Pos (16U)
3787#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
3788#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
3789#define CAN_F8R1_FB17_Pos (17U)
3790#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
3791#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
3792#define CAN_F8R1_FB18_Pos (18U)
3793#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
3794#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
3795#define CAN_F8R1_FB19_Pos (19U)
3796#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
3797#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
3798#define CAN_F8R1_FB20_Pos (20U)
3799#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
3800#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
3801#define CAN_F8R1_FB21_Pos (21U)
3802#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
3803#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
3804#define CAN_F8R1_FB22_Pos (22U)
3805#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
3806#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
3807#define CAN_F8R1_FB23_Pos (23U)
3808#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
3809#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
3810#define CAN_F8R1_FB24_Pos (24U)
3811#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
3812#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
3813#define CAN_F8R1_FB25_Pos (25U)
3814#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
3815#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
3816#define CAN_F8R1_FB26_Pos (26U)
3817#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
3818#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
3819#define CAN_F8R1_FB27_Pos (27U)
3820#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
3821#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
3822#define CAN_F8R1_FB28_Pos (28U)
3823#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
3824#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
3825#define CAN_F8R1_FB29_Pos (29U)
3826#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
3827#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
3828#define CAN_F8R1_FB30_Pos (30U)
3829#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
3830#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
3831#define CAN_F8R1_FB31_Pos (31U)
3832#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
3833#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
3834
3835/******************* Bit definition for CAN_F9R1 register *******************/
3836#define CAN_F9R1_FB0_Pos (0U)
3837#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
3838#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
3839#define CAN_F9R1_FB1_Pos (1U)
3840#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
3841#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
3842#define CAN_F9R1_FB2_Pos (2U)
3843#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
3844#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
3845#define CAN_F9R1_FB3_Pos (3U)
3846#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
3847#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
3848#define CAN_F9R1_FB4_Pos (4U)
3849#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
3850#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
3851#define CAN_F9R1_FB5_Pos (5U)
3852#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
3853#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
3854#define CAN_F9R1_FB6_Pos (6U)
3855#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
3856#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
3857#define CAN_F9R1_FB7_Pos (7U)
3858#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
3859#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
3860#define CAN_F9R1_FB8_Pos (8U)
3861#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
3862#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
3863#define CAN_F9R1_FB9_Pos (9U)
3864#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
3865#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
3866#define CAN_F9R1_FB10_Pos (10U)
3867#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
3868#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
3869#define CAN_F9R1_FB11_Pos (11U)
3870#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
3871#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
3872#define CAN_F9R1_FB12_Pos (12U)
3873#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
3874#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
3875#define CAN_F9R1_FB13_Pos (13U)
3876#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
3877#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
3878#define CAN_F9R1_FB14_Pos (14U)
3879#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
3880#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
3881#define CAN_F9R1_FB15_Pos (15U)
3882#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
3883#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
3884#define CAN_F9R1_FB16_Pos (16U)
3885#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
3886#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
3887#define CAN_F9R1_FB17_Pos (17U)
3888#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
3889#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
3890#define CAN_F9R1_FB18_Pos (18U)
3891#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
3892#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
3893#define CAN_F9R1_FB19_Pos (19U)
3894#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
3895#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
3896#define CAN_F9R1_FB20_Pos (20U)
3897#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
3898#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
3899#define CAN_F9R1_FB21_Pos (21U)
3900#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
3901#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
3902#define CAN_F9R1_FB22_Pos (22U)
3903#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
3904#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
3905#define CAN_F9R1_FB23_Pos (23U)
3906#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
3907#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
3908#define CAN_F9R1_FB24_Pos (24U)
3909#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
3910#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
3911#define CAN_F9R1_FB25_Pos (25U)
3912#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
3913#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
3914#define CAN_F9R1_FB26_Pos (26U)
3915#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
3916#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
3917#define CAN_F9R1_FB27_Pos (27U)
3918#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
3919#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
3920#define CAN_F9R1_FB28_Pos (28U)
3921#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
3922#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
3923#define CAN_F9R1_FB29_Pos (29U)
3924#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
3925#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
3926#define CAN_F9R1_FB30_Pos (30U)
3927#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
3928#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
3929#define CAN_F9R1_FB31_Pos (31U)
3930#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
3931#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
3932
3933/******************* Bit definition for CAN_F10R1 register ******************/
3934#define CAN_F10R1_FB0_Pos (0U)
3935#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
3936#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
3937#define CAN_F10R1_FB1_Pos (1U)
3938#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
3939#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
3940#define CAN_F10R1_FB2_Pos (2U)
3941#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
3942#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
3943#define CAN_F10R1_FB3_Pos (3U)
3944#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
3945#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
3946#define CAN_F10R1_FB4_Pos (4U)
3947#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
3948#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
3949#define CAN_F10R1_FB5_Pos (5U)
3950#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
3951#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
3952#define CAN_F10R1_FB6_Pos (6U)
3953#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
3954#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
3955#define CAN_F10R1_FB7_Pos (7U)
3956#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
3957#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
3958#define CAN_F10R1_FB8_Pos (8U)
3959#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
3960#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
3961#define CAN_F10R1_FB9_Pos (9U)
3962#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
3963#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
3964#define CAN_F10R1_FB10_Pos (10U)
3965#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
3966#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
3967#define CAN_F10R1_FB11_Pos (11U)
3968#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
3969#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
3970#define CAN_F10R1_FB12_Pos (12U)
3971#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
3972#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
3973#define CAN_F10R1_FB13_Pos (13U)
3974#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
3975#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
3976#define CAN_F10R1_FB14_Pos (14U)
3977#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
3978#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
3979#define CAN_F10R1_FB15_Pos (15U)
3980#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
3981#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
3982#define CAN_F10R1_FB16_Pos (16U)
3983#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
3984#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
3985#define CAN_F10R1_FB17_Pos (17U)
3986#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
3987#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
3988#define CAN_F10R1_FB18_Pos (18U)
3989#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
3990#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
3991#define CAN_F10R1_FB19_Pos (19U)
3992#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
3993#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
3994#define CAN_F10R1_FB20_Pos (20U)
3995#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
3996#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
3997#define CAN_F10R1_FB21_Pos (21U)
3998#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
3999#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
4000#define CAN_F10R1_FB22_Pos (22U)
4001#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
4002#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
4003#define CAN_F10R1_FB23_Pos (23U)
4004#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
4005#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
4006#define CAN_F10R1_FB24_Pos (24U)
4007#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
4008#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
4009#define CAN_F10R1_FB25_Pos (25U)
4010#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
4011#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
4012#define CAN_F10R1_FB26_Pos (26U)
4013#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
4014#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
4015#define CAN_F10R1_FB27_Pos (27U)
4016#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
4017#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
4018#define CAN_F10R1_FB28_Pos (28U)
4019#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
4020#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
4021#define CAN_F10R1_FB29_Pos (29U)
4022#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
4023#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
4024#define CAN_F10R1_FB30_Pos (30U)
4025#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
4026#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
4027#define CAN_F10R1_FB31_Pos (31U)
4028#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
4029#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
4030
4031/******************* Bit definition for CAN_F11R1 register ******************/
4032#define CAN_F11R1_FB0_Pos (0U)
4033#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
4034#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
4035#define CAN_F11R1_FB1_Pos (1U)
4036#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
4037#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
4038#define CAN_F11R1_FB2_Pos (2U)
4039#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
4040#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
4041#define CAN_F11R1_FB3_Pos (3U)
4042#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
4043#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
4044#define CAN_F11R1_FB4_Pos (4U)
4045#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
4046#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
4047#define CAN_F11R1_FB5_Pos (5U)
4048#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
4049#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
4050#define CAN_F11R1_FB6_Pos (6U)
4051#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
4052#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
4053#define CAN_F11R1_FB7_Pos (7U)
4054#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
4055#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
4056#define CAN_F11R1_FB8_Pos (8U)
4057#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
4058#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
4059#define CAN_F11R1_FB9_Pos (9U)
4060#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
4061#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
4062#define CAN_F11R1_FB10_Pos (10U)
4063#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
4064#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
4065#define CAN_F11R1_FB11_Pos (11U)
4066#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
4067#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
4068#define CAN_F11R1_FB12_Pos (12U)
4069#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
4070#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
4071#define CAN_F11R1_FB13_Pos (13U)
4072#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
4073#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
4074#define CAN_F11R1_FB14_Pos (14U)
4075#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
4076#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
4077#define CAN_F11R1_FB15_Pos (15U)
4078#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
4079#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
4080#define CAN_F11R1_FB16_Pos (16U)
4081#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
4082#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
4083#define CAN_F11R1_FB17_Pos (17U)
4084#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
4085#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
4086#define CAN_F11R1_FB18_Pos (18U)
4087#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
4088#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
4089#define CAN_F11R1_FB19_Pos (19U)
4090#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
4091#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
4092#define CAN_F11R1_FB20_Pos (20U)
4093#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
4094#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
4095#define CAN_F11R1_FB21_Pos (21U)
4096#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
4097#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
4098#define CAN_F11R1_FB22_Pos (22U)
4099#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
4100#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
4101#define CAN_F11R1_FB23_Pos (23U)
4102#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
4103#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
4104#define CAN_F11R1_FB24_Pos (24U)
4105#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
4106#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
4107#define CAN_F11R1_FB25_Pos (25U)
4108#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
4109#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
4110#define CAN_F11R1_FB26_Pos (26U)
4111#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
4112#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
4113#define CAN_F11R1_FB27_Pos (27U)
4114#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
4115#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
4116#define CAN_F11R1_FB28_Pos (28U)
4117#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
4118#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
4119#define CAN_F11R1_FB29_Pos (29U)
4120#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
4121#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
4122#define CAN_F11R1_FB30_Pos (30U)
4123#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
4124#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
4125#define CAN_F11R1_FB31_Pos (31U)
4126#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
4127#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
4128
4129/******************* Bit definition for CAN_F12R1 register ******************/
4130#define CAN_F12R1_FB0_Pos (0U)
4131#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
4132#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
4133#define CAN_F12R1_FB1_Pos (1U)
4134#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
4135#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
4136#define CAN_F12R1_FB2_Pos (2U)
4137#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
4138#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
4139#define CAN_F12R1_FB3_Pos (3U)
4140#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
4141#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
4142#define CAN_F12R1_FB4_Pos (4U)
4143#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
4144#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
4145#define CAN_F12R1_FB5_Pos (5U)
4146#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
4147#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
4148#define CAN_F12R1_FB6_Pos (6U)
4149#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
4150#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
4151#define CAN_F12R1_FB7_Pos (7U)
4152#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
4153#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
4154#define CAN_F12R1_FB8_Pos (8U)
4155#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
4156#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
4157#define CAN_F12R1_FB9_Pos (9U)
4158#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
4159#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
4160#define CAN_F12R1_FB10_Pos (10U)
4161#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
4162#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
4163#define CAN_F12R1_FB11_Pos (11U)
4164#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
4165#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
4166#define CAN_F12R1_FB12_Pos (12U)
4167#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
4168#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
4169#define CAN_F12R1_FB13_Pos (13U)
4170#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
4171#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
4172#define CAN_F12R1_FB14_Pos (14U)
4173#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
4174#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
4175#define CAN_F12R1_FB15_Pos (15U)
4176#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
4177#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
4178#define CAN_F12R1_FB16_Pos (16U)
4179#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
4180#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
4181#define CAN_F12R1_FB17_Pos (17U)
4182#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
4183#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
4184#define CAN_F12R1_FB18_Pos (18U)
4185#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
4186#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
4187#define CAN_F12R1_FB19_Pos (19U)
4188#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
4189#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
4190#define CAN_F12R1_FB20_Pos (20U)
4191#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
4192#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
4193#define CAN_F12R1_FB21_Pos (21U)
4194#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
4195#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
4196#define CAN_F12R1_FB22_Pos (22U)
4197#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
4198#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
4199#define CAN_F12R1_FB23_Pos (23U)
4200#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
4201#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
4202#define CAN_F12R1_FB24_Pos (24U)
4203#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
4204#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
4205#define CAN_F12R1_FB25_Pos (25U)
4206#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
4207#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
4208#define CAN_F12R1_FB26_Pos (26U)
4209#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
4210#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
4211#define CAN_F12R1_FB27_Pos (27U)
4212#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
4213#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
4214#define CAN_F12R1_FB28_Pos (28U)
4215#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
4216#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
4217#define CAN_F12R1_FB29_Pos (29U)
4218#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
4219#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
4220#define CAN_F12R1_FB30_Pos (30U)
4221#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
4222#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
4223#define CAN_F12R1_FB31_Pos (31U)
4224#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
4225#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
4226
4227/******************* Bit definition for CAN_F13R1 register ******************/
4228#define CAN_F13R1_FB0_Pos (0U)
4229#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
4230#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
4231#define CAN_F13R1_FB1_Pos (1U)
4232#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
4233#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
4234#define CAN_F13R1_FB2_Pos (2U)
4235#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
4236#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
4237#define CAN_F13R1_FB3_Pos (3U)
4238#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
4239#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
4240#define CAN_F13R1_FB4_Pos (4U)
4241#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
4242#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
4243#define CAN_F13R1_FB5_Pos (5U)
4244#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
4245#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
4246#define CAN_F13R1_FB6_Pos (6U)
4247#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
4248#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
4249#define CAN_F13R1_FB7_Pos (7U)
4250#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
4251#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
4252#define CAN_F13R1_FB8_Pos (8U)
4253#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
4254#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
4255#define CAN_F13R1_FB9_Pos (9U)
4256#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
4257#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
4258#define CAN_F13R1_FB10_Pos (10U)
4259#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
4260#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
4261#define CAN_F13R1_FB11_Pos (11U)
4262#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
4263#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
4264#define CAN_F13R1_FB12_Pos (12U)
4265#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
4266#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
4267#define CAN_F13R1_FB13_Pos (13U)
4268#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
4269#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
4270#define CAN_F13R1_FB14_Pos (14U)
4271#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
4272#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
4273#define CAN_F13R1_FB15_Pos (15U)
4274#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
4275#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
4276#define CAN_F13R1_FB16_Pos (16U)
4277#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
4278#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
4279#define CAN_F13R1_FB17_Pos (17U)
4280#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
4281#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
4282#define CAN_F13R1_FB18_Pos (18U)
4283#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
4284#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
4285#define CAN_F13R1_FB19_Pos (19U)
4286#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
4287#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
4288#define CAN_F13R1_FB20_Pos (20U)
4289#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
4290#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
4291#define CAN_F13R1_FB21_Pos (21U)
4292#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
4293#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
4294#define CAN_F13R1_FB22_Pos (22U)
4295#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
4296#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
4297#define CAN_F13R1_FB23_Pos (23U)
4298#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
4299#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
4300#define CAN_F13R1_FB24_Pos (24U)
4301#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
4302#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
4303#define CAN_F13R1_FB25_Pos (25U)
4304#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
4305#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
4306#define CAN_F13R1_FB26_Pos (26U)
4307#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
4308#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
4309#define CAN_F13R1_FB27_Pos (27U)
4310#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
4311#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
4312#define CAN_F13R1_FB28_Pos (28U)
4313#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
4314#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
4315#define CAN_F13R1_FB29_Pos (29U)
4316#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
4317#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
4318#define CAN_F13R1_FB30_Pos (30U)
4319#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
4320#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
4321#define CAN_F13R1_FB31_Pos (31U)
4322#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
4323#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
4324
4325/******************* Bit definition for CAN_F0R2 register *******************/
4326#define CAN_F0R2_FB0_Pos (0U)
4327#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
4328#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
4329#define CAN_F0R2_FB1_Pos (1U)
4330#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
4331#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
4332#define CAN_F0R2_FB2_Pos (2U)
4333#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
4334#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
4335#define CAN_F0R2_FB3_Pos (3U)
4336#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
4337#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
4338#define CAN_F0R2_FB4_Pos (4U)
4339#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
4340#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
4341#define CAN_F0R2_FB5_Pos (5U)
4342#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
4343#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
4344#define CAN_F0R2_FB6_Pos (6U)
4345#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
4346#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
4347#define CAN_F0R2_FB7_Pos (7U)
4348#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
4349#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
4350#define CAN_F0R2_FB8_Pos (8U)
4351#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
4352#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
4353#define CAN_F0R2_FB9_Pos (9U)
4354#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
4355#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
4356#define CAN_F0R2_FB10_Pos (10U)
4357#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
4358#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
4359#define CAN_F0R2_FB11_Pos (11U)
4360#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
4361#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
4362#define CAN_F0R2_FB12_Pos (12U)
4363#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
4364#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
4365#define CAN_F0R2_FB13_Pos (13U)
4366#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
4367#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
4368#define CAN_F0R2_FB14_Pos (14U)
4369#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
4370#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
4371#define CAN_F0R2_FB15_Pos (15U)
4372#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
4373#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
4374#define CAN_F0R2_FB16_Pos (16U)
4375#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
4376#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
4377#define CAN_F0R2_FB17_Pos (17U)
4378#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
4379#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
4380#define CAN_F0R2_FB18_Pos (18U)
4381#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
4382#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
4383#define CAN_F0R2_FB19_Pos (19U)
4384#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
4385#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
4386#define CAN_F0R2_FB20_Pos (20U)
4387#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
4388#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
4389#define CAN_F0R2_FB21_Pos (21U)
4390#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
4391#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
4392#define CAN_F0R2_FB22_Pos (22U)
4393#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
4394#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
4395#define CAN_F0R2_FB23_Pos (23U)
4396#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
4397#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
4398#define CAN_F0R2_FB24_Pos (24U)
4399#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
4400#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
4401#define CAN_F0R2_FB25_Pos (25U)
4402#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
4403#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
4404#define CAN_F0R2_FB26_Pos (26U)
4405#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
4406#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
4407#define CAN_F0R2_FB27_Pos (27U)
4408#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
4409#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
4410#define CAN_F0R2_FB28_Pos (28U)
4411#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
4412#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
4413#define CAN_F0R2_FB29_Pos (29U)
4414#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
4415#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
4416#define CAN_F0R2_FB30_Pos (30U)
4417#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
4418#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
4419#define CAN_F0R2_FB31_Pos (31U)
4420#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
4421#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
4422
4423/******************* Bit definition for CAN_F1R2 register *******************/
4424#define CAN_F1R2_FB0_Pos (0U)
4425#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
4426#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
4427#define CAN_F1R2_FB1_Pos (1U)
4428#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
4429#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
4430#define CAN_F1R2_FB2_Pos (2U)
4431#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
4432#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
4433#define CAN_F1R2_FB3_Pos (3U)
4434#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
4435#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
4436#define CAN_F1R2_FB4_Pos (4U)
4437#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
4438#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
4439#define CAN_F1R2_FB5_Pos (5U)
4440#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
4441#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
4442#define CAN_F1R2_FB6_Pos (6U)
4443#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
4444#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
4445#define CAN_F1R2_FB7_Pos (7U)
4446#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
4447#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
4448#define CAN_F1R2_FB8_Pos (8U)
4449#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
4450#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
4451#define CAN_F1R2_FB9_Pos (9U)
4452#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
4453#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
4454#define CAN_F1R2_FB10_Pos (10U)
4455#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
4456#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
4457#define CAN_F1R2_FB11_Pos (11U)
4458#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
4459#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
4460#define CAN_F1R2_FB12_Pos (12U)
4461#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
4462#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
4463#define CAN_F1R2_FB13_Pos (13U)
4464#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
4465#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
4466#define CAN_F1R2_FB14_Pos (14U)
4467#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
4468#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
4469#define CAN_F1R2_FB15_Pos (15U)
4470#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
4471#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
4472#define CAN_F1R2_FB16_Pos (16U)
4473#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
4474#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
4475#define CAN_F1R2_FB17_Pos (17U)
4476#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
4477#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
4478#define CAN_F1R2_FB18_Pos (18U)
4479#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
4480#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
4481#define CAN_F1R2_FB19_Pos (19U)
4482#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
4483#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
4484#define CAN_F1R2_FB20_Pos (20U)
4485#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
4486#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
4487#define CAN_F1R2_FB21_Pos (21U)
4488#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
4489#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
4490#define CAN_F1R2_FB22_Pos (22U)
4491#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
4492#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
4493#define CAN_F1R2_FB23_Pos (23U)
4494#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
4495#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
4496#define CAN_F1R2_FB24_Pos (24U)
4497#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
4498#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
4499#define CAN_F1R2_FB25_Pos (25U)
4500#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
4501#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
4502#define CAN_F1R2_FB26_Pos (26U)
4503#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
4504#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
4505#define CAN_F1R2_FB27_Pos (27U)
4506#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
4507#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
4508#define CAN_F1R2_FB28_Pos (28U)
4509#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
4510#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
4511#define CAN_F1R2_FB29_Pos (29U)
4512#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
4513#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
4514#define CAN_F1R2_FB30_Pos (30U)
4515#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
4516#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
4517#define CAN_F1R2_FB31_Pos (31U)
4518#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
4519#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
4520
4521/******************* Bit definition for CAN_F2R2 register *******************/
4522#define CAN_F2R2_FB0_Pos (0U)
4523#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
4524#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
4525#define CAN_F2R2_FB1_Pos (1U)
4526#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
4527#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
4528#define CAN_F2R2_FB2_Pos (2U)
4529#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
4530#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
4531#define CAN_F2R2_FB3_Pos (3U)
4532#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
4533#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
4534#define CAN_F2R2_FB4_Pos (4U)
4535#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
4536#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
4537#define CAN_F2R2_FB5_Pos (5U)
4538#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
4539#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
4540#define CAN_F2R2_FB6_Pos (6U)
4541#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
4542#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
4543#define CAN_F2R2_FB7_Pos (7U)
4544#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
4545#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
4546#define CAN_F2R2_FB8_Pos (8U)
4547#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
4548#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
4549#define CAN_F2R2_FB9_Pos (9U)
4550#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
4551#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
4552#define CAN_F2R2_FB10_Pos (10U)
4553#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
4554#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
4555#define CAN_F2R2_FB11_Pos (11U)
4556#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
4557#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
4558#define CAN_F2R2_FB12_Pos (12U)
4559#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
4560#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
4561#define CAN_F2R2_FB13_Pos (13U)
4562#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
4563#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
4564#define CAN_F2R2_FB14_Pos (14U)
4565#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
4566#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
4567#define CAN_F2R2_FB15_Pos (15U)
4568#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
4569#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
4570#define CAN_F2R2_FB16_Pos (16U)
4571#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
4572#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
4573#define CAN_F2R2_FB17_Pos (17U)
4574#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
4575#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
4576#define CAN_F2R2_FB18_Pos (18U)
4577#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
4578#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
4579#define CAN_F2R2_FB19_Pos (19U)
4580#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
4581#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
4582#define CAN_F2R2_FB20_Pos (20U)
4583#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
4584#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
4585#define CAN_F2R2_FB21_Pos (21U)
4586#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
4587#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
4588#define CAN_F2R2_FB22_Pos (22U)
4589#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
4590#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
4591#define CAN_F2R2_FB23_Pos (23U)
4592#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
4593#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
4594#define CAN_F2R2_FB24_Pos (24U)
4595#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
4596#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
4597#define CAN_F2R2_FB25_Pos (25U)
4598#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
4599#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
4600#define CAN_F2R2_FB26_Pos (26U)
4601#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
4602#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
4603#define CAN_F2R2_FB27_Pos (27U)
4604#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
4605#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
4606#define CAN_F2R2_FB28_Pos (28U)
4607#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
4608#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
4609#define CAN_F2R2_FB29_Pos (29U)
4610#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
4611#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
4612#define CAN_F2R2_FB30_Pos (30U)
4613#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
4614#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
4615#define CAN_F2R2_FB31_Pos (31U)
4616#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
4617#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
4618
4619/******************* Bit definition for CAN_F3R2 register *******************/
4620#define CAN_F3R2_FB0_Pos (0U)
4621#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
4622#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
4623#define CAN_F3R2_FB1_Pos (1U)
4624#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
4625#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
4626#define CAN_F3R2_FB2_Pos (2U)
4627#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
4628#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
4629#define CAN_F3R2_FB3_Pos (3U)
4630#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
4631#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
4632#define CAN_F3R2_FB4_Pos (4U)
4633#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
4634#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
4635#define CAN_F3R2_FB5_Pos (5U)
4636#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
4637#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
4638#define CAN_F3R2_FB6_Pos (6U)
4639#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
4640#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
4641#define CAN_F3R2_FB7_Pos (7U)
4642#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
4643#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
4644#define CAN_F3R2_FB8_Pos (8U)
4645#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
4646#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
4647#define CAN_F3R2_FB9_Pos (9U)
4648#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
4649#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
4650#define CAN_F3R2_FB10_Pos (10U)
4651#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
4652#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
4653#define CAN_F3R2_FB11_Pos (11U)
4654#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
4655#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
4656#define CAN_F3R2_FB12_Pos (12U)
4657#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
4658#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
4659#define CAN_F3R2_FB13_Pos (13U)
4660#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
4661#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
4662#define CAN_F3R2_FB14_Pos (14U)
4663#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
4664#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
4665#define CAN_F3R2_FB15_Pos (15U)
4666#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
4667#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
4668#define CAN_F3R2_FB16_Pos (16U)
4669#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
4670#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
4671#define CAN_F3R2_FB17_Pos (17U)
4672#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
4673#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
4674#define CAN_F3R2_FB18_Pos (18U)
4675#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
4676#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
4677#define CAN_F3R2_FB19_Pos (19U)
4678#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
4679#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
4680#define CAN_F3R2_FB20_Pos (20U)
4681#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
4682#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
4683#define CAN_F3R2_FB21_Pos (21U)
4684#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
4685#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
4686#define CAN_F3R2_FB22_Pos (22U)
4687#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
4688#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
4689#define CAN_F3R2_FB23_Pos (23U)
4690#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
4691#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
4692#define CAN_F3R2_FB24_Pos (24U)
4693#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
4694#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
4695#define CAN_F3R2_FB25_Pos (25U)
4696#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
4697#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
4698#define CAN_F3R2_FB26_Pos (26U)
4699#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
4700#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
4701#define CAN_F3R2_FB27_Pos (27U)
4702#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
4703#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
4704#define CAN_F3R2_FB28_Pos (28U)
4705#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
4706#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
4707#define CAN_F3R2_FB29_Pos (29U)
4708#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
4709#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
4710#define CAN_F3R2_FB30_Pos (30U)
4711#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
4712#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
4713#define CAN_F3R2_FB31_Pos (31U)
4714#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
4715#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
4716
4717/******************* Bit definition for CAN_F4R2 register *******************/
4718#define CAN_F4R2_FB0_Pos (0U)
4719#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
4720#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
4721#define CAN_F4R2_FB1_Pos (1U)
4722#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
4723#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
4724#define CAN_F4R2_FB2_Pos (2U)
4725#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
4726#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
4727#define CAN_F4R2_FB3_Pos (3U)
4728#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
4729#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
4730#define CAN_F4R2_FB4_Pos (4U)
4731#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
4732#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
4733#define CAN_F4R2_FB5_Pos (5U)
4734#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
4735#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
4736#define CAN_F4R2_FB6_Pos (6U)
4737#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
4738#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
4739#define CAN_F4R2_FB7_Pos (7U)
4740#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
4741#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
4742#define CAN_F4R2_FB8_Pos (8U)
4743#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
4744#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
4745#define CAN_F4R2_FB9_Pos (9U)
4746#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
4747#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
4748#define CAN_F4R2_FB10_Pos (10U)
4749#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
4750#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
4751#define CAN_F4R2_FB11_Pos (11U)
4752#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
4753#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
4754#define CAN_F4R2_FB12_Pos (12U)
4755#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
4756#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
4757#define CAN_F4R2_FB13_Pos (13U)
4758#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
4759#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
4760#define CAN_F4R2_FB14_Pos (14U)
4761#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
4762#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
4763#define CAN_F4R2_FB15_Pos (15U)
4764#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
4765#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
4766#define CAN_F4R2_FB16_Pos (16U)
4767#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
4768#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
4769#define CAN_F4R2_FB17_Pos (17U)
4770#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
4771#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
4772#define CAN_F4R2_FB18_Pos (18U)
4773#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
4774#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
4775#define CAN_F4R2_FB19_Pos (19U)
4776#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
4777#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
4778#define CAN_F4R2_FB20_Pos (20U)
4779#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
4780#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
4781#define CAN_F4R2_FB21_Pos (21U)
4782#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
4783#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
4784#define CAN_F4R2_FB22_Pos (22U)
4785#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
4786#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
4787#define CAN_F4R2_FB23_Pos (23U)
4788#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
4789#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
4790#define CAN_F4R2_FB24_Pos (24U)
4791#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
4792#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
4793#define CAN_F4R2_FB25_Pos (25U)
4794#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
4795#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
4796#define CAN_F4R2_FB26_Pos (26U)
4797#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
4798#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
4799#define CAN_F4R2_FB27_Pos (27U)
4800#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
4801#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
4802#define CAN_F4R2_FB28_Pos (28U)
4803#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
4804#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
4805#define CAN_F4R2_FB29_Pos (29U)
4806#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
4807#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
4808#define CAN_F4R2_FB30_Pos (30U)
4809#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
4810#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
4811#define CAN_F4R2_FB31_Pos (31U)
4812#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
4813#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
4814
4815/******************* Bit definition for CAN_F5R2 register *******************/
4816#define CAN_F5R2_FB0_Pos (0U)
4817#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
4818#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
4819#define CAN_F5R2_FB1_Pos (1U)
4820#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
4821#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
4822#define CAN_F5R2_FB2_Pos (2U)
4823#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
4824#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
4825#define CAN_F5R2_FB3_Pos (3U)
4826#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
4827#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
4828#define CAN_F5R2_FB4_Pos (4U)
4829#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
4830#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
4831#define CAN_F5R2_FB5_Pos (5U)
4832#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
4833#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
4834#define CAN_F5R2_FB6_Pos (6U)
4835#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
4836#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
4837#define CAN_F5R2_FB7_Pos (7U)
4838#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
4839#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
4840#define CAN_F5R2_FB8_Pos (8U)
4841#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
4842#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
4843#define CAN_F5R2_FB9_Pos (9U)
4844#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
4845#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
4846#define CAN_F5R2_FB10_Pos (10U)
4847#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
4848#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
4849#define CAN_F5R2_FB11_Pos (11U)
4850#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
4851#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
4852#define CAN_F5R2_FB12_Pos (12U)
4853#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
4854#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
4855#define CAN_F5R2_FB13_Pos (13U)
4856#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
4857#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
4858#define CAN_F5R2_FB14_Pos (14U)
4859#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
4860#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
4861#define CAN_F5R2_FB15_Pos (15U)
4862#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
4863#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
4864#define CAN_F5R2_FB16_Pos (16U)
4865#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
4866#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
4867#define CAN_F5R2_FB17_Pos (17U)
4868#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
4869#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
4870#define CAN_F5R2_FB18_Pos (18U)
4871#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
4872#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
4873#define CAN_F5R2_FB19_Pos (19U)
4874#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
4875#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
4876#define CAN_F5R2_FB20_Pos (20U)
4877#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
4878#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
4879#define CAN_F5R2_FB21_Pos (21U)
4880#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
4881#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
4882#define CAN_F5R2_FB22_Pos (22U)
4883#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
4884#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
4885#define CAN_F5R2_FB23_Pos (23U)
4886#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
4887#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
4888#define CAN_F5R2_FB24_Pos (24U)
4889#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
4890#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
4891#define CAN_F5R2_FB25_Pos (25U)
4892#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
4893#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
4894#define CAN_F5R2_FB26_Pos (26U)
4895#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
4896#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
4897#define CAN_F5R2_FB27_Pos (27U)
4898#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
4899#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
4900#define CAN_F5R2_FB28_Pos (28U)
4901#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
4902#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
4903#define CAN_F5R2_FB29_Pos (29U)
4904#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
4905#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
4906#define CAN_F5R2_FB30_Pos (30U)
4907#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
4908#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
4909#define CAN_F5R2_FB31_Pos (31U)
4910#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
4911#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
4912
4913/******************* Bit definition for CAN_F6R2 register *******************/
4914#define CAN_F6R2_FB0_Pos (0U)
4915#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
4916#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
4917#define CAN_F6R2_FB1_Pos (1U)
4918#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
4919#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
4920#define CAN_F6R2_FB2_Pos (2U)
4921#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
4922#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
4923#define CAN_F6R2_FB3_Pos (3U)
4924#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
4925#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
4926#define CAN_F6R2_FB4_Pos (4U)
4927#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
4928#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
4929#define CAN_F6R2_FB5_Pos (5U)
4930#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
4931#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
4932#define CAN_F6R2_FB6_Pos (6U)
4933#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
4934#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
4935#define CAN_F6R2_FB7_Pos (7U)
4936#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
4937#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
4938#define CAN_F6R2_FB8_Pos (8U)
4939#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
4940#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
4941#define CAN_F6R2_FB9_Pos (9U)
4942#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
4943#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
4944#define CAN_F6R2_FB10_Pos (10U)
4945#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
4946#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
4947#define CAN_F6R2_FB11_Pos (11U)
4948#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
4949#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
4950#define CAN_F6R2_FB12_Pos (12U)
4951#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
4952#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
4953#define CAN_F6R2_FB13_Pos (13U)
4954#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
4955#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
4956#define CAN_F6R2_FB14_Pos (14U)
4957#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
4958#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
4959#define CAN_F6R2_FB15_Pos (15U)
4960#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
4961#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
4962#define CAN_F6R2_FB16_Pos (16U)
4963#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
4964#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
4965#define CAN_F6R2_FB17_Pos (17U)
4966#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
4967#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
4968#define CAN_F6R2_FB18_Pos (18U)
4969#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
4970#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
4971#define CAN_F6R2_FB19_Pos (19U)
4972#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
4973#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
4974#define CAN_F6R2_FB20_Pos (20U)
4975#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
4976#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
4977#define CAN_F6R2_FB21_Pos (21U)
4978#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
4979#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
4980#define CAN_F6R2_FB22_Pos (22U)
4981#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
4982#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
4983#define CAN_F6R2_FB23_Pos (23U)
4984#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
4985#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
4986#define CAN_F6R2_FB24_Pos (24U)
4987#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
4988#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
4989#define CAN_F6R2_FB25_Pos (25U)
4990#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
4991#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
4992#define CAN_F6R2_FB26_Pos (26U)
4993#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
4994#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
4995#define CAN_F6R2_FB27_Pos (27U)
4996#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
4997#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
4998#define CAN_F6R2_FB28_Pos (28U)
4999#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
5000#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
5001#define CAN_F6R2_FB29_Pos (29U)
5002#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
5003#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
5004#define CAN_F6R2_FB30_Pos (30U)
5005#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
5006#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
5007#define CAN_F6R2_FB31_Pos (31U)
5008#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
5009#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
5010
5011/******************* Bit definition for CAN_F7R2 register *******************/
5012#define CAN_F7R2_FB0_Pos (0U)
5013#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
5014#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
5015#define CAN_F7R2_FB1_Pos (1U)
5016#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
5017#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
5018#define CAN_F7R2_FB2_Pos (2U)
5019#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
5020#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
5021#define CAN_F7R2_FB3_Pos (3U)
5022#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
5023#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
5024#define CAN_F7R2_FB4_Pos (4U)
5025#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
5026#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
5027#define CAN_F7R2_FB5_Pos (5U)
5028#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
5029#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
5030#define CAN_F7R2_FB6_Pos (6U)
5031#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
5032#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
5033#define CAN_F7R2_FB7_Pos (7U)
5034#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
5035#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
5036#define CAN_F7R2_FB8_Pos (8U)
5037#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
5038#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
5039#define CAN_F7R2_FB9_Pos (9U)
5040#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
5041#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
5042#define CAN_F7R2_FB10_Pos (10U)
5043#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
5044#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
5045#define CAN_F7R2_FB11_Pos (11U)
5046#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
5047#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
5048#define CAN_F7R2_FB12_Pos (12U)
5049#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
5050#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
5051#define CAN_F7R2_FB13_Pos (13U)
5052#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
5053#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
5054#define CAN_F7R2_FB14_Pos (14U)
5055#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
5056#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
5057#define CAN_F7R2_FB15_Pos (15U)
5058#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
5059#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
5060#define CAN_F7R2_FB16_Pos (16U)
5061#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
5062#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
5063#define CAN_F7R2_FB17_Pos (17U)
5064#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
5065#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
5066#define CAN_F7R2_FB18_Pos (18U)
5067#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
5068#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
5069#define CAN_F7R2_FB19_Pos (19U)
5070#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
5071#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
5072#define CAN_F7R2_FB20_Pos (20U)
5073#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
5074#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
5075#define CAN_F7R2_FB21_Pos (21U)
5076#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
5077#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
5078#define CAN_F7R2_FB22_Pos (22U)
5079#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
5080#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
5081#define CAN_F7R2_FB23_Pos (23U)
5082#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
5083#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
5084#define CAN_F7R2_FB24_Pos (24U)
5085#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
5086#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
5087#define CAN_F7R2_FB25_Pos (25U)
5088#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
5089#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
5090#define CAN_F7R2_FB26_Pos (26U)
5091#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
5092#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
5093#define CAN_F7R2_FB27_Pos (27U)
5094#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
5095#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
5096#define CAN_F7R2_FB28_Pos (28U)
5097#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
5098#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
5099#define CAN_F7R2_FB29_Pos (29U)
5100#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
5101#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
5102#define CAN_F7R2_FB30_Pos (30U)
5103#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
5104#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
5105#define CAN_F7R2_FB31_Pos (31U)
5106#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
5107#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
5108
5109/******************* Bit definition for CAN_F8R2 register *******************/
5110#define CAN_F8R2_FB0_Pos (0U)
5111#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
5112#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
5113#define CAN_F8R2_FB1_Pos (1U)
5114#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
5115#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
5116#define CAN_F8R2_FB2_Pos (2U)
5117#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
5118#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
5119#define CAN_F8R2_FB3_Pos (3U)
5120#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
5121#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
5122#define CAN_F8R2_FB4_Pos (4U)
5123#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
5124#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
5125#define CAN_F8R2_FB5_Pos (5U)
5126#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
5127#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
5128#define CAN_F8R2_FB6_Pos (6U)
5129#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
5130#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
5131#define CAN_F8R2_FB7_Pos (7U)
5132#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
5133#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
5134#define CAN_F8R2_FB8_Pos (8U)
5135#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
5136#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
5137#define CAN_F8R2_FB9_Pos (9U)
5138#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
5139#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
5140#define CAN_F8R2_FB10_Pos (10U)
5141#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
5142#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
5143#define CAN_F8R2_FB11_Pos (11U)
5144#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
5145#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
5146#define CAN_F8R2_FB12_Pos (12U)
5147#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
5148#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
5149#define CAN_F8R2_FB13_Pos (13U)
5150#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
5151#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
5152#define CAN_F8R2_FB14_Pos (14U)
5153#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
5154#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
5155#define CAN_F8R2_FB15_Pos (15U)
5156#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
5157#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
5158#define CAN_F8R2_FB16_Pos (16U)
5159#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
5160#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
5161#define CAN_F8R2_FB17_Pos (17U)
5162#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
5163#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
5164#define CAN_F8R2_FB18_Pos (18U)
5165#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
5166#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
5167#define CAN_F8R2_FB19_Pos (19U)
5168#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
5169#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
5170#define CAN_F8R2_FB20_Pos (20U)
5171#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
5172#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
5173#define CAN_F8R2_FB21_Pos (21U)
5174#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
5175#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
5176#define CAN_F8R2_FB22_Pos (22U)
5177#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
5178#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
5179#define CAN_F8R2_FB23_Pos (23U)
5180#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
5181#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
5182#define CAN_F8R2_FB24_Pos (24U)
5183#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
5184#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
5185#define CAN_F8R2_FB25_Pos (25U)
5186#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
5187#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
5188#define CAN_F8R2_FB26_Pos (26U)
5189#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
5190#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
5191#define CAN_F8R2_FB27_Pos (27U)
5192#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
5193#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
5194#define CAN_F8R2_FB28_Pos (28U)
5195#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
5196#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
5197#define CAN_F8R2_FB29_Pos (29U)
5198#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
5199#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
5200#define CAN_F8R2_FB30_Pos (30U)
5201#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
5202#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
5203#define CAN_F8R2_FB31_Pos (31U)
5204#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
5205#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
5206
5207/******************* Bit definition for CAN_F9R2 register *******************/
5208#define CAN_F9R2_FB0_Pos (0U)
5209#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
5210#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
5211#define CAN_F9R2_FB1_Pos (1U)
5212#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
5213#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
5214#define CAN_F9R2_FB2_Pos (2U)
5215#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
5216#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
5217#define CAN_F9R2_FB3_Pos (3U)
5218#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
5219#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
5220#define CAN_F9R2_FB4_Pos (4U)
5221#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
5222#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
5223#define CAN_F9R2_FB5_Pos (5U)
5224#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
5225#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
5226#define CAN_F9R2_FB6_Pos (6U)
5227#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
5228#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
5229#define CAN_F9R2_FB7_Pos (7U)
5230#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
5231#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
5232#define CAN_F9R2_FB8_Pos (8U)
5233#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
5234#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
5235#define CAN_F9R2_FB9_Pos (9U)
5236#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
5237#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
5238#define CAN_F9R2_FB10_Pos (10U)
5239#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
5240#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
5241#define CAN_F9R2_FB11_Pos (11U)
5242#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
5243#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
5244#define CAN_F9R2_FB12_Pos (12U)
5245#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
5246#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
5247#define CAN_F9R2_FB13_Pos (13U)
5248#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
5249#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
5250#define CAN_F9R2_FB14_Pos (14U)
5251#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
5252#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
5253#define CAN_F9R2_FB15_Pos (15U)
5254#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
5255#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
5256#define CAN_F9R2_FB16_Pos (16U)
5257#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
5258#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
5259#define CAN_F9R2_FB17_Pos (17U)
5260#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
5261#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
5262#define CAN_F9R2_FB18_Pos (18U)
5263#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
5264#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
5265#define CAN_F9R2_FB19_Pos (19U)
5266#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
5267#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
5268#define CAN_F9R2_FB20_Pos (20U)
5269#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
5270#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
5271#define CAN_F9R2_FB21_Pos (21U)
5272#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
5273#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
5274#define CAN_F9R2_FB22_Pos (22U)
5275#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
5276#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
5277#define CAN_F9R2_FB23_Pos (23U)
5278#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
5279#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
5280#define CAN_F9R2_FB24_Pos (24U)
5281#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
5282#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
5283#define CAN_F9R2_FB25_Pos (25U)
5284#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
5285#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
5286#define CAN_F9R2_FB26_Pos (26U)
5287#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
5288#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
5289#define CAN_F9R2_FB27_Pos (27U)
5290#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
5291#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
5292#define CAN_F9R2_FB28_Pos (28U)
5293#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
5294#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
5295#define CAN_F9R2_FB29_Pos (29U)
5296#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
5297#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
5298#define CAN_F9R2_FB30_Pos (30U)
5299#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
5300#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
5301#define CAN_F9R2_FB31_Pos (31U)
5302#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
5303#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
5304
5305/******************* Bit definition for CAN_F10R2 register ******************/
5306#define CAN_F10R2_FB0_Pos (0U)
5307#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
5308#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
5309#define CAN_F10R2_FB1_Pos (1U)
5310#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
5311#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
5312#define CAN_F10R2_FB2_Pos (2U)
5313#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
5314#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
5315#define CAN_F10R2_FB3_Pos (3U)
5316#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
5317#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
5318#define CAN_F10R2_FB4_Pos (4U)
5319#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
5320#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
5321#define CAN_F10R2_FB5_Pos (5U)
5322#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
5323#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
5324#define CAN_F10R2_FB6_Pos (6U)
5325#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
5326#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
5327#define CAN_F10R2_FB7_Pos (7U)
5328#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
5329#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
5330#define CAN_F10R2_FB8_Pos (8U)
5331#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
5332#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
5333#define CAN_F10R2_FB9_Pos (9U)
5334#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
5335#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
5336#define CAN_F10R2_FB10_Pos (10U)
5337#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
5338#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
5339#define CAN_F10R2_FB11_Pos (11U)
5340#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
5341#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
5342#define CAN_F10R2_FB12_Pos (12U)
5343#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
5344#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
5345#define CAN_F10R2_FB13_Pos (13U)
5346#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
5347#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
5348#define CAN_F10R2_FB14_Pos (14U)
5349#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
5350#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
5351#define CAN_F10R2_FB15_Pos (15U)
5352#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
5353#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
5354#define CAN_F10R2_FB16_Pos (16U)
5355#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
5356#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
5357#define CAN_F10R2_FB17_Pos (17U)
5358#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
5359#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
5360#define CAN_F10R2_FB18_Pos (18U)
5361#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
5362#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
5363#define CAN_F10R2_FB19_Pos (19U)
5364#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
5365#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
5366#define CAN_F10R2_FB20_Pos (20U)
5367#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
5368#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
5369#define CAN_F10R2_FB21_Pos (21U)
5370#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
5371#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
5372#define CAN_F10R2_FB22_Pos (22U)
5373#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
5374#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
5375#define CAN_F10R2_FB23_Pos (23U)
5376#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
5377#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
5378#define CAN_F10R2_FB24_Pos (24U)
5379#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
5380#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
5381#define CAN_F10R2_FB25_Pos (25U)
5382#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
5383#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
5384#define CAN_F10R2_FB26_Pos (26U)
5385#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
5386#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
5387#define CAN_F10R2_FB27_Pos (27U)
5388#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
5389#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
5390#define CAN_F10R2_FB28_Pos (28U)
5391#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
5392#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
5393#define CAN_F10R2_FB29_Pos (29U)
5394#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
5395#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
5396#define CAN_F10R2_FB30_Pos (30U)
5397#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
5398#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
5399#define CAN_F10R2_FB31_Pos (31U)
5400#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
5401#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
5402
5403/******************* Bit definition for CAN_F11R2 register ******************/
5404#define CAN_F11R2_FB0_Pos (0U)
5405#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
5406#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
5407#define CAN_F11R2_FB1_Pos (1U)
5408#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
5409#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
5410#define CAN_F11R2_FB2_Pos (2U)
5411#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
5412#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
5413#define CAN_F11R2_FB3_Pos (3U)
5414#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
5415#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
5416#define CAN_F11R2_FB4_Pos (4U)
5417#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
5418#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
5419#define CAN_F11R2_FB5_Pos (5U)
5420#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
5421#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
5422#define CAN_F11R2_FB6_Pos (6U)
5423#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
5424#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
5425#define CAN_F11R2_FB7_Pos (7U)
5426#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
5427#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
5428#define CAN_F11R2_FB8_Pos (8U)
5429#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
5430#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
5431#define CAN_F11R2_FB9_Pos (9U)
5432#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
5433#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
5434#define CAN_F11R2_FB10_Pos (10U)
5435#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
5436#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
5437#define CAN_F11R2_FB11_Pos (11U)
5438#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
5439#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
5440#define CAN_F11R2_FB12_Pos (12U)
5441#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
5442#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
5443#define CAN_F11R2_FB13_Pos (13U)
5444#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
5445#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
5446#define CAN_F11R2_FB14_Pos (14U)
5447#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
5448#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
5449#define CAN_F11R2_FB15_Pos (15U)
5450#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
5451#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
5452#define CAN_F11R2_FB16_Pos (16U)
5453#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
5454#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
5455#define CAN_F11R2_FB17_Pos (17U)
5456#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
5457#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
5458#define CAN_F11R2_FB18_Pos (18U)
5459#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
5460#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
5461#define CAN_F11R2_FB19_Pos (19U)
5462#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
5463#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
5464#define CAN_F11R2_FB20_Pos (20U)
5465#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
5466#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
5467#define CAN_F11R2_FB21_Pos (21U)
5468#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
5469#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
5470#define CAN_F11R2_FB22_Pos (22U)
5471#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
5472#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
5473#define CAN_F11R2_FB23_Pos (23U)
5474#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
5475#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
5476#define CAN_F11R2_FB24_Pos (24U)
5477#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
5478#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
5479#define CAN_F11R2_FB25_Pos (25U)
5480#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
5481#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
5482#define CAN_F11R2_FB26_Pos (26U)
5483#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
5484#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
5485#define CAN_F11R2_FB27_Pos (27U)
5486#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
5487#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
5488#define CAN_F11R2_FB28_Pos (28U)
5489#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
5490#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
5491#define CAN_F11R2_FB29_Pos (29U)
5492#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
5493#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
5494#define CAN_F11R2_FB30_Pos (30U)
5495#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
5496#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
5497#define CAN_F11R2_FB31_Pos (31U)
5498#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
5499#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
5500
5501/******************* Bit definition for CAN_F12R2 register ******************/
5502#define CAN_F12R2_FB0_Pos (0U)
5503#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
5504#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
5505#define CAN_F12R2_FB1_Pos (1U)
5506#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
5507#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
5508#define CAN_F12R2_FB2_Pos (2U)
5509#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
5510#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
5511#define CAN_F12R2_FB3_Pos (3U)
5512#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
5513#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
5514#define CAN_F12R2_FB4_Pos (4U)
5515#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
5516#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
5517#define CAN_F12R2_FB5_Pos (5U)
5518#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
5519#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
5520#define CAN_F12R2_FB6_Pos (6U)
5521#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
5522#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
5523#define CAN_F12R2_FB7_Pos (7U)
5524#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
5525#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
5526#define CAN_F12R2_FB8_Pos (8U)
5527#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
5528#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
5529#define CAN_F12R2_FB9_Pos (9U)
5530#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
5531#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
5532#define CAN_F12R2_FB10_Pos (10U)
5533#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
5534#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
5535#define CAN_F12R2_FB11_Pos (11U)
5536#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
5537#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
5538#define CAN_F12R2_FB12_Pos (12U)
5539#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
5540#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
5541#define CAN_F12R2_FB13_Pos (13U)
5542#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
5543#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
5544#define CAN_F12R2_FB14_Pos (14U)
5545#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
5546#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
5547#define CAN_F12R2_FB15_Pos (15U)
5548#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
5549#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
5550#define CAN_F12R2_FB16_Pos (16U)
5551#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
5552#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
5553#define CAN_F12R2_FB17_Pos (17U)
5554#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
5555#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
5556#define CAN_F12R2_FB18_Pos (18U)
5557#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
5558#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
5559#define CAN_F12R2_FB19_Pos (19U)
5560#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
5561#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
5562#define CAN_F12R2_FB20_Pos (20U)
5563#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
5564#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
5565#define CAN_F12R2_FB21_Pos (21U)
5566#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
5567#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
5568#define CAN_F12R2_FB22_Pos (22U)
5569#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
5570#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
5571#define CAN_F12R2_FB23_Pos (23U)
5572#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
5573#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
5574#define CAN_F12R2_FB24_Pos (24U)
5575#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
5576#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
5577#define CAN_F12R2_FB25_Pos (25U)
5578#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
5579#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
5580#define CAN_F12R2_FB26_Pos (26U)
5581#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
5582#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
5583#define CAN_F12R2_FB27_Pos (27U)
5584#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
5585#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
5586#define CAN_F12R2_FB28_Pos (28U)
5587#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
5588#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
5589#define CAN_F12R2_FB29_Pos (29U)
5590#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
5591#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
5592#define CAN_F12R2_FB30_Pos (30U)
5593#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
5594#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
5595#define CAN_F12R2_FB31_Pos (31U)
5596#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
5597#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
5598
5599/******************* Bit definition for CAN_F13R2 register ******************/
5600#define CAN_F13R2_FB0_Pos (0U)
5601#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
5602#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
5603#define CAN_F13R2_FB1_Pos (1U)
5604#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
5605#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
5606#define CAN_F13R2_FB2_Pos (2U)
5607#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
5608#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
5609#define CAN_F13R2_FB3_Pos (3U)
5610#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
5611#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
5612#define CAN_F13R2_FB4_Pos (4U)
5613#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
5614#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
5615#define CAN_F13R2_FB5_Pos (5U)
5616#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
5617#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
5618#define CAN_F13R2_FB6_Pos (6U)
5619#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
5620#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
5621#define CAN_F13R2_FB7_Pos (7U)
5622#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
5623#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
5624#define CAN_F13R2_FB8_Pos (8U)
5625#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
5626#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
5627#define CAN_F13R2_FB9_Pos (9U)
5628#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
5629#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
5630#define CAN_F13R2_FB10_Pos (10U)
5631#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
5632#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
5633#define CAN_F13R2_FB11_Pos (11U)
5634#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
5635#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
5636#define CAN_F13R2_FB12_Pos (12U)
5637#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
5638#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
5639#define CAN_F13R2_FB13_Pos (13U)
5640#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
5641#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
5642#define CAN_F13R2_FB14_Pos (14U)
5643#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
5644#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
5645#define CAN_F13R2_FB15_Pos (15U)
5646#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
5647#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
5648#define CAN_F13R2_FB16_Pos (16U)
5649#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
5650#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
5651#define CAN_F13R2_FB17_Pos (17U)
5652#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
5653#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
5654#define CAN_F13R2_FB18_Pos (18U)
5655#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
5656#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
5657#define CAN_F13R2_FB19_Pos (19U)
5658#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
5659#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
5660#define CAN_F13R2_FB20_Pos (20U)
5661#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
5662#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
5663#define CAN_F13R2_FB21_Pos (21U)
5664#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
5665#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
5666#define CAN_F13R2_FB22_Pos (22U)
5667#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
5668#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
5669#define CAN_F13R2_FB23_Pos (23U)
5670#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
5671#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
5672#define CAN_F13R2_FB24_Pos (24U)
5673#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
5674#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
5675#define CAN_F13R2_FB25_Pos (25U)
5676#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
5677#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
5678#define CAN_F13R2_FB26_Pos (26U)
5679#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
5680#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
5681#define CAN_F13R2_FB27_Pos (27U)
5682#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
5683#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
5684#define CAN_F13R2_FB28_Pos (28U)
5685#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
5686#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
5687#define CAN_F13R2_FB29_Pos (29U)
5688#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
5689#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
5690#define CAN_F13R2_FB30_Pos (30U)
5691#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
5692#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
5693#define CAN_F13R2_FB31_Pos (31U)
5694#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
5695#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
5696
5697/******************************************************************************/
5698/* */
5699/* HDMI-CEC (CEC) */
5700/* */
5701/******************************************************************************/
5702
5703/******************* Bit definition for CEC_CR register *********************/
5704#define CEC_CR_CECEN_Pos (0U)
5705#define CEC_CR_CECEN_Msk (0x1U << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
5706#define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
5707#define CEC_CR_TXSOM_Pos (1U)
5708#define CEC_CR_TXSOM_Msk (0x1U << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
5709#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
5710#define CEC_CR_TXEOM_Pos (2U)
5711#define CEC_CR_TXEOM_Msk (0x1U << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
5712#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
5713
5714/******************* Bit definition for CEC_CFGR register *******************/
5715#define CEC_CFGR_SFT_Pos (0U)
5716#define CEC_CFGR_SFT_Msk (0x7U << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
5717#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
5718#define CEC_CFGR_RXTOL_Pos (3U)
5719#define CEC_CFGR_RXTOL_Msk (0x1U << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
5720#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
5721#define CEC_CFGR_BRESTP_Pos (4U)
5722#define CEC_CFGR_BRESTP_Msk (0x1U << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
5723#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
5724#define CEC_CFGR_BREGEN_Pos (5U)
5725#define CEC_CFGR_BREGEN_Msk (0x1U << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
5726#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
5727#define CEC_CFGR_LBPEGEN_Pos (6U)
5728#define CEC_CFGR_LBPEGEN_Msk (0x1U << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
5729#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Period Error generation */
5730#define CEC_CFGR_BRDNOGEN_Pos (7U)
5731#define CEC_CFGR_BRDNOGEN_Msk (0x1U << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
5732#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast no Error generation */
5733#define CEC_CFGR_SFTOPT_Pos (8U)
5734#define CEC_CFGR_SFTOPT_Msk (0x1U << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
5735#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
5736#define CEC_CFGR_OAR_Pos (16U)
5737#define CEC_CFGR_OAR_Msk (0x7FFFU << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
5738#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
5739#define CEC_CFGR_LSTN_Pos (31U)
5740#define CEC_CFGR_LSTN_Msk (0x1U << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
5741#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
5742
5743/******************* Bit definition for CEC_TXDR register *******************/
5744#define CEC_TXDR_TXD_Pos (0U)
5745#define CEC_TXDR_TXD_Msk (0xFFU << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
5746#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
5747
5748/******************* Bit definition for CEC_RXDR register *******************/
5749#define CEC_TXDR_RXD_Pos (0U)
5750#define CEC_TXDR_RXD_Msk (0xFFU << CEC_TXDR_RXD_Pos) /*!< 0x000000FF */
5751#define CEC_TXDR_RXD CEC_TXDR_RXD_Msk /*!< CEC Rx Data */
5752
5753/******************* Bit definition for CEC_ISR register ********************/
5754#define CEC_ISR_RXBR_Pos (0U)
5755#define CEC_ISR_RXBR_Msk (0x1U << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
5756#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
5757#define CEC_ISR_RXEND_Pos (1U)
5758#define CEC_ISR_RXEND_Msk (0x1U << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
5759#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
5760#define CEC_ISR_RXOVR_Pos (2U)
5761#define CEC_ISR_RXOVR_Msk (0x1U << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
5762#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
5763#define CEC_ISR_BRE_Pos (3U)
5764#define CEC_ISR_BRE_Msk (0x1U << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
5765#define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
5766#define CEC_ISR_SBPE_Pos (4U)
5767#define CEC_ISR_SBPE_Msk (0x1U << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
5768#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
5769#define CEC_ISR_LBPE_Pos (5U)
5770#define CEC_ISR_LBPE_Msk (0x1U << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
5771#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
5772#define CEC_ISR_RXACKE_Pos (6U)
5773#define CEC_ISR_RXACKE_Msk (0x1U << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
5774#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
5775#define CEC_ISR_ARBLST_Pos (7U)
5776#define CEC_ISR_ARBLST_Msk (0x1U << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
5777#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
5778#define CEC_ISR_TXBR_Pos (8U)
5779#define CEC_ISR_TXBR_Msk (0x1U << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
5780#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
5781#define CEC_ISR_TXEND_Pos (9U)
5782#define CEC_ISR_TXEND_Msk (0x1U << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
5783#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
5784#define CEC_ISR_TXUDR_Pos (10U)
5785#define CEC_ISR_TXUDR_Msk (0x1U << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
5786#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
5787#define CEC_ISR_TXERR_Pos (11U)
5788#define CEC_ISR_TXERR_Msk (0x1U << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
5789#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
5790#define CEC_ISR_TXACKE_Pos (12U)
5791#define CEC_ISR_TXACKE_Msk (0x1U << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
5792#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
5793
5794/******************* Bit definition for CEC_IER register ********************/
5795#define CEC_IER_RXBRIE_Pos (0U)
5796#define CEC_IER_RXBRIE_Msk (0x1U << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
5797#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
5798#define CEC_IER_RXENDIE_Pos (1U)
5799#define CEC_IER_RXENDIE_Msk (0x1U << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
5800#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
5801#define CEC_IER_RXOVRIE_Pos (2U)
5802#define CEC_IER_RXOVRIE_Msk (0x1U << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
5803#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
5804#define CEC_IER_BREIE_Pos (3U)
5805#define CEC_IER_BREIE_Msk (0x1U << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
5806#define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
5807#define CEC_IER_SBPEIE_Pos (4U)
5808#define CEC_IER_SBPEIE_Msk (0x1U << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
5809#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable*/
5810#define CEC_IER_LBPEIE_Pos (5U)
5811#define CEC_IER_LBPEIE_Msk (0x1U << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
5812#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
5813#define CEC_IER_RXACKEIE_Pos (6U)
5814#define CEC_IER_RXACKEIE_Msk (0x1U << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
5815#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
5816#define CEC_IER_ARBLSTIE_Pos (7U)
5817#define CEC_IER_ARBLSTIE_Msk (0x1U << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
5818#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
5819#define CEC_IER_TXBRIE_Pos (8U)
5820#define CEC_IER_TXBRIE_Msk (0x1U << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
5821#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
5822#define CEC_IER_TXENDIE_Pos (9U)
5823#define CEC_IER_TXENDIE_Msk (0x1U << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
5824#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
5825#define CEC_IER_TXUDRIE_Pos (10U)
5826#define CEC_IER_TXUDRIE_Msk (0x1U << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
5827#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
5828#define CEC_IER_TXERRIE_Pos (11U)
5829#define CEC_IER_TXERRIE_Msk (0x1U << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
5830#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
5831#define CEC_IER_TXACKEIE_Pos (12U)
5832#define CEC_IER_TXACKEIE_Msk (0x1U << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
5833#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
5834
5835/******************************************************************************/
5836/* */
5837/* CRC calculation unit */
5838/* */
5839/******************************************************************************/
5840/******************* Bit definition for CRC_DR register *********************/
5841#define CRC_DR_DR_Pos (0U)
5842#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
5843#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
5844
5845/******************* Bit definition for CRC_IDR register ********************/
5846#define CRC_IDR_IDR_Pos (0U)
5847#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
5848#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
5849
5850/******************** Bit definition for CRC_CR register ********************/
5851#define CRC_CR_RESET_Pos (0U)
5852#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
5853#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
5854#define CRC_CR_POLYSIZE_Pos (3U)
5855#define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
5856#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
5857#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
5858#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
5859#define CRC_CR_REV_IN_Pos (5U)
5860#define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
5861#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
5862#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
5863#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
5864#define CRC_CR_REV_OUT_Pos (7U)
5865#define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
5866#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
5867
5868/******************* Bit definition for CRC_INIT register *******************/
5869#define CRC_INIT_INIT_Pos (0U)
5870#define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
5871#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
5872
5873/******************* Bit definition for CRC_POL register ********************/
5874#define CRC_POL_POL_Pos (0U)
5875#define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
5876#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
5877
5878
5879/******************************************************************************/
5880/* */
5881/* Digital to Analog Converter */
5882/* */
5883/******************************************************************************/
5884/******************** Bit definition for DAC_CR register ********************/
5885#define DAC_CR_EN1_Pos (0U)
5886#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
5887#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
5888#define DAC_CR_BOFF1_Pos (1U)
5889#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
5890#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
5891#define DAC_CR_TEN1_Pos (2U)
5892#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
5893#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
5894#define DAC_CR_TSEL1_Pos (3U)
5895#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
5896#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5897#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
5898#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
5899#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
5900#define DAC_CR_WAVE1_Pos (6U)
5901#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
5902#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) */
5903#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
5904#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
5905#define DAC_CR_MAMP1_Pos (8U)
5906#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
5907#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5908#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
5909#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
5910#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
5911#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
5912#define DAC_CR_DMAEN1_Pos (12U)
5913#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
5914#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
5915#define DAC_CR_DMAUDRIE1_Pos (13U)
5916#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
5917#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable */
5918#define DAC_CR_EN2_Pos (16U)
5919#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
5920#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
5921#define DAC_CR_BOFF2_Pos (17U)
5922#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
5923#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
5924#define DAC_CR_TEN2_Pos (18U)
5925#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
5926#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
5927#define DAC_CR_TSEL2_Pos (19U)
5928#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
5929#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5930#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
5931#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
5932#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
5933#define DAC_CR_WAVE2_Pos (22U)
5934#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
5935#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5936#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
5937#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
5938#define DAC_CR_MAMP2_Pos (24U)
5939#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
5940#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5941#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
5942#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
5943#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
5944#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
5945#define DAC_CR_DMAEN2_Pos (28U)
5946#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
5947#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enable */
5948#define DAC_CR_DMAUDRIE2_Pos (29U)
5949#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
5950#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable */
5951
5952/***************** Bit definition for DAC_SWTRIGR register ******************/
5953#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5954#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
5955#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
5956#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5957#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
5958#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
5959
5960/***************** Bit definition for DAC_DHR12R1 register ******************/
5961#define DAC_DHR12R1_DACC1DHR_Pos (0U)
5962#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
5963#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5964
5965/***************** Bit definition for DAC_DHR12L1 register ******************/
5966#define DAC_DHR12L1_DACC1DHR_Pos (4U)
5967#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5968#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5969
5970/****************** Bit definition for DAC_DHR8R1 register ******************/
5971#define DAC_DHR8R1_DACC1DHR_Pos (0U)
5972#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
5973#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5974
5975/***************** Bit definition for DAC_DHR12R2 register ******************/
5976#define DAC_DHR12R2_DACC2DHR_Pos (0U)
5977#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
5978#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5979
5980/***************** Bit definition for DAC_DHR12L2 register ******************/
5981#define DAC_DHR12L2_DACC2DHR_Pos (4U)
5982#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
5983#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5984
5985/****************** Bit definition for DAC_DHR8R2 register ******************/
5986#define DAC_DHR8R2_DACC2DHR_Pos (0U)
5987#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
5988#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5989
5990/***************** Bit definition for DAC_DHR12RD register ******************/
5991#define DAC_DHR12RD_DACC1DHR_Pos (0U)
5992#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
5993#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5994#define DAC_DHR12RD_DACC2DHR_Pos (16U)
5995#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
5996#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5997
5998/***************** Bit definition for DAC_DHR12LD register ******************/
5999#define DAC_DHR12LD_DACC1DHR_Pos (4U)
6000#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
6001#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
6002#define DAC_DHR12LD_DACC2DHR_Pos (20U)
6003#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
6004#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
6005
6006/****************** Bit definition for DAC_DHR8RD register ******************/
6007#define DAC_DHR8RD_DACC1DHR_Pos (0U)
6008#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
6009#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
6010#define DAC_DHR8RD_DACC2DHR_Pos (8U)
6011#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
6012#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
6013
6014/******************* Bit definition for DAC_DOR1 register *******************/
6015#define DAC_DOR1_DACC1DOR_Pos (0U)
6016#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
6017#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
6018
6019/******************* Bit definition for DAC_DOR2 register *******************/
6020#define DAC_DOR2_DACC2DOR_Pos (0U)
6021#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
6022#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
6023
6024/******************** Bit definition for DAC_SR register ********************/
6025#define DAC_SR_DMAUDR1_Pos (13U)
6026#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
6027#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
6028#define DAC_SR_DMAUDR2_Pos (29U)
6029#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
6030#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
6031
6032/******************************************************************************/
6033/* */
6034/* Digital Filter for Sigma Delta Modulators */
6035/* */
6036/******************************************************************************/
6037
6038/**************** DFSDM channel configuration registers ********************/
6039
6040/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
6041#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
6042#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
6043#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
6044#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
6045#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
6046#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
6047#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
6048#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
6049#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
6050#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
6051#define DFSDM_CHCFGR1_DATPACK_Msk (0x3U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
6052#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
6053#define DFSDM_CHCFGR1_DATPACK_1 (0x2U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
6054#define DFSDM_CHCFGR1_DATPACK_0 (0x1U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
6055#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
6056#define DFSDM_CHCFGR1_DATMPX_Msk (0x3U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
6057#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
6058#define DFSDM_CHCFGR1_DATMPX_1 (0x2U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
6059#define DFSDM_CHCFGR1_DATMPX_0 (0x1U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
6060#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
6061#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
6062#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
6063#define DFSDM_CHCFGR1_CHEN_Pos (7U)
6064#define DFSDM_CHCFGR1_CHEN_Msk (0x1U << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
6065#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
6066#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
6067#define DFSDM_CHCFGR1_CKABEN_Msk (0x1U << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
6068#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
6069#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
6070#define DFSDM_CHCFGR1_SCDEN_Msk (0x1U << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
6071#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
6072#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
6073#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
6074#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
6075#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
6076#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
6077#define DFSDM_CHCFGR1_SITP_Pos (0U)
6078#define DFSDM_CHCFGR1_SITP_Msk (0x3U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
6079#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
6080#define DFSDM_CHCFGR1_SITP_1 (0x2U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
6081#define DFSDM_CHCFGR1_SITP_0 (0x1U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
6082
6083/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
6084#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
6085#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
6086#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
6087#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
6088#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
6089#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
6090
6091/****************** Bit definition for DFSDM_CHAWSCDR register *****************/
6092#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
6093#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
6094#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
6095#define DFSDM_CHAWSCDR_AWFORD_1 (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
6096#define DFSDM_CHAWSCDR_AWFORD_0 (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
6097#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
6098#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
6099#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
6100#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
6101#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
6102#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
6103#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
6104#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
6105#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
6106
6107/**************** Bit definition for DFSDM_CHWDATR register *******************/
6108#define DFSDM_CHWDATR_WDATA_Pos (0U)
6109#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
6110#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
6111
6112/**************** Bit definition for DFSDM_CHDATINR register *****************/
6113#define DFSDM_CHDATINR_INDAT0_Pos (0U)
6114#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
6115#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
6116#define DFSDM_CHDATINR_INDAT1_Pos (16U)
6117#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
6118#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
6119
6120/************************ DFSDM module registers ****************************/
6121
6122/******************** Bit definition for DFSDM_FLTCR1 register *******************/
6123#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
6124#define DFSDM_FLTCR1_AWFSEL_Msk (0x1U << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
6125#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
6126#define DFSDM_FLTCR1_FAST_Pos (29U)
6127#define DFSDM_FLTCR1_FAST_Msk (0x1U << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
6128#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
6129#define DFSDM_FLTCR1_RCH_Pos (24U)
6130#define DFSDM_FLTCR1_RCH_Msk (0x7U << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
6131#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
6132#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
6133#define DFSDM_FLTCR1_RDMAEN_Msk (0x1U << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
6134#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
6135#define DFSDM_FLTCR1_RSYNC_Pos (19U)
6136#define DFSDM_FLTCR1_RSYNC_Msk (0x1U << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
6137#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
6138#define DFSDM_FLTCR1_RCONT_Pos (18U)
6139#define DFSDM_FLTCR1_RCONT_Msk (0x1U << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
6140#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
6141#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
6142#define DFSDM_FLTCR1_RSWSTART_Msk (0x1U << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
6143#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
6144#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
6145#define DFSDM_FLTCR1_JEXTEN_Msk (0x3U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
6146#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
6147#define DFSDM_FLTCR1_JEXTEN_1 (0x2U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
6148#define DFSDM_FLTCR1_JEXTEN_0 (0x1U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
6149#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
6150#define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FU << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001F00 */
6151#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
6152#define DFSDM_FLTCR1_JEXTSEL_0 (0x01U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
6153#define DFSDM_FLTCR1_JEXTSEL_1 (0x02U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
6154#define DFSDM_FLTCR1_JEXTSEL_2 (0x04U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
6155#define DFSDM_FLTCR1_JEXTSEL_3 (0x08U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000800 */
6156#define DFSDM_FLTCR1_JEXTSEL_4 (0x10U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001000 */
6157#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
6158#define DFSDM_FLTCR1_JDMAEN_Msk (0x1U << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
6159#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
6160#define DFSDM_FLTCR1_JSCAN_Pos (4U)
6161#define DFSDM_FLTCR1_JSCAN_Msk (0x1U << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
6162#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
6163#define DFSDM_FLTCR1_JSYNC_Pos (3U)
6164#define DFSDM_FLTCR1_JSYNC_Msk (0x1U << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
6165#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
6166#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
6167#define DFSDM_FLTCR1_JSWSTART_Msk (0x1U << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
6168#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
6169#define DFSDM_FLTCR1_DFEN_Pos (0U)
6170#define DFSDM_FLTCR1_DFEN_Msk (0x1U << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
6171#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
6172
6173/******************** Bit definition for DFSDM_FLTCR2 register *******************/
6174#define DFSDM_FLTCR2_AWDCH_Pos (16U)
6175#define DFSDM_FLTCR2_AWDCH_Msk (0xFFU << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
6176#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
6177#define DFSDM_FLTCR2_EXCH_Pos (8U)
6178#define DFSDM_FLTCR2_EXCH_Msk (0xFFU << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
6179#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
6180#define DFSDM_FLTCR2_CKABIE_Pos (6U)
6181#define DFSDM_FLTCR2_CKABIE_Msk (0x1U << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
6182#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
6183#define DFSDM_FLTCR2_SCDIE_Pos (5U)
6184#define DFSDM_FLTCR2_SCDIE_Msk (0x1U << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
6185#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
6186#define DFSDM_FLTCR2_AWDIE_Pos (4U)
6187#define DFSDM_FLTCR2_AWDIE_Msk (0x1U << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
6188#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
6189#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
6190#define DFSDM_FLTCR2_ROVRIE_Msk (0x1U << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
6191#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
6192#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
6193#define DFSDM_FLTCR2_JOVRIE_Msk (0x1U << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
6194#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
6195#define DFSDM_FLTCR2_REOCIE_Pos (1U)
6196#define DFSDM_FLTCR2_REOCIE_Msk (0x1U << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
6197#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
6198#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
6199#define DFSDM_FLTCR2_JEOCIE_Msk (0x1U << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
6200#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
6201
6202/******************** Bit definition for DFSDM_FLTISR register *******************/
6203#define DFSDM_FLTISR_SCDF_Pos (24U)
6204#define DFSDM_FLTISR_SCDF_Msk (0xFFU << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
6205#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
6206#define DFSDM_FLTISR_CKABF_Pos (16U)
6207#define DFSDM_FLTISR_CKABF_Msk (0xFFU << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
6208#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
6209#define DFSDM_FLTISR_RCIP_Pos (14U)
6210#define DFSDM_FLTISR_RCIP_Msk (0x1U << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
6211#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
6212#define DFSDM_FLTISR_JCIP_Pos (13U)
6213#define DFSDM_FLTISR_JCIP_Msk (0x1U << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
6214#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
6215#define DFSDM_FLTISR_AWDF_Pos (4U)
6216#define DFSDM_FLTISR_AWDF_Msk (0x1U << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
6217#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
6218#define DFSDM_FLTISR_ROVRF_Pos (3U)
6219#define DFSDM_FLTISR_ROVRF_Msk (0x1U << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
6220#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
6221#define DFSDM_FLTISR_JOVRF_Pos (2U)
6222#define DFSDM_FLTISR_JOVRF_Msk (0x1U << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
6223#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
6224#define DFSDM_FLTISR_REOCF_Pos (1U)
6225#define DFSDM_FLTISR_REOCF_Msk (0x1U << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
6226#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
6227#define DFSDM_FLTISR_JEOCF_Pos (0U)
6228#define DFSDM_FLTISR_JEOCF_Msk (0x1U << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
6229#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
6230
6231/******************** Bit definition for DFSDM_FLTICR register *******************/
6232#define DFSDM_FLTICR_CLRSCSDF_Pos (24U)
6233#define DFSDM_FLTICR_CLRSCSDF_Msk (0xFFU << DFSDM_FLTICR_CLRSCSDF_Pos) /*!< 0xFF000000 */
6234#define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCSDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
6235#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
6236#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFU << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
6237#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
6238#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
6239#define DFSDM_FLTICR_CLRROVRF_Msk (0x1U << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
6240#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
6241#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
6242#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
6243#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
6244
6245/******************* Bit definition for DFSDM_FLTJCHGR register ******************/
6246#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
6247#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFU << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
6248#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
6249
6250/******************** Bit definition for DFSDM_FLTFCR register *******************/
6251#define DFSDM_FLTFCR_FORD_Pos (29U)
6252#define DFSDM_FLTFCR_FORD_Msk (0x7U << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
6253#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
6254#define DFSDM_FLTFCR_FORD_2 (0x4U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
6255#define DFSDM_FLTFCR_FORD_1 (0x2U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
6256#define DFSDM_FLTFCR_FORD_0 (0x1U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
6257#define DFSDM_FLTFCR_FOSR_Pos (16U)
6258#define DFSDM_FLTFCR_FOSR_Msk (0x3FFU << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
6259#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
6260#define DFSDM_FLTFCR_IOSR_Pos (0U)
6261#define DFSDM_FLTFCR_IOSR_Msk (0xFFU << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
6262#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
6263
6264/****************** Bit definition for DFSDM_FLTJDATAR register *****************/
6265#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
6266#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
6267#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
6268#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
6269#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
6270#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
6271
6272/****************** Bit definition for DFSDM_FLTRDATAR register *****************/
6273#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
6274#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
6275#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
6276#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
6277#define DFSDM_FLTRDATAR_RPEND_Msk (0x1U << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
6278#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
6279#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
6280#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
6281#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
6282
6283/****************** Bit definition for DFSDM_FLTAWHTR register ******************/
6284#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
6285#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
6286#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
6287#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
6288#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
6289#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
6290
6291/****************** Bit definition for DFSDM_FLTAWLTR register ******************/
6292#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
6293#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
6294#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWLT[23:0] Analog watchdog low threshold */
6295#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
6296#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
6297#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
6298
6299/****************** Bit definition for DFSDM_FLTAWSR register ******************/
6300#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
6301#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFU << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
6302#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
6303#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
6304#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFU << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
6305#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
6306
6307/****************** Bit definition for DFSDM_FLTAWCFR register *****************/
6308#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
6309#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
6310#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
6311#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
6312#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
6313#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
6314
6315/****************** Bit definition for DFSDM_FLTEXMAX register ******************/
6316#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
6317#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
6318#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
6319#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
6320#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
6321#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
6322
6323/****************** Bit definition for DFSDM_FLTEXMIN register ******************/
6324#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
6325#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
6326#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
6327#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
6328#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
6329#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
6330
6331/****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
6332#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
6333#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
6334#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
6335
6336/******************************************************************************/
6337/* */
6338/* Debug MCU */
6339/* */
6340/******************************************************************************/
6341
6342/******************************************************************************/
6343/* */
6344/* DCMI */
6345/* */
6346/******************************************************************************/
6347/******************** Bits definition for DCMI_CR register ******************/
6348#define DCMI_CR_CAPTURE_Pos (0U)
6349#define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
6350#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
6351#define DCMI_CR_CM_Pos (1U)
6352#define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
6353#define DCMI_CR_CM DCMI_CR_CM_Msk
6354#define DCMI_CR_CROP_Pos (2U)
6355#define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
6356#define DCMI_CR_CROP DCMI_CR_CROP_Msk
6357#define DCMI_CR_JPEG_Pos (3U)
6358#define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
6359#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
6360#define DCMI_CR_ESS_Pos (4U)
6361#define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
6362#define DCMI_CR_ESS DCMI_CR_ESS_Msk
6363#define DCMI_CR_PCKPOL_Pos (5U)
6364#define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
6365#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
6366#define DCMI_CR_HSPOL_Pos (6U)
6367#define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
6368#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
6369#define DCMI_CR_VSPOL_Pos (7U)
6370#define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
6371#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
6372#define DCMI_CR_FCRC_0 0x00000100U
6373#define DCMI_CR_FCRC_1 0x00000200U
6374#define DCMI_CR_EDM_0 0x00000400U
6375#define DCMI_CR_EDM_1 0x00000800U
6376#define DCMI_CR_CRE_Pos (12U)
6377#define DCMI_CR_CRE_Msk (0x1U << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
6378#define DCMI_CR_CRE DCMI_CR_CRE_Msk
6379#define DCMI_CR_ENABLE_Pos (14U)
6380#define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
6381#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
6382#define DCMI_CR_BSM_Pos (16U)
6383#define DCMI_CR_BSM_Msk (0x3U << DCMI_CR_BSM_Pos) /*!< 0x00030000 */
6384#define DCMI_CR_BSM DCMI_CR_BSM_Msk
6385#define DCMI_CR_BSM_0 (0x1U << DCMI_CR_BSM_Pos) /*!< 0x00010000 */
6386#define DCMI_CR_BSM_1 (0x2U << DCMI_CR_BSM_Pos) /*!< 0x00020000 */
6387#define DCMI_CR_OEBS_Pos (18U)
6388#define DCMI_CR_OEBS_Msk (0x1U << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
6389#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
6390#define DCMI_CR_LSM_Pos (19U)
6391#define DCMI_CR_LSM_Msk (0x1U << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
6392#define DCMI_CR_LSM DCMI_CR_LSM_Msk
6393#define DCMI_CR_OELS_Pos (20U)
6394#define DCMI_CR_OELS_Msk (0x1U << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
6395#define DCMI_CR_OELS DCMI_CR_OELS_Msk
6396
6397/******************** Bits definition for DCMI_SR register ******************/
6398#define DCMI_SR_HSYNC_Pos (0U)
6399#define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
6400#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
6401#define DCMI_SR_VSYNC_Pos (1U)
6402#define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
6403#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
6404#define DCMI_SR_FNE_Pos (2U)
6405#define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
6406#define DCMI_SR_FNE DCMI_SR_FNE_Msk
6407
6408/******************** Bits definition for DCMI_RIS register ****************/
6409#define DCMI_RIS_FRAME_RIS_Pos (0U)
6410#define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
6411#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
6412#define DCMI_RIS_OVR_RIS_Pos (1U)
6413#define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
6414#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
6415#define DCMI_RIS_ERR_RIS_Pos (2U)
6416#define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
6417#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
6418#define DCMI_RIS_VSYNC_RIS_Pos (3U)
6419#define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
6420#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
6421#define DCMI_RIS_LINE_RIS_Pos (4U)
6422#define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
6423#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
6424
6425/* Legacy defines */
6426#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
6427#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
6428#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
6429#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
6430#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
6431
6432/******************** Bits definition for DCMI_IER register *****************/
6433#define DCMI_IER_FRAME_IE_Pos (0U)
6434#define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
6435#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
6436#define DCMI_IER_OVR_IE_Pos (1U)
6437#define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
6438#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
6439#define DCMI_IER_ERR_IE_Pos (2U)
6440#define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
6441#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
6442#define DCMI_IER_VSYNC_IE_Pos (3U)
6443#define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
6444#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
6445#define DCMI_IER_LINE_IE_Pos (4U)
6446#define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
6447#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
6448
6449
6450/******************** Bits definition for DCMI_MIS register *****************/
6451#define DCMI_MIS_FRAME_MIS_Pos (0U)
6452#define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
6453#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
6454#define DCMI_MIS_OVR_MIS_Pos (1U)
6455#define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
6456#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
6457#define DCMI_MIS_ERR_MIS_Pos (2U)
6458#define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
6459#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
6460#define DCMI_MIS_VSYNC_MIS_Pos (3U)
6461#define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
6462#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
6463#define DCMI_MIS_LINE_MIS_Pos (4U)
6464#define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
6465#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
6466
6467
6468/******************** Bits definition for DCMI_ICR register *****************/
6469#define DCMI_ICR_FRAME_ISC_Pos (0U)
6470#define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
6471#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
6472#define DCMI_ICR_OVR_ISC_Pos (1U)
6473#define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
6474#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
6475#define DCMI_ICR_ERR_ISC_Pos (2U)
6476#define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
6477#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
6478#define DCMI_ICR_VSYNC_ISC_Pos (3U)
6479#define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
6480#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
6481#define DCMI_ICR_LINE_ISC_Pos (4U)
6482#define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
6483#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
6484
6485
6486/******************** Bits definition for DCMI_ESCR register ******************/
6487#define DCMI_ESCR_FSC_Pos (0U)
6488#define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
6489#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
6490#define DCMI_ESCR_LSC_Pos (8U)
6491#define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
6492#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
6493#define DCMI_ESCR_LEC_Pos (16U)
6494#define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
6495#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
6496#define DCMI_ESCR_FEC_Pos (24U)
6497#define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
6498#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
6499
6500/******************** Bits definition for DCMI_ESUR register ******************/
6501#define DCMI_ESUR_FSU_Pos (0U)
6502#define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
6503#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
6504#define DCMI_ESUR_LSU_Pos (8U)
6505#define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
6506#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
6507#define DCMI_ESUR_LEU_Pos (16U)
6508#define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
6509#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
6510#define DCMI_ESUR_FEU_Pos (24U)
6511#define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
6512#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
6513
6514/******************** Bits definition for DCMI_CWSTRT register ******************/
6515#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
6516#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
6517#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
6518#define DCMI_CWSTRT_VST_Pos (16U)
6519#define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
6520#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
6521
6522/******************** Bits definition for DCMI_CWSIZE register ******************/
6523#define DCMI_CWSIZE_CAPCNT_Pos (0U)
6524#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
6525#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
6526#define DCMI_CWSIZE_VLINE_Pos (16U)
6527#define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
6528#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
6529
6530/******************** Bits definition for DCMI_DR register ******************/
6531#define DCMI_DR_BYTE0_Pos (0U)
6532#define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
6533#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
6534#define DCMI_DR_BYTE1_Pos (8U)
6535#define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
6536#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
6537#define DCMI_DR_BYTE2_Pos (16U)
6538#define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
6539#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
6540#define DCMI_DR_BYTE3_Pos (24U)
6541#define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
6542#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
6543
6544/******************************************************************************/
6545/* */
6546/* DMA Controller */
6547/* */
6548/******************************************************************************/
6549/******************** Bits definition for DMA_SxCR register *****************/
6550#define DMA_SxCR_CHSEL_Pos (25U)
6551#define DMA_SxCR_CHSEL_Msk (0xFU << DMA_SxCR_CHSEL_Pos) /*!< 0x1E000000 */
6552#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
6553#define DMA_SxCR_CHSEL_0 (0x1U << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */
6554#define DMA_SxCR_CHSEL_1 (0x2U << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */
6555#define DMA_SxCR_CHSEL_2 (0x4U << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */
6556#define DMA_SxCR_CHSEL_3 (0x8U << DMA_SxCR_CHSEL_Pos) /*!< 0x10000000 */
6557#define DMA_SxCR_MBURST_Pos (23U)
6558#define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
6559#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
6560#define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
6561#define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
6562#define DMA_SxCR_PBURST_Pos (21U)
6563#define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
6564#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
6565#define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
6566#define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
6567#define DMA_SxCR_CT_Pos (19U)
6568#define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
6569#define DMA_SxCR_CT DMA_SxCR_CT_Msk
6570#define DMA_SxCR_DBM_Pos (18U)
6571#define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
6572#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
6573#define DMA_SxCR_PL_Pos (16U)
6574#define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
6575#define DMA_SxCR_PL DMA_SxCR_PL_Msk
6576#define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
6577#define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
6578#define DMA_SxCR_PINCOS_Pos (15U)
6579#define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
6580#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
6581#define DMA_SxCR_MSIZE_Pos (13U)
6582#define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
6583#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
6584#define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
6585#define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
6586#define DMA_SxCR_PSIZE_Pos (11U)
6587#define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
6588#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
6589#define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
6590#define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
6591#define DMA_SxCR_MINC_Pos (10U)
6592#define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
6593#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
6594#define DMA_SxCR_PINC_Pos (9U)
6595#define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
6596#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
6597#define DMA_SxCR_CIRC_Pos (8U)
6598#define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
6599#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
6600#define DMA_SxCR_DIR_Pos (6U)
6601#define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
6602#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
6603#define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
6604#define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
6605#define DMA_SxCR_PFCTRL_Pos (5U)
6606#define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
6607#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
6608#define DMA_SxCR_TCIE_Pos (4U)
6609#define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
6610#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
6611#define DMA_SxCR_HTIE_Pos (3U)
6612#define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
6613#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
6614#define DMA_SxCR_TEIE_Pos (2U)
6615#define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
6616#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
6617#define DMA_SxCR_DMEIE_Pos (1U)
6618#define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
6619#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
6620#define DMA_SxCR_EN_Pos (0U)
6621#define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
6622#define DMA_SxCR_EN DMA_SxCR_EN_Msk
6623
6624/******************** Bits definition for DMA_SxCNDTR register **************/
6625#define DMA_SxNDT_Pos (0U)
6626#define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
6627#define DMA_SxNDT DMA_SxNDT_Msk
6628#define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
6629#define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
6630#define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
6631#define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
6632#define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
6633#define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
6634#define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
6635#define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
6636#define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
6637#define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
6638#define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
6639#define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
6640#define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
6641#define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
6642#define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
6643#define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
6644
6645/******************** Bits definition for DMA_SxFCR register ****************/
6646#define DMA_SxFCR_FEIE_Pos (7U)
6647#define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
6648#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
6649#define DMA_SxFCR_FS_Pos (3U)
6650#define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
6651#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
6652#define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
6653#define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
6654#define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
6655#define DMA_SxFCR_DMDIS_Pos (2U)
6656#define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
6657#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
6658#define DMA_SxFCR_FTH_Pos (0U)
6659#define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
6660#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
6661#define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
6662#define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
6663
6664/******************** Bits definition for DMA_LISR register *****************/
6665#define DMA_LISR_TCIF3_Pos (27U)
6666#define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
6667#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
6668#define DMA_LISR_HTIF3_Pos (26U)
6669#define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
6670#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
6671#define DMA_LISR_TEIF3_Pos (25U)
6672#define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
6673#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
6674#define DMA_LISR_DMEIF3_Pos (24U)
6675#define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
6676#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
6677#define DMA_LISR_FEIF3_Pos (22U)
6678#define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
6679#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
6680#define DMA_LISR_TCIF2_Pos (21U)
6681#define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
6682#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
6683#define DMA_LISR_HTIF2_Pos (20U)
6684#define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
6685#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
6686#define DMA_LISR_TEIF2_Pos (19U)
6687#define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
6688#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
6689#define DMA_LISR_DMEIF2_Pos (18U)
6690#define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
6691#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
6692#define DMA_LISR_FEIF2_Pos (16U)
6693#define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
6694#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
6695#define DMA_LISR_TCIF1_Pos (11U)
6696#define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
6697#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
6698#define DMA_LISR_HTIF1_Pos (10U)
6699#define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
6700#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
6701#define DMA_LISR_TEIF1_Pos (9U)
6702#define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
6703#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
6704#define DMA_LISR_DMEIF1_Pos (8U)
6705#define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
6706#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
6707#define DMA_LISR_FEIF1_Pos (6U)
6708#define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
6709#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
6710#define DMA_LISR_TCIF0_Pos (5U)
6711#define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
6712#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
6713#define DMA_LISR_HTIF0_Pos (4U)
6714#define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
6715#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
6716#define DMA_LISR_TEIF0_Pos (3U)
6717#define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
6718#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
6719#define DMA_LISR_DMEIF0_Pos (2U)
6720#define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
6721#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
6722#define DMA_LISR_FEIF0_Pos (0U)
6723#define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
6724#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
6725
6726/******************** Bits definition for DMA_HISR register *****************/
6727#define DMA_HISR_TCIF7_Pos (27U)
6728#define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
6729#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
6730#define DMA_HISR_HTIF7_Pos (26U)
6731#define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
6732#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
6733#define DMA_HISR_TEIF7_Pos (25U)
6734#define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
6735#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
6736#define DMA_HISR_DMEIF7_Pos (24U)
6737#define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
6738#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
6739#define DMA_HISR_FEIF7_Pos (22U)
6740#define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
6741#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
6742#define DMA_HISR_TCIF6_Pos (21U)
6743#define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
6744#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
6745#define DMA_HISR_HTIF6_Pos (20U)
6746#define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
6747#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
6748#define DMA_HISR_TEIF6_Pos (19U)
6749#define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
6750#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
6751#define DMA_HISR_DMEIF6_Pos (18U)
6752#define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
6753#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
6754#define DMA_HISR_FEIF6_Pos (16U)
6755#define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
6756#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
6757#define DMA_HISR_TCIF5_Pos (11U)
6758#define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
6759#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
6760#define DMA_HISR_HTIF5_Pos (10U)
6761#define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
6762#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
6763#define DMA_HISR_TEIF5_Pos (9U)
6764#define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
6765#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
6766#define DMA_HISR_DMEIF5_Pos (8U)
6767#define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
6768#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
6769#define DMA_HISR_FEIF5_Pos (6U)
6770#define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
6771#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
6772#define DMA_HISR_TCIF4_Pos (5U)
6773#define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
6774#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
6775#define DMA_HISR_HTIF4_Pos (4U)
6776#define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
6777#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
6778#define DMA_HISR_TEIF4_Pos (3U)
6779#define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
6780#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
6781#define DMA_HISR_DMEIF4_Pos (2U)
6782#define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
6783#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
6784#define DMA_HISR_FEIF4_Pos (0U)
6785#define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
6786#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
6787
6788/******************** Bits definition for DMA_LIFCR register ****************/
6789#define DMA_LIFCR_CTCIF3_Pos (27U)
6790#define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
6791#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
6792#define DMA_LIFCR_CHTIF3_Pos (26U)
6793#define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
6794#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
6795#define DMA_LIFCR_CTEIF3_Pos (25U)
6796#define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
6797#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
6798#define DMA_LIFCR_CDMEIF3_Pos (24U)
6799#define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
6800#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
6801#define DMA_LIFCR_CFEIF3_Pos (22U)
6802#define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
6803#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
6804#define DMA_LIFCR_CTCIF2_Pos (21U)
6805#define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
6806#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
6807#define DMA_LIFCR_CHTIF2_Pos (20U)
6808#define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
6809#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
6810#define DMA_LIFCR_CTEIF2_Pos (19U)
6811#define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
6812#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
6813#define DMA_LIFCR_CDMEIF2_Pos (18U)
6814#define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
6815#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
6816#define DMA_LIFCR_CFEIF2_Pos (16U)
6817#define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
6818#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
6819#define DMA_LIFCR_CTCIF1_Pos (11U)
6820#define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
6821#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
6822#define DMA_LIFCR_CHTIF1_Pos (10U)
6823#define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
6824#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
6825#define DMA_LIFCR_CTEIF1_Pos (9U)
6826#define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
6827#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
6828#define DMA_LIFCR_CDMEIF1_Pos (8U)
6829#define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
6830#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
6831#define DMA_LIFCR_CFEIF1_Pos (6U)
6832#define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
6833#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
6834#define DMA_LIFCR_CTCIF0_Pos (5U)
6835#define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
6836#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
6837#define DMA_LIFCR_CHTIF0_Pos (4U)
6838#define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
6839#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
6840#define DMA_LIFCR_CTEIF0_Pos (3U)
6841#define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
6842#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
6843#define DMA_LIFCR_CDMEIF0_Pos (2U)
6844#define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
6845#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
6846#define DMA_LIFCR_CFEIF0_Pos (0U)
6847#define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
6848#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
6849
6850/******************** Bits definition for DMA_HIFCR register ****************/
6851#define DMA_HIFCR_CTCIF7_Pos (27U)
6852#define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
6853#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
6854#define DMA_HIFCR_CHTIF7_Pos (26U)
6855#define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
6856#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
6857#define DMA_HIFCR_CTEIF7_Pos (25U)
6858#define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
6859#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
6860#define DMA_HIFCR_CDMEIF7_Pos (24U)
6861#define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
6862#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
6863#define DMA_HIFCR_CFEIF7_Pos (22U)
6864#define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
6865#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
6866#define DMA_HIFCR_CTCIF6_Pos (21U)
6867#define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
6868#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
6869#define DMA_HIFCR_CHTIF6_Pos (20U)
6870#define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
6871#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
6872#define DMA_HIFCR_CTEIF6_Pos (19U)
6873#define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
6874#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
6875#define DMA_HIFCR_CDMEIF6_Pos (18U)
6876#define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
6877#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
6878#define DMA_HIFCR_CFEIF6_Pos (16U)
6879#define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
6880#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
6881#define DMA_HIFCR_CTCIF5_Pos (11U)
6882#define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
6883#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
6884#define DMA_HIFCR_CHTIF5_Pos (10U)
6885#define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
6886#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
6887#define DMA_HIFCR_CTEIF5_Pos (9U)
6888#define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
6889#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
6890#define DMA_HIFCR_CDMEIF5_Pos (8U)
6891#define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
6892#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
6893#define DMA_HIFCR_CFEIF5_Pos (6U)
6894#define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
6895#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
6896#define DMA_HIFCR_CTCIF4_Pos (5U)
6897#define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
6898#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
6899#define DMA_HIFCR_CHTIF4_Pos (4U)
6900#define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
6901#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
6902#define DMA_HIFCR_CTEIF4_Pos (3U)
6903#define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
6904#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
6905#define DMA_HIFCR_CDMEIF4_Pos (2U)
6906#define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
6907#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
6908#define DMA_HIFCR_CFEIF4_Pos (0U)
6909#define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
6910#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
6911
6912/****************** Bit definition for DMA_SxPAR register ********************/
6913#define DMA_SxPAR_PA_Pos (0U)
6914#define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
6915#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
6916
6917/****************** Bit definition for DMA_SxM0AR register ********************/
6918#define DMA_SxM0AR_M0A_Pos (0U)
6919#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
6920#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
6921
6922/****************** Bit definition for DMA_SxM1AR register ********************/
6923#define DMA_SxM1AR_M1A_Pos (0U)
6924#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
6925#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
6926
6927/******************************************************************************/
6928/* */
6929/* AHB Master DMA2D Controller (DMA2D) */
6930/* */
6931/******************************************************************************/
6932/*
6933 * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
6934 */
6935#define DMA2D_ALPHA_INV_RB_SWAP_SUPPORT
6936/******************** Bit definition for DMA2D_CR register ******************/
6937
6938#define DMA2D_CR_START_Pos (0U)
6939#define DMA2D_CR_START_Msk (0x1U << DMA2D_CR_START_Pos) /*!< 0x00000001 */
6940#define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
6941#define DMA2D_CR_SUSP_Pos (1U)
6942#define DMA2D_CR_SUSP_Msk (0x1U << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
6943#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
6944#define DMA2D_CR_ABORT_Pos (2U)
6945#define DMA2D_CR_ABORT_Msk (0x1U << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
6946#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
6947#define DMA2D_CR_TEIE_Pos (8U)
6948#define DMA2D_CR_TEIE_Msk (0x1U << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
6949#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
6950#define DMA2D_CR_TCIE_Pos (9U)
6951#define DMA2D_CR_TCIE_Msk (0x1U << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
6952#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
6953#define DMA2D_CR_TWIE_Pos (10U)
6954#define DMA2D_CR_TWIE_Msk (0x1U << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
6955#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
6956#define DMA2D_CR_CAEIE_Pos (11U)
6957#define DMA2D_CR_CAEIE_Msk (0x1U << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
6958#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
6959#define DMA2D_CR_CTCIE_Pos (12U)
6960#define DMA2D_CR_CTCIE_Msk (0x1U << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
6961#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
6962#define DMA2D_CR_CEIE_Pos (13U)
6963#define DMA2D_CR_CEIE_Msk (0x1U << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
6964#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
6965#define DMA2D_CR_MODE_Pos (16U)
6966#define DMA2D_CR_MODE_Msk (0x3U << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */
6967#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */
6968#define DMA2D_CR_MODE_0 (0x1U << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
6969#define DMA2D_CR_MODE_1 (0x2U << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
6970
6971/******************** Bit definition for DMA2D_ISR register *****************/
6972
6973#define DMA2D_ISR_TEIF_Pos (0U)
6974#define DMA2D_ISR_TEIF_Msk (0x1U << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
6975#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
6976#define DMA2D_ISR_TCIF_Pos (1U)
6977#define DMA2D_ISR_TCIF_Msk (0x1U << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
6978#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
6979#define DMA2D_ISR_TWIF_Pos (2U)
6980#define DMA2D_ISR_TWIF_Msk (0x1U << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
6981#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
6982#define DMA2D_ISR_CAEIF_Pos (3U)
6983#define DMA2D_ISR_CAEIF_Msk (0x1U << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
6984#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
6985#define DMA2D_ISR_CTCIF_Pos (4U)
6986#define DMA2D_ISR_CTCIF_Msk (0x1U << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
6987#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
6988#define DMA2D_ISR_CEIF_Pos (5U)
6989#define DMA2D_ISR_CEIF_Msk (0x1U << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
6990#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
6991
6992/******************** Bit definition for DMA2D_IFCR register ****************/
6993
6994#define DMA2D_IFCR_CTEIF_Pos (0U)
6995#define DMA2D_IFCR_CTEIF_Msk (0x1U << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
6996#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
6997#define DMA2D_IFCR_CTCIF_Pos (1U)
6998#define DMA2D_IFCR_CTCIF_Msk (0x1U << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
6999#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
7000#define DMA2D_IFCR_CTWIF_Pos (2U)
7001#define DMA2D_IFCR_CTWIF_Msk (0x1U << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
7002#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
7003#define DMA2D_IFCR_CAECIF_Pos (3U)
7004#define DMA2D_IFCR_CAECIF_Msk (0x1U << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
7005#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
7006#define DMA2D_IFCR_CCTCIF_Pos (4U)
7007#define DMA2D_IFCR_CCTCIF_Msk (0x1U << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
7008#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
7009#define DMA2D_IFCR_CCEIF_Pos (5U)
7010#define DMA2D_IFCR_CCEIF_Msk (0x1U << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
7011#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
7012
7013/* Legacy defines */
7014#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
7015#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
7016#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
7017#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
7018#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
7019#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
7020
7021/******************** Bit definition for DMA2D_FGMAR register ***************/
7022
7023#define DMA2D_FGMAR_MA_Pos (0U)
7024#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
7025#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */
7026
7027/******************** Bit definition for DMA2D_FGOR register ****************/
7028
7029#define DMA2D_FGOR_LO_Pos (0U)
7030#define DMA2D_FGOR_LO_Msk (0x3FFFU << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */
7031#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
7032
7033/******************** Bit definition for DMA2D_BGMAR register ***************/
7034
7035#define DMA2D_BGMAR_MA_Pos (0U)
7036#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
7037#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */
7038
7039/******************** Bit definition for DMA2D_BGOR register ****************/
7040
7041#define DMA2D_BGOR_LO_Pos (0U)
7042#define DMA2D_BGOR_LO_Msk (0x3FFFU << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */
7043#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
7044
7045/******************** Bit definition for DMA2D_FGPFCCR register *************/
7046
7047#define DMA2D_FGPFCCR_CM_Pos (0U)
7048#define DMA2D_FGPFCCR_CM_Msk (0xFU << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
7049#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
7050#define DMA2D_FGPFCCR_CM_0 (0x1U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
7051#define DMA2D_FGPFCCR_CM_1 (0x2U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
7052#define DMA2D_FGPFCCR_CM_2 (0x4U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
7053#define DMA2D_FGPFCCR_CM_3 (0x8U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
7054#define DMA2D_FGPFCCR_CCM_Pos (4U)
7055#define DMA2D_FGPFCCR_CCM_Msk (0x1U << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
7056#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
7057#define DMA2D_FGPFCCR_START_Pos (5U)
7058#define DMA2D_FGPFCCR_START_Msk (0x1U << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
7059#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
7060#define DMA2D_FGPFCCR_CS_Pos (8U)
7061#define DMA2D_FGPFCCR_CS_Msk (0xFFU << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
7062#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
7063#define DMA2D_FGPFCCR_AM_Pos (16U)
7064#define DMA2D_FGPFCCR_AM_Msk (0x3U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
7065#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
7066#define DMA2D_FGPFCCR_AM_0 (0x1U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
7067#define DMA2D_FGPFCCR_AM_1 (0x2U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
7068#define DMA2D_FGPFCCR_AI_Pos (20U)
7069#define DMA2D_FGPFCCR_AI_Msk (0x1U << DMA2D_FGPFCCR_AI_Pos) /*!< 0x00100000 */
7070#define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk /*!< Foreground Input Alpha Inverted */
7071#define DMA2D_FGPFCCR_RBS_Pos (21U)
7072#define DMA2D_FGPFCCR_RBS_Msk (0x1U << DMA2D_FGPFCCR_RBS_Pos) /*!< 0x00200000 */
7073#define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk /*!< Foreground Input Red Blue Swap */
7074#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
7075#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
7076#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
7077
7078/******************** Bit definition for DMA2D_FGCOLR register **************/
7079
7080#define DMA2D_FGCOLR_BLUE_Pos (0U)
7081#define DMA2D_FGCOLR_BLUE_Msk (0xFFU << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
7082#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */
7083#define DMA2D_FGCOLR_GREEN_Pos (8U)
7084#define DMA2D_FGCOLR_GREEN_Msk (0xFFU << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
7085#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */
7086#define DMA2D_FGCOLR_RED_Pos (16U)
7087#define DMA2D_FGCOLR_RED_Msk (0xFFU << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
7088#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */
7089
7090/******************** Bit definition for DMA2D_BGPFCCR register *************/
7091
7092#define DMA2D_BGPFCCR_CM_Pos (0U)
7093#define DMA2D_BGPFCCR_CM_Msk (0xFU << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
7094#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
7095#define DMA2D_BGPFCCR_CM_0 (0x1U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
7096#define DMA2D_BGPFCCR_CM_1 (0x2U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
7097#define DMA2D_BGPFCCR_CM_2 (0x4U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
7098#define DMA2D_BGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
7099#define DMA2D_BGPFCCR_CCM_Pos (4U)
7100#define DMA2D_BGPFCCR_CCM_Msk (0x1U << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
7101#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
7102#define DMA2D_BGPFCCR_START_Pos (5U)
7103#define DMA2D_BGPFCCR_START_Msk (0x1U << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
7104#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
7105#define DMA2D_BGPFCCR_CS_Pos (8U)
7106#define DMA2D_BGPFCCR_CS_Msk (0xFFU << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
7107#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
7108#define DMA2D_BGPFCCR_AM_Pos (16U)
7109#define DMA2D_BGPFCCR_AM_Msk (0x3U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
7110#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
7111#define DMA2D_BGPFCCR_AM_0 (0x1U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
7112#define DMA2D_BGPFCCR_AM_1 (0x2U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
7113#define DMA2D_BGPFCCR_AI_Pos (20U)
7114#define DMA2D_BGPFCCR_AI_Msk (0x1U << DMA2D_BGPFCCR_AI_Pos) /*!< 0x00100000 */
7115#define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk /*!< background Input Alpha Inverted */
7116#define DMA2D_BGPFCCR_RBS_Pos (21U)
7117#define DMA2D_BGPFCCR_RBS_Msk (0x1U << DMA2D_BGPFCCR_RBS_Pos) /*!< 0x00200000 */
7118#define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk /*!< Background Input Red Blue Swap */
7119#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
7120#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
7121#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
7122
7123/******************** Bit definition for DMA2D_BGCOLR register **************/
7124
7125#define DMA2D_BGCOLR_BLUE_Pos (0U)
7126#define DMA2D_BGCOLR_BLUE_Msk (0xFFU << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
7127#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */
7128#define DMA2D_BGCOLR_GREEN_Pos (8U)
7129#define DMA2D_BGCOLR_GREEN_Msk (0xFFU << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
7130#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */
7131#define DMA2D_BGCOLR_RED_Pos (16U)
7132#define DMA2D_BGCOLR_RED_Msk (0xFFU << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
7133#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */
7134
7135/******************** Bit definition for DMA2D_FGCMAR register **************/
7136
7137#define DMA2D_FGCMAR_MA_Pos (0U)
7138#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
7139#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */
7140
7141/******************** Bit definition for DMA2D_BGCMAR register **************/
7142
7143#define DMA2D_BGCMAR_MA_Pos (0U)
7144#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
7145#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */
7146
7147/******************** Bit definition for DMA2D_OPFCCR register **************/
7148
7149#define DMA2D_OPFCCR_CM_Pos (0U)
7150#define DMA2D_OPFCCR_CM_Msk (0x7U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
7151#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */
7152#define DMA2D_OPFCCR_CM_0 (0x1U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
7153#define DMA2D_OPFCCR_CM_1 (0x2U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
7154#define DMA2D_OPFCCR_CM_2 (0x4U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
7155#define DMA2D_OPFCCR_AI_Pos (20U)
7156#define DMA2D_OPFCCR_AI_Msk (0x1U << DMA2D_OPFCCR_AI_Pos) /*!< 0x00100000 */
7157#define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk /*!< Output Alpha Inverted */
7158#define DMA2D_OPFCCR_RBS_Pos (21U)
7159#define DMA2D_OPFCCR_RBS_Msk (0x1U << DMA2D_OPFCCR_RBS_Pos) /*!< 0x00200000 */
7160#define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk /*!< Output Red Blue Swap */
7161
7162/******************** Bit definition for DMA2D_OCOLR register ***************/
7163
7164/*!<Mode_ARGB8888/RGB888 */
7165
7166#define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
7167#define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
7168#define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
7169#define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
7170
7171/*!<Mode_RGB565 */
7172#define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
7173#define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
7174#define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
7175
7176/*!<Mode_ARGB1555 */
7177#define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
7178#define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
7179#define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
7180#define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
7181
7182/*!<Mode_ARGB4444 */
7183#define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
7184#define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
7185#define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
7186#define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
7187
7188/******************** Bit definition for DMA2D_OMAR register ****************/
7189
7190#define DMA2D_OMAR_MA_Pos (0U)
7191#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
7192#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */
7193
7194/******************** Bit definition for DMA2D_OOR register *****************/
7195
7196#define DMA2D_OOR_LO_Pos (0U)
7197#define DMA2D_OOR_LO_Msk (0x3FFFU << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */
7198#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */
7199
7200/******************** Bit definition for DMA2D_NLR register *****************/
7201
7202#define DMA2D_NLR_NL_Pos (0U)
7203#define DMA2D_NLR_NL_Msk (0xFFFFU << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
7204#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
7205#define DMA2D_NLR_PL_Pos (16U)
7206#define DMA2D_NLR_PL_Msk (0x3FFFU << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
7207#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
7208
7209/******************** Bit definition for DMA2D_LWR register *****************/
7210
7211#define DMA2D_LWR_LW_Pos (0U)
7212#define DMA2D_LWR_LW_Msk (0xFFFFU << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
7213#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
7214
7215/******************** Bit definition for DMA2D_AMTCR register ***************/
7216
7217#define DMA2D_AMTCR_EN_Pos (0U)
7218#define DMA2D_AMTCR_EN_Msk (0x1U << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
7219#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
7220#define DMA2D_AMTCR_DT_Pos (8U)
7221#define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
7222#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
7223
7224
7225/******************** Bit definition for DMA2D_FGCLUT register **************/
7226
7227/******************** Bit definition for DMA2D_BGCLUT register **************/
7228
7229/******************************************************************************/
7230/* */
7231/* External Interrupt/Event Controller */
7232/* */
7233/******************************************************************************/
7234/******************* Bit definition for EXTI_IMR register *******************/
7235#define EXTI_IMR_MR0_Pos (0U)
7236#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
7237#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
7238#define EXTI_IMR_MR1_Pos (1U)
7239#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
7240#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
7241#define EXTI_IMR_MR2_Pos (2U)
7242#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
7243#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
7244#define EXTI_IMR_MR3_Pos (3U)
7245#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
7246#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
7247#define EXTI_IMR_MR4_Pos (4U)
7248#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
7249#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
7250#define EXTI_IMR_MR5_Pos (5U)
7251#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
7252#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
7253#define EXTI_IMR_MR6_Pos (6U)
7254#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
7255#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
7256#define EXTI_IMR_MR7_Pos (7U)
7257#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
7258#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
7259#define EXTI_IMR_MR8_Pos (8U)
7260#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
7261#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
7262#define EXTI_IMR_MR9_Pos (9U)
7263#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
7264#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
7265#define EXTI_IMR_MR10_Pos (10U)
7266#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
7267#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
7268#define EXTI_IMR_MR11_Pos (11U)
7269#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
7270#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
7271#define EXTI_IMR_MR12_Pos (12U)
7272#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
7273#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
7274#define EXTI_IMR_MR13_Pos (13U)
7275#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
7276#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
7277#define EXTI_IMR_MR14_Pos (14U)
7278#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
7279#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
7280#define EXTI_IMR_MR15_Pos (15U)
7281#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
7282#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
7283#define EXTI_IMR_MR16_Pos (16U)
7284#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
7285#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
7286#define EXTI_IMR_MR17_Pos (17U)
7287#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
7288#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
7289#define EXTI_IMR_MR18_Pos (18U)
7290#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
7291#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
7292#define EXTI_IMR_MR19_Pos (19U)
7293#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
7294#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
7295#define EXTI_IMR_MR20_Pos (20U)
7296#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
7297#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
7298#define EXTI_IMR_MR21_Pos (21U)
7299#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
7300#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
7301#define EXTI_IMR_MR22_Pos (22U)
7302#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
7303#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
7304#define EXTI_IMR_MR23_Pos (23U)
7305#define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
7306#define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
7307#define EXTI_IMR_MR24_Pos (24U)
7308#define EXTI_IMR_MR24_Msk (0x1U << EXTI_IMR_MR24_Pos) /*!< 0x01000000 */
7309#define EXTI_IMR_MR24 EXTI_IMR_MR24_Msk /*!< Interrupt Mask on line 24 */
7310
7311/* Reference Defines */
7312#define EXTI_IMR_IM0 EXTI_IMR_MR0
7313#define EXTI_IMR_IM1 EXTI_IMR_MR1
7314#define EXTI_IMR_IM2 EXTI_IMR_MR2
7315#define EXTI_IMR_IM3 EXTI_IMR_MR3
7316#define EXTI_IMR_IM4 EXTI_IMR_MR4
7317#define EXTI_IMR_IM5 EXTI_IMR_MR5
7318#define EXTI_IMR_IM6 EXTI_IMR_MR6
7319#define EXTI_IMR_IM7 EXTI_IMR_MR7
7320#define EXTI_IMR_IM8 EXTI_IMR_MR8
7321#define EXTI_IMR_IM9 EXTI_IMR_MR9
7322#define EXTI_IMR_IM10 EXTI_IMR_MR10
7323#define EXTI_IMR_IM11 EXTI_IMR_MR11
7324#define EXTI_IMR_IM12 EXTI_IMR_MR12
7325#define EXTI_IMR_IM13 EXTI_IMR_MR13
7326#define EXTI_IMR_IM14 EXTI_IMR_MR14
7327#define EXTI_IMR_IM15 EXTI_IMR_MR15
7328#define EXTI_IMR_IM16 EXTI_IMR_MR16
7329#define EXTI_IMR_IM17 EXTI_IMR_MR17
7330#define EXTI_IMR_IM18 EXTI_IMR_MR18
7331#define EXTI_IMR_IM19 EXTI_IMR_MR19
7332#define EXTI_IMR_IM20 EXTI_IMR_MR20
7333#define EXTI_IMR_IM21 EXTI_IMR_MR21
7334#define EXTI_IMR_IM22 EXTI_IMR_MR22
7335#define EXTI_IMR_IM23 EXTI_IMR_MR23
7336#define EXTI_IMR_IM24 EXTI_IMR_MR24
7337
7338#define EXTI_IMR_IM_Pos (0U)
7339#define EXTI_IMR_IM_Msk (0x1FFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x01FFFFFF */
7340#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
7341
7342/******************* Bit definition for EXTI_EMR register *******************/
7343#define EXTI_EMR_MR0_Pos (0U)
7344#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
7345#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
7346#define EXTI_EMR_MR1_Pos (1U)
7347#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
7348#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
7349#define EXTI_EMR_MR2_Pos (2U)
7350#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
7351#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
7352#define EXTI_EMR_MR3_Pos (3U)
7353#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
7354#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
7355#define EXTI_EMR_MR4_Pos (4U)
7356#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
7357#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
7358#define EXTI_EMR_MR5_Pos (5U)
7359#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
7360#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
7361#define EXTI_EMR_MR6_Pos (6U)
7362#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
7363#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
7364#define EXTI_EMR_MR7_Pos (7U)
7365#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
7366#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
7367#define EXTI_EMR_MR8_Pos (8U)
7368#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
7369#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
7370#define EXTI_EMR_MR9_Pos (9U)
7371#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
7372#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
7373#define EXTI_EMR_MR10_Pos (10U)
7374#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
7375#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
7376#define EXTI_EMR_MR11_Pos (11U)
7377#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
7378#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
7379#define EXTI_EMR_MR12_Pos (12U)
7380#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
7381#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
7382#define EXTI_EMR_MR13_Pos (13U)
7383#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
7384#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
7385#define EXTI_EMR_MR14_Pos (14U)
7386#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
7387#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
7388#define EXTI_EMR_MR15_Pos (15U)
7389#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
7390#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
7391#define EXTI_EMR_MR16_Pos (16U)
7392#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
7393#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
7394#define EXTI_EMR_MR17_Pos (17U)
7395#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
7396#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
7397#define EXTI_EMR_MR18_Pos (18U)
7398#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
7399#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
7400#define EXTI_EMR_MR19_Pos (19U)
7401#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
7402#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
7403#define EXTI_EMR_MR20_Pos (20U)
7404#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
7405#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
7406#define EXTI_EMR_MR21_Pos (21U)
7407#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
7408#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
7409#define EXTI_EMR_MR22_Pos (22U)
7410#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
7411#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
7412#define EXTI_EMR_MR23_Pos (23U)
7413#define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
7414#define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
7415#define EXTI_EMR_MR24_Pos (24U)
7416#define EXTI_EMR_MR24_Msk (0x1U << EXTI_EMR_MR24_Pos) /*!< 0x01000000 */
7417#define EXTI_EMR_MR24 EXTI_EMR_MR24_Msk /*!< Event Mask on line 24 */
7418
7419/* Reference Defines */
7420#define EXTI_EMR_EM0 EXTI_EMR_MR0
7421#define EXTI_EMR_EM1 EXTI_EMR_MR1
7422#define EXTI_EMR_EM2 EXTI_EMR_MR2
7423#define EXTI_EMR_EM3 EXTI_EMR_MR3
7424#define EXTI_EMR_EM4 EXTI_EMR_MR4
7425#define EXTI_EMR_EM5 EXTI_EMR_MR5
7426#define EXTI_EMR_EM6 EXTI_EMR_MR6
7427#define EXTI_EMR_EM7 EXTI_EMR_MR7
7428#define EXTI_EMR_EM8 EXTI_EMR_MR8
7429#define EXTI_EMR_EM9 EXTI_EMR_MR9
7430#define EXTI_EMR_EM10 EXTI_EMR_MR10
7431#define EXTI_EMR_EM11 EXTI_EMR_MR11
7432#define EXTI_EMR_EM12 EXTI_EMR_MR12
7433#define EXTI_EMR_EM13 EXTI_EMR_MR13
7434#define EXTI_EMR_EM14 EXTI_EMR_MR14
7435#define EXTI_EMR_EM15 EXTI_EMR_MR15
7436#define EXTI_EMR_EM16 EXTI_EMR_MR16
7437#define EXTI_EMR_EM17 EXTI_EMR_MR17
7438#define EXTI_EMR_EM18 EXTI_EMR_MR18
7439#define EXTI_EMR_EM19 EXTI_EMR_MR19
7440#define EXTI_EMR_EM20 EXTI_EMR_MR20
7441#define EXTI_EMR_EM21 EXTI_EMR_MR21
7442#define EXTI_EMR_EM22 EXTI_EMR_MR22
7443#define EXTI_EMR_EM23 EXTI_EMR_MR23
7444#define EXTI_EMR_EM24 EXTI_EMR_MR24
7445
7446
7447/****************** Bit definition for EXTI_RTSR register *******************/
7448#define EXTI_RTSR_TR0_Pos (0U)
7449#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
7450#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
7451#define EXTI_RTSR_TR1_Pos (1U)
7452#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
7453#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
7454#define EXTI_RTSR_TR2_Pos (2U)
7455#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
7456#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
7457#define EXTI_RTSR_TR3_Pos (3U)
7458#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
7459#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
7460#define EXTI_RTSR_TR4_Pos (4U)
7461#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
7462#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
7463#define EXTI_RTSR_TR5_Pos (5U)
7464#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
7465#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
7466#define EXTI_RTSR_TR6_Pos (6U)
7467#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
7468#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
7469#define EXTI_RTSR_TR7_Pos (7U)
7470#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
7471#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
7472#define EXTI_RTSR_TR8_Pos (8U)
7473#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
7474#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
7475#define EXTI_RTSR_TR9_Pos (9U)
7476#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
7477#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
7478#define EXTI_RTSR_TR10_Pos (10U)
7479#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
7480#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
7481#define EXTI_RTSR_TR11_Pos (11U)
7482#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
7483#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
7484#define EXTI_RTSR_TR12_Pos (12U)
7485#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
7486#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
7487#define EXTI_RTSR_TR13_Pos (13U)
7488#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
7489#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
7490#define EXTI_RTSR_TR14_Pos (14U)
7491#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
7492#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
7493#define EXTI_RTSR_TR15_Pos (15U)
7494#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
7495#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
7496#define EXTI_RTSR_TR16_Pos (16U)
7497#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
7498#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
7499#define EXTI_RTSR_TR17_Pos (17U)
7500#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
7501#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
7502#define EXTI_RTSR_TR18_Pos (18U)
7503#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
7504#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
7505#define EXTI_RTSR_TR19_Pos (19U)
7506#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
7507#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
7508#define EXTI_RTSR_TR20_Pos (20U)
7509#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
7510#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
7511#define EXTI_RTSR_TR21_Pos (21U)
7512#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
7513#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
7514#define EXTI_RTSR_TR22_Pos (22U)
7515#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
7516#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
7517#define EXTI_RTSR_TR23_Pos (23U)
7518#define EXTI_RTSR_TR23_Msk (0x1U << EXTI_RTSR_TR23_Pos) /*!< 0x00800000 */
7519#define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk /*!< Rising trigger event configuration bit of line 23 */
7520#define EXTI_RTSR_TR24_Pos (24U)
7521#define EXTI_RTSR_TR24_Msk (0x1U << EXTI_RTSR_TR24_Pos) /*!< 0x01000000 */
7522#define EXTI_RTSR_TR24 EXTI_RTSR_TR24_Msk /*!< Rising trigger event configuration bit of line 24 */
7523
7524/****************** Bit definition for EXTI_FTSR register *******************/
7525#define EXTI_FTSR_TR0_Pos (0U)
7526#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
7527#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
7528#define EXTI_FTSR_TR1_Pos (1U)
7529#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
7530#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
7531#define EXTI_FTSR_TR2_Pos (2U)
7532#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
7533#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
7534#define EXTI_FTSR_TR3_Pos (3U)
7535#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
7536#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
7537#define EXTI_FTSR_TR4_Pos (4U)
7538#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
7539#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
7540#define EXTI_FTSR_TR5_Pos (5U)
7541#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
7542#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
7543#define EXTI_FTSR_TR6_Pos (6U)
7544#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
7545#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
7546#define EXTI_FTSR_TR7_Pos (7U)
7547#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
7548#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
7549#define EXTI_FTSR_TR8_Pos (8U)
7550#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
7551#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
7552#define EXTI_FTSR_TR9_Pos (9U)
7553#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
7554#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
7555#define EXTI_FTSR_TR10_Pos (10U)
7556#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
7557#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
7558#define EXTI_FTSR_TR11_Pos (11U)
7559#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
7560#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
7561#define EXTI_FTSR_TR12_Pos (12U)
7562#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
7563#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
7564#define EXTI_FTSR_TR13_Pos (13U)
7565#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
7566#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
7567#define EXTI_FTSR_TR14_Pos (14U)
7568#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
7569#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
7570#define EXTI_FTSR_TR15_Pos (15U)
7571#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
7572#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
7573#define EXTI_FTSR_TR16_Pos (16U)
7574#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
7575#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
7576#define EXTI_FTSR_TR17_Pos (17U)
7577#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
7578#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
7579#define EXTI_FTSR_TR18_Pos (18U)
7580#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
7581#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
7582#define EXTI_FTSR_TR19_Pos (19U)
7583#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
7584#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
7585#define EXTI_FTSR_TR20_Pos (20U)
7586#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
7587#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
7588#define EXTI_FTSR_TR21_Pos (21U)
7589#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
7590#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
7591#define EXTI_FTSR_TR22_Pos (22U)
7592#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
7593#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
7594#define EXTI_FTSR_TR23_Pos (23U)
7595#define EXTI_FTSR_TR23_Msk (0x1U << EXTI_FTSR_TR23_Pos) /*!< 0x00800000 */
7596#define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk /*!< Falling trigger event configuration bit of line 23 */
7597#define EXTI_FTSR_TR24_Pos (24U)
7598#define EXTI_FTSR_TR24_Msk (0x1U << EXTI_FTSR_TR24_Pos) /*!< 0x01000000 */
7599#define EXTI_FTSR_TR24 EXTI_FTSR_TR24_Msk /*!< Falling trigger event configuration bit of line 24 */
7600
7601/****************** Bit definition for EXTI_SWIER register ******************/
7602#define EXTI_SWIER_SWIER0_Pos (0U)
7603#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
7604#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
7605#define EXTI_SWIER_SWIER1_Pos (1U)
7606#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
7607#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
7608#define EXTI_SWIER_SWIER2_Pos (2U)
7609#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
7610#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
7611#define EXTI_SWIER_SWIER3_Pos (3U)
7612#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
7613#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
7614#define EXTI_SWIER_SWIER4_Pos (4U)
7615#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
7616#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
7617#define EXTI_SWIER_SWIER5_Pos (5U)
7618#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
7619#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
7620#define EXTI_SWIER_SWIER6_Pos (6U)
7621#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
7622#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
7623#define EXTI_SWIER_SWIER7_Pos (7U)
7624#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
7625#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
7626#define EXTI_SWIER_SWIER8_Pos (8U)
7627#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
7628#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
7629#define EXTI_SWIER_SWIER9_Pos (9U)
7630#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
7631#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
7632#define EXTI_SWIER_SWIER10_Pos (10U)
7633#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
7634#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
7635#define EXTI_SWIER_SWIER11_Pos (11U)
7636#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
7637#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
7638#define EXTI_SWIER_SWIER12_Pos (12U)
7639#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
7640#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
7641#define EXTI_SWIER_SWIER13_Pos (13U)
7642#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
7643#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
7644#define EXTI_SWIER_SWIER14_Pos (14U)
7645#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
7646#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
7647#define EXTI_SWIER_SWIER15_Pos (15U)
7648#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
7649#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
7650#define EXTI_SWIER_SWIER16_Pos (16U)
7651#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
7652#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
7653#define EXTI_SWIER_SWIER17_Pos (17U)
7654#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
7655#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
7656#define EXTI_SWIER_SWIER18_Pos (18U)
7657#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
7658#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
7659#define EXTI_SWIER_SWIER19_Pos (19U)
7660#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
7661#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
7662#define EXTI_SWIER_SWIER20_Pos (20U)
7663#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
7664#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
7665#define EXTI_SWIER_SWIER21_Pos (21U)
7666#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
7667#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
7668#define EXTI_SWIER_SWIER22_Pos (22U)
7669#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
7670#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
7671#define EXTI_SWIER_SWIER23_Pos (23U)
7672#define EXTI_SWIER_SWIER23_Msk (0x1U << EXTI_SWIER_SWIER23_Pos) /*!< 0x00800000 */
7673#define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk /*!< Software Interrupt on line 23 */
7674#define EXTI_SWIER_SWIER24_Pos (24U)
7675#define EXTI_SWIER_SWIER24_Msk (0x1U << EXTI_SWIER_SWIER24_Pos) /*!< 0x01000000 */
7676#define EXTI_SWIER_SWIER24 EXTI_SWIER_SWIER24_Msk /*!< Software Interrupt on line 24 */
7677
7678/******************* Bit definition for EXTI_PR register ********************/
7679#define EXTI_PR_PR0_Pos (0U)
7680#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
7681#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
7682#define EXTI_PR_PR1_Pos (1U)
7683#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
7684#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
7685#define EXTI_PR_PR2_Pos (2U)
7686#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
7687#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
7688#define EXTI_PR_PR3_Pos (3U)
7689#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
7690#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
7691#define EXTI_PR_PR4_Pos (4U)
7692#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
7693#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
7694#define EXTI_PR_PR5_Pos (5U)
7695#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
7696#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
7697#define EXTI_PR_PR6_Pos (6U)
7698#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
7699#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
7700#define EXTI_PR_PR7_Pos (7U)
7701#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
7702#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
7703#define EXTI_PR_PR8_Pos (8U)
7704#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
7705#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
7706#define EXTI_PR_PR9_Pos (9U)
7707#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
7708#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
7709#define EXTI_PR_PR10_Pos (10U)
7710#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
7711#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
7712#define EXTI_PR_PR11_Pos (11U)
7713#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
7714#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
7715#define EXTI_PR_PR12_Pos (12U)
7716#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
7717#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
7718#define EXTI_PR_PR13_Pos (13U)
7719#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
7720#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
7721#define EXTI_PR_PR14_Pos (14U)
7722#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
7723#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
7724#define EXTI_PR_PR15_Pos (15U)
7725#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
7726#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
7727#define EXTI_PR_PR16_Pos (16U)
7728#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
7729#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
7730#define EXTI_PR_PR17_Pos (17U)
7731#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
7732#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
7733#define EXTI_PR_PR18_Pos (18U)
7734#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
7735#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
7736#define EXTI_PR_PR19_Pos (19U)
7737#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
7738#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
7739#define EXTI_PR_PR20_Pos (20U)
7740#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
7741#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
7742#define EXTI_PR_PR21_Pos (21U)
7743#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
7744#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
7745#define EXTI_PR_PR22_Pos (22U)
7746#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
7747#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
7748#define EXTI_PR_PR23_Pos (23U)
7749#define EXTI_PR_PR23_Msk (0x1U << EXTI_PR_PR23_Pos) /*!< 0x00800000 */
7750#define EXTI_PR_PR23 EXTI_PR_PR23_Msk /*!< Pending bit for line 23 */
7751#define EXTI_PR_PR24_Pos (24U)
7752#define EXTI_PR_PR24_Msk (0x1U << EXTI_PR_PR24_Pos) /*!< 0x01000000 */
7753#define EXTI_PR_PR24 EXTI_PR_PR24_Msk /*!< Pending bit for line 24 */
7754
7755/******************************************************************************/
7756/* */
7757/* FLASH */
7758/* */
7759/******************************************************************************/
7760/*
7761* @brief FLASH Total Sectors Number
7762*/
7763#define FLASH_SECTOR_TOTAL 24
7764
7765/******************* Bits definition for FLASH_ACR register *****************/
7766#define FLASH_ACR_LATENCY_Pos (0U)
7767#define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
7768#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
7769#define FLASH_ACR_LATENCY_0WS 0x00000000U
7770#define FLASH_ACR_LATENCY_1WS 0x00000001U
7771#define FLASH_ACR_LATENCY_2WS 0x00000002U
7772#define FLASH_ACR_LATENCY_3WS 0x00000003U
7773#define FLASH_ACR_LATENCY_4WS 0x00000004U
7774#define FLASH_ACR_LATENCY_5WS 0x00000005U
7775#define FLASH_ACR_LATENCY_6WS 0x00000006U
7776#define FLASH_ACR_LATENCY_7WS 0x00000007U
7777#define FLASH_ACR_LATENCY_8WS 0x00000008U
7778#define FLASH_ACR_LATENCY_9WS 0x00000009U
7779#define FLASH_ACR_LATENCY_10WS 0x0000000AU
7780#define FLASH_ACR_LATENCY_11WS 0x0000000BU
7781#define FLASH_ACR_LATENCY_12WS 0x0000000CU
7782#define FLASH_ACR_LATENCY_13WS 0x0000000DU
7783#define FLASH_ACR_LATENCY_14WS 0x0000000EU
7784#define FLASH_ACR_LATENCY_15WS 0x0000000FU
7785#define FLASH_ACR_PRFTEN_Pos (8U)
7786#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
7787#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
7788#define FLASH_ACR_ARTEN_Pos (9U)
7789#define FLASH_ACR_ARTEN_Msk (0x1U << FLASH_ACR_ARTEN_Pos) /*!< 0x00000200 */
7790#define FLASH_ACR_ARTEN FLASH_ACR_ARTEN_Msk
7791#define FLASH_ACR_ARTRST_Pos (11U)
7792#define FLASH_ACR_ARTRST_Msk (0x1U << FLASH_ACR_ARTRST_Pos) /*!< 0x00000800 */
7793#define FLASH_ACR_ARTRST FLASH_ACR_ARTRST_Msk
7794
7795/******************* Bits definition for FLASH_SR register ******************/
7796#define FLASH_SR_EOP_Pos (0U)
7797#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
7798#define FLASH_SR_EOP FLASH_SR_EOP_Msk
7799#define FLASH_SR_OPERR_Pos (1U)
7800#define FLASH_SR_OPERR_Msk (0x1U << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
7801#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
7802#define FLASH_SR_WRPERR_Pos (4U)
7803#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
7804#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
7805#define FLASH_SR_PGAERR_Pos (5U)
7806#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
7807#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
7808#define FLASH_SR_PGPERR_Pos (6U)
7809#define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
7810#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
7811#define FLASH_SR_ERSERR_Pos (7U)
7812#define FLASH_SR_ERSERR_Msk (0x1U << FLASH_SR_ERSERR_Pos) /*!< 0x00000080 */
7813#define FLASH_SR_ERSERR FLASH_SR_ERSERR_Msk
7814#define FLASH_SR_BSY_Pos (16U)
7815#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
7816#define FLASH_SR_BSY FLASH_SR_BSY_Msk
7817
7818/******************* Bits definition for FLASH_CR register ******************/
7819#define FLASH_CR_PG_Pos (0U)
7820#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
7821#define FLASH_CR_PG FLASH_CR_PG_Msk
7822#define FLASH_CR_SER_Pos (1U)
7823#define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
7824#define FLASH_CR_SER FLASH_CR_SER_Msk
7825#define FLASH_CR_MER_Pos (2U)
7826#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
7827#define FLASH_CR_MER FLASH_CR_MER_Msk
7828#define FLASH_CR_MER1 FLASH_CR_MER
7829#define FLASH_CR_SNB_Pos (3U)
7830#define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
7831#define FLASH_CR_SNB FLASH_CR_SNB_Msk
7832#define FLASH_CR_SNB_0 0x00000008U
7833#define FLASH_CR_SNB_1 0x00000010U
7834#define FLASH_CR_SNB_2 0x00000020U
7835#define FLASH_CR_SNB_3 0x00000040U
7836#define FLASH_CR_SNB_4 0x00000080U
7837#define FLASH_CR_PSIZE_Pos (8U)
7838#define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
7839#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
7840#define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
7841#define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
7842#define FLASH_CR_MER2_Pos (15U)
7843#define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
7844#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
7845#define FLASH_CR_STRT_Pos (16U)
7846#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
7847#define FLASH_CR_STRT FLASH_CR_STRT_Msk
7848#define FLASH_CR_EOPIE_Pos (24U)
7849#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos)