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authorAkshay <[email protected]>2022-04-10 12:13:40 +0100
committerAkshay <[email protected]>2022-04-10 12:13:40 +0100
commitdc90387ce7d8ba7b607d9c48540bf6d8b560f14d (patch)
tree4ccb8fa5886b66fa9d480edef74236c27f035e16 /lib/chibios/os/common/ext/ST/STM32H7xx/stm32h743xx.h
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diff --git a/lib/chibios/os/common/ext/ST/STM32H7xx/stm32h743xx.h b/lib/chibios/os/common/ext/ST/STM32H7xx/stm32h743xx.h
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1/**
2 ******************************************************************************
3 * @file stm32h743xx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32H743xx Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
16 * All rights reserved.</center></h2>
17 *
18 * This software component is licensed by ST under BSD 3-Clause license,
19 * the "License"; You may not use this file except in compliance with the
20 * License. You may obtain a copy of the License at:
21 * opensource.org/licenses/BSD-3-Clause
22 *
23 ******************************************************************************
24 */
25
26/** @addtogroup CMSIS_Device
27 * @{
28 */
29
30/** @addtogroup stm32h743xx
31 * @{
32 */
33
34#ifndef STM32H743xx_H
35#define STM32H743xx_H
36
37#ifdef __cplusplus
38 extern "C" {
39#endif /* __cplusplus */
40
41/** @addtogroup Peripheral_interrupt_number_definition
42 * @{
43 */
44
45/**
46 * @brief STM32H7XX Interrupt Number Definition, according to the selected device
47 * in @ref Library_configuration_section
48 */
49typedef enum
50{
51/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
52 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
53 HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
54 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
55 BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
56 UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
57 SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
58 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */
59 PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
60 SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
61/****** STM32 specific Interrupt Numbers **********************************************************************/
62 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
63 PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */
64 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
65 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
66 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
67 RCC_IRQn = 5, /*!< RCC global Interrupt */
68 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
69 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
70 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
71 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
72 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
73 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
74 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
75 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
76 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
77 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
78 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
79 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
80 ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */
81 FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */
82 FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */
83 FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */
84 FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */
85 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
86 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
87 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
88 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
89 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
90 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
91 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
92 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
93 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
94 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
95 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
96 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
97 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
98 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
99 USART1_IRQn = 37, /*!< USART1 global Interrupt */
100 USART2_IRQn = 38, /*!< USART2 global Interrupt */
101 USART3_IRQn = 39, /*!< USART3 global Interrupt */
102 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
103 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
104 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
105 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
106 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
107 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
108 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
109 FMC_IRQn = 48, /*!< FMC global Interrupt */
110 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
111 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
112 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
113 UART4_IRQn = 52, /*!< UART4 global Interrupt */
114 UART5_IRQn = 53, /*!< UART5 global Interrupt */
115 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
116 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
117 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
118 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
119 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
120 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
121 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
122 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
123 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
124 FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */
125 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
126 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
127 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
128 USART6_IRQn = 71, /*!< USART6 global interrupt */
129 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
130 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
131 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
132 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
133 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
134 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
135 DCMI_IRQn = 78, /*!< DCMI global interrupt */
136 RNG_IRQn = 80, /*!< RNG global interrupt */
137 FPU_IRQn = 81, /*!< FPU global interrupt */
138 UART7_IRQn = 82, /*!< UART7 global interrupt */
139 UART8_IRQn = 83, /*!< UART8 global interrupt */
140 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
141 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
142 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
143 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
144 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
145 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
146 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
147 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
148 QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
149 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
150 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
151 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
152 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
153 SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
154 OTG_FS_EP1_OUT_IRQn = 98, /*!< USB OTG HS2 global interrupt */
155 OTG_FS_EP1_IN_IRQn = 99, /*!< USB OTG HS2 End Point 1 Out global interrupt */
156 OTG_FS_WKUP_IRQn = 100, /*!< USB OTG HS2 End Point 1 In global interrupt */
157 OTG_FS_IRQn = 101, /*!< USB OTG HS2 Wakeup through EXTI interrupt */
158 DMAMUX1_OVR_IRQn = 102, /*!<DMAMUX1 Overrun interrupt */
159 HRTIM1_Master_IRQn = 103, /*!< HRTIM Master Timer global Interrupts */
160 HRTIM1_TIMA_IRQn = 104, /*!< HRTIM Timer A global Interrupt */
161 HRTIM1_TIMB_IRQn = 105, /*!< HRTIM Timer B global Interrupt */
162 HRTIM1_TIMC_IRQn = 106, /*!< HRTIM Timer C global Interrupt */
163 HRTIM1_TIMD_IRQn = 107, /*!< HRTIM Timer D global Interrupt */
164 HRTIM1_TIME_IRQn = 108, /*!< HRTIM Timer E global Interrupt */
165 HRTIM1_FLT_IRQn = 109, /*!< HRTIM Fault global Interrupt */
166 DFSDM1_FLT0_IRQn = 110, /*!<DFSDM Filter1 Interrupt */
167 DFSDM1_FLT1_IRQn = 111, /*!<DFSDM Filter2 Interrupt */
168 DFSDM1_FLT2_IRQn = 112, /*!<DFSDM Filter3 Interrupt */
169 DFSDM1_FLT3_IRQn = 113, /*!<DFSDM Filter4 Interrupt */
170 SAI3_IRQn = 114, /*!< SAI3 global Interrupt */
171 SWPMI1_IRQn = 115, /*!< Serial Wire Interface 1 global interrupt */
172 TIM15_IRQn = 116, /*!< TIM15 global Interrupt */
173 TIM16_IRQn = 117, /*!< TIM16 global Interrupt */
174 TIM17_IRQn = 118, /*!< TIM17 global Interrupt */
175 MDIOS_WKUP_IRQn = 119, /*!< MDIOS Wakeup Interrupt */
176 MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */
177 JPEG_IRQn = 121, /*!< JPEG global Interrupt */
178 MDMA_IRQn = 122, /*!< MDMA global Interrupt */
179 SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */
180 HSEM1_IRQn = 125, /*!< HSEM1 global Interrupt */
181 ADC3_IRQn = 127, /*!< ADC3 global Interrupt */
182 DMAMUX2_OVR_IRQn = 128, /*!<DMAMUX2 Overrun interrupt */
183 BDMA_Channel0_IRQn = 129, /*!< BDMA Channel 0 global Interrupt */
184 BDMA_Channel1_IRQn = 130, /*!< BDMA Channel 1 global Interrupt */
185 BDMA_Channel2_IRQn = 131, /*!< BDMA Channel 2 global Interrupt */
186 BDMA_Channel3_IRQn = 132, /*!< BDMA Channel 3 global Interrupt */
187 BDMA_Channel4_IRQn = 133, /*!< BDMA Channel 4 global Interrupt */
188 BDMA_Channel5_IRQn = 134, /*!< BDMA Channel 5 global Interrupt */
189 BDMA_Channel6_IRQn = 135, /*!< BDMA Channel 6 global Interrupt */
190 BDMA_Channel7_IRQn = 136, /*!< BDMA Channel 7 global Interrupt */
191 COMP_IRQn = 137 , /*!< COMP global Interrupt */
192 LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */
193 LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */
194 LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */
195 LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */
196 LPUART1_IRQn = 142, /*!< LP UART1 interrupt */
197 CRS_IRQn = 144, /*!< Clock Recovery Global Interrupt */
198 ECC_IRQn = 145, /*!< ECC diagnostic Global Interrupt */
199 SAI4_IRQn = 146, /*!< SAI4 global interrupt */
200 WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */
201} IRQn_Type;
202
203/**
204 * @}
205 */
206
207/** @addtogroup Configuration_section_for_CMSIS
208 * @{
209 */
210
211
212
213
214/**
215 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
216 */
217#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
218#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
219#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
220#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
221#define __FPU_PRESENT 1 /*!< FPU present */
222#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
223#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
224#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
225
226/**
227 * @}
228 */
229
230
231
232
233#include "system_stm32h7xx.h"
234#include <stdint.h>
235
236/** @addtogroup Peripheral_registers_structures
237 * @{
238 */
239
240/**
241 * @brief Analog to Digital Converter
242 */
243
244typedef struct
245{
246 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
247 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
248 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
249 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
250 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
251 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
252 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
253 __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */
254 __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
255 __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
256 uint32_t RESERVED1; /*!< Reserved, 0x028 */
257 uint32_t RESERVED2; /*!< Reserved, 0x02C */
258 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
259 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
260 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
261 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
262 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
263 uint32_t RESERVED3; /*!< Reserved, 0x044 */
264 uint32_t RESERVED4; /*!< Reserved, 0x048 */
265 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
266 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
267 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
268 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
269 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
270 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
271 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
272 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
273 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
274 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
275 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
276 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
277 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
278 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
279 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
280 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
281 __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */
282 __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */
283 __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */
284 __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */
285 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */
286 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */
287 __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */
288} ADC_TypeDef;
289
290
291typedef struct
292{
293__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
294uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
295__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
296__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
297__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
298
299} ADC_Common_TypeDef;
300
301
302/**
303 * @brief VREFBUF
304 */
305
306typedef struct
307{
308 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
309 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
310} VREFBUF_TypeDef;
311
312
313/**
314 * @brief FD Controller Area Network
315 */
316
317typedef struct
318{
319 __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
320 __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
321 __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */
322 __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
323 __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
324 __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
325 __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
326 __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
327 __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
328 __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
329 __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
330 __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
331 __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
332 __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
333 __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
334 __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
335 __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */
336 __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
337 __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
338 __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
339 __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
340 __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
341 __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
342 __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */
343 __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */
344 __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */
345 __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */
346 __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */
347 __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */
348 __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */
349 __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */
350 __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */
351 __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */
352 __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */
353 __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */
354 __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */
355 __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */
356 __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */
357 __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
358 __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
359 __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */
360 __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */
361 __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */
362 __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */
363 __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */
364 __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */
365 __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */
366 __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
367 __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */
368 __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */
369 __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */
370 __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */
371 __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */
372} FDCAN_GlobalTypeDef;
373
374/**
375 * @brief TTFD Controller Area Network
376 */
377
378typedef struct
379{
380 __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */
381 __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */
382 __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */
383 __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */
384 __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */
385 __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */
386 __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */
387 __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */
388 __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */
389 __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */
390 __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */
391 __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */
392 __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */
393 __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */
394 __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */
395 __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */
396 __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */
397 __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */
398 __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */
399} TTCAN_TypeDef;
400
401/**
402 * @brief FD Controller Area Network
403 */
404
405typedef struct
406{
407 __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
408 __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */
409 __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */
410 __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */
411 __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */
412 __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */
413} FDCAN_ClockCalibrationUnit_TypeDef;
414
415
416/**
417 * @brief Consumer Electronics Control
418 */
419
420typedef struct
421{
422 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
423 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
424 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
425 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
426 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
427 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
428}CEC_TypeDef;
429
430/**
431 * @brief CRC calculation unit
432 */
433
434typedef struct
435{
436 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
437 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
438 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
439 uint32_t RESERVED2; /*!< Reserved, 0x0C */
440 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
441 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
442} CRC_TypeDef;
443
444
445/**
446 * @brief Clock Recovery System
447 */
448typedef struct
449{
450__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
451__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
452__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
453__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
454} CRS_TypeDef;
455
456
457/**
458 * @brief Digital to Analog Converter
459 */
460
461typedef struct
462{
463 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
464 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
465 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
466 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
467 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
468 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
469 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
470 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
471 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
472 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
473 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
474 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
475 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
476 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
477 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
478 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
479 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
480 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
481 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
482 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
483} DAC_TypeDef;
484
485/**
486 * @brief DFSDM module registers
487 */
488typedef struct
489{
490 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
491 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
492 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
493 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
494 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
495 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
496 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
497 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
498 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
499 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
500 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
501 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
502 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
503 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
504 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
505} DFSDM_Filter_TypeDef;
506
507/**
508 * @brief DFSDM channel configuration registers
509 */
510typedef struct
511{
512 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
513 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
514 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
515 short circuit detector register, Address offset: 0x08 */
516 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
517 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
518} DFSDM_Channel_TypeDef;
519
520/**
521 * @brief Debug MCU
522 */
523typedef struct
524{
525 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
526 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
527 uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */
528 __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */
529 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x38 */
530 __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */
531 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x40 */
532 __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */
533 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x48 */
534 __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */
535 uint32_t RESERVED8; /*!< Reserved, Address offset: 0x50 */
536 __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */
537}DBGMCU_TypeDef;
538/**
539 * @brief DCMI
540 */
541
542typedef struct
543{
544 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
545 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
546 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
547 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
548 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
549 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
550 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
551 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
552 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
553 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
554 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
555} DCMI_TypeDef;
556
557/**
558 * @brief DMA Controller
559 */
560
561typedef struct
562{
563 __IO uint32_t CR; /*!< DMA stream x configuration register */
564 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
565 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
566 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
567 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
568 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
569} DMA_Stream_TypeDef;
570
571typedef struct
572{
573 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
574 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
575 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
576 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
577} DMA_TypeDef;
578
579typedef struct
580{
581 __IO uint32_t CCR; /*!< DMA channel x configuration register */
582 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
583 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
584 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */
585 __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */
586} BDMA_Channel_TypeDef;
587
588typedef struct
589{
590 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
591 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
592} BDMA_TypeDef;
593
594typedef struct
595{
596 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */
597}DMAMUX_Channel_TypeDef;
598
599typedef struct
600{
601 __IO uint32_t CSR; /*!< DMA Channel Status Register */
602 __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */
603}DMAMUX_ChannelStatus_TypeDef;
604
605typedef struct
606{
607 __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */
608}DMAMUX_RequestGen_TypeDef;
609
610typedef struct
611{
612 __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */
613 __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */
614}DMAMUX_RequestGenStatus_TypeDef;
615
616/**
617 * @brief MDMA Controller
618 */
619typedef struct
620{
621 __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */
622}MDMA_TypeDef;
623
624typedef struct
625{
626 __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */
627 __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */
628 __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */
629 __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */
630 __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */
631 __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */
632 __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */
633 __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */
634 __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
635 __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
636 __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
637 uint32_t RESERVED0; /*!< Reserved, 0x68 */
638 __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
639 __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
640}MDMA_Channel_TypeDef;
641
642/**
643 * @brief DMA2D Controller
644 */
645
646typedef struct
647{
648 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
649 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
650 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
651 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
652 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
653 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
654 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
655 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
656 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
657 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
658 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
659 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
660 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
661 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
662 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
663 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
664 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
665 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
666 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
667 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
668 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
669 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
670 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
671} DMA2D_TypeDef;
672
673
674/**
675 * @brief Ethernet MAC
676 */
677typedef struct
678{
679 __IO uint32_t MACCR;
680 __IO uint32_t MACECR;
681 __IO uint32_t MACPFR;
682 __IO uint32_t MACWTR;
683 __IO uint32_t MACHT0R;
684 __IO uint32_t MACHT1R;
685 uint32_t RESERVED1[14];
686 __IO uint32_t MACVTR;
687 uint32_t RESERVED2;
688 __IO uint32_t MACVHTR;
689 uint32_t RESERVED3;
690 __IO uint32_t MACVIR;
691 __IO uint32_t MACIVIR;
692 uint32_t RESERVED4[2];
693 __IO uint32_t MACTFCR;
694 uint32_t RESERVED5[7];
695 __IO uint32_t MACRFCR;
696 uint32_t RESERVED6[7];
697 __IO uint32_t MACISR;
698 __IO uint32_t MACIER;
699 __IO uint32_t MACRXTXSR;
700 uint32_t RESERVED7;
701 __IO uint32_t MACPCSR;
702 __IO uint32_t MACRWKPFR;
703 uint32_t RESERVED8[2];
704 __IO uint32_t MACLCSR;
705 __IO uint32_t MACLTCR;
706 __IO uint32_t MACLETR;
707 __IO uint32_t MAC1USTCR;
708 uint32_t RESERVED9[12];
709 __IO uint32_t MACVR;
710 __IO uint32_t MACDR;
711 uint32_t RESERVED10;
712 __IO uint32_t MACHWF0R;
713 __IO uint32_t MACHWF1R;
714 __IO uint32_t MACHWF2R;
715 uint32_t RESERVED11[54];
716 __IO uint32_t MACMDIOAR;
717 __IO uint32_t MACMDIODR;
718 uint32_t RESERVED12[2];
719 __IO uint32_t MACARPAR;
720 uint32_t RESERVED13[59];
721 __IO uint32_t MACA0HR;
722 __IO uint32_t MACA0LR;
723 __IO uint32_t MACA1HR;
724 __IO uint32_t MACA1LR;
725 __IO uint32_t MACA2HR;
726 __IO uint32_t MACA2LR;
727 __IO uint32_t MACA3HR;
728 __IO uint32_t MACA3LR;
729 uint32_t RESERVED14[248];
730 __IO uint32_t MMCCR;
731 __IO uint32_t MMCRIR;
732 __IO uint32_t MMCTIR;
733 __IO uint32_t MMCRIMR;
734 __IO uint32_t MMCTIMR;
735 uint32_t RESERVED15[14];
736 __IO uint32_t MMCTSCGPR;
737 __IO uint32_t MMCTMCGPR;
738 uint32_t RESERVED16[5];
739 __IO uint32_t MMCTPCGR;
740 uint32_t RESERVED17[10];
741 __IO uint32_t MMCRCRCEPR;
742 __IO uint32_t MMCRAEPR;
743 uint32_t RESERVED18[10];
744 __IO uint32_t MMCRUPGR;
745 uint32_t RESERVED19[9];
746 __IO uint32_t MMCTLPIMSTR;
747 __IO uint32_t MMCTLPITCR;
748 __IO uint32_t MMCRLPIMSTR;
749 __IO uint32_t MMCRLPITCR;
750 uint32_t RESERVED20[65];
751 __IO uint32_t MACL3L4C0R;
752 __IO uint32_t MACL4A0R;
753 uint32_t RESERVED21[2];
754 __IO uint32_t MACL3A0R0R;
755 __IO uint32_t MACL3A1R0R;
756 __IO uint32_t MACL3A2R0R;
757 __IO uint32_t MACL3A3R0R;
758 uint32_t RESERVED22[4];
759 __IO uint32_t MACL3L4C1R;
760 __IO uint32_t MACL4A1R;
761 uint32_t RESERVED23[2];
762 __IO uint32_t MACL3A0R1R;
763 __IO uint32_t MACL3A1R1R;
764 __IO uint32_t MACL3A2R1R;
765 __IO uint32_t MACL3A3R1R;
766 uint32_t RESERVED24[108];
767 __IO uint32_t MACTSCR;
768 __IO uint32_t MACSSIR;
769 __IO uint32_t MACSTSR;
770 __IO uint32_t MACSTNR;
771 __IO uint32_t MACSTSUR;
772 __IO uint32_t MACSTNUR;
773 __IO uint32_t MACTSAR;
774 uint32_t RESERVED25;
775 __IO uint32_t MACTSSR;
776 uint32_t RESERVED26[3];
777 __IO uint32_t MACTTSSNR;
778 __IO uint32_t MACTTSSSR;
779 uint32_t RESERVED27[2];
780 __IO uint32_t MACACR;
781 uint32_t RESERVED28;
782 __IO uint32_t MACATSNR;
783 __IO uint32_t MACATSSR;
784 __IO uint32_t MACTSIACR;
785 __IO uint32_t MACTSEACR;
786 __IO uint32_t MACTSICNR;
787 __IO uint32_t MACTSECNR;
788 uint32_t RESERVED29[4];
789 __IO uint32_t MACPPSCR;
790 uint32_t RESERVED30[3];
791 __IO uint32_t MACPPSTTSR;
792 __IO uint32_t MACPPSTTNR;
793 __IO uint32_t MACPPSIR;
794 __IO uint32_t MACPPSWR;
795 uint32_t RESERVED31[12];
796 __IO uint32_t MACPOCR;
797 __IO uint32_t MACSPI0R;
798 __IO uint32_t MACSPI1R;
799 __IO uint32_t MACSPI2R;
800 __IO uint32_t MACLMIR;
801 uint32_t RESERVED32[11];
802 __IO uint32_t MTLOMR;
803 uint32_t RESERVED33[7];
804 __IO uint32_t MTLISR;
805 uint32_t RESERVED34[55];
806 __IO uint32_t MTLTQOMR;
807 __IO uint32_t MTLTQUR;
808 __IO uint32_t MTLTQDR;
809 uint32_t RESERVED35[8];
810 __IO uint32_t MTLQICSR;
811 __IO uint32_t MTLRQOMR;
812 __IO uint32_t MTLRQMPOCR;
813 __IO uint32_t MTLRQDR;
814 uint32_t RESERVED36[177];
815 __IO uint32_t DMAMR;
816 __IO uint32_t DMASBMR;
817 __IO uint32_t DMAISR;
818 __IO uint32_t DMADSR;
819 uint32_t RESERVED37[60];
820 __IO uint32_t DMACCR;
821 __IO uint32_t DMACTCR;
822 __IO uint32_t DMACRCR;
823 uint32_t RESERVED38[2];
824 __IO uint32_t DMACTDLAR;
825 uint32_t RESERVED39;
826 __IO uint32_t DMACRDLAR;
827 __IO uint32_t DMACTDTPR;
828 uint32_t RESERVED40;
829 __IO uint32_t DMACRDTPR;
830 __IO uint32_t DMACTDRLR;
831 __IO uint32_t DMACRDRLR;
832 __IO uint32_t DMACIER;
833 __IO uint32_t DMACRIWTR;
834__IO uint32_t DMACSFCSR;
835 uint32_t RESERVED41;
836 __IO uint32_t DMACCATDR;
837 uint32_t RESERVED42;
838 __IO uint32_t DMACCARDR;
839 uint32_t RESERVED43;
840 __IO uint32_t DMACCATBR;
841 uint32_t RESERVED44;
842 __IO uint32_t DMACCARBR;
843 __IO uint32_t DMACSR;
844uint32_t RESERVED45[2];
845__IO uint32_t DMACMFCR;
846}ETH_TypeDef;
847/**
848 * @brief External Interrupt/Event Controller
849 */
850
851typedef struct
852{
853__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */
854__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */
855__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */
856__IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */
857__IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */
858__IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */
859uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */
860__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */
861__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */
862__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */
863__IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */
864__IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */
865__IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */
866uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */
867__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */
868__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */
869__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */
870__IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */
871__IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */
872__IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */
873uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */
874__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */
875__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */
876__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */
877uint32_t RESERVED4; /*!< Reserved, 0x8C */
878__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */
879__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */
880__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */
881uint32_t RESERVED5; /*!< Reserved, 0x9C */
882__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */
883__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */
884__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
885}EXTI_TypeDef;
886
887typedef struct
888{
889__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
890__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */
891__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */
892uint32_t RESERVED1; /*!< Reserved, 0x0C */
893__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */
894__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */
895__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */
896uint32_t RESERVED2; /*!< Reserved, 0x1C */
897__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
898__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */
899__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */
900}EXTI_Core_TypeDef;
901
902
903/**
904 * @brief FLASH Registers
905 */
906
907typedef struct
908{
909 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
910 __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */
911 __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */
912 __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */
913 __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */
914 __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */
915 __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */
916 __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */
917 __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */
918 __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */
919 __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */
920 __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */
921 __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */
922 __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */
923 __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */
924 __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */
925 __IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */
926 __IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */
927 uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */
928 __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */
929 __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */
930 __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */
931 __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */
932 __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */
933 uint32_t RESERVED1[40]; /*!< Reserved, 0x64 to 0x100 */
934 __IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */
935 uint32_t RESERVED2; /*!< Reserved, 0x108 */
936 __IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */
937 __IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */
938 __IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */
939 uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */
940 __IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */
941 __IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */
942 __IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */
943 __IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */
944 __IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */
945 __IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */
946 uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */
947 __IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */
948 __IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */
949 __IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */
950 __IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */
951 __IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */
952} FLASH_TypeDef;
953
954/**
955 * @brief Flexible Memory Controller
956 */
957
958typedef struct
959{
960 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
961} FMC_Bank1_TypeDef;
962
963/**
964 * @brief Flexible Memory Controller Bank1E
965 */
966
967typedef struct
968{
969 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
970} FMC_Bank1E_TypeDef;
971
972/**
973 * @brief Flexible Memory Controller Bank2
974 */
975
976typedef struct
977{
978 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
979 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
980 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
981 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
982 uint32_t RESERVED0; /*!< Reserved, 0x70 */
983 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
984} FMC_Bank2_TypeDef;
985
986/**
987 * @brief Flexible Memory Controller Bank3
988 */
989
990typedef struct
991{
992 __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */
993 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
994 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
995 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
996 uint32_t RESERVED; /*!< Reserved, 0x90 */
997 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
998} FMC_Bank3_TypeDef;
999
1000/**
1001 * @brief Flexible Memory Controller Bank5 and 6
1002 */
1003
1004
1005typedef struct
1006{
1007 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
1008 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
1009 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
1010 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
1011 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
1012} FMC_Bank5_6_TypeDef;
1013
1014/**
1015 * @brief General Purpose I/O
1016 */
1017
1018typedef struct
1019{
1020 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
1021 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
1022 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
1023 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
1024 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
1025 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
1026 __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */
1027 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
1028 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
1029} GPIO_TypeDef;
1030
1031/**
1032 * @brief Operational Amplifier (OPAMP)
1033 */
1034
1035typedef struct
1036{
1037 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
1038 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
1039 __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
1040} OPAMP_TypeDef;
1041
1042/**
1043 * @brief System configuration controller
1044 */
1045
1046typedef struct
1047{
1048 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */
1049 __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
1050 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
1051 __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */
1052 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
1053 __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */
1054 __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */
1055 __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */
1056 __IO uint32_t PWRCR; /*!< PWR control register, Address offset: 0x2C */
1057 uint32_t RESERVED3[61]; /*!< Reserved, 0x30-0x120 */
1058 __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */
1059 uint32_t RESERVED4[118]; /*!< Reserved, 0x128-0x2FC */
1060 __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */
1061 __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */
1062 __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */
1063 __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */
1064 __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */
1065 __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */
1066 __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */
1067 __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */
1068 __IO uint32_t UR8; /*!< SYSCFG user register 8, Address offset: 0x320 */
1069 __IO uint32_t UR9; /*!< SYSCFG user register 9, Address offset: 0x324 */
1070 __IO uint32_t UR10; /*!< SYSCFG user register 10, Address offset: 0x328 */
1071 __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */
1072 __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */
1073 __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */
1074 __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */
1075 __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */
1076 __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */
1077 __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */
1078
1079} SYSCFG_TypeDef;
1080
1081/**
1082 * @brief Inter-integrated Circuit Interface
1083 */
1084
1085typedef struct
1086{
1087 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
1088 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
1089 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
1090 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
1091 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
1092 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
1093 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
1094 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
1095 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
1096 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
1097 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
1098} I2C_TypeDef;
1099
1100/**
1101 * @brief Independent WATCHDOG
1102 */
1103
1104typedef struct
1105{
1106 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
1107 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
1108 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
1109 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
1110 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
1111} IWDG_TypeDef;
1112
1113
1114/**
1115 * @brief JPEG Codec
1116 */
1117typedef struct
1118{
1119 __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
1120 __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
1121 __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
1122 __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
1123 __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
1124 __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
1125 __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
1126 __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
1127 uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
1128 __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
1129 __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
1130 __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
1131 uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
1132 __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
1133 __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
1134 uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
1135 __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
1136 __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
1137 __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
1138 __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
1139 __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
1140 __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
1141 __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
1142 __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
1143 uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
1144 __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
1145 __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
1146 __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
1147 __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
1148
1149} JPEG_TypeDef;
1150
1151/**
1152 * @brief LCD-TFT Display Controller
1153 */
1154
1155typedef struct
1156{
1157 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
1158 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
1159 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
1160 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
1161 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
1162 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
1163 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
1164 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
1165 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
1166 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
1167 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
1168 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
1169 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
1170 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
1171 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
1172 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
1173 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
1174} LTDC_TypeDef;
1175
1176/**
1177 * @brief LCD-TFT Display layer x Controller
1178 */
1179
1180typedef struct
1181{
1182 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
1183 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
1184 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
1185 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
1186 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
1187 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
1188 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
1189 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
1190 uint32_t RESERVED0[2]; /*!< Reserved */
1191 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
1192 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
1193 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
1194 uint32_t RESERVED1[3]; /*!< Reserved */
1195 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
1196
1197} LTDC_Layer_TypeDef;
1198
1199/**
1200 * @brief Power Control
1201 */
1202
1203typedef struct
1204{
1205 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
1206 __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */
1207 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
1208 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */
1209 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */
1210 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */
1211 __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */
1212 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
1213 __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */
1214 __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */
1215 __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
1216} PWR_TypeDef;
1217
1218/**
1219 * @brief Reset and Clock Control
1220 */
1221
1222typedef struct
1223{
1224 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
1225 __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */
1226 __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */
1227 __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */
1228 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */
1229 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
1230 __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */
1231 __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */
1232 __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */
1233 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
1234 __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */
1235 __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */
1236 __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */
1237 __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */
1238 __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */
1239 __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */
1240 __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */
1241 __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */
1242 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
1243 __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */
1244 __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */
1245 __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */
1246 __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */
1247 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */
1248 __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */
1249 __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */
1250 __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */
1251 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */
1252 __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */
1253 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
1254 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */
1255 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */
1256 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */
1257 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */
1258 __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */
1259 __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */
1260 __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */
1261 __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */
1262 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */
1263 __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */
1264 __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */
1265 uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */
1266 __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */
1267 uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */
1268 __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */
1269 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */
1270 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */
1271 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */
1272 __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */
1273 __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */
1274 __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */
1275 __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */
1276 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */
1277 __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */
1278 uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */
1279 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */
1280 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */
1281 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */
1282 __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */
1283 __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */
1284 __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */
1285 __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */
1286 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */
1287 __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */
1288 uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */
1289
1290} RCC_TypeDef;
1291
1292
1293/**
1294 * @brief Real-Time Clock
1295 */
1296typedef struct
1297{
1298 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
1299 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
1300 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
1301 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
1302 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
1303 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
1304 uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
1305 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
1306 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
1307 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
1308 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
1309 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
1310 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
1311 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
1312 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
1313 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
1314 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
1315 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
1316 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
1317 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
1318 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
1319 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
1320 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
1321 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
1322 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
1323 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
1324 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
1325 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
1326 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
1327 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
1328 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
1329 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
1330 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
1331 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
1332 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
1333 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
1334 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
1335 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
1336 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
1337 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
1338 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
1339 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
1340 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
1341 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
1342 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
1343 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
1344 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
1345 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
1346 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
1347 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
1348 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
1349 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
1350} RTC_TypeDef;
1351
1352/**
1353 * @brief Serial Audio Interface
1354 */
1355
1356typedef struct
1357{
1358 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
1359 uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
1360 __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
1361 __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
1362} SAI_TypeDef;
1363
1364typedef struct
1365{
1366 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
1367 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
1368 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
1369 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
1370 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
1371 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
1372 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
1373 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
1374} SAI_Block_TypeDef;
1375
1376/**
1377 * @brief SPDIF-RX Interface
1378 */
1379
1380typedef struct
1381{
1382 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
1383 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
1384 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
1385 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
1386 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
1387 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
1388 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
1389 uint32_t RESERVED2; /*!< Reserved, 0x1A */
1390} SPDIFRX_TypeDef;
1391
1392
1393/**
1394 * @brief Secure digital input/output Interface
1395 */
1396
1397typedef struct
1398{
1399 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
1400 __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
1401 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
1402 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
1403 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
1404 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
1405 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
1406 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
1407 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
1408 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
1409 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
1410 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
1411 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
1412 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
1413 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
1414 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
1415 __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
1416 uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
1417 __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
1418 __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
1419 __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
1420 __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
1421 uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
1422 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
1423 uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */
1424 __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */
1425} SDMMC_TypeDef;
1426
1427
1428/**
1429 * @brief Delay Block DLYB
1430 */
1431
1432typedef struct
1433{
1434 __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */
1435 __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */
1436} DLYB_TypeDef;
1437
1438/**
1439 * @brief HW Semaphore HSEM
1440 */
1441
1442typedef struct
1443{
1444 __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */
1445 __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */
1446 __IO uint32_t C1IER; /*!< HSEM Interrupt enable register , Address offset: 100h */
1447 __IO uint32_t C1ICR; /*!< HSEM Interrupt clear register , Address offset: 104h */
1448 __IO uint32_t C1ISR; /*!< HSEM Interrupt Status register , Address offset: 108h */
1449 __IO uint32_t C1MISR; /*!< HSEM Interrupt Masked Status register , Address offset: 10Ch */
1450 uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch */
1451 __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */
1452 __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */
1453
1454} HSEM_TypeDef;
1455
1456typedef struct
1457{
1458 __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */
1459 __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */
1460 __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */
1461 __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */
1462} HSEM_Common_TypeDef;
1463
1464/**
1465 * @brief Serial Peripheral Interface
1466 */
1467
1468typedef struct
1469{
1470 __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */
1471 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
1472 __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */
1473 __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */
1474 __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */
1475 __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */
1476 __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */
1477 uint32_t RESERVED0; /*!< Reserved, 0x1C */
1478 __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */
1479 uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */
1480 __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */
1481 uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
1482 __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */
1483 __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */
1484 __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */
1485 __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */
1486 __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */
1487
1488} SPI_TypeDef;
1489/**
1490 * @brief QUAD Serial Peripheral Interface
1491 */
1492
1493typedef struct
1494{
1495 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
1496 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
1497 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
1498 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
1499 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
1500 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
1501 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
1502 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
1503 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
1504 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
1505 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
1506 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
1507 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
1508} QUADSPI_TypeDef;
1509
1510/**
1511 * @brief TIM
1512 */
1513
1514typedef struct
1515{
1516 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
1517 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
1518 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
1519 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
1520 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
1521 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
1522 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
1523 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
1524 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
1525 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
1526 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
1527 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
1528 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
1529 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
1530 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
1531 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
1532 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
1533 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
1534 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
1535 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
1536 uint32_t RESERVED1; /*!< Reserved, 0x50 */
1537 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
1538 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
1539 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
1540 __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
1541 __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
1542 __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
1543} TIM_TypeDef;
1544
1545/**
1546 * @brief LPTIMIMER
1547 */
1548typedef struct
1549{
1550 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
1551 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
1552 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
1553 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
1554 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
1555 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
1556 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
1557 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
1558 uint32_t RESERVED1; /*!< Reserved, 0x20 */
1559 __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */
1560} LPTIM_TypeDef;
1561
1562/**
1563 * @brief Comparator
1564 */
1565typedef struct
1566{
1567 __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */
1568 __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */
1569 __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */
1570} COMPOPT_TypeDef;
1571
1572typedef struct
1573{
1574 __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */
1575} COMP_TypeDef;
1576
1577typedef struct
1578{
1579 __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
1580} COMP_Common_TypeDef;
1581/**
1582 * @brief Universal Synchronous Asynchronous Receiver Transmitter
1583 */
1584
1585typedef struct
1586{
1587 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
1588 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
1589 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
1590 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
1591 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
1592 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
1593 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
1594 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
1595 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
1596 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
1597 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
1598 __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */
1599} USART_TypeDef;
1600
1601/**
1602 * @brief Single Wire Protocol Master Interface SPWMI
1603 */
1604typedef struct
1605{
1606 __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
1607 __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
1608 uint32_t RESERVED1; /*!< Reserved, 0x08 */
1609 __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
1610 __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
1611 __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
1612 __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
1613 __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
1614 __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
1615 __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
1616} SWPMI_TypeDef;
1617
1618/**
1619 * @brief Window WATCHDOG
1620 */
1621
1622typedef struct
1623{
1624 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
1625 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
1626 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
1627} WWDG_TypeDef;
1628
1629
1630/**
1631 * @brief RAM_ECC_Specific_Registers
1632 */
1633typedef struct
1634{
1635 __IO uint32_t CR; /*!< RAMECC monitor configuration register */
1636 __IO uint32_t SR; /*!< RAMECC monitor status register */
1637 __IO uint32_t FAR; /*!< RAMECC monitor failing address register */
1638 __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */
1639 __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */
1640 __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */
1641} RAMECC_MonitorTypeDef;
1642
1643typedef struct
1644{
1645 __IO uint32_t IER; /*!< RAMECC interrupt enable register */
1646} RAMECC_TypeDef;
1647/**
1648 * @}
1649 */
1650
1651
1652
1653/**
1654 * @brief High resolution Timer (HRTIM)
1655 */
1656/* HRTIM master registers definition */
1657typedef struct
1658{
1659 __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
1660 __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
1661 __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
1662 __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
1663 __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
1664 __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
1665 __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */
1666 __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */
1667 uint32_t RESERVED0; /*!< Reserved, 0x20 */
1668 __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */
1669 __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */
1670 __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */
1671 uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */
1672}HRTIM_Master_TypeDef;
1673
1674/* HRTIM Timer A to E registers definition */
1675typedef struct
1676{
1677 __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */
1678 __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */
1679 __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */
1680 __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */
1681 __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */
1682 __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */
1683 __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */
1684 __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */
1685 __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */
1686 __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */
1687 __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */
1688 __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */
1689 __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */
1690 __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */
1691 __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */
1692 __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */
1693 __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */
1694 __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */
1695 __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */
1696 __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */
1697 __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */
1698 __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */
1699 __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */
1700 __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */
1701 __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */
1702 __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */
1703 __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */
1704 uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */
1705}HRTIM_Timerx_TypeDef;
1706
1707/* HRTIM common register definition */
1708typedef struct
1709{
1710 __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */
1711 __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */
1712 __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */
1713 __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */
1714 __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */
1715 __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */
1716 __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
1717 __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
1718 __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
1719 __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
1720 __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
1721 __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
1722 __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
1723 __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */
1724 __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */
1725 __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */
1726 __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */
1727 __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */
1728 __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */
1729 __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x4C */
1730 __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */
1731 __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */
1732 __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */
1733 __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */
1734 __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */
1735 __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */
1736 __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */
1737 __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */
1738 __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */
1739}HRTIM_Common_TypeDef;
1740
1741/* HRTIM register definition */
1742typedef struct {
1743 HRTIM_Master_TypeDef sMasterRegs;
1744 HRTIM_Timerx_TypeDef sTimerxRegs[5];
1745 uint32_t RESERVED0[32];
1746 HRTIM_Common_TypeDef sCommonRegs;
1747}HRTIM_TypeDef;
1748/**
1749 * @brief RNG
1750 */
1751
1752typedef struct
1753{
1754 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
1755 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
1756 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
1757} RNG_TypeDef;
1758
1759/**
1760 * @brief MDIOS
1761 */
1762
1763typedef struct
1764{
1765 __IO uint32_t CR;
1766 __IO uint32_t WRFR;
1767 __IO uint32_t CWRFR;
1768 __IO uint32_t RDFR;
1769 __IO uint32_t CRDFR;
1770 __IO uint32_t SR;
1771 __IO uint32_t CLRFR;
1772 uint32_t RESERVED[57];
1773 __IO uint32_t DINR0;
1774 __IO uint32_t DINR1;
1775 __IO uint32_t DINR2;
1776 __IO uint32_t DINR3;
1777 __IO uint32_t DINR4;
1778 __IO uint32_t DINR5;
1779 __IO uint32_t DINR6;
1780 __IO uint32_t DINR7;
1781 __IO uint32_t DINR8;
1782 __IO uint32_t DINR9;
1783 __IO uint32_t DINR10;
1784 __IO uint32_t DINR11;
1785 __IO uint32_t DINR12;
1786 __IO uint32_t DINR13;
1787 __IO uint32_t DINR14;
1788 __IO uint32_t DINR15;
1789 __IO uint32_t DINR16;
1790 __IO uint32_t DINR17;
1791 __IO uint32_t DINR18;
1792 __IO uint32_t DINR19;
1793 __IO uint32_t DINR20;
1794 __IO uint32_t DINR21;
1795 __IO uint32_t DINR22;
1796 __IO uint32_t DINR23;
1797 __IO uint32_t DINR24;
1798 __IO uint32_t DINR25;
1799 __IO uint32_t DINR26;
1800 __IO uint32_t DINR27;
1801 __IO uint32_t DINR28;
1802 __IO uint32_t DINR29;
1803 __IO uint32_t DINR30;
1804 __IO uint32_t DINR31;
1805 __IO uint32_t DOUTR0;
1806 __IO uint32_t DOUTR1;
1807 __IO uint32_t DOUTR2;
1808 __IO uint32_t DOUTR3;
1809 __IO uint32_t DOUTR4;
1810 __IO uint32_t DOUTR5;
1811 __IO uint32_t DOUTR6;
1812 __IO uint32_t DOUTR7;
1813 __IO uint32_t DOUTR8;
1814 __IO uint32_t DOUTR9;
1815 __IO uint32_t DOUTR10;
1816 __IO uint32_t DOUTR11;
1817 __IO uint32_t DOUTR12;
1818 __IO uint32_t DOUTR13;
1819 __IO uint32_t DOUTR14;
1820 __IO uint32_t DOUTR15;
1821 __IO uint32_t DOUTR16;
1822 __IO uint32_t DOUTR17;
1823 __IO uint32_t DOUTR18;
1824 __IO uint32_t DOUTR19;
1825 __IO uint32_t DOUTR20;
1826 __IO uint32_t DOUTR21;
1827 __IO uint32_t DOUTR22;
1828 __IO uint32_t DOUTR23;
1829 __IO uint32_t DOUTR24;
1830 __IO uint32_t DOUTR25;
1831 __IO uint32_t DOUTR26;
1832 __IO uint32_t DOUTR27;
1833 __IO uint32_t DOUTR28;
1834 __IO uint32_t DOUTR29;
1835 __IO uint32_t DOUTR30;
1836 __IO uint32_t DOUTR31;
1837} MDIOS_TypeDef;
1838
1839
1840/**
1841 * @brief USB_OTG_Core_Registers
1842 */
1843typedef struct
1844{
1845 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
1846 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
1847 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
1848 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
1849 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
1850 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
1851 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
1852 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
1853 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
1854 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
1855 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
1856 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
1857 uint32_t Reserved30[2]; /*!< Reserved 030h */
1858 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
1859 __IO uint32_t CID; /*!< User ID Register 03Ch */
1860 __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
1861 __IO uint32_t GHWCFG1; /* User HW config1 044h*/
1862 __IO uint32_t GHWCFG2; /* User HW config2 048h*/
1863 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
1864 uint32_t Reserved6; /*!< Reserved 050h */
1865 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
1866 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
1867 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
1868 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
1869 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
1870 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
1871 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
1872} USB_OTG_GlobalTypeDef;
1873
1874
1875/**
1876 * @brief USB_OTG_device_Registers
1877 */
1878typedef struct
1879{
1880 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
1881 __IO uint32_t DCTL; /*!< dev Control Register 804h */
1882 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
1883 uint32_t Reserved0C; /*!< Reserved 80Ch */
1884 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
1885 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
1886 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
1887 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
1888 uint32_t Reserved20; /*!< Reserved 820h */
1889 uint32_t Reserved9; /*!< Reserved 824h */
1890 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
1891 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
1892 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
1893 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
1894 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
1895 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
1896 uint32_t Reserved40; /*!< dedicated EP mask 840h */
1897 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
1898 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
1899 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
1900} USB_OTG_DeviceTypeDef;
1901
1902
1903/**
1904 * @brief USB_OTG_IN_Endpoint-Specific_Register
1905 */
1906typedef struct
1907{
1908 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
1909 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
1910 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
1911 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
1912 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
1913 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
1914 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
1915 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
1916} USB_OTG_INEndpointTypeDef;
1917
1918
1919/**
1920 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1921 */
1922typedef struct
1923{
1924 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
1925 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
1926 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
1927 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
1928 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
1929 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
1930 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
1931} USB_OTG_OUTEndpointTypeDef;
1932
1933
1934/**
1935 * @brief USB_OTG_Host_Mode_Register_Structures
1936 */
1937typedef struct
1938{
1939 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
1940 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
1941 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
1942 uint32_t Reserved40C; /*!< Reserved 40Ch */
1943 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
1944 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
1945 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
1946} USB_OTG_HostTypeDef;
1947
1948/**
1949 * @brief USB_OTG_Host_Channel_Specific_Registers
1950 */
1951typedef struct
1952{
1953 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
1954 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
1955 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
1956 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
1957 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
1958 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
1959 uint32_t Reserved[2]; /*!< Reserved */
1960} USB_OTG_HostChannelTypeDef;
1961/**
1962 * @}
1963 */
1964
1965
1966/** @addtogroup Peripheral_memory_map
1967 * @{
1968 */
1969#define D1_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */
1970#define D1_ITCMICP_BASE (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */
1971#define D1_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM */
1972#define D1_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
1973#define D1_AXIICP_BASE (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */
1974#define D1_AXISRAM_BASE (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI */
1975
1976#define D2_AXISRAM_BASE (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI */
1977#define D2_AHBSRAM_BASE (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge */
1978
1979#define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */
1980#define D3_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */
1981
1982#define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/APB Peripherals */
1983#define QSPI_BASE (0x90000000UL) /*!< Base address of : QSPI memories accessible over AXI */
1984
1985#define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */
1986#define FLASH_BANK2_BASE (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI */
1987#define FLASH_END (0x081FFFFFUL) /*!< FLASH end address */
1988
1989/* Legacy define */
1990#define FLASH_BASE FLASH_BANK1_BASE
1991
1992/*!< Device electronic signature memory map */
1993#define UID_BASE (0x1FF1E800UL) /*!< Unique device ID register base address */
1994#define FLASHSIZE_BASE (0x1FF1E880UL) /*!< FLASH Size register base address */
1995
1996
1997/*!< Peripheral memory map */
1998#define D2_APB1PERIPH_BASE PERIPH_BASE
1999#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
2000#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
2001#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL)
2002
2003#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
2004#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL)
2005
2006#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL)
2007#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL)
2008
2009/*!< Legacy Peripheral memory map */
2010#define APB1PERIPH_BASE PERIPH_BASE
2011#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
2012#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
2013#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
2014
2015
2016/*!< D1_AHB1PERIPH peripherals */
2017
2018#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL)
2019#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL)
2020#define JPGDEC_BASE (D1_AHB1PERIPH_BASE + 0x3000UL)
2021#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL)
2022#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL)
2023#define QSPI_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL)
2024#define DLYB_QSPI_BASE (D1_AHB1PERIPH_BASE + 0x6000UL)
2025#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL)
2026#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL)
2027#define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL)
2028
2029/*!< D2_AHB1PERIPH peripherals */
2030
2031#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL)
2032#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL)
2033#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL)
2034#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL)
2035#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL)
2036#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL)
2037#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL)
2038#define ETH_MAC_BASE (ETH_BASE)
2039
2040/*!< USB registers base address */
2041#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL)
2042#define USB2_OTG_FS_PERIPH_BASE (0x40080000UL)
2043#define USB_OTG_GLOBAL_BASE (0x000UL)
2044#define USB_OTG_DEVICE_BASE (0x800UL)
2045#define USB_OTG_IN_ENDPOINT_BASE (0x900UL)
2046#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL)
2047#define USB_OTG_EP_REG_SIZE (0x20UL)
2048#define USB_OTG_HOST_BASE (0x400UL)
2049#define USB_OTG_HOST_PORT_BASE (0x440UL)
2050#define USB_OTG_HOST_CHANNEL_BASE (0x500UL)
2051#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL)
2052#define USB_OTG_PCGCCTL_BASE (0xE00UL)
2053#define USB_OTG_FIFO_BASE (0x1000UL)
2054#define USB_OTG_FIFO_SIZE (0x1000UL)
2055
2056/*!< D2_AHB2PERIPH peripherals */
2057
2058#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL)
2059#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL)
2060#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL)
2061#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL)
2062#define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL)
2063
2064/*!< D3_AHB1PERIPH peripherals */
2065#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL)
2066#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL)
2067#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL)
2068#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL)
2069#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL)
2070#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL)
2071#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL)
2072#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL)
2073#define GPIOI_BASE (D3_AHB1PERIPH_BASE + 0x2000UL)
2074#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL)
2075#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL)
2076#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL)
2077#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL)
2078#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL)
2079#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL)
2080#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL)
2081#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL)
2082#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL)
2083#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL)
2084#define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL)
2085
2086/*!< D1_APB1PERIPH peripherals */
2087#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL)
2088#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)
2089#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)
2090#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL)
2091
2092/*!< D2_APB1PERIPH peripherals */
2093#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL)
2094#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL)
2095#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL)
2096#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL)
2097#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL)
2098#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL)
2099#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL)
2100#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL)
2101#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL)
2102#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL)
2103
2104
2105#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL)
2106#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL)
2107#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL)
2108#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL)
2109#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL)
2110#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL)
2111#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL)
2112#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL)
2113#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL)
2114#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL)
2115#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL)
2116#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL)
2117#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL)
2118#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL)
2119#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL)
2120#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL)
2121#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
2122#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
2123#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL)
2124#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL)
2125#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL)
2126#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL)
2127#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL)
2128#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL)
2129
2130/*!< D2_APB2PERIPH peripherals */
2131
2132#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL)
2133#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL)
2134#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL)
2135#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL)
2136#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL)
2137#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL)
2138#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL)
2139#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL)
2140#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL)
2141#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL)
2142#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL)
2143#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
2144#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
2145#define SAI2_BASE (D2_APB2PERIPH_BASE + 0x5C00UL)
2146#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
2147#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
2148#define SAI3_BASE (D2_APB2PERIPH_BASE + 0x6000UL)
2149#define SAI3_Block_A_BASE (SAI3_BASE + 0x004UL)
2150#define SAI3_Block_B_BASE (SAI3_BASE + 0x024UL)
2151#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7000UL)
2152#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
2153#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
2154#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
2155#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
2156#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)
2157#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)
2158#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)
2159#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)
2160#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
2161#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
2162#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)
2163#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)
2164#define HRTIM1_BASE (D2_APB2PERIPH_BASE + 0x7400UL)
2165#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080UL)
2166#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100UL)
2167#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180UL)
2168#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200UL)
2169#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280UL)
2170#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380UL)
2171
2172
2173/*!< D3_APB1PERIPH peripherals */
2174#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL)
2175#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL)
2176#define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL)
2177#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL)
2178#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL)
2179#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL)
2180#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL)
2181#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL)
2182#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL)
2183#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL)
2184#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL)
2185#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL)
2186#define COMP1_BASE (COMP12_BASE + 0x0CUL)
2187#define COMP2_BASE (COMP12_BASE + 0x10UL)
2188#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL)
2189#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL)
2190#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL)
2191
2192
2193#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL)
2194#define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL)
2195#define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL)
2196
2197
2198
2199
2200#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL)
2201#define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL)
2202#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL)
2203#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL)
2204#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL)
2205#define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL)
2206#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL)
2207#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL)
2208
2209#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE)
2210#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL)
2211#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL)
2212#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL)
2213#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL)
2214#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL)
2215#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL)
2216#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL)
2217
2218#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL)
2219#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL)
2220#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL)
2221#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL)
2222#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL)
2223#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL)
2224#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL)
2225#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL)
2226
2227#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL)
2228#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL)
2229
2230#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
2231#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
2232#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
2233#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
2234#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
2235#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
2236#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
2237#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
2238
2239#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
2240#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
2241#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
2242#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
2243#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
2244#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
2245#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
2246#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
2247
2248#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
2249#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
2250#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
2251#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
2252#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
2253#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
2254#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
2255#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
2256#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
2257#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
2258#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
2259#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
2260#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
2261#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
2262#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
2263#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
2264
2265#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
2266#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
2267#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
2268#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
2269#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL)
2270#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL)
2271#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL)
2272#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL)
2273
2274#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
2275#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
2276
2277/*!< FMC Banks registers base address */
2278#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
2279#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
2280#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL)
2281#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
2282#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
2283
2284/* Debug MCU registers base address */
2285#define DBGMCU_BASE (0x5C001000UL)
2286
2287#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL)
2288#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL)
2289#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL)
2290#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL)
2291#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL)
2292#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL)
2293#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL)
2294#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL)
2295#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL)
2296#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL)
2297#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL)
2298#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL)
2299#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL)
2300#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
2301#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
2302#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
2303
2304#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)
2305#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)
2306#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)
2307#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)
2308#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)
2309
2310#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)
2311#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)
2312#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)
2313#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)
2314#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)
2315
2316#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)
2317#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
2318
2319
2320/**
2321 * @}
2322 */
2323
2324/** @addtogroup Peripheral_declaration
2325 * @{
2326 */
2327#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
2328#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
2329#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
2330#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
2331#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
2332#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
2333#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
2334#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
2335#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
2336#define RTC ((RTC_TypeDef *) RTC_BASE)
2337#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)
2338
2339
2340#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)
2341#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
2342#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
2343#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
2344#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
2345#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
2346#define USART2 ((USART_TypeDef *) USART2_BASE)
2347#define USART3 ((USART_TypeDef *) USART3_BASE)
2348#define USART6 ((USART_TypeDef *) USART6_BASE)
2349#define UART7 ((USART_TypeDef *) UART7_BASE)
2350#define UART8 ((USART_TypeDef *) UART8_BASE)
2351#define CRS ((CRS_TypeDef *) CRS_BASE)
2352#define UART4 ((USART_TypeDef *) UART4_BASE)
2353#define UART5 ((USART_TypeDef *) UART5_BASE)
2354#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
2355#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
2356#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
2357#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
2358#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
2359#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
2360#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
2361#define CEC ((CEC_TypeDef *) CEC_BASE)
2362#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
2363#define PWR ((PWR_TypeDef *) PWR_BASE)
2364#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
2365#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
2366#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
2367#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
2368#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)
2369#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)
2370#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)
2371
2372#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
2373#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)
2374#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
2375#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
2376#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
2377#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
2378#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
2379#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
2380
2381
2382#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
2383#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
2384#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
2385#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
2386#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
2387#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
2388#define USART1 ((USART_TypeDef *) USART1_BASE)
2389#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
2390#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
2391#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
2392#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
2393#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
2394#define HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)
2395#define HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)
2396#define HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)
2397#define HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)
2398#define HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)
2399#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
2400#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
2401#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
2402#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
2403#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
2404#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
2405#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
2406#define SAI3 ((SAI_TypeDef *) SAI3_BASE)
2407#define SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)
2408#define SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)
2409#define SAI4 ((SAI_TypeDef *) SAI4_BASE)
2410#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
2411#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
2412
2413#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
2414#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
2415#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
2416#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
2417#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
2418#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
2419#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
2420#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
2421#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
2422#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
2423#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
2424#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
2425#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
2426#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)
2427#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
2428#define RCC ((RCC_TypeDef *) RCC_BASE)
2429#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
2430#define CRC ((CRC_TypeDef *) CRC_BASE)
2431
2432#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
2433#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
2434#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
2435#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
2436#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
2437#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
2438#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
2439#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
2440#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
2441#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
2442#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
2443
2444#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
2445#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
2446#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
2447#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)
2448#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
2449
2450#define RNG ((RNG_TypeDef *) RNG_BASE)
2451#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
2452#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
2453
2454#define BDMA ((BDMA_TypeDef *) BDMA_BASE)
2455#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)
2456#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)
2457#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)
2458#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)
2459#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)
2460#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)
2461#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)
2462#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)
2463
2464#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)
2465#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)
2466#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)
2467#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)
2468#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)
2469#define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)
2470
2471#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)
2472#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)
2473#define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)
2474#define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)
2475#define RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)
2476#define RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)
2477
2478#define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)
2479#define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)
2480#define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)
2481
2482#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
2483#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
2484#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
2485#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
2486#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
2487#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
2488#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
2489#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
2490#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
2491
2492
2493#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
2494#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
2495#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
2496#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
2497#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
2498#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
2499#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
2500#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
2501
2502#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
2503#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
2504
2505#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
2506#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
2507#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
2508#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
2509#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
2510#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
2511#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
2512#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
2513#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
2514
2515#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
2516#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
2517#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
2518#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
2519#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
2520#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
2521#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
2522#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
2523#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
2524
2525
2526#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
2527#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
2528#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
2529#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
2530#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
2531#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
2532#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
2533#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
2534#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
2535#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
2536#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
2537#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
2538#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
2539#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
2540#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
2541#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
2542#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
2543
2544#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
2545#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
2546#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
2547#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
2548#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
2549#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
2550#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
2551#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
2552
2553#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
2554#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
2555
2556
2557#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
2558#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
2559#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
2560#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
2561#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
2562
2563
2564#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
2565#define DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)
2566#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
2567#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
2568
2569#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
2570
2571#define JPEG ((JPEG_TypeDef *) JPGDEC_BASE)
2572#define HSEM ((HSEM_TypeDef *) HSEM_BASE)
2573#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
2574
2575#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
2576#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
2577#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
2578
2579#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
2580
2581#define ETH ((ETH_TypeDef *)ETH_BASE)
2582#define MDMA ((MDMA_TypeDef *)MDMA_BASE)
2583#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
2584#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
2585#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
2586#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
2587#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
2588#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
2589#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
2590#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
2591#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
2592#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
2593#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
2594#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
2595#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
2596#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
2597#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
2598#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
2599
2600
2601#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
2602#define USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)
2603
2604/* Legacy defines */
2605#define USB_OTG_HS USB1_OTG_HS
2606#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
2607#define USB_OTG_FS USB2_OTG_FS
2608#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
2609
2610/**
2611 * @}
2612 */
2613
2614/** @addtogroup Exported_constants
2615 * @{
2616 */
2617
2618 /** @addtogroup Peripheral_Registers_Bits_Definition
2619 * @{
2620 */
2621
2622/******************************************************************************/
2623/* Peripheral Registers_Bits_Definition */
2624/******************************************************************************/
2625
2626/******************************************************************************/
2627/* */
2628/* Analog to Digital Converter */
2629/* */
2630/******************************************************************************/
2631/******************************* ADC VERSION ********************************/
2632#define ADC_VER_V5_X
2633/******************** Bit definition for ADC_ISR register ********************/
2634#define ADC_ISR_ADRDY_Pos (0U)
2635#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
2636#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */
2637#define ADC_ISR_EOSMP_Pos (1U)
2638#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
2639#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */
2640#define ADC_ISR_EOC_Pos (2U)
2641#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
2642#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */
2643#define ADC_ISR_EOS_Pos (3U)
2644#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
2645#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */
2646#define ADC_ISR_OVR_Pos (4U)
2647#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
2648#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */
2649#define ADC_ISR_JEOC_Pos (5U)
2650#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
2651#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */
2652#define ADC_ISR_JEOS_Pos (6U)
2653#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
2654#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */
2655#define ADC_ISR_AWD1_Pos (7U)
2656#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
2657#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */
2658#define ADC_ISR_AWD2_Pos (8U)
2659#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
2660#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */
2661#define ADC_ISR_AWD3_Pos (9U)
2662#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
2663#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */
2664#define ADC_ISR_JQOVF_Pos (10U)
2665#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
2666#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
2667
2668/******************** Bit definition for ADC_IER register ********************/
2669#define ADC_IER_ADRDYIE_Pos (0U)
2670#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
2671#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */
2672#define ADC_IER_EOSMPIE_Pos (1U)
2673#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
2674#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */
2675#define ADC_IER_EOCIE_Pos (2U)
2676#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
2677#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */
2678#define ADC_IER_EOSIE_Pos (3U)
2679#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
2680#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */
2681#define ADC_IER_OVRIE_Pos (4U)
2682#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
2683#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */
2684#define ADC_IER_JEOCIE_Pos (5U)
2685#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
2686#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */
2687#define ADC_IER_JEOSIE_Pos (6U)
2688#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
2689#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */
2690#define ADC_IER_AWD1IE_Pos (7U)
2691#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
2692#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */
2693#define ADC_IER_AWD2IE_Pos (8U)
2694#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
2695#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */
2696#define ADC_IER_AWD3IE_Pos (9U)
2697#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
2698#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */
2699#define ADC_IER_JQOVFIE_Pos (10U)
2700#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
2701#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */
2702
2703/******************** Bit definition for ADC_CR register ********************/
2704#define ADC_CR_ADEN_Pos (0U)
2705#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
2706#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */
2707#define ADC_CR_ADDIS_Pos (1U)
2708#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
2709#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */
2710#define ADC_CR_ADSTART_Pos (2U)
2711#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
2712#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */
2713#define ADC_CR_JADSTART_Pos (3U)
2714#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
2715#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */
2716#define ADC_CR_ADSTP_Pos (4U)
2717#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
2718#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */
2719#define ADC_CR_JADSTP_Pos (5U)
2720#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
2721#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */
2722#define ADC_CR_BOOST_Pos (8U)
2723#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */
2724#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */
2725#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */
2726#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */
2727#define ADC_CR_ADCALLIN_Pos (16U)
2728#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */
2729#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */
2730#define ADC_CR_LINCALRDYW1_Pos (22U)
2731#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */
2732#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */
2733#define ADC_CR_LINCALRDYW2_Pos (23U)
2734#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */
2735#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */
2736#define ADC_CR_LINCALRDYW3_Pos (24U)
2737#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */
2738#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */
2739#define ADC_CR_LINCALRDYW4_Pos (25U)
2740#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */
2741#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */
2742#define ADC_CR_LINCALRDYW5_Pos (26U)
2743#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */
2744#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */
2745#define ADC_CR_LINCALRDYW6_Pos (27U)
2746#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */
2747#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */
2748#define ADC_CR_ADVREGEN_Pos (28U)
2749#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
2750#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */
2751#define ADC_CR_DEEPPWD_Pos (29U)
2752#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
2753#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */
2754#define ADC_CR_ADCALDIF_Pos (30U)
2755#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
2756#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */
2757#define ADC_CR_ADCAL_Pos (31U)
2758#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
2759#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */
2760
2761/******************** Bit definition for ADC_CFGR register ********************/
2762#define ADC_CFGR_DMNGT_Pos (0U)
2763#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */
2764#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */
2765#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */
2766#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */
2767
2768#define ADC_CFGR_RES_Pos (2U)
2769#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */
2770#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */
2771#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */
2772#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
2773#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
2774
2775#define ADC_CFGR_EXTSEL_Pos (5U)
2776#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
2777#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */
2778#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
2779#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
2780#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
2781#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
2782#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
2783
2784#define ADC_CFGR_EXTEN_Pos (10U)
2785#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
2786#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */
2787#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
2788#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
2789
2790#define ADC_CFGR_OVRMOD_Pos (12U)
2791#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
2792#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */
2793#define ADC_CFGR_CONT_Pos (13U)
2794#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
2795#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */
2796#define ADC_CFGR_AUTDLY_Pos (14U)
2797#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
2798#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */
2799
2800#define ADC_CFGR_DISCEN_Pos (16U)
2801#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
2802#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */
2803
2804#define ADC_CFGR_DISCNUM_Pos (17U)
2805#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
2806#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
2807#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
2808#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
2809#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
2810
2811#define ADC_CFGR_JDISCEN_Pos (20U)
2812#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
2813#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
2814#define ADC_CFGR_JQM_Pos (21U)
2815#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
2816#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */
2817#define ADC_CFGR_AWD1SGL_Pos (22U)
2818#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
2819#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */
2820#define ADC_CFGR_AWD1EN_Pos (23U)
2821#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
2822#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */
2823#define ADC_CFGR_JAWD1EN_Pos (24U)
2824#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
2825#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */
2826#define ADC_CFGR_JAUTO_Pos (25U)
2827#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
2828#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */
2829
2830#define ADC_CFGR_AWD1CH_Pos (26U)
2831#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
2832#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */
2833#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
2834#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
2835#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
2836#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
2837#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
2838
2839#define ADC_CFGR_JQDIS_Pos (31U)
2840#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
2841#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */
2842
2843/******************** Bit definition for ADC_CFGR2 register ********************/
2844#define ADC_CFGR2_ROVSE_Pos (0U)
2845#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
2846#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */
2847#define ADC_CFGR2_JOVSE_Pos (1U)
2848#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
2849#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */
2850
2851#define ADC_CFGR2_OVSS_Pos (5U)
2852#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
2853#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */
2854#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
2855#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
2856#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
2857#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
2858
2859#define ADC_CFGR2_TROVS_Pos (9U)
2860#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
2861#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */
2862#define ADC_CFGR2_ROVSM_Pos (10U)
2863#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
2864#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */
2865
2866#define ADC_CFGR2_RSHIFT1_Pos (11U)
2867#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */
2868#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */
2869#define ADC_CFGR2_RSHIFT2_Pos (12U)
2870#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */
2871#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */
2872#define ADC_CFGR2_RSHIFT3_Pos (13U)
2873#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */
2874#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */
2875#define ADC_CFGR2_RSHIFT4_Pos (14U)
2876#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */
2877#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */
2878
2879#define ADC_CFGR2_OVSR_Pos (16U)
2880#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */
2881#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */
2882#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */
2883#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */
2884#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */
2885#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */
2886#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */
2887#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */
2888#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */
2889#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */
2890#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */
2891#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */
2892
2893#define ADC_CFGR2_LSHIFT_Pos (28U)
2894#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */
2895#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */
2896#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */
2897#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */
2898#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */
2899#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */
2900
2901/******************** Bit definition for ADC_SMPR1 register ********************/
2902#define ADC_SMPR1_SMP0_Pos (0U)
2903#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
2904#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */
2905#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
2906#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
2907#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
2908
2909#define ADC_SMPR1_SMP1_Pos (3U)
2910#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
2911#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */
2912#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
2913#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
2914#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
2915
2916#define ADC_SMPR1_SMP2_Pos (6U)
2917#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
2918#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */
2919#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
2920#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
2921#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
2922
2923#define ADC_SMPR1_SMP3_Pos (9U)
2924#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
2925#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */
2926#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
2927#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
2928#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
2929
2930#define ADC_SMPR1_SMP4_Pos (12U)
2931#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
2932#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */
2933#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
2934#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
2935#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
2936
2937#define ADC_SMPR1_SMP5_Pos (15U)
2938#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
2939#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */
2940#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
2941#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
2942#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
2943
2944#define ADC_SMPR1_SMP6_Pos (18U)
2945#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
2946#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */
2947#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
2948#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
2949#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
2950
2951#define ADC_SMPR1_SMP7_Pos (21U)
2952#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
2953#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */
2954#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
2955#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
2956#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
2957
2958#define ADC_SMPR1_SMP8_Pos (24U)
2959#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
2960#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */
2961#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
2962#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
2963#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
2964
2965#define ADC_SMPR1_SMP9_Pos (27U)
2966#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
2967#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */
2968#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
2969#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
2970#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
2971
2972/******************** Bit definition for ADC_SMPR2 register ********************/
2973#define ADC_SMPR2_SMP10_Pos (0U)
2974#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
2975#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */
2976#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
2977#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
2978#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
2979
2980#define ADC_SMPR2_SMP11_Pos (3U)
2981#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
2982#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */
2983#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
2984#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
2985#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
2986
2987#define ADC_SMPR2_SMP12_Pos (6U)
2988#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
2989#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */
2990#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
2991#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
2992#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
2993
2994#define ADC_SMPR2_SMP13_Pos (9U)
2995#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
2996#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */
2997#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
2998#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
2999#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
3000
3001#define ADC_SMPR2_SMP14_Pos (12U)
3002#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
3003#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */
3004#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
3005#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
3006#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
3007
3008#define ADC_SMPR2_SMP15_Pos (15U)
3009#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
3010#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */
3011#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
3012#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
3013#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
3014
3015#define ADC_SMPR2_SMP16_Pos (18U)
3016#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
3017#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */
3018#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
3019#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
3020#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
3021
3022#define ADC_SMPR2_SMP17_Pos (21U)
3023#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
3024#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */
3025#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
3026#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
3027#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
3028
3029#define ADC_SMPR2_SMP18_Pos (24U)
3030#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
3031#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */
3032#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
3033#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
3034#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
3035
3036#define ADC_SMPR2_SMP19_Pos (27U)
3037#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
3038#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */
3039#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
3040#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
3041#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
3042
3043/******************** Bit definition for ADC_PCSEL register ********************/
3044#define ADC_PCSEL_PCSEL_Pos (0U)
3045#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */
3046#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */
3047#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */
3048#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */
3049#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */
3050#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */
3051#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */
3052#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */
3053#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */
3054#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */
3055#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */
3056#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */
3057#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */
3058#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */
3059#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */
3060#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */
3061#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */
3062#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */
3063#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */
3064#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */
3065#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */
3066#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */
3067
3068/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/
3069#define ADC_LTR_LT_Pos (0U)
3070#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */
3071#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */
3072
3073/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/
3074#define ADC_HTR_HT_Pos (0U)
3075#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */
3076#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */
3077
3078
3079/******************** Bit definition for ADC_SQR1 register ********************/
3080#define ADC_SQR1_L_Pos (0U)
3081#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
3082#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
3083#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
3084#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
3085#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
3086#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
3087
3088#define ADC_SQR1_SQ1_Pos (6U)
3089#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
3090#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */
3091#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
3092#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
3093#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
3094#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
3095#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
3096
3097#define ADC_SQR1_SQ2_Pos (12U)
3098#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
3099#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */
3100#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
3101#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
3102#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
3103#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
3104#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
3105
3106#define ADC_SQR1_SQ3_Pos (18U)
3107#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
3108#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */
3109#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
3110#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
3111#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
3112#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
3113#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
3114
3115#define ADC_SQR1_SQ4_Pos (24U)
3116#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
3117#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */
3118#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
3119#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
3120#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
3121#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
3122#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
3123
3124/******************** Bit definition for ADC_SQR2 register ********************/
3125#define ADC_SQR2_SQ5_Pos (0U)
3126#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
3127#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */
3128#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
3129#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
3130#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
3131#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
3132#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
3133
3134#define ADC_SQR2_SQ6_Pos (6U)
3135#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
3136#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */
3137#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
3138#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
3139#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
3140#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
3141#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
3142
3143#define ADC_SQR2_SQ7_Pos (12U)
3144#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
3145#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */
3146#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
3147#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
3148#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
3149#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
3150#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
3151
3152#define ADC_SQR2_SQ8_Pos (18U)
3153#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
3154#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */
3155#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
3156#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
3157#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
3158#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
3159#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
3160
3161#define ADC_SQR2_SQ9_Pos (24U)
3162#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
3163#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */
3164#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
3165#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
3166#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
3167#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
3168#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
3169
3170/******************** Bit definition for ADC_SQR3 register ********************/
3171#define ADC_SQR3_SQ10_Pos (0U)
3172#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
3173#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */
3174#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
3175#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
3176#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
3177#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
3178#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
3179
3180#define ADC_SQR3_SQ11_Pos (6U)
3181#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
3182#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */
3183#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
3184#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
3185#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
3186#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
3187#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
3188
3189#define ADC_SQR3_SQ12_Pos (12U)
3190#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
3191#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */
3192#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
3193#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
3194#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
3195#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
3196#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
3197
3198#define ADC_SQR3_SQ13_Pos (18U)
3199#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
3200#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */
3201#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
3202#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
3203#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
3204#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
3205#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
3206
3207#define ADC_SQR3_SQ14_Pos (24U)
3208#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
3209#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */
3210#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
3211#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
3212#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
3213#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
3214#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
3215
3216/******************** Bit definition for ADC_SQR4 register ********************/
3217#define ADC_SQR4_SQ15_Pos (0U)
3218#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
3219#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */
3220#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
3221#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
3222#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
3223#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
3224#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
3225
3226#define ADC_SQR4_SQ16_Pos (6U)
3227#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
3228#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */
3229#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
3230#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
3231#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
3232#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
3233#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
3234/******************** Bit definition for ADC_DR register ********************/
3235#define ADC_DR_RDATA_Pos (0U)
3236#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */
3237#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */
3238
3239/******************** Bit definition for ADC_JSQR register ********************/
3240#define ADC_JSQR_JL_Pos (0U)
3241#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
3242#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */
3243#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
3244#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
3245
3246#define ADC_JSQR_JEXTSEL_Pos (2U)
3247#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
3248#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */
3249#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
3250#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
3251#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
3252#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
3253#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
3254
3255#define ADC_JSQR_JEXTEN_Pos (7U)
3256#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
3257#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */
3258#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
3259#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
3260
3261#define ADC_JSQR_JSQ1_Pos (9U)
3262#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
3263#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */
3264#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
3265#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
3266#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
3267#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
3268#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
3269
3270#define ADC_JSQR_JSQ2_Pos (15U)
3271#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */
3272#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */
3273#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
3274#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
3275#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
3276#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
3277#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */
3278
3279#define ADC_JSQR_JSQ3_Pos (21U)
3280#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
3281#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */
3282#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
3283#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
3284#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
3285#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
3286#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
3287
3288#define ADC_JSQR_JSQ4_Pos (27U)
3289#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
3290#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */
3291#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
3292#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
3293#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
3294#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
3295#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
3296
3297/******************** Bit definition for ADC_OFR1 register ********************/
3298#define ADC_OFR1_OFFSET1_Pos (0U)
3299#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
3300#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
3301#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
3302#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
3303#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
3304#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
3305#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
3306#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
3307#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
3308#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
3309#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
3310#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
3311#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
3312#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
3313#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
3314#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
3315#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
3316#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
3317#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
3318#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
3319#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
3320#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
3321#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
3322#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
3323#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
3324#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
3325#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
3326#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
3327
3328#define ADC_OFR1_OFFSET1_CH_Pos (26U)
3329#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
3330#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */
3331#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
3332#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
3333#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
3334#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
3335#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
3336
3337#define ADC_OFR1_SSATE_Pos (31U)
3338#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */
3339#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */
3340
3341
3342/******************** Bit definition for ADC_OFR2 register ********************/
3343#define ADC_OFR2_OFFSET2_Pos (0U)
3344#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
3345#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
3346#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
3347#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
3348#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
3349#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
3350#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
3351#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
3352#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
3353#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
3354#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
3355#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
3356#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
3357#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
3358#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
3359#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
3360#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
3361#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
3362#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
3363#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
3364#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
3365#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
3366#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
3367#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
3368#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
3369#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
3370#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
3371#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
3372
3373#define ADC_OFR2_OFFSET2_CH_Pos (26U)
3374#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
3375#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */
3376#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
3377#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
3378#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
3379#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
3380#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
3381
3382#define ADC_OFR2_SSATE_Pos (31U)
3383#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */
3384#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */
3385
3386
3387/******************** Bit definition for ADC_OFR3 register ********************/
3388#define ADC_OFR3_OFFSET3_Pos (0U)
3389#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
3390#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
3391#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
3392#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
3393#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
3394#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
3395#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
3396#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
3397#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
3398#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
3399#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
3400#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
3401#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
3402#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
3403#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
3404#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
3405#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
3406#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
3407#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
3408#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
3409#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
3410#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
3411#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
3412#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
3413#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
3414#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
3415#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
3416#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
3417
3418#define ADC_OFR3_OFFSET3_CH_Pos (26U)
3419#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
3420#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */
3421#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
3422#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
3423#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
3424#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
3425#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
3426
3427#define ADC_OFR3_SSATE_Pos (31U)
3428#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */
3429#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */
3430
3431
3432/******************** Bit definition for ADC_OFR4 register ********************/
3433#define ADC_OFR4_OFFSET4_Pos (0U)
3434#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
3435#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
3436#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
3437#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
3438#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
3439#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
3440#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
3441#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
3442#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
3443#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
3444#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
3445#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
3446#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
3447#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
3448#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
3449#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
3450#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
3451#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
3452#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
3453#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
3454#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
3455#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
3456#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
3457#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
3458#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
3459#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
3460#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
3461#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
3462
3463#define ADC_OFR4_OFFSET4_CH_Pos (26U)
3464#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
3465#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */
3466#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
3467#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
3468#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
3469#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
3470#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
3471
3472#define ADC_OFR4_SSATE_Pos (31U)
3473#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */
3474#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */
3475
3476
3477/******************** Bit definition for ADC_JDR1 register ********************/
3478#define ADC_JDR1_JDATA_Pos (0U)
3479#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */
3480#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */
3481#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
3482#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
3483#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
3484#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
3485#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
3486#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
3487#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
3488#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
3489#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
3490#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
3491#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
3492#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
3493#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
3494#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
3495#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
3496#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
3497#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */
3498#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */
3499#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */
3500#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */
3501#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */
3502#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */
3503#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */
3504#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */
3505#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */
3506#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */
3507#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */
3508#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */
3509#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */
3510#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */
3511#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */
3512#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */
3513
3514/******************** Bit definition for ADC_JDR2 register ********************/
3515#define ADC_JDR2_JDATA_Pos (0U)
3516#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */
3517#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */
3518#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
3519#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
3520#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
3521#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
3522#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
3523#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
3524#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
3525#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
3526#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
3527#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
3528#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
3529#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
3530#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
3531#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
3532#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
3533#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
3534#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */
3535#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */
3536#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */
3537#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */
3538#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */
3539#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */
3540#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */
3541#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */
3542#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */
3543#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */
3544#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */
3545#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */
3546#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */
3547#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */
3548#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */
3549#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */
3550
3551/******************** Bit definition for ADC_JDR3 register ********************/
3552#define ADC_JDR3_JDATA_Pos (0U)
3553#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */
3554#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */
3555#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
3556#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
3557#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
3558#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
3559#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
3560#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
3561#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
3562#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
3563#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
3564#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
3565#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
3566#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
3567#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
3568#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
3569#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
3570#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
3571#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */
3572#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */
3573#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */
3574#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */
3575#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */
3576#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */
3577#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */
3578#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */
3579#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */
3580#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */
3581#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */
3582#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */
3583#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */
3584#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */
3585#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */
3586#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */
3587
3588/******************** Bit definition for ADC_JDR4 register ********************/
3589#define ADC_JDR4_JDATA_Pos (0U)
3590#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */
3591#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */
3592#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
3593#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
3594#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
3595#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
3596#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
3597#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
3598#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
3599#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
3600#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
3601#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
3602#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
3603#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
3604#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
3605#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
3606#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
3607#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
3608#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */
3609#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */
3610#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */
3611#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */
3612#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */
3613#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */
3614#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */
3615#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */
3616#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */
3617#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */
3618#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */
3619#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */
3620#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */
3621#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */
3622#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */
3623#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */
3624
3625/******************** Bit definition for ADC_AWD2CR register ********************/
3626#define ADC_AWD2CR_AWD2CH_Pos (0U)
3627#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */
3628#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
3629#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
3630#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
3631#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
3632#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
3633#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
3634#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
3635#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
3636#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
3637#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
3638#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
3639#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
3640#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
3641#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
3642#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
3643#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
3644#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
3645#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
3646#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
3647#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
3648#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
3649
3650/******************** Bit definition for ADC_AWD3CR register ********************/
3651#define ADC_AWD3CR_AWD3CH_Pos (0U)
3652#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
3653#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */
3654#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
3655#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
3656#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
3657#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
3658#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
3659#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
3660#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
3661#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
3662#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
3663#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
3664#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
3665#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
3666#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
3667#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
3668#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
3669#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
3670#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
3671#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
3672#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
3673#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
3674
3675/******************** Bit definition for ADC_DIFSEL register ********************/
3676#define ADC_DIFSEL_DIFSEL_Pos (0U)
3677#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
3678#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */
3679#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
3680#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
3681#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
3682#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
3683#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
3684#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
3685#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
3686#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
3687#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
3688#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
3689#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
3690#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
3691#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
3692#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
3693#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
3694#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
3695#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
3696#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
3697#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
3698#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */
3699
3700/******************** Bit definition for ADC_CALFACT register ********************/
3701#define ADC_CALFACT_CALFACT_S_Pos (0U)
3702#define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
3703#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */
3704#define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
3705#define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
3706#define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
3707#define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
3708#define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
3709#define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
3710#define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
3711#define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
3712#define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
3713#define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
3714#define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
3715#define ADC_CALFACT_CALFACT_D_Pos (16U)
3716#define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
3717#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */
3718#define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
3719#define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
3720#define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
3721#define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
3722#define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
3723#define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
3724#define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
3725#define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
3726#define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
3727#define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
3728#define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
3729
3730/******************** Bit definition for ADC_CALFACT2 register ********************/
3731#define ADC_CALFACT2_LINCALFACT_Pos (0U)
3732#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
3733#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */
3734#define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
3735#define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
3736#define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
3737#define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
3738#define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
3739#define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
3740#define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
3741#define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
3742#define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
3743#define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
3744#define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
3745#define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
3746#define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
3747#define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
3748#define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
3749#define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
3750#define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
3751#define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
3752#define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
3753#define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
3754#define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
3755#define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
3756#define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
3757#define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
3758#define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
3759#define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
3760#define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
3761#define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */
3762#define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
3763#define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
3764
3765/************************* ADC Common registers *****************************/
3766/******************** Bit definition for ADC_CSR register ********************/
3767#define ADC_CSR_ADRDY_MST_Pos (0U)
3768#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
3769#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
3770#define ADC_CSR_EOSMP_MST_Pos (1U)
3771#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
3772#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
3773#define ADC_CSR_EOC_MST_Pos (2U)
3774#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
3775#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
3776#define ADC_CSR_EOS_MST_Pos (3U)
3777#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
3778#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
3779#define ADC_CSR_OVR_MST_Pos (4U)
3780#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
3781#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */
3782#define ADC_CSR_JEOC_MST_Pos (5U)
3783#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
3784#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
3785#define ADC_CSR_JEOS_MST_Pos (6U)
3786#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
3787#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
3788#define ADC_CSR_AWD1_MST_Pos (7U)
3789#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
3790#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
3791#define ADC_CSR_AWD2_MST_Pos (8U)
3792#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
3793#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
3794#define ADC_CSR_AWD3_MST_Pos (9U)
3795#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
3796#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
3797#define ADC_CSR_JQOVF_MST_Pos (10U)
3798#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
3799#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
3800#define ADC_CSR_ADRDY_SLV_Pos (16U)
3801#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
3802#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
3803#define ADC_CSR_EOSMP_SLV_Pos (17U)
3804#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
3805#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
3806#define ADC_CSR_EOC_SLV_Pos (18U)
3807#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
3808#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
3809#define ADC_CSR_EOS_SLV_Pos (19U)
3810#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
3811#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
3812#define ADC_CSR_OVR_SLV_Pos (20U)
3813#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
3814#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
3815#define ADC_CSR_JEOC_SLV_Pos (21U)
3816#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
3817#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */
3818#define ADC_CSR_JEOS_SLV_Pos (22U)
3819#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
3820#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */
3821#define ADC_CSR_AWD1_SLV_Pos (23U)
3822#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
3823#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */
3824#define ADC_CSR_AWD2_SLV_Pos (24U)
3825#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
3826#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */
3827#define ADC_CSR_AWD3_SLV_Pos (25U)
3828#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
3829#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */
3830#define ADC_CSR_JQOVF_SLV_Pos (26U)
3831#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
3832#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */
3833
3834/******************** Bit definition for ADC_CCR register ********************/
3835#define ADC_CCR_DUAL_Pos (0U)
3836#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
3837#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */
3838#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
3839#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
3840#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
3841#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
3842#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
3843
3844#define ADC_CCR_DELAY_Pos (8U)
3845#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
3846#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */
3847#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
3848#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
3849#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
3850#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
3851
3852
3853#define ADC_CCR_DAMDF_Pos (14U)
3854#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */
3855#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */
3856#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */
3857#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */
3858
3859#define ADC_CCR_CKMODE_Pos (16U)
3860#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
3861#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */
3862#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
3863#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
3864
3865#define ADC_CCR_PRESC_Pos (18U)
3866#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
3867#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */
3868#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
3869#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
3870#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
3871#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
3872
3873#define ADC_CCR_VREFEN_Pos (22U)
3874#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
3875#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */
3876#define ADC_CCR_TSEN_Pos (23U)
3877#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
3878#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */
3879#define ADC_CCR_VBATEN_Pos (24U)
3880#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
3881#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */
3882
3883/******************** Bit definition for ADC_CDR register *******************/
3884#define ADC_CDR_RDATA_MST_Pos (0U)
3885#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
3886#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
3887
3888#define ADC_CDR_RDATA_SLV_Pos (16U)
3889#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
3890#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
3891
3892/******************** Bit definition for ADC_CDR2 register ******************/
3893#define ADC_CDR2_RDATA_ALT_Pos (0U)
3894#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
3895#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */
3896
3897
3898/******************************************************************************/
3899/* */
3900/* VREFBUF */
3901/* */
3902/******************************************************************************/
3903/******************* Bit definition for VREFBUF_CSR register ****************/
3904#define VREFBUF_CSR_ENVR_Pos (0U)
3905#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
3906#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
3907#define VREFBUF_CSR_HIZ_Pos (1U)
3908#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
3909#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
3910#define VREFBUF_CSR_VRR_Pos (3U)
3911#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
3912#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
3913#define VREFBUF_CSR_VRS_Pos (4U)
3914#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
3915#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
3916
3917#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
3918#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
3919#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
3920#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
3921#define VREFBUF_CSR_VRS_OUT3_Pos (5U)
3922#define VREFBUF_CSR_VRS_OUT3_Msk (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos) /*!< 0x00000020 */
3923#define VREFBUF_CSR_VRS_OUT3 VREFBUF_CSR_VRS_OUT3_Msk /*!<Voltage reference VREF_OUT3 */
3924#define VREFBUF_CSR_VRS_OUT4_Pos (4U)
3925#define VREFBUF_CSR_VRS_OUT4_Msk (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos) /*!< 0x00000030 */
3926#define VREFBUF_CSR_VRS_OUT4 VREFBUF_CSR_VRS_OUT4_Msk /*!<Voltage reference VREF_OUT4 */
3927
3928/******************* Bit definition for VREFBUF_CCR register ****************/
3929#define VREFBUF_CCR_TRIM_Pos (0U)
3930#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
3931#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
3932
3933/******************************************************************************/
3934/* */
3935/* Flexible Datarate Controller Area Network */
3936/* */
3937/******************************************************************************/
3938/*!<FDCAN control and status registers */
3939/***************** Bit definition for FDCAN_CREL register *******************/
3940#define FDCAN_CREL_DAY_Pos (0U)
3941#define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */
3942#define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */
3943#define FDCAN_CREL_MON_Pos (8U)
3944#define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */
3945#define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */
3946#define FDCAN_CREL_YEAR_Pos (16U)
3947#define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */
3948#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */
3949#define FDCAN_CREL_SUBSTEP_Pos (20U)
3950#define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
3951#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
3952#define FDCAN_CREL_STEP_Pos (24U)
3953#define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */
3954#define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */
3955#define FDCAN_CREL_REL_Pos (28U)
3956#define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */
3957#define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */
3958
3959/***************** Bit definition for FDCAN_ENDN register *******************/
3960#define FDCAN_ENDN_ETV_Pos (0U)
3961#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
3962#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
3963
3964/***************** Bit definition for FDCAN_DBTP register *******************/
3965#define FDCAN_DBTP_DSJW_Pos (0U)
3966#define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */
3967#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */
3968#define FDCAN_DBTP_DTSEG2_Pos (4U)
3969#define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */
3970#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */
3971#define FDCAN_DBTP_DTSEG1_Pos (8U)
3972#define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */
3973#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */
3974#define FDCAN_DBTP_DBRP_Pos (16U)
3975#define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */
3976#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */
3977#define FDCAN_DBTP_TDC_Pos (23U)
3978#define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */
3979#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */
3980
3981/***************** Bit definition for FDCAN_TEST register *******************/
3982#define FDCAN_TEST_LBCK_Pos (4U)
3983#define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */
3984#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */
3985#define FDCAN_TEST_TX_Pos (5U)
3986#define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */
3987#define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */
3988#define FDCAN_TEST_RX_Pos (7U)
3989#define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */
3990#define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */
3991
3992/***************** Bit definition for FDCAN_RWD register ********************/
3993#define FDCAN_RWD_WDC_Pos (0U)
3994#define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */
3995#define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */
3996#define FDCAN_RWD_WDV_Pos (8U)
3997#define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */
3998#define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */
3999
4000/***************** Bit definition for FDCAN_CCCR register ********************/
4001#define FDCAN_CCCR_INIT_Pos (0U)
4002#define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
4003#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */
4004#define FDCAN_CCCR_CCE_Pos (1U)
4005#define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */
4006#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */
4007#define FDCAN_CCCR_ASM_Pos (2U)
4008#define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */
4009#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */
4010#define FDCAN_CCCR_CSA_Pos (3U)
4011#define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */
4012#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */
4013#define FDCAN_CCCR_CSR_Pos (4U)
4014#define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */
4015#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */
4016#define FDCAN_CCCR_MON_Pos (5U)
4017#define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */
4018#define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */
4019#define FDCAN_CCCR_DAR_Pos (6U)
4020#define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */
4021#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */
4022#define FDCAN_CCCR_TEST_Pos (7U)
4023#define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */
4024#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */
4025#define FDCAN_CCCR_FDOE_Pos (8U)
4026#define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */
4027#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */
4028#define FDCAN_CCCR_BRSE_Pos (9U)
4029#define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */
4030#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */
4031#define FDCAN_CCCR_PXHD_Pos (12U)
4032#define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */
4033#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */
4034#define FDCAN_CCCR_EFBI_Pos (13U)
4035#define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */
4036#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */
4037#define FDCAN_CCCR_TXP_Pos (14U)
4038#define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */
4039#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */
4040#define FDCAN_CCCR_NISO_Pos (15U)
4041#define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */
4042#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */
4043
4044/***************** Bit definition for FDCAN_NBTP register ********************/
4045#define FDCAN_NBTP_NTSEG2_Pos (0U)
4046#define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */
4047#define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */
4048#define FDCAN_NBTP_NTSEG1_Pos (8U)
4049#define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */
4050#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */
4051#define FDCAN_NBTP_NBRP_Pos (16U)
4052#define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */
4053#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */
4054#define FDCAN_NBTP_NSJW_Pos (25U)
4055#define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */
4056#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */
4057
4058/***************** Bit definition for FDCAN_TSCC register ********************/
4059#define FDCAN_TSCC_TSS_Pos (0U)
4060#define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */
4061#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */
4062#define FDCAN_TSCC_TCP_Pos (16U)
4063#define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */
4064#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */
4065
4066/***************** Bit definition for FDCAN_TSCV register ********************/
4067#define FDCAN_TSCV_TSC_Pos (0U)
4068#define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */
4069#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */
4070
4071/***************** Bit definition for FDCAN_TOCC register ********************/
4072#define FDCAN_TOCC_ETOC_Pos (0U)
4073#define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */
4074#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */
4075#define FDCAN_TOCC_TOS_Pos (1U)
4076#define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */
4077#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */
4078#define FDCAN_TOCC_TOP_Pos (16U)
4079#define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */
4080#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */
4081
4082/***************** Bit definition for FDCAN_TOCV register ********************/
4083#define FDCAN_TOCV_TOC_Pos (0U)
4084#define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */
4085#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */
4086
4087/***************** Bit definition for FDCAN_ECR register *********************/
4088#define FDCAN_ECR_TEC_Pos (0U)
4089#define FDCAN_ECR_TEC_Msk (0xFUL << FDCAN_ECR_TEC_Pos) /*!< 0x0000000F */
4090#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
4091#define FDCAN_ECR_REC_Pos (8U)
4092#define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */
4093#define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */
4094#define FDCAN_ECR_RP_Pos (15U)
4095#define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */
4096#define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */
4097#define FDCAN_ECR_CEL_Pos (16U)
4098#define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */
4099#define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */
4100
4101/***************** Bit definition for FDCAN_PSR register *********************/
4102#define FDCAN_PSR_LEC_Pos (0U)
4103#define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */
4104#define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */
4105#define FDCAN_PSR_ACT_Pos (3U)
4106#define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */
4107#define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */
4108#define FDCAN_PSR_EP_Pos (5U)
4109#define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */
4110#define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */
4111#define FDCAN_PSR_EW_Pos (6U)
4112#define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */
4113#define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */
4114#define FDCAN_PSR_BO_Pos (7U)
4115#define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */
4116#define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */
4117#define FDCAN_PSR_DLEC_Pos (8U)
4118#define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */
4119#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */
4120#define FDCAN_PSR_RESI_Pos (11U)
4121#define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */
4122#define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */
4123#define FDCAN_PSR_RBRS_Pos (12U)
4124#define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */
4125#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */
4126#define FDCAN_PSR_REDL_Pos (13U)
4127#define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */
4128#define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */
4129#define FDCAN_PSR_PXE_Pos (14U)
4130#define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */
4131#define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */
4132#define FDCAN_PSR_TDCV_Pos (16U)
4133#define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */
4134#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */
4135
4136/***************** Bit definition for FDCAN_TDCR register ********************/
4137#define FDCAN_TDCR_TDCF_Pos (0U)
4138#define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */
4139#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */
4140#define FDCAN_TDCR_TDCO_Pos (8U)
4141#define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */
4142#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */
4143
4144/***************** Bit definition for FDCAN_IR register **********************/
4145#define FDCAN_IR_RF0N_Pos (0U)
4146#define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */
4147#define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */
4148#define FDCAN_IR_RF0W_Pos (1U)
4149#define FDCAN_IR_RF0W_Msk (0x1UL << FDCAN_IR_RF0W_Pos) /*!< 0x00000002 */
4150#define FDCAN_IR_RF0W FDCAN_IR_RF0W_Msk /*!<Rx FIFO 0 Watermark Reached */
4151#define FDCAN_IR_RF0F_Pos (2U)
4152#define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) /*!< 0x00000004 */
4153#define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */
4154#define FDCAN_IR_RF0L_Pos (3U)
4155#define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) /*!< 0x00000008 */
4156#define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
4157#define FDCAN_IR_RF1N_Pos (4U)
4158#define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) /*!< 0x00000010 */
4159#define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */
4160#define FDCAN_IR_RF1W_Pos (5U)
4161#define FDCAN_IR_RF1W_Msk (0x1UL << FDCAN_IR_RF1W_Pos) /*!< 0x00000020 */
4162#define FDCAN_IR_RF1W FDCAN_IR_RF1W_Msk /*!<Rx FIFO 1 Watermark Reached */
4163#define FDCAN_IR_RF1F_Pos (6U)
4164#define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) /*!< 0x00000040 */
4165#define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */
4166#define FDCAN_IR_RF1L_Pos (7U)
4167#define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) /*!< 0x00000080 */
4168#define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
4169#define FDCAN_IR_HPM_Pos (8U)
4170#define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) /*!< 0x00000100 */
4171#define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */
4172#define FDCAN_IR_TC_Pos (9U)
4173#define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) /*!< 0x00000200 */
4174#define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */
4175#define FDCAN_IR_TCF_Pos (10U)
4176#define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) /*!< 0x00000400 */
4177#define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */
4178#define FDCAN_IR_TFE_Pos (11U)
4179#define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) /*!< 0x00000800 */
4180#define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */
4181#define FDCAN_IR_TEFN_Pos (12U)
4182#define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) /*!< 0x00001000 */
4183#define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */
4184#define FDCAN_IR_TEFW_Pos (13U)
4185#define FDCAN_IR_TEFW_Msk (0x1UL << FDCAN_IR_TEFW_Pos) /*!< 0x00002000 */
4186#define FDCAN_IR_TEFW FDCAN_IR_TEFW_Msk /*!<Tx Event FIFO Watermark Reached */
4187#define FDCAN_IR_TEFF_Pos (14U)
4188#define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) /*!< 0x00004000 */
4189#define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */
4190#define FDCAN_IR_TEFL_Pos (15U)
4191#define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) /*!< 0x00008000 */
4192#define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */
4193#define FDCAN_IR_TSW_Pos (16U)
4194#define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) /*!< 0x00010000 */
4195#define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */
4196#define FDCAN_IR_MRAF_Pos (17U)
4197#define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) /*!< 0x00020000 */
4198#define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */
4199#define FDCAN_IR_TOO_Pos (18U)
4200#define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) /*!< 0x00040000 */
4201#define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */
4202#define FDCAN_IR_DRX_Pos (19U)
4203#define FDCAN_IR_DRX_Msk (0x1UL << FDCAN_IR_DRX_Pos) /*!< 0x00080000 */
4204#define FDCAN_IR_DRX FDCAN_IR_DRX_Msk /*!<Message stored to Dedicated Rx Buffer */
4205#define FDCAN_IR_ELO_Pos (22U)
4206#define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) /*!< 0x00400000 */
4207#define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */
4208#define FDCAN_IR_EP_Pos (23U)
4209#define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) /*!< 0x00800000 */
4210#define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */
4211#define FDCAN_IR_EW_Pos (24U)
4212#define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) /*!< 0x01000000 */
4213#define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */
4214#define FDCAN_IR_BO_Pos (25U)
4215#define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) /*!< 0x02000000 */
4216#define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */
4217#define FDCAN_IR_WDI_Pos (26U)
4218#define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) /*!< 0x04000000 */
4219#define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */
4220#define FDCAN_IR_PEA_Pos (27U)
4221#define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) /*!< 0x08000000 */
4222#define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */
4223#define FDCAN_IR_PED_Pos (28U)
4224#define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) /*!< 0x10000000 */
4225#define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */
4226#define FDCAN_IR_ARA_Pos (29U)
4227#define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) /*!< 0x20000000 */
4228#define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */
4229
4230/***************** Bit definition for FDCAN_IE register **********************/
4231#define FDCAN_IE_RF0NE_Pos (0U)
4232#define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */
4233#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */
4234#define FDCAN_IE_RF0WE_Pos (1U)
4235#define FDCAN_IE_RF0WE_Msk (0x1UL << FDCAN_IE_RF0WE_Pos) /*!< 0x00000002 */
4236#define FDCAN_IE_RF0WE FDCAN_IE_RF0WE_Msk /*!<Rx FIFO 0 Watermark Reached Enable */
4237#define FDCAN_IE_RF0FE_Pos (2U)
4238#define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) /*!< 0x00000004 */
4239#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */
4240#define FDCAN_IE_RF0LE_Pos (3U)
4241#define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) /*!< 0x00000008 */
4242#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */
4243#define FDCAN_IE_RF1NE_Pos (4U)
4244#define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) /*!< 0x00000010 */
4245#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */
4246#define FDCAN_IE_RF1WE_Pos (5U)
4247#define FDCAN_IE_RF1WE_Msk (0x1UL << FDCAN_IE_RF1WE_Pos) /*!< 0x00000020 */
4248#define FDCAN_IE_RF1WE FDCAN_IE_RF1WE_Msk /*!<Rx FIFO 1 Watermark Reached Enable */
4249#define FDCAN_IE_RF1FE_Pos (6U)
4250#define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) /*!< 0x00000040 */
4251#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */
4252#define FDCAN_IE_RF1LE_Pos (7U)
4253#define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) /*!< 0x00000080 */
4254#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */
4255#define FDCAN_IE_HPME_Pos (8U)
4256#define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) /*!< 0x00000100 */
4257#define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */
4258#define FDCAN_IE_TCE_Pos (9U)
4259#define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) /*!< 0x00000200 */
4260#define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */
4261#define FDCAN_IE_TCFE_Pos (10U)
4262#define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) /*!< 0x00000400 */
4263#define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable */
4264#define FDCAN_IE_TFEE_Pos (11U)
4265#define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) /*!< 0x00000800 */
4266#define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */
4267#define FDCAN_IE_TEFNE_Pos (12U)
4268#define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) /*!< 0x00001000 */
4269#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */
4270#define FDCAN_IE_TEFWE_Pos (13U)
4271#define FDCAN_IE_TEFWE_Msk (0x1UL << FDCAN_IE_TEFWE_Pos) /*!< 0x00002000 */
4272#define FDCAN_IE_TEFWE FDCAN_IE_TEFWE_Msk /*!<Tx Event FIFO Watermark Reached Enable */
4273#define FDCAN_IE_TEFFE_Pos (14U)
4274#define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) /*!< 0x00004000 */
4275#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */
4276#define FDCAN_IE_TEFLE_Pos (15U)
4277#define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) /*!< 0x00008000 */
4278#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */
4279#define FDCAN_IE_TSWE_Pos (16U)
4280#define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) /*!< 0x00010000 */
4281#define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */
4282#define FDCAN_IE_MRAFE_Pos (17U)
4283#define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) /*!< 0x00020000 */
4284#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */
4285#define FDCAN_IE_TOOE_Pos (18U)
4286#define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) /*!< 0x00040000 */
4287#define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */
4288#define FDCAN_IE_DRXE_Pos (19U)
4289#define FDCAN_IE_DRXE_Msk (0x1UL << FDCAN_IE_DRXE_Pos) /*!< 0x00080000 */
4290#define FDCAN_IE_DRXE FDCAN_IE_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Enable */
4291#define FDCAN_IE_BECE_Pos (20U)
4292#define FDCAN_IE_BECE_Msk (0x1UL << FDCAN_IE_BECE_Pos) /*!< 0x00100000 */
4293#define FDCAN_IE_BECE FDCAN_IE_BECE_Msk /*!<Bit Error Corrected Interrupt Enable */
4294#define FDCAN_IE_BEUE_Pos (21U)
4295#define FDCAN_IE_BEUE_Msk (0x1UL << FDCAN_IE_BEUE_Pos) /*!< 0x00200000 */
4296#define FDCAN_IE_BEUE FDCAN_IE_BEUE_Msk /*!<Bit Error Uncorrected Interrupt Enable */
4297#define FDCAN_IE_ELOE_Pos (22U)
4298#define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) /*!< 0x00400000 */
4299#define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */
4300#define FDCAN_IE_EPE_Pos (23U)
4301#define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) /*!< 0x00800000 */
4302#define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */
4303#define FDCAN_IE_EWE_Pos (24U)
4304#define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) /*!< 0x01000000 */
4305#define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */
4306#define FDCAN_IE_BOE_Pos (25U)
4307#define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) /*!< 0x02000000 */
4308#define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */
4309#define FDCAN_IE_WDIE_Pos (26U)
4310#define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) /*!< 0x04000000 */
4311#define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */
4312#define FDCAN_IE_PEAE_Pos (27U)
4313#define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) /*!< 0x08000000 */
4314#define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable */
4315#define FDCAN_IE_PEDE_Pos (28U)
4316#define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) /*!< 0x10000000 */
4317#define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */
4318#define FDCAN_IE_ARAE_Pos (29U)
4319#define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) /*!< 0x20000000 */
4320#define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */
4321
4322/***************** Bit definition for FDCAN_ILS register **********************/
4323#define FDCAN_ILS_RF0NL_Pos (0U)
4324#define FDCAN_ILS_RF0NL_Msk (0x1UL << FDCAN_ILS_RF0NL_Pos) /*!< 0x00000001 */
4325#define FDCAN_ILS_RF0NL FDCAN_ILS_RF0NL_Msk /*!<Rx FIFO 0 New Message Line */
4326#define FDCAN_ILS_RF0WL_Pos (1U)
4327#define FDCAN_ILS_RF0WL_Msk (0x1UL << FDCAN_ILS_RF0WL_Pos) /*!< 0x00000002 */
4328#define FDCAN_ILS_RF0WL FDCAN_ILS_RF0WL_Msk /*!<Rx FIFO 0 Watermark Reached Line */
4329#define FDCAN_ILS_RF0FL_Pos (2U)
4330#define FDCAN_ILS_RF0FL_Msk (0x1UL << FDCAN_ILS_RF0FL_Pos) /*!< 0x00000004 */
4331#define FDCAN_ILS_RF0FL FDCAN_ILS_RF0FL_Msk /*!<Rx FIFO 0 Full Line */
4332#define FDCAN_ILS_RF0LL_Pos (3U)
4333#define FDCAN_ILS_RF0LL_Msk (0x1UL << FDCAN_ILS_RF0LL_Pos) /*!< 0x00000008 */
4334#define FDCAN_ILS_RF0LL FDCAN_ILS_RF0LL_Msk /*!<Rx FIFO 0 Message Lost Line */
4335#define FDCAN_ILS_RF1NL_Pos (4U)
4336#define FDCAN_ILS_RF1NL_Msk (0x1UL << FDCAN_ILS_RF1NL_Pos) /*!< 0x00000010 */
4337#define FDCAN_ILS_RF1NL FDCAN_ILS_RF1NL_Msk /*!<Rx FIFO 1 New Message Line */
4338#define FDCAN_ILS_RF1WL_Pos (5U)
4339#define FDCAN_ILS_RF1WL_Msk (0x1UL << FDCAN_ILS_RF1WL_Pos) /*!< 0x00000020 */
4340#define FDCAN_ILS_RF1WL FDCAN_ILS_RF1WL_Msk /*!<Rx FIFO 1 Watermark Reached Line */
4341#define FDCAN_ILS_RF1FL_Pos (6U)
4342#define FDCAN_ILS_RF1FL_Msk (0x1UL << FDCAN_ILS_RF1FL_Pos) /*!< 0x00000040 */
4343#define FDCAN_ILS_RF1FL FDCAN_ILS_RF1FL_Msk /*!<Rx FIFO 1 Full Line */
4344#define FDCAN_ILS_RF1LL_Pos (7U)
4345#define FDCAN_ILS_RF1LL_Msk (0x1UL << FDCAN_ILS_RF1LL_Pos) /*!< 0x00000080 */
4346#define FDCAN_ILS_RF1LL FDCAN_ILS_RF1LL_Msk /*!<Rx FIFO 1 Message Lost Line */
4347#define FDCAN_ILS_HPML_Pos (8U)
4348#define FDCAN_ILS_HPML_Msk (0x1UL << FDCAN_ILS_HPML_Pos) /*!< 0x00000100 */
4349#define FDCAN_ILS_HPML FDCAN_ILS_HPML_Msk /*!<High Priority Message Line */
4350#define FDCAN_ILS_TCL_Pos (9U)
4351#define FDCAN_ILS_TCL_Msk (0x1UL << FDCAN_ILS_TCL_Pos) /*!< 0x00000200 */
4352#define FDCAN_ILS_TCL FDCAN_ILS_TCL_Msk /*!<Transmission Completed Line */
4353#define FDCAN_ILS_TCFL_Pos (10U)
4354#define FDCAN_ILS_TCFL_Msk (0x1UL << FDCAN_ILS_TCFL_Pos) /*!< 0x00000400 */
4355#define FDCAN_ILS_TCFL FDCAN_ILS_TCFL_Msk /*!<Transmission Cancellation Finished Line */
4356#define FDCAN_ILS_TFEL_Pos (11U)
4357#define FDCAN_ILS_TFEL_Msk (0x1UL << FDCAN_ILS_TFEL_Pos) /*!< 0x00000800 */
4358#define FDCAN_ILS_TFEL FDCAN_ILS_TFEL_Msk /*!<Tx FIFO Empty Line */
4359#define FDCAN_ILS_TEFNL_Pos (12U)
4360#define FDCAN_ILS_TEFNL_Msk (0x1UL << FDCAN_ILS_TEFNL_Pos) /*!< 0x00001000 */
4361#define FDCAN_ILS_TEFNL FDCAN_ILS_TEFNL_Msk /*!<Tx Event FIFO New Entry Line */
4362#define FDCAN_ILS_TEFWL_Pos (13U)
4363#define FDCAN_ILS_TEFWL_Msk (0x1UL << FDCAN_ILS_TEFWL_Pos) /*!< 0x00002000 */
4364#define FDCAN_ILS_TEFWL FDCAN_ILS_TEFWL_Msk /*!<Tx Event FIFO Watermark Reached Line */
4365#define FDCAN_ILS_TEFFL_Pos (14U)
4366#define FDCAN_ILS_TEFFL_Msk (0x1UL << FDCAN_ILS_TEFFL_Pos) /*!< 0x00004000 */
4367#define FDCAN_ILS_TEFFL FDCAN_ILS_TEFFL_Msk /*!<Tx Event FIFO Full Line */
4368#define FDCAN_ILS_TEFLL_Pos (15U)
4369#define FDCAN_ILS_TEFLL_Msk (0x1UL << FDCAN_ILS_TEFLL_Pos) /*!< 0x00008000 */
4370#define FDCAN_ILS_TEFLL FDCAN_ILS_TEFLL_Msk /*!<Tx Event FIFO Element Lost Line */
4371#define FDCAN_ILS_TSWL_Pos (16U)
4372#define FDCAN_ILS_TSWL_Msk (0x1UL << FDCAN_ILS_TSWL_Pos) /*!< 0x00010000 */
4373#define FDCAN_ILS_TSWL FDCAN_ILS_TSWL_Msk /*!<Timestamp Wraparound Line */
4374#define FDCAN_ILS_MRAFE_Pos (17U)
4375#define FDCAN_ILS_MRAFE_Msk (0x1UL << FDCAN_ILS_MRAFE_Pos) /*!< 0x00020000 */
4376#define FDCAN_ILS_MRAFE FDCAN_ILS_MRAFE_Msk /*!<Message RAM Access Failure Line */
4377#define FDCAN_ILS_TOOE_Pos (18U)
4378#define FDCAN_ILS_TOOE_Msk (0x1UL << FDCAN_ILS_TOOE_Pos) /*!< 0x00040000 */
4379#define FDCAN_ILS_TOOE FDCAN_ILS_TOOE_Msk /*!<Timeout Occurred Line */
4380#define FDCAN_ILS_DRXE_Pos (19U)
4381#define FDCAN_ILS_DRXE_Msk (0x1UL << FDCAN_ILS_DRXE_Pos) /*!< 0x00080000 */
4382#define FDCAN_ILS_DRXE FDCAN_ILS_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Line */
4383#define FDCAN_ILS_BECE_Pos (20U)
4384#define FDCAN_ILS_BECE_Msk (0x1UL << FDCAN_ILS_BECE_Pos) /*!< 0x00100000 */
4385#define FDCAN_ILS_BECE FDCAN_ILS_BECE_Msk /*!<Bit Error Corrected Interrupt Line */
4386#define FDCAN_ILS_BEUE_Pos (21U)
4387#define FDCAN_ILS_BEUE_Msk (0x1UL << FDCAN_ILS_BEUE_Pos) /*!< 0x00200000 */
4388#define FDCAN_ILS_BEUE FDCAN_ILS_BEUE_Msk /*!<Bit Error Uncorrected Interrupt Line */
4389#define FDCAN_ILS_ELOE_Pos (22U)
4390#define FDCAN_ILS_ELOE_Msk (0x1UL << FDCAN_ILS_ELOE_Pos) /*!< 0x00400000 */
4391#define FDCAN_ILS_ELOE FDCAN_ILS_ELOE_Msk /*!<Error Logging Overflow Line */
4392#define FDCAN_ILS_EPE_Pos (23U)
4393#define FDCAN_ILS_EPE_Msk (0x1UL << FDCAN_ILS_EPE_Pos) /*!< 0x00800000 */
4394#define FDCAN_ILS_EPE FDCAN_ILS_EPE_Msk /*!<Error Passive Line */
4395#define FDCAN_ILS_EWE_Pos (24U)
4396#define FDCAN_ILS_EWE_Msk (0x1UL << FDCAN_ILS_EWE_Pos) /*!< 0x01000000 */
4397#define FDCAN_ILS_EWE FDCAN_ILS_EWE_Msk /*!<Warning Status Line */
4398#define FDCAN_ILS_BOE_Pos (25U)
4399#define FDCAN_ILS_BOE_Msk (0x1UL << FDCAN_ILS_BOE_Pos) /*!< 0x02000000 */
4400#define FDCAN_ILS_BOE FDCAN_ILS_BOE_Msk /*!<Bus_Off Status Line */
4401#define FDCAN_ILS_WDIE_Pos (26U)
4402#define FDCAN_ILS_WDIE_Msk (0x1UL << FDCAN_ILS_WDIE_Pos) /*!< 0x04000000 */
4403#define FDCAN_ILS_WDIE FDCAN_ILS_WDIE_Msk /*!<Watchdog Interrupt Line */
4404#define FDCAN_ILS_PEAE_Pos (27U)
4405#define FDCAN_ILS_PEAE_Msk (0x1UL << FDCAN_ILS_PEAE_Pos) /*!< 0x08000000 */
4406#define FDCAN_ILS_PEAE FDCAN_ILS_PEAE_Msk /*!<Protocol Error in Arbitration Phase Line */
4407#define FDCAN_ILS_PEDE_Pos (28U)
4408#define FDCAN_ILS_PEDE_Msk (0x1UL << FDCAN_ILS_PEDE_Pos) /*!< 0x10000000 */
4409#define FDCAN_ILS_PEDE FDCAN_ILS_PEDE_Msk /*!<Protocol Error in Data Phase Line */
4410#define FDCAN_ILS_ARAE_Pos (29U)
4411#define FDCAN_ILS_ARAE_Msk (0x1UL << FDCAN_ILS_ARAE_Pos) /*!< 0x20000000 */
4412#define FDCAN_ILS_ARAE FDCAN_ILS_ARAE_Msk /*!<Access to Reserved Address Line */
4413
4414/***************** Bit definition for FDCAN_ILE register **********************/
4415#define FDCAN_ILE_EINT0_Pos (0U)
4416#define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */
4417#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */
4418#define FDCAN_ILE_EINT1_Pos (1U)
4419#define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */
4420#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */
4421
4422/***************** Bit definition for FDCAN_GFC register **********************/
4423#define FDCAN_GFC_RRFE_Pos (0U)
4424#define FDCAN_GFC_RRFE_Msk (0x1UL << FDCAN_GFC_RRFE_Pos) /*!< 0x00000001 */
4425#define FDCAN_GFC_RRFE FDCAN_GFC_RRFE_Msk /*!<Reject Remote Frames Extended */
4426#define FDCAN_GFC_RRFS_Pos (1U)
4427#define FDCAN_GFC_RRFS_Msk (0x1UL << FDCAN_GFC_RRFS_Pos) /*!< 0x00000002 */
4428#define FDCAN_GFC_RRFS FDCAN_GFC_RRFS_Msk /*!<Reject Remote Frames Standard */
4429#define FDCAN_GFC_ANFE_Pos (2U)
4430#define FDCAN_GFC_ANFE_Msk (0x3UL << FDCAN_GFC_ANFE_Pos) /*!< 0x0000000C */
4431#define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */
4432#define FDCAN_GFC_ANFS_Pos (4U)
4433#define FDCAN_GFC_ANFS_Msk (0x3UL << FDCAN_GFC_ANFS_Pos) /*!< 0x00000030 */
4434#define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */
4435
4436/***************** Bit definition for FDCAN_SIDFC register ********************/
4437#define FDCAN_SIDFC_FLSSA_Pos (2U)
4438#define FDCAN_SIDFC_FLSSA_Msk (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos) /*!< 0x0000FFFC */
4439#define FDCAN_SIDFC_FLSSA FDCAN_SIDFC_FLSSA_Msk /*!<Filter List Standard Start Address */
4440#define FDCAN_SIDFC_LSS_Pos (16U)
4441#define FDCAN_SIDFC_LSS_Msk (0xFFUL << FDCAN_SIDFC_LSS_Pos) /*!< 0x00FF0000 */
4442#define FDCAN_SIDFC_LSS FDCAN_SIDFC_LSS_Msk /*!<List Size Standard */
4443
4444/***************** Bit definition for FDCAN_XIDFC register ********************/
4445#define FDCAN_XIDFC_FLESA_Pos (2U)
4446#define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
4447#define FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_Msk /*!<Filter List Standard Start Address */
4448#define FDCAN_XIDFC_LSE_Pos (16U)
4449#define FDCAN_XIDFC_LSE_Msk (0x7FUL << FDCAN_XIDFC_LSE_Pos) /*!< 0x007F0000 */
4450#define FDCAN_XIDFC_LSE FDCAN_XIDFC_LSE_Msk /*!<List Size Extended */
4451
4452/***************** Bit definition for FDCAN_XIDAM register ********************/
4453#define FDCAN_XIDAM_EIDM_Pos (0U)
4454#define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */
4455#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */
4456
4457/***************** Bit definition for FDCAN_HPMS register *********************/
4458#define FDCAN_HPMS_BIDX_Pos (0U)
4459#define FDCAN_HPMS_BIDX_Msk (0x3FUL << FDCAN_HPMS_BIDX_Pos) /*!< 0x0000003F */
4460#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */
4461#define FDCAN_HPMS_MSI_Pos (6U)
4462#define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */
4463#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */
4464#define FDCAN_HPMS_FIDX_Pos (8U)
4465#define FDCAN_HPMS_FIDX_Msk (0x7FUL << FDCAN_HPMS_FIDX_Pos) /*!< 0x00007F00 */
4466#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */
4467#define FDCAN_HPMS_FLST_Pos (15U)
4468#define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */
4469#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */
4470
4471/***************** Bit definition for FDCAN_NDAT1 register ********************/
4472#define FDCAN_NDAT1_ND0_Pos (0U)
4473#define FDCAN_NDAT1_ND0_Msk (0x1UL << FDCAN_NDAT1_ND0_Pos) /*!< 0x00000001 */
4474#define FDCAN_NDAT1_ND0 FDCAN_NDAT1_ND0_Msk /*!<New Data flag of Rx Buffer 0 */
4475#define FDCAN_NDAT1_ND1_Pos (1U)
4476#define FDCAN_NDAT1_ND1_Msk (0x1UL << FDCAN_NDAT1_ND1_Pos) /*!< 0x00000002 */
4477#define FDCAN_NDAT1_ND1 FDCAN_NDAT1_ND1_Msk /*!<New Data flag of Rx Buffer 1 */
4478#define FDCAN_NDAT1_ND2_Pos (2U)
4479#define FDCAN_NDAT1_ND2_Msk (0x1UL << FDCAN_NDAT1_ND2_Pos) /*!< 0x00000004 */
4480#define FDCAN_NDAT1_ND2 FDCAN_NDAT1_ND2_Msk /*!<New Data flag of Rx Buffer 2 */
4481#define FDCAN_NDAT1_ND3_Pos (3U)
4482#define FDCAN_NDAT1_ND3_Msk (0x1UL << FDCAN_NDAT1_ND3_Pos) /*!< 0x00000008 */
4483#define FDCAN_NDAT1_ND3 FDCAN_NDAT1_ND3_Msk /*!<New Data flag of Rx Buffer 3 */
4484#define FDCAN_NDAT1_ND4_Pos (4U)
4485#define FDCAN_NDAT1_ND4_Msk (0x1UL << FDCAN_NDAT1_ND4_Pos) /*!< 0x00000010 */
4486#define FDCAN_NDAT1_ND4 FDCAN_NDAT1_ND4_Msk /*!<New Data flag of Rx Buffer 4 */
4487#define FDCAN_NDAT1_ND5_Pos (5U)
4488#define FDCAN_NDAT1_ND5_Msk (0x1UL << FDCAN_NDAT1_ND5_Pos) /*!< 0x00000020 */
4489#define FDCAN_NDAT1_ND5 FDCAN_NDAT1_ND5_Msk /*!<New Data flag of Rx Buffer 5 */
4490#define FDCAN_NDAT1_ND6_Pos (6U)
4491#define FDCAN_NDAT1_ND6_Msk (0x1UL << FDCAN_NDAT1_ND6_Pos) /*!< 0x00000040 */
4492#define FDCAN_NDAT1_ND6 FDCAN_NDAT1_ND6_Msk /*!<New Data flag of Rx Buffer 6 */
4493#define FDCAN_NDAT1_ND7_Pos (7U)
4494#define FDCAN_NDAT1_ND7_Msk (0x1UL << FDCAN_NDAT1_ND7_Pos) /*!< 0x00000080 */
4495#define FDCAN_NDAT1_ND7 FDCAN_NDAT1_ND7_Msk /*!<New Data flag of Rx Buffer 7 */
4496#define FDCAN_NDAT1_ND8_Pos (8U)
4497#define FDCAN_NDAT1_ND8_Msk (0x1UL << FDCAN_NDAT1_ND8_Pos) /*!< 0x00000100 */
4498#define FDCAN_NDAT1_ND8 FDCAN_NDAT1_ND8_Msk /*!<New Data flag of Rx Buffer 8 */
4499#define FDCAN_NDAT1_ND9_Pos (9U)
4500#define FDCAN_NDAT1_ND9_Msk (0x1UL << FDCAN_NDAT1_ND9_Pos) /*!< 0x00000200 */
4501#define FDCAN_NDAT1_ND9 FDCAN_NDAT1_ND9_Msk /*!<New Data flag of Rx Buffer 9 */
4502#define FDCAN_NDAT1_ND10_Pos (10U)
4503#define FDCAN_NDAT1_ND10_Msk (0x1UL << FDCAN_NDAT1_ND10_Pos) /*!< 0x00000400 */
4504#define FDCAN_NDAT1_ND10 FDCAN_NDAT1_ND10_Msk /*!<New Data flag of Rx Buffer 10 */
4505#define FDCAN_NDAT1_ND11_Pos (11U)
4506#define FDCAN_NDAT1_ND11_Msk (0x1UL << FDCAN_NDAT1_ND11_Pos) /*!< 0x00000800 */
4507#define FDCAN_NDAT1_ND11 FDCAN_NDAT1_ND11_Msk /*!<New Data flag of Rx Buffer 11 */
4508#define FDCAN_NDAT1_ND12_Pos (12U)
4509#define FDCAN_NDAT1_ND12_Msk (0x1UL << FDCAN_NDAT1_ND12_Pos) /*!< 0x00001000 */
4510#define FDCAN_NDAT1_ND12 FDCAN_NDAT1_ND12_Msk /*!<New Data flag of Rx Buffer 12 */
4511#define FDCAN_NDAT1_ND13_Pos (13U)
4512#define FDCAN_NDAT1_ND13_Msk (0x1UL << FDCAN_NDAT1_ND13_Pos) /*!< 0x00002000 */
4513#define FDCAN_NDAT1_ND13 FDCAN_NDAT1_ND13_Msk /*!<New Data flag of Rx Buffer 13 */
4514#define FDCAN_NDAT1_ND14_Pos (14U)
4515#define FDCAN_NDAT1_ND14_Msk (0x1UL << FDCAN_NDAT1_ND14_Pos) /*!< 0x00004000 */
4516#define FDCAN_NDAT1_ND14 FDCAN_NDAT1_ND14_Msk /*!<New Data flag of Rx Buffer 14 */
4517#define FDCAN_NDAT1_ND15_Pos (15U)
4518#define FDCAN_NDAT1_ND15_Msk (0x1UL << FDCAN_NDAT1_ND15_Pos) /*!< 0x00008000 */
4519#define FDCAN_NDAT1_ND15 FDCAN_NDAT1_ND15_Msk /*!<New Data flag of Rx Buffer 15 */
4520#define FDCAN_NDAT1_ND16_Pos (16U)
4521#define FDCAN_NDAT1_ND16_Msk (0x1UL << FDCAN_NDAT1_ND16_Pos) /*!< 0x00010000 */
4522#define FDCAN_NDAT1_ND16 FDCAN_NDAT1_ND16_Msk /*!<New Data flag of Rx Buffer 16 */
4523#define FDCAN_NDAT1_ND17_Pos (17U)
4524#define FDCAN_NDAT1_ND17_Msk (0x1UL << FDCAN_NDAT1_ND17_Pos) /*!< 0x00020000 */
4525#define FDCAN_NDAT1_ND17 FDCAN_NDAT1_ND17_Msk /*!<New Data flag of Rx Buffer 17 */
4526#define FDCAN_NDAT1_ND18_Pos (18U)
4527#define FDCAN_NDAT1_ND18_Msk (0x1UL << FDCAN_NDAT1_ND18_Pos) /*!< 0x00040000 */
4528#define FDCAN_NDAT1_ND18 FDCAN_NDAT1_ND18_Msk /*!<New Data flag of Rx Buffer 18 */
4529#define FDCAN_NDAT1_ND19_Pos (19U)
4530#define FDCAN_NDAT1_ND19_Msk (0x1UL << FDCAN_NDAT1_ND19_Pos) /*!< 0x00080000 */
4531#define FDCAN_NDAT1_ND19 FDCAN_NDAT1_ND19_Msk /*!<New Data flag of Rx Buffer 19 */
4532#define FDCAN_NDAT1_ND20_Pos (20U)
4533#define FDCAN_NDAT1_ND20_Msk (0x1UL << FDCAN_NDAT1_ND20_Pos) /*!< 0x00100000 */
4534#define FDCAN_NDAT1_ND20 FDCAN_NDAT1_ND20_Msk /*!<New Data flag of Rx Buffer 20 */
4535#define FDCAN_NDAT1_ND21_Pos (21U)
4536#define FDCAN_NDAT1_ND21_Msk (0x1UL << FDCAN_NDAT1_ND21_Pos) /*!< 0x00200000 */
4537#define FDCAN_NDAT1_ND21 FDCAN_NDAT1_ND21_Msk /*!<New Data flag of Rx Buffer 21 */
4538#define FDCAN_NDAT1_ND22_Pos (22U)
4539#define FDCAN_NDAT1_ND22_Msk (0x1UL << FDCAN_NDAT1_ND22_Pos) /*!< 0x00400000 */
4540#define FDCAN_NDAT1_ND22 FDCAN_NDAT1_ND22_Msk /*!<New Data flag of Rx Buffer 22 */
4541#define FDCAN_NDAT1_ND23_Pos (23U)
4542#define FDCAN_NDAT1_ND23_Msk (0x1UL << FDCAN_NDAT1_ND23_Pos) /*!< 0x00800000 */
4543#define FDCAN_NDAT1_ND23 FDCAN_NDAT1_ND23_Msk /*!<New Data flag of Rx Buffer 23 */
4544#define FDCAN_NDAT1_ND24_Pos (24U)
4545#define FDCAN_NDAT1_ND24_Msk (0x1UL << FDCAN_NDAT1_ND24_Pos) /*!< 0x01000000 */
4546#define FDCAN_NDAT1_ND24 FDCAN_NDAT1_ND24_Msk /*!<New Data flag of Rx Buffer 24 */
4547#define FDCAN_NDAT1_ND25_Pos (25U)
4548#define FDCAN_NDAT1_ND25_Msk (0x1UL << FDCAN_NDAT1_ND25_Pos) /*!< 0x02000000 */
4549#define FDCAN_NDAT1_ND25 FDCAN_NDAT1_ND25_Msk /*!<New Data flag of Rx Buffer 25 */
4550#define FDCAN_NDAT1_ND26_Pos (26U)
4551#define FDCAN_NDAT1_ND26_Msk (0x1UL << FDCAN_NDAT1_ND26_Pos) /*!< 0x04000000 */
4552#define FDCAN_NDAT1_ND26 FDCAN_NDAT1_ND26_Msk /*!<New Data flag of Rx Buffer 26 */
4553#define FDCAN_NDAT1_ND27_Pos (27U)
4554#define FDCAN_NDAT1_ND27_Msk (0x1UL << FDCAN_NDAT1_ND27_Pos) /*!< 0x08000000 */
4555#define FDCAN_NDAT1_ND27 FDCAN_NDAT1_ND27_Msk /*!<New Data flag of Rx Buffer 27 */
4556#define FDCAN_NDAT1_ND28_Pos (28U)
4557#define FDCAN_NDAT1_ND28_Msk (0x1UL << FDCAN_NDAT1_ND28_Pos) /*!< 0x10000000 */
4558#define FDCAN_NDAT1_ND28 FDCAN_NDAT1_ND28_Msk /*!<New Data flag of Rx Buffer 28 */
4559#define FDCAN_NDAT1_ND29_Pos (29U)
4560#define FDCAN_NDAT1_ND29_Msk (0x1UL << FDCAN_NDAT1_ND29_Pos) /*!< 0x20000000 */
4561#define FDCAN_NDAT1_ND29 FDCAN_NDAT1_ND29_Msk /*!<New Data flag of Rx Buffer 29 */
4562#define FDCAN_NDAT1_ND30_Pos (30U)
4563#define FDCAN_NDAT1_ND30_Msk (0x1UL << FDCAN_NDAT1_ND30_Pos) /*!< 0x40000000 */
4564#define FDCAN_NDAT1_ND30 FDCAN_NDAT1_ND30_Msk /*!<New Data flag of Rx Buffer 30 */
4565#define FDCAN_NDAT1_ND31_Pos (31U)
4566#define FDCAN_NDAT1_ND31_Msk (0x1UL << FDCAN_NDAT1_ND31_Pos) /*!< 0x80000000 */
4567#define FDCAN_NDAT1_ND31 FDCAN_NDAT1_ND31_Msk /*!<New Data flag of Rx Buffer 31 */
4568
4569/***************** Bit definition for FDCAN_NDAT2 register ********************/
4570#define FDCAN_NDAT2_ND32_Pos (0U)
4571#define FDCAN_NDAT2_ND32_Msk (0x1UL << FDCAN_NDAT2_ND32_Pos) /*!< 0x00000001 */
4572#define FDCAN_NDAT2_ND32 FDCAN_NDAT2_ND32_Msk /*!<New Data flag of Rx Buffer 32 */
4573#define FDCAN_NDAT2_ND33_Pos (1U)
4574#define FDCAN_NDAT2_ND33_Msk (0x1UL << FDCAN_NDAT2_ND33_Pos) /*!< 0x00000002 */
4575#define FDCAN_NDAT2_ND33 FDCAN_NDAT2_ND33_Msk /*!<New Data flag of Rx Buffer 33 */
4576#define FDCAN_NDAT2_ND34_Pos (2U)
4577#define FDCAN_NDAT2_ND34_Msk (0x1UL << FDCAN_NDAT2_ND34_Pos) /*!< 0x00000004 */
4578#define FDCAN_NDAT2_ND34 FDCAN_NDAT2_ND34_Msk /*!<New Data flag of Rx Buffer 34 */
4579#define FDCAN_NDAT2_ND35_Pos (3U)
4580#define FDCAN_NDAT2_ND35_Msk (0x1UL << FDCAN_NDAT2_ND35_Pos) /*!< 0x00000008 */
4581#define FDCAN_NDAT2_ND35 FDCAN_NDAT2_ND35_Msk /*!<New Data flag of Rx Buffer 35 */
4582#define FDCAN_NDAT2_ND36_Pos (4U)
4583#define FDCAN_NDAT2_ND36_Msk (0x1UL << FDCAN_NDAT2_ND36_Pos) /*!< 0x00000010 */
4584#define FDCAN_NDAT2_ND36 FDCAN_NDAT2_ND36_Msk /*!<New Data flag of Rx Buffer 36 */
4585#define FDCAN_NDAT2_ND37_Pos (5U)
4586#define FDCAN_NDAT2_ND37_Msk (0x1UL << FDCAN_NDAT2_ND37_Pos) /*!< 0x00000020 */
4587#define FDCAN_NDAT2_ND37 FDCAN_NDAT2_ND37_Msk /*!<New Data flag of Rx Buffer 37 */
4588#define FDCAN_NDAT2_ND38_Pos (6U)
4589#define FDCAN_NDAT2_ND38_Msk (0x1UL << FDCAN_NDAT2_ND38_Pos) /*!< 0x00000040 */
4590#define FDCAN_NDAT2_ND38 FDCAN_NDAT2_ND38_Msk /*!<New Data flag of Rx Buffer 38 */
4591#define FDCAN_NDAT2_ND39_Pos (7U)
4592#define FDCAN_NDAT2_ND39_Msk (0x1UL << FDCAN_NDAT2_ND39_Pos) /*!< 0x00000080 */
4593#define FDCAN_NDAT2_ND39 FDCAN_NDAT2_ND39_Msk /*!<New Data flag of Rx Buffer 39 */
4594#define FDCAN_NDAT2_ND40_Pos (8U)
4595#define FDCAN_NDAT2_ND40_Msk (0x1UL << FDCAN_NDAT2_ND40_Pos) /*!< 0x00000100 */
4596#define FDCAN_NDAT2_ND40 FDCAN_NDAT2_ND40_Msk /*!<New Data flag of Rx Buffer 40 */
4597#define FDCAN_NDAT2_ND41_Pos (9U)
4598#define FDCAN_NDAT2_ND41_Msk (0x1UL << FDCAN_NDAT2_ND41_Pos) /*!< 0x00000200 */
4599#define FDCAN_NDAT2_ND41 FDCAN_NDAT2_ND41_Msk /*!<New Data flag of Rx Buffer 41 */
4600#define FDCAN_NDAT2_ND42_Pos (10U)
4601#define FDCAN_NDAT2_ND42_Msk (0x1UL << FDCAN_NDAT2_ND42_Pos) /*!< 0x00000400 */
4602#define FDCAN_NDAT2_ND42 FDCAN_NDAT2_ND42_Msk /*!<New Data flag of Rx Buffer 42 */
4603#define FDCAN_NDAT2_ND43_Pos (11U)
4604#define FDCAN_NDAT2_ND43_Msk (0x1UL << FDCAN_NDAT2_ND43_Pos) /*!< 0x00000800 */
4605#define FDCAN_NDAT2_ND43 FDCAN_NDAT2_ND43_Msk /*!<New Data flag of Rx Buffer 43 */
4606#define FDCAN_NDAT2_ND44_Pos (12U)
4607#define FDCAN_NDAT2_ND44_Msk (0x1UL << FDCAN_NDAT2_ND44_Pos) /*!< 0x00001000 */
4608#define FDCAN_NDAT2_ND44 FDCAN_NDAT2_ND44_Msk /*!<New Data flag of Rx Buffer 44 */
4609#define FDCAN_NDAT2_ND45_Pos (13U)
4610#define FDCAN_NDAT2_ND45_Msk (0x1UL << FDCAN_NDAT2_ND45_Pos) /*!< 0x00002000 */
4611#define FDCAN_NDAT2_ND45 FDCAN_NDAT2_ND45_Msk /*!<New Data flag of Rx Buffer 45 */
4612#define FDCAN_NDAT2_ND46_Pos (14U)
4613#define FDCAN_NDAT2_ND46_Msk (0x1UL << FDCAN_NDAT2_ND46_Pos) /*!< 0x00004000 */
4614#define FDCAN_NDAT2_ND46 FDCAN_NDAT2_ND46_Msk /*!<New Data flag of Rx Buffer 46 */
4615#define FDCAN_NDAT2_ND47_Pos (15U)
4616#define FDCAN_NDAT2_ND47_Msk (0x1UL << FDCAN_NDAT2_ND47_Pos) /*!< 0x00008000 */
4617#define FDCAN_NDAT2_ND47 FDCAN_NDAT2_ND47_Msk /*!<New Data flag of Rx Buffer 47 */
4618#define FDCAN_NDAT2_ND48_Pos (16U)
4619#define FDCAN_NDAT2_ND48_Msk (0x1UL << FDCAN_NDAT2_ND48_Pos) /*!< 0x00010000 */
4620#define FDCAN_NDAT2_ND48 FDCAN_NDAT2_ND48_Msk /*!<New Data flag of Rx Buffer 48 */
4621#define FDCAN_NDAT2_ND49_Pos (17U)
4622#define FDCAN_NDAT2_ND49_Msk (0x1UL << FDCAN_NDAT2_ND49_Pos) /*!< 0x00020000 */
4623#define FDCAN_NDAT2_ND49 FDCAN_NDAT2_ND49_Msk /*!<New Data flag of Rx Buffer 49 */
4624#define FDCAN_NDAT2_ND50_Pos (18U)
4625#define FDCAN_NDAT2_ND50_Msk (0x1UL << FDCAN_NDAT2_ND50_Pos) /*!< 0x00040000 */
4626#define FDCAN_NDAT2_ND50 FDCAN_NDAT2_ND50_Msk /*!<New Data flag of Rx Buffer 50 */
4627#define FDCAN_NDAT2_ND51_Pos (19U)
4628#define FDCAN_NDAT2_ND51_Msk (0x1UL << FDCAN_NDAT2_ND51_Pos) /*!< 0x00080000 */
4629#define FDCAN_NDAT2_ND51 FDCAN_NDAT2_ND51_Msk /*!<New Data flag of Rx Buffer 51 */
4630#define FDCAN_NDAT2_ND52_Pos (20U)
4631#define FDCAN_NDAT2_ND52_Msk (0x1UL << FDCAN_NDAT2_ND52_Pos) /*!< 0x00100000 */
4632#define FDCAN_NDAT2_ND52 FDCAN_NDAT2_ND52_Msk /*!<New Data flag of Rx Buffer 52 */
4633#define FDCAN_NDAT2_ND53_Pos (21U)
4634#define FDCAN_NDAT2_ND53_Msk (0x1UL << FDCAN_NDAT2_ND53_Pos) /*!< 0x00200000 */
4635#define FDCAN_NDAT2_ND53 FDCAN_NDAT2_ND53_Msk /*!<New Data flag of Rx Buffer 53 */
4636#define FDCAN_NDAT2_ND54_Pos (22U)
4637#define FDCAN_NDAT2_ND54_Msk (0x1UL << FDCAN_NDAT2_ND54_Pos) /*!< 0x00400000 */
4638#define FDCAN_NDAT2_ND54 FDCAN_NDAT2_ND54_Msk /*!<New Data flag of Rx Buffer 54 */
4639#define FDCAN_NDAT2_ND55_Pos (23U)
4640#define FDCAN_NDAT2_ND55_Msk (0x1UL << FDCAN_NDAT2_ND55_Pos) /*!< 0x00800000 */
4641#define FDCAN_NDAT2_ND55 FDCAN_NDAT2_ND55_Msk /*!<New Data flag of Rx Buffer 55 */
4642#define FDCAN_NDAT2_ND56_Pos (24U)
4643#define FDCAN_NDAT2_ND56_Msk (0x1UL << FDCAN_NDAT2_ND56_Pos) /*!< 0x01000000 */
4644#define FDCAN_NDAT2_ND56 FDCAN_NDAT2_ND56_Msk /*!<New Data flag of Rx Buffer 56 */
4645#define FDCAN_NDAT2_ND57_Pos (25U)
4646#define FDCAN_NDAT2_ND57_Msk (0x1UL << FDCAN_NDAT2_ND57_Pos) /*!< 0x02000000 */
4647#define FDCAN_NDAT2_ND57 FDCAN_NDAT2_ND57_Msk /*!<New Data flag of Rx Buffer 57 */
4648#define FDCAN_NDAT2_ND58_Pos (26U)
4649#define FDCAN_NDAT2_ND58_Msk (0x1UL << FDCAN_NDAT2_ND58_Pos) /*!< 0x04000000 */
4650#define FDCAN_NDAT2_ND58 FDCAN_NDAT2_ND58_Msk /*!<New Data flag of Rx Buffer 58 */
4651#define FDCAN_NDAT2_ND59_Pos (27U)
4652#define FDCAN_NDAT2_ND59_Msk (0x1UL << FDCAN_NDAT2_ND59_Pos) /*!< 0x08000000 */
4653#define FDCAN_NDAT2_ND59 FDCAN_NDAT2_ND59_Msk /*!<New Data flag of Rx Buffer 59 */
4654#define FDCAN_NDAT2_ND60_Pos (28U)
4655#define FDCAN_NDAT2_ND60_Msk (0x1UL << FDCAN_NDAT2_ND60_Pos) /*!< 0x10000000 */
4656#define FDCAN_NDAT2_ND60 FDCAN_NDAT2_ND60_Msk /*!<New Data flag of Rx Buffer 60 */
4657#define FDCAN_NDAT2_ND61_Pos (29U)
4658#define FDCAN_NDAT2_ND61_Msk (0x1UL << FDCAN_NDAT2_ND61_Pos) /*!< 0x20000000 */
4659#define FDCAN_NDAT2_ND61 FDCAN_NDAT2_ND61_Msk /*!<New Data flag of Rx Buffer 61 */
4660#define FDCAN_NDAT2_ND62_Pos (30U)
4661#define FDCAN_NDAT2_ND62_Msk (0x1UL << FDCAN_NDAT2_ND62_Pos) /*!< 0x40000000 */
4662#define FDCAN_NDAT2_ND62 FDCAN_NDAT2_ND62_Msk /*!<New Data flag of Rx Buffer 62 */
4663#define FDCAN_NDAT2_ND63_Pos (31U)
4664#define FDCAN_NDAT2_ND63_Msk (0x1UL << FDCAN_NDAT2_ND63_Pos) /*!< 0x80000000 */
4665#define FDCAN_NDAT2_ND63 FDCAN_NDAT2_ND63_Msk /*!<New Data flag of Rx Buffer 63 */
4666
4667/***************** Bit definition for FDCAN_RXF0C register ********************/
4668#define FDCAN_RXF0C_F0SA_Pos (2U)
4669#define FDCAN_RXF0C_F0SA_Msk (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos) /*!< 0x0000FFFC */
4670#define FDCAN_RXF0C_F0SA FDCAN_RXF0C_F0SA_Msk /*!<Rx FIFO 0 Start Address */
4671#define FDCAN_RXF0C_F0S_Pos (16U)
4672#define FDCAN_RXF0C_F0S_Msk (0x7FUL << FDCAN_RXF0C_F0S_Pos) /*!< 0x007F0000 */
4673#define FDCAN_RXF0C_F0S FDCAN_RXF0C_F0S_Msk /*!<Number of Rx FIFO 0 elements */
4674#define FDCAN_RXF0C_F0WM_Pos (24U)
4675#define FDCAN_RXF0C_F0WM_Msk (0x7FUL << FDCAN_RXF0C_F0WM_Pos) /*!< 0x7F000000 */
4676#define FDCAN_RXF0C_F0WM FDCAN_RXF0C_F0WM_Msk /*!<FIFO 0 Watermark */
4677#define FDCAN_RXF0C_F0OM_Pos (31U)
4678#define FDCAN_RXF0C_F0OM_Msk (0x1UL << FDCAN_RXF0C_F0OM_Pos) /*!< 0x80000000 */
4679#define FDCAN_RXF0C_F0OM FDCAN_RXF0C_F0OM_Msk /*!<FIFO 0 Operation Mode */
4680
4681/***************** Bit definition for FDCAN_RXF0S register ********************/
4682#define FDCAN_RXF0S_F0FL_Pos (0U)
4683#define FDCAN_RXF0S_F0FL_Msk (0x7FUL << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000007F */
4684#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */
4685#define FDCAN_RXF0S_F0GI_Pos (8U)
4686#define FDCAN_RXF0S_F0GI_Msk (0x3FUL << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00003F00 */
4687#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */
4688#define FDCAN_RXF0S_F0PI_Pos (16U)
4689#define FDCAN_RXF0S_F0PI_Msk (0x3FUL << FDCAN_RXF0S_F0PI_Pos) /*!< 0x003F0000 */
4690#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */
4691#define FDCAN_RXF0S_F0F_Pos (24U)
4692#define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */
4693#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */
4694#define FDCAN_RXF0S_RF0L_Pos (25U)
4695#define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */
4696#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
4697
4698/***************** Bit definition for FDCAN_RXF0A register ********************/
4699#define FDCAN_RXF0A_F0AI_Pos (0U)
4700#define FDCAN_RXF0A_F0AI_Msk (0x3FUL << FDCAN_RXF0A_F0AI_Pos) /*!< 0x0000003F */
4701#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */
4702
4703/***************** Bit definition for FDCAN_RXBC register ********************/
4704#define FDCAN_RXBC_RBSA_Pos (2U)
4705#define FDCAN_RXBC_RBSA_Msk (0x3FFFUL << FDCAN_RXBC_RBSA_Pos) /*!< 0x0000FFFC */
4706#define FDCAN_RXBC_RBSA FDCAN_RXBC_RBSA_Msk /*!<Rx Buffer Start Address */
4707
4708/***************** Bit definition for FDCAN_RXF1C register ********************/
4709#define FDCAN_RXF1C_F1SA_Pos (2U)
4710#define FDCAN_RXF1C_F1SA_Msk (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos) /*!< 0x0000FFFC */
4711#define FDCAN_RXF1C_F1SA FDCAN_RXF1C_F1SA_Msk /*!<Rx FIFO 1 Start Address */
4712#define FDCAN_RXF1C_F1S_Pos (16U)
4713#define FDCAN_RXF1C_F1S_Msk (0x7FUL << FDCAN_RXF1C_F1S_Pos) /*!< 0x007F0000 */
4714#define FDCAN_RXF1C_F1S FDCAN_RXF1C_F1S_Msk /*!<Number of Rx FIFO 1 elements */
4715#define FDCAN_RXF1C_F1WM_Pos (24U)
4716#define FDCAN_RXF1C_F1WM_Msk (0x7FUL << FDCAN_RXF1C_F1WM_Pos) /*!< 0x7F000000 */
4717#define FDCAN_RXF1C_F1WM FDCAN_RXF1C_F1WM_Msk /*!<Rx FIFO 1 Watermark */
4718#define FDCAN_RXF1C_F1OM_Pos (31U)
4719#define FDCAN_RXF1C_F1OM_Msk (0x1UL << FDCAN_RXF1C_F1OM_Pos) /*!< 0x80000000 */
4720#define FDCAN_RXF1C_F1OM FDCAN_RXF1C_F1OM_Msk /*!<FIFO 1 Operation Mode */
4721
4722/***************** Bit definition for FDCAN_RXF1S register ********************/
4723#define FDCAN_RXF1S_F1FL_Pos (0U)
4724#define FDCAN_RXF1S_F1FL_Msk (0x7FUL << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000007F */
4725#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */
4726#define FDCAN_RXF1S_F1GI_Pos (8U)
4727#define FDCAN_RXF1S_F1GI_Msk (0x3FUL << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00003F00 */
4728#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */
4729#define FDCAN_RXF1S_F1PI_Pos (16U)
4730#define FDCAN_RXF1S_F1PI_Msk (0x3FUL << FDCAN_RXF1S_F1PI_Pos) /*!< 0x003F0000 */
4731#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */
4732#define FDCAN_RXF1S_F1F_Pos (24U)
4733#define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */
4734#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */
4735#define FDCAN_RXF1S_RF1L_Pos (25U)
4736#define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */
4737#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
4738
4739/***************** Bit definition for FDCAN_RXF1A register ********************/
4740#define FDCAN_RXF1A_F1AI_Pos (0U)
4741#define FDCAN_RXF1A_F1AI_Msk (0x3FUL << FDCAN_RXF1A_F1AI_Pos) /*!< 0x0000003F */
4742#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */
4743
4744/***************** Bit definition for FDCAN_RXESC register ********************/
4745#define FDCAN_RXESC_F0DS_Pos (0U)
4746#define FDCAN_RXESC_F0DS_Msk (0x7UL << FDCAN_RXESC_F0DS_Pos) /*!< 0x00000007 */
4747#define FDCAN_RXESC_F0DS FDCAN_RXESC_F0DS_Msk /*!<Rx FIFO 1 Data Field Size */
4748#define FDCAN_RXESC_F1DS_Pos (4U)
4749#define FDCAN_RXESC_F1DS_Msk (0x7UL << FDCAN_RXESC_F1DS_Pos) /*!< 0x00000070 */
4750#define FDCAN_RXESC_F1DS FDCAN_RXESC_F1DS_Msk /*!<Rx FIFO 0 Data Field Size */
4751#define FDCAN_RXESC_RBDS_Pos (8U)
4752#define FDCAN_RXESC_RBDS_Msk (0x7UL << FDCAN_RXESC_RBDS_Pos) /*!< 0x00000700 */
4753#define FDCAN_RXESC_RBDS FDCAN_RXESC_RBDS_Msk /*!<Rx Buffer Data Field Size */
4754
4755/***************** Bit definition for FDCAN_TXBC register *********************/
4756#define FDCAN_TXBC_TBSA_Pos (2U)
4757#define FDCAN_TXBC_TBSA_Msk (0x3FFFUL << FDCAN_TXBC_TBSA_Pos) /*!< 0x0000FFFC */
4758#define FDCAN_TXBC_TBSA FDCAN_TXBC_TBSA_Msk /*!<Tx Buffers Start Address */
4759#define FDCAN_TXBC_NDTB_Pos (16U)
4760#define FDCAN_TXBC_NDTB_Msk (0x3FUL << FDCAN_TXBC_NDTB_Pos) /*!< 0x003F0000 */
4761#define FDCAN_TXBC_NDTB FDCAN_TXBC_NDTB_Msk /*!<Number of Dedicated Transmit Buffers */
4762#define FDCAN_TXBC_TFQS_Pos (24U)
4763#define FDCAN_TXBC_TFQS_Msk (0x3FUL << FDCAN_TXBC_TFQS_Pos) /*!< 0x3F000000 */
4764#define FDCAN_TXBC_TFQS FDCAN_TXBC_TFQS_Msk /*!<Transmit FIFO/Queue Size */
4765#define FDCAN_TXBC_TFQM_Pos (30U)
4766#define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) /*!< 0x40000000 */
4767#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */
4768
4769/***************** Bit definition for FDCAN_TXFQS register *********************/
4770#define FDCAN_TXFQS_TFFL_Pos (0U)
4771#define FDCAN_TXFQS_TFFL_Msk (0x3FUL << FDCAN_TXFQS_TFFL_Pos) /*!< 0x0000003F */
4772#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */
4773#define FDCAN_TXFQS_TFGI_Pos (8U)
4774#define FDCAN_TXFQS_TFGI_Msk (0x1FUL << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00001F00 */
4775#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */
4776#define FDCAN_TXFQS_TFQPI_Pos (16U)
4777#define FDCAN_TXFQS_TFQPI_Msk (0x1FUL << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x001F0000 */
4778#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */
4779#define FDCAN_TXFQS_TFQF_Pos (21U)
4780#define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */
4781#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */
4782
4783/***************** Bit definition for FDCAN_TXESC register *********************/
4784#define FDCAN_TXESC_TBDS_Pos (0U)
4785#define FDCAN_TXESC_TBDS_Msk (0x7UL << FDCAN_TXESC_TBDS_Pos) /*!< 0x00000007 */
4786#define FDCAN_TXESC_TBDS FDCAN_TXESC_TBDS_Msk /*!<Tx Buffer Data Field Size */
4787
4788/***************** Bit definition for FDCAN_TXBRP register *********************/
4789#define FDCAN_TXBRP_TRP_Pos (0U)
4790#define FDCAN_TXBRP_TRP_Msk (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos) /*!< 0xFFFFFFFF */
4791#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */
4792
4793/***************** Bit definition for FDCAN_TXBAR register *********************/
4794#define FDCAN_TXBAR_AR_Pos (0U)
4795#define FDCAN_TXBAR_AR_Msk (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos) /*!< 0xFFFFFFFF */
4796#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */
4797
4798/***************** Bit definition for FDCAN_TXBCR register *********************/
4799#define FDCAN_TXBCR_CR_Pos (0U)
4800#define FDCAN_TXBCR_CR_Msk (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos) /*!< 0xFFFFFFFF */
4801#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */
4802
4803/***************** Bit definition for FDCAN_TXBTO register *********************/
4804#define FDCAN_TXBTO_TO_Pos (0U)
4805#define FDCAN_TXBTO_TO_Msk (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos) /*!< 0xFFFFFFFF */
4806#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */
4807
4808/***************** Bit definition for FDCAN_TXBCF register *********************/
4809#define FDCAN_TXBCF_CF_Pos (0U)
4810#define FDCAN_TXBCF_CF_Msk (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos) /*!< 0xFFFFFFFF */
4811#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */
4812
4813/***************** Bit definition for FDCAN_TXBTIE register ********************/
4814#define FDCAN_TXBTIE_TIE_Pos (0U)
4815#define FDCAN_TXBTIE_TIE_Msk (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos) /*!< 0xFFFFFFFF */
4816#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */
4817
4818/***************** Bit definition for FDCAN_ TXBCIE register *******************/
4819#define FDCAN_TXBCIE_CFIE_Pos (0U)
4820#define FDCAN_TXBCIE_CFIE_Msk (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos) /*!< 0xFFFFFFFF */
4821#define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk /*!<Cancellation Finished Interrupt Enable */
4822
4823/***************** Bit definition for FDCAN_TXEFC register *********************/
4824#define FDCAN_TXEFC_EFSA_Pos (2U)
4825#define FDCAN_TXEFC_EFSA_Msk (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos) /*!< 0x0000FFFC */
4826#define FDCAN_TXEFC_EFSA FDCAN_TXEFC_EFSA_Msk /*!<Event FIFO Start Address */
4827#define FDCAN_TXEFC_EFS_Pos (16U)
4828#define FDCAN_TXEFC_EFS_Msk (0x3FUL << FDCAN_TXEFC_EFS_Pos) /*!< 0x003F0000 */
4829#define FDCAN_TXEFC_EFS FDCAN_TXEFC_EFS_Msk /*!<Event FIFO Size */
4830#define FDCAN_TXEFC_EFWM_Pos (24U)
4831#define FDCAN_TXEFC_EFWM_Msk (0x3FUL << FDCAN_TXEFC_EFWM_Pos) /*!< 0x3F000000 */
4832#define FDCAN_TXEFC_EFWM FDCAN_TXEFC_EFWM_Msk /*!<Event FIFO Watermark */
4833
4834/***************** Bit definition for FDCAN_TXEFS register *********************/
4835#define FDCAN_TXEFS_EFFL_Pos (0U)
4836#define FDCAN_TXEFS_EFFL_Msk (0x3FUL << FDCAN_TXEFS_EFFL_Pos) /*!< 0x0000003F */
4837#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */
4838#define FDCAN_TXEFS_EFGI_Pos (8U)
4839#define FDCAN_TXEFS_EFGI_Msk (0x1FUL << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00001F00 */
4840#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */
4841#define FDCAN_TXEFS_EFPI_Pos (16U)
4842#define FDCAN_TXEFS_EFPI_Msk (0x1FUL << FDCAN_TXEFS_EFPI_Pos) /*!< 0x001F0000 */
4843#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */
4844#define FDCAN_TXEFS_EFF_Pos (24U)
4845#define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */
4846#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */
4847#define FDCAN_TXEFS_TEFL_Pos (25U)
4848#define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */
4849#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */
4850
4851/***************** Bit definition for FDCAN_TXEFA register *********************/
4852#define FDCAN_TXEFA_EFAI_Pos (0U)
4853#define FDCAN_TXEFA_EFAI_Msk (0x1FUL << FDCAN_TXEFA_EFAI_Pos) /*!< 0x0000001F */
4854#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */
4855
4856/***************** Bit definition for FDCAN_TTTMC register *********************/
4857#define FDCAN_TTTMC_TMSA_Pos (2U)
4858#define FDCAN_TTTMC_TMSA_Msk (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos) /*!< 0x0000FFFC */
4859#define FDCAN_TTTMC_TMSA FDCAN_TTTMC_TMSA_Msk /*!<Trigger Memory Start Address */
4860#define FDCAN_TTTMC_TME_Pos (16U)
4861#define FDCAN_TTTMC_TME_Msk (0x7FUL << FDCAN_TTTMC_TME_Pos) /*!< 0x007F0000 */
4862#define FDCAN_TTTMC_TME FDCAN_TTTMC_TME_Msk /*!<Trigger Memory Elements */
4863
4864/***************** Bit definition for FDCAN_TTRMC register *********************/
4865#define FDCAN_TTRMC_RID_Pos (0U)
4866#define FDCAN_TTRMC_RID_Msk (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos) /*!< 0x1FFFFFFF */
4867#define FDCAN_TTRMC_RID FDCAN_TTRMC_RID_Msk /*!<Reference Identifier */
4868#define FDCAN_TTRMC_XTD_Pos (30U)
4869#define FDCAN_TTRMC_XTD_Msk (0x1UL << FDCAN_TTRMC_XTD_Pos) /*!< 0x40000000 */
4870#define FDCAN_TTRMC_XTD FDCAN_TTRMC_XTD_Msk /*!< Extended Identifier */
4871#define FDCAN_TTRMC_RMPS_Pos (31U)
4872#define FDCAN_TTRMC_RMPS_Msk (0x1UL << FDCAN_TTRMC_RMPS_Pos) /*!< 0x80000000 */
4873#define FDCAN_TTRMC_RMPS FDCAN_TTRMC_RMPS_Msk /*!<Reference Message Payload Select */
4874
4875/***************** Bit definition for FDCAN_TTOCF register *********************/
4876#define FDCAN_TTOCF_OM_Pos (0U)
4877#define FDCAN_TTOCF_OM_Msk (0x3UL << FDCAN_TTOCF_OM_Pos) /*!< 0x00000003 */
4878#define FDCAN_TTOCF_OM FDCAN_TTOCF_OM_Msk /*!<Operation Mode */
4879#define FDCAN_TTOCF_GEN_Pos (3U)
4880#define FDCAN_TTOCF_GEN_Msk (0x1UL << FDCAN_TTOCF_GEN_Pos) /*!< 0x00000008 */
4881#define FDCAN_TTOCF_GEN FDCAN_TTOCF_GEN_Msk /*!<Gap Enable */
4882#define FDCAN_TTOCF_TM_Pos (4U)
4883#define FDCAN_TTOCF_TM_Msk (0x1UL << FDCAN_TTOCF_TM_Pos) /*!< 0x00000010 */
4884#define FDCAN_TTOCF_TM FDCAN_TTOCF_TM_Msk /*!<Time Master */
4885#define FDCAN_TTOCF_LDSDL_Pos (5U)
4886#define FDCAN_TTOCF_LDSDL_Msk (0x7UL << FDCAN_TTOCF_LDSDL_Pos) /*!< 0x000000E0 */
4887#define FDCAN_TTOCF_LDSDL FDCAN_TTOCF_LDSDL_Msk /*!<LD of Synchronization Deviation Limit */
4888#define FDCAN_TTOCF_IRTO_Pos (8U)
4889#define FDCAN_TTOCF_IRTO_Msk (0x7FUL << FDCAN_TTOCF_IRTO_Pos) /*!< 0x00007F00 */
4890#define FDCAN_TTOCF_IRTO FDCAN_TTOCF_IRTO_Msk /*!<Initial Reference Trigger Offset */
4891#define FDCAN_TTOCF_EECS_Pos (15U)
4892#define FDCAN_TTOCF_EECS_Msk (0x1UL << FDCAN_TTOCF_EECS_Pos) /*!< 0x00008000 */
4893#define FDCAN_TTOCF_EECS FDCAN_TTOCF_EECS_Msk /*!<Enable External Clock Synchronization */
4894#define FDCAN_TTOCF_AWL_Pos (16U)
4895#define FDCAN_TTOCF_AWL_Msk (0xFFUL << FDCAN_TTOCF_AWL_Pos) /*!< 0x00FF0000 */
4896#define FDCAN_TTOCF_AWL FDCAN_TTOCF_AWL_Msk /*!<Application Watchdog Limit */
4897#define FDCAN_TTOCF_EGTF_Pos (24U)
4898#define FDCAN_TTOCF_EGTF_Msk (0x1UL << FDCAN_TTOCF_EGTF_Pos) /*!< 0x01000000 */
4899#define FDCAN_TTOCF_EGTF FDCAN_TTOCF_EGTF_Msk /*!<Enable Global Time Filtering */
4900#define FDCAN_TTOCF_ECC_Pos (25U)
4901#define FDCAN_TTOCF_ECC_Msk (0x1UL << FDCAN_TTOCF_ECC_Pos) /*!< 0x02000000 */
4902#define FDCAN_TTOCF_ECC FDCAN_TTOCF_ECC_Msk /*!<Enable Clock Calibration */
4903#define FDCAN_TTOCF_EVTP_Pos (26U)
4904#define FDCAN_TTOCF_EVTP_Msk (0x1UL << FDCAN_TTOCF_EVTP_Pos) /*!< 0x04000000 */
4905#define FDCAN_TTOCF_EVTP FDCAN_TTOCF_EVTP_Msk /*!<Event Trigger Polarity */
4906
4907/***************** Bit definition for FDCAN_TTMLM register *********************/
4908#define FDCAN_TTMLM_CCM_Pos (0U)
4909#define FDCAN_TTMLM_CCM_Msk (0x3FUL << FDCAN_TTMLM_CCM_Pos) /*!< 0x0000003F */
4910#define FDCAN_TTMLM_CCM FDCAN_TTMLM_CCM_Msk /*!<Cycle Count Max */
4911#define FDCAN_TTMLM_CSS_Pos (6U)
4912#define FDCAN_TTMLM_CSS_Msk (0x3UL << FDCAN_TTMLM_CSS_Pos) /*!< 0x000000C0 */
4913#define FDCAN_TTMLM_CSS FDCAN_TTMLM_CSS_Msk /*!<Cycle Start Synchronization */
4914#define FDCAN_TTMLM_TXEW_Pos (8U)
4915#define FDCAN_TTMLM_TXEW_Msk (0xFUL << FDCAN_TTMLM_TXEW_Pos) /*!< 0x00000F00 */
4916#define FDCAN_TTMLM_TXEW FDCAN_TTMLM_TXEW_Msk /*!<Tx Enable Window */
4917#define FDCAN_TTMLM_ENTT_Pos (16U)
4918#define FDCAN_TTMLM_ENTT_Msk (0xFFFUL << FDCAN_TTMLM_ENTT_Pos) /*!< 0x0FFF0000 */
4919#define FDCAN_TTMLM_ENTT FDCAN_TTMLM_ENTT_Msk /*!<Expected Number of Tx Triggers */
4920
4921/***************** Bit definition for FDCAN_TURCF register *********************/
4922#define FDCAN_TURCF_NCL_Pos (0U)
4923#define FDCAN_TURCF_NCL_Msk (0xFFFFUL << FDCAN_TURCF_NCL_Pos) /*!< 0x0000FFFF */
4924#define FDCAN_TURCF_NCL FDCAN_TURCF_NCL_Msk /*!<Numerator Configuration Low */
4925#define FDCAN_TURCF_DC_Pos (16U)
4926#define FDCAN_TURCF_DC_Msk (0x3FFFUL << FDCAN_TURCF_DC_Pos) /*!< 0x3FFF0000 */
4927#define FDCAN_TURCF_DC FDCAN_TURCF_DC_Msk /*!<Denominator Configuration */
4928#define FDCAN_TURCF_ELT_Pos (31U)
4929#define FDCAN_TURCF_ELT_Msk (0x1UL << FDCAN_TURCF_ELT_Pos) /*!< 0x80000000 */
4930#define FDCAN_TURCF_ELT FDCAN_TURCF_ELT_Msk /*!<Enable Local Time */
4931
4932/***************** Bit definition for FDCAN_TTOCN register ********************/
4933#define FDCAN_TTOCN_SGT_Pos (0U)
4934#define FDCAN_TTOCN_SGT_Msk (0x1UL << FDCAN_TTOCN_SGT_Pos) /*!< 0x00000001 */
4935#define FDCAN_TTOCN_SGT FDCAN_TTOCN_SGT_Msk /*!<Set Global time */
4936#define FDCAN_TTOCN_ECS_Pos (1U)
4937#define FDCAN_TTOCN_ECS_Msk (0x1UL << FDCAN_TTOCN_ECS_Pos) /*!< 0x00000002 */
4938#define FDCAN_TTOCN_ECS FDCAN_TTOCN_ECS_Msk /*!<External Clock Synchronization */
4939#define FDCAN_TTOCN_SWP_Pos (2U)
4940#define FDCAN_TTOCN_SWP_Msk (0x1UL << FDCAN_TTOCN_SWP_Pos) /*!< 0x00000004 */
4941#define FDCAN_TTOCN_SWP FDCAN_TTOCN_SWP_Msk /*!<Stop Watch Polarity */
4942#define FDCAN_TTOCN_SWS_Pos (3U)
4943#define FDCAN_TTOCN_SWS_Msk (0x3UL << FDCAN_TTOCN_SWS_Pos) /*!< 0x00000018 */
4944#define FDCAN_TTOCN_SWS FDCAN_TTOCN_SWS_Msk /*!<Stop Watch Source */
4945#define FDCAN_TTOCN_RTIE_Pos (5U)
4946#define FDCAN_TTOCN_RTIE_Msk (0x1UL << FDCAN_TTOCN_RTIE_Pos) /*!< 0x00000020 */
4947#define FDCAN_TTOCN_RTIE FDCAN_TTOCN_RTIE_Msk /*!<Register Time Mark Interrupt Pulse Enable */
4948#define FDCAN_TTOCN_TMC_Pos (6U)
4949#define FDCAN_TTOCN_TMC_Msk (0x3UL << FDCAN_TTOCN_TMC_Pos) /*!< 0x000000C0 */
4950#define FDCAN_TTOCN_TMC FDCAN_TTOCN_TMC_Msk /*!<Register Time Mark Compare */
4951#define FDCAN_TTOCN_TTIE_Pos (8U)
4952#define FDCAN_TTOCN_TTIE_Msk (0x1UL << FDCAN_TTOCN_TTIE_Pos) /*!< 0x00000100 */
4953#define FDCAN_TTOCN_TTIE FDCAN_TTOCN_TTIE_Msk /*!<Trigger Time Mark Interrupt Pulse Enable */
4954#define FDCAN_TTOCN_GCS_Pos (9U)
4955#define FDCAN_TTOCN_GCS_Msk (0x1UL << FDCAN_TTOCN_GCS_Pos) /*!< 0x00000200 */
4956#define FDCAN_TTOCN_GCS FDCAN_TTOCN_GCS_Msk /*!<Gap Control Select */
4957#define FDCAN_TTOCN_FGP_Pos (10U)
4958#define FDCAN_TTOCN_FGP_Msk (0x1UL << FDCAN_TTOCN_FGP_Pos) /*!< 0x00000400 */
4959#define FDCAN_TTOCN_FGP FDCAN_TTOCN_FGP_Msk /*!<Finish Gap */
4960#define FDCAN_TTOCN_TMG_Pos (11U)
4961#define FDCAN_TTOCN_TMG_Msk (0x1UL << FDCAN_TTOCN_TMG_Pos) /*!< 0x00000800 */
4962#define FDCAN_TTOCN_TMG FDCAN_TTOCN_TMG_Msk /*!<Time Mark Gap */
4963#define FDCAN_TTOCN_NIG_Pos (12U)
4964#define FDCAN_TTOCN_NIG_Msk (0x1UL << FDCAN_TTOCN_NIG_Pos) /*!< 0x00001000 */
4965#define FDCAN_TTOCN_NIG FDCAN_TTOCN_NIG_Msk /*!<Next is Gap */
4966#define FDCAN_TTOCN_ESCN_Pos (13U)
4967#define FDCAN_TTOCN_ESCN_Msk (0x1UL << FDCAN_TTOCN_ESCN_Pos) /*!< 0x00002000 */
4968#define FDCAN_TTOCN_ESCN FDCAN_TTOCN_ESCN_Msk /*!<External Synchronization Control */
4969#define FDCAN_TTOCN_LCKC_Pos (15U)
4970#define FDCAN_TTOCN_LCKC_Msk (0x1UL << FDCAN_TTOCN_LCKC_Pos) /*!< 0x00008000 */
4971#define FDCAN_TTOCN_LCKC FDCAN_TTOCN_LCKC_Msk /*!<TT Operation Control Register Locked */
4972
4973/***************** Bit definition for FDCAN_TTGTP register ********************/
4974#define FDCAN_TTGTP_TP_Pos (0U)
4975#define FDCAN_TTGTP_TP_Msk (0xFFFFUL << FDCAN_TTGTP_TP_Pos) /*!< 0x0000FFFF */
4976#define FDCAN_TTGTP_TP FDCAN_TTGTP_TP_Msk /*!<Time Preset */
4977#define FDCAN_TTGTP_CTP_Pos (16U)
4978#define FDCAN_TTGTP_CTP_Msk (0xFFFFUL << FDCAN_TTGTP_CTP_Pos) /*!< 0xFFFF0000 */
4979#define FDCAN_TTGTP_CTP FDCAN_TTGTP_CTP_Msk /*!<Cycle Time Target Phase */
4980
4981/***************** Bit definition for FDCAN_TTTMK register ********************/
4982#define FDCAN_TTTMK_TM_Pos (0U)
4983#define FDCAN_TTTMK_TM_Msk (0xFFFFUL << FDCAN_TTTMK_TM_Pos) /*!< 0x0000FFFF */
4984#define FDCAN_TTTMK_TM FDCAN_TTTMK_TM_Msk /*!<Time Mark */
4985#define FDCAN_TTTMK_TICC_Pos (16U)
4986#define FDCAN_TTTMK_TICC_Msk (0x7FUL << FDCAN_TTTMK_TICC_Pos) /*!< 0x007F0000 */
4987#define FDCAN_TTTMK_TICC FDCAN_TTTMK_TICC_Msk /*!<Time Mark Cycle Code */
4988#define FDCAN_TTTMK_LCKM_Pos (31U)
4989#define FDCAN_TTTMK_LCKM_Msk (0x1UL << FDCAN_TTTMK_LCKM_Pos) /*!< 0x80000000 */
4990#define FDCAN_TTTMK_LCKM FDCAN_TTTMK_LCKM_Msk /*!<TT Time Mark Register Locked */
4991
4992/***************** Bit definition for FDCAN_TTIR register ********************/
4993#define FDCAN_TTIR_SBC_Pos (0U)
4994#define FDCAN_TTIR_SBC_Msk (0x1UL << FDCAN_TTIR_SBC_Pos) /*!< 0x00000001 */
4995#define FDCAN_TTIR_SBC FDCAN_TTIR_SBC_Msk /*!<Start of Basic Cycle */
4996#define FDCAN_TTIR_SMC_Pos (1U)
4997#define FDCAN_TTIR_SMC_Msk (0x1UL << FDCAN_TTIR_SMC_Pos) /*!< 0x00000002 */
4998#define FDCAN_TTIR_SMC FDCAN_TTIR_SMC_Msk /*!<Start of Matrix Cycle */
4999#define FDCAN_TTIR_CSM_Pos (2U)
5000#define FDCAN_TTIR_CSM_Msk (0x1UL << FDCAN_TTIR_CSM_Pos) /*!< 0x00000004 */
5001#define FDCAN_TTIR_CSM FDCAN_TTIR_CSM_Msk /*!<Change of Synchronization Mode */
5002#define FDCAN_TTIR_SOG_Pos (3U)
5003#define FDCAN_TTIR_SOG_Msk (0x1UL << FDCAN_TTIR_SOG_Pos) /*!< 0x00000008 */
5004#define FDCAN_TTIR_SOG FDCAN_TTIR_SOG_Msk /*!<Start of Gap */
5005#define FDCAN_TTIR_RTMI_Pos (4U)
5006#define FDCAN_TTIR_RTMI_Msk (0x1UL << FDCAN_TTIR_RTMI_Pos) /*!< 0x00000010 */
5007#define FDCAN_TTIR_RTMI FDCAN_TTIR_RTMI_Msk /*!<Register Time Mark Interrupt */
5008#define FDCAN_TTIR_TTMI_Pos (5U)
5009#define FDCAN_TTIR_TTMI_Msk (0x1UL << FDCAN_TTIR_TTMI_Pos) /*!< 0x00000020 */
5010#define FDCAN_TTIR_TTMI FDCAN_TTIR_TTMI_Msk /*!<Trigger Time Mark Event Internal */
5011#define FDCAN_TTIR_SWE_Pos (6U)
5012#define FDCAN_TTIR_SWE_Msk (0x1UL << FDCAN_TTIR_SWE_Pos) /*!< 0x00000040 */
5013#define FDCAN_TTIR_SWE FDCAN_TTIR_SWE_Msk /*!<Stop Watch Event */
5014#define FDCAN_TTIR_GTW_Pos (7U)
5015#define FDCAN_TTIR_GTW_Msk (0x1UL << FDCAN_TTIR_GTW_Pos) /*!< 0x00000080 */
5016#define FDCAN_TTIR_GTW FDCAN_TTIR_GTW_Msk /*!<Global Time Wrap */
5017#define FDCAN_TTIR_GTD_Pos (8U)
5018#define FDCAN_TTIR_GTD_Msk (0x1UL << FDCAN_TTIR_GTD_Pos) /*!< 0x00000100 */
5019#define FDCAN_TTIR_GTD FDCAN_TTIR_GTD_Msk /*!<Global Time Discontinuity */
5020#define FDCAN_TTIR_GTE_Pos (9U)
5021#define FDCAN_TTIR_GTE_Msk (0x1UL << FDCAN_TTIR_GTE_Pos) /*!< 0x00000200 */
5022#define FDCAN_TTIR_GTE FDCAN_TTIR_GTE_Msk /*!<Global Time Error */
5023#define FDCAN_TTIR_TXU_Pos (10U)
5024#define FDCAN_TTIR_TXU_Msk (0x1UL << FDCAN_TTIR_TXU_Pos) /*!< 0x00000400 */
5025#define FDCAN_TTIR_TXU FDCAN_TTIR_TXU_Msk /*!<Tx Count Underflow */
5026#define FDCAN_TTIR_TXO_Pos (11U)
5027#define FDCAN_TTIR_TXO_Msk (0x1UL << FDCAN_TTIR_TXO_Pos) /*!< 0x00000800 */
5028#define FDCAN_TTIR_TXO FDCAN_TTIR_TXO_Msk /*!<Tx Count Overflow */
5029#define FDCAN_TTIR_SE1_Pos (12U)
5030#define FDCAN_TTIR_SE1_Msk (0x1UL << FDCAN_TTIR_SE1_Pos) /*!< 0x00001000 */
5031#define FDCAN_TTIR_SE1 FDCAN_TTIR_SE1_Msk /*!<Scheduling Error 1 */
5032#define FDCAN_TTIR_SE2_Pos (13U)
5033#define FDCAN_TTIR_SE2_Msk (0x1UL << FDCAN_TTIR_SE2_Pos) /*!< 0x00002000 */
5034#define FDCAN_TTIR_SE2 FDCAN_TTIR_SE2_Msk /*!<Scheduling Error 2 */
5035#define FDCAN_TTIR_ELC_Pos (14U)
5036#define FDCAN_TTIR_ELC_Msk (0x1UL << FDCAN_TTIR_ELC_Pos) /*!< 0x00004000 */
5037#define FDCAN_TTIR_ELC FDCAN_TTIR_ELC_Msk /*!<Error Level Changed */
5038#define FDCAN_TTIR_IWT_Pos (15U)
5039#define FDCAN_TTIR_IWT_Msk (0x1UL << FDCAN_TTIR_IWT_Pos) /*!< 0x00008000 */
5040#define FDCAN_TTIR_IWT FDCAN_TTIR_IWT_Msk /*!<Initialization Watch Trigger */
5041#define FDCAN_TTIR_WT_Pos (16U)
5042#define FDCAN_TTIR_WT_Msk (0x1UL << FDCAN_TTIR_WT_Pos) /*!< 0x00010000 */
5043#define FDCAN_TTIR_WT FDCAN_TTIR_WT_Msk /*!<Watch Trigger */
5044#define FDCAN_TTIR_AW_Pos (17U)
5045#define FDCAN_TTIR_AW_Msk (0x1UL << FDCAN_TTIR_AW_Pos) /*!< 0x00020000 */
5046#define FDCAN_TTIR_AW FDCAN_TTIR_AW_Msk /*!<Application Watchdog */
5047#define FDCAN_TTIR_CER_Pos (18U)
5048#define FDCAN_TTIR_CER_Msk (0x1UL << FDCAN_TTIR_CER_Pos) /*!< 0x00040000 */
5049#define FDCAN_TTIR_CER FDCAN_TTIR_CER_Msk /*!<Configuration Error */
5050
5051/***************** Bit definition for FDCAN_TTIE register ********************/
5052#define FDCAN_TTIE_SBCE_Pos (0U)
5053#define FDCAN_TTIE_SBCE_Msk (0x1UL << FDCAN_TTIE_SBCE_Pos) /*!< 0x00000001 */
5054#define FDCAN_TTIE_SBCE FDCAN_TTIE_SBCE_Msk /*!<Start of Basic Cycle Interrupt Enable */
5055#define FDCAN_TTIE_SMCE_Pos (1U)
5056#define FDCAN_TTIE_SMCE_Msk (0x1UL << FDCAN_TTIE_SMCE_Pos) /*!< 0x00000002 */
5057#define FDCAN_TTIE_SMCE FDCAN_TTIE_SMCE_Msk /*!<Start of Matrix Cycle Interrupt Enable */
5058#define FDCAN_TTIE_CSME_Pos (2U)
5059#define FDCAN_TTIE_CSME_Msk (0x1UL << FDCAN_TTIE_CSME_Pos) /*!< 0x00000004 */
5060#define FDCAN_TTIE_CSME FDCAN_TTIE_CSME_Msk /*!<Change of Synchronization Mode Interrupt Enable */
5061#define FDCAN_TTIE_SOGE_Pos (3U)
5062#define FDCAN_TTIE_SOGE_Msk (0x1UL << FDCAN_TTIE_SOGE_Pos) /*!< 0x00000008 */
5063#define FDCAN_TTIE_SOGE FDCAN_TTIE_SOGE_Msk /*!<Start of Gap Interrupt Enable */
5064#define FDCAN_TTIE_RTMIE_Pos (4U)
5065#define FDCAN_TTIE_RTMIE_Msk (0x1UL << FDCAN_TTIE_RTMIE_Pos) /*!< 0x00000010 */
5066#define FDCAN_TTIE_RTMIE FDCAN_TTIE_RTMIE_Msk /*!<Register Time Mark Interrupt Interrupt Enable */
5067#define FDCAN_TTIE_TTMIE_Pos (5U)
5068#define FDCAN_TTIE_TTMIE_Msk (0x1UL << FDCAN_TTIE_TTMIE_Pos) /*!< 0x00000020 */
5069#define FDCAN_TTIE_TTMIE FDCAN_TTIE_TTMIE_Msk /*!<Trigger Time Mark Event Internal Interrupt Enable */
5070#define FDCAN_TTIE_SWEE_Pos (6U)
5071#define FDCAN_TTIE_SWEE_Msk (0x1UL << FDCAN_TTIE_SWEE_Pos) /*!< 0x00000040 */
5072#define FDCAN_TTIE_SWEE FDCAN_TTIE_SWEE_Msk /*!<Stop Watch Event Interrupt Enable */
5073#define FDCAN_TTIE_GTWE_Pos (7U)
5074#define FDCAN_TTIE_GTWE_Msk (0x1UL << FDCAN_TTIE_GTWE_Pos) /*!< 0x00000080 */
5075#define FDCAN_TTIE_GTWE FDCAN_TTIE_GTWE_Msk /*!<Global Time Wrap Interrupt Enable */
5076#define FDCAN_TTIE_GTDE_Pos (8U)
5077#define FDCAN_TTIE_GTDE_Msk (0x1UL << FDCAN_TTIE_GTDE_Pos) /*!< 0x00000100 */
5078#define FDCAN_TTIE_GTDE FDCAN_TTIE_GTDE_Msk /*!<Global Time Discontinuity Interrupt Enable */
5079#define FDCAN_TTIE_GTEE_Pos (9U)
5080#define FDCAN_TTIE_GTEE_Msk (0x1UL << FDCAN_TTIE_GTEE_Pos) /*!< 0x00000200 */
5081#define FDCAN_TTIE_GTEE FDCAN_TTIE_GTEE_Msk /*!<Global Time Error Interrupt Enable */
5082#define FDCAN_TTIE_TXUE_Pos (10U)
5083#define FDCAN_TTIE_TXUE_Msk (0x1UL << FDCAN_TTIE_TXUE_Pos) /*!< 0x00000400 */
5084#define FDCAN_TTIE_TXUE FDCAN_TTIE_TXUE_Msk /*!<Tx Count Underflow Interrupt Enable */
5085#define FDCAN_TTIE_TXOE_Pos (11U)
5086#define FDCAN_TTIE_TXOE_Msk (0x1UL << FDCAN_TTIE_TXOE_Pos) /*!< 0x00000800 */
5087#define FDCAN_TTIE_TXOE FDCAN_TTIE_TXOE_Msk /*!<Tx Count Overflow Interrupt Enable */
5088#define FDCAN_TTIE_SE1E_Pos (12U)
5089#define FDCAN_TTIE_SE1E_Msk (0x1UL << FDCAN_TTIE_SE1E_Pos) /*!< 0x00001000 */
5090#define FDCAN_TTIE_SE1E FDCAN_TTIE_SE1E_Msk /*!<Scheduling Error 1 Interrupt Enable */
5091#define FDCAN_TTIE_SE2E_Pos (13U)
5092#define FDCAN_TTIE_SE2E_Msk (0x1UL << FDCAN_TTIE_SE2E_Pos) /*!< 0x00002000 */
5093#define FDCAN_TTIE_SE2E FDCAN_TTIE_SE2E_Msk /*!<Scheduling Error 2 Interrupt Enable */
5094#define FDCAN_TTIE_ELCE_Pos (14U)
5095#define FDCAN_TTIE_ELCE_Msk (0x1UL << FDCAN_TTIE_ELCE_Pos) /*!< 0x00004000 */
5096#define FDCAN_TTIE_ELCE FDCAN_TTIE_ELCE_Msk /*!<Error Level Changed Interrupt Enable */
5097#define FDCAN_TTIE_IWTE_Pos (15U)
5098#define FDCAN_TTIE_IWTE_Msk (0x1UL << FDCAN_TTIE_IWTE_Pos) /*!< 0x00008000 */
5099#define FDCAN_TTIE_IWTE FDCAN_TTIE_IWTE_Msk /*!<Initialization Watch Trigger Interrupt Enable */
5100#define FDCAN_TTIE_WTE_Pos (16U)
5101#define FDCAN_TTIE_WTE_Msk (0x1UL << FDCAN_TTIE_WTE_Pos) /*!< 0x00010000 */
5102#define FDCAN_TTIE_WTE FDCAN_TTIE_WTE_Msk /*!<Watch Trigger Interrupt Enable */
5103#define FDCAN_TTIE_AWE_Pos (17U)
5104#define FDCAN_TTIE_AWE_Msk (0x1UL << FDCAN_TTIE_AWE_Pos) /*!< 0x00020000 */
5105#define FDCAN_TTIE_AWE FDCAN_TTIE_AWE_Msk /*!<Application Watchdog Interrupt Enable */
5106#define FDCAN_TTIE_CERE_Pos (18U)
5107#define FDCAN_TTIE_CERE_Msk (0x1UL << FDCAN_TTIE_CERE_Pos) /*!< 0x00040000 */
5108#define FDCAN_TTIE_CERE FDCAN_TTIE_CERE_Msk /*!<Configuration Error Interrupt Enable */
5109
5110/***************** Bit definition for FDCAN_TTILS register ********************/
5111#define FDCAN_TTILS_SBCS_Pos (0U)
5112#define FDCAN_TTILS_SBCS_Msk (0x1UL << FDCAN_TTILS_SBCS_Pos) /*!< 0x00000001 */
5113#define FDCAN_TTILS_SBCS FDCAN_TTILS_SBCS_Msk /*!<Start of Basic Cycle Interrupt Line */
5114#define FDCAN_TTILS_SMCS_Pos (1U)
5115#define FDCAN_TTILS_SMCS_Msk (0x1UL << FDCAN_TTILS_SMCS_Pos) /*!< 0x00000002 */
5116#define FDCAN_TTILS_SMCS FDCAN_TTILS_SMCS_Msk /*!<Start of Matrix Cycle Interrupt Line */
5117#define FDCAN_TTILS_CSMS_Pos (2U)
5118#define FDCAN_TTILS_CSMS_Msk (0x1UL << FDCAN_TTILS_CSMS_Pos) /*!< 0x00000004 */
5119#define FDCAN_TTILS_CSMS FDCAN_TTILS_CSMS_Msk /*!<Change of Synchronization Mode Interrupt Line */
5120#define FDCAN_TTILS_SOGS_Pos (3U)
5121#define FDCAN_TTILS_SOGS_Msk (0x1UL << FDCAN_TTILS_SOGS_Pos) /*!< 0x00000008 */
5122#define FDCAN_TTILS_SOGS FDCAN_TTILS_SOGS_Msk /*!<Start of Gap Interrupt Line */
5123#define FDCAN_TTILS_RTMIS_Pos (4U)
5124#define FDCAN_TTILS_RTMIS_Msk (0x1UL << FDCAN_TTILS_RTMIS_Pos) /*!< 0x00000010 */
5125#define FDCAN_TTILS_RTMIS FDCAN_TTILS_RTMIS_Msk /*!<Register Time Mark Interrupt Interrupt Line */
5126#define FDCAN_TTILS_TTMIS_Pos (5U)
5127#define FDCAN_TTILS_TTMIS_Msk (0x1UL << FDCAN_TTILS_TTMIS_Pos) /*!< 0x00000020 */
5128#define FDCAN_TTILS_TTMIS FDCAN_TTILS_TTMIS_Msk /*!<Trigger Time Mark Event Internal Interrupt Line */
5129#define FDCAN_TTILS_SWES_Pos (6U)
5130#define FDCAN_TTILS_SWES_Msk (0x1UL << FDCAN_TTILS_SWES_Pos) /*!< 0x00000040 */
5131#define FDCAN_TTILS_SWES FDCAN_TTILS_SWES_Msk /*!<Stop Watch Event Interrupt Line */
5132#define FDCAN_TTILS_GTWS_Pos (7U)
5133#define FDCAN_TTILS_GTWS_Msk (0x1UL << FDCAN_TTILS_GTWS_Pos) /*!< 0x00000080 */
5134#define FDCAN_TTILS_GTWS FDCAN_TTILS_GTWS_Msk /*!<Global Time Wrap Interrupt Line */
5135#define FDCAN_TTILS_GTDS_Pos (8U)
5136#define FDCAN_TTILS_GTDS_Msk (0x1UL << FDCAN_TTILS_GTDS_Pos) /*!< 0x00000100 */
5137#define FDCAN_TTILS_GTDS FDCAN_TTILS_GTDS_Msk /*!<Global Time Discontinuity Interrupt Line */
5138#define FDCAN_TTILS_GTES_Pos (9U)
5139#define FDCAN_TTILS_GTES_Msk (0x1UL << FDCAN_TTILS_GTES_Pos) /*!< 0x00000200 */
5140#define FDCAN_TTILS_GTES FDCAN_TTILS_GTES_Msk /*!<Global Time Error Interrupt Line */
5141#define FDCAN_TTILS_TXUS_Pos (10U)
5142#define FDCAN_TTILS_TXUS_Msk (0x1UL << FDCAN_TTILS_TXUS_Pos) /*!< 0x00000400 */
5143#define FDCAN_TTILS_TXUS FDCAN_TTILS_TXUS_Msk /*!<Tx Count Underflow Interrupt Line */
5144#define FDCAN_TTILS_TXOS_Pos (11U)
5145#define FDCAN_TTILS_TXOS_Msk (0x1UL << FDCAN_TTILS_TXOS_Pos) /*!< 0x00000800 */
5146#define FDCAN_TTILS_TXOS FDCAN_TTILS_TXOS_Msk /*!<Tx Count Overflow Interrupt Line */
5147#define FDCAN_TTILS_SE1S_Pos (12U)
5148#define FDCAN_TTILS_SE1S_Msk (0x1UL << FDCAN_TTILS_SE1S_Pos) /*!< 0x00001000 */
5149#define FDCAN_TTILS_SE1S FDCAN_TTILS_SE1S_Msk /*!<Scheduling Error 1 Interrupt Line */
5150#define FDCAN_TTILS_SE2S_Pos (13U)
5151#define FDCAN_TTILS_SE2S_Msk (0x1UL << FDCAN_TTILS_SE2S_Pos) /*!< 0x00002000 */
5152#define FDCAN_TTILS_SE2S FDCAN_TTILS_SE2S_Msk /*!<Scheduling Error 2 Interrupt Line */
5153#define FDCAN_TTILS_ELCS_Pos (14U)
5154#define FDCAN_TTILS_ELCS_Msk (0x1UL << FDCAN_TTILS_ELCS_Pos) /*!< 0x00004000 */
5155#define FDCAN_TTILS_ELCS FDCAN_TTILS_ELCS_Msk /*!<Error Level Changed Interrupt Line */
5156#define FDCAN_TTILS_IWTS_Pos (15U)
5157#define FDCAN_TTILS_IWTS_Msk (0x1UL << FDCAN_TTILS_IWTS_Pos) /*!< 0x00008000 */
5158#define FDCAN_TTILS_IWTS FDCAN_TTILS_IWTS_Msk /*!<Initialization Watch Trigger Interrupt Line */
5159#define FDCAN_TTILS_WTS_Pos (16U)
5160#define FDCAN_TTILS_WTS_Msk (0x1UL << FDCAN_TTILS_WTS_Pos) /*!< 0x00010000 */
5161#define FDCAN_TTILS_WTS FDCAN_TTILS_WTS_Msk /*!<Watch Trigger Interrupt Line */
5162#define FDCAN_TTILS_AWS_Pos (17U)
5163#define FDCAN_TTILS_AWS_Msk (0x1UL << FDCAN_TTILS_AWS_Pos) /*!< 0x00020000 */
5164#define FDCAN_TTILS_AWS FDCAN_TTILS_AWS_Msk /*!<Application Watchdog Interrupt Line */
5165#define FDCAN_TTILS_CERS_Pos (18U)
5166#define FDCAN_TTILS_CERS_Msk (0x1UL << FDCAN_TTILS_CERS_Pos) /*!< 0x00040000 */
5167#define FDCAN_TTILS_CERS FDCAN_TTILS_CERS_Msk /*!<Configuration Error Interrupt Line */
5168
5169/***************** Bit definition for FDCAN_TTOST register ********************/
5170#define FDCAN_TTOST_EL_Pos (0U)
5171#define FDCAN_TTOST_EL_Msk (0x3UL << FDCAN_TTOST_EL_Pos) /*!< 0x00000003 */
5172#define FDCAN_TTOST_EL FDCAN_TTOST_EL_Msk /*!<Error Level */
5173#define FDCAN_TTOST_MS_Pos (2U)
5174#define FDCAN_TTOST_MS_Msk (0x3UL << FDCAN_TTOST_MS_Pos) /*!< 0x0000000C */
5175#define FDCAN_TTOST_MS FDCAN_TTOST_MS_Msk /*!<Master State */
5176#define FDCAN_TTOST_SYS_Pos (4U)
5177#define FDCAN_TTOST_SYS_Msk (0x3UL << FDCAN_TTOST_SYS_Pos) /*!< 0x00000030 */
5178#define FDCAN_TTOST_SYS FDCAN_TTOST_SYS_Msk /*!<Synchronization State */
5179#define FDCAN_TTOST_QGTP_Pos (6U)
5180#define FDCAN_TTOST_QGTP_Msk (0x1UL << FDCAN_TTOST_QGTP_Pos) /*!< 0x00000040 */
5181#define FDCAN_TTOST_QGTP FDCAN_TTOST_QGTP_Msk /*!<Quality of Global Time Phase */
5182#define FDCAN_TTOST_QCS_Pos (7U)
5183#define FDCAN_TTOST_QCS_Msk (0x1UL << FDCAN_TTOST_QCS_Pos) /*!< 0x00000080 */
5184#define FDCAN_TTOST_QCS FDCAN_TTOST_QCS_Msk /*!<Quality of Clock Speed */
5185#define FDCAN_TTOST_RTO_Pos (8U)
5186#define FDCAN_TTOST_RTO_Msk (0xFFUL << FDCAN_TTOST_RTO_Pos) /*!< 0x0000FF00 */
5187#define FDCAN_TTOST_RTO FDCAN_TTOST_RTO_Msk /*!<Reference Trigger Offset */
5188#define FDCAN_TTOST_WGTD_Pos (22U)
5189#define FDCAN_TTOST_WGTD_Msk (0x1UL << FDCAN_TTOST_WGTD_Pos) /*!< 0x00400000 */
5190#define FDCAN_TTOST_WGTD FDCAN_TTOST_WGTD_Msk /*!<Wait for Global Time Discontinuity */
5191#define FDCAN_TTOST_GFI_Pos (23U)
5192#define FDCAN_TTOST_GFI_Msk (0x1UL << FDCAN_TTOST_GFI_Pos) /*!< 0x00800000 */
5193#define FDCAN_TTOST_GFI FDCAN_TTOST_GFI_Msk /*!<Gap Finished Indicator */
5194#define FDCAN_TTOST_TMP_Pos (24U)
5195#define FDCAN_TTOST_TMP_Msk (0x7UL << FDCAN_TTOST_TMP_Pos) /*!< 0x07000000 */
5196#define FDCAN_TTOST_TMP FDCAN_TTOST_TMP_Msk /*!<Time Master Priority */
5197#define FDCAN_TTOST_GSI_Pos (27U)
5198#define FDCAN_TTOST_GSI_Msk (0x1UL << FDCAN_TTOST_GSI_Pos) /*!< 0x08000000 */
5199#define FDCAN_TTOST_GSI FDCAN_TTOST_GSI_Msk /*!<Gap Started Indicator */
5200#define FDCAN_TTOST_WFE_Pos (28U)
5201#define FDCAN_TTOST_WFE_Msk (0x1UL << FDCAN_TTOST_WFE_Pos) /*!< 0x10000000 */
5202#define FDCAN_TTOST_WFE FDCAN_TTOST_WFE_Msk /*!<Wait for Event */
5203#define FDCAN_TTOST_AWE_Pos (29U)
5204#define FDCAN_TTOST_AWE_Msk (0x1UL << FDCAN_TTOST_AWE_Pos) /*!< 0x20000000 */
5205#define FDCAN_TTOST_AWE FDCAN_TTOST_AWE_Msk /*!<Application Watchdog Event */
5206#define FDCAN_TTOST_WECS_Pos (30U)
5207#define FDCAN_TTOST_WECS_Msk (0x1UL << FDCAN_TTOST_WECS_Pos) /*!< 0x40000000 */
5208#define FDCAN_TTOST_WECS FDCAN_TTOST_WECS_Msk /*!<Wait for External Clock Synchronization */
5209#define FDCAN_TTOST_SPL_Pos (31U)
5210#define FDCAN_TTOST_SPL_Msk (0x1UL << FDCAN_TTOST_SPL_Pos) /*!< 0x80000000 */
5211#define FDCAN_TTOST_SPL FDCAN_TTOST_SPL_Msk /*!<Schedule Phase Lock */
5212
5213/***************** Bit definition for FDCAN_TURNA register ********************/
5214#define FDCAN_TURNA_NAV_Pos (0U)
5215#define FDCAN_TURNA_NAV_Msk (0x3FFFFUL << FDCAN_TURNA_NAV_Pos) /*!< 0x0003FFFF */
5216#define FDCAN_TURNA_NAV FDCAN_TURNA_NAV_Msk /*!<Numerator Actual Value */
5217
5218/***************** Bit definition for FDCAN_TTLGT register ********************/
5219#define FDCAN_TTLGT_LT_Pos (0U)
5220#define FDCAN_TTLGT_LT_Msk (0xFFFFUL << FDCAN_TTLGT_LT_Pos) /*!< 0x0000FFFF */
5221#define FDCAN_TTLGT_LT FDCAN_TTLGT_LT_Msk /*!<Local Time */
5222#define FDCAN_TTLGT_GT_Pos (16U)
5223#define FDCAN_TTLGT_GT_Msk (0xFFFFUL << FDCAN_TTLGT_GT_Pos) /*!< 0xFFFF0000 */
5224#define FDCAN_TTLGT_GT FDCAN_TTLGT_GT_Msk /*!<Global Time */
5225
5226/***************** Bit definition for FDCAN_TTCTC register ********************/
5227#define FDCAN_TTCTC_CT_Pos (0U)
5228#define FDCAN_TTCTC_CT_Msk (0xFFFFUL << FDCAN_TTCTC_CT_Pos) /*!< 0x0000FFFF */
5229#define FDCAN_TTCTC_CT FDCAN_TTCTC_CT_Msk /*!<Cycle Time */
5230#define FDCAN_TTCTC_CC_Pos (16U)
5231#define FDCAN_TTCTC_CC_Msk (0x3FUL << FDCAN_TTCTC_CC_Pos) /*!< 0x003F0000 */
5232#define FDCAN_TTCTC_CC FDCAN_TTCTC_CC_Msk /*!<Cycle Count */
5233
5234/***************** Bit definition for FDCAN_TTCPT register ********************/
5235#define FDCAN_TTCPT_CCV_Pos (0U)
5236#define FDCAN_TTCPT_CCV_Msk (0x3FUL << FDCAN_TTCPT_CCV_Pos) /*!< 0x0000003F */
5237#define FDCAN_TTCPT_CCV FDCAN_TTCPT_CCV_Msk /*!<Cycle Count Value */
5238#define FDCAN_TTCPT_SWV_Pos (16U)
5239#define FDCAN_TTCPT_SWV_Msk (0xFFFFUL << FDCAN_TTCPT_SWV_Pos) /*!< 0xFFFF0000 */
5240#define FDCAN_TTCPT_SWV FDCAN_TTCPT_SWV_Msk /*!<Stop Watch Value */
5241
5242/***************** Bit definition for FDCAN_TTCSM register ********************/
5243#define FDCAN_TTCSM_CSM_Pos (0U)
5244#define FDCAN_TTCSM_CSM_Msk (0xFFFFUL << FDCAN_TTCSM_CSM_Pos) /*!< 0x0000FFFF */
5245#define FDCAN_TTCSM_CSM FDCAN_TTCSM_CSM_Msk /*!<Cycle Sync Mark */
5246
5247/***************** Bit definition for FDCAN_TTTS register *********************/
5248#define FDCAN_TTTS_SWTSEL_Pos (0U)
5249#define FDCAN_TTTS_SWTSEL_Msk (0x3UL << FDCAN_TTTS_SWTSEL_Pos) /*!< 0x00000003 */
5250#define FDCAN_TTTS_SWTSEL FDCAN_TTTS_SWTSEL_Msk /*!<Stop watch trigger input selection */
5251#define FDCAN_TTTS_EVTSEL_Pos (4U)
5252#define FDCAN_TTTS_EVTSEL_Msk (0x3UL << FDCAN_TTTS_EVTSEL_Pos) /*!< 0x00000030 */
5253#define FDCAN_TTTS_EVTSEL FDCAN_TTTS_EVTSEL_Msk /*!<Event trigger input selection */
5254
5255/********************************************************************************/
5256/* */
5257/* FDCANCCU (Clock Calibration unit) */
5258/* */
5259/********************************************************************************/
5260
5261/***************** Bit definition for FDCANCCU_CREL register ******************/
5262#define FDCANCCU_CREL_DAY_Pos (0U)
5263#define FDCANCCU_CREL_DAY_Msk (0xFFUL << FDCANCCU_CREL_DAY_Pos) /*!< 0x000000FF */
5264#define FDCANCCU_CREL_DAY FDCANCCU_CREL_DAY_Msk /*!<Timestamp Day */
5265#define FDCANCCU_CREL_MON_Pos (8U)
5266#define FDCANCCU_CREL_MON_Msk (0xFFUL << FDCANCCU_CREL_MON_Pos) /*!< 0x0000FF00 */
5267#define FDCANCCU_CREL_MON FDCANCCU_CREL_MON_Msk /*!<Timestamp Month */
5268#define FDCANCCU_CREL_YEAR_Pos (16U)
5269#define FDCANCCU_CREL_YEAR_Msk (0xFUL << FDCANCCU_CREL_YEAR_Pos) /*!< 0x000F0000 */
5270#define FDCANCCU_CREL_YEAR FDCANCCU_CREL_YEAR_Msk /*!<Timestamp Year */
5271#define FDCANCCU_CREL_SUBSTEP_Pos (20U)
5272#define FDCANCCU_CREL_SUBSTEP_Msk (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
5273#define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
5274#define FDCANCCU_CREL_STEP_Pos (24U)
5275#define FDCANCCU_CREL_STEP_Msk (0xFUL << FDCANCCU_CREL_STEP_Pos) /*!< 0x0F000000 */
5276#define FDCANCCU_CREL_STEP FDCANCCU_CREL_STEP_Msk /*!<Step of Core release */
5277#define FDCANCCU_CREL_REL_Pos (28U)
5278#define FDCANCCU_CREL_REL_Msk (0xFUL << FDCANCCU_CREL_REL_Pos) /*!< 0xF0000000 */
5279#define FDCANCCU_CREL_REL FDCANCCU_CREL_REL_Msk /*!<Core release */
5280
5281/***************** Bit definition for FDCANCCU_CCFG register ******************/
5282#define FDCANCCU_CCFG_TQBT_Pos (0U)
5283#define FDCANCCU_CCFG_TQBT_Msk (0x1FUL << FDCANCCU_CCFG_TQBT_Pos) /*!< 0x0000001F */
5284#define FDCANCCU_CCFG_TQBT FDCANCCU_CCFG_TQBT_Msk /*!<Time Quanta per Bit Time */
5285#define FDCANCCU_CCFG_BCC_Pos (6U)
5286#define FDCANCCU_CCFG_BCC_Msk (0x1UL << FDCANCCU_CCFG_BCC_Pos) /*!< 0x00000040 */
5287#define FDCANCCU_CCFG_BCC FDCANCCU_CCFG_BCC_Msk /*!<Bypass Clock Calibration */
5288#define FDCANCCU_CCFG_CFL_Pos (7U)
5289#define FDCANCCU_CCFG_CFL_Msk (0x1UL << FDCANCCU_CCFG_CFL_Pos) /*!< 0x00000080 */
5290#define FDCANCCU_CCFG_CFL FDCANCCU_CCFG_CFL_Msk /*!<Calibration Field Length */
5291#define FDCANCCU_CCFG_OCPM_Pos (8U)
5292#define FDCANCCU_CCFG_OCPM_Msk (0xFFUL << FDCANCCU_CCFG_OCPM_Pos) /*!< 0x0000FF00 */
5293#define FDCANCCU_CCFG_OCPM FDCANCCU_CCFG_OCPM_Msk /*!<Oscillator Clock Periods Minimum */
5294#define FDCANCCU_CCFG_CDIV_Pos (16U)
5295#define FDCANCCU_CCFG_CDIV_Msk (0xFUL << FDCANCCU_CCFG_CDIV_Pos) /*!< 0x000F0000 */
5296#define FDCANCCU_CCFG_CDIV FDCANCCU_CCFG_CDIV_Msk /*!<Clock Divider */
5297#define FDCANCCU_CCFG_SWR_Pos (31U)
5298#define FDCANCCU_CCFG_SWR_Msk (0x1UL << FDCANCCU_CCFG_SWR_Pos) /*!< 0x80000000 */
5299#define FDCANCCU_CCFG_SWR FDCANCCU_CCFG_SWR_Msk /*!<Software Reset */
5300
5301/***************** Bit definition for FDCANCCU_CSTAT register *****************/
5302#define FDCANCCU_CSTAT_OCPC_Pos (0U)
5303#define FDCANCCU_CSTAT_OCPC_Msk (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos) /*!< 0x0003FFFF */
5304#define FDCANCCU_CSTAT_OCPC FDCANCCU_CSTAT_OCPC_Msk /*!<Oscillator Clock Period Counter */
5305#define FDCANCCU_CSTAT_TQC_Pos (18U)
5306#define FDCANCCU_CSTAT_TQC_Msk (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos) /*!< 0x1FFC0000 */
5307#define FDCANCCU_CSTAT_TQC FDCANCCU_CSTAT_TQC_Msk /*!<Time Quanta Counter */
5308#define FDCANCCU_CSTAT_CALS_Pos (30U)
5309#define FDCANCCU_CSTAT_CALS_Msk (0x3UL << FDCANCCU_CSTAT_CALS_Pos) /*!< 0xC0000000 */
5310#define FDCANCCU_CSTAT_CALS FDCANCCU_CSTAT_CALS_Msk /*!<Calibration State */
5311
5312/****************** Bit definition for FDCANCCU_CWD register ******************/
5313#define FDCANCCU_CWD_WDC_Pos (0U)
5314#define FDCANCCU_CWD_WDC_Msk (0xFFFFUL << FDCANCCU_CWD_WDC_Pos) /*!< 0x0000FFFF */
5315#define FDCANCCU_CWD_WDC FDCANCCU_CWD_WDC_Msk /*!<Watchdog Configuration */
5316#define FDCANCCU_CWD_WDV_Pos (16U)
5317#define FDCANCCU_CWD_WDV_Msk (0xFFFFUL << FDCANCCU_CWD_WDV_Pos) /*!< 0xFFFF0000 */
5318#define FDCANCCU_CWD_WDV FDCANCCU_CWD_WDV_Msk /*!<Watchdog Value */
5319
5320/****************** Bit definition for FDCANCCU_IR register *******************/
5321#define FDCANCCU_IR_CWE_Pos (0U)
5322#define FDCANCCU_IR_CWE_Msk (0x1UL << FDCANCCU_IR_CWE_Pos) /*!< 0x00000001 */
5323#define FDCANCCU_IR_CWE FDCANCCU_IR_CWE_Msk /*!<Calibration Watchdog Event */
5324#define FDCANCCU_IR_CSC_Pos (1U)
5325#define FDCANCCU_IR_CSC_Msk (0x1UL << FDCANCCU_IR_CSC_Pos) /*!< 0x00000002 */
5326#define FDCANCCU_IR_CSC FDCANCCU_IR_CSC_Msk /*!<Calibration State Changed */
5327
5328/****************** Bit definition for FDCANCCU_IE register *******************/
5329#define FDCANCCU_IE_CWEE_Pos (0U)
5330#define FDCANCCU_IE_CWEE_Msk (0x1UL << FDCANCCU_IE_CWEE_Pos) /*!< 0x00000001 */
5331#define FDCANCCU_IE_CWEE FDCANCCU_IE_CWEE_Msk /*!<Calibration Watchdog Event Enable */
5332#define FDCANCCU_IE_CSCE_Pos (1U)
5333#define FDCANCCU_IE_CSCE_Msk (0x1UL << FDCANCCU_IE_CSCE_Pos) /*!< 0x00000002 */
5334#define FDCANCCU_IE_CSCE FDCANCCU_IE_CSCE_Msk /*!<Calibration State Changed Enable */
5335
5336/******************************************************************************/
5337/* */
5338/* HDMI-CEC (CEC) */
5339/* */
5340/******************************************************************************/
5341
5342/******************* Bit definition for CEC_CR register *********************/
5343#define CEC_CR_CECEN_Pos (0U)
5344#define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
5345#define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
5346#define CEC_CR_TXSOM_Pos (1U)
5347#define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
5348#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
5349#define CEC_CR_TXEOM_Pos (2U)
5350#define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
5351#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
5352
5353/******************* Bit definition for CEC_CFGR register *******************/
5354#define CEC_CFGR_SFT_Pos (0U)
5355#define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
5356#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
5357#define CEC_CFGR_RXTOL_Pos (3U)
5358#define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
5359#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
5360#define CEC_CFGR_BRESTP_Pos (4U)
5361#define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
5362#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
5363#define CEC_CFGR_BREGEN_Pos (5U)
5364#define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
5365#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
5366#define CEC_CFGR_LBPEGEN_Pos (6U)
5367#define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
5368#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error generation */
5369#define CEC_CFGR_SFTOPT_Pos (8U)
5370#define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
5371#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
5372#define CEC_CFGR_BRDNOGEN_Pos (7U)
5373#define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
5374#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No error generation */
5375#define CEC_CFGR_OAR_Pos (16U)
5376#define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
5377#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
5378#define CEC_CFGR_LSTN_Pos (31U)
5379#define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
5380#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
5381
5382/******************* Bit definition for CEC_TXDR register *******************/
5383#define CEC_TXDR_TXD_Pos (0U)
5384#define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
5385#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
5386
5387/******************* Bit definition for CEC_RXDR register *******************/
5388#define CEC_RXDR_RXD_Pos (0U)
5389#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */
5390#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */
5391
5392/******************* Bit definition for CEC_ISR register ********************/
5393#define CEC_ISR_RXBR_Pos (0U)
5394#define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
5395#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
5396#define CEC_ISR_RXEND_Pos (1U)
5397#define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
5398#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
5399#define CEC_ISR_RXOVR_Pos (2U)
5400#define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
5401#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
5402#define CEC_ISR_BRE_Pos (3U)
5403#define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
5404#define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
5405#define CEC_ISR_SBPE_Pos (4U)
5406#define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
5407#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
5408#define CEC_ISR_LBPE_Pos (5U)
5409#define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
5410#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
5411#define CEC_ISR_RXACKE_Pos (6U)
5412#define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
5413#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
5414#define CEC_ISR_ARBLST_Pos (7U)
5415#define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
5416#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
5417#define CEC_ISR_TXBR_Pos (8U)
5418#define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
5419#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
5420#define CEC_ISR_TXEND_Pos (9U)
5421#define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
5422#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
5423#define CEC_ISR_TXUDR_Pos (10U)
5424#define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
5425#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
5426#define CEC_ISR_TXERR_Pos (11U)
5427#define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
5428#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
5429#define CEC_ISR_TXACKE_Pos (12U)
5430#define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
5431#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
5432
5433/******************* Bit definition for CEC_IER register ********************/
5434#define CEC_IER_RXBRIE_Pos (0U)
5435#define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
5436#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
5437#define CEC_IER_RXENDIE_Pos (1U)
5438#define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
5439#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
5440#define CEC_IER_RXOVRIE_Pos (2U)
5441#define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
5442#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
5443#define CEC_IER_BREIE_Pos (3U)
5444#define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
5445#define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
5446#define CEC_IER_SBPEIE_Pos (4U)
5447#define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
5448#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable */
5449#define CEC_IER_LBPEIE_Pos (5U)
5450#define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
5451#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
5452#define CEC_IER_RXACKEIE_Pos (6U)
5453#define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
5454#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
5455#define CEC_IER_ARBLSTIE_Pos (7U)
5456#define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
5457#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
5458#define CEC_IER_TXBRIE_Pos (8U)
5459#define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
5460#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
5461#define CEC_IER_TXENDIE_Pos (9U)
5462#define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
5463#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
5464#define CEC_IER_TXUDRIE_Pos (10U)
5465#define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
5466#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
5467#define CEC_IER_TXERRIE_Pos (11U)
5468#define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
5469#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
5470#define CEC_IER_TXACKEIE_Pos (12U)
5471#define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
5472#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
5473
5474/******************************************************************************/
5475/* */
5476/* CRC calculation unit */
5477/* */
5478/******************************************************************************/
5479/******************* Bit definition for CRC_DR register *********************/
5480#define CRC_DR_DR_Pos (0U)
5481#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
5482#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
5483
5484/******************* Bit definition for CRC_IDR register ********************/
5485#define CRC_IDR_IDR_Pos (0U)
5486#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
5487#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
5488
5489/******************** Bit definition for CRC_CR register ********************/
5490#define CRC_CR_RESET_Pos (0U)
5491#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
5492#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
5493#define CRC_CR_POLYSIZE_Pos (3U)
5494#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
5495#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
5496#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
5497#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
5498#define CRC_CR_REV_IN_Pos (5U)
5499#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
5500#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
5501#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
5502#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
5503#define CRC_CR_REV_OUT_Pos (7U)
5504#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
5505#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
5506
5507/******************* Bit definition for CRC_INIT register *******************/
5508#define CRC_INIT_INIT_Pos (0U)
5509#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
5510#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
5511
5512/******************* Bit definition for CRC_POL register ********************/
5513#define CRC_POL_POL_Pos (0U)
5514#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
5515#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
5516
5517/******************************************************************************/
5518/* */
5519/* CRS Clock Recovery System */
5520/******************************************************************************/
5521
5522/******************* Bit definition for CRS_CR register *********************/
5523#define CRS_CR_SYNCOKIE_Pos (0U)
5524#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
5525#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
5526#define CRS_CR_SYNCWARNIE_Pos (1U)
5527#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
5528#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
5529#define CRS_CR_ERRIE_Pos (2U)
5530#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
5531#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
5532#define CRS_CR_ESYNCIE_Pos (3U)
5533#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
5534#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
5535#define CRS_CR_CEN_Pos (5U)
5536#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
5537#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
5538#define CRS_CR_AUTOTRIMEN_Pos (6U)
5539#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
5540#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
5541#define CRS_CR_SWSYNC_Pos (7U)
5542#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
5543#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
5544#define CRS_CR_TRIM_Pos (8U)
5545#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
5546#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
5547
5548/******************* Bit definition for CRS_CFGR register *********************/
5549#define CRS_CFGR_RELOAD_Pos (0U)
5550#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
5551#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
5552#define CRS_CFGR_FELIM_Pos (16U)
5553#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
5554#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
5555
5556#define CRS_CFGR_SYNCDIV_Pos (24U)
5557#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
5558#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
5559#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
5560#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
5561#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
5562
5563#define CRS_CFGR_SYNCSRC_Pos (28U)
5564#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
5565#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
5566#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
5567#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
5568
5569#define CRS_CFGR_SYNCPOL_Pos (31U)
5570#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
5571#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
5572
5573/******************* Bit definition for CRS_ISR register *********************/
5574#define CRS_ISR_SYNCOKF_Pos (0U)
5575#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
5576#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
5577#define CRS_ISR_SYNCWARNF_Pos (1U)
5578#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
5579#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
5580#define CRS_ISR_ERRF_Pos (2U)
5581#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
5582#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
5583#define CRS_ISR_ESYNCF_Pos (3U)
5584#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
5585#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
5586#define CRS_ISR_SYNCERR_Pos (8U)
5587#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
5588#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
5589#define CRS_ISR_SYNCMISS_Pos (9U)
5590#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
5591#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
5592#define CRS_ISR_TRIMOVF_Pos (10U)
5593#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
5594#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
5595#define CRS_ISR_FEDIR_Pos (15U)
5596#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
5597#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
5598#define CRS_ISR_FECAP_Pos (16U)
5599#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
5600#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
5601
5602/******************* Bit definition for CRS_ICR register *********************/
5603#define CRS_ICR_SYNCOKC_Pos (0U)
5604#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
5605#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
5606#define CRS_ICR_SYNCWARNC_Pos (1U)
5607#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
5608#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
5609#define CRS_ICR_ERRC_Pos (2U)
5610#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
5611#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
5612#define CRS_ICR_ESYNCC_Pos (3U)
5613#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
5614#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
5615
5616/******************************************************************************/
5617/* */
5618/* Digital to Analog Converter */
5619/* */
5620/******************************************************************************/
5621/******************** Bit definition for DAC_CR register ********************/
5622#define DAC_CR_EN1_Pos (0U)
5623#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
5624#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
5625#define DAC_CR_TEN1_Pos (1U)
5626#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
5627#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
5628
5629#define DAC_CR_TSEL1_Pos (2U)
5630#define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
5631#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5632#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
5633#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
5634#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
5635#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
5636
5637
5638#define DAC_CR_WAVE1_Pos (6U)
5639#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
5640#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5641#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
5642#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
5643
5644#define DAC_CR_MAMP1_Pos (8U)
5645#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
5646#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5647#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
5648#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
5649#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
5650#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
5651
5652#define DAC_CR_DMAEN1_Pos (12U)
5653#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
5654#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
5655#define DAC_CR_DMAUDRIE1_Pos (13U)
5656#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
5657#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
5658#define DAC_CR_CEN1_Pos (14U)
5659#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
5660#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
5661
5662#define DAC_CR_EN2_Pos (16U)
5663#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
5664#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
5665#define DAC_CR_TEN2_Pos (17U)
5666#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
5667#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
5668
5669#define DAC_CR_TSEL2_Pos (18U)
5670#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
5671#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5672#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
5673#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
5674#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
5675#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
5676
5677
5678#define DAC_CR_WAVE2_Pos (22U)
5679#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
5680#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5681#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
5682#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
5683
5684#define DAC_CR_MAMP2_Pos (24U)
5685#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
5686#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5687#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
5688#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
5689#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
5690#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
5691
5692#define DAC_CR_DMAEN2_Pos (28U)
5693#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
5694#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
5695#define DAC_CR_DMAUDRIE2_Pos (29U)
5696#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
5697#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
5698#define DAC_CR_CEN2_Pos (30U)
5699#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
5700#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
5701
5702/***************** Bit definition for DAC_SWTRIGR register ******************/
5703#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5704#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
5705#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
5706#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5707#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
5708#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
5709
5710/***************** Bit definition for DAC_DHR12R1 register ******************/
5711#define DAC_DHR12R1_DACC1DHR_Pos (0U)
5712#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
5713#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5714
5715/***************** Bit definition for DAC_DHR12L1 register ******************/
5716#define DAC_DHR12L1_DACC1DHR_Pos (4U)
5717#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5718#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5719
5720/****************** Bit definition for DAC_DHR8R1 register ******************/
5721#define DAC_DHR8R1_DACC1DHR_Pos (0U)
5722#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
5723#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5724
5725/***************** Bit definition for DAC_DHR12R2 register ******************/
5726#define DAC_DHR12R2_DACC2DHR_Pos (0U)
5727#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
5728#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5729
5730/***************** Bit definition for DAC_DHR12L2 register ******************/
5731#define DAC_DHR12L2_DACC2DHR_Pos (4U)
5732#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
5733#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5734
5735/****************** Bit definition for DAC_DHR8R2 register ******************/
5736#define DAC_DHR8R2_DACC2DHR_Pos (0U)
5737#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
5738#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5739
5740/***************** Bit definition for DAC_DHR12RD register ******************/
5741#define DAC_DHR12RD_DACC1DHR_Pos (0U)
5742#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
5743#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5744#define DAC_DHR12RD_DACC2DHR_Pos (16U)
5745#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
5746#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5747
5748/***************** Bit definition for DAC_DHR12LD register ******************/
5749#define DAC_DHR12LD_DACC1DHR_Pos (4U)
5750#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5751#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5752#define DAC_DHR12LD_DACC2DHR_Pos (20U)
5753#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
5754#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5755
5756/****************** Bit definition for DAC_DHR8RD register ******************/
5757#define DAC_DHR8RD_DACC1DHR_Pos (0U)
5758#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
5759#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5760#define DAC_DHR8RD_DACC2DHR_Pos (8U)
5761#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
5762#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5763
5764/******************* Bit definition for DAC_DOR1 register *******************/
5765#define DAC_DOR1_DACC1DOR_Pos (0U)
5766#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
5767#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
5768
5769/******************* Bit definition for DAC_DOR2 register *******************/
5770#define DAC_DOR2_DACC2DOR_Pos (0U)
5771#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
5772#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
5773
5774/******************** Bit definition for DAC_SR register ********************/
5775#define DAC_SR_DMAUDR1_Pos (13U)
5776#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
5777#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
5778#define DAC_SR_CAL_FLAG1_Pos (14U)
5779#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
5780#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
5781#define DAC_SR_BWST1_Pos (15U)
5782#define DAC_SR_BWST1_Msk (0x4001UL << DAC_SR_BWST1_Pos) /*!< 0x20008000 */
5783#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
5784
5785#define DAC_SR_DMAUDR2_Pos (29U)
5786#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
5787#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
5788#define DAC_SR_CAL_FLAG2_Pos (30U)
5789#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
5790#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
5791#define DAC_SR_BWST2_Pos (31U)
5792#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
5793#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
5794
5795/******************* Bit definition for DAC_CCR register ********************/
5796#define DAC_CCR_OTRIM1_Pos (0U)
5797#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
5798#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
5799#define DAC_CCR_OTRIM2_Pos (16U)
5800#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
5801#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
5802
5803/******************* Bit definition for DAC_MCR register *******************/
5804#define DAC_MCR_MODE1_Pos (0U)
5805#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
5806#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
5807#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
5808#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
5809#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
5810
5811#define DAC_MCR_MODE2_Pos (16U)
5812#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
5813#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
5814#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
5815#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
5816#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
5817
5818/****************** Bit definition for DAC_SHSR1 register ******************/
5819#define DAC_SHSR1_TSAMPLE1_Pos (0U)
5820#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
5821#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
5822
5823/****************** Bit definition for DAC_SHSR2 register ******************/
5824#define DAC_SHSR2_TSAMPLE2_Pos (0U)
5825#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
5826#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
5827
5828/****************** Bit definition for DAC_SHHR register ******************/
5829#define DAC_SHHR_THOLD1_Pos (0U)
5830#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
5831#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
5832#define DAC_SHHR_THOLD2_Pos (16U)
5833#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
5834#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
5835
5836/****************** Bit definition for DAC_SHRR register ******************/
5837#define DAC_SHRR_TREFRESH1_Pos (0U)
5838#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
5839#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
5840#define DAC_SHRR_TREFRESH2_Pos (16U)
5841#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
5842#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
5843
5844/******************************************************************************/
5845/* */
5846/* DCMI */
5847/* */
5848/******************************************************************************/
5849/******************** Bits definition for DCMI_CR register ******************/
5850#define DCMI_CR_CAPTURE_Pos (0U)
5851#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
5852#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
5853#define DCMI_CR_CM_Pos (1U)
5854#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */
5855#define DCMI_CR_CM DCMI_CR_CM_Msk
5856#define DCMI_CR_CROP_Pos (2U)
5857#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
5858#define DCMI_CR_CROP DCMI_CR_CROP_Msk
5859#define DCMI_CR_JPEG_Pos (3U)
5860#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
5861#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
5862#define DCMI_CR_ESS_Pos (4U)
5863#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
5864#define DCMI_CR_ESS DCMI_CR_ESS_Msk
5865#define DCMI_CR_PCKPOL_Pos (5U)
5866#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
5867#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
5868#define DCMI_CR_HSPOL_Pos (6U)
5869#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
5870#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
5871#define DCMI_CR_VSPOL_Pos (7U)
5872#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
5873#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
5874#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
5875#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
5876#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
5877#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
5878#define DCMI_CR_CRE_Pos (12U)
5879#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
5880#define DCMI_CR_CRE DCMI_CR_CRE_Msk
5881#define DCMI_CR_ENABLE_Pos (14U)
5882#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
5883#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
5884#define DCMI_CR_BSM_Pos (16U)
5885#define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) /*!< 0x00030000 */
5886#define DCMI_CR_BSM DCMI_CR_BSM_Msk
5887#define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos) /*!< 0x00010000 */
5888#define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos) /*!< 0x00020000 */
5889#define DCMI_CR_OEBS_Pos (18U)
5890#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
5891#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
5892#define DCMI_CR_LSM_Pos (19U)
5893#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
5894#define DCMI_CR_LSM DCMI_CR_LSM_Msk
5895#define DCMI_CR_OELS_Pos (20U)
5896#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
5897#define DCMI_CR_OELS DCMI_CR_OELS_Msk
5898
5899/******************** Bits definition for DCMI_SR register ******************/
5900#define DCMI_SR_HSYNC_Pos (0U)
5901#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
5902#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
5903#define DCMI_SR_VSYNC_Pos (1U)
5904#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
5905#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
5906#define DCMI_SR_FNE_Pos (2U)
5907#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
5908#define DCMI_SR_FNE DCMI_SR_FNE_Msk
5909
5910/******************** Bits definition for DCMI_RIS register ****************/
5911#define DCMI_RIS_FRAME_RIS_Pos (0U)
5912#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
5913#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
5914#define DCMI_RIS_OVR_RIS_Pos (1U)
5915#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
5916#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
5917#define DCMI_RIS_ERR_RIS_Pos (2U)
5918#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
5919#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
5920#define DCMI_RIS_VSYNC_RIS_Pos (3U)
5921#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
5922#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
5923#define DCMI_RIS_LINE_RIS_Pos (4U)
5924#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
5925#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
5926
5927/******************** Bits definition for DCMI_IER register *****************/
5928#define DCMI_IER_FRAME_IE_Pos (0U)
5929#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
5930#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
5931#define DCMI_IER_OVR_IE_Pos (1U)
5932#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
5933#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
5934#define DCMI_IER_ERR_IE_Pos (2U)
5935#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
5936#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
5937#define DCMI_IER_VSYNC_IE_Pos (3U)
5938#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
5939#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
5940#define DCMI_IER_LINE_IE_Pos (4U)
5941#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
5942#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
5943
5944
5945/******************** Bits definition for DCMI_MIS register *****************/
5946#define DCMI_MIS_FRAME_MIS_Pos (0U)
5947#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
5948#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
5949#define DCMI_MIS_OVR_MIS_Pos (1U)
5950#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
5951#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
5952#define DCMI_MIS_ERR_MIS_Pos (2U)
5953#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
5954#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
5955#define DCMI_MIS_VSYNC_MIS_Pos (3U)
5956#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
5957#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
5958#define DCMI_MIS_LINE_MIS_Pos (4U)
5959#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
5960#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
5961
5962
5963/******************** Bits definition for DCMI_ICR register *****************/
5964#define DCMI_ICR_FRAME_ISC_Pos (0U)
5965#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
5966#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
5967#define DCMI_ICR_OVR_ISC_Pos (1U)
5968#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
5969#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
5970#define DCMI_ICR_ERR_ISC_Pos (2U)
5971#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
5972#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
5973#define DCMI_ICR_VSYNC_ISC_Pos (3U)
5974#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
5975#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
5976#define DCMI_ICR_LINE_ISC_Pos (4U)
5977#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
5978#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
5979
5980
5981/******************** Bits definition for DCMI_ESCR register ******************/
5982#define DCMI_ESCR_FSC_Pos (0U)
5983#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
5984#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
5985#define DCMI_ESCR_LSC_Pos (8U)
5986#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
5987#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
5988#define DCMI_ESCR_LEC_Pos (16U)
5989#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
5990#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
5991#define DCMI_ESCR_FEC_Pos (24U)
5992#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
5993#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
5994
5995/******************** Bits definition for DCMI_ESUR register ******************/
5996#define DCMI_ESUR_FSU_Pos (0U)
5997#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
5998#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
5999#define DCMI_ESUR_LSU_Pos (8U)
6000#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
6001#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
6002#define DCMI_ESUR_LEU_Pos (16U)
6003#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
6004#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
6005#define DCMI_ESUR_FEU_Pos (24U)
6006#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
6007#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
6008
6009/******************** Bits definition for DCMI_CWSTRT register ******************/
6010#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
6011#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
6012#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
6013#define DCMI_CWSTRT_VST_Pos (16U)
6014#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
6015#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
6016
6017/******************** Bits definition for DCMI_CWSIZE register ******************/
6018#define DCMI_CWSIZE_CAPCNT_Pos (0U)
6019#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
6020#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
6021#define DCMI_CWSIZE_VLINE_Pos (16U)
6022#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
6023#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
6024
6025/******************** Bits definition for DCMI_DR register ******************/
6026#define DCMI_DR_BYTE0_Pos (0U)
6027#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
6028#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
6029#define DCMI_DR_BYTE1_Pos (8U)
6030#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
6031#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
6032#define DCMI_DR_BYTE2_Pos (16U)
6033#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
6034#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
6035#define DCMI_DR_BYTE3_Pos (24U)
6036#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
6037#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
6038
6039/******************************************************************************/
6040/* */
6041/* Digital Filter for Sigma Delta Modulators */
6042/* */
6043/******************************************************************************/
6044
6045/**************** DFSDM channel configuration registers ********************/
6046
6047/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
6048#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
6049#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
6050#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
6051#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
6052#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
6053#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
6054#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
6055#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
6056#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
6057#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
6058#define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
6059#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
6060#define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
6061#define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
6062#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
6063#define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
6064#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
6065#define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
6066#define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
6067#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
6068#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
6069#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
6070#define DFSDM_CHCFGR1_CHEN_Pos (7U)
6071#define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
6072#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
6073#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
6074#define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
6075#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
6076#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
6077#define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
6078#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
6079#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
6080#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
6081#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
6082#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
6083#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
6084#define DFSDM_CHCFGR1_SITP_Pos (0U)
6085#define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
6086#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
6087#define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
6088#define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
6089
6090/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
6091#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
6092#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
6093#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
6094#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
6095#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
6096#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
6097
6098/****************** Bit definition for DFSDM_CHAWSCDR register *****************/
6099#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
6100#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
6101#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
6102#define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
6103#define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
6104#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
6105#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
6106#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
6107#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
6108#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
6109#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
6110#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
6111#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
6112#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
6113
6114/**************** Bit definition for DFSDM_CHWDATR register *******************/
6115#define DFSDM_CHWDATR_WDATA_Pos (0U)
6116#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
6117#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
6118
6119/**************** Bit definition for DFSDM_CHDATINR register *****************/
6120#define DFSDM_CHDATINR_INDAT0_Pos (0U)
6121#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
6122#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
6123#define DFSDM_CHDATINR_INDAT1_Pos (16U)
6124#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
6125#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
6126
6127/************************ DFSDM module registers ****************************/
6128
6129/******************** Bit definition for DFSDM_FLTCR1 register *******************/
6130#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
6131#define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
6132#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
6133#define DFSDM_FLTCR1_FAST_Pos (29U)
6134#define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
6135#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
6136#define DFSDM_FLTCR1_RCH_Pos (24U)
6137#define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
6138#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
6139#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
6140#define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
6141#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
6142#define DFSDM_FLTCR1_RSYNC_Pos (19U)
6143#define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
6144#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
6145#define DFSDM_FLTCR1_RCONT_Pos (18U)
6146#define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
6147#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
6148#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
6149#define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
6150#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
6151#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
6152#define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
6153#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
6154#define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
6155#define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
6156#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
6157#define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001F00 */
6158#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
6159#define DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
6160#define DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
6161#define DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
6162#define DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000800 */
6163#define DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001000 */
6164
6165#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
6166#define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
6167#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
6168#define DFSDM_FLTCR1_JSCAN_Pos (4U)
6169#define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
6170#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
6171#define DFSDM_FLTCR1_JSYNC_Pos (3U)
6172#define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
6173#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
6174#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
6175#define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
6176#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
6177#define DFSDM_FLTCR1_DFEN_Pos (0U)
6178#define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
6179#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
6180
6181/******************** Bit definition for DFSDM_FLTCR2 register *******************/
6182#define DFSDM_FLTCR2_AWDCH_Pos (16U)
6183#define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
6184#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
6185#define DFSDM_FLTCR2_EXCH_Pos (8U)
6186#define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
6187#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
6188#define DFSDM_FLTCR2_CKABIE_Pos (6U)
6189#define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
6190#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
6191#define DFSDM_FLTCR2_SCDIE_Pos (5U)
6192#define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
6193#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
6194#define DFSDM_FLTCR2_AWDIE_Pos (4U)
6195#define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
6196#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
6197#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
6198#define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
6199#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
6200#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
6201#define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
6202#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
6203#define DFSDM_FLTCR2_REOCIE_Pos (1U)
6204#define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
6205#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
6206#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
6207#define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
6208#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
6209
6210/******************** Bit definition for DFSDM_FLTISR register *******************/
6211#define DFSDM_FLTISR_SCDF_Pos (24U)
6212#define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
6213#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
6214#define DFSDM_FLTISR_CKABF_Pos (16U)
6215#define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
6216#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
6217#define DFSDM_FLTISR_RCIP_Pos (14U)
6218#define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
6219#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
6220#define DFSDM_FLTISR_JCIP_Pos (13U)
6221#define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
6222#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
6223#define DFSDM_FLTISR_AWDF_Pos (4U)
6224#define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
6225#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
6226#define DFSDM_FLTISR_ROVRF_Pos (3U)
6227#define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
6228#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
6229#define DFSDM_FLTISR_JOVRF_Pos (2U)
6230#define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
6231#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
6232#define DFSDM_FLTISR_REOCF_Pos (1U)
6233#define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
6234#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
6235#define DFSDM_FLTISR_JEOCF_Pos (0U)
6236#define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
6237#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
6238
6239/******************** Bit definition for DFSDM_FLTICR register *******************/
6240#define DFSDM_FLTICR_CLRSCDF_Pos (24U)
6241#define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0xFF000000 */
6242#define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
6243#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
6244#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
6245#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
6246#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
6247#define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
6248#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
6249#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
6250#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
6251#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
6252
6253/******************* Bit definition for DFSDM_FLTJCHGR register ******************/
6254#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
6255#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
6256#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
6257
6258/******************** Bit definition for DFSDM_FLTFCR register *******************/
6259#define DFSDM_FLTFCR_FORD_Pos (29U)
6260#define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
6261#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
6262#define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
6263#define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
6264#define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
6265#define DFSDM_FLTFCR_FOSR_Pos (16U)
6266#define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
6267#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
6268#define DFSDM_FLTFCR_IOSR_Pos (0U)
6269#define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
6270#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
6271
6272/****************** Bit definition for DFSDM_FLTJDATAR register *****************/
6273#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
6274#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
6275#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
6276#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
6277#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
6278#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
6279
6280/****************** Bit definition for DFSDM_FLTRDATAR register *****************/
6281#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
6282#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
6283#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
6284#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
6285#define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
6286#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
6287#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
6288#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
6289#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
6290
6291/****************** Bit definition for DFSDM_FLTAWHTR register ******************/
6292#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
6293#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
6294#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
6295#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
6296#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
6297#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
6298
6299/****************** Bit definition for DFSDM_FLTAWLTR register ******************/
6300#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
6301#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
6302#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWHT[23:0] Analog watchdog low threshold */
6303#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
6304#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
6305#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
6306
6307/****************** Bit definition for DFSDM_FLTAWSR register ******************/
6308#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
6309#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
6310#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
6311#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
6312#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
6313#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
6314
6315/****************** Bit definition for DFSDM_FLTAWCFR) register *****************/
6316#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
6317#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
6318#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
6319#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
6320#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
6321#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
6322
6323/****************** Bit definition for DFSDM_FLTEXMAX register ******************/
6324#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
6325#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
6326#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
6327#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
6328#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
6329#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
6330
6331/****************** Bit definition for DFSDM_FLTEXMIN register ******************/
6332#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
6333#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
6334#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
6335#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
6336#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
6337#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
6338
6339/****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
6340#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
6341#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
6342#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
6343
6344/******************************************************************************/
6345/* */
6346/* BDMA Controller */
6347/* */
6348/******************************************************************************/
6349
6350/******************* Bit definition for BDMA_ISR register ********************/
6351#define BDMA_ISR_GIF0_Pos (0U)
6352#define BDMA_ISR_GIF0_Msk (0x1UL << BDMA_ISR_GIF0_Pos) /*!< 0x00000001 */
6353#define BDMA_ISR_GIF0 BDMA_ISR_GIF0_Msk /*!< Channel 0 Global interrupt flag */
6354#define BDMA_ISR_TCIF0_Pos (1U)
6355#define BDMA_ISR_TCIF0_Msk (0x1UL << BDMA_ISR_TCIF0_Pos) /*!< 0x00000002 */
6356#define BDMA_ISR_TCIF0 BDMA_ISR_TCIF0_Msk /*!< Channel 0 Transfer Complete flag */
6357#define BDMA_ISR_HTIF0_Pos (2U)
6358#define BDMA_ISR_HTIF0_Msk (0x1UL << BDMA_ISR_HTIF0_Pos) /*!< 0x00000004 */
6359#define BDMA_ISR_HTIF0 BDMA_ISR_HTIF0_Msk /*!< Channel 0 Half Transfer flag */
6360#define BDMA_ISR_TEIF0_Pos (3U)
6361#define BDMA_ISR_TEIF0_Msk (0x1UL << BDMA_ISR_TEIF0_Pos) /*!< 0x00000008 */
6362#define BDMA_ISR_TEIF0 BDMA_ISR_TEIF0_Msk /*!< Channel 0 Transfer Error flag */
6363#define BDMA_ISR_GIF1_Pos (4U)
6364#define BDMA_ISR_GIF1_Msk (0x1UL << BDMA_ISR_GIF1_Pos) /*!< 0x00000010 */
6365#define BDMA_ISR_GIF1 BDMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
6366#define BDMA_ISR_TCIF1_Pos (5U)
6367#define BDMA_ISR_TCIF1_Msk (0x1UL << BDMA_ISR_TCIF1_Pos) /*!< 0x00000020 */
6368#define BDMA_ISR_TCIF1 BDMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
6369#define BDMA_ISR_HTIF1_Pos (6U)
6370#define BDMA_ISR_HTIF1_Msk (0x1UL << BDMA_ISR_HTIF1_Pos) /*!< 0x00000040 */
6371#define BDMA_ISR_HTIF1 BDMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
6372#define BDMA_ISR_TEIF1_Pos (7U)
6373#define BDMA_ISR_TEIF1_Msk (0x1UL << BDMA_ISR_TEIF1_Pos) /*!< 0x00000080 */
6374#define BDMA_ISR_TEIF1 BDMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
6375#define BDMA_ISR_GIF2_Pos (8U)
6376#define BDMA_ISR_GIF2_Msk (0x1UL << BDMA_ISR_GIF2_Pos) /*!< 0x00000100 */
6377#define BDMA_ISR_GIF2 BDMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
6378#define BDMA_ISR_TCIF2_Pos (9U)
6379#define BDMA_ISR_TCIF2_Msk (0x1UL << BDMA_ISR_TCIF2_Pos) /*!< 0x00000200 */
6380#define BDMA_ISR_TCIF2 BDMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
6381#define BDMA_ISR_HTIF2_Pos (10U)
6382#define BDMA_ISR_HTIF2_Msk (0x1UL << BDMA_ISR_HTIF2_Pos) /*!< 0x00000400 */
6383#define BDMA_ISR_HTIF2 BDMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
6384#define BDMA_ISR_TEIF2_Pos (11U)
6385#define BDMA_ISR_TEIF2_Msk (0x1UL << BDMA_ISR_TEIF2_Pos) /*!< 0x00000800 */
6386#define BDMA_ISR_TEIF2 BDMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
6387#define BDMA_ISR_GIF3_Pos (12U)
6388#define BDMA_ISR_GIF3_Msk (0x1UL << BDMA_ISR_GIF3_Pos) /*!< 0x00001000 */
6389#define BDMA_ISR_GIF3 BDMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
6390#define BDMA_ISR_TCIF3_Pos (13U)
6391#define BDMA_ISR_TCIF3_Msk (0x1UL << BDMA_ISR_TCIF3_Pos) /*!< 0x00002000 */
6392#define BDMA_ISR_TCIF3 BDMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
6393#define BDMA_ISR_HTIF3_Pos (14U)
6394#define BDMA_ISR_HTIF3_Msk (0x1UL << BDMA_ISR_HTIF3_Pos) /*!< 0x00004000 */
6395#define BDMA_ISR_HTIF3 BDMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
6396#define BDMA_ISR_TEIF3_Pos (15U)
6397#define BDMA_ISR_TEIF3_Msk (0x1UL << BDMA_ISR_TEIF3_Pos) /*!< 0x00008000 */
6398#define BDMA_ISR_TEIF3 BDMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
6399#define BDMA_ISR_GIF4_Pos (16U)
6400#define BDMA_ISR_GIF4_Msk (0x1UL << BDMA_ISR_GIF4_Pos) /*!< 0x00010000 */
6401#define BDMA_ISR_GIF4 BDMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
6402#define BDMA_ISR_TCIF4_Pos (17U)
6403#define BDMA_ISR_TCIF4_Msk (0x1UL << BDMA_ISR_TCIF4_Pos) /*!< 0x00020000 */
6404#define BDMA_ISR_TCIF4 BDMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
6405#define BDMA_ISR_HTIF4_Pos (18U)
6406#define BDMA_ISR_HTIF4_Msk (0x1UL << BDMA_ISR_HTIF4_Pos) /*!< 0x00040000 */
6407#define BDMA_ISR_HTIF4 BDMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
6408#define BDMA_ISR_TEIF4_Pos (19U)
6409#define BDMA_ISR_TEIF4_Msk (0x1UL << BDMA_ISR_TEIF4_Pos) /*!< 0x00080000 */
6410#define BDMA_ISR_TEIF4 BDMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
6411#define BDMA_ISR_GIF5_Pos (20U)
6412#define BDMA_ISR_GIF5_Msk (0x1UL << BDMA_ISR_GIF5_Pos) /*!< 0x00100000 */
6413#define BDMA_ISR_GIF5 BDMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
6414#define BDMA_ISR_TCIF5_Pos (21U)
6415#define BDMA_ISR_TCIF5_Msk (0x1UL << BDMA_ISR_TCIF5_Pos) /*!< 0x00200000 */
6416#define BDMA_ISR_TCIF5 BDMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
6417#define BDMA_ISR_HTIF5_Pos (22U)
6418#define BDMA_ISR_HTIF5_Msk (0x1UL << BDMA_ISR_HTIF5_Pos) /*!< 0x00400000 */
6419#define BDMA_ISR_HTIF5 BDMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
6420#define BDMA_ISR_TEIF5_Pos (23U)
6421#define BDMA_ISR_TEIF5_Msk (0x1UL << BDMA_ISR_TEIF5_Pos) /*!< 0x00800000 */
6422#define BDMA_ISR_TEIF5 BDMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
6423#define BDMA_ISR_GIF6_Pos (24U)
6424#define BDMA_ISR_GIF6_Msk (0x1UL << BDMA_ISR_GIF6_Pos) /*!< 0x01000000 */
6425#define BDMA_ISR_GIF6 BDMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
6426#define BDMA_ISR_TCIF6_Pos (25U)
6427#define BDMA_ISR_TCIF6_Msk (0x1UL << BDMA_ISR_TCIF6_Pos) /*!< 0x02000000 */
6428#define BDMA_ISR_TCIF6 BDMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
6429#define BDMA_ISR_HTIF6_Pos (26U)
6430#define BDMA_ISR_HTIF6_Msk (0x1UL << BDMA_ISR_HTIF6_Pos) /*!< 0x04000000 */
6431#define BDMA_ISR_HTIF6 BDMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
6432#define BDMA_ISR_TEIF6_Pos (27U)
6433#define BDMA_ISR_TEIF6_Msk (0x1UL << BDMA_ISR_TEIF6_Pos) /*!< 0x08000000 */
6434#define BDMA_ISR_TEIF6 BDMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
6435#define BDMA_ISR_GIF7_Pos (28U)
6436#define BDMA_ISR_GIF7_Msk (0x1UL << BDMA_ISR_GIF7_Pos) /*!< 0x10000000 */
6437#define BDMA_ISR_GIF7 BDMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
6438#define BDMA_ISR_TCIF7_Pos (29U)
6439#define BDMA_ISR_TCIF7_Msk (0x1UL << BDMA_ISR_TCIF7_Pos) /*!< 0x20000000 */
6440#define BDMA_ISR_TCIF7 BDMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
6441#define BDMA_ISR_HTIF7_Pos (30U)
6442#define BDMA_ISR_HTIF7_Msk (0x1UL << BDMA_ISR_HTIF7_Pos) /*!< 0x40000000 */
6443#define BDMA_ISR_HTIF7 BDMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
6444#define BDMA_ISR_TEIF7_Pos (31U)
6445#define BDMA_ISR_TEIF7_Msk (0x1UL << BDMA_ISR_TEIF7_Pos) /*!< 0x80000000 */
6446#define BDMA_ISR_TEIF7 BDMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
6447
6448/******************* Bit definition for BDMA_IFCR register *******************/
6449#define BDMA_IFCR_CGIF0_Pos (0U)
6450#define BDMA_IFCR_CGIF0_Msk (0x1UL << BDMA_IFCR_CGIF0_Pos) /*!< 0x00000001 */
6451#define BDMA_IFCR_CGIF0 BDMA_IFCR_CGIF0_Msk /*!< Channel 0 Global interrupt clearr */
6452#define BDMA_IFCR_CTCIF0_Pos (1U)
6453#define BDMA_IFCR_CTCIF0_Msk (0x1UL << BDMA_IFCR_CTCIF0_Pos) /*!< 0x00000002 */
6454#define BDMA_IFCR_CTCIF0 BDMA_IFCR_CTCIF0_Msk /*!< Channel 0 Transfer Complete clear */
6455#define BDMA_IFCR_CHTIF0_Pos (2U)
6456#define BDMA_IFCR_CHTIF0_Msk (0x1UL << BDMA_IFCR_CHTIF0_Pos) /*!< 0x00000004 */
6457#define BDMA_IFCR_CHTIF0 BDMA_IFCR_CHTIF0_Msk /*!< Channel 0 Half Transfer clear */
6458#define BDMA_IFCR_CTEIF0_Pos (3U)
6459#define BDMA_IFCR_CTEIF0_Msk (0x1UL << BDMA_IFCR_CTEIF0_Pos) /*!< 0x00000008 */
6460#define BDMA_IFCR_CTEIF0 BDMA_IFCR_CTEIF0_Msk /*!< Channel 0 Transfer Error clear */
6461#define BDMA_IFCR_CGIF1_Pos (4U)
6462#define BDMA_IFCR_CGIF1_Msk (0x1UL << BDMA_IFCR_CGIF1_Pos) /*!< 0x00000010 */
6463#define BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
6464#define BDMA_IFCR_CTCIF1_Pos (5U)
6465#define BDMA_IFCR_CTCIF1_Msk (0x1UL << BDMA_IFCR_CTCIF1_Pos) /*!< 0x00000020 */
6466#define BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
6467#define BDMA_IFCR_CHTIF1_Pos (6U)
6468#define BDMA_IFCR_CHTIF1_Msk (0x1UL << BDMA_IFCR_CHTIF1_Pos) /*!< 0x00000040 */
6469#define BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
6470#define BDMA_IFCR_CTEIF1_Pos (7U)
6471#define BDMA_IFCR_CTEIF1_Msk (0x1UL << BDMA_IFCR_CTEIF1_Pos) /*!< 0x00000080 */
6472#define BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
6473#define BDMA_IFCR_CGIF2_Pos (8U)
6474#define BDMA_IFCR_CGIF2_Msk (0x1UL << BDMA_IFCR_CGIF2_Pos) /*!< 0x00000100 */
6475#define BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
6476#define BDMA_IFCR_CTCIF2_Pos (9U)
6477#define BDMA_IFCR_CTCIF2_Msk (0x1UL << BDMA_IFCR_CTCIF2_Pos) /*!< 0x00000200 */
6478#define BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
6479#define BDMA_IFCR_CHTIF2_Pos (10U)
6480#define BDMA_IFCR_CHTIF2_Msk (0x1UL << BDMA_IFCR_CHTIF2_Pos) /*!< 0x00000400 */
6481#define BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
6482#define BDMA_IFCR_CTEIF2_Pos (11U)
6483#define BDMA_IFCR_CTEIF2_Msk (0x1UL << BDMA_IFCR_CTEIF2_Pos) /*!< 0x00000800 */
6484#define BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
6485#define BDMA_IFCR_CGIF3_Pos (12U)
6486#define BDMA_IFCR_CGIF3_Msk (0x1UL << BDMA_IFCR_CGIF3_Pos) /*!< 0x00001000 */
6487#define BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
6488#define BDMA_IFCR_CTCIF3_Pos (13U)
6489#define BDMA_IFCR_CTCIF3_Msk (0x1UL << BDMA_IFCR_CTCIF3_Pos) /*!< 0x00002000 */
6490#define BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
6491#define BDMA_IFCR_CHTIF3_Pos (14U)
6492#define BDMA_IFCR_CHTIF3_Msk (0x1UL << BDMA_IFCR_CHTIF3_Pos) /*!< 0x00004000 */
6493#define BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
6494#define BDMA_IFCR_CTEIF3_Pos (15U)
6495#define BDMA_IFCR_CTEIF3_Msk (0x1UL << BDMA_IFCR_CTEIF3_Pos) /*!< 0x00008000 */
6496#define BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
6497#define BDMA_IFCR_CGIF4_Pos (16U)
6498#define BDMA_IFCR_CGIF4_Msk (0x1UL << BDMA_IFCR_CGIF4_Pos) /*!< 0x00010000 */
6499#define BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
6500#define BDMA_IFCR_CTCIF4_Pos (17U)
6501#define BDMA_IFCR_CTCIF4_Msk (0x1UL << BDMA_IFCR_CTCIF4_Pos) /*!< 0x00020000 */
6502#define BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
6503#define BDMA_IFCR_CHTIF4_Pos (18U)
6504#define BDMA_IFCR_CHTIF4_Msk (0x1UL << BDMA_IFCR_CHTIF4_Pos) /*!< 0x00040000 */
6505#define BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
6506#define BDMA_IFCR_CTEIF4_Pos (19U)
6507#define BDMA_IFCR_CTEIF4_Msk (0x1UL << BDMA_IFCR_CTEIF4_Pos) /*!< 0x00080000 */
6508#define BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
6509#define BDMA_IFCR_CGIF5_Pos (20U)
6510#define BDMA_IFCR_CGIF5_Msk (0x1UL << BDMA_IFCR_CGIF5_Pos) /*!< 0x00100000 */
6511#define BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
6512#define BDMA_IFCR_CTCIF5_Pos (21U)
6513#define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
6514#define BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
6515#define BDMA_IFCR_CHTIF5_Pos (22U)
6516#define BDMA_IFCR_CHTIF5_Msk (0x1UL << BDMA_IFCR_CHTIF5_Pos) /*!< 0x00400000 */
6517#define BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
6518#define BDMA_IFCR_CTEIF5_Pos (23U)
6519#define BDMA_IFCR_CTEIF5_Msk (0x1UL << BDMA_IFCR_CTEIF5_Pos) /*!< 0x00800000 */
6520#define BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
6521#define BDMA_IFCR_CGIF6_Pos (24U)
6522#define BDMA_IFCR_CGIF6_Msk (0x1UL << BDMA_IFCR_CGIF6_Pos) /*!< 0x01000000 */
6523#define BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
6524#define BDMA_IFCR_CTCIF6_Pos (25U)
6525#define BDMA_IFCR_CTCIF6_Msk (0x1UL << BDMA_IFCR_CTCIF6_Pos) /*!< 0x02000000 */
6526#define BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
6527#define BDMA_IFCR_CHTIF6_Pos (26U)
6528#define BDMA_IFCR_CHTIF6_Msk (0x1UL << BDMA_IFCR_CHTIF6_Pos) /*!< 0x04000000 */
6529#define BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
6530#define BDMA_IFCR_CTEIF6_Pos (27U)
6531#define BDMA_IFCR_CTEIF6_Msk (0x1UL << BDMA_IFCR_CTEIF6_Pos) /*!< 0x08000000 */
6532#define BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
6533#define BDMA_IFCR_CGIF7_Pos (28U)
6534#define BDMA_IFCR_CGIF7_Msk (0x1UL << BDMA_IFCR_CGIF7_Pos) /*!< 0x10000000 */
6535#define BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
6536#define BDMA_IFCR_CTCIF7_Pos (29U)
6537#define BDMA_IFCR_CTCIF7_Msk (0x1UL << BDMA_IFCR_CTCIF7_Pos) /*!< 0x20000000 */
6538#define BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
6539#define BDMA_IFCR_CHTIF7_Pos (30U)
6540#define BDMA_IFCR_CHTIF7_Msk (0x1UL << BDMA_IFCR_CHTIF7_Pos) /*!< 0x40000000 */
6541#define BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
6542#define BDMA_IFCR_CTEIF7_Pos (31U)
6543#define BDMA_IFCR_CTEIF7_Msk (0x1UL << BDMA_IFCR_CTEIF7_Pos) /*!< 0x80000000 */
6544#define BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
6545
6546/******************* Bit definition for BDMA_CCR register ********************/
6547#define BDMA_CCR_EN_Pos (0U)
6548#define BDMA_CCR_EN_Msk (0x1UL << BDMA_CCR_EN_Pos) /*!< 0x00000001 */
6549#define BDMA_CCR_EN BDMA_CCR_EN_Msk /*!< Channel enable */
6550#define BDMA_CCR_TCIE_Pos (1U)
6551#define BDMA_CCR_TCIE_Msk (0x1UL << BDMA_CCR_TCIE_Pos) /*!< 0x00000002 */
6552#define BDMA_CCR_TCIE BDMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
6553#define BDMA_CCR_HTIE_Pos (2U)
6554#define BDMA_CCR_HTIE_Msk (0x1UL << BDMA_CCR_HTIE_Pos) /*!< 0x00000004 */
6555#define BDMA_CCR_HTIE BDMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
6556#define BDMA_CCR_TEIE_Pos (3U)
6557#define BDMA_CCR_TEIE_Msk (0x1UL << BDMA_CCR_TEIE_Pos) /*!< 0x00000008 */
6558#define BDMA_CCR_TEIE BDMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
6559#define BDMA_CCR_DIR_Pos (4U)
6560#define BDMA_CCR_DIR_Msk (0x1UL << BDMA_CCR_DIR_Pos) /*!< 0x00000010 */
6561#define BDMA_CCR_DIR BDMA_CCR_DIR_Msk /*!< Data transfer direction */
6562#define BDMA_CCR_CIRC_Pos (5U)
6563#define BDMA_CCR_CIRC_Msk (0x1UL << BDMA_CCR_CIRC_Pos) /*!< 0x00000020 */
6564#define BDMA_CCR_CIRC BDMA_CCR_CIRC_Msk /*!< Circular mode */
6565#define BDMA_CCR_PINC_Pos (6U)
6566#define BDMA_CCR_PINC_Msk (0x1UL << BDMA_CCR_PINC_Pos) /*!< 0x00000040 */
6567#define BDMA_CCR_PINC BDMA_CCR_PINC_Msk /*!< Peripheral increment mode */
6568#define BDMA_CCR_MINC_Pos (7U)
6569#define BDMA_CCR_MINC_Msk (0x1UL << BDMA_CCR_MINC_Pos) /*!< 0x00000080 */
6570#define BDMA_CCR_MINC BDMA_CCR_MINC_Msk /*!< Memory increment mode */
6571
6572#define BDMA_CCR_PSIZE_Pos (8U)
6573#define BDMA_CCR_PSIZE_Msk (0x3UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
6574#define BDMA_CCR_PSIZE BDMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
6575#define BDMA_CCR_PSIZE_0 (0x1UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
6576#define BDMA_CCR_PSIZE_1 (0x2UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
6577
6578#define BDMA_CCR_MSIZE_Pos (10U)
6579#define BDMA_CCR_MSIZE_Msk (0x3UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
6580#define BDMA_CCR_MSIZE BDMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
6581#define BDMA_CCR_MSIZE_0 (0x1UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
6582#define BDMA_CCR_MSIZE_1 (0x2UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
6583
6584#define BDMA_CCR_PL_Pos (12U)
6585#define BDMA_CCR_PL_Msk (0x3UL << BDMA_CCR_PL_Pos) /*!< 0x00003000 */
6586#define BDMA_CCR_PL BDMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
6587#define BDMA_CCR_PL_0 (0x1UL << BDMA_CCR_PL_Pos) /*!< 0x00001000 */
6588#define BDMA_CCR_PL_1 (0x2UL << BDMA_CCR_PL_Pos) /*!< 0x00002000 */
6589
6590#define BDMA_CCR_MEM2MEM_Pos (14U)
6591#define BDMA_CCR_MEM2MEM_Msk (0x1UL << BDMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
6592#define BDMA_CCR_MEM2MEM BDMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
6593#define BDMA_CCR_DBM_Pos (15U)
6594#define BDMA_CCR_DBM_Msk (0x1UL << BDMA_CCR_DBM_Pos) /*!< 0x0000A000 */
6595#define BDMA_CCR_DBM BDMA_CCR_DBM_Msk /*!< Memory to memory mode */
6596#define BDMA_CCR_CT_Pos (16U)
6597#define BDMA_CCR_CT_Msk (0x1UL << BDMA_CCR_CT_Pos) /*!< 0x00010000 */
6598#define BDMA_CCR_CT BDMA_CCR_CT_Msk /*!< Memory to memory mode */
6599
6600/****************** Bit definition for BDMA_CNDTR register *******************/
6601#define BDMA_CNDTR_NDT_Pos (0U)
6602#define BDMA_CNDTR_NDT_Msk (0xFFFFUL << BDMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
6603#define BDMA_CNDTR_NDT BDMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
6604
6605/****************** Bit definition for BDMA_CPAR register ********************/
6606#define BDMA_CPAR_PA_Pos (0U)
6607#define BDMA_CPAR_PA_Msk (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
6608#define BDMA_CPAR_PA BDMA_CPAR_PA_Msk /*!< Peripheral Address */
6609
6610/****************** Bit definition for BDMA_CM0AR register ********************/
6611#define BDMA_CM0AR_MA_Pos (0U)
6612#define BDMA_CM0AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos) /*!< 0xFFFFFFFF */
6613#define BDMA_CM0AR_MA BDMA_CM0AR_MA_Msk /*!< Memory Address */
6614
6615/****************** Bit definition for BDMA_CM1AR register ********************/
6616#define BDMA_CM1AR_MA_Pos (0U)
6617#define BDMA_CM1AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos) /*!< 0xFFFFFFFF */
6618#define BDMA_CM1AR_MA BDMA_CM1AR_MA_Msk /*!< Memory Address */
6619
6620/******************************************************************************/
6621/* */
6622/* Ethernet MAC Registers bits definitions */
6623/* */
6624/******************************************************************************/
6625/* Bit definition for Ethernet MAC Configuration Register register */
6626#define ETH_MACCR_ARP_Pos (31U)
6627#define ETH_MACCR_ARP_Msk (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */
6628#define ETH_MACCR_ARP ETH_MACCR_ARP_Msk /* ARP Offload Enable */
6629#define ETH_MACCR_SARC_Pos (28U)
6630#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
6631#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
6632#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
6633#define ETH_MACCR_SARC_INSADDR0_Pos (29U)
6634#define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
6635#define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
6636#define ETH_MACCR_SARC_INSADDR1_Pos (29U)
6637#define ETH_MACCR_SARC_INSADDR1_Msk (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */
6638#define ETH_MACCR_SARC_INSADDR1 ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
6639#define ETH_MACCR_SARC_REPADDR0_Pos (28U)
6640#define ETH_MACCR_SARC_REPADDR0_Msk (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */
6641#define ETH_MACCR_SARC_REPADDR0 ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
6642#define ETH_MACCR_SARC_REPADDR1_Pos (28U)
6643#define ETH_MACCR_SARC_REPADDR1_Msk (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */
6644#define ETH_MACCR_SARC_REPADDR1 ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
6645#define ETH_MACCR_IPC_Pos (27U)
6646#define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */
6647#define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /* Checksum Offload */
6648#define ETH_MACCR_IPG_Pos (24U)
6649#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
6650#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
6651#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */
6652#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */
6653#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */
6654#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */
6655#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */
6656#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */
6657#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */
6658#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */
6659#define ETH_MACCR_GPSLCE_Pos (23U)
6660#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
6661#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
6662#define ETH_MACCR_S2KP_Pos (22U)
6663#define ETH_MACCR_S2KP_Msk (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */
6664#define ETH_MACCR_S2KP ETH_MACCR_S2KP_Msk /* IEEE 802.3as Support for 2K Packets */
6665#define ETH_MACCR_CST_Pos (21U)
6666#define ETH_MACCR_CST_Msk (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */
6667#define ETH_MACCR_CST ETH_MACCR_CST_Msk /* CRC stripping for Type packets */
6668#define ETH_MACCR_ACS_Pos (20U)
6669#define ETH_MACCR_ACS_Msk (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */
6670#define ETH_MACCR_ACS ETH_MACCR_ACS_Msk /* Automatic Pad or CRC Stripping */
6671#define ETH_MACCR_WD_Pos (19U)
6672#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */
6673#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
6674#define ETH_MACCR_JD_Pos (17U)
6675#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */
6676#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
6677#define ETH_MACCR_JE_Pos (16U)
6678#define ETH_MACCR_JE_Msk (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */
6679#define ETH_MACCR_JE ETH_MACCR_JE_Msk /* Jumbo Packet Enable */
6680#define ETH_MACCR_FES_Pos (14U)
6681#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
6682#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
6683#define ETH_MACCR_DM_Pos (13U)
6684#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */
6685#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
6686#define ETH_MACCR_LM_Pos (12U)
6687#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
6688#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
6689#define ETH_MACCR_ECRSFD_Pos (11U)
6690#define ETH_MACCR_ECRSFD_Msk (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */
6691#define ETH_MACCR_ECRSFD ETH_MACCR_ECRSFD_Msk /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
6692#define ETH_MACCR_DO_Pos (10U)
6693#define ETH_MACCR_DO_Msk (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */
6694#define ETH_MACCR_DO ETH_MACCR_DO_Msk /* Disable Receive own */
6695#define ETH_MACCR_DCRS_Pos (9U)
6696#define ETH_MACCR_DCRS_Msk (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */
6697#define ETH_MACCR_DCRS ETH_MACCR_DCRS_Msk /* Disable Carrier Sense During Transmission */
6698#define ETH_MACCR_DR_Pos (8U)
6699#define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */
6700#define ETH_MACCR_DR ETH_MACCR_DR_Msk /* Disable Retry */
6701#define ETH_MACCR_BL_Pos (5U)
6702#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
6703#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit mask */
6704#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */
6705#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */
6706#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */
6707#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
6708#define ETH_MACCR_DC_Pos (4U)
6709#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
6710#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
6711#define ETH_MACCR_PRELEN_Pos (2U)
6712#define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */
6713#define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /* Preamble Length for Transmit packets */
6714#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */
6715#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */
6716#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */
6717#define ETH_MACCR_TE_Pos (1U)
6718#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */
6719#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
6720#define ETH_MACCR_RE_Pos (0U)
6721#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */
6722#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
6723
6724/* Bit definition for Ethernet MAC Extended Configuration Register register */
6725#define ETH_MACECR_EIPG_Pos (25U)
6726#define ETH_MACECR_EIPG_Msk (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */
6727#define ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk /* Extended Inter-Packet Gap */
6728#define ETH_MACECR_EIPGEN_Pos (24U)
6729#define ETH_MACECR_EIPGEN_Msk (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */
6730#define ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk /* Extended Inter-Packet Gap Enable */
6731#define ETH_MACECR_USP_Pos (18U)
6732#define ETH_MACECR_USP_Msk (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */
6733#define ETH_MACECR_USP ETH_MACECR_USP_Msk /* Unicast Slow Protocol Packet Detect */
6734#define ETH_MACECR_SPEN_Pos (17U)
6735#define ETH_MACECR_SPEN_Msk (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */
6736#define ETH_MACECR_SPEN ETH_MACECR_SPEN_Msk /* Slow Protocol Detection Enable */
6737#define ETH_MACECR_DCRCC_Pos (16U)
6738#define ETH_MACECR_DCRCC_Msk (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */
6739#define ETH_MACECR_DCRCC ETH_MACECR_DCRCC_Msk /* Disable CRC Checking for Received Packets */
6740#define ETH_MACECR_GPSL_Pos (0U)
6741#define ETH_MACECR_GPSL_Msk (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */
6742#define ETH_MACECR_GPSL ETH_MACECR_GPSL_Msk /* Giant Packet Size Limit */
6743
6744/* Bit definition for Ethernet MAC Packet Filter Register */
6745#define ETH_MACPFR_RA_Pos (31U)
6746#define ETH_MACPFR_RA_Msk (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */
6747#define ETH_MACPFR_RA ETH_MACPFR_RA_Msk /* Receive all */
6748#define ETH_MACPFR_DNTU_Pos (21U)
6749#define ETH_MACPFR_DNTU_Msk (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */
6750#define ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk /* Drop Non-TCP/UDP over IP Packets */
6751#define ETH_MACPFR_IPFE_Pos (20U)
6752#define ETH_MACPFR_IPFE_Msk (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */
6753#define ETH_MACPFR_IPFE ETH_MACPFR_IPFE_Msk /* Layer 3 and Layer 4 Filter Enable */
6754#define ETH_MACPFR_VTFE_Pos (16U)
6755#define ETH_MACPFR_VTFE_Msk (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */
6756#define ETH_MACPFR_VTFE ETH_MACPFR_VTFE_Msk /* VLAN Tag Filter Enable */
6757#define ETH_MACPFR_HPF_Pos (10U)
6758#define ETH_MACPFR_HPF_Msk (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */
6759#define ETH_MACPFR_HPF ETH_MACPFR_HPF_Msk /* Hash or perfect filter */
6760#define ETH_MACPFR_SAF_Pos (9U)
6761#define ETH_MACPFR_SAF_Msk (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */
6762#define ETH_MACPFR_SAF ETH_MACPFR_SAF_Msk /* Source address filter enable */
6763#define ETH_MACPFR_SAIF_Pos (8U)
6764#define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */
6765#define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /* SA inverse filtering */
6766#define ETH_MACPFR_PCF_Pos (6U)
6767#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
6768#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
6769#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */
6770#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
6771#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
6772#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
6773#define ETH_MACPFR_PCF_FORWARDALL_Pos (7U)
6774#define ETH_MACPFR_PCF_FORWARDALL_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */
6775#define ETH_MACPFR_PCF_FORWARDALL ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
6776#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos (6U)
6777#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */
6778#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
6779#define ETH_MACPFR_DBF_Pos (5U)
6780#define ETH_MACPFR_DBF_Msk (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */
6781#define ETH_MACPFR_DBF ETH_MACPFR_DBF_Msk /* Disable Broadcast Packets */
6782#define ETH_MACPFR_PM_Pos (4U)
6783#define ETH_MACPFR_PM_Msk (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */
6784#define ETH_MACPFR_PM ETH_MACPFR_PM_Msk /* Pass all mutlicast */
6785#define ETH_MACPFR_DAIF_Pos (3U)
6786#define ETH_MACPFR_DAIF_Msk (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */
6787#define ETH_MACPFR_DAIF ETH_MACPFR_DAIF_Msk /* DA Inverse filtering */
6788#define ETH_MACPFR_HMC_Pos (2U)
6789#define ETH_MACPFR_HMC_Msk (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */
6790#define ETH_MACPFR_HMC ETH_MACPFR_HMC_Msk /* Hash multicast */
6791#define ETH_MACPFR_HUC_Pos (1U)
6792#define ETH_MACPFR_HUC_Msk (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */
6793#define ETH_MACPFR_HUC ETH_MACPFR_HUC_Msk /* Hash unicast */
6794#define ETH_MACPFR_PR_Pos (0U)
6795#define ETH_MACPFR_PR_Msk (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */
6796#define ETH_MACPFR_PR ETH_MACPFR_PR_Msk /* Promiscuous mode */
6797
6798/* Bit definition for Ethernet MAC Watchdog Timeout Register */
6799#define ETH_MACWTR_PWE_Pos (8U)
6800#define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */
6801#define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /* Programmable Watchdog Enable */
6802#define ETH_MACWTR_WTO_Pos (0U)
6803#define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
6804#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
6805#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/
6806#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */
6807#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */
6808#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */
6809#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */
6810#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */
6811#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */
6812#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */
6813#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */
6814#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */
6815#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */
6816#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */
6817#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */
6818#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */
6819#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */
6820
6821/* Bit definition for Ethernet MAC Hash Table High Register */
6822#define ETH_MACHTHR_HTH_Pos (0U)
6823#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
6824#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
6825
6826/* Bit definition for Ethernet MAC Hash Table Low Register */
6827#define ETH_MACHTLR_HTL_Pos (0U)
6828#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
6829#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
6830
6831/* Bit definition for Ethernet MAC VLAN Tag Register */
6832#define ETH_MACVTR_EIVLRXS_Pos (31U)
6833#define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */
6834#define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /* Enable Inner VLAN Tag in Rx Status */
6835#define ETH_MACVTR_EIVLS_Pos (28U)
6836#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
6837#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
6838#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
6839#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
6840#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
6841#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
6842#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U)
6843#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */
6844#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
6845#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U)
6846#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */
6847#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
6848#define ETH_MACVTR_ERIVLT_Pos (27U)
6849#define ETH_MACVTR_ERIVLT_Msk (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */
6850#define ETH_MACVTR_ERIVLT ETH_MACVTR_ERIVLT_Msk /* Enable Inner VLAN Tag */
6851#define ETH_MACVTR_EDVLP_Pos (26U)
6852#define ETH_MACVTR_EDVLP_Msk (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */
6853#define ETH_MACVTR_EDVLP ETH_MACVTR_EDVLP_Msk /* Enable Double VLAN Processing */
6854#define ETH_MACVTR_VTHM_Pos (25U)
6855#define ETH_MACVTR_VTHM_Msk (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */
6856#define ETH_MACVTR_VTHM ETH_MACVTR_VTHM_Msk /* VLAN Tag Hash Table Match Enable */
6857#define ETH_MACVTR_EVLRXS_Pos (24U)
6858#define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */
6859#define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /* Enable VLAN Tag in Rx status */
6860#define ETH_MACVTR_EVLS_Pos (21U)
6861#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
6862#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
6863#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
6864#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
6865#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
6866#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
6867#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U)
6868#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */
6869#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
6870#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U)
6871#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */
6872#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
6873#define ETH_MACVTR_DOVLTC_Pos (20U)
6874#define ETH_MACVTR_DOVLTC_Msk (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */
6875#define ETH_MACVTR_DOVLTC ETH_MACVTR_DOVLTC_Msk /* Disable VLAN Type Check */
6876#define ETH_MACVTR_ERSVLM_Pos (19U)
6877#define ETH_MACVTR_ERSVLM_Msk (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */
6878#define ETH_MACVTR_ERSVLM ETH_MACVTR_ERSVLM_Msk /* Enable Receive S-VLAN Match */
6879#define ETH_MACVTR_ESVL_Pos (18U)
6880#define ETH_MACVTR_ESVL_Msk (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */
6881#define ETH_MACVTR_ESVL ETH_MACVTR_ESVL_Msk /* Enable S-VLAN */
6882#define ETH_MACVTR_VTIM_Pos (17U)
6883#define ETH_MACVTR_VTIM_Msk (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */
6884#define ETH_MACVTR_VTIM ETH_MACVTR_VTIM_Msk /* VLAN Tag Inverse Match Enable */
6885#define ETH_MACVTR_ETV_Pos (16U)
6886#define ETH_MACVTR_ETV_Msk (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */
6887#define ETH_MACVTR_ETV ETH_MACVTR_ETV_Msk /* Enable 12-Bit VLAN Tag Comparison */
6888#define ETH_MACVTR_VL_Pos (0U)
6889#define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */
6890#define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /* VLAN Tag Identifier for Receive Packets */
6891#define ETH_MACVTR_VL_UP_Pos (13U)
6892#define ETH_MACVTR_VL_UP_Msk (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */
6893#define ETH_MACVTR_VL_UP ETH_MACVTR_VL_UP_Msk /* User Priority */
6894#define ETH_MACVTR_VL_CFIDEI_Pos (12U)
6895#define ETH_MACVTR_VL_CFIDEI_Msk (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */
6896#define ETH_MACVTR_VL_CFIDEI ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
6897#define ETH_MACVTR_VL_VID_Pos (0U)
6898#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */
6899#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /* VLAN Identifier field of VLAN tag */
6900
6901/* Bit definition for Ethernet MAC VLAN Hash Table Register */
6902#define ETH_MACVHTR_VLHT_Pos (0U)
6903#define ETH_MACVHTR_VLHT_Msk (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */
6904#define ETH_MACVHTR_VLHT ETH_MACVHTR_VLHT_Msk /* VLAN Hash Table */
6905
6906/* Bit definition for Ethernet MAC VLAN Incl Register */
6907#define ETH_MACVIR_VLTI_Pos (20U)
6908#define ETH_MACVIR_VLTI_Msk (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */
6909#define ETH_MACVIR_VLTI ETH_MACVIR_VLTI_Msk /* VLAN Tag Input */
6910#define ETH_MACVIR_CSVL_Pos (19U)
6911#define ETH_MACVIR_CSVL_Msk (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */
6912#define ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk /* C-VLAN or S-VLAN */
6913#define ETH_MACVIR_VLP_Pos (18U)
6914#define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */
6915#define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /* VLAN Priority Control */
6916#define ETH_MACVIR_VLC_Pos (16U)
6917#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
6918#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
6919#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
6920#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
6921#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
6922#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
6923#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U)
6924#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
6925#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
6926#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U)
6927#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
6928#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
6929#define ETH_MACVIR_VLT_Pos (0U)
6930#define ETH_MACVIR_VLT_Msk (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */
6931#define ETH_MACVIR_VLT ETH_MACVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
6932#define ETH_MACVIR_VLT_UP_Pos (13U)
6933#define ETH_MACVIR_VLT_UP_Msk (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */
6934#define ETH_MACVIR_VLT_UP ETH_MACVIR_VLT_UP_Msk /* User Priority */
6935#define ETH_MACVIR_VLT_CFIDEI_Pos (12U)
6936#define ETH_MACVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
6937#define ETH_MACVIR_VLT_CFIDEI ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
6938#define ETH_MACVIR_VLT_VID_Pos (0U)
6939#define ETH_MACVIR_VLT_VID_Msk (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */
6940#define ETH_MACVIR_VLT_VID ETH_MACVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
6941
6942/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */
6943#define ETH_MACIVIR_VLTI_Pos (20U)
6944#define ETH_MACIVIR_VLTI_Msk (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */
6945#define ETH_MACIVIR_VLTI ETH_MACIVIR_VLTI_Msk /* VLAN Tag Input */
6946#define ETH_MACIVIR_CSVL_Pos (19U)
6947#define ETH_MACIVIR_CSVL_Msk (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */
6948#define ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk /* C-VLAN or S-VLAN */
6949#define ETH_MACIVIR_VLP_Pos (18U)
6950#define ETH_MACIVIR_VLP_Msk (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */
6951#define ETH_MACIVIR_VLP ETH_MACIVIR_VLP_Msk /* VLAN Priority Control */
6952#define ETH_MACIVIR_VLC_Pos (16U)
6953#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
6954#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
6955#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
6956#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
6957#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
6958#define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
6959#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos (17U)
6960#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
6961#define ETH_MACIVIR_VLC_VLANTAGINSERT ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
6962#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos (16U)
6963#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
6964#define ETH_MACIVIR_VLC_VLANTAGREPLACE ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
6965#define ETH_MACIVIR_VLT_Pos (0U)
6966#define ETH_MACIVIR_VLT_Msk (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */
6967#define ETH_MACIVIR_VLT ETH_MACIVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
6968#define ETH_MACIVIR_VLT_UP_Pos (13U)
6969#define ETH_MACIVIR_VLT_UP_Msk (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */
6970#define ETH_MACIVIR_VLT_UP ETH_MACIVIR_VLT_UP_Msk /* User Priority */
6971#define ETH_MACIVIR_VLT_CFIDEI_Pos (12U)
6972#define ETH_MACIVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
6973#define ETH_MACIVIR_VLT_CFIDEI ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
6974#define ETH_MACIVIR_VLT_VID_Pos (0U)
6975#define ETH_MACIVIR_VLT_VID_Msk (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */
6976#define ETH_MACIVIR_VLT_VID ETH_MACIVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
6977
6978/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */
6979#define ETH_MACTFCR_PT_Pos (16U)
6980#define ETH_MACTFCR_PT_Msk (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */
6981#define ETH_MACTFCR_PT ETH_MACTFCR_PT_Msk /* Pause Time */
6982#define ETH_MACTFCR_DZPQ_Pos (7U)
6983#define ETH_MACTFCR_DZPQ_Msk (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */
6984#define ETH_MACTFCR_DZPQ ETH_MACTFCR_DZPQ_Msk /* Disable Zero-Quanta Pause */
6985#define ETH_MACTFCR_PLT_Pos (4U)
6986#define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
6987#define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
6988#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
6989#define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
6990#define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
6991#define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
6992#define ETH_MACTFCR_PLT_MINUS36_Pos (5U)
6993#define ETH_MACTFCR_PLT_MINUS36_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */
6994#define ETH_MACTFCR_PLT_MINUS36 ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
6995#define ETH_MACTFCR_PLT_MINUS144_Pos (4U)
6996#define ETH_MACTFCR_PLT_MINUS144_Msk (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */
6997#define ETH_MACTFCR_PLT_MINUS144 ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
6998#define ETH_MACTFCR_PLT_MINUS256_Pos (6U)
6999#define ETH_MACTFCR_PLT_MINUS256_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */
7000#define ETH_MACTFCR_PLT_MINUS256 ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
7001#define ETH_MACTFCR_PLT_MINUS512_Pos (4U)
7002#define ETH_MACTFCR_PLT_MINUS512_Msk (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */
7003#define ETH_MACTFCR_PLT_MINUS512 ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
7004#define ETH_MACTFCR_TFE_Pos (1U)
7005#define ETH_MACTFCR_TFE_Msk (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */
7006#define ETH_MACTFCR_TFE ETH_MACTFCR_TFE_Msk /* Transmit Flow Control Enable */
7007#define ETH_MACTFCR_FCB_Pos (0U)
7008#define ETH_MACTFCR_FCB_Msk (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */
7009#define ETH_MACTFCR_FCB ETH_MACTFCR_FCB_Msk /* Flow Control Busy or Backpressure Activate */
7010
7011/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */
7012#define ETH_MACRFCR_UP_Pos (1U)
7013#define ETH_MACRFCR_UP_Msk (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */
7014#define ETH_MACRFCR_UP ETH_MACRFCR_UP_Msk /* Unicast Pause Packet Detect */
7015#define ETH_MACRFCR_RFE_Pos (0U)
7016#define ETH_MACRFCR_RFE_Msk (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */
7017#define ETH_MACRFCR_RFE ETH_MACRFCR_RFE_Msk /* Receive Flow Control Enable */
7018
7019/* Bit definition for Ethernet MAC Interrupt Status Register */
7020#define ETH_MACISR_RXSTSIS_Pos (14U)
7021#define ETH_MACISR_RXSTSIS_Msk (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */
7022#define ETH_MACISR_RXSTSIS ETH_MACISR_RXSTSIS_Msk /* Receive Status Interrupt */
7023#define ETH_MACISR_TXSTSIS_Pos (13U)
7024#define ETH_MACISR_TXSTSIS_Msk (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */
7025#define ETH_MACISR_TXSTSIS ETH_MACISR_TXSTSIS_Msk /* Transmit Status Interrupt */
7026#define ETH_MACISR_TSIS_Pos (12U)
7027#define ETH_MACISR_TSIS_Msk (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */
7028#define ETH_MACISR_TSIS ETH_MACISR_TSIS_Msk /* Timestamp Interrupt Status */
7029#define ETH_MACISR_MMCTXIS_Pos (10U)
7030#define ETH_MACISR_MMCTXIS_Msk (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */
7031#define ETH_MACISR_MMCTXIS ETH_MACISR_MMCTXIS_Msk /* MMC Transmit Interrupt Status */
7032#define ETH_MACISR_MMCRXIS_Pos (9U)
7033#define ETH_MACISR_MMCRXIS_Msk (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */
7034#define ETH_MACISR_MMCRXIS ETH_MACISR_MMCRXIS_Msk /* MMC Receive Interrupt Status */
7035#define ETH_MACISR_MMCIS_Pos (8U)
7036#define ETH_MACISR_MMCIS_Msk (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */
7037#define ETH_MACISR_MMCIS ETH_MACISR_MMCIS_Msk /* MMC Interrupt Status */
7038#define ETH_MACISR_LPIIS_Pos (5U)
7039#define ETH_MACISR_LPIIS_Msk (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */
7040#define ETH_MACISR_LPIIS ETH_MACISR_LPIIS_Msk /* LPI Interrupt Status */
7041#define ETH_MACISR_PMTIS_Pos (4U)
7042#define ETH_MACISR_PMTIS_Msk (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */
7043#define ETH_MACISR_PMTIS ETH_MACISR_PMTIS_Msk /* PMT Interrupt Status */
7044#define ETH_MACISR_PHYIS_Pos (3U)
7045#define ETH_MACISR_PHYIS_Msk (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */
7046#define ETH_MACISR_PHYIS ETH_MACISR_PHYIS_Msk /* PHY Interrupt */
7047
7048/* Bit definition for Ethernet MAC Interrupt Enable Register */
7049#define ETH_MACIER_RXSTSIE_Pos (14U)
7050#define ETH_MACIER_RXSTSIE_Msk (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */
7051#define ETH_MACIER_RXSTSIE ETH_MACIER_RXSTSIE_Msk /* Receive Status Interrupt Enable */
7052#define ETH_MACIER_TXSTSIE_Pos (13U)
7053#define ETH_MACIER_TXSTSIE_Msk (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */
7054#define ETH_MACIER_TXSTSIE ETH_MACIER_TXSTSIE_Msk /* Transmit Status Interrupt Enable */
7055#define ETH_MACIER_TSIE_Pos (12U)
7056#define ETH_MACIER_TSIE_Msk (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */
7057#define ETH_MACIER_TSIE ETH_MACIER_TSIE_Msk /* Timestamp Interrupt Enable */
7058#define ETH_MACIER_LPIIE_Pos (5U)
7059#define ETH_MACIER_LPIIE_Msk (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */
7060#define ETH_MACIER_LPIIE ETH_MACIER_LPIIE_Msk /* LPI Interrupt Enable */
7061#define ETH_MACIER_PMTIE_Pos (4U)
7062#define ETH_MACIER_PMTIE_Msk (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */
7063#define ETH_MACIER_PMTIE ETH_MACIER_PMTIE_Msk /* PMT Interrupt Enable */
7064#define ETH_MACIER_PHYIE_Pos (3U)
7065#define ETH_MACIER_PHYIE_Msk (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */
7066#define ETH_MACIER_PHYIE ETH_MACIER_PHYIE_Msk /* PHY Interrupt Enable */
7067
7068/* Bit definition for Ethernet MAC Rx Tx Status Register */
7069#define ETH_MACRXTXSR_RWT_Pos (8U)
7070#define ETH_MACRXTXSR_RWT_Msk (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */
7071#define ETH_MACRXTXSR_RWT ETH_MACRXTXSR_RWT_Msk /* Receive Watchdog Timeout */
7072#define ETH_MACRXTXSR_EXCOL_Pos (5U)
7073#define ETH_MACRXTXSR_EXCOL_Msk (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */
7074#define ETH_MACRXTXSR_EXCOL ETH_MACRXTXSR_EXCOL_Msk /* Excessive Collisions */
7075#define ETH_MACRXTXSR_LCOL_Pos (4U)
7076#define ETH_MACRXTXSR_LCOL_Msk (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */
7077#define ETH_MACRXTXSR_LCOL ETH_MACRXTXSR_LCOL_Msk /* Late Collision */
7078#define ETH_MACRXTXSR_EXDEF_Pos (3U)
7079#define ETH_MACRXTXSR_EXDEF_Msk (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */
7080#define ETH_MACRXTXSR_EXDEF ETH_MACRXTXSR_EXDEF_Msk /* Excessive Deferral */
7081#define ETH_MACRXTXSR_LCARR_Pos (2U)
7082#define ETH_MACRXTXSR_LCARR_Msk (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */
7083#define ETH_MACRXTXSR_LCARR ETH_MACRXTXSR_LCARR_Msk /* Loss of Carrier */
7084#define ETH_MACRXTXSR_NCARR_Pos (1U)
7085#define ETH_MACRXTXSR_NCARR_Msk (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */
7086#define ETH_MACRXTXSR_NCARR ETH_MACRXTXSR_NCARR_Msk /* No Carrier */
7087#define ETH_MACRXTXSR_TJT_Pos (0U)
7088#define ETH_MACRXTXSR_TJT_Msk (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */
7089#define ETH_MACRXTXSR_TJT ETH_MACRXTXSR_TJT_Msk /* Transmit Jabber Timeout */
7090
7091/* Bit definition for Ethernet MAC PMT Control Status Register */
7092#define ETH_MACPCSR_RWKFILTRST_Pos (31U)
7093#define ETH_MACPCSR_RWKFILTRST_Msk (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */
7094#define ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
7095#define ETH_MACPCSR_RWKPTR_Pos (24U)
7096#define ETH_MACPCSR_RWKPTR_Msk (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */
7097#define ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk /* Remote Wake-up FIFO Pointer */
7098#define ETH_MACPCSR_RWKPFE_Pos (10U)
7099#define ETH_MACPCSR_RWKPFE_Msk (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */
7100#define ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk /* Remote Wake-up Packet Forwarding Enable */
7101#define ETH_MACPCSR_GLBLUCAST_Pos (9U)
7102#define ETH_MACPCSR_GLBLUCAST_Msk (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */
7103#define ETH_MACPCSR_GLBLUCAST ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
7104#define ETH_MACPCSR_RWKPRCVD_Pos (6U)
7105#define ETH_MACPCSR_RWKPRCVD_Msk (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */
7106#define ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
7107#define ETH_MACPCSR_MGKPRCVD_Pos (5U)
7108#define ETH_MACPCSR_MGKPRCVD_Msk (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */
7109#define ETH_MACPCSR_MGKPRCVD ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
7110#define ETH_MACPCSR_RWKPKTEN_Pos (2U)
7111#define ETH_MACPCSR_RWKPKTEN_Msk (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */
7112#define ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
7113#define ETH_MACPCSR_MGKPKTEN_Pos (1U)
7114#define ETH_MACPCSR_MGKPKTEN_Msk (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */
7115#define ETH_MACPCSR_MGKPKTEN ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
7116#define ETH_MACPCSR_PWRDWN_Pos (0U)
7117#define ETH_MACPCSR_PWRDWN_Msk (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */
7118#define ETH_MACPCSR_PWRDWN ETH_MACPCSR_PWRDWN_Msk /* Power Down */
7119
7120/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */
7121#define ETH_MACRWUPFR_D_Pos (0U)
7122#define ETH_MACRWUPFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */
7123#define ETH_MACRWUPFR_D ETH_MACRWUPFR_D_Msk /* Wake-up Packet filter register data */
7124
7125/* Bit definition for Ethernet MAC LPI Control Status Register */
7126#define ETH_MACLCSR_LPITCSE_Pos (21U)
7127#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */
7128#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */
7129#define ETH_MACLCSR_LPITE_Pos (20U)
7130#define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */
7131#define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /* LPI Timer Enable */
7132#define ETH_MACLCSR_LPITXA_Pos (19U)
7133#define ETH_MACLCSR_LPITXA_Msk (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */
7134#define ETH_MACLCSR_LPITXA ETH_MACLCSR_LPITXA_Msk /* LPI Tx Automate */
7135#define ETH_MACLCSR_PLS_Pos (17U)
7136#define ETH_MACLCSR_PLS_Msk (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */
7137#define ETH_MACLCSR_PLS ETH_MACLCSR_PLS_Msk /* PHY Link Status */
7138#define ETH_MACLCSR_LPIEN_Pos (16U)
7139#define ETH_MACLCSR_LPIEN_Msk (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */
7140#define ETH_MACLCSR_LPIEN ETH_MACLCSR_LPIEN_Msk /* LPI Enable */
7141#define ETH_MACLCSR_RLPIST_Pos (9U)
7142#define ETH_MACLCSR_RLPIST_Msk (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */
7143#define ETH_MACLCSR_RLPIST ETH_MACLCSR_RLPIST_Msk /* Receive LPI State */
7144#define ETH_MACLCSR_TLPIST_Pos (8U)
7145#define ETH_MACLCSR_TLPIST_Msk (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */
7146#define ETH_MACLCSR_TLPIST ETH_MACLCSR_TLPIST_Msk /* Transmit LPI State */
7147#define ETH_MACLCSR_RLPIEX_Pos (3U)
7148#define ETH_MACLCSR_RLPIEX_Msk (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */
7149#define ETH_MACLCSR_RLPIEX ETH_MACLCSR_RLPIEX_Msk /* Receive LPI Exit */
7150#define ETH_MACLCSR_RLPIEN_Pos (2U)
7151#define ETH_MACLCSR_RLPIEN_Msk (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */
7152#define ETH_MACLCSR_RLPIEN ETH_MACLCSR_RLPIEN_Msk /* Receive LPI Entry */
7153#define ETH_MACLCSR_TLPIEX_Pos (1U)
7154#define ETH_MACLCSR_TLPIEX_Msk (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */
7155#define ETH_MACLCSR_TLPIEX ETH_MACLCSR_TLPIEX_Msk /* Transmit LPI Exit */
7156#define ETH_MACLCSR_TLPIEN_Pos (0U)
7157#define ETH_MACLCSR_TLPIEN_Msk (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */
7158#define ETH_MACLCSR_TLPIEN ETH_MACLCSR_TLPIEN_Msk /* Transmit LPI Entry */
7159
7160/* Bit definition for Ethernet MAC LPI Timers Control Register */
7161#define ETH_MACLTCR_LST_Pos (16U)
7162#define ETH_MACLTCR_LST_Msk (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */
7163#define ETH_MACLTCR_LST ETH_MACLTCR_LST_Msk /* LPI LS TIMER */
7164#define ETH_MACLTCR_TWT_Pos (0U)
7165#define ETH_MACLTCR_TWT_Msk (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */
7166#define ETH_MACLTCR_TWT ETH_MACLTCR_TWT_Msk /* LPI TW TIMER */
7167
7168/* Bit definition for Ethernet MAC LPI Entry Timer Register */
7169#define ETH_MACLETR_LPIET_Pos (0U)
7170#define ETH_MACLETR_LPIET_Msk (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */
7171#define ETH_MACLETR_LPIET ETH_MACLETR_LPIET_Msk /* LPI Entry Timer */
7172
7173/* Bit definition for Ethernet MAC 1US Tic Counter Register */
7174#define ETH_MAC1USTCR_TIC1USCNTR_Pos (0U)
7175#define ETH_MAC1USTCR_TIC1USCNTR_Msk (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */
7176#define ETH_MAC1USTCR_TIC1USCNTR ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
7177
7178/* Bit definition for Ethernet MAC Version Register */
7179#define ETH_MACVR_USERVER_Pos (8U)
7180#define ETH_MACVR_USERVER_Msk (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */
7181#define ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk /* User-defined Version */
7182#define ETH_MACVR_SNPSVER_Pos (0U)
7183#define ETH_MACVR_SNPSVER_Msk (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */
7184#define ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk /* Synopsys-defined Version */
7185
7186/* Bit definition for Ethernet MAC Debug Register */
7187#define ETH_MACDR_TFCSTS_Pos (17U)
7188#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
7189#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
7190#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
7191#define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
7192#define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
7193#define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
7194#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos (18U)
7195#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */
7196#define ETH_MACDR_TFCSTS_GENERATEPCP ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
7197#define ETH_MACDR_TFCSTS_TRASFERIP_Pos (17U)
7198#define ETH_MACDR_TFCSTS_TRASFERIP_Msk (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */
7199#define ETH_MACDR_TFCSTS_TRASFERIP ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
7200#define ETH_MACDR_TPESTS_Pos (16U)
7201#define ETH_MACDR_TPESTS_Msk (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */
7202#define ETH_MACDR_TPESTS ETH_MACDR_TPESTS_Msk /* MAC Receive Packet Controller FIFO Status */
7203#define ETH_MACDR_RFCFCSTS_Pos (1U)
7204#define ETH_MACDR_RFCFCSTS_Msk (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */
7205#define ETH_MACDR_RFCFCSTS ETH_MACDR_RFCFCSTS_Msk /* MAC MII Transmit Protocol Engine Status */
7206#define ETH_MACDR_RPESTS_Pos (0U)
7207#define ETH_MACDR_RPESTS_Msk (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */
7208#define ETH_MACDR_RPESTS ETH_MACDR_RPESTS_Msk /* MAC MII Receive Protocol Engine Status */
7209
7210/* Bit definition for Ethernet MAC HW Feature0 Register */
7211#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
7212#define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
7213#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
7214#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */
7215#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
7216#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
7217#define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
7218#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos (28U)
7219#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */
7220#define ETH_MACHWF0R_ACTPHYSEL_REVMII ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */
7221#define ETH_MACHWF0R_SAVLANINS_Pos (27U)
7222#define ETH_MACHWF0R_SAVLANINS_Msk (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */
7223#define ETH_MACHWF0R_SAVLANINS ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
7224#define ETH_MACHWF0R_TSSTSSEL_Pos (25U)
7225#define ETH_MACHWF0R_TSSTSSEL_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */
7226#define ETH_MACHWF0R_TSSTSSEL ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
7227#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos (25U)
7228#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */
7229#define ETH_MACHWF0R_TSSTSSEL_INTERNAL ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
7230#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos (26U)
7231#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */
7232#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
7233#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos (25U)
7234#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */
7235#define ETH_MACHWF0R_TSSTSSEL_BOTH ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
7236#define ETH_MACHWF0R_MACADR64SEL_Pos (24U)
7237#define ETH_MACHWF0R_MACADR64SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */
7238#define ETH_MACHWF0R_MACADR64SEL ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
7239#define ETH_MACHWF0R_MACADR32SEL_Pos (23U)
7240#define ETH_MACHWF0R_MACADR32SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */
7241#define ETH_MACHWF0R_MACADR32SEL ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
7242#define ETH_MACHWF0R_ADDMACADRSEL_Pos (18U)
7243#define ETH_MACHWF0R_ADDMACADRSEL_Msk (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */
7244#define ETH_MACHWF0R_ADDMACADRSEL ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
7245#define ETH_MACHWF0R_RXCOESEL_Pos (16U)
7246#define ETH_MACHWF0R_RXCOESEL_Msk (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */
7247#define ETH_MACHWF0R_RXCOESEL ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
7248#define ETH_MACHWF0R_TXCOESEL_Pos (14U)
7249#define ETH_MACHWF0R_TXCOESEL_Msk (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */
7250#define ETH_MACHWF0R_TXCOESEL ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
7251#define ETH_MACHWF0R_EEESEL_Pos (13U)
7252#define ETH_MACHWF0R_EEESEL_Msk (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */
7253#define ETH_MACHWF0R_EEESEL ETH_MACHWF0R_EEESEL_Msk /* Energy Efficient Ethernet Enabled */
7254#define ETH_MACHWF0R_TSSEL_Pos (12U)
7255#define ETH_MACHWF0R_TSSEL_Msk (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */
7256#define ETH_MACHWF0R_TSSEL ETH_MACHWF0R_TSSEL_Msk /* IEEE 1588-2008 Timestamp Enabled */
7257#define ETH_MACHWF0R_ARPOFFSEL_Pos (9U)
7258#define ETH_MACHWF0R_ARPOFFSEL_Msk (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */
7259#define ETH_MACHWF0R_ARPOFFSEL ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
7260#define ETH_MACHWF0R_MMCSEL_Pos (8U)
7261#define ETH_MACHWF0R_MMCSEL_Msk (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */
7262#define ETH_MACHWF0R_MMCSEL ETH_MACHWF0R_MMCSEL_Msk /* RMON Module Enable */
7263#define ETH_MACHWF0R_MGKSEL_Pos (7U)
7264#define ETH_MACHWF0R_MGKSEL_Msk (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */
7265#define ETH_MACHWF0R_MGKSEL ETH_MACHWF0R_MGKSEL_Msk /* PMT Magic Packet Enable */
7266#define ETH_MACHWF0R_RWKSEL_Pos (6U)
7267#define ETH_MACHWF0R_RWKSEL_Msk (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */
7268#define ETH_MACHWF0R_RWKSEL ETH_MACHWF0R_RWKSEL_Msk /* PMT Remote Wake-up Packet Enable */
7269#define ETH_MACHWF0R_SMASEL_Pos (5U)
7270#define ETH_MACHWF0R_SMASEL_Msk (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */
7271#define ETH_MACHWF0R_SMASEL ETH_MACHWF0R_SMASEL_Msk /* SMA (MDIO) Interface */
7272#define ETH_MACHWF0R_VLHASH_Pos (4U)
7273#define ETH_MACHWF0R_VLHASH_Msk (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */
7274#define ETH_MACHWF0R_VLHASH ETH_MACHWF0R_VLHASH_Msk /* VLAN Hash Filter Selected */
7275#define ETH_MACHWF0R_PCSSEL_Pos (3U)
7276#define ETH_MACHWF0R_PCSSEL_Msk (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */
7277#define ETH_MACHWF0R_PCSSEL ETH_MACHWF0R_PCSSEL_Msk /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
7278#define ETH_MACHWF0R_HDSEL_Pos (2U)
7279#define ETH_MACHWF0R_HDSEL_Msk (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */
7280#define ETH_MACHWF0R_HDSEL ETH_MACHWF0R_HDSEL_Msk /* Half-duplex Support */
7281#define ETH_MACHWF0R_GMIISEL_Pos (1U)
7282#define ETH_MACHWF0R_GMIISEL_Msk (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */
7283#define ETH_MACHWF0R_GMIISEL ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
7284#define ETH_MACHWF0R_MIISEL_Pos (0U)
7285#define ETH_MACHWF0R_MIISEL_Msk (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */
7286#define ETH_MACHWF0R_MIISEL ETH_MACHWF0R_MIISEL_Msk /* 10 or 100 Mbps Support */
7287
7288/* Bit definition for Ethernet MAC HW Feature1 Register */
7289#define ETH_MACHWF1R_L3L4FNUM_Pos (27U)
7290#define ETH_MACHWF1R_L3L4FNUM_Msk (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */
7291#define ETH_MACHWF1R_L3L4FNUM ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
7292#define ETH_MACHWF1R_HASHTBLSZ_Pos (24U)
7293#define ETH_MACHWF1R_HASHTBLSZ_Msk (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */
7294#define ETH_MACHWF1R_HASHTBLSZ ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
7295#define ETH_MACHWF1R_AVSEL_Pos (20U)
7296#define ETH_MACHWF1R_AVSEL_Msk (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */
7297#define ETH_MACHWF1R_AVSEL ETH_MACHWF1R_AVSEL_Msk /* AV Feature Enabled */
7298#define ETH_MACHWF1R_DBGMEMA_Pos (19U)
7299#define ETH_MACHWF1R_DBGMEMA_Msk (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */
7300#define ETH_MACHWF1R_DBGMEMA ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
7301#define ETH_MACHWF1R_TSOEN_Pos (18U)
7302#define ETH_MACHWF1R_TSOEN_Msk (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */
7303#define ETH_MACHWF1R_TSOEN ETH_MACHWF1R_TSOEN_Msk /* TCP Segmentation Offload Enable */
7304#define ETH_MACHWF1R_SPHEN_Pos (17U)
7305#define ETH_MACHWF1R_SPHEN_Msk (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */
7306#define ETH_MACHWF1R_SPHEN ETH_MACHWF1R_SPHEN_Msk /* Split Header Feature Enable */
7307#define ETH_MACHWF1R_DCBEN_Pos (16U)
7308#define ETH_MACHWF1R_DCBEN_Msk (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */
7309#define ETH_MACHWF1R_DCBEN ETH_MACHWF1R_DCBEN_Msk /* DCB Feature Enable */
7310#define ETH_MACHWF1R_ADDR64_Pos (14U)
7311#define ETH_MACHWF1R_ADDR64_Msk (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */
7312#define ETH_MACHWF1R_ADDR64 ETH_MACHWF1R_ADDR64_Msk /* Address Width */
7313#define ETH_MACHWF1R_ADDR64_32 (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */
7314#define ETH_MACHWF1R_ADDR64_40 (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */
7315#define ETH_MACHWF1R_ADDR64_48 (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */
7316#define ETH_MACHWF1R_ADVTHWORD_Pos (13U)
7317#define ETH_MACHWF1R_ADVTHWORD_Msk (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */
7318#define ETH_MACHWF1R_ADVTHWORD ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
7319#define ETH_MACHWF1R_PTOEN_Pos (12U)
7320#define ETH_MACHWF1R_PTOEN_Msk (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */
7321#define ETH_MACHWF1R_PTOEN ETH_MACHWF1R_PTOEN_Msk /* PTP Offload Enable */
7322#define ETH_MACHWF1R_OSTEN_Pos (11U)
7323#define ETH_MACHWF1R_OSTEN_Msk (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */
7324#define ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk /* One-Step Timestamping Enable */
7325#define ETH_MACHWF1R_TXFIFOSIZE_Pos (6U)
7326#define ETH_MACHWF1R_TXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */
7327#define ETH_MACHWF1R_TXFIFOSIZE ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
7328#define ETH_MACHWF1R_RXFIFOSIZE_Pos (0U)
7329#define ETH_MACHWF1R_RXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */
7330#define ETH_MACHWF1R_RXFIFOSIZE ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
7331
7332/* Bit definition for Ethernet MAC HW Feature2 Register */
7333#define ETH_MACHWF2R_AUXSNAPNUM_Pos (28U)
7334#define ETH_MACHWF2R_AUXSNAPNUM_Msk (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */
7335#define ETH_MACHWF2R_AUXSNAPNUM ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
7336#define ETH_MACHWF2R_PPSOUTNUM_Pos (24U)
7337#define ETH_MACHWF2R_PPSOUTNUM_Msk (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */
7338#define ETH_MACHWF2R_PPSOUTNUM ETH_MACHWF2R_PPSOUTNUM_Msk /* Number of PPS Outputs */
7339#define ETH_MACHWF2R_TXCHCNT_Pos (18U)
7340#define ETH_MACHWF2R_TXCHCNT_Msk (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */
7341#define ETH_MACHWF2R_TXCHCNT ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
7342#define ETH_MACHWF2R_RXCHCNT_Pos (13U)
7343#define ETH_MACHWF2R_RXCHCNT_Msk (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */
7344#define ETH_MACHWF2R_RXCHCNT ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
7345#define ETH_MACHWF2R_TXQCNT_Pos (6U)
7346#define ETH_MACHWF2R_TXQCNT_Msk (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */
7347#define ETH_MACHWF2R_TXQCNT ETH_MACHWF2R_TXQCNT_Msk /* Number of MTL Transmit Queues */
7348#define ETH_MACHWF2R_RXQCNT_Pos (0U)
7349#define ETH_MACHWF2R_RXQCNT_Msk (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */
7350#define ETH_MACHWF2R_RXQCNT ETH_MACHWF2R_RXQCNT_Msk /* Number of MTL Receive Queues */
7351
7352/* Bit definition for Ethernet MAC MDIO Address Register */
7353#define ETH_MACMDIOAR_PSE_Pos (27U)
7354#define ETH_MACMDIOAR_PSE_Msk (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */
7355#define ETH_MACMDIOAR_PSE ETH_MACMDIOAR_PSE_Msk /* Preamble Suppression Enable */
7356#define ETH_MACMDIOAR_BTB_Pos (26U)
7357#define ETH_MACMDIOAR_BTB_Msk (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */
7358#define ETH_MACMDIOAR_BTB ETH_MACMDIOAR_BTB_Msk /* Back to Back transactions */
7359#define ETH_MACMDIOAR_PA_Pos (21U)
7360#define ETH_MACMDIOAR_PA_Msk (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */
7361#define ETH_MACMDIOAR_PA ETH_MACMDIOAR_PA_Msk /* Physical Layer Address */
7362#define ETH_MACMDIOAR_RDA_Pos (16U)
7363#define ETH_MACMDIOAR_RDA_Msk (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */
7364#define ETH_MACMDIOAR_RDA ETH_MACMDIOAR_RDA_Msk /* Register/Device Address */
7365#define ETH_MACMDIOAR_NTC_Pos (12U)
7366#define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */
7367#define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /* Number of Trailing Clocks */
7368#define ETH_MACMDIOAR_CR_Pos (8U)
7369#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
7370#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
7371#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */
7372#define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
7373#define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
7374#define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
7375#define ETH_MACMDIOAR_CR_DIV16_Pos (9U)
7376#define ETH_MACMDIOAR_CR_DIV16_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */
7377#define ETH_MACMDIOAR_CR_DIV16 ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
7378#define ETH_MACMDIOAR_CR_DIV26_Pos (8U)
7379#define ETH_MACMDIOAR_CR_DIV26_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */
7380#define ETH_MACMDIOAR_CR_DIV26 ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
7381#define ETH_MACMDIOAR_CR_DIV102_Pos (10U)
7382#define ETH_MACMDIOAR_CR_DIV102_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */
7383#define ETH_MACMDIOAR_CR_DIV102 ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
7384#define ETH_MACMDIOAR_CR_DIV124_Pos (8U)
7385#define ETH_MACMDIOAR_CR_DIV124_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */
7386#define ETH_MACMDIOAR_CR_DIV124 ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
7387#define ETH_MACMDIOAR_CR_DIV4AR_Pos (11U)
7388#define ETH_MACMDIOAR_CR_DIV4AR_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */
7389#define ETH_MACMDIOAR_CR_DIV4AR ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
7390#define ETH_MACMDIOAR_CR_DIV6AR_Pos (8U)
7391#define ETH_MACMDIOAR_CR_DIV6AR_Msk (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */
7392#define ETH_MACMDIOAR_CR_DIV6AR ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
7393#define ETH_MACMDIOAR_CR_DIV8AR_Pos (9U)
7394#define ETH_MACMDIOAR_CR_DIV8AR_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */
7395#define ETH_MACMDIOAR_CR_DIV8AR ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
7396#define ETH_MACMDIOAR_CR_DIV10AR_Pos (8U)
7397#define ETH_MACMDIOAR_CR_DIV10AR_Msk (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */
7398#define ETH_MACMDIOAR_CR_DIV10AR ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
7399#define ETH_MACMDIOAR_CR_DIV12AR_Pos (10U)
7400#define ETH_MACMDIOAR_CR_DIV12AR_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */
7401#define ETH_MACMDIOAR_CR_DIV12AR ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
7402#define ETH_MACMDIOAR_CR_DIV14AR_Pos (8U)
7403#define ETH_MACMDIOAR_CR_DIV14AR_Msk (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */
7404#define ETH_MACMDIOAR_CR_DIV14AR ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
7405#define ETH_MACMDIOAR_CR_DIV16AR_Pos (9U)
7406#define ETH_MACMDIOAR_CR_DIV16AR_Msk (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */
7407#define ETH_MACMDIOAR_CR_DIV16AR ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
7408#define ETH_MACMDIOAR_CR_DIV18AR_Pos (8U)
7409#define ETH_MACMDIOAR_CR_DIV18AR_Msk (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */
7410#define ETH_MACMDIOAR_CR_DIV18AR ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
7411#define ETH_MACMDIOAR_SKAP_Pos (4U)
7412#define ETH_MACMDIOAR_SKAP_Msk (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */
7413#define ETH_MACMDIOAR_SKAP ETH_MACMDIOAR_SKAP_Msk /* Skip Address Packet */
7414#define ETH_MACMDIOAR_MOC_Pos (2U)
7415#define ETH_MACMDIOAR_MOC_Msk (0x3UL << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */
7416#define ETH_MACMDIOAR_MOC ETH_MACMDIOAR_MOC_Msk /* MII Operation Command */
7417#define ETH_MACMDIOAR_MOC_WR_Pos (2U)
7418#define ETH_MACMDIOAR_MOC_WR_Msk (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */
7419#define ETH_MACMDIOAR_MOC_WR ETH_MACMDIOAR_MOC_WR_Msk /* Write */
7420#define ETH_MACMDIOAR_MOC_PRDIA_Pos (3U)
7421#define ETH_MACMDIOAR_MOC_PRDIA_Msk (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */
7422#define ETH_MACMDIOAR_MOC_PRDIA ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */
7423#define ETH_MACMDIOAR_MOC_RD_Pos (2U)
7424#define ETH_MACMDIOAR_MOC_RD_Msk (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */
7425#define ETH_MACMDIOAR_MOC_RD ETH_MACMDIOAR_MOC_RD_Msk /* Read */
7426#define ETH_MACMDIOAR_C45E_Pos (1U)
7427#define ETH_MACMDIOAR_C45E_Msk (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */
7428#define ETH_MACMDIOAR_C45E ETH_MACMDIOAR_C45E_Msk /* Clause 45 PHY Enable */
7429#define ETH_MACMDIOAR_MB_Pos (0U)
7430#define ETH_MACMDIOAR_MB_Msk (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */
7431#define ETH_MACMDIOAR_MB ETH_MACMDIOAR_MB_Msk /* MII Busy */
7432
7433/* Bit definition for Ethernet MAC MDIO Data Register */
7434#define ETH_MACMDIODR_RA_Pos (16U)
7435#define ETH_MACMDIODR_RA_Msk (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */
7436#define ETH_MACMDIODR_RA ETH_MACMDIODR_RA_Msk /* Register Address */
7437#define ETH_MACMDIODR_MD_Pos (0U)
7438#define ETH_MACMDIODR_MD_Msk (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */
7439#define ETH_MACMDIODR_MD ETH_MACMDIODR_MD_Msk /* MII Data */
7440
7441/* Bit definition for Ethernet ARP Address Register */
7442#define ETH_MACARPAR_ARPPA_Pos (0U)
7443#define ETH_MACARPAR_ARPPA_Msk (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */
7444#define ETH_MACARPAR_ARPPA ETH_MACARPAR_ARPPA_Msk /* ARP Protocol Address */
7445
7446/* Bit definition for Ethernet MAC Address 0 High Register */
7447#define ETH_MACA0HR_AE_Pos (31U)
7448#define ETH_MACA0HR_AE_Msk (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */
7449#define ETH_MACA0HR_AE ETH_MACA0HR_AE_Msk /* Address Enable*/
7450#define ETH_MACA0HR_ADDRHI_Pos (0U)
7451#define ETH_MACA0HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */
7452#define ETH_MACA0HR_ADDRHI ETH_MACA0HR_ADDRHI_Msk /* MAC Address 0*/
7453
7454/* Bit definition for Ethernet MAC Address 0 Low Register */
7455#define ETH_MACA0LR_ADDRLO_Pos (0U)
7456#define ETH_MACA0LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
7457#define ETH_MACA0LR_ADDRLO ETH_MACA0LR_ADDRLO_Msk /* MAC Address 0*/
7458
7459/* Bit definition for Ethernet MAC Address 1 High Register */
7460#define ETH_MACA1HR_AE_Pos (31U)
7461#define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
7462#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address Enable*/
7463#define ETH_MACA1HR_SA_Pos (30U)
7464#define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
7465#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source Address */
7466#define ETH_MACA1HR_MBC_Pos (24U)
7467#define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
7468#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask Byte Control */
7469#define ETH_MACA1HR_ADDRHI_Pos (0U)
7470#define ETH_MACA1HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */
7471#define ETH_MACA1HR_ADDRHI ETH_MACA1HR_ADDRHI_Msk /* MAC Address 1*/
7472
7473/* Bit definition for Ethernet MAC Address 1 Low Register */
7474#define ETH_MACA1LR_ADDRLO_Pos (0U)
7475#define ETH_MACA1LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
7476#define ETH_MACA1LR_ADDRLO ETH_MACA1LR_ADDRLO_Msk /* MAC Address 1*/
7477
7478/* Bit definition for Ethernet MAC Address 2 High Register */
7479#define ETH_MACA2HR_AE_Pos (31U)
7480#define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
7481#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address Enable*/
7482#define ETH_MACA2HR_SA_Pos (30U)
7483#define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
7484#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source Address */
7485#define ETH_MACA2HR_MBC_Pos (24U)
7486#define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
7487#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask Byte Control */
7488#define ETH_MACA2HR_ADDRHI_Pos (0U)
7489#define ETH_MACA2HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */
7490#define ETH_MACA2HR_ADDRHI ETH_MACA2HR_ADDRHI_Msk /* MAC Address 1*/
7491
7492/* Bit definition for Ethernet MAC Address 2 Low Register */
7493#define ETH_MACA2LR_ADDRLO_Pos (0U)
7494#define ETH_MACA2LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
7495#define ETH_MACA2LR_ADDRLO ETH_MACA2LR_ADDRLO_Msk /* MAC Address 2*/
7496
7497/* Bit definition for Ethernet MAC Address 3 High Register */
7498#define ETH_MACA3HR_AE_Pos (31U)
7499#define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
7500#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address Enable*/
7501#define ETH_MACA3HR_SA_Pos (30U)
7502#define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
7503#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source Address */
7504#define ETH_MACA3HR_MBC_Pos (24U)
7505#define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
7506#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask Byte Control */
7507#define ETH_MACA3HR_ADDRHI_Pos (0U)
7508#define ETH_MACA3HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */
7509#define ETH_MACA3HR_ADDRHI ETH_MACA3HR_ADDRHI_Msk /* MAC Address 1*/
7510
7511/* Bit definition for Ethernet MAC Address 3 Low Register */
7512#define ETH_MACA3LR_ADDRLO_Pos (0U)
7513#define ETH_MACA3LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
7514#define ETH_MACA3LR_ADDRLO ETH_MACA3LR_ADDRLO_Msk /* MAC Address 3*/
7515
7516/* Bit definition for Ethernet MAC Address High Register */
7517#define ETH_MACAHR_AE_Pos (31U)
7518#define ETH_MACAHR_AE_Msk (0x1UL << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */
7519#define ETH_MACAHR_AE ETH_MACAHR_AE_Msk /* Address enable */
7520#define ETH_MACAHR_SA_Pos (30U)
7521#define ETH_MACAHR_SA_Msk (0x1UL << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */
7522#define ETH_MACAHR_SA ETH_MACAHR_SA_Msk /* Source address */
7523#define ETH_MACAHR_MBC_Pos (24U)
7524#define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
7525#define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
7526#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
7527#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
7528#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
7529#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
7530#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
7531#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
7532#define ETH_MACAHR_MACAH_Pos (0U)
7533#define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
7534#define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
7535
7536/* Bit definition for Ethernet MAC Address Low Register */
7537#define ETH_MACALR_MACAL_Pos (0U)
7538#define ETH_MACALR_MACAL_Msk (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */
7539#define ETH_MACALR_MACAL ETH_MACALR_MACAL_Msk /* MAC address low */
7540
7541/* Bit definition for Ethernet MMC Control Register */
7542#define ETH_MMCCR_UCDBC_Pos (8U)
7543#define ETH_MMCCR_UCDBC_Msk (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */
7544#define ETH_MMCCR_UCDBC ETH_MMCCR_UCDBC_Msk /* Update MMC Counters for Dropped Broadcast Packets */
7545#define ETH_MMCCR_CNTPRSTLVL_Pos (5U)
7546#define ETH_MMCCR_CNTPRSTLVL_Msk (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */
7547#define ETH_MMCCR_CNTPRSTLVL ETH_MMCCR_CNTPRSTLVL_Msk /* Full-Half Preset */
7548#define ETH_MMCCR_CNTPRST_Pos (4U)
7549#define ETH_MMCCR_CNTPRST_Msk (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */
7550#define ETH_MMCCR_CNTPRST ETH_MMCCR_CNTPRST_Msk /* Counters Reset */
7551#define ETH_MMCCR_CNTFREEZ_Pos (3U)
7552#define ETH_MMCCR_CNTFREEZ_Msk (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */
7553#define ETH_MMCCR_CNTFREEZ ETH_MMCCR_CNTFREEZ_Msk /* MMC Counter Freeze */
7554#define ETH_MMCCR_RSTONRD_Pos (2U)
7555#define ETH_MMCCR_RSTONRD_Msk (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */
7556#define ETH_MMCCR_RSTONRD ETH_MMCCR_RSTONRD_Msk /* Reset On Read */
7557#define ETH_MMCCR_CNTSTOPRO_Pos (1U)
7558#define ETH_MMCCR_CNTSTOPRO_Msk (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */
7559#define ETH_MMCCR_CNTSTOPRO ETH_MMCCR_CNTSTOPRO_Msk /* Counter Stop Rollover */
7560#define ETH_MMCCR_CNTRST_Pos (0U)
7561#define ETH_MMCCR_CNTRST_Msk (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */
7562#define ETH_MMCCR_CNTRST ETH_MMCCR_CNTRST_Msk /* Counters Reset */
7563
7564/* Bit definition for Ethernet MMC Rx Interrupt Register */
7565#define ETH_MMCRIR_RXLPITRCIS_Pos (27U)
7566#define ETH_MMCRIR_RXLPITRCIS_Msk (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */
7567#define ETH_MMCRIR_RXLPITRCIS ETH_MMCRIR_RXLPITRCIS_Msk /* MMC Receive LPI transition counter interrupt status */
7568#define ETH_MMCRIR_RXLPIUSCIS_Pos (26U)
7569#define ETH_MMCRIR_RXLPIUSCIS_Msk (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */
7570#define ETH_MMCRIR_RXLPIUSCIS ETH_MMCRIR_RXLPIUSCIS_Msk /* MMC Receive LPI microsecond counter interrupt status */
7571#define ETH_MMCRIR_RXUCGPIS_Pos (17U)
7572#define ETH_MMCRIR_RXUCGPIS_Msk (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */
7573#define ETH_MMCRIR_RXUCGPIS ETH_MMCRIR_RXUCGPIS_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Status */
7574#define ETH_MMCRIR_RXALGNERPIS_Pos (6U)
7575#define ETH_MMCRIR_RXALGNERPIS_Msk (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */
7576#define ETH_MMCRIR_RXALGNERPIS ETH_MMCRIR_RXALGNERPIS_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Status */
7577#define ETH_MMCRIR_RXCRCERPIS_Pos (5U)
7578#define ETH_MMCRIR_RXCRCERPIS_Msk (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */
7579#define ETH_MMCRIR_RXCRCERPIS ETH_MMCRIR_RXCRCERPIS_Msk /* MMC Receive CRC Error Packet Counter Interrupt Status */
7580
7581/* Bit definition for Ethernet MMC Tx Interrupt Register */
7582#define ETH_MMCTIR_TXLPITRCIS_Pos (27U)
7583#define ETH_MMCTIR_TXLPITRCIS_Msk (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */
7584#define ETH_MMCTIR_TXLPITRCIS ETH_MMCTIR_TXLPITRCIS_Msk /* MMC Transmit LPI transition counter interrupt status */
7585#define ETH_MMCTIR_TXLPIUSCIS_Pos (26U)
7586#define ETH_MMCTIR_TXLPIUSCIS_Msk (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */
7587#define ETH_MMCTIR_TXLPIUSCIS ETH_MMCTIR_TXLPIUSCIS_Msk /* MMC Transmit LPI microsecond counter interrupt status */
7588#define ETH_MMCTIR_TXGPKTIS_Pos (21U)
7589#define ETH_MMCTIR_TXGPKTIS_Msk (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */
7590#define ETH_MMCTIR_TXGPKTIS ETH_MMCTIR_TXGPKTIS_Msk /* MMC Transmit Good Packet Counter Interrupt Status */
7591#define ETH_MMCTIR_TXMCOLGPIS_Pos (15U)
7592#define ETH_MMCTIR_TXMCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */
7593#define ETH_MMCTIR_TXMCOLGPIS ETH_MMCTIR_TXMCOLGPIS_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
7594#define ETH_MMCTIR_TXSCOLGPIS_Pos (14U)
7595#define ETH_MMCTIR_TXSCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */
7596#define ETH_MMCTIR_TXSCOLGPIS ETH_MMCTIR_TXSCOLGPIS_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */
7597
7598/* Bit definition for Ethernet MMC Rx interrupt Mask register */
7599#define ETH_MMCRIMR_RXLPITRCIM_Pos (27U)
7600#define ETH_MMCRIMR_RXLPITRCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */
7601#define ETH_MMCRIMR_RXLPITRCIM ETH_MMCRIMR_RXLPITRCIM_Msk /* MMC Receive LPI transition counter interrupt Mask */
7602#define ETH_MMCRIMR_RXLPIUSCIM_Pos (26U)
7603#define ETH_MMCRIMR_RXLPIUSCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */
7604#define ETH_MMCRIMR_RXLPIUSCIM ETH_MMCRIMR_RXLPIUSCIM_Msk /* MMC Receive LPI microsecond counter interrupt Mask */
7605#define ETH_MMCRIMR_RXUCGPIM_Pos (17U)
7606#define ETH_MMCRIMR_RXUCGPIM_Msk (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */
7607#define ETH_MMCRIMR_RXUCGPIM ETH_MMCRIMR_RXUCGPIM_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Mask */
7608#define ETH_MMCRIMR_RXALGNERPIM_Pos (6U)
7609#define ETH_MMCRIMR_RXALGNERPIM_Msk (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */
7610#define ETH_MMCRIMR_RXALGNERPIM ETH_MMCRIMR_RXALGNERPIM_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Mask */
7611#define ETH_MMCRIMR_RXCRCERPIM_Pos (5U)
7612#define ETH_MMCRIMR_RXCRCERPIM_Msk (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */
7613#define ETH_MMCRIMR_RXCRCERPIM ETH_MMCRIMR_RXCRCERPIM_Msk /* MMC Receive CRC Error Packet Counter Interrupt Mask */
7614
7615/* Bit definition for Ethernet MMC Tx Interrupt Mask Register */
7616#define ETH_MMCTIMR_TXLPITRCIM_Pos (27U)
7617#define ETH_MMCTIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */
7618#define ETH_MMCTIMR_TXLPITRCIM ETH_MMCTIMR_TXLPITRCIM_Msk /* MMC Transmit LPI transition counter interrupt Mask*/
7619#define ETH_MMCTIMR_TXLPIUSCIM_Pos (26U)
7620#define ETH_MMCTIMR_TXLPIUSCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */
7621#define ETH_MMCTIMR_TXLPIUSCIM ETH_MMCTIMR_TXLPIUSCIM_Msk /* MMC Transmit LPI microsecond counter interrupt Mask*/
7622#define ETH_MMCTIMR_TXGPKTIM_Pos (21U)
7623#define ETH_MMCTIMR_TXGPKTIM_Msk (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */
7624#define ETH_MMCTIMR_TXGPKTIM ETH_MMCTIMR_TXGPKTIM_Msk /* MMC Transmit Good Packet Counter Interrupt Mask*/
7625#define ETH_MMCTIMR_TXMCOLGPIM_Pos (15U)
7626#define ETH_MMCTIMR_TXMCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */
7627#define ETH_MMCTIMR_TXMCOLGPIM ETH_MMCTIMR_TXMCOLGPIM_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
7628#define ETH_MMCTIMR_TXSCOLGPIM_Pos (14U)
7629#define ETH_MMCTIMR_TXSCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */
7630#define ETH_MMCTIMR_TXSCOLGPIM ETH_MMCTIMR_TXSCOLGPIM_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
7631
7632/* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */
7633#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos (0U)
7634#define ETH_MMCTSCGPR_TXSNGLCOLG_msk (0xFFFFFFFFUL << ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */
7635#define ETH_MMCTSCGPR_TXSNGLCOLG ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */
7636
7637/* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */
7638#define ETH_MMCTMCGPR_TXMULTCOLG_Pos (0U)
7639#define ETH_MMCTMCGPR_TXMULTCOLG_msk (0xFFFFFFFFUL << ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */
7640#define ETH_MMCTMCGPR_TXMULTCOLG ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */
7641
7642/* Bit definition for Ethernet MMC Tx Packet Count Good Register */
7643#define ETH_MMCTPCGR_TXPKTG_Pos (0U)
7644#define ETH_MMCTPCGR_TXPKTG_msk (0xFFFFFFFFUL << ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */
7645#define ETH_MMCTPCGR_TXPKTG ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */
7646
7647/* Bit definition for Ethernet MMC Rx CRC Error Packets Register */
7648#define ETH_MMCRCRCEPR_RXCRCERR_Pos (0U)
7649#define ETH_MMCRCRCEPR_RXCRCERR_msk (0xFFFFFFFFUL << ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */
7650#define ETH_MMCRCRCEPR_RXCRCERR ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */
7651
7652/* Bit definition for Ethernet MMC Rx alignment error packets register */
7653#define ETH_MMCRAEPR_RXALGNERR_Pos (0U)
7654#define ETH_MMCRAEPR_RXALGNERR_msk (0xFFFFFFFFUL << ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */
7655#define ETH_MMCRAEPR_RXALGNERR ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */
7656
7657/* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */
7658#define ETH_MMCRUPGR_RXUCASTG_Pos (0U)
7659#define ETH_MMCRUPGR_RXUCASTG_msk (0xFFFFFFFFUL << ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */
7660#define ETH_MMCRUPGR_RXUCASTG ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */
7661
7662/* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */
7663#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos (0U)
7664#define ETH_MMCTLPIMSTR_TXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */
7665#define ETH_MMCTLPIMSTR_TXLPIUSC ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */
7666
7667/* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */
7668#define ETH_MMCTLPITCR_TXLPITRC_Pos (0U)
7669#define ETH_MMCTLPITCR_TXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */
7670#define ETH_MMCTLPITCR_TXLPITRC ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */
7671
7672/* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */
7673#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos (0U)
7674#define ETH_MMCRLPIMSTR_RXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */
7675#define ETH_MMCRLPIMSTR_RXLPIUSC ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */
7676
7677/* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */
7678#define ETH_MMCRLPITCR_RXLPITRC_Pos (0U)
7679#define ETH_MMCRLPITCR_RXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */
7680#define ETH_MMCRLPITCR_RXLPITRC ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */
7681
7682/* Bit definition for Ethernet MAC L3 L4 Control Register */
7683#define ETH_MACL3L4CR_L4DPIM_Pos (21U)
7684#define ETH_MACL3L4CR_L4DPIM_Msk (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */
7685#define ETH_MACL3L4CR_L4DPIM ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */
7686#define ETH_MACL3L4CR_L4DPM_Pos (20U)
7687#define ETH_MACL3L4CR_L4DPM_Msk (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */
7688#define ETH_MACL3L4CR_L4DPM ETH_MACL3L4CR_L4DPM_Msk /* Layer 4 Destination Port Match Enable */
7689#define ETH_MACL3L4CR_L4SPIM_Pos (19U)
7690#define ETH_MACL3L4CR_L4SPIM_Msk (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */
7691#define ETH_MACL3L4CR_L4SPIM ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */
7692#define ETH_MACL3L4CR_L4SPM_Pos (18U)
7693#define ETH_MACL3L4CR_L4SPM_Msk (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */
7694#define ETH_MACL3L4CR_L4SPM ETH_MACL3L4CR_L4SPM_Msk /* Layer 4 Source Port Match Enable */
7695#define ETH_MACL3L4CR_L4PEN_Pos (16U)
7696#define ETH_MACL3L4CR_L4PEN_Msk (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */
7697#define ETH_MACL3L4CR_L4PEN ETH_MACL3L4CR_L4PEN_Msk /* Layer 4 Protocol Enable */
7698#define ETH_MACL3L4CR_L3HDBM_Pos (11U)
7699#define ETH_MACL3L4CR_L3HDBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */
7700#define ETH_MACL3L4CR_L3HDBM ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */
7701#define ETH_MACL3L4CR_L3HSBM_Pos (6U)
7702#define ETH_MACL3L4CR_L3HSBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */
7703#define ETH_MACL3L4CR_L3HSBM ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */
7704#define ETH_MACL3L4CR_L3DAIM_Pos (5U)
7705#define ETH_MACL3L4CR_L3DAIM_Msk (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */
7706#define ETH_MACL3L4CR_L3DAIM ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */
7707#define ETH_MACL3L4CR_L3DAM_Pos (4U)
7708#define ETH_MACL3L4CR_L3DAM_Msk (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */
7709#define ETH_MACL3L4CR_L3DAM ETH_MACL3L4CR_L3DAM_Msk /* Layer 3 IP DA Match Enable */
7710#define ETH_MACL3L4CR_L3SAIM_Pos (3U)
7711#define ETH_MACL3L4CR_L3SAIM_Msk (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */
7712#define ETH_MACL3L4CR_L3SAIM ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */
7713#define ETH_MACL3L4CR_L3SAM_Pos (2U)
7714#define ETH_MACL3L4CR_L3SAM_Msk (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */
7715#define ETH_MACL3L4CR_L3SAM ETH_MACL3L4CR_L3SAM_Msk /* Layer 3 IP SA Match Enable*/
7716#define ETH_MACL3L4CR_L3PEN_Pos (0U)
7717#define ETH_MACL3L4CR_L3PEN_Msk (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */
7718#define ETH_MACL3L4CR_L3PEN ETH_MACL3L4CR_L3PEN_Msk /* Layer 3 Protocol Enable */
7719
7720/* Bit definition for Ethernet MAC L4 Address Register */
7721#define ETH_MACL4AR_L4DP_Pos (16U)
7722#define ETH_MACL4AR_L4DP_Msk (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */
7723#define ETH_MACL4AR_L4DP ETH_MACL4AR_L4DP_Msk /* Layer 4 Destination Port Number Field */
7724#define ETH_MACL4AR_L4SP_Pos (0U)
7725#define ETH_MACL4AR_L4SP_Msk (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */
7726#define ETH_MACL4AR_L4SP ETH_MACL4AR_L4SP_Msk /* Layer 4 Source Port Number Field */
7727
7728/* Bit definition for Ethernet MAC L3 Address0 Register */
7729#define ETH_MACL3A0R_L3A0_Pos (0U)
7730#define ETH_MACL3A0R_L3A0_Msk (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */
7731#define ETH_MACL3A0R_L3A0 ETH_MACL3A0R_L3A0_Msk /* Layer 3 Address 0 Field */
7732
7733/* Bit definition for Ethernet MAC L4 Address1 Register */
7734#define ETH_MACL3A1R_L3A1_Pos (0U)
7735#define ETH_MACL3A1R_L3A1_Msk (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */
7736#define ETH_MACL3A1R_L3A1 ETH_MACL3A1R_L3A1_Msk /* Layer 3 Address 1 Field */
7737
7738/* Bit definition for Ethernet MAC L4 Address2 Register */
7739#define ETH_MACL3A2R_L3A2_Pos (0U)
7740#define ETH_MACL3A2R_L3A2_Msk (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */
7741#define ETH_MACL3A2R_L3A2 ETH_MACL3A2R_L3A2_Msk /* Layer 3 Address 2 Field */
7742
7743/* Bit definition for Ethernet MAC L4 Address3 Register */
7744#define ETH_MACL3A3R_L3A3_Pos (0U)
7745#define ETH_MACL3A3R_L3A3_Msk (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */
7746#define ETH_MACL3A3R_L3A3 ETH_MACL3A3R_L3A3_Msk /* Layer 3 Address 3 Field */
7747
7748/* Bit definition for Ethernet MAC Timestamp Control Register */
7749#define ETH_MACTSCR_TXTSSTSM_Pos (24U)
7750#define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */
7751#define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /* Transmit Timestamp Status Mode */
7752#define ETH_MACTSCR_CSC_Pos (19U)
7753#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */
7754#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */
7755#define ETH_MACTSCR_TSENMACADDR_Pos (18U)
7756#define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */
7757#define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /* Enable MAC Address for PTP Packet Filtering */
7758#define ETH_MACTSCR_SNAPTYPSEL_Pos (16U)
7759#define ETH_MACTSCR_SNAPTYPSEL_Msk (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */
7760#define ETH_MACTSCR_SNAPTYPSEL ETH_MACTSCR_SNAPTYPSEL_Msk /* Select PTP packets for Taking Snapshots */
7761#define ETH_MACTSCR_TSMSTRENA_Pos (15U)
7762#define ETH_MACTSCR_TSMSTRENA_Msk (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */
7763#define ETH_MACTSCR_TSMSTRENA ETH_MACTSCR_TSMSTRENA_Msk /* Enable Snapshot for Messages Relevant to Master */
7764#define ETH_MACTSCR_TSEVNTENA_Pos (14U)
7765#define ETH_MACTSCR_TSEVNTENA_Msk (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */
7766#define ETH_MACTSCR_TSEVNTENA ETH_MACTSCR_TSEVNTENA_Msk /* Enable Timestamp Snapshot for Event Messages */
7767#define ETH_MACTSCR_TSIPV4ENA_Pos (13U)
7768#define ETH_MACTSCR_TSIPV4ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */
7769#define ETH_MACTSCR_TSIPV4ENA ETH_MACTSCR_TSIPV4ENA_Msk /* Enable Processing of PTP Packets Sent over IPv4-UDP */
7770#define ETH_MACTSCR_TSIPV6ENA_Pos (12U)
7771#define ETH_MACTSCR_TSIPV6ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */
7772#define ETH_MACTSCR_TSIPV6ENA ETH_MACTSCR_TSIPV6ENA_Msk /* Enable Processing of PTP Packets Sent over IPv6-UDP */
7773#define ETH_MACTSCR_TSIPENA_Pos (11U)
7774#define ETH_MACTSCR_TSIPENA_Msk (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */
7775#define ETH_MACTSCR_TSIPENA ETH_MACTSCR_TSIPENA_Msk /* Enable Processing of PTP over Ethernet Packets */
7776#define ETH_MACTSCR_TSVER2ENA_Pos (10U)
7777#define ETH_MACTSCR_TSVER2ENA_Msk (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */
7778#define ETH_MACTSCR_TSVER2ENA ETH_MACTSCR_TSVER2ENA_Msk /* Enable PTP Packet Processing for Version 2 Format */
7779#define ETH_MACTSCR_TSCTRLSSR_Pos (9U)
7780#define ETH_MACTSCR_TSCTRLSSR_Msk (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */
7781#define ETH_MACTSCR_TSCTRLSSR ETH_MACTSCR_TSCTRLSSR_Msk /* Timestamp Digital or Binary Rollover Control */
7782#define ETH_MACTSCR_TSENALL_Pos (8U)
7783#define ETH_MACTSCR_TSENALL_Msk (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */
7784#define ETH_MACTSCR_TSENALL ETH_MACTSCR_TSENALL_Msk /* Enable Timestamp for All Packets */
7785#define ETH_MACTSCR_TSADDREG_Pos (5U)
7786#define ETH_MACTSCR_TSADDREG_Msk (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */
7787#define ETH_MACTSCR_TSADDREG ETH_MACTSCR_TSADDREG_Msk /* Update Addend Register */
7788#define ETH_MACTSCR_TSUPDT_Pos (3U)
7789#define ETH_MACTSCR_TSUPDT_Msk (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */
7790#define ETH_MACTSCR_TSUPDT ETH_MACTSCR_TSUPDT_Msk /* Update Timestamp */
7791#define ETH_MACTSCR_TSINIT_Pos (2U)
7792#define ETH_MACTSCR_TSINIT_Msk (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */
7793#define ETH_MACTSCR_TSINIT ETH_MACTSCR_TSINIT_Msk /* Initialize Timestamp */
7794#define ETH_MACTSCR_TSCFUPDT_Pos (1U)
7795#define ETH_MACTSCR_TSCFUPDT_Msk (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */
7796#define ETH_MACTSCR_TSCFUPDT ETH_MACTSCR_TSCFUPDT_Msk /* Fine or Coarse Timestamp Update*/
7797#define ETH_MACTSCR_TSENA_Pos (0U)
7798#define ETH_MACTSCR_TSENA_Msk (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */
7799#define ETH_MACTSCR_TSENA ETH_MACTSCR_TSENA_Msk /* Enable Timestamp */
7800
7801/* Bit definition for Ethernet MAC Sub-second Increment Register */
7802#define ETH_MACMACSSIR_SSINC_Pos (16U)
7803#define ETH_MACMACSSIR_SSINC_Msk (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */
7804#define ETH_MACMACSSIR_SSINC ETH_MACMACSSIR_SSINC_Msk /* Sub-second Increment Value */
7805#define ETH_MACMACSSIR_SNSINC_Pos (8U)
7806#define ETH_MACMACSSIR_SNSINC_Msk (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) /*!< 0x000000FF */
7807#define ETH_MACMACSSIR_SNSINC ETH_MACMACSSIR_SNSINC_Msk /* Sub-nanosecond Increment Value */
7808
7809/* Bit definition for Ethernet MAC System Time Seconds Register */
7810#define ETH_MACSTSR_TSS_Pos (0U)
7811#define ETH_MACSTSR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */
7812#define ETH_MACSTSR_TSS ETH_MACSTSR_TSS_Msk /* Timestamp Second */
7813
7814/* Bit definition for Ethernet MAC System Time Nanoseconds Register */
7815#define ETH_MACSTNR_TSSS_Pos (0U)
7816#define ETH_MACSTNR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */
7817#define ETH_MACSTNR_TSSS ETH_MACSTNR_TSSS_Msk /* Timestamp Sub-seconds */
7818
7819/* Bit definition for Ethernet MAC System Time Seconds Update Register */
7820#define ETH_MACSTSUR_TSS_Pos (0U)
7821#define ETH_MACSTSUR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */
7822#define ETH_MACSTSUR_TSS ETH_MACSTSUR_TSS_Msk /* Timestamp Seconds */
7823
7824/* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */
7825#define ETH_MACSTNUR_ADDSUB_Pos (31U)
7826#define ETH_MACSTNUR_ADDSUB_Msk (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */
7827#define ETH_MACSTNUR_ADDSUB ETH_MACSTNUR_ADDSUB_Msk /* Add or Subtract Time */
7828#define ETH_MACSTNUR_TSSS_Pos (0U)
7829#define ETH_MACSTNUR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */
7830#define ETH_MACSTNUR_TSSS ETH_MACSTNUR_TSSS_Msk /* Timestamp Sub-seconds */
7831
7832/* Bit definition for Ethernet MAC Timestamp Addend Register */
7833#define ETH_MACTSAR_TSAR_Pos (0U)
7834#define ETH_MACTSAR_TSAR_Msk (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */
7835#define ETH_MACTSAR_TSAR ETH_MACTSAR_TSAR_Msk /* Timestamp Addend Register */
7836
7837/* Bit definition for Ethernet MAC Timestamp Status Register */
7838#define ETH_MACTSSR_ATSNS_Pos (25U)
7839#define ETH_MACTSSR_ATSNS_Msk (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */
7840#define ETH_MACTSSR_ATSNS ETH_MACTSSR_ATSNS_Msk /* Number of Auxiliary Timestamp Snapshots */
7841#define ETH_MACTSSR_ATSSTM_Pos (24U)
7842#define ETH_MACTSSR_ATSSTM_Msk (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */
7843#define ETH_MACTSSR_ATSSTM ETH_MACTSSR_ATSSTM_Msk /* Auxiliary Timestamp Snapshot Trigger Missed */
7844#define ETH_MACTSSR_ATSSTN_Pos (16U)
7845#define ETH_MACTSSR_ATSSTN_Msk (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */
7846#define ETH_MACTSSR_ATSSTN ETH_MACTSSR_ATSSTN_Msk /* Auxiliary Timestamp Snapshot Trigger Identifier */
7847#define ETH_MACTSSR_TXTSSIS_Pos (15U)
7848#define ETH_MACTSSR_TXTSSIS_Msk (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */
7849#define ETH_MACTSSR_TXTSSIS ETH_MACTSSR_TXTSSIS_Msk /* Tx Timestamp Status Interrupt Status */
7850#define ETH_MACTSSR_TSTRGTERR0_Pos (3U)
7851#define ETH_MACTSSR_TSTRGTERR0_Msk (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */
7852#define ETH_MACTSSR_TSTRGTERR0 ETH_MACTSSR_TSTRGTERR0_Msk /* Timestamp Target Time Error */
7853#define ETH_MACTSSR_AUXTSTRIG_Pos (2U)
7854#define ETH_MACTSSR_AUXTSTRIG_Msk (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */
7855#define ETH_MACTSSR_AUXTSTRIG ETH_MACTSSR_AUXTSTRIG_Msk /* Auxiliary Timestamp Trigger Snapshot*/
7856#define ETH_MACTSSR_TSTARGT0_Pos (1U)
7857#define ETH_MACTSSR_TSTARGT0_Msk (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */
7858#define ETH_MACTSSR_TSTARGT0 ETH_MACTSSR_TSTARGT0_Msk /* Timestamp Target Time Reached */
7859#define ETH_MACTSSR_TSSOVF_Pos (0U)
7860#define ETH_MACTSSR_TSSOVF_Msk (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */
7861#define ETH_MACTSSR_TSSOVF ETH_MACTSSR_TSSOVF_Msk /* Timestamp Seconds Overflow */
7862
7863/* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */
7864#define ETH_MACTTSSNR_TXTSSMIS_Pos (31U)
7865#define ETH_MACTTSSNR_TXTSSMIS_Msk (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */
7866#define ETH_MACTTSSNR_TXTSSMIS ETH_MACTTSSNR_TXTSSMIS_Msk /* Transmit Timestamp Status Missed */
7867#define ETH_MACTTSSNR_TXTSSLO_Pos (0U)
7868#define ETH_MACTTSSNR_TXTSSLO_Msk (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */
7869#define ETH_MACTTSSNR_TXTSSLO ETH_MACTTSSNR_TXTSSLO_Msk /* Transmit Timestamp Status Low */
7870
7871/* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */
7872#define ETH_MACTTSSSR_TXTSSHI_Pos (0U)
7873#define ETH_MACTTSSSR_TXTSSHI_Msk (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */
7874#define ETH_MACTTSSSR_TXTSSHI ETH_MACTTSSSR_TXTSSHI_Msk /* Transmit Timestamp Status High */
7875
7876/* Bit definition for Ethernet MAC Auxiliary Control Register*/
7877#define ETH_MACACR_ATSEN3_Pos (7U)
7878#define ETH_MACACR_ATSEN3_Msk (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */
7879#define ETH_MACACR_ATSEN3 ETH_MACACR_ATSEN3_Msk /* Auxiliary Snapshot 3 Enable */
7880#define ETH_MACACR_ATSEN2_Pos (6U)
7881#define ETH_MACACR_ATSEN2_Msk (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */
7882#define ETH_MACACR_ATSEN2 ETH_MACACR_ATSEN2_Msk /* Auxiliary Snapshot 2 Enable */
7883#define ETH_MACACR_ATSEN1_Pos (5U)
7884#define ETH_MACACR_ATSEN1_Msk (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */
7885#define ETH_MACACR_ATSEN1 ETH_MACACR_ATSEN1_Msk /* Auxiliary Snapshot 1 Enable */
7886#define ETH_MACACR_ATSEN0_Pos (4U)
7887#define ETH_MACACR_ATSEN0_Msk (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */
7888#define ETH_MACACR_ATSEN0 ETH_MACACR_ATSEN0_Msk /* Auxiliary Snapshot 0 Enable */
7889#define ETH_MACACR_ATSFC_Pos (0U)
7890#define ETH_MACACR_ATSFC_Msk (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */
7891#define ETH_MACACR_ATSFC ETH_MACACR_ATSFC_Msk /* Auxiliary Snapshot FIFO Clear */
7892
7893/* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */
7894#define ETH_MACATSNR_AUXTSLO_Pos (0U)
7895#define ETH_MACATSNR_AUXTSLO_Msk (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */
7896#define ETH_MACATSNR_AUXTSLO ETH_MACATSNR_AUXTSLO_Msk /* Auxiliary Timestamp */
7897
7898/* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */
7899#define ETH_MACATSSR_AUXTSHI_Pos (0U)
7900#define ETH_MACATSSR_AUXTSHI_Msk (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */
7901#define ETH_MACATSSR_AUXTSHI ETH_MACATSSR_AUXTSHI_Msk /* Auxiliary Timestamp */
7902
7903/* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */
7904#define ETH_MACTSIACR_OSTIAC_Pos (0U)
7905#define ETH_MACTSIACR_OSTIAC_Msk (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */
7906#define ETH_MACTSIACR_OSTIAC ETH_MACTSIACR_OSTIAC_Msk /* One-Step Timestamp Ingress Asymmetry Correction */
7907
7908/* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */
7909#define ETH_MACTSEACR_OSTEAC_Pos (0U)
7910#define ETH_MACTSEACR_OSTEAC_Msk (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */
7911#define ETH_MACTSEACR_OSTEAC ETH_MACTSEACR_OSTEAC_Msk /* One-Step Timestamp Egress Asymmetry Correction */
7912
7913/* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */
7914#define ETH_MACTSICNR_TSIC_Pos (0U)
7915#define ETH_MACTSICNR_TSIC_Msk (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */
7916#define ETH_MACTSICNR_TSIC ETH_MACTSICNR_TSIC_Msk /* Timestamp Ingress Correction */
7917
7918/* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */
7919#define ETH_MACTSECNR_TSEC_Pos (0U)
7920#define ETH_MACTSECNR_TSEC_Msk (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */
7921#define ETH_MACTSECNR_TSEC ETH_MACTSECNR_TSEC_Msk /* Timestamp Egress Correction */
7922
7923/* Bit definition for Ethernet MAC PPS Control Register */
7924#define ETH_MACPPSCR_TRGTMODSEL0_Pos (5U)
7925#define ETH_MACPPSCR_TRGTMODSEL0_Msk (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */
7926#define ETH_MACPPSCR_TRGTMODSEL0 ETH_MACPPSCR_TRGTMODSEL0_Msk /* Target Time Register Mode for PPS Output */
7927#define ETH_MACPPSCR_PPSEN0_Pos (4U)
7928#define ETH_MACPPSCR_PPSEN0_Msk (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */
7929#define ETH_MACPPSCR_PPSEN0 ETH_MACPPSCR_PPSEN0_Msk /* Flexible PPS Output Mode Enable */
7930#define ETH_MACPPSCR_PPSCTRL_Pos (0U)
7931#define ETH_MACPPSCR_PPSCTRL_Msk (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */
7932#define ETH_MACPPSCR_PPSCTRL ETH_MACPPSCR_PPSCTRL_Msk /* PPS Output Frequency Control */
7933
7934/* Bit definition for Ethernet MAC PPS Target Time Seconds Register */
7935#define ETH_MACPPSTTSR_TSTRH0_Pos (0U)
7936#define ETH_MACPPSTTSR_TSTRH0_Msk (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */
7937#define ETH_MACPPSTTSR_TSTRH0 ETH_MACPPSTTSR_TSTRH0_Msk /* PPS Target Time Seconds Register */
7938
7939/* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */
7940#define ETH_MACPPSTTNR_TRGTBUSY0_Pos (31U)
7941#define ETH_MACPPSTTNR_TRGTBUSY0_Msk (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */
7942#define ETH_MACPPSTTNR_TRGTBUSY0 ETH_MACPPSTTNR_TRGTBUSY0_Msk /* PPS Target Time Register Busy */
7943#define ETH_MACPPSTTNR_TTSL0_Pos (0U)
7944#define ETH_MACPPSTTNR_TTSL0_Msk (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */
7945#define ETH_MACPPSTTNR_TTSL0 ETH_MACPPSTTNR_TTSL0_Msk /* Target Time Low for PPS Register */
7946
7947/* Bit definition for Ethernet MAC PPS Interval Register */
7948#define ETH_MACPPSIR_PPSINT0_Pos (0U)
7949#define ETH_MACPPSIR_PPSINT0_Msk (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */
7950#define ETH_MACPPSIR_PPSINT0 ETH_MACPPSIR_PPSINT0_Msk /* PPS Output Signal Interval */
7951
7952/* Bit definition for Ethernet MAC PPS Width Register */
7953#define ETH_MACPPSWR_PPSWIDTH0_Pos (0U)
7954#define ETH_MACPPSWR_PPSWIDTH0_Msk (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */
7955#define ETH_MACPPSWR_PPSWIDTH0 ETH_MACPPSWR_PPSWIDTH0_Msk /* PPS Output Signal Width */
7956
7957/* Bit definition for Ethernet MAC PTP Offload Control Register */
7958#define ETH_MACPOCR_DN_Pos (8U)
7959#define ETH_MACPOCR_DN_Msk (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */
7960#define ETH_MACPOCR_DN ETH_MACPOCR_DN_Msk /* Domain Number */
7961#define ETH_MACPOCR_DRRDIS_Pos (6U)
7962#define ETH_MACPOCR_DRRDIS_Msk (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */
7963#define ETH_MACPOCR_DRRDIS ETH_MACPOCR_DRRDIS_Msk /* Disable PTO Delay Request/Response response generation */
7964#define ETH_MACPOCR_APDREQTRIG_Pos (5U)
7965#define ETH_MACPOCR_APDREQTRIG_Msk (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */
7966#define ETH_MACPOCR_APDREQTRIG ETH_MACPOCR_APDREQTRIG_Msk /* Automatic PTP Pdelay_Req message Trigger */
7967#define ETH_MACPOCR_ASYNCTRIG_Pos (4U)
7968#define ETH_MACPOCR_ASYNCTRIG_Msk (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */
7969#define ETH_MACPOCR_ASYNCTRIG ETH_MACPOCR_ASYNCTRIG_Msk /* Automatic PTP SYNC message Trigger */
7970#define ETH_MACPOCR_APDREQEN_Pos (2U)
7971#define ETH_MACPOCR_APDREQEN_Msk (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */
7972#define ETH_MACPOCR_APDREQEN ETH_MACPOCR_APDREQEN_Msk /* Automatic PTP Pdelay_Req message Enable */
7973#define ETH_MACPOCR_ASYNCEN_Pos (1U)
7974#define ETH_MACPOCR_ASYNCEN_Msk (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */
7975#define ETH_MACPOCR_ASYNCEN ETH_MACPOCR_ASYNCEN_Msk /* Automatic PTP SYNC message Enable */
7976#define ETH_MACPOCR_PTOEN_Pos (0U)
7977#define ETH_MACPOCR_PTOEN_Msk (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */
7978#define ETH_MACPOCR_PTOEN ETH_MACPOCR_PTOEN_Msk /* PTP Offload Enable */
7979
7980/* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */
7981#define ETH_MACSPI0R_SPI0_Pos (0U)
7982#define ETH_MACSPI0R_SPI0_Msk (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */
7983#define ETH_MACSPI0R_SPI0 ETH_MACSPI0R_SPI0_Msk /* Source Port Identity 0 */
7984
7985/* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */
7986#define ETH_MACSPI1R_SPI1_Pos (0U)
7987#define ETH_MACSPI1R_SPI1_Msk (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */
7988#define ETH_MACSPI1R_SPI1 ETH_MACSPI1R_SPI1_Msk /* Source Port Identity 1 */
7989
7990/* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */
7991#define ETH_MACSPI2R_SPI2_Pos (0U)
7992#define ETH_MACSPI2R_SPI2_Msk (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */
7993#define ETH_MACSPI2R_SPI2 ETH_MACSPI2R_SPI2_Msk /* Source Port Identity 2 */
7994
7995/* Bit definition for Ethernet MAC Log Message Interval Register */
7996#define ETH_MACLMIR_LMPDRI_Pos (24U)
7997#define ETH_MACLMIR_LMPDRI_Msk (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */
7998#define ETH_MACLMIR_LMPDRI ETH_MACLMIR_LMPDRI_Msk /* Log Min Pdelay_Req Interval */
7999#define ETH_MACLMIR_DRSYNCR_Pos (8U)
8000#define ETH_MACLMIR_DRSYNCR_Msk (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */
8001#define ETH_MACLMIR_DRSYNCR ETH_MACLMIR_DRSYNCR_Msk /* Delay_Req to SYNC Ratio */
8002#define ETH_MACLMIR_LSI_Pos (0U)
8003#define ETH_MACLMIR_LSI_Msk (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */
8004#define ETH_MACLMIR_LSI ETH_MACLMIR_LSI_Msk /* Log Sync Interval */
8005
8006/* Bit definition for Ethernet MTL Operation Mode Register */
8007#define ETH_MTLOMR_CNTCLR_Pos (9U)
8008#define ETH_MTLOMR_CNTCLR_Msk (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */
8009#define ETH_MTLOMR_CNTCLR ETH_MTLOMR_CNTCLR_Msk /* Counters Reset */
8010#define ETH_MTLOMR_CNTPRST_Pos (8U)
8011#define ETH_MTLOMR_CNTPRST_Msk (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */
8012#define ETH_MTLOMR_CNTPRST ETH_MTLOMR_CNTPRST_Msk /* Counters Preset */
8013#define ETH_MTLOMR_DTXSTS_Pos (1U)
8014#define ETH_MTLOMR_DTXSTS_Msk (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */
8015#define ETH_MTLOMR_DTXSTS ETH_MTLOMR_DTXSTS_Msk /* Drop Transmit Status */
8016
8017/* Bit definition for Ethernet MTL Interrupt Status Register */
8018#define ETH_MTLISR_MACIS_Pos (16U)
8019#define ETH_MTLISR_MACIS_Msk (0x1UL << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */
8020#define ETH_MTLISR_MACIS ETH_MTLISR_MACIS_Msk /* MAC Interrupt Status */
8021#define ETH_MTLISR_QIS_Pos (0U)
8022#define ETH_MTLISR_QIS_Msk (0x1UL << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */
8023#define ETH_MTLISR_QIS ETH_MTLISR_QIS_Msk /* Queue Interrupt status */
8024
8025/* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */
8026#define ETH_MTLTQOMR_TTC_Pos (4U)
8027#define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
8028#define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
8029#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */
8030#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */
8031#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */
8032#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */
8033#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */
8034#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */
8035#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */
8036#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */
8037#define ETH_MTLTQOMR_TSF_Pos (1U)
8038#define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
8039#define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
8040#define ETH_MTLTQOMR_FTQ_Pos (0U)
8041#define ETH_MTLTQOMR_FTQ_Msk (0x1UL << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */
8042#define ETH_MTLTQOMR_FTQ ETH_MTLTQOMR_FTQ_Msk /* Flush Transmit Queue */
8043
8044/* Bit definition for Ethernet MTL Tx Queue Underflow Register */
8045#define ETH_MTLTQUR_UFCNTOVF_Pos (11U)
8046#define ETH_MTLTQUR_UFCNTOVF_Msk (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */
8047#define ETH_MTLTQUR_UFCNTOVF ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
8048#define ETH_MTLTQUR_UFPKTCNT_Pos (0U)
8049#define ETH_MTLTQUR_UFPKTCNT_Msk (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */
8050#define ETH_MTLTQUR_UFPKTCNT ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */
8051
8052/* Bit definition for Ethernet MTL Tx Queue Debug Register */
8053#define ETH_MTLTQDR_STXSTSF_Pos (20U)
8054#define ETH_MTLTQDR_STXSTSF_Msk (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */
8055#define ETH_MTLTQDR_STXSTSF ETH_MTLTQDR_STXSTSF_Msk /* Number of Status Words in the Tx Status FIFO of Queue */
8056#define ETH_MTLTQDR_PTXQ_Pos (16U)
8057#define ETH_MTLTQDR_PTXQ_Msk (0x7UL << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */
8058#define ETH_MTLTQDR_PTXQ ETH_MTLTQDR_PTXQ_Msk /* Number of Packets in the Transmit Queue */
8059#define ETH_MTLTQDR_TXSTSFSTS_Pos (5U)
8060#define ETH_MTLTQDR_TXSTSFSTS_Msk (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */
8061#define ETH_MTLTQDR_TXSTSFSTS ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
8062#define ETH_MTLTQDR_TXQSTS_Pos (4U)
8063#define ETH_MTLTQDR_TXQSTS_Msk (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */
8064#define ETH_MTLTQDR_TXQSTS ETH_MTLTQDR_TXQSTS_Msk /* MTL Tx Queue Not Empty Status */
8065#define ETH_MTLTQDR_TWCSTS_Pos (3U)
8066#define ETH_MTLTQDR_TWCSTS_Msk (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */
8067#define ETH_MTLTQDR_TWCSTS ETH_MTLTQDR_TWCSTS_Msk /* MTL Tx Queue Write Controller Status */
8068#define ETH_MTLTQDR_TRCSTS_Pos (1U)
8069#define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
8070#define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
8071#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
8072#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */
8073#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */
8074#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
8075#define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
8076#define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
8077#define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
8078
8079/* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */
8080#define ETH_MTLQICSR_RXOIE_Pos (24U)
8081#define ETH_MTLQICSR_RXOIE_Msk (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */
8082#define ETH_MTLQICSR_RXOIE ETH_MTLQICSR_RXOIE_Msk /* Receive Queue Overflow Interrupt Enable */
8083#define ETH_MTLQICSR_RXOVFIS_Pos (16U)
8084#define ETH_MTLQICSR_RXOVFIS_Msk (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */
8085#define ETH_MTLQICSR_RXOVFIS ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
8086#define ETH_MTLQICSR_TXUIE_Pos (8U)
8087#define ETH_MTLQICSR_TXUIE_Msk (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */
8088#define ETH_MTLQICSR_TXUIE ETH_MTLQICSR_TXUIE_Msk /* Transmit Queue Underflow Interrupt Enable */
8089#define ETH_MTLQICSR_TXUNFIS_Pos (0U)
8090#define ETH_MTLQICSR_TXUNFIS_Msk (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */
8091#define ETH_MTLQICSR_TXUNFIS ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */
8092
8093/* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */
8094#define ETH_MTLRQOMR_RQS_Pos (20U)
8095#define ETH_MTLRQOMR_RQS_Msk (0x7UL << ETH_MTLRQOMR_RQS_Pos) /*!< 0x00700000 */
8096#define ETH_MTLRQOMR_RQS ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */
8097#define ETH_MTLRQOMR_RFD_Pos (14U)
8098#define ETH_MTLRQOMR_RFD_Msk (0x7UL << ETH_MTLRQOMR_RFD_Pos) /*!< 0x0001C000 */
8099#define ETH_MTLRQOMR_RFD ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
8100#define ETH_MTLRQOMR_RFA_Pos (8U)
8101#define ETH_MTLRQOMR_RFA_Msk (0x7UL << ETH_MTLRQOMR_RFA_Pos) /*!< 0x00000700 */
8102#define ETH_MTLRQOMR_RFA ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
8103#define ETH_MTLRQOMR_EHFC_Pos (7U)
8104#define ETH_MTLRQOMR_EHFC_Msk (0x1UL << ETH_MTLRQOMR_EHFC_Pos) /*!< 0x00000080 */
8105#define ETH_MTLRQOMR_EHFC ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */
8106#define ETH_MTLRQOMR_DISTCPEF_Pos (6U)
8107#define ETH_MTLRQOMR_DISTCPEF_Msk (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */
8108#define ETH_MTLRQOMR_DISTCPEF ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
8109#define ETH_MTLRQOMR_RSF_Pos (5U)
8110#define ETH_MTLRQOMR_RSF_Msk (0x1UL << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */
8111#define ETH_MTLRQOMR_RSF ETH_MTLRQOMR_RSF_Msk /* Receive Queue Store and Forward */
8112#define ETH_MTLRQOMR_FEP_Pos (4U)
8113#define ETH_MTLRQOMR_FEP_Msk (0x1UL << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */
8114#define ETH_MTLRQOMR_FEP ETH_MTLRQOMR_FEP_Msk /* Forward Error Packets */
8115#define ETH_MTLRQOMR_FUP_Pos (3U)
8116#define ETH_MTLRQOMR_FUP_Msk (0x1UL << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */
8117#define ETH_MTLRQOMR_FUP ETH_MTLRQOMR_FUP_Msk /* Forward Undersized Good Packets */
8118#define ETH_MTLRQOMR_RTC_Pos (0U)
8119#define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
8120#define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
8121#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */
8122#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */
8123#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */
8124#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */
8125
8126/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
8127#define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
8128#define ETH_MTLRQMPOCR_MISCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */
8129#define ETH_MTLRQMPOCR_MISCNTOVF ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
8130#define ETH_MTLRQMPOCR_MISPKTCNT_Pos (16U)
8131#define ETH_MTLRQMPOCR_MISPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */
8132#define ETH_MTLRQMPOCR_MISPKTCNT ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
8133#define ETH_MTLRQMPOCR_OVFCNTOVF_Pos (11U)
8134#define ETH_MTLRQMPOCR_OVFCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */
8135#define ETH_MTLRQMPOCR_OVFCNTOVF ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
8136#define ETH_MTLRQMPOCR_OVFPKTCNT_Pos (0U)
8137#define ETH_MTLRQMPOCR_OVFPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */
8138#define ETH_MTLRQMPOCR_OVFPKTCNT ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */
8139
8140/* Bit definition for Ethernet MTL Rx Queue Debug Register */
8141#define ETH_MTLRQDR_PRXQ_Pos (16U)
8142#define ETH_MTLRQDR_PRXQ_Msk (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */
8143#define ETH_MTLRQDR_PRXQ ETH_MTLRQDR_PRXQ_Msk /* Number of Packets in Receive Queue */
8144#define ETH_MTLRQDR_RXQSTS_Pos (4U)
8145#define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
8146#define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
8147#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */
8148#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
8149#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
8150#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
8151#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos (5U)
8152#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */
8153#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
8154#define ETH_MTLRQDR_RXQSTS_FULL_Pos (4U)
8155#define ETH_MTLRQDR_RXQSTS_FULL_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */
8156#define ETH_MTLRQDR_RXQSTS_FULL ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */
8157#define ETH_MTLRQDR_RRCSTS_Pos (1U)
8158#define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
8159#define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
8160#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
8161#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
8162#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
8163#define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
8164#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos (2U)
8165#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */
8166#define ETH_MTLRQDR_RRCSTS_READINGSTATUS ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
8167#define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos (1U)
8168#define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */
8169#define ETH_MTLRQDR_RRCSTS_FLUSHING ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
8170#define ETH_MTLRQDR_RWCSTS_Pos (0U)
8171#define ETH_MTLRQDR_RWCSTS_Msk (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */
8172#define ETH_MTLRQDR_RWCSTS ETH_MTLRQDR_RWCSTS_Msk /* MTL Rx Queue Write Controller Active Status */
8173
8174/* Bit definition for Ethernet MTL Rx Queue Control Register */
8175#define ETH_MTLRQCR_RQPA_Pos (3U)
8176#define ETH_MTLRQCR_RQPA_Msk (0x1UL << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */
8177#define ETH_MTLRQCR_RQPA ETH_MTLRQCR_RQPA_Msk /* Receive Queue Packet Arbitration */
8178#define ETH_MTLRQCR_RQW_Pos (0U)
8179#define ETH_MTLRQCR_RQW_Msk (0x7UL << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */
8180#define ETH_MTLRQCR_RQW ETH_MTLRQCR_RQW_Msk /* Receive Queue Weight */
8181
8182/* Bit definition for Ethernet DMA Mode Register */
8183#define ETH_DMAMR_INTM_Pos (16U)
8184#define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */
8185#define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /* This field defines the interrupt mode */
8186#define ETH_DMAMR_INTM_0 (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */
8187#define ETH_DMAMR_INTM_1 (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */
8188#define ETH_DMAMR_INTM_2 (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */
8189#define ETH_DMAMR_PR_Pos (12U)
8190#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
8191#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
8192#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */
8193#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */
8194#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */
8195#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */
8196#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */
8197#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */
8198#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */
8199#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */
8200#define ETH_DMAMR_TXPR_Pos (11U)
8201#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
8202#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
8203#define ETH_DMAMR_DA_Pos (1U)
8204#define ETH_DMAMR_DA_Msk (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */
8205#define ETH_DMAMR_DA ETH_DMAMR_DA_Msk /* DMA Tx or Rx Arbitration Scheme */
8206#define ETH_DMAMR_SWR_Pos (0U)
8207#define ETH_DMAMR_SWR_Msk (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */
8208#define ETH_DMAMR_SWR ETH_DMAMR_SWR_Msk /* Software Reset */
8209
8210/* Bit definition for Ethernet DMA SysBus Mode Register */
8211#define ETH_DMASBMR_RB_Pos (15U)
8212#define ETH_DMASBMR_RB_Msk (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */
8213#define ETH_DMASBMR_RB ETH_DMASBMR_RB_Msk /* Rebuild INCRx Burst */
8214#define ETH_DMASBMR_MB_Pos (14U)
8215#define ETH_DMASBMR_MB_Msk (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */
8216#define ETH_DMASBMR_MB ETH_DMASBMR_MB_Msk /* Mixed Burst */
8217#define ETH_DMASBMR_AAL_Pos (12U)
8218#define ETH_DMASBMR_AAL_Msk (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */
8219#define ETH_DMASBMR_AAL ETH_DMASBMR_AAL_Msk /* Address-Aligned Beats */
8220#define ETH_DMASBMR_FB_Pos (0U)
8221#define ETH_DMASBMR_FB_Msk (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */
8222#define ETH_DMASBMR_FB ETH_DMASBMR_FB_Msk /* Fixed Burst Length */
8223
8224/* Bit definition for Ethernet DMA Interrupt Status Register */
8225#define ETH_DMAISR_MACIS_Pos (17U)
8226#define ETH_DMAISR_MACIS_Msk (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */
8227#define ETH_DMAISR_MACIS ETH_DMAISR_MACIS_Msk /* MAC Interrupt Status */
8228#define ETH_DMAISR_MTLIS_Pos (16U)
8229#define ETH_DMAISR_MTLIS_Msk (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */
8230#define ETH_DMAISR_MTLIS ETH_DMAISR_MTLIS_Msk /* MAC Interrupt Status */
8231#define ETH_DMAISR_DMACIS_Pos (0U)
8232#define ETH_DMAISR_DMACIS_Msk (0x1UL << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */
8233#define ETH_DMAISR_DMACIS ETH_DMAISR_DMACIS_Msk /* DMA Channel Interrupt Status */
8234
8235/* Bit definition for Ethernet DMA Debug Status Register */
8236#define ETH_DMADSR_TPS_Pos (12U)
8237#define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
8238#define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
8239#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */
8240#define ETH_DMADSR_TPS_FETCHING_Pos (12U)
8241#define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
8242#define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
8243#define ETH_DMADSR_TPS_WAITING_Pos (13U)
8244#define ETH_DMADSR_TPS_WAITING_Msk (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */
8245#define ETH_DMADSR_TPS_WAITING ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */
8246#define ETH_DMADSR_TPS_READING_Pos (12U)
8247#define ETH_DMADSR_TPS_READING_Msk (0x3UL << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */
8248#define ETH_DMADSR_TPS_READING ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
8249#define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos (14U)
8250#define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */
8251#define ETH_DMADSR_TPS_TIMESTAMP_WR ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */
8252#define ETH_DMADSR_TPS_SUSPENDED_Pos (13U)
8253#define ETH_DMADSR_TPS_SUSPENDED_Msk (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */
8254#define ETH_DMADSR_TPS_SUSPENDED ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
8255#define ETH_DMADSR_TPS_CLOSING_Pos (12U)
8256#define ETH_DMADSR_TPS_CLOSING_Msk (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */
8257#define ETH_DMADSR_TPS_CLOSING ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */
8258#define ETH_DMADSR_RPS_Pos (8U)
8259#define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
8260#define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
8261#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */
8262#define ETH_DMADSR_RPS_FETCHING_Pos (12U)
8263#define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
8264#define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
8265#define ETH_DMADSR_RPS_WAITING_Pos (12U)
8266#define ETH_DMADSR_RPS_WAITING_Msk (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */
8267#define ETH_DMADSR_RPS_WAITING ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */
8268#define ETH_DMADSR_RPS_SUSPENDED_Pos (14U)
8269#define ETH_DMADSR_RPS_SUSPENDED_Msk (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */
8270#define ETH_DMADSR_RPS_SUSPENDED ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
8271#define ETH_DMADSR_RPS_CLOSING_Pos (12U)
8272#define ETH_DMADSR_RPS_CLOSING_Msk (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */
8273#define ETH_DMADSR_RPS_CLOSING ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
8274#define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos (13U)
8275#define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */
8276#define ETH_DMADSR_RPS_TIMESTAMP_WR ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */
8277#define ETH_DMADSR_RPS_TRANSFERRING_Pos (12U)
8278#define ETH_DMADSR_RPS_TRANSFERRING_Msk (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */
8279#define ETH_DMADSR_RPS_TRANSFERRING ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
8280
8281/* Bit definition for Ethernet DMA Channel Control Register */
8282#define ETH_DMACCR_DSL_Pos (18U)
8283#define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
8284#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
8285#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000)
8286#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000)
8287#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000)
8288#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000)
8289#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */
8290#define ETH_DMACCR_MSS_Pos (0U)
8291#define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
8292#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
8293
8294/* Bit definition for Ethernet DMA Channel Tx Control Register */
8295#define ETH_DMACTCR_TPBL_Pos (16U)
8296#define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
8297#define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
8298#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */
8299#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */
8300#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */
8301#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */
8302#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */
8303#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */
8304#define ETH_DMACTCR_TSE_Pos (12U)
8305#define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
8306#define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
8307#define ETH_DMACTCR_OSP_Pos (4U)
8308#define ETH_DMACTCR_OSP_Msk (0x1UL << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */
8309#define ETH_DMACTCR_OSP ETH_DMACTCR_OSP_Msk /* Operate on Second Packet */
8310#define ETH_DMACTCR_ST_Pos (0U)
8311#define ETH_DMACTCR_ST_Msk (0x1UL << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */
8312#define ETH_DMACTCR_ST ETH_DMACTCR_ST_Msk /* Start or Stop Transmission Command */
8313
8314/* Bit definition for Ethernet DMA Channel Rx Control Register */
8315#define ETH_DMACRCR_RPF_Pos (31U)
8316#define ETH_DMACRCR_RPF_Msk (0x1UL << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */
8317#define ETH_DMACRCR_RPF ETH_DMACRCR_RPF_Msk /* Rx Packet Flush */
8318#define ETH_DMACRCR_RPBL_Pos (16U)
8319#define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
8320#define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
8321#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */
8322#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */
8323#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */
8324#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */
8325#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */
8326#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */
8327#define ETH_DMACRCR_RBSZ_Pos (1U)
8328#define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
8329#define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
8330#define ETH_DMACRCR_SR_Pos (0U)
8331#define ETH_DMACRCR_SR_Msk (0x1UL << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */
8332#define ETH_DMACRCR_SR ETH_DMACRCR_SR_Msk /* Start or Stop Receive */
8333
8334/* Bit definition for Ethernet DMA CH Tx Desc List Address Register */
8335#define ETH_DMACTDLAR_TDESLA_Pos (2U)
8336#define ETH_DMACTDLAR_TDESLA_Msk (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */
8337#define ETH_DMACTDLAR_TDESLA ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */
8338
8339/* Bit definition for Ethernet DMA CH Rx Desc List Address Register */
8340#define ETH_DMACRDLAR_RDESLA_Pos (2U)
8341#define ETH_DMACRDLAR_RDESLA_Msk (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */
8342#define ETH_DMACRDLAR_RDESLA ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */
8343
8344/* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */
8345#define ETH_DMACTDTPR_TDT_Pos (2U)
8346#define ETH_DMACTDTPR_TDT_Msk (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */
8347#define ETH_DMACTDTPR_TDT ETH_DMACTDTPR_TDT_Msk /* Transmit Descriptor Tail Pointer */
8348
8349/* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */
8350#define ETH_DMACRDTPR_RDT_Pos (2U)
8351#define ETH_DMACRDTPR_RDT_Msk (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */
8352#define ETH_DMACRDTPR_RDT ETH_DMACRDTPR_RDT_Msk /* Receive Descriptor Tail Pointer */
8353
8354/* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */
8355#define ETH_DMACTDRLR_TDRL_Pos (0U)
8356#define ETH_DMACTDRLR_TDRL_Msk (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */
8357#define ETH_DMACTDRLR_TDRL ETH_DMACTDRLR_TDRL_Msk /* Transmit Descriptor Ring Length */
8358
8359/* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */
8360#define ETH_DMACRDRLR_RDRL_Pos (0U)
8361#define ETH_DMACRDRLR_RDRL_Msk (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */
8362#define ETH_DMACRDRLR_RDRL ETH_DMACRDRLR_RDRL_Msk /* Receive Descriptor Ring Length */
8363
8364/* Bit definition for Ethernet DMA Channel Interrupt Enable Register */
8365#define ETH_DMACIER_NIE_Pos (15U)
8366#define ETH_DMACIER_NIE_Msk (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */
8367#define ETH_DMACIER_NIE ETH_DMACIER_NIE_Msk /* Normal Interrupt Summary Enable */
8368#define ETH_DMACIER_AIE_Pos (14U)
8369#define ETH_DMACIER_AIE_Msk (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */
8370#define ETH_DMACIER_AIE ETH_DMACIER_AIE_Msk /* Abnormal Interrupt Summary Enable */
8371#define ETH_DMACIER_CDEE_Pos (13U)
8372#define ETH_DMACIER_CDEE_Msk (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */
8373#define ETH_DMACIER_CDEE ETH_DMACIER_CDEE_Msk /* Context Descriptor Error Enable */
8374#define ETH_DMACIER_FBEE_Pos (12U)
8375#define ETH_DMACIER_FBEE_Msk (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */
8376#define ETH_DMACIER_FBEE ETH_DMACIER_FBEE_Msk /* Fatal Bus Error Enable */
8377#define ETH_DMACIER_ERIE_Pos (11U)
8378#define ETH_DMACIER_ERIE_Msk (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */
8379#define ETH_DMACIER_ERIE ETH_DMACIER_ERIE_Msk /* Early Receive Interrupt Enable */
8380#define ETH_DMACIER_ETIE_Pos (10U)
8381#define ETH_DMACIER_ETIE_Msk (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */
8382#define ETH_DMACIER_ETIE ETH_DMACIER_ETIE_Msk /* Early Transmit Interrupt Enable */
8383#define ETH_DMACIER_RWTE_Pos (9U)
8384#define ETH_DMACIER_RWTE_Msk (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */
8385#define ETH_DMACIER_RWTE ETH_DMACIER_RWTE_Msk /* Receive Watchdog Timeout Enable */
8386#define ETH_DMACIER_RSE_Pos (8U)
8387#define ETH_DMACIER_RSE_Msk (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */
8388#define ETH_DMACIER_RSE ETH_DMACIER_RSE_Msk /* Receive Stopped Enable */
8389#define ETH_DMACIER_RBUE_Pos (7U)
8390#define ETH_DMACIER_RBUE_Msk (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */
8391#define ETH_DMACIER_RBUE ETH_DMACIER_RBUE_Msk /* Receive Buffer Unavailable Enable */
8392#define ETH_DMACIER_RIE_Pos (6U)
8393#define ETH_DMACIER_RIE_Msk (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */
8394#define ETH_DMACIER_RIE ETH_DMACIER_RIE_Msk /* Receive Interrupt Enable */
8395#define ETH_DMACIER_TBUE_Pos (2U)
8396#define ETH_DMACIER_TBUE_Msk (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */
8397#define ETH_DMACIER_TBUE ETH_DMACIER_TBUE_Msk /* Transmit Buffer Unavailable Enable */
8398#define ETH_DMACIER_TXSE_Pos (1U)
8399#define ETH_DMACIER_TXSE_Msk (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */
8400#define ETH_DMACIER_TXSE ETH_DMACIER_TXSE_Msk /* Transmit Stopped Enable */
8401#define ETH_DMACIER_TIE_Pos (0U)
8402#define ETH_DMACIER_TIE_Msk (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */
8403#define ETH_DMACIER_TIE ETH_DMACIER_TIE_Msk /* Transmit Interrupt Enable */
8404
8405/* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */
8406#define ETH_DMACRIWTR_RWT_Pos (0U)
8407#define ETH_DMACRIWTR_RWT_Msk (0xFFUL << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */
8408#define ETH_DMACRIWTR_RWT ETH_DMACRIWTR_RWT_Msk /* Receive Interrupt Watchdog Timer Count */
8409
8410/* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */
8411#define ETH_DMACCATDR_CURTDESAPTR_Pos (0U)
8412#define ETH_DMACCATDR_CURTDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */
8413#define ETH_DMACCATDR_CURTDESAPTR ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
8414
8415/* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */
8416#define ETH_DMACCARDR_CURRDESAPTR_Pos (0U)
8417#define ETH_DMACCARDR_CURRDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */
8418#define ETH_DMACCARDR_CURRDESAPTR ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */
8419
8420/* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */
8421#define ETH_DMACCATBR_CURTBUFAPTR_Pos (0U)
8422#define ETH_DMACCATBR_CURTBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */
8423#define ETH_DMACCATBR_CURTBUFAPTR ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */
8424
8425/* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */
8426#define ETH_DMACCARBR_CURRBUFAPTR_Pos (0U)
8427#define ETH_DMACCARBR_CURRBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */
8428#define ETH_DMACCARBR_CURRBUFAPTR ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */
8429
8430/* Bit definition for Ethernet DMA Channel Status Register */
8431#define ETH_DMACSR_REB_Pos (19U)
8432#define ETH_DMACSR_REB_Msk (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */
8433#define ETH_DMACSR_REB ETH_DMACSR_REB_Msk /* Rx DMA Error Bits */
8434#define ETH_DMACSR_TEB_Pos (16U)
8435#define ETH_DMACSR_TEB_Msk (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */
8436#define ETH_DMACSR_TEB ETH_DMACSR_TEB_Msk /* Tx DMA Error Bits */
8437#define ETH_DMACSR_NIS_Pos (15U)
8438#define ETH_DMACSR_NIS_Msk (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */
8439#define ETH_DMACSR_NIS ETH_DMACSR_NIS_Msk /* Normal Interrupt Summary */
8440#define ETH_DMACSR_AIS_Pos (14U)
8441#define ETH_DMACSR_AIS_Msk (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */
8442#define ETH_DMACSR_AIS ETH_DMACSR_AIS_Msk /* Abnormal Interrupt Summary */
8443#define ETH_DMACSR_CDE_Pos (13U)
8444#define ETH_DMACSR_CDE_Msk (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */
8445#define ETH_DMACSR_CDE ETH_DMACSR_CDE_Msk /* Context Descriptor Error */
8446#define ETH_DMACSR_FBE_Pos (12U)
8447#define ETH_DMACSR_FBE_Msk (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */
8448#define ETH_DMACSR_FBE ETH_DMACSR_FBE_Msk /* Fatal Bus Error */
8449#define ETH_DMACSR_ERI_Pos (11U)
8450#define ETH_DMACSR_ERI_Msk (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */
8451#define ETH_DMACSR_ERI ETH_DMACSR_ERI_Msk /* Early Receive Interrupt */
8452#define ETH_DMACSR_ETI_Pos (10U)
8453#define ETH_DMACSR_ETI_Msk (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */
8454#define ETH_DMACSR_ETI ETH_DMACSR_ETI_Msk /* Early Transmit Interrupt */
8455#define ETH_DMACSR_RWT_Pos (9U)
8456#define ETH_DMACSR_RWT_Msk (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */
8457#define ETH_DMACSR_RWT ETH_DMACSR_RWT_Msk /* Receive Watchdog Timeout */
8458#define ETH_DMACSR_RPS_Pos (8U)
8459#define ETH_DMACSR_RPS_Msk (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */
8460#define ETH_DMACSR_RPS ETH_DMACSR_RPS_Msk /* Receive Process Stopped */
8461#define ETH_DMACSR_RBU_Pos (7U)
8462#define ETH_DMACSR_RBU_Msk (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */
8463#define ETH_DMACSR_RBU ETH_DMACSR_RBU_Msk /* Receive Buffer Unavailable */
8464#define ETH_DMACSR_RI_Pos (6U)
8465#define ETH_DMACSR_RI_Msk (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */
8466#define ETH_DMACSR_RI ETH_DMACSR_RI_Msk /* Receive Interrupt */
8467#define ETH_DMACSR_TBU_Pos (2U)
8468#define ETH_DMACSR_TBU_Msk (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */
8469#define ETH_DMACSR_TBU ETH_DMACSR_TBU_Msk /* Transmit Buffer Unavailable */
8470#define ETH_DMACSR_TPS_Pos (1U)
8471#define ETH_DMACSR_TPS_Msk (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */
8472#define ETH_DMACSR_TPS ETH_DMACSR_TPS_Msk /* Transmit Process Stopped */
8473#define ETH_DMACSR_TI_Pos (0U)
8474#define ETH_DMACSR_TI_Msk (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */
8475#define ETH_DMACSR_TI ETH_DMACSR_TI_Msk /* Transmit Interrupt */
8476
8477/* Bit definition for Ethernet DMA Channel missed frame count register */
8478#define ETH_DMACMFCR_MFCO_Pos (15U)
8479#define ETH_DMACMFCR_MFCO_Msk (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */
8480#define ETH_DMACMFCR_MFCO ETH_DMACMFCR_MFCO_Msk /* Overflow status of the MFC Counter */
8481#define ETH_DMACMFCR_MFC_Pos (0U)
8482#define ETH_DMACMFCR_MFC_Msk (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */
8483#define ETH_DMACMFCR_MFC ETH_DMACMFCR_MFC_Msk /* The number of packet counters dropped by the DMA */
8484
8485/******************************************************************************/
8486/* */
8487/* DMA Controller */
8488/* */
8489/******************************************************************************/
8490/******************** Bits definition for DMA_SxCR register *****************/
8491#define DMA_SxCR_MBURST_Pos (23U)
8492#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
8493#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk /*!< Memory burst transfer configuration */
8494#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
8495#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
8496#define DMA_SxCR_PBURST_Pos (21U)
8497#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
8498#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
8499#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
8500#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
8501#define DMA_SxCR_CT_Pos (19U)
8502#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
8503#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
8504#define DMA_SxCR_DBM_Pos (18U)
8505#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
8506#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk /*!< Double buffer mode */
8507#define DMA_SxCR_PL_Pos (16U)
8508#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
8509#define DMA_SxCR_PL DMA_SxCR_PL_Msk /*!< Priority level */
8510#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
8511#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
8512#define DMA_SxCR_PINCOS_Pos (15U)
8513#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
8514#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk /*!< Peripheral increment offset size */
8515#define DMA_SxCR_MSIZE_Pos (13U)
8516#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
8517#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk /*!< Memory data size */
8518#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
8519#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
8520#define DMA_SxCR_PSIZE_Pos (11U)
8521#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
8522#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk /*< Peripheral data size */
8523#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
8524#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
8525#define DMA_SxCR_MINC_Pos (10U)
8526#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
8527#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk /*!< Memory increment mode */
8528#define DMA_SxCR_PINC_Pos (9U)
8529#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
8530#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk /*!< Peripheral increment mode */
8531#define DMA_SxCR_CIRC_Pos (8U)
8532#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
8533#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk /*!< Circular mode */
8534#define DMA_SxCR_DIR_Pos (6U)
8535#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
8536#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk /*!< Data transfer direction */
8537#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
8538#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
8539#define DMA_SxCR_PFCTRL_Pos (5U)
8540#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
8541#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk /*!< Peripheral flow controller */
8542#define DMA_SxCR_TCIE_Pos (4U)
8543#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
8544#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk /*!< Transfer complete interrupt enable */
8545#define DMA_SxCR_HTIE_Pos (3U)
8546#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
8547#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk /*!< Half transfer interrupt enable */
8548#define DMA_SxCR_TEIE_Pos (2U)
8549#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
8550#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk /*!< Transfer error interrupt enable */
8551#define DMA_SxCR_DMEIE_Pos (1U)
8552#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
8553#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk /*!< Direct mode error interrupt enable */
8554#define DMA_SxCR_EN_Pos (0U)
8555#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
8556#define DMA_SxCR_EN DMA_SxCR_EN_Msk /*!< Stream enable / flag stream ready when read low */
8557
8558/******************** Bits definition for DMA_SxCNDTR register **************/
8559#define DMA_SxNDT_Pos (0U)
8560#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
8561#define DMA_SxNDT DMA_SxNDT_Msk /*!< Number of data items to transfer */
8562#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos) /*!< 0x00000001 */
8563#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos) /*!< 0x00000002 */
8564#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos) /*!< 0x00000004 */
8565#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos) /*!< 0x00000008 */
8566#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos) /*!< 0x00000010 */
8567#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos) /*!< 0x00000020 */
8568#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos) /*!< 0x00000040 */
8569#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos) /*!< 0x00000080 */
8570#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos) /*!< 0x00000100 */
8571#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos) /*!< 0x00000200 */
8572#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos) /*!< 0x00000400 */
8573#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos) /*!< 0x00000800 */
8574#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos) /*!< 0x00001000 */
8575#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos) /*!< 0x00002000 */
8576#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos) /*!< 0x00004000 */
8577#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos) /*!< 0x00008000 */
8578
8579/******************** Bits definition for DMA_SxFCR register ****************/
8580#define DMA_SxFCR_FEIE_Pos (7U)
8581#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
8582#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk /*!< FIFO error interrupt enable */
8583#define DMA_SxFCR_FS_Pos (3U)
8584#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
8585#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk /*!< FIFO status */
8586#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
8587#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
8588#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
8589#define DMA_SxFCR_DMDIS_Pos (2U)
8590#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
8591#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk /*!< Direct mode disable */
8592#define DMA_SxFCR_FTH_Pos (0U)
8593#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
8594#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk /*!< FIFO threshold selection */
8595#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
8596#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
8597
8598/******************** Bits definition for DMA_LISR register *****************/
8599#define DMA_LISR_TCIF3_Pos (27U)
8600#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
8601#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk /*!< Stream 3 transfer complete interrupt flag */
8602#define DMA_LISR_HTIF3_Pos (26U)
8603#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
8604#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk /*!< Stream 3 half transfer interrupt flag */
8605#define DMA_LISR_TEIF3_Pos (25U)
8606#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
8607#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk /*!< Stream 3 transfer error interrupt flag */
8608#define DMA_LISR_DMEIF3_Pos (24U)
8609#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
8610#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk /*!< Stream 3 direct mode error interrupt flag */
8611#define DMA_LISR_FEIF3_Pos (22U)
8612#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
8613#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk /*!< Stream 3 FIFO error interrupt flag */
8614#define DMA_LISR_TCIF2_Pos (21U)
8615#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
8616#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk /*!< Stream 2 transfer complete interrupt flag */
8617#define DMA_LISR_HTIF2_Pos (20U)
8618#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
8619#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk /*!< Stream 2 half transfer interrupt flag */
8620#define DMA_LISR_TEIF2_Pos (19U)
8621#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
8622#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk /*!< Stream 2 transfer error interrupt flag */
8623#define DMA_LISR_DMEIF2_Pos (18U)
8624#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
8625#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk /*!< Stream 2 direct mode error interrupt flag */
8626#define DMA_LISR_FEIF2_Pos (16U)
8627#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
8628#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk /*!< Stream 2 FIFO error interrupt flag */
8629#define DMA_LISR_TCIF1_Pos (11U)
8630#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
8631#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk /*!< Stream 1 transfer complete interrupt flag */
8632#define DMA_LISR_HTIF1_Pos (10U)
8633#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
8634#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk /*!< Stream 1 half transfer interrupt flag */
8635#define DMA_LISR_TEIF1_Pos (9U)
8636#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
8637#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk /*!< Stream 1 transfer error interrupt flag */
8638#define DMA_LISR_DMEIF1_Pos (8U)
8639#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
8640#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk /*!< Stream 1 direct mode error interrupt flag */
8641#define DMA_LISR_FEIF1_Pos (6U)
8642#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
8643#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk /*!< Stream 1 FIFO error interrupt flag */
8644#define DMA_LISR_TCIF0_Pos (5U)
8645#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
8646#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk /*!< Stream 0 transfer complete interrupt flag */
8647#define DMA_LISR_HTIF0_Pos (4U)
8648#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
8649#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk /*!< Stream 0 half transfer interrupt flag */
8650#define DMA_LISR_TEIF0_Pos (3U)
8651#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
8652#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk /*!< Stream 0 transfer error interrupt flag */
8653#define DMA_LISR_DMEIF0_Pos (2U)
8654#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
8655#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk /*!< Stream 0 direct mode error interrupt flag */
8656#define DMA_LISR_FEIF0_Pos (0U)
8657#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
8658#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk /*!< Stream 0 FIFO error interrupt flag */
8659
8660/******************** Bits definition for DMA_HISR register *****************/
8661#define DMA_HISR_TCIF7_Pos (27U)
8662#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
8663#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk /*!< Stream 7 transfer complete interrupt flag */
8664#define DMA_HISR_HTIF7_Pos (26U)
8665#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
8666#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk /*!< Stream 7 half transfer interrupt flag */
8667#define DMA_HISR_TEIF7_Pos (25U)
8668#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
8669#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk /*!< Stream 7 transfer error interrupt flag */
8670#define DMA_HISR_DMEIF7_Pos (24U)
8671#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
8672#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk /*!< Stream 7 direct mode error interrupt flag */
8673#define DMA_HISR_FEIF7_Pos (22U)
8674#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
8675#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk /*!< Stream 7 FIFO error interrupt flag */
8676#define DMA_HISR_TCIF6_Pos (21U)
8677#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
8678#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk /*!< Stream 6 transfer complete interrupt flag */
8679#define DMA_HISR_HTIF6_Pos (20U)
8680#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
8681#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk /*!< Stream 6 half transfer interrupt flag */
8682#define DMA_HISR_TEIF6_Pos (19U)
8683#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
8684#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk /*!< Stream 6 transfer error interrupt flag */
8685#define DMA_HISR_DMEIF6_Pos (18U)
8686#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
8687#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk /*!< Stream 6 direct mode error interrupt flag */
8688#define DMA_HISR_FEIF6_Pos (16U)
8689#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
8690#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk /*!< Stream 6 FIFO error interrupt flag */
8691#define DMA_HISR_TCIF5_Pos (11U)
8692#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
8693#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk /*!< Stream 5 transfer complete interrupt flag */
8694#define DMA_HISR_HTIF5_Pos (10U)
8695#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
8696#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk /*!< Stream 5 half transfer interrupt flag */
8697#define DMA_HISR_TEIF5_Pos (9U)
8698#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
8699#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk /*!< Stream 5 transfer error interrupt flag */
8700#define DMA_HISR_DMEIF5_Pos (8U)
8701#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
8702#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk /*!< Stream 5 direct mode error interrupt flag */
8703#define DMA_HISR_FEIF5_Pos (6U)
8704#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
8705#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk /*!< Stream 5 FIFO error interrupt flag */
8706#define DMA_HISR_TCIF4_Pos (5U)
8707#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
8708#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk /*!< Stream 4 transfer complete interrupt flag */
8709#define DMA_HISR_HTIF4_Pos (4U)
8710#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
8711#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk /*!< Stream 4 half transfer interrupt flag */
8712#define DMA_HISR_TEIF4_Pos (3U)
8713#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
8714#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk /*!< Stream 4 transfer error interrupt flag */
8715#define DMA_HISR_DMEIF4_Pos (2U)
8716#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
8717#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk /*!< Stream 4 direct mode error interrupt flag */
8718#define DMA_HISR_FEIF4_Pos (0U)
8719#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
8720#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk /*!< Stream 4 FIFO error interrupt flag */
8721
8722/******************** Bits definition for DMA_LIFCR register ****************/
8723#define DMA_LIFCR_CTCIF3_Pos (27U)
8724#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
8725#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk /*!< Stream 3 clear transfer complete interrupt flag */
8726#define DMA_LIFCR_CHTIF3_Pos (26U)
8727#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
8728#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk /*!< Stream 3 clear half transfer interrupt flag */
8729#define DMA_LIFCR_CTEIF3_Pos (25U)
8730#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
8731#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk /*!< Stream 3 clear transfer error interrupt flag */
8732#define DMA_LIFCR_CDMEIF3_Pos (24U)
8733#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
8734#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk /*!< Stream 3 clear direct mode error interrupt flag */
8735#define DMA_LIFCR_CFEIF3_Pos (22U)
8736#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
8737#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk /*!< Stream 3 clear FIFO error interrupt flag */
8738#define DMA_LIFCR_CTCIF2_Pos (21U)
8739#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
8740#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk /*!< Stream 2 clear transfer complete interrupt flag */
8741#define DMA_LIFCR_CHTIF2_Pos (20U)
8742#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
8743#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk /*!< Stream 2 clear half transfer interrupt flag */
8744#define DMA_LIFCR_CTEIF2_Pos (19U)
8745#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
8746#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk /*!< Stream 2 clear transfer error interrupt flag */
8747#define DMA_LIFCR_CDMEIF2_Pos (18U)
8748#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
8749#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk /*!< Stream 2 clear direct mode error interrupt flag */
8750#define DMA_LIFCR_CFEIF2_Pos (16U)
8751#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
8752#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk /*!< Stream 2 clear FIFO error interrupt flag */
8753#define DMA_LIFCR_CTCIF1_Pos (11U)
8754#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
8755#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk /*!< Stream 1 clear transfer complete interrupt flag */
8756#define DMA_LIFCR_CHTIF1_Pos (10U)
8757#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
8758#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk /*!< Stream 1 clear half transfer interrupt flag */
8759#define DMA_LIFCR_CTEIF1_Pos (9U)
8760#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
8761#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk /*!< Stream 1 clear transfer error interrupt flag */
8762#define DMA_LIFCR_CDMEIF1_Pos (8U)
8763#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
8764#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk /*!< Stream 1 clear direct mode error interrupt flag */
8765#define DMA_LIFCR_CFEIF1_Pos (6U)
8766#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
8767#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk /*!< Stream 1 clear FIFO error interrupt flag */
8768#define DMA_LIFCR_CTCIF0_Pos (5U)
8769#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
8770#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk /*!< Stream 0 clear transfer complete interrupt flag */
8771#define DMA_LIFCR_CHTIF0_Pos (4U)
8772#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
8773#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk /*!< Stream 0 clear half transfer interrupt flag */
8774#define DMA_LIFCR_CTEIF0_Pos (3U)
8775#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
8776#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk /*!< Stream 0 clear transfer error interrupt flag */
8777#define DMA_LIFCR_CDMEIF0_Pos (2U)
8778#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
8779#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk /*!< Stream 0 clear direct mode error interrupt flag */
8780#define DMA_LIFCR_CFEIF0_Pos (0U)
8781#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
8782#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk /*!< Stream 0 clear FIFO error interrupt flag */
8783
8784/******************** Bits definition for DMA_HIFCR register ****************/
8785#define DMA_HIFCR_CTCIF7_Pos (27U)
8786#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
8787#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk /*!< Stream 7 clear transfer complete interrupt flag */
8788#define DMA_HIFCR_CHTIF7_Pos (26U)
8789#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
8790#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk /*!< Stream 7 clear half transfer interrupt flag */
8791#define DMA_HIFCR_CTEIF7_Pos (25U)
8792#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
8793#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk /*!< Stream 7 clear transfer error interrupt flag */
8794#define DMA_HIFCR_CDMEIF7_Pos (24U)
8795#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
8796#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk /*!< Stream 7 clear direct mode error interrupt flag */
8797#define DMA_HIFCR_CFEIF7_Pos (22U)
8798#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
8799#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk /*!< Stream 7 clear FIFO error interrupt flag */
8800#define DMA_HIFCR_CTCIF6_Pos (21U)
8801#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
8802#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk /*!< Stream 6 clear transfer complete interrupt flag */
8803#define DMA_HIFCR_CHTIF6_Pos (20U)
8804#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
8805#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk /*!< Stream 6 clear half transfer interrupt flag */
8806#define DMA_HIFCR_CTEIF6_Pos (19U)
8807#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
8808#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk /*!< Stream 6 clear transfer error interrupt flag */
8809#define DMA_HIFCR_CDMEIF6_Pos (18U)
8810#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
8811#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk /*!< Stream 6 clear direct mode error interrupt flag */
8812#define DMA_HIFCR_CFEIF6_Pos (16U)
8813#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
8814#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk /*!< Stream 6 clear FIFO error interrupt flag */
8815#define DMA_HIFCR_CTCIF5_Pos (11U)
8816#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
8817#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk /*!< Stream 5 clear transfer complete interrupt flag */
8818#define DMA_HIFCR_CHTIF5_Pos (10U)
8819#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
8820#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk /*!< Stream 5 clear half transfer interrupt flag */
8821#define DMA_HIFCR_CTEIF5_Pos (9U)
8822#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
8823#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk /*!< Stream 5 clear transfer error interrupt flag */
8824#define DMA_HIFCR_CDMEIF5_Pos (8U)
8825#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
8826#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk /*!< Stream 5 clear direct mode error interrupt flag */
8827#define DMA_HIFCR_CFEIF5_Pos (6U)
8828#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
8829#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk /*!< Stream 5 clear FIFO error interrupt flag */
8830#define DMA_HIFCR_CTCIF4_Pos (5U)
8831#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
8832#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk /*!< Stream 4 clear transfer complete interrupt flag */
8833#define DMA_HIFCR_CHTIF4_Pos (4U)
8834#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
8835#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk /*!< Stream 4 clear half transfer interrupt flag */
8836#define DMA_HIFCR_CTEIF4_Pos (3U)
8837#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
8838#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk /*!< Stream 4 clear transfer error interrupt flag */
8839#define DMA_HIFCR_CDMEIF4_Pos (2U)
8840#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
8841#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk /*!< Stream 4 clear direct mode error interrupt flag */
8842#define DMA_HIFCR_CFEIF4_Pos (0U)
8843#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
8844#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk /*!< Stream 4 clear FIFO error interrupt flag */
8845
8846/****************** Bit definition for DMA_SxPAR register ********************/
8847#define DMA_SxPAR_PA_Pos (0U)
8848#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
8849#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
8850
8851/****************** Bit definition for DMA_SxM0AR register ********************/
8852#define DMA_SxM0AR_M0A_Pos (0U)
8853#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
8854#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory 0 Address */
8855
8856/****************** Bit definition for DMA_SxM1AR register ********************/
8857#define DMA_SxM1AR_M1A_Pos (0U)
8858#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
8859#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory 1 Address */
8860
8861/******************************************************************************/
8862/* */
8863/* DMAMUX Controller */
8864/* */
8865/******************************************************************************/
8866/******************** Bits definition for DMAMUX_CxCR register **************/
8867#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
8868#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */
8869#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA request identification */
8870#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
8871#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
8872#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
8873#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
8874#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
8875#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
8876#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
8877#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
8878#define DMAMUX_CxCR_SOIE_Pos (8U)
8879#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
8880#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchronization overrun interrupt enable */
8881#define DMAMUX_CxCR_EGE_Pos (9U)
8882#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */
8883#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation enable */
8884#define DMAMUX_CxCR_SE_Pos (16U)
8885#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */
8886#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */
8887#define DMAMUX_CxCR_SPOL_Pos (17U)
8888#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
8889#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */
8890#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */
8891#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */
8892#define DMAMUX_CxCR_NBREQ_Pos (19U)
8893#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
8894#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of DMA requests minus 1 to forward */
8895#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
8896#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
8897#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
8898#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
8899#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
8900#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
8901#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
8902#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization identification */
8903#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
8904#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
8905#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
8906#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
8907#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
8908
8909/******************** Bits definition for DMAMUX_CSR register **************/
8910#define DMAMUX_CSR_SOF0_Pos (0U)
8911#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */
8912#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Channel 0 Synchronization overrun event flag */
8913#define DMAMUX_CSR_SOF1_Pos (1U)
8914#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */
8915#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Channel 1 Synchronization overrun event flag */
8916#define DMAMUX_CSR_SOF2_Pos (2U)
8917#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */
8918#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Channel 2 Synchronization overrun event flag */
8919#define DMAMUX_CSR_SOF3_Pos (3U)
8920#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */
8921#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Channel 3 Synchronization overrun event flag */
8922#define DMAMUX_CSR_SOF4_Pos (4U)
8923#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */
8924#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Channel 4 Synchronization overrun event flag */
8925#define DMAMUX_CSR_SOF5_Pos (5U)
8926#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */
8927#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Channel 5 Synchronization overrun event flag */
8928#define DMAMUX_CSR_SOF6_Pos (6U)
8929#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */
8930#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Channel 6 Synchronization overrun event flag */
8931#define DMAMUX_CSR_SOF7_Pos (7U)
8932#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */
8933#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk /*!< Channel 7 Synchronization overrun event flag */
8934#define DMAMUX_CSR_SOF8_Pos (8U)
8935#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */
8936#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk /*!< Channel 8 Synchronization overrun event flag */
8937#define DMAMUX_CSR_SOF9_Pos (9U)
8938#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */
8939#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk /*!< Channel 9 Synchronization overrun event flag */
8940#define DMAMUX_CSR_SOF10_Pos (10U)
8941#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */
8942#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk /*!< Channel 10 Synchronization overrun event flag */
8943#define DMAMUX_CSR_SOF11_Pos (11U)
8944#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */
8945#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk /*!< Channel 11 Synchronization overrun event flag */
8946#define DMAMUX_CSR_SOF12_Pos (12U)
8947#define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */
8948#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk /*!< Channel 12 Synchronization overrun event flag */
8949#define DMAMUX_CSR_SOF13_Pos (13U)
8950#define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */
8951#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk /*!< Channel 13 Synchronization overrun event flag */
8952#define DMAMUX_CSR_SOF14_Pos (14U)
8953#define DMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos) /*!< 0x00004000 */
8954#define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk /*!< Channel 14 Synchronization overrun event flag */
8955#define DMAMUX_CSR_SOF15_Pos (15U)
8956#define DMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos) /*!< 0x00008000 */
8957#define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk /*!< Channel 15 Synchronization overrun event flag */
8958
8959/******************** Bits definition for DMAMUX_CFR register **************/
8960#define DMAMUX_CFR_CSOF0_Pos (0U)
8961#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
8962#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Channel 0 Clear synchronization overrun event flag */
8963#define DMAMUX_CFR_CSOF1_Pos (1U)
8964#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
8965#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Channel 1 Clear synchronization overrun event flag */
8966#define DMAMUX_CFR_CSOF2_Pos (2U)
8967#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
8968#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Channel 2 Clear synchronization overrun event flag */
8969#define DMAMUX_CFR_CSOF3_Pos (3U)
8970#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
8971#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Channel 3 Clear synchronization overrun event flag */
8972#define DMAMUX_CFR_CSOF4_Pos (4U)
8973#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
8974#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Channel 4 Clear synchronization overrun event flag */
8975#define DMAMUX_CFR_CSOF5_Pos (5U)
8976#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
8977#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Channel 5 Clear synchronization overrun event flag */
8978#define DMAMUX_CFR_CSOF6_Pos (6U)
8979#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
8980#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Channel 6 Clear synchronization overrun event flag */
8981#define DMAMUX_CFR_CSOF7_Pos (7U)
8982#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */
8983#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk /*!< Channel 7 Clear synchronization overrun event flag */
8984#define DMAMUX_CFR_CSOF8_Pos (8U)
8985#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */
8986#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk /*!< Channel 8 Clear synchronization overrun event flag */
8987#define DMAMUX_CFR_CSOF9_Pos (9U)
8988#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */
8989#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk /*!< Channel 9 Clear synchronization overrun event flag */
8990#define DMAMUX_CFR_CSOF10_Pos (10U)
8991#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */
8992#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk /*!< Channel 10 Clear synchronization overrun event flag */
8993#define DMAMUX_CFR_CSOF11_Pos (11U)
8994#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */
8995#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk /*!< Channel 11 Clear synchronization overrun event flag */
8996#define DMAMUX_CFR_CSOF12_Pos (12U)
8997#define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos) /*!< 0x00001000 */
8998#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk /*!< Channel 12 Clear synchronization overrun event flag */
8999#define DMAMUX_CFR_CSOF13_Pos (13U)
9000#define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos) /*!< 0x00002000 */
9001#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk /*!< Channel 13 Clear synchronization overrun event flag */
9002#define DMAMUX_CFR_CSOF14_Pos (14U)
9003#define DMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos) /*!< 0x00004000 */
9004#define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk /*!< Channel 14 Clear synchronization overrun event flag */
9005#define DMAMUX_CFR_CSOF15_Pos (15U)
9006#define DMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos) /*!< 0x00008000 */
9007#define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk /*!< Channel 15 Clear synchronization overrun event flag */
9008
9009/******************** Bits definition for DMAMUX_RGxCR register ************/
9010#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
9011#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
9012#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal identification */
9013#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
9014#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
9015#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
9016#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
9017#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
9018#define DMAMUX_RGxCR_OIE_Pos (8U)
9019#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
9020#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Trigger overrun interrupt enable */
9021#define DMAMUX_RGxCR_GE_Pos (16U)
9022#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */
9023#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< DMA request generator enable */
9024#define DMAMUX_RGxCR_GPOL_Pos (17U)
9025#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
9026#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< DMA request generator trigger polarity */
9027#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
9028#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
9029#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
9030#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
9031#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of DMA requests to be generated */
9032#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
9033#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */
9034#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */
9035#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */
9036#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */
9037
9038/******************** Bits definition for DMAMUX_RGSR register **************/
9039#define DMAMUX_RGSR_OF0_Pos (0U)
9040#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */
9041#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Request generator channel 0 Trigger overrun event flag */
9042#define DMAMUX_RGSR_OF1_Pos (1U)
9043#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */
9044#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Request generator channel 1 Trigger overrun event flag */
9045#define DMAMUX_RGSR_OF2_Pos (2U)
9046#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */
9047#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Request generator channel 2 Trigger overrun event flag */
9048#define DMAMUX_RGSR_OF3_Pos (3U)
9049#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */
9050#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Request generator channel 3 Trigger overrun event flag */
9051#define DMAMUX_RGSR_OF4_Pos (4U)
9052#define DMAMUX_RGSR_OF4_Msk (0x1UL << DMAMUX_RGSR_OF4_Pos) /*!< 0x00000010 */
9053#define DMAMUX_RGSR_OF4 DMAMUX_RGSR_OF4_Msk /*!< Request generator channel 4 Trigger overrun event flag */
9054#define DMAMUX_RGSR_OF5_Pos (5U)
9055#define DMAMUX_RGSR_OF5_Msk (0x1UL << DMAMUX_RGSR_OF5_Pos) /*!< 0x00000020 */
9056#define DMAMUX_RGSR_OF5 DMAMUX_RGSR_OF5_Msk /*!< Request generator channel 5 Trigger overrun event flag */
9057#define DMAMUX_RGSR_OF6_Pos (6U)
9058#define DMAMUX_RGSR_OF6_Msk (0x1UL << DMAMUX_RGSR_OF6_Pos) /*!< 0x00000040 */
9059#define DMAMUX_RGSR_OF6 DMAMUX_RGSR_OF6_Msk /*!< Request generator channel 6 Trigger overrun event flag */
9060#define DMAMUX_RGSR_OF7_Pos (7U)
9061#define DMAMUX_RGSR_OF7_Msk (0x1UL << DMAMUX_RGSR_OF7_Pos) /*!< 0x00000080 */
9062#define DMAMUX_RGSR_OF7 DMAMUX_RGSR_OF7_Msk /*!< Request generator channel 7 Trigger overrun event flag */
9063
9064/******************** Bits definition for DMAMUX_RGCFR register **************/
9065#define DMAMUX_RGCFR_COF0_Pos (0U)
9066#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
9067#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Request generator channel 0 Clear trigger overrun event flag */
9068#define DMAMUX_RGCFR_COF1_Pos (1U)
9069#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
9070#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Request generator channel 1 Clear trigger overrun event flag */
9071#define DMAMUX_RGCFR_COF2_Pos (2U)
9072#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
9073#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Request generator channel 2 Clear trigger overrun event flag */
9074#define DMAMUX_RGCFR_COF3_Pos (3U)
9075#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
9076#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Request generator channel 3 Clear trigger overrun event flag */
9077#define DMAMUX_RGCFR_COF4_Pos (4U)
9078#define DMAMUX_RGCFR_COF4_Msk (0x1UL << DMAMUX_RGCFR_COF4_Pos) /*!< 0x00000010 */
9079#define DMAMUX_RGCFR_COF4 DMAMUX_RGCFR_COF4_Msk /*!< Request generator channel 4 Clear trigger overrun event flag */
9080#define DMAMUX_RGCFR_COF5_Pos (5U)
9081#define DMAMUX_RGCFR_COF5_Msk (0x1UL << DMAMUX_RGCFR_COF5_Pos) /*!< 0x00000020 */
9082#define DMAMUX_RGCFR_COF5 DMAMUX_RGCFR_COF5_Msk /*!< Request generator channel 5 Clear trigger overrun event flag */
9083#define DMAMUX_RGCFR_COF6_Pos (6U)
9084#define DMAMUX_RGCFR_COF6_Msk (0x1UL << DMAMUX_RGCFR_COF6_Pos) /*!< 0x00000040 */
9085#define DMAMUX_RGCFR_COF6 DMAMUX_RGCFR_COF6_Msk /*!< Request generator channel 6 Clear trigger overrun event flag */
9086#define DMAMUX_RGCFR_COF7_Pos (7U)
9087#define DMAMUX_RGCFR_COF7_Msk (0x1UL << DMAMUX_RGCFR_COF7_Pos) /*!< 0x00000080 */
9088#define DMAMUX_RGCFR_COF7 DMAMUX_RGCFR_COF7_Msk /*!< Request generator channel 7 Clear trigger overrun event flag */
9089
9090/******************************************************************************/
9091/* */
9092/* AHB Master DMA2D Controller (DMA2D) */
9093/* */
9094/******************************************************************************/
9095
9096/******************** Bit definition for DMA2D_CR register ******************/
9097
9098#define DMA2D_CR_START_Pos (0U)
9099#define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos) /*!< 0x00000001 */
9100#define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
9101#define DMA2D_CR_SUSP_Pos (1U)
9102#define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
9103#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
9104#define DMA2D_CR_ABORT_Pos (2U)
9105#define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
9106#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
9107#define DMA2D_CR_LOM_Pos (6U)
9108#define DMA2D_CR_LOM_Msk (0x1UL << DMA2D_CR_LOM_Pos) /*!< 0x00000040 */
9109#define DMA2D_CR_LOM DMA2D_CR_LOM_Msk /*!< Line Offset Mode */
9110#define DMA2D_CR_TEIE_Pos (8U)
9111#define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
9112#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
9113#define DMA2D_CR_TCIE_Pos (9U)
9114#define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
9115#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
9116#define DMA2D_CR_TWIE_Pos (10U)
9117#define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
9118#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
9119#define DMA2D_CR_CAEIE_Pos (11U)
9120#define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
9121#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
9122#define DMA2D_CR_CTCIE_Pos (12U)
9123#define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
9124#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
9125#define DMA2D_CR_CEIE_Pos (13U)
9126#define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
9127#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
9128#define DMA2D_CR_MODE_Pos (16U)
9129#define DMA2D_CR_MODE_Msk (0x7UL << DMA2D_CR_MODE_Pos) /*!< 0x00070000 */
9130#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[2:0] */
9131#define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
9132#define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
9133#define DMA2D_CR_MODE_2 (0x4UL << DMA2D_CR_MODE_Pos) /*!< 0x00040000 */
9134
9135/******************** Bit definition for DMA2D_ISR register *****************/
9136
9137#define DMA2D_ISR_TEIF_Pos (0U)
9138#define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
9139#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
9140#define DMA2D_ISR_TCIF_Pos (1U)
9141#define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
9142#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
9143#define DMA2D_ISR_TWIF_Pos (2U)
9144#define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
9145#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
9146#define DMA2D_ISR_CAEIF_Pos (3U)
9147#define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
9148#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
9149#define DMA2D_ISR_CTCIF_Pos (4U)
9150#define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
9151#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
9152#define DMA2D_ISR_CEIF_Pos (5U)
9153#define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
9154#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
9155
9156/******************** Bit definition for DMA2D_IFCR register ****************/
9157
9158#define DMA2D_IFCR_CTEIF_Pos (0U)
9159#define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
9160#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
9161#define DMA2D_IFCR_CTCIF_Pos (1U)
9162#define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
9163#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
9164#define DMA2D_IFCR_CTWIF_Pos (2U)
9165#define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
9166#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
9167#define DMA2D_IFCR_CAECIF_Pos (3U)
9168#define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
9169#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
9170#define DMA2D_IFCR_CCTCIF_Pos (4U)
9171#define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
9172#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
9173#define DMA2D_IFCR_CCEIF_Pos (5U)
9174#define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
9175#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
9176
9177/******************** Bit definition for DMA2D_FGMAR register ***************/
9178
9179#define DMA2D_FGMAR_MA_Pos (0U)
9180#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
9181#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Foreground Memory Address */
9182
9183/******************** Bit definition for DMA2D_FGOR register ****************/
9184
9185#define DMA2D_FGOR_LO_Pos (0U)
9186#define DMA2D_FGOR_LO_Msk (0xFFFFUL << DMA2D_FGOR_LO_Pos) /*!< 0x0000FFFF */
9187#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
9188
9189/******************** Bit definition for DMA2D_BGMAR register ***************/
9190
9191#define DMA2D_BGMAR_MA_Pos (0U)
9192#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
9193#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Background Memory Address */
9194
9195/******************** Bit definition for DMA2D_BGOR register ****************/
9196
9197#define DMA2D_BGOR_LO_Pos (0U)
9198#define DMA2D_BGOR_LO_Msk (0xFFFFUL << DMA2D_BGOR_LO_Pos) /*!< 0x0000FFFF */
9199#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
9200
9201/******************** Bit definition for DMA2D_FGPFCCR register *************/
9202
9203#define DMA2D_FGPFCCR_CM_Pos (0U)
9204#define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
9205#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
9206#define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
9207#define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
9208#define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
9209#define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
9210#define DMA2D_FGPFCCR_CCM_Pos (4U)
9211#define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
9212#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
9213#define DMA2D_FGPFCCR_START_Pos (5U)
9214#define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
9215#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
9216#define DMA2D_FGPFCCR_CS_Pos (8U)
9217#define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
9218#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
9219#define DMA2D_FGPFCCR_AM_Pos (16U)
9220#define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
9221#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
9222#define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
9223#define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
9224#define DMA2D_FGPFCCR_CSS_Pos (18U)
9225#define DMA2D_FGPFCCR_CSS_Msk (0x3UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x000C0000 */
9226#define DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sampling */
9227#define DMA2D_FGPFCCR_CSS_0 (0x1UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00040000 */
9228#define DMA2D_FGPFCCR_CSS_1 (0x2UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00080000 */
9229#define DMA2D_FGPFCCR_AI_Pos (20U)
9230#define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos) /*!< 0x00100000 */
9231#define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk /*!< Foreground Input Alpha Inverted */
9232#define DMA2D_FGPFCCR_RBS_Pos (21U)
9233#define DMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos) /*!< 0x00200000 */
9234#define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk /*!< Foreground Input Red Blue Swap */
9235#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
9236#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
9237#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
9238
9239/******************** Bit definition for DMA2D_FGCOLR register **************/
9240
9241#define DMA2D_FGCOLR_BLUE_Pos (0U)
9242#define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
9243#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Foreground Blue Value */
9244#define DMA2D_FGCOLR_GREEN_Pos (8U)
9245#define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
9246#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Foreground Green Value */
9247#define DMA2D_FGCOLR_RED_Pos (16U)
9248#define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
9249#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Foreground Red Value */
9250
9251/******************** Bit definition for DMA2D_BGPFCCR register *************/
9252
9253#define DMA2D_BGPFCCR_CM_Pos (0U)
9254#define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
9255#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
9256#define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
9257#define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
9258#define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
9259#define DMA2D_BGPFCCR_CM_3 (0x8UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000008 */
9260#define DMA2D_BGPFCCR_CCM_Pos (4U)
9261#define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
9262#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
9263#define DMA2D_BGPFCCR_START_Pos (5U)
9264#define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
9265#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
9266#define DMA2D_BGPFCCR_CS_Pos (8U)
9267#define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
9268#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
9269#define DMA2D_BGPFCCR_AM_Pos (16U)
9270#define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
9271#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
9272#define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
9273#define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
9274#define DMA2D_BGPFCCR_AI_Pos (20U)
9275#define DMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos) /*!< 0x00100000 */
9276#define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk /*!< background Input Alpha Inverted */
9277#define DMA2D_BGPFCCR_RBS_Pos (21U)
9278#define DMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos) /*!< 0x00200000 */
9279#define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk /*!< Background Input Red Blue Swap */
9280#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
9281#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
9282#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
9283
9284/******************** Bit definition for DMA2D_BGCOLR register **************/
9285
9286#define DMA2D_BGCOLR_BLUE_Pos (0U)
9287#define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
9288#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Background Blue Value */
9289#define DMA2D_BGCOLR_GREEN_Pos (8U)
9290#define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
9291#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Background Green Value */
9292#define DMA2D_BGCOLR_RED_Pos (16U)
9293#define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
9294#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Background Red Value */
9295
9296/******************** Bit definition for DMA2D_FGCMAR register **************/
9297
9298#define DMA2D_FGCMAR_MA_Pos (0U)
9299#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
9300#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Foreground CLUT Memory Address */
9301
9302/******************** Bit definition for DMA2D_BGCMAR register **************/
9303
9304#define DMA2D_BGCMAR_MA_Pos (0U)
9305#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
9306#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Background CLUT Memory Address */
9307
9308/******************** Bit definition for DMA2D_OPFCCR register **************/
9309
9310#define DMA2D_OPFCCR_CM_Pos (0U)
9311#define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
9312#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Output Color mode CM[2:0] */
9313#define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
9314#define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
9315#define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
9316#define DMA2D_OPFCCR_SB_Pos (8U)
9317#define DMA2D_OPFCCR_SB_Msk (0x1UL << DMA2D_OPFCCR_SB_Pos) /*!< 0x00000100 */
9318#define DMA2D_OPFCCR_SB DMA2D_OPFCCR_SB_Msk /*!< Swap Bytes */
9319#define DMA2D_OPFCCR_AI_Pos (20U)
9320#define DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos) /*!< 0x00100000 */
9321#define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk /*!< Output Alpha Inverted */
9322#define DMA2D_OPFCCR_RBS_Pos (21U)
9323#define DMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos) /*!< 0x00200000 */
9324#define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk /*!< Output Red Blue Swap */
9325
9326/******************** Bit definition for DMA2D_OCOLR register ***************/
9327
9328/*!<Mode_ARGB8888/RGB888 */
9329
9330#define DMA2D_OCOLR_BLUE_1_Pos (0U)
9331#define DMA2D_OCOLR_BLUE_1_Msk (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos) /*0x000000FFU*/
9332#define DMA2D_OCOLR_BLUE_1 DMA2D_OCOLR_BLUE_1_Msk /*!< Output BLUE Value */
9333#define DMA2D_OCOLR_GREEN_1_Pos (8U)
9334#define DMA2D_OCOLR_GREEN_1_Msk (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos) /*0x0000FF00U)*/
9335#define DMA2D_OCOLR_GREEN_1 DMA2D_OCOLR_GREEN_1_Msk /*!< Output GREEN Value */
9336#define DMA2D_OCOLR_RED_1_Pos (16U)
9337#define DMA2D_OCOLR_RED_1_Msk (0xFFUL << DMA2D_OCOLR_RED_1_Pos) /*0x00FF0000U */
9338#define DMA2D_OCOLR_RED_1 DMA2D_OCOLR_RED_1_Msk /*!< Output Red Value */
9339#define DMA2D_OCOLR_ALPHA_1_Pos (24U)
9340#define DMA2D_OCOLR_ALPHA_1_Msk (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos) /*0xFF000000U*/
9341#define DMA2D_OCOLR_ALPHA_1 DMA2D_OCOLR_ALPHA_1_Msk /*!< Output Alpha Channel Value */
9342
9343/*!<Mode_RGB565 */
9344#define DMA2D_OCOLR_BLUE_2_Pos (0U)
9345#define DMA2D_OCOLR_BLUE_2_Msk (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos) /*0x0000001FU*/
9346#define DMA2D_OCOLR_BLUE_2 DMA2D_OCOLR_BLUE_2_Msk /*!< Output BLUE Value */
9347#define DMA2D_OCOLR_GREEN_2_Pos (5U)
9348#define DMA2D_OCOLR_GREEN_2_Msk (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos) /* 0x000007E0U */
9349#define DMA2D_OCOLR_GREEN_2 DMA2D_OCOLR_GREEN_2_Msk /*!< Output GREEN Value */
9350#define DMA2D_OCOLR_RED_2_Pos (11U)
9351#define DMA2D_OCOLR_RED_2_Msk (0xF8UL<<DMA2D_OCOLR_RED_2_Pos) /*0x0000F800U*/
9352#define DMA2D_OCOLR_RED_2 DMA2D_OCOLR_RED_2_Msk /*!< Output Red Value */
9353
9354/*!<Mode_ARGB1555 */
9355#define DMA2D_OCOLR_BLUE_3_Pos (0U)
9356#define DMA2D_OCOLR_BLUE_3_Msk (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos) /*0x0000001FU*/
9357#define DMA2D_OCOLR_BLUE_3 DMA2D_OCOLR_BLUE_3_Msk /*!< Output BLUE Value */
9358#define DMA2D_OCOLR_GREEN_3_Pos (5U)
9359#define DMA2D_OCOLR_GREEN_3_Msk (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos) /*0x000003E0U*/
9360#define DMA2D_OCOLR_GREEN_3 DMA2D_OCOLR_GREEN_3_Msk /*!< Output GREEN Value */
9361#define DMA2D_OCOLR_RED_3_Pos (10U)
9362#define DMA2D_OCOLR_RED_3_Msk (0x7CUL << DMA2D_OCOLR_RED_3_Pos) /* 0x00007C00U*/
9363#define DMA2D_OCOLR_RED_3 DMA2D_OCOLR_RED_3_Msk /*!< Output Red Value */
9364#define DMA2D_OCOLR_ALPHA_3_Pos (15U)
9365#define DMA2D_OCOLR_ALPHA_3_Msk (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos) /*0x00008000U*/
9366#define DMA2D_OCOLR_ALPHA_3 DMA2D_OCOLR_ALPHA_3_Msk /*!< Output Alpha Channel Value */
9367
9368/*!<Mode_ARGB4444 */
9369#define DMA2D_OCOLR_BLUE_4_Pos (0U)
9370#define DMA2D_OCOLR_BLUE_4_Msk (0xFUL << DMA2D_OCOLR_BLUE_4_Pos) /*0x0000000FU*/
9371#define DMA2D_OCOLR_BLUE_4 DMA2D_OCOLR_BLUE_4_Msk /*!< Output BLUE Value */
9372#define DMA2D_OCOLR_GREEN_4_Pos (4U)
9373#define DMA2D_OCOLR_GREEN_4_Msk (0xFUL << DMA2D_OCOLR_GREEN_4_Pos) /*0x000000F0U*/
9374#define DMA2D_OCOLR_GREEN_4 DMA2D_OCOLR_GREEN_4_Msk /*!< Output GREEN Value */
9375#define DMA2D_OCOLR_RED_4_Pos (8U)
9376#define DMA2D_OCOLR_RED_4_Msk (0xFUL << DMA2D_OCOLR_RED_4_Pos) /*0x00000F00U*/
9377#define DMA2D_OCOLR_RED_4 DMA2D_OCOLR_RED_4_Msk /*!< Output Red Value */
9378#define DMA2D_OCOLR_ALPHA_4_Pos (12U)
9379#define DMA2D_OCOLR_ALPHA_4_Msk (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos) /*0x0000F000U*/
9380#define DMA2D_OCOLR_ALPHA_4 DMA2D_OCOLR_ALPHA_4_Msk /*!< Output Alpha Channel Value */
9381
9382/******************** Bit definition for DMA2D_OMAR register ****************/
9383
9384#define DMA2D_OMAR_MA_Pos (0U)
9385#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
9386#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Output Memory Address */
9387
9388/******************** Bit definition for DMA2D_OOR register *****************/
9389
9390#define DMA2D_OOR_LO_Pos (0U)
9391#define DMA2D_OOR_LO_Msk (0xFFFFUL << DMA2D_OOR_LO_Pos) /*!< 0x0000FFFF */
9392#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Output Line Offset */
9393
9394/******************** Bit definition for DMA2D_NLR register *****************/
9395
9396#define DMA2D_NLR_NL_Pos (0U)
9397#define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
9398#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
9399#define DMA2D_NLR_PL_Pos (16U)
9400#define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
9401#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
9402
9403/******************** Bit definition for DMA2D_LWR register *****************/
9404
9405#define DMA2D_LWR_LW_Pos (0U)
9406#define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
9407#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
9408
9409/******************** Bit definition for DMA2D_AMTCR register ***************/
9410
9411#define DMA2D_AMTCR_EN_Pos (0U)
9412#define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
9413#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
9414#define DMA2D_AMTCR_DT_Pos (8U)
9415#define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
9416#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
9417
9418
9419/******************** Bit definition for DMA2D_FGCLUT register **************/
9420
9421/******************** Bit definition for DMA2D_BGCLUT register **************/
9422
9423
9424/******************************************************************************/
9425/* */
9426/* External Interrupt/Event Controller */
9427/* */
9428/******************************************************************************/
9429/****************** Bit definition for EXTI_RTSR1 register *******************/
9430#define EXTI_RTSR1_TR_Pos (0U)
9431#define EXTI_RTSR1_TR_Msk (0x3FFFFFUL << EXTI_RTSR1_TR_Pos) /*!< 0x003FFFFF */
9432#define EXTI_RTSR1_TR EXTI_RTSR1_TR_Msk /*!< Rising trigger event configuration bit */
9433#define EXTI_RTSR1_TR0_Pos (0U)
9434#define EXTI_RTSR1_TR0_Msk (0x1UL << EXTI_RTSR1_TR0_Pos) /*!< 0x00000001 */
9435#define EXTI_RTSR1_TR0 EXTI_RTSR1_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
9436#define EXTI_RTSR1_TR1_Pos (1U)
9437#define EXTI_RTSR1_TR1_Msk (0x1UL << EXTI_RTSR1_TR1_Pos) /*!< 0x00000002 */
9438#define EXTI_RTSR1_TR1 EXTI_RTSR1_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
9439#define EXTI_RTSR1_TR2_Pos (2U)
9440#define EXTI_RTSR1_TR2_Msk (0x1UL << EXTI_RTSR1_TR2_Pos) /*!< 0x00000004 */
9441#define EXTI_RTSR1_TR2 EXTI_RTSR1_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
9442#define EXTI_RTSR1_TR3_Pos (3U)
9443#define EXTI_RTSR1_TR3_Msk (0x1UL << EXTI_RTSR1_TR3_Pos) /*!< 0x00000008 */
9444#define EXTI_RTSR1_TR3 EXTI_RTSR1_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
9445#define EXTI_RTSR1_TR4_Pos (4U)
9446#define EXTI_RTSR1_TR4_Msk (0x1UL << EXTI_RTSR1_TR4_Pos) /*!< 0x00000010 */
9447#define EXTI_RTSR1_TR4 EXTI_RTSR1_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
9448#define EXTI_RTSR1_TR5_Pos (5U)
9449#define EXTI_RTSR1_TR5_Msk (0x1UL << EXTI_RTSR1_TR5_Pos) /*!< 0x00000020 */
9450#define EXTI_RTSR1_TR5 EXTI_RTSR1_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
9451#define EXTI_RTSR1_TR6_Pos (6U)
9452#define EXTI_RTSR1_TR6_Msk (0x1UL << EXTI_RTSR1_TR6_Pos) /*!< 0x00000040 */
9453#define EXTI_RTSR1_TR6 EXTI_RTSR1_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
9454#define EXTI_RTSR1_TR7_Pos (7U)
9455#define EXTI_RTSR1_TR7_Msk (0x1UL << EXTI_RTSR1_TR7_Pos) /*!< 0x00000080 */
9456#define EXTI_RTSR1_TR7 EXTI_RTSR1_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
9457#define EXTI_RTSR1_TR8_Pos (8U)
9458#define EXTI_RTSR1_TR8_Msk (0x1UL << EXTI_RTSR1_TR8_Pos) /*!< 0x00000100 */
9459#define EXTI_RTSR1_TR8 EXTI_RTSR1_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
9460#define EXTI_RTSR1_TR9_Pos (9U)
9461#define EXTI_RTSR1_TR9_Msk (0x1UL << EXTI_RTSR1_TR9_Pos) /*!< 0x00000200 */
9462#define EXTI_RTSR1_TR9 EXTI_RTSR1_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
9463#define EXTI_RTSR1_TR10_Pos (10U)
9464#define EXTI_RTSR1_TR10_Msk (0x1UL << EXTI_RTSR1_TR10_Pos) /*!< 0x00000400 */
9465#define EXTI_RTSR1_TR10 EXTI_RTSR1_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
9466#define EXTI_RTSR1_TR11_Pos (11U)
9467#define EXTI_RTSR1_TR11_Msk (0x1UL << EXTI_RTSR1_TR11_Pos) /*!< 0x00000800 */
9468#define EXTI_RTSR1_TR11 EXTI_RTSR1_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
9469#define EXTI_RTSR1_TR12_Pos (12U)
9470#define EXTI_RTSR1_TR12_Msk (0x1UL << EXTI_RTSR1_TR12_Pos) /*!< 0x00001000 */
9471#define EXTI_RTSR1_TR12 EXTI_RTSR1_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
9472#define EXTI_RTSR1_TR13_Pos (13U)
9473#define EXTI_RTSR1_TR13_Msk (0x1UL << EXTI_RTSR1_TR13_Pos) /*!< 0x00002000 */
9474#define EXTI_RTSR1_TR13 EXTI_RTSR1_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
9475#define EXTI_RTSR1_TR14_Pos (14U)
9476#define EXTI_RTSR1_TR14_Msk (0x1UL << EXTI_RTSR1_TR14_Pos) /*!< 0x00004000 */
9477#define EXTI_RTSR1_TR14 EXTI_RTSR1_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
9478#define EXTI_RTSR1_TR15_Pos (15U)
9479#define EXTI_RTSR1_TR15_Msk (0x1UL << EXTI_RTSR1_TR15_Pos) /*!< 0x00008000 */
9480#define EXTI_RTSR1_TR15 EXTI_RTSR1_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
9481#define EXTI_RTSR1_TR16_Pos (16U)
9482#define EXTI_RTSR1_TR16_Msk (0x1UL << EXTI_RTSR1_TR16_Pos) /*!< 0x00010000 */
9483#define EXTI_RTSR1_TR16 EXTI_RTSR1_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
9484#define EXTI_RTSR1_TR17_Pos (17U)
9485#define EXTI_RTSR1_TR17_Msk (0x1UL << EXTI_RTSR1_TR17_Pos) /*!< 0x00020000 */
9486#define EXTI_RTSR1_TR17 EXTI_RTSR1_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
9487#define EXTI_RTSR1_TR18_Pos (18U)
9488#define EXTI_RTSR1_TR18_Msk (0x1UL << EXTI_RTSR1_TR18_Pos) /*!< 0x00040000 */
9489#define EXTI_RTSR1_TR18 EXTI_RTSR1_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
9490#define EXTI_RTSR1_TR19_Pos (19U)
9491#define EXTI_RTSR1_TR19_Msk (0x1UL << EXTI_RTSR1_TR19_Pos) /*!< 0x00080000 */
9492#define EXTI_RTSR1_TR19 EXTI_RTSR1_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
9493#define EXTI_RTSR1_TR20_Pos (20U)
9494#define EXTI_RTSR1_TR20_Msk (0x1UL << EXTI_RTSR1_TR20_Pos) /*!< 0x00100000 */
9495#define EXTI_RTSR1_TR20 EXTI_RTSR1_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
9496#define EXTI_RTSR1_TR21_Pos (21U)
9497#define EXTI_RTSR1_TR21_Msk (0x1UL << EXTI_RTSR1_TR21_Pos) /*!< 0x00200000 */
9498#define EXTI_RTSR1_TR21 EXTI_RTSR1_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
9499
9500/****************** Bit definition for EXTI_FTSR1 register *******************/
9501#define EXTI_FTSR1_TR_Pos (0U)
9502#define EXTI_FTSR1_TR_Msk (0x3FFFFFUL << EXTI_FTSR1_TR_Pos) /*!< 0x003FFFFF */
9503#define EXTI_FTSR1_TR EXTI_FTSR1_TR_Msk /*!< Falling trigger event configuration bit */
9504#define EXTI_FTSR1_TR0_Pos (0U)
9505#define EXTI_FTSR1_TR0_Msk (0x1UL << EXTI_FTSR1_TR0_Pos) /*!< 0x00000001 */
9506#define EXTI_FTSR1_TR0 EXTI_FTSR1_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
9507#define EXTI_FTSR1_TR1_Pos (1U)
9508#define EXTI_FTSR1_TR1_Msk (0x1UL << EXTI_FTSR1_TR1_Pos) /*!< 0x00000002 */
9509#define EXTI_FTSR1_TR1 EXTI_FTSR1_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
9510#define EXTI_FTSR1_TR2_Pos (2U)
9511#define EXTI_FTSR1_TR2_Msk (0x1UL << EXTI_FTSR1_TR2_Pos) /*!< 0x00000004 */
9512#define EXTI_FTSR1_TR2 EXTI_FTSR1_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
9513#define EXTI_FTSR1_TR3_Pos (3U)
9514#define EXTI_FTSR1_TR3_Msk (0x1UL << EXTI_FTSR1_TR3_Pos) /*!< 0x00000008 */
9515#define EXTI_FTSR1_TR3 EXTI_FTSR1_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
9516#define EXTI_FTSR1_TR4_Pos (4U)
9517#define EXTI_FTSR1_TR4_Msk (0x1UL << EXTI_FTSR1_TR4_Pos) /*!< 0x00000010 */
9518#define EXTI_FTSR1_TR4 EXTI_FTSR1_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
9519#define EXTI_FTSR1_TR5_Pos (5U)
9520#define EXTI_FTSR1_TR5_Msk (0x1UL << EXTI_FTSR1_TR5_Pos) /*!< 0x00000020 */
9521#define EXTI_FTSR1_TR5 EXTI_FTSR1_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
9522#define EXTI_FTSR1_TR6_Pos (6U)
9523#define EXTI_FTSR1_TR6_Msk (0x1UL << EXTI_FTSR1_TR6_Pos) /*!< 0x00000040 */
9524#define EXTI_FTSR1_TR6 EXTI_FTSR1_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
9525#define EXTI_FTSR1_TR7_Pos (7U)
9526#define EXTI_FTSR1_TR7_Msk (0x1UL << EXTI_FTSR1_TR7_Pos) /*!< 0x00000080 */
9527#define EXTI_FTSR1_TR7 EXTI_FTSR1_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
9528#define EXTI_FTSR1_TR8_Pos (8U)
9529#define EXTI_FTSR1_TR8_Msk (0x1UL << EXTI_FTSR1_TR8_Pos) /*!< 0x00000100 */
9530#define EXTI_FTSR1_TR8 EXTI_FTSR1_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
9531#define EXTI_FTSR1_TR9_Pos (9U)
9532#define EXTI_FTSR1_TR9_Msk (0x1UL << EXTI_FTSR1_TR9_Pos) /*!< 0x00000200 */
9533#define EXTI_FTSR1_TR9 EXTI_FTSR1_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
9534#define EXTI_FTSR1_TR10_Pos (10U)
9535#define EXTI_FTSR1_TR10_Msk (0x1UL << EXTI_FTSR1_TR10_Pos) /*!< 0x00000400 */
9536#define EXTI_FTSR1_TR10 EXTI_FTSR1_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
9537#define EXTI_FTSR1_TR11_Pos (11U)
9538#define EXTI_FTSR1_TR11_Msk (0x1UL << EXTI_FTSR1_TR11_Pos) /*!< 0x00000800 */
9539#define EXTI_FTSR1_TR11 EXTI_FTSR1_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
9540#define EXTI_FTSR1_TR12_Pos (12U)
9541#define EXTI_FTSR1_TR12_Msk (0x1UL << EXTI_FTSR1_TR12_Pos) /*!< 0x00001000 */
9542#define EXTI_FTSR1_TR12 EXTI_FTSR1_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
9543#define EXTI_FTSR1_TR13_Pos (13U)
9544#define EXTI_FTSR1_TR13_Msk (0x1UL << EXTI_FTSR1_TR13_Pos) /*!< 0x00002000 */
9545#define EXTI_FTSR1_TR13 EXTI_FTSR1_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
9546#define EXTI_FTSR1_TR14_Pos (14U)
9547#define EXTI_FTSR1_TR14_Msk (0x1UL << EXTI_FTSR1_TR14_Pos) /*!< 0x00004000 */
9548#define EXTI_FTSR1_TR14 EXTI_FTSR1_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
9549#define EXTI_FTSR1_TR15_Pos (15U)
9550#define EXTI_FTSR1_TR15_Msk (0x1UL << EXTI_FTSR1_TR15_Pos) /*!< 0x00008000 */
9551#define EXTI_FTSR1_TR15 EXTI_FTSR1_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
9552#define EXTI_FTSR1_TR16_Pos (16U)
9553#define EXTI_FTSR1_TR16_Msk (0x1UL << EXTI_FTSR1_TR16_Pos) /*!< 0x00010000 */
9554#define EXTI_FTSR1_TR16 EXTI_FTSR1_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
9555#define EXTI_FTSR1_TR17_Pos (17U)
9556#define EXTI_FTSR1_TR17_Msk (0x1UL << EXTI_FTSR1_TR17_Pos) /*!< 0x00020000 */
9557#define EXTI_FTSR1_TR17 EXTI_FTSR1_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
9558#define EXTI_FTSR1_TR18_Pos (18U)
9559#define EXTI_FTSR1_TR18_Msk (0x1UL << EXTI_FTSR1_TR18_Pos) /*!< 0x00040000 */
9560#define EXTI_FTSR1_TR18 EXTI_FTSR1_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
9561#define EXTI_FTSR1_TR19_Pos (19U)
9562#define EXTI_FTSR1_TR19_Msk (0x1UL << EXTI_FTSR1_TR19_Pos) /*!< 0x00080000 */
9563#define EXTI_FTSR1_TR19 EXTI_FTSR1_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
9564#define EXTI_FTSR1_TR20_Pos (20U)
9565#define EXTI_FTSR1_TR20_Msk (0x1UL << EXTI_FTSR1_TR20_Pos) /*!< 0x00100000 */
9566#define EXTI_FTSR1_TR20 EXTI_FTSR1_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
9567#define EXTI_FTSR1_TR21_Pos (21U)
9568#define EXTI_FTSR1_TR21_Msk (0x1UL << EXTI_FTSR1_TR21_Pos) /*!< 0x00200000 */
9569#define EXTI_FTSR1_TR21 EXTI_FTSR1_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
9570
9571/****************** Bit definition for EXTI_SWIER1 register ******************/
9572#define EXTI_SWIER1_SWIER0_Pos (0U)
9573#define EXTI_SWIER1_SWIER0_Msk (0x1UL << EXTI_SWIER1_SWIER0_Pos) /*!< 0x00000001 */
9574#define EXTI_SWIER1_SWIER0 EXTI_SWIER1_SWIER0_Msk /*!< Software Interrupt on line 0 */
9575#define EXTI_SWIER1_SWIER1_Pos (1U)
9576#define EXTI_SWIER1_SWIER1_Msk (0x1UL << EXTI_SWIER1_SWIER1_Pos) /*!< 0x00000002 */
9577#define EXTI_SWIER1_SWIER1 EXTI_SWIER1_SWIER1_Msk /*!< Software Interrupt on line 1 */
9578#define EXTI_SWIER1_SWIER2_Pos (2U)
9579#define EXTI_SWIER1_SWIER2_Msk (0x1UL << EXTI_SWIER1_SWIER2_Pos) /*!< 0x00000004 */
9580#define EXTI_SWIER1_SWIER2 EXTI_SWIER1_SWIER2_Msk /*!< Software Interrupt on line 2 */
9581#define EXTI_SWIER1_SWIER3_Pos (3U)
9582#define EXTI_SWIER1_SWIER3_Msk (0x1UL << EXTI_SWIER1_SWIER3_Pos) /*!< 0x00000008 */
9583#define EXTI_SWIER1_SWIER3 EXTI_SWIER1_SWIER3_Msk /*!< Software Interrupt on line 3 */
9584#define EXTI_SWIER1_SWIER4_Pos (4U)
9585#define EXTI_SWIER1_SWIER4_Msk (0x1UL << EXTI_SWIER1_SWIER4_Pos) /*!< 0x00000010 */
9586#define EXTI_SWIER1_SWIER4 EXTI_SWIER1_SWIER4_Msk /*!< Software Interrupt on line 4 */
9587#define EXTI_SWIER1_SWIER5_Pos (5U)
9588#define EXTI_SWIER1_SWIER5_Msk (0x1UL << EXTI_SWIER1_SWIER5_Pos) /*!< 0x00000020 */
9589#define EXTI_SWIER1_SWIER5 EXTI_SWIER1_SWIER5_Msk /*!< Software Interrupt on line 5 */
9590#define EXTI_SWIER1_SWIER6_Pos (6U)
9591#define EXTI_SWIER1_SWIER6_Msk (0x1UL << EXTI_SWIER1_SWIER6_Pos) /*!< 0x00000040 */
9592#define EXTI_SWIER1_SWIER6 EXTI_SWIER1_SWIER6_Msk /*!< Software Interrupt on line 6 */
9593#define EXTI_SWIER1_SWIER7_Pos (7U)
9594#define EXTI_SWIER1_SWIER7_Msk (0x1UL << EXTI_SWIER1_SWIER7_Pos) /*!< 0x00000080 */
9595#define EXTI_SWIER1_SWIER7 EXTI_SWIER1_SWIER7_Msk /*!< Software Interrupt on line 7 */
9596#define EXTI_SWIER1_SWIER8_Pos (8U)
9597#define EXTI_SWIER1_SWIER8_Msk (0x1UL << EXTI_SWIER1_SWIER8_Pos) /*!< 0x00000100 */
9598#define EXTI_SWIER1_SWIER8 EXTI_SWIER1_SWIER8_Msk /*!< Software Interrupt on line 8 */
9599#define EXTI_SWIER1_SWIER9_Pos (9U)
9600#define EXTI_SWIER1_SWIER9_Msk (0x1UL << EXTI_SWIER1_SWIER9_Pos) /*!< 0x00000200 */
9601#define EXTI_SWIER1_SWIER9 EXTI_SWIER1_SWIER9_Msk /*!< Software Interrupt on line 9 */
9602#define EXTI_SWIER1_SWIER10_Pos (10U)
9603#define EXTI_SWIER1_SWIER10_Msk (0x1UL << EXTI_SWIER1_SWIER10_Pos) /*!< 0x00000400 */
9604#define EXTI_SWIER1_SWIER10 EXTI_SWIER1_SWIER10_Msk /*!< Software Interrupt on line 10 */
9605#define EXTI_SWIER1_SWIER11_Pos (11U)
9606#define EXTI_SWIER1_SWIER11_Msk (0x1UL << EXTI_SWIER1_SWIER11_Pos) /*!< 0x00000800 */
9607#define EXTI_SWIER1_SWIER11 EXTI_SWIER1_SWIER11_Msk /*!< Software Interrupt on line 11 */
9608#define EXTI_SWIER1_SWIER12_Pos (12U)
9609#define EXTI_SWIER1_SWIER12_Msk (0x1UL << EXTI_SWIER1_SWIER12_Pos) /*!< 0x00001000 */
9610#define EXTI_SWIER1_SWIER12 EXTI_SWIER1_SWIER12_Msk /*!< Software Interrupt on line 12 */
9611#define EXTI_SWIER1_SWIER13_Pos (13U)
9612#define EXTI_SWIER1_SWIER13_Msk (0x1UL << EXTI_SWIER1_SWIER13_Pos) /*!< 0x00002000 */
9613#define EXTI_SWIER1_SWIER13 EXTI_SWIER1_SWIER13_Msk /*!< Software Interrupt on line 13 */
9614#define EXTI_SWIER1_SWIER14_Pos (14U)
9615#define EXTI_SWIER1_SWIER14_Msk (0x1UL << EXTI_SWIER1_SWIER14_Pos) /*!< 0x00004000 */
9616#define EXTI_SWIER1_SWIER14 EXTI_SWIER1_SWIER14_Msk /*!< Software Interrupt on line 14 */
9617#define EXTI_SWIER1_SWIER15_Pos (15U)
9618#define EXTI_SWIER1_SWIER15_Msk (0x1UL << EXTI_SWIER1_SWIER15_Pos) /*!< 0x00008000 */
9619#define EXTI_SWIER1_SWIER15 EXTI_SWIER1_SWIER15_Msk /*!< Software Interrupt on line 15 */
9620#define EXTI_SWIER1_SWIER16_Pos (16U)
9621#define EXTI_SWIER1_SWIER16_Msk (0x1UL << EXTI_SWIER1_SWIER16_Pos) /*!< 0x00010000 */
9622#define EXTI_SWIER1_SWIER16 EXTI_SWIER1_SWIER16_Msk /*!< Software Interrupt on line 16 */
9623#define EXTI_SWIER1_SWIER17_Pos (17U)
9624#define EXTI_SWIER1_SWIER17_Msk (0x1UL << EXTI_SWIER1_SWIER17_Pos) /*!< 0x00020000 */
9625#define EXTI_SWIER1_SWIER17 EXTI_SWIER1_SWIER17_Msk /*!< Software Interrupt on line 17 */
9626#define EXTI_SWIER1_SWIER18_Pos (18U)
9627#define EXTI_SWIER1_SWIER18_Msk (0x1UL << EXTI_SWIER1_SWIER18_Pos) /*!< 0x00040000 */
9628#define EXTI_SWIER1_SWIER18 EXTI_SWIER1_SWIER18_Msk /*!< Software Interrupt on line 18 */
9629#define EXTI_SWIER1_SWIER19_Pos (19U)
9630#define EXTI_SWIER1_SWIER19_Msk (0x1UL << EXTI_SWIER1_SWIER19_Pos) /*!< 0x00080000 */
9631#define EXTI_SWIER1_SWIER19 EXTI_SWIER1_SWIER19_Msk /*!< Software Interrupt on line 19 */
9632#define EXTI_SWIER1_SWIER20_Pos (20U)
9633#define EXTI_SWIER1_SWIER20_Msk (0x1UL << EXTI_SWIER1_SWIER20_Pos) /*!< 0x00100000 */
9634#define EXTI_SWIER1_SWIER20 EXTI_SWIER1_SWIER20_Msk /*!< Software Interrupt on line 20 */
9635#define EXTI_SWIER1_SWIER21_Pos (21U)
9636#define EXTI_SWIER1_SWIER21_Msk (0x1UL << EXTI_SWIER1_SWIER21_Pos) /*!< 0x00200000 */
9637#define EXTI_SWIER1_SWIER21 EXTI_SWIER1_SWIER21_Msk /*!< Software Interrupt on line 21 */
9638
9639/****************** Bit definition for EXTI_D3PMR1 register ******************/
9640#define EXTI_D3PMR1_MR0_Pos (0U)
9641#define EXTI_D3PMR1_MR0_Msk (0x1UL << EXTI_D3PMR1_MR0_Pos) /*!< 0x00000001 */
9642#define EXTI_D3PMR1_MR0 EXTI_D3PMR1_MR0_Msk /*!< Pending Mask Event for line 0 */
9643#define EXTI_D3PMR1_MR1_Pos (1U)
9644#define EXTI_D3PMR1_MR1_Msk (0x1UL << EXTI_D3PMR1_MR1_Pos) /*!< 0x00000002 */
9645#define EXTI_D3PMR1_MR1 EXTI_D3PMR1_MR1_Msk /*!< Pending Mask Event for line 1 */
9646#define EXTI_D3PMR1_MR2_Pos (2U)
9647#define EXTI_D3PMR1_MR2_Msk (0x1UL << EXTI_D3PMR1_MR2_Pos) /*!< 0x00000004 */
9648#define EXTI_D3PMR1_MR2 EXTI_D3PMR1_MR2_Msk /*!< Pending Mask Event for line 2 */
9649#define EXTI_D3PMR1_MR3_Pos (3U)
9650#define EXTI_D3PMR1_MR3_Msk (0x1UL << EXTI_D3PMR1_MR3_Pos) /*!< 0x00000008 */
9651#define EXTI_D3PMR1_MR3 EXTI_D3PMR1_MR3_Msk /*!< Pending Mask Event for line 3 */
9652#define EXTI_D3PMR1_MR4_Pos (4U)
9653#define EXTI_D3PMR1_MR4_Msk (0x1UL << EXTI_D3PMR1_MR4_Pos) /*!< 0x00000010 */
9654#define EXTI_D3PMR1_MR4 EXTI_D3PMR1_MR4_Msk /*!< Pending Mask Event for line 4 */
9655#define EXTI_D3PMR1_MR5_Pos (5U)
9656#define EXTI_D3PMR1_MR5_Msk (0x1UL << EXTI_D3PMR1_MR5_Pos) /*!< 0x00000020 */
9657#define EXTI_D3PMR1_MR5 EXTI_D3PMR1_MR5_Msk /*!< Pending Mask Event for line 5 */
9658#define EXTI_D3PMR1_MR6_Pos (6U)
9659#define EXTI_D3PMR1_MR6_Msk (0x1UL << EXTI_D3PMR1_MR6_Pos) /*!< 0x00000040 */
9660#define EXTI_D3PMR1_MR6 EXTI_D3PMR1_MR6_Msk /*!< Pending Mask Event for line 6 */
9661#define EXTI_D3PMR1_MR7_Pos (7U)
9662#define EXTI_D3PMR1_MR7_Msk (0x1UL << EXTI_D3PMR1_MR7_Pos) /*!< 0x00000080 */
9663#define EXTI_D3PMR1_MR7 EXTI_D3PMR1_MR7_Msk /*!< Pending Mask Event for line 7 */
9664#define EXTI_D3PMR1_MR8_Pos (8U)
9665#define EXTI_D3PMR1_MR8_Msk (0x1UL << EXTI_D3PMR1_MR8_Pos) /*!< 0x00000100 */
9666#define EXTI_D3PMR1_MR8 EXTI_D3PMR1_MR8_Msk /*!< Pending Mask Event for line 8 */
9667#define EXTI_D3PMR1_MR9_Pos (9U)
9668#define EXTI_D3PMR1_MR9_Msk (0x1UL << EXTI_D3PMR1_MR9_Pos) /*!< 0x00000200 */
9669#define EXTI_D3PMR1_MR9 EXTI_D3PMR1_MR9_Msk /*!< Pending Mask Event for line 9 */
9670#define EXTI_D3PMR1_MR10_Pos (10U)
9671#define EXTI_D3PMR1_MR10_Msk (0x1UL << EXTI_D3PMR1_MR10_Pos) /*!< 0x00000400 */
9672#define EXTI_D3PMR1_MR10 EXTI_D3PMR1_MR10_Msk /*!< Pending Mask Event for line 10 */
9673#define EXTI_D3PMR1_MR11_Pos (11U)
9674#define EXTI_D3PMR1_MR11_Msk (0x1UL << EXTI_D3PMR1_MR11_Pos) /*!< 0x00000800 */
9675#define EXTI_D3PMR1_MR11 EXTI_D3PMR1_MR11_Msk /*!< Pending Mask Event for line 11 */
9676#define EXTI_D3PMR1_MR12_Pos (12U)
9677#define EXTI_D3PMR1_MR12_Msk (0x1UL << EXTI_D3PMR1_MR12_Pos) /*!< 0x00001000 */
9678#define EXTI_D3PMR1_MR12 EXTI_D3PMR1_MR12_Msk /*!< Pending Mask Event for line 12 */
9679#define EXTI_D3PMR1_MR13_Pos (13U)
9680#define EXTI_D3PMR1_MR13_Msk (0x1UL << EXTI_D3PMR1_MR13_Pos) /*!< 0x00002000 */
9681#define EXTI_D3PMR1_MR13 EXTI_D3PMR1_MR13_Msk /*!< Pending Mask Event for line 13 */
9682#define EXTI_D3PMR1_MR14_Pos (14U)
9683#define EXTI_D3PMR1_MR14_Msk (0x1UL << EXTI_D3PMR1_MR14_Pos) /*!< 0x00004000 */
9684#define EXTI_D3PMR1_MR14 EXTI_D3PMR1_MR14_Msk /*!< Pending Mask Event for line 14 */
9685#define EXTI_D3PMR1_MR15_Pos (15U)
9686#define EXTI_D3PMR1_MR15_Msk (0x1UL << EXTI_D3PMR1_MR15_Pos) /*!< 0x00008000 */
9687#define EXTI_D3PMR1_MR15 EXTI_D3PMR1_MR15_Msk /*!< Pending Mask Event for line 15 */
9688#define EXTI_D3PMR1_MR19_Pos (19U)
9689#define EXTI_D3PMR1_MR19_Msk (0x1UL << EXTI_D3PMR1_MR19_Pos) /*!< 0x00080000 */
9690#define EXTI_D3PMR1_MR19 EXTI_D3PMR1_MR19_Msk /*!< Pending Mask Event for line 19 */
9691#define EXTI_D3PMR1_MR20_Pos (20U)
9692#define EXTI_D3PMR1_MR20_Msk (0x1UL << EXTI_D3PMR1_MR20_Pos) /*!< 0x00100000 */
9693#define EXTI_D3PMR1_MR20 EXTI_D3PMR1_MR20_Msk /*!< Pending Mask Event for line 20 */
9694#define EXTI_D3PMR1_MR21_Pos (21U)
9695#define EXTI_D3PMR1_MR21_Msk (0x1UL << EXTI_D3PMR1_MR21_Pos) /*!< 0x00200000 */
9696#define EXTI_D3PMR1_MR21 EXTI_D3PMR1_MR21_Msk /*!< Pending Mask Event for line 21 */
9697#define EXTI_D3PMR1_MR25_Pos (24U)
9698#define EXTI_D3PMR1_MR25_Msk (0x1UL << EXTI_D3PMR1_MR25_Pos) /*!< 0x01000000 */
9699#define EXTI_D3PMR1_MR25 EXTI_D3PMR1_MR25_Msk /*!< Pending Mask Event for line 25 */
9700
9701/******************* Bit definition for EXTI_D3PCR1L register ****************/
9702#define EXTI_D3PCR1L_PCS0_Pos (0U)
9703#define EXTI_D3PCR1L_PCS0_Msk (0x3UL << EXTI_D3PCR1L_PCS0_Pos) /*!< 0x00000003 */
9704#define EXTI_D3PCR1L_PCS0 EXTI_D3PCR1L_PCS0_Msk /*!< D3 Pending request clear input signal selection on line 0 */
9705#define EXTI_D3PCR1L_PCS1_Pos (2U)
9706#define EXTI_D3PCR1L_PCS1_Msk (0x3UL << EXTI_D3PCR1L_PCS1_Pos) /*!< 0x000000C0 */
9707#define EXTI_D3PCR1L_PCS1 EXTI_D3PCR1L_PCS1_Msk /*!< D3 Pending request clear input signal selection on line 1 */
9708#define EXTI_D3PCR1L_PCS2_Pos (4U)
9709#define EXTI_D3PCR1L_PCS2_Msk (0x3UL << EXTI_D3PCR1L_PCS2_Pos) /*!< 0x00000030 */
9710#define EXTI_D3PCR1L_PCS2 EXTI_D3PCR1L_PCS2_Msk /*!< D3 Pending request clear input signal selection on line 2 */
9711#define EXTI_D3PCR1L_PCS3_Pos (6U)
9712#define EXTI_D3PCR1L_PCS3_Msk (0x3UL << EXTI_D3PCR1L_PCS3_Pos) /*!< 0x000000C0 */
9713#define EXTI_D3PCR1L_PCS3 EXTI_D3PCR1L_PCS3_Msk /*!< D3 Pending request clear input signal selection on line 3 */
9714#define EXTI_D3PCR1L_PCS4_Pos (8U)
9715#define EXTI_D3PCR1L_PCS4_Msk (0x3UL << EXTI_D3PCR1L_PCS4_Pos) /*!< 0x00000300 */
9716#define EXTI_D3PCR1L_PCS4 EXTI_D3PCR1L_PCS4_Msk /*!< D3 Pending request clear input signal selection on line 4 */
9717#define EXTI_D3PCR1L_PCS5_Pos (10U)
9718#define EXTI_D3PCR1L_PCS5_Msk (0x3UL << EXTI_D3PCR1L_PCS5_Pos) /*!< 0x00000C00 */
9719#define EXTI_D3PCR1L_PCS5 EXTI_D3PCR1L_PCS5_Msk /*!< D3 Pending request clear input signal selection on line 5 */
9720#define EXTI_D3PCR1L_PCS6_Pos (12U)
9721#define EXTI_D3PCR1L_PCS6_Msk (0x3UL << EXTI_D3PCR1L_PCS6_Pos) /*!< 0x00003000 */
9722#define EXTI_D3PCR1L_PCS6 EXTI_D3PCR1L_PCS6_Msk /*!< D3 Pending request clear input signal selection on line 6 */
9723#define EXTI_D3PCR1L_PCS7_Pos (14U)
9724#define EXTI_D3PCR1L_PCS7_Msk (0x3UL << EXTI_D3PCR1L_PCS7_Pos) /*!< 0x0000C000 */
9725#define EXTI_D3PCR1L_PCS7 EXTI_D3PCR1L_PCS7_Msk /*!< D3 Pending request clear input signal selection on line 7 */
9726#define EXTI_D3PCR1L_PCS8_Pos (16U)
9727#define EXTI_D3PCR1L_PCS8_Msk (0x3UL << EXTI_D3PCR1L_PCS8_Pos) /*!< 0x00030000 */
9728#define EXTI_D3PCR1L_PCS8 EXTI_D3PCR1L_PCS8_Msk /*!< D3 Pending request clear input signal selection on line 8 */
9729#define EXTI_D3PCR1L_PCS9_Pos (18U)
9730#define EXTI_D3PCR1L_PCS9_Msk (0x3UL << EXTI_D3PCR1L_PCS9_Pos) /*!< 0x000C0000 */
9731#define EXTI_D3PCR1L_PCS9 EXTI_D3PCR1L_PCS9_Msk /*!< D3 Pending request clear input signal selection on line 9 */
9732#define EXTI_D3PCR1L_PCS10_Pos (20U)
9733#define EXTI_D3PCR1L_PCS10_Msk (0x3UL << EXTI_D3PCR1L_PCS10_Pos) /*!< 0x00300000 */
9734#define EXTI_D3PCR1L_PCS10 EXTI_D3PCR1L_PCS10_Msk /*!< D3 Pending request clear input signal selection on line 10*/
9735#define EXTI_D3PCR1L_PCS11_Pos (22U)
9736#define EXTI_D3PCR1L_PCS11_Msk (0x3UL << EXTI_D3PCR1L_PCS11_Pos) /*!< 0x00C00000 */
9737#define EXTI_D3PCR1L_PCS11 EXTI_D3PCR1L_PCS11_Msk /*!< D3 Pending request clear input signal selection on line 11*/
9738#define EXTI_D3PCR1L_PCS12_Pos (24U)
9739#define EXTI_D3PCR1L_PCS12_Msk (0x3UL << EXTI_D3PCR1L_PCS12_Pos) /*!< 0x03000000 */
9740#define EXTI_D3PCR1L_PCS12 EXTI_D3PCR1L_PCS12_Msk /*!< D3 Pending request clear input signal selection on line 12*/
9741#define EXTI_D3PCR1L_PCS13_Pos (26U)
9742#define EXTI_D3PCR1L_PCS13_Msk (0x3UL << EXTI_D3PCR1L_PCS13_Pos) /*!< 0x0C000000 */
9743#define EXTI_D3PCR1L_PCS13 EXTI_D3PCR1L_PCS13_Msk /*!< D3 Pending request clear input signal selection on line 13*/
9744#define EXTI_D3PCR1L_PCS14_Pos (28U)
9745#define EXTI_D3PCR1L_PCS14_Msk (0x3UL << EXTI_D3PCR1L_PCS14_Pos) /*!< 0x30000000 */
9746#define EXTI_D3PCR1L_PCS14 EXTI_D3PCR1L_PCS14_Msk /*!< D3 Pending request clear input signal selection on line 14*/
9747#define EXTI_D3PCR1L_PCS15_Pos (30U)
9748#define EXTI_D3PCR1L_PCS15_Msk (0x3UL << EXTI_D3PCR1L_PCS15_Pos) /*!< 0xC0000000 */
9749#define EXTI_D3PCR1L_PCS15 EXTI_D3PCR1L_PCS15_Msk /*!< D3 Pending request clear input signal selection on line 15*/
9750
9751/******************* Bit definition for EXTI_D3PCR1H register ****************/
9752#define EXTI_D3PCR1H_PCS19_Pos (6U)
9753#define EXTI_D3PCR1H_PCS19_Msk (0x3UL << EXTI_D3PCR1H_PCS19_Pos) /*!< 0x000000C0 */
9754#define EXTI_D3PCR1H_PCS19 EXTI_D3PCR1H_PCS19_Msk /*!< D3 Pending request clear input signal selection on line 19 */
9755#define EXTI_D3PCR1H_PCS20_Pos (8U)
9756#define EXTI_D3PCR1H_PCS20_Msk (0x3UL << EXTI_D3PCR1H_PCS20_Pos) /*!< 0x00000300 */
9757#define EXTI_D3PCR1H_PCS20 EXTI_D3PCR1H_PCS20_Msk /*!< D3 Pending request clear input signal selection on line 20 */
9758#define EXTI_D3PCR1H_PCS21_Pos (10U)
9759#define EXTI_D3PCR1H_PCS21_Msk (0x3UL << EXTI_D3PCR1H_PCS21_Pos) /*!< 0x00000C00 */
9760#define EXTI_D3PCR1H_PCS21 EXTI_D3PCR1H_PCS21_Msk /*!< D3 Pending request clear input signal selection on line 21 */
9761#define EXTI_D3PCR1H_PCS25_Pos (18U)
9762#define EXTI_D3PCR1H_PCS25_Msk (0x3UL << EXTI_D3PCR1H_PCS25_Pos) /*!< 0x000C0000 */
9763#define EXTI_D3PCR1H_PCS25 EXTI_D3PCR1H_PCS25_Msk /*!< D3 Pending request clear input signal selection on line 25 */
9764
9765/****************** Bit definition for EXTI_RTSR2 register *******************/
9766#define EXTI_RTSR2_TR_Pos (17U)
9767#define EXTI_RTSR2_TR_Msk (0x5UL << EXTI_RTSR2_TR_Pos) /*!< 0x000A0000 */
9768#define EXTI_RTSR2_TR EXTI_RTSR2_TR_Msk /*!< Rising trigger event configuration bit */
9769#define EXTI_RTSR2_TR49_Pos (17U)
9770#define EXTI_RTSR2_TR49_Msk (0x1UL << EXTI_RTSR2_TR49_Pos) /*!< 0x00020000 */
9771#define EXTI_RTSR2_TR49 EXTI_RTSR2_TR49_Msk /*!< Rising trigger event configuration bit of line 49 */
9772#define EXTI_RTSR2_TR51_Pos (19U)
9773#define EXTI_RTSR2_TR51_Msk (0x1UL << EXTI_RTSR2_TR51_Pos) /*!< 0x00080000 */
9774#define EXTI_RTSR2_TR51 EXTI_RTSR2_TR51_Msk /*!< Rising trigger event configuration bit of line 51 */
9775
9776/****************** Bit definition for EXTI_FTSR2 register *******************/
9777#define EXTI_FTSR2_TR_Pos (17U)
9778#define EXTI_FTSR2_TR_Msk (0x5UL << EXTI_FTSR2_TR_Pos) /*!< 0x000A0000 */
9779#define EXTI_FTSR2_TR EXTI_FTSR2_TR_Msk /*!< Falling trigger event configuration bit */
9780#define EXTI_FTSR2_TR49_Pos (17U)
9781#define EXTI_FTSR2_TR49_Msk (0x1UL << EXTI_FTSR2_TR49_Pos) /*!< 0x00020000 */
9782#define EXTI_FTSR2_TR49 EXTI_FTSR2_TR49_Msk /*!< Falling trigger event configuration bit of line 49 */
9783#define EXTI_FTSR2_TR51_Pos (19U)
9784#define EXTI_FTSR2_TR51_Msk (0x1UL << EXTI_FTSR2_TR51_Pos) /*!< 0x00080000 */
9785#define EXTI_FTSR2_TR51 EXTI_FTSR2_TR51_Msk /*!< Falling trigger event configuration bit of line 51 */
9786
9787/****************** Bit definition for EXTI_SWIER2 register ******************/
9788#define EXTI_SWIER2_SWIER49_Pos (17U)
9789#define EXTI_SWIER2_SWIER49_Msk (0x1UL << EXTI_SWIER2_SWIER49_Pos) /*!< 0x00020000 */
9790#define EXTI_SWIER2_SWIER49 EXTI_SWIER2_SWIER49_Msk /*!< Software Interrupt on line 49 */
9791#define EXTI_SWIER2_SWIER51_Pos (19U)
9792#define EXTI_SWIER2_SWIER51_Msk (0x1UL << EXTI_SWIER2_SWIER51_Pos) /*!< 0x00080000 */
9793#define EXTI_SWIER2_SWIER51 EXTI_SWIER2_SWIER51_Msk /*!< Software Interrupt on line 51 */
9794
9795/****************** Bit definition for EXTI_D3PMR2 register ******************/
9796#define EXTI_D3PMR2_MR34_Pos (2U)
9797#define EXTI_D3PMR2_MR34_Msk (0x1UL << EXTI_D3PMR2_MR34_Pos) /*!< 0x00000004 */
9798#define EXTI_D3PMR2_MR34 EXTI_D3PMR2_MR34_Msk /*!< Pending Mask Event for line 34 */
9799#define EXTI_D3PMR2_MR35_Pos (3U)
9800#define EXTI_D3PMR2_MR35_Msk (0x1UL << EXTI_D3PMR2_MR35_Pos) /*!< 0x00000008 */
9801#define EXTI_D3PMR2_MR35 EXTI_D3PMR2_MR35_Msk /*!< Pending Mask Event for line 35 */
9802#define EXTI_D3PMR2_MR41_Pos (9U)
9803#define EXTI_D3PMR2_MR41_Msk (0x1UL << EXTI_D3PMR2_MR41_Pos) /*!< 0x00000200 */
9804#define EXTI_D3PMR2_MR41 EXTI_D3PMR2_MR41_Msk /*!< Pending Mask Event for line 41 */
9805#define EXTI_D3PMR2_MR48_Pos (16U)
9806#define EXTI_D3PMR2_MR48_Msk (0x1UL << EXTI_D3PMR2_MR48_Pos) /*!< 0x00010000 */
9807#define EXTI_D3PMR2_MR48 EXTI_D3PMR2_MR48_Msk /*!< Pending Mask Event for line 48 */
9808#define EXTI_D3PMR2_MR49_Pos (17U)
9809#define EXTI_D3PMR2_MR49_Msk (0x1UL << EXTI_D3PMR2_MR49_Pos) /*!< 0x00020000 */
9810#define EXTI_D3PMR2_MR49 EXTI_D3PMR2_MR49_Msk /*!< Pending Mask Event for line 49 */
9811#define EXTI_D3PMR2_MR50_Pos (18U)
9812#define EXTI_D3PMR2_MR50_Msk (0x1UL << EXTI_D3PMR2_MR50_Pos) /*!< 0x00040000 */
9813#define EXTI_D3PMR2_MR50 EXTI_D3PMR2_MR50_Msk /*!< Pending Mask Event for line 50 */
9814#define EXTI_D3PMR2_MR51_Pos (19U)
9815#define EXTI_D3PMR2_MR51_Msk (0x1UL << EXTI_D3PMR2_MR51_Pos) /*!< 0x00080000 */
9816#define EXTI_D3PMR2_MR51 EXTI_D3PMR2_MR51_Msk /*!< Pending Mask Event for line 51 */
9817#define EXTI_D3PMR2_MR52_Pos (20U)
9818#define EXTI_D3PMR2_MR52_Msk (0x1UL << EXTI_D3PMR2_MR52_Pos) /*!< 0x00100000 */
9819#define EXTI_D3PMR2_MR52 EXTI_D3PMR2_MR52_Msk /*!< Pending Mask Event for line 52 */
9820#define EXTI_D3PMR2_MR53_Pos (21U)
9821#define EXTI_D3PMR2_MR53_Msk (0x1UL << EXTI_D3PMR2_MR53_Pos) /*!< 0x00200000 */
9822#define EXTI_D3PMR2_MR53 EXTI_D3PMR2_MR53_Msk /*!< Pending Mask Event for line 53 */
9823/******************* Bit definition for EXTI_D3PCR2L register ****************/
9824#define EXTI_D3PCR2L_PCS34_Pos (4U)
9825#define EXTI_D3PCR2L_PCS34_Msk (0x3UL << EXTI_D3PCR2L_PCS34_Pos) /*!< 0x00000030 */
9826#define EXTI_D3PCR2L_PCS34 EXTI_D3PCR2L_PCS34_Msk /*!< D3 Pending request clear input signal selection on line 34 */
9827#define EXTI_D3PCR2L_PCS35_Pos (6U)
9828#define EXTI_D3PCR2L_PCS35_Msk (0x3UL << EXTI_D3PCR2L_PCS35_Pos) /*!< 0x000000C0 */
9829#define EXTI_D3PCR2L_PCS35 EXTI_D3PCR2L_PCS35_Msk /*!< D3 Pending request clear input signal selection on line 35 */
9830#define EXTI_D3PCR2L_PCS41_Pos (18U)
9831#define EXTI_D3PCR2L_PCS41_Msk (0x3UL << EXTI_D3PCR2L_PCS41_Pos) /*!< 0x000C0000 */
9832#define EXTI_D3PCR2L_PCS41 EXTI_D3PCR2L_PCS41_Msk /*!< D3 Pending request clear input signal selection on line 41 */
9833
9834
9835/******************* Bit definition for EXTI_D3PCR2H register ****************/
9836#define EXTI_D3PCR2H_PCS48_Pos (0U)
9837#define EXTI_D3PCR2H_PCS48_Msk (0x3UL << EXTI_D3PCR2H_PCS48_Pos) /*!< 0x00000003 */
9838#define EXTI_D3PCR2H_PCS48 EXTI_D3PCR2H_PCS48_Msk /*!< D3 Pending request clear input signal selection on line 48 */
9839#define EXTI_D3PCR2H_PCS49_Pos (2U)
9840#define EXTI_D3PCR2H_PCS49_Msk (0x3UL << EXTI_D3PCR2H_PCS49_Pos) /*!< 0x0000000C */
9841#define EXTI_D3PCR2H_PCS49 EXTI_D3PCR2H_PCS49_Msk /*!< D3 Pending request clear input signal selection on line 49 */
9842#define EXTI_D3PCR2H_PCS50_Pos (4U)
9843#define EXTI_D3PCR2H_PCS50_Msk (0x3UL << EXTI_D3PCR2H_PCS50_Pos) /*!< 0x00000030 */
9844#define EXTI_D3PCR2H_PCS50 EXTI_D3PCR2H_PCS50_Msk /*!< D3 Pending request clear input signal selection on line 50 */
9845#define EXTI_D3PCR2H_PCS51_Pos (6U)
9846#define EXTI_D3PCR2H_PCS51_Msk (0x3UL << EXTI_D3PCR2H_PCS51_Pos) /*!< 0x000000C0 */
9847#define EXTI_D3PCR2H_PCS51 EXTI_D3PCR2H_PCS51_Msk /*!< D3 Pending request clear input signal selection on line 51 */
9848#define EXTI_D3PCR2H_PCS52_Pos (8U)
9849#define EXTI_D3PCR2H_PCS52_Msk (0x3UL << EXTI_D3PCR2H_PCS52_Pos) /*!< 0x00000300 */
9850#define EXTI_D3PCR2H_PCS52 EXTI_D3PCR2H_PCS52_Msk /*!< D3 Pending request clear input signal selection on line 52 */
9851#define EXTI_D3PCR2H_PCS53_Pos (10U)
9852#define EXTI_D3PCR2H_PCS53_Msk (0x3UL << EXTI_D3PCR2H_PCS53_Pos) /*!< 0x00000C00 */
9853#define EXTI_D3PCR2H_PCS53 EXTI_D3PCR2H_PCS53_Msk /*!< D3 Pending request clear input signal selection on line 53 */
9854/****************** Bit definition for EXTI_RTSR3 register *******************/
9855#define EXTI_RTSR3_TR_Pos (18U)
9856#define EXTI_RTSR3_TR_Msk (0x1DUL << EXTI_RTSR3_TR_Pos) /*!< 0x00740000 */
9857#define EXTI_RTSR3_TR EXTI_RTSR3_TR_Msk /*!< Rising trigger event configuration bit */
9858#define EXTI_RTSR3_TR82_Pos (18U)
9859#define EXTI_RTSR3_TR82_Msk (0x1UL << EXTI_RTSR3_TR82_Pos) /*!< 0x00040000 */
9860#define EXTI_RTSR3_TR82 EXTI_RTSR3_TR82_Msk /*!< Rising trigger event configuration bit of line 82 */
9861#define EXTI_RTSR3_TR84_Pos (20U)
9862#define EXTI_RTSR3_TR84_Msk (0x1UL << EXTI_RTSR3_TR84_Pos) /*!< 0x00100000 */
9863#define EXTI_RTSR3_TR84 EXTI_RTSR3_TR84_Msk /*!< Rising trigger event configuration bit of line 84 */
9864#define EXTI_RTSR3_TR85_Pos (21U)
9865#define EXTI_RTSR3_TR85_Msk (0x1UL << EXTI_RTSR3_TR85_Pos) /*!< 0x00200000 */
9866#define EXTI_RTSR3_TR85 EXTI_RTSR3_TR85_Msk /*!< Rising trigger event configuration bit of line 85 */
9867#define EXTI_RTSR3_TR86_Pos (22U)
9868#define EXTI_RTSR3_TR86_Msk (0x1UL << EXTI_RTSR3_TR86_Pos) /*!< 0x00400000 */
9869#define EXTI_RTSR3_TR86 EXTI_RTSR3_TR86_Msk /*!< Rising trigger event configuration bit of line 86 */
9870
9871/****************** Bit definition for EXTI_FTSR3 register *******************/
9872#define EXTI_FTSR3_TR_Pos (18U)
9873#define EXTI_FTSR3_TR_Msk (0x1DUL << EXTI_FTSR3_TR_Pos) /*!< 0x00740000 */
9874#define EXTI_FTSR3_TR EXTI_FTSR3_TR_Msk /*!< Falling trigger event configuration bit */
9875#define EXTI_FTSR3_TR82_Pos (18U)
9876#define EXTI_FTSR3_TR82_Msk (0x1UL << EXTI_FTSR3_TR82_Pos) /*!< 0x00040000 */
9877#define EXTI_FTSR3_TR82 EXTI_FTSR3_TR82_Msk /*!< Falling trigger event configuration bit of line 82 */
9878#define EXTI_FTSR3_TR84_Pos (20U)
9879#define EXTI_FTSR3_TR84_Msk (0x1UL << EXTI_FTSR3_TR84_Pos) /*!< 0x00100000 */
9880#define EXTI_FTSR3_TR84 EXTI_FTSR3_TR84_Msk /*!< Falling trigger event configuration bit of line 84 */
9881#define EXTI_FTSR3_TR85_Pos (21U)
9882#define EXTI_FTSR3_TR85_Msk (0x1UL << EXTI_FTSR3_TR85_Pos) /*!< 0x00200000 */
9883#define EXTI_FTSR3_TR85 EXTI_FTSR3_TR85_Msk /*!< Falling trigger event configuration bit of line 85 */
9884#define EXTI_FTSR3_TR86_Pos (22U)
9885#define EXTI_FTSR3_TR86_Msk (0x1UL << EXTI_FTSR3_TR86_Pos) /*!< 0x00400000 */
9886#define EXTI_FTSR3_TR86 EXTI_FTSR3_TR86_Msk /*!< Falling trigger event configuration bit of line 86 */
9887
9888/****************** Bit definition for EXTI_SWIER3 register ******************/
9889#define EXTI_SWIER3_SWI_Pos (18U)
9890#define EXTI_SWIER3_SWI_Msk (0x1DUL << EXTI_SWIER3_SWI_Pos) /*!< 0x00740000 */
9891#define EXTI_SWIER3_SWI EXTI_SWIER3_SWI_Msk /*!< Software Interrupt event bit */
9892#define EXTI_SWIER3_SWIER82_Pos (18U)
9893#define EXTI_SWIER3_SWIER82_Msk (0x1UL << EXTI_SWIER3_SWIER82_Pos) /*!< 0x00040000 */
9894#define EXTI_SWIER3_SWIER82 EXTI_SWIER3_SWIER82_Msk /*!< Software Interrupt on line 82 */
9895#define EXTI_SWIER3_SWIER84_Pos (20U)
9896#define EXTI_SWIER3_SWIER84_Msk (0x1UL << EXTI_SWIER3_SWIER84_Pos) /*!< 0x00100000 */
9897#define EXTI_SWIER3_SWIER84 EXTI_SWIER3_SWIER84_Msk /*!< Software Interrupt on line 84 */
9898#define EXTI_SWIER3_SWIER85_Pos (21U)
9899#define EXTI_SWIER3_SWIER85_Msk (0x1UL << EXTI_SWIER3_SWIER85_Pos) /*!< 0x00200000 */
9900#define EXTI_SWIER3_SWIER85 EXTI_SWIER3_SWIER85_Msk /*!< Software Interrupt on line 85 */
9901#define EXTI_SWIER3_SWIER86_Pos (22U)
9902#define EXTI_SWIER3_SWIER86_Msk (0x1UL << EXTI_SWIER3_SWIER86_Pos) /*!< 0x00400000 */
9903#define EXTI_SWIER3_SWIER86 EXTI_SWIER3_SWIER86_Msk /*!< Software Interrupt on line 86 */
9904
9905/******************* Bit definition for EXTI_IMR1 register *******************/
9906#define EXTI_IMR1_IM_Pos (0U)
9907#define EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0xFFFFFFFF */
9908#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask */
9909#define EXTI_IMR1_IM0_Pos (0U)
9910#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
9911#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
9912#define EXTI_IMR1_IM1_Pos (1U)
9913#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
9914#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
9915#define EXTI_IMR1_IM2_Pos (2U)
9916#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
9917#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
9918#define EXTI_IMR1_IM3_Pos (3U)
9919#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
9920#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
9921#define EXTI_IMR1_IM4_Pos (4U)
9922#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
9923#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
9924#define EXTI_IMR1_IM5_Pos (5U)
9925#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
9926#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
9927#define EXTI_IMR1_IM6_Pos (6U)
9928#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
9929#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
9930#define EXTI_IMR1_IM7_Pos (7U)
9931#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
9932#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
9933#define EXTI_IMR1_IM8_Pos (8U)
9934#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
9935#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
9936#define EXTI_IMR1_IM9_Pos (9U)
9937#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
9938#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
9939#define EXTI_IMR1_IM10_Pos (10U)
9940#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
9941#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
9942#define EXTI_IMR1_IM11_Pos (11U)
9943#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
9944#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
9945#define EXTI_IMR1_IM12_Pos (12U)
9946#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
9947#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
9948#define EXTI_IMR1_IM13_Pos (13U)
9949#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
9950#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
9951#define EXTI_IMR1_IM14_Pos (14U)
9952#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
9953#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
9954#define EXTI_IMR1_IM15_Pos (15U)
9955#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
9956#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
9957#define EXTI_IMR1_IM16_Pos (16U)
9958#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
9959#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
9960#define EXTI_IMR1_IM17_Pos (17U)
9961#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
9962#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
9963#define EXTI_IMR1_IM18_Pos (18U)
9964#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
9965#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
9966#define EXTI_IMR1_IM19_Pos (19U)
9967#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
9968#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
9969#define EXTI_IMR1_IM20_Pos (20U)
9970#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
9971#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
9972#define EXTI_IMR1_IM21_Pos (21U)
9973#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
9974#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
9975#define EXTI_IMR1_IM22_Pos (22U)
9976#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
9977#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
9978#define EXTI_IMR1_IM23_Pos (23U)
9979#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
9980#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
9981#define EXTI_IMR1_IM24_Pos (24U)
9982#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
9983#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
9984#define EXTI_IMR1_IM25_Pos (25U)
9985#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
9986#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
9987#define EXTI_IMR1_IM26_Pos (26U)
9988#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
9989#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
9990#define EXTI_IMR1_IM27_Pos (27U)
9991#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
9992#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
9993#define EXTI_IMR1_IM28_Pos (28U)
9994#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
9995#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
9996#define EXTI_IMR1_IM29_Pos (29U)
9997#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
9998#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
9999#define EXTI_IMR1_IM30_Pos (30U)
10000#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
10001#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
10002#define EXTI_IMR1_IM31_Pos (31U)
10003#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
10004#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
10005
10006/******************* Bit definition for EXTI_EMR1 register *******************/
10007#define EXTI_EMR1_EM_Pos (0U)
10008#define EXTI_EMR1_EM_Msk (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos) /*!< 0xFFFFFFFF */
10009#define EXTI_EMR1_EM EXTI_EMR1_EM_Msk /*!< Event Mask */
10010#define EXTI_EMR1_EM0_Pos (0U)
10011#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
10012#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
10013#define EXTI_EMR1_EM1_Pos (1U)
10014#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
10015#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
10016#define EXTI_EMR1_EM2_Pos (2U)
10017#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
10018#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
10019#define EXTI_EMR1_EM3_Pos (3U)
10020#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
10021#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
10022#define EXTI_EMR1_EM4_Pos (4U)
10023#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
10024#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
10025#define EXTI_EMR1_EM5_Pos (5U)
10026#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
10027#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
10028#define EXTI_EMR1_EM6_Pos (6U)
10029#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
10030#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
10031#define EXTI_EMR1_EM7_Pos (7U)
10032#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
10033#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
10034#define EXTI_EMR1_EM8_Pos (8U)
10035#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
10036#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
10037#define EXTI_EMR1_EM9_Pos (9U)
10038#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
10039#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
10040#define EXTI_EMR1_EM10_Pos (10U)
10041#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
10042#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
10043#define EXTI_EMR1_EM11_Pos (11U)
10044#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
10045#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
10046#define EXTI_EMR1_EM12_Pos (12U)
10047#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
10048#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
10049#define EXTI_EMR1_EM13_Pos (13U)
10050#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
10051#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
10052#define EXTI_EMR1_EM14_Pos (14U)
10053#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
10054#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
10055#define EXTI_EMR1_EM15_Pos (15U)
10056#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
10057#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
10058#define EXTI_EMR1_EM16_Pos (16U)
10059#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
10060#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
10061#define EXTI_EMR1_EM17_Pos (17U)
10062#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
10063#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
10064#define EXTI_EMR1_EM18_Pos (18U)
10065#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
10066#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
10067#define EXTI_EMR1_EM20_Pos (20U)
10068#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
10069#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
10070#define EXTI_EMR1_EM21_Pos (21U)
10071#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
10072#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
10073#define EXTI_EMR1_EM22_Pos (22U)
10074#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
10075#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
10076#define EXTI_EMR1_EM23_Pos (23U)
10077#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
10078#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
10079#define EXTI_EMR1_EM24_Pos (24U)
10080#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
10081#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
10082#define EXTI_EMR1_EM25_Pos (25U)
10083#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
10084#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
10085#define EXTI_EMR1_EM26_Pos (26U)
10086#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
10087#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
10088#define EXTI_EMR1_EM27_Pos (27U)
10089#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
10090#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
10091#define EXTI_EMR1_EM28_Pos (28U)
10092#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
10093#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
10094#define EXTI_EMR1_EM29_Pos (29U)
10095#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
10096#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
10097#define EXTI_EMR1_EM30_Pos (30U)
10098#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
10099#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
10100#define EXTI_EMR1_EM31_Pos (31U)
10101#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
10102#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
10103
10104/******************* Bit definition for EXTI_PR1 register ********************/
10105#define EXTI_PR1_PR_Pos (0U)
10106#define EXTI_PR1_PR_Msk (0x3FFFFFUL << EXTI_PR1_PR_Pos) /*!< 0x003FFFFF */
10107#define EXTI_PR1_PR EXTI_PR1_PR_Msk /*!< Pending bit */
10108#define EXTI_PR1_PR0_Pos (0U)
10109#define EXTI_PR1_PR0_Msk (0x1UL << EXTI_PR1_PR0_Pos) /*!< 0x00000001 */
10110#define EXTI_PR1_PR0 EXTI_PR1_PR0_Msk /*!< Pending bit for line 0 */
10111#define EXTI_PR1_PR1_Pos (1U)
10112#define EXTI_PR1_PR1_Msk (0x1UL << EXTI_PR1_PR1_Pos) /*!< 0x00000002 */
10113#define EXTI_PR1_PR1 EXTI_PR1_PR1_Msk /*!< Pending bit for line 1 */
10114#define EXTI_PR1_PR2_Pos (2U)
10115#define EXTI_PR1_PR2_Msk (0x1UL << EXTI_PR1_PR2_Pos) /*!< 0x00000004 */
10116#define EXTI_PR1_PR2 EXTI_PR1_PR2_Msk /*!< Pending bit for line 2 */
10117#define EXTI_PR1_PR3_Pos (3U)
10118#define EXTI_PR1_PR3_Msk (0x1UL << EXTI_PR1_PR3_Pos) /*!< 0x00000008 */
10119#define EXTI_PR1_PR3 EXTI_PR1_PR3_Msk /*!< Pending bit for line 3 */
10120#define EXTI_PR1_PR4_Pos (4U)
10121#define EXTI_PR1_PR4_Msk (0x1UL << EXTI_PR1_PR4_Pos) /*!< 0x00000010 */
10122#define EXTI_PR1_PR4 EXTI_PR1_PR4_Msk /*!< Pending bit for line 4 */
10123#define EXTI_PR1_PR5_Pos (5U)
10124#define EXTI_PR1_PR5_Msk (0x1UL << EXTI_PR1_PR5_Pos) /*!< 0x00000020 */
10125#define EXTI_PR1_PR5 EXTI_PR1_PR5_Msk /*!< Pending bit for line 5 */
10126#define EXTI_PR1_PR6_Pos (6U)
10127#define EXTI_PR1_PR6_Msk (0x1UL << EXTI_PR1_PR6_Pos) /*!< 0x00000040 */
10128#define EXTI_PR1_PR6 EXTI_PR1_PR6_Msk /*!< Pending bit for line 6 */
10129#define EXTI_PR1_PR7_Pos (7U)
10130#define EXTI_PR1_PR7_Msk (0x1UL << EXTI_PR1_PR7_Pos) /*!< 0x00000080 */
10131#define EXTI_PR1_PR7 EXTI_PR1_PR7_Msk /*!< Pending bit for line 7 */
10132#define EXTI_PR1_PR8_Pos (8U)
10133#define EXTI_PR1_PR8_Msk (0x1UL << EXTI_PR1_PR8_Pos) /*!< 0x00000100 */
10134#define EXTI_PR1_PR8 EXTI_PR1_PR8_Msk /*!< Pending bit for line 8 */
10135#define EXTI_PR1_PR9_Pos (9U)
10136#define EXTI_PR1_PR9_Msk (0x1UL << EXTI_PR1_PR9_Pos) /*!< 0x00000200 */
10137#define EXTI_PR1_PR9 EXTI_PR1_PR9_Msk /*!< Pending bit for line 9 */
10138#define EXTI_PR1_PR10_Pos (10U)
10139#define EXTI_PR1_PR10_Msk (0x1UL << EXTI_PR1_PR10_Pos) /*!< 0x00000400 */
10140#define EXTI_PR1_PR10 EXTI_PR1_PR10_Msk /*!< Pending bit for line 10 */
10141#define EXTI_PR1_PR11_Pos (11U)
10142#define EXTI_PR1_PR11_Msk (0x1UL << EXTI_PR1_PR11_Pos) /*!< 0x00000800 */
10143#define EXTI_PR1_PR11 EXTI_PR1_PR11_Msk /*!< Pending bit for line 11 */
10144#define EXTI_PR1_PR12_Pos (12U)
10145#define EXTI_PR1_PR12_Msk (0x1UL << EXTI_PR1_PR12_Pos) /*!< 0x00001000 */
10146#define EXTI_PR1_PR12 EXTI_PR1_PR12_Msk /*!< Pending bit for line 12 */
10147#define EXTI_PR1_PR13_Pos (13U)
10148#define EXTI_PR1_PR13_Msk (0x1UL << EXTI_PR1_PR13_Pos) /*!< 0x00002000 */
10149#define EXTI_PR1_PR13 EXTI_PR1_PR13_Msk /*!< Pending bit for line 13 */
10150#define EXTI_PR1_PR14_Pos (14U)
10151#define EXTI_PR1_PR14_Msk (0x1UL << EXTI_PR1_PR14_Pos) /*!< 0x00004000 */
10152#define EXTI_PR1_PR14 EXTI_PR1_PR14_Msk /*!< Pending bit for line 14 */
10153#define EXTI_PR1_PR15_Pos (15U)
10154#define EXTI_PR1_PR15_Msk (0x1UL << EXTI_PR1_PR15_Pos) /*!< 0x00008000 */
10155#define EXTI_PR1_PR15 EXTI_PR1_PR15_Msk /*!< Pending bit for line 15 */
10156#define EXTI_PR1_PR16_Pos (16U)
10157#define EXTI_PR1_PR16_Msk (0x1UL << EXTI_PR1_PR16_Pos) /*!< 0x00010000 */
10158#define EXTI_PR1_PR16 EXTI_PR1_PR16_Msk /*!< Pending bit for line 16 */
10159#define EXTI_PR1_PR17_Pos (17U)
10160#define EXTI_PR1_PR17_Msk (0x1UL << EXTI_PR1_PR17_Pos) /*!< 0x00020000 */
10161#define EXTI_PR1_PR17 EXTI_PR1_PR17_Msk /*!< Pending bit for line 17 */
10162#define EXTI_PR1_PR18_Pos (18U)
10163#define EXTI_PR1_PR18_Msk (0x1UL << EXTI_PR1_PR18_Pos) /*!< 0x00040000 */
10164#define EXTI_PR1_PR18 EXTI_PR1_PR18_Msk /*!< Pending bit for line 18 */
10165#define EXTI_PR1_PR19_Pos (19U)
10166#define EXTI_PR1_PR19_Msk (0x1UL << EXTI_PR1_PR19_Pos) /*!< 0x00080000 */
10167#define EXTI_PR1_PR19 EXTI_PR1_PR19_Msk /*!< Pending bit for line 19 */
10168#define EXTI_PR1_PR20_Pos (20U)
10169#define EXTI_PR1_PR20_Msk (0x1UL << EXTI_PR1_PR20_Pos) /*!< 0x00100000 */
10170#define EXTI_PR1_PR20 EXTI_PR1_PR20_Msk /*!< Pending bit for line 20 */
10171#define EXTI_PR1_PR21_Pos (21U)
10172#define EXTI_PR1_PR21_Msk (0x1UL << EXTI_PR1_PR21_Pos) /*!< 0x00200000 */
10173#define EXTI_PR1_PR21 EXTI_PR1_PR21_Msk /*!< Pending bit for line 21 */
10174
10175/******************* Bit definition for EXTI_IMR2 register *******************/
10176#define EXTI_IMR2_IM_Pos (0U)
10177#define EXTI_IMR2_IM_Msk (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos) /*!< 0xFFFFDFFF */
10178#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask */
10179#define EXTI_IMR2_IM32_Pos (0U)
10180#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
10181#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
10182#define EXTI_IMR2_IM33_Pos (1U)
10183#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
10184#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
10185#define EXTI_IMR2_IM34_Pos (2U)
10186#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
10187#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
10188#define EXTI_IMR2_IM35_Pos (3U)
10189#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
10190#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
10191#define EXTI_IMR2_IM36_Pos (4U)
10192#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
10193#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
10194#define EXTI_IMR2_IM37_Pos (5U)
10195#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
10196#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
10197#define EXTI_IMR2_IM38_Pos (6U)
10198#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
10199#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
10200#define EXTI_IMR2_IM39_Pos (7U)
10201#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
10202#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
10203#define EXTI_IMR2_IM40_Pos (8U)
10204#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
10205#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
10206#define EXTI_IMR2_IM41_Pos (9U)
10207#define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */
10208#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< Interrupt Mask on line 41 */
10209#define EXTI_IMR2_IM42_Pos (10U)
10210#define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */
10211#define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< Interrupt Mask on line 42 */
10212#define EXTI_IMR2_IM43_Pos (11U)
10213#define EXTI_IMR2_IM43_Msk (0x1UL << EXTI_IMR2_IM43_Pos) /*!< 0x00000800 */
10214#define EXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk /*!< Interrupt Mask on line 43 */
10215#define EXTI_IMR2_IM44_Pos (12U)
10216#define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */
10217#define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< Interrupt Mask on line 44 */
10218#define EXTI_IMR2_IM46_Pos (14U)
10219#define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */
10220#define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< Interrupt Mask on line 46 */
10221#define EXTI_IMR2_IM47_Pos (15U)
10222#define EXTI_IMR2_IM47_Msk (0x1UL << EXTI_IMR2_IM47_Pos) /*!< 0x00008000 */
10223#define EXTI_IMR2_IM47 EXTI_IMR2_IM47_Msk /*!< Interrupt Mask on line 47 */
10224#define EXTI_IMR2_IM48_Pos (16U)
10225#define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos) /*!< 0x00010000 */
10226#define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk /*!< Interrupt Mask on line 48 */
10227#define EXTI_IMR2_IM49_Pos (17U)
10228#define EXTI_IMR2_IM49_Msk (0x1UL << EXTI_IMR2_IM49_Pos) /*!< 0x00020000 */
10229#define EXTI_IMR2_IM49 EXTI_IMR2_IM49_Msk /*!< Interrupt Mask on line 49 */
10230#define EXTI_IMR2_IM50_Pos (18U)
10231#define EXTI_IMR2_IM50_Msk (0x1UL << EXTI_IMR2_IM50_Pos) /*!< 0x00040000 */
10232#define EXTI_IMR2_IM50 EXTI_IMR2_IM50_Msk /*!< Interrupt Mask on line 50 */
10233#define EXTI_IMR2_IM51_Pos (19U)
10234#define EXTI_IMR2_IM51_Msk (0x1UL << EXTI_IMR2_IM51_Pos) /*!< 0x00080000 */
10235#define EXTI_IMR2_IM51 EXTI_IMR2_IM51_Msk /*!< Interrupt Mask on line 51 */
10236#define EXTI_IMR2_IM52_Pos (20U)
10237#define EXTI_IMR2_IM52_Msk (0x1UL << EXTI_IMR2_IM52_Pos) /*!< 0x00100000 */
10238#define EXTI_IMR2_IM52 EXTI_IMR2_IM52_Msk /*!< Interrupt Mask on line 52 */
10239#define EXTI_IMR2_IM53_Pos (21U)
10240#define EXTI_IMR2_IM53_Msk (0x1UL << EXTI_IMR2_IM53_Pos) /*!< 0x00200000 */
10241#define EXTI_IMR2_IM53 EXTI_IMR2_IM53_Msk /*!< Interrupt Mask on line 53 */
10242#define EXTI_IMR2_IM54_Pos (22U)
10243#define EXTI_IMR2_IM54_Msk (0x1UL << EXTI_IMR2_IM54_Pos) /*!< 0x00400000 */
10244#define EXTI_IMR2_IM54 EXTI_IMR2_IM54_Msk /*!< Interrupt Mask on line 54 */
10245#define EXTI_IMR2_IM55_Pos (23U)
10246#define EXTI_IMR2_IM55_Msk (0x1UL << EXTI_IMR2_IM55_Pos) /*!< 0x00800000 */
10247#define EXTI_IMR2_IM55 EXTI_IMR2_IM55_Msk /*!< Interrupt Mask on line 55 */
10248#define EXTI_IMR2_IM56_Pos (24U)
10249#define EXTI_IMR2_IM56_Msk (0x1UL << EXTI_IMR2_IM56_Pos) /*!< 0x01000000 */
10250#define EXTI_IMR2_IM56 EXTI_IMR2_IM56_Msk /*!< Interrupt Mask on line 56 */
10251#define EXTI_IMR2_IM57_Pos (25U)
10252#define EXTI_IMR2_IM57_Msk (0x1UL << EXTI_IMR2_IM57_Pos) /*!< 0x02000000 */
10253#define EXTI_IMR2_IM57 EXTI_IMR2_IM57_Msk /*!< Interrupt Mask on line 57 */
10254#define EXTI_IMR2_IM58_Pos (26U)
10255#define EXTI_IMR2_IM58_Msk (0x1UL << EXTI_IMR2_IM58_Pos) /*!< 0x04000000 */
10256#define EXTI_IMR2_IM58 EXTI_IMR2_IM58_Msk /*!< Interrupt Mask on line 58 */
10257#define EXTI_IMR2_IM59_Pos (27U)
10258#define EXTI_IMR2_IM59_Msk (0x1UL << EXTI_IMR2_IM59_Pos) /*!< 0x08000000 */
10259#define EXTI_IMR2_IM59 EXTI_IMR2_IM59_Msk /*!< Interrupt Mask on line 59 */
10260#define EXTI_IMR2_IM60_Pos (28U)
10261#define EXTI_IMR2_IM60_Msk (0x1UL << EXTI_IMR2_IM60_Pos) /*!< 0x10000000 */
10262#define EXTI_IMR2_IM60 EXTI_IMR2_IM60_Msk /*!< Interrupt Mask on line 60 */
10263#define EXTI_IMR2_IM61_Pos (29U)
10264#define EXTI_IMR2_IM61_Msk (0x1UL << EXTI_IMR2_IM61_Pos) /*!< 0x20000000 */
10265#define EXTI_IMR2_IM61 EXTI_IMR2_IM61_Msk /*!< Interrupt Mask on line 61 */
10266#define EXTI_IMR2_IM62_Pos (30U)
10267#define EXTI_IMR2_IM62_Msk (0x1UL << EXTI_IMR2_IM62_Pos) /*!< 0x40000000 */
10268#define EXTI_IMR2_IM62 EXTI_IMR2_IM62_Msk /*!< Interrupt Mask on line 62 */
10269#define EXTI_IMR2_IM63_Pos (31U)
10270#define EXTI_IMR2_IM63_Msk (0x1UL << EXTI_IMR2_IM63_Pos) /*!< 0x80000000 */
10271#define EXTI_IMR2_IM63 EXTI_IMR2_IM63_Msk /*!< Interrupt Mask on line 63 */
10272
10273/******************* Bit definition for EXTI_EMR2 register *******************/
10274#define EXTI_EMR2_EM_Pos (0U)
10275#define EXTI_EMR2_EM_Msk (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos) /*!< 0xFFFFDFFF */
10276#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Event Mask */
10277#define EXTI_EMR2_EM32_Pos (0U)
10278#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
10279#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32*/
10280#define EXTI_EMR2_EM33_Pos (1U)
10281#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
10282#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33*/
10283#define EXTI_EMR2_EM34_Pos (2U)
10284#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
10285#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34*/
10286#define EXTI_EMR2_EM35_Pos (3U)
10287#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
10288#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35*/
10289#define EXTI_EMR2_EM36_Pos (4U)
10290#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
10291#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36*/
10292#define EXTI_EMR2_EM37_Pos (5U)
10293#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
10294#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37*/
10295#define EXTI_EMR2_EM38_Pos (6U)
10296#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
10297#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38*/
10298#define EXTI_EMR2_EM39_Pos (7U)
10299#define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
10300#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39*/
10301#define EXTI_EMR2_EM40_Pos (8U)
10302#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
10303#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40*/
10304#define EXTI_EMR2_EM41_Pos (9U)
10305#define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */
10306#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< Event Mask on line 41*/
10307#define EXTI_EMR2_EM42_Pos (10U)
10308#define EXTI_EMR2_EM42_Msk (0x1UL << EXTI_EMR2_EM42_Pos) /*!< 0x00000400 */
10309#define EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk /*!< Event Mask on line 42 */
10310#define EXTI_EMR2_EM43_Pos (11U)
10311#define EXTI_EMR2_EM43_Msk (0x1UL << EXTI_EMR2_EM43_Pos) /*!< 0x00000800 */
10312#define EXTI_EMR2_EM43 EXTI_EMR2_EM43_Msk /*!< Event Mask on line 43 */
10313#define EXTI_EMR2_EM44_Pos (12U)
10314#define EXTI_EMR2_EM44_Msk (0x1UL << EXTI_EMR2_EM44_Pos) /*!< 0x00001000 */
10315#define EXTI_EMR2_EM44 EXTI_EMR2_EM44_Msk /*!< Event Mask on line 44 */
10316#define EXTI_EMR2_EM46_Pos (14U)
10317#define EXTI_EMR2_EM46_Msk (0x1UL << EXTI_EMR2_EM46_Pos) /*!< 0x00004000 */
10318#define EXTI_EMR2_EM46 EXTI_EMR2_EM46_Msk /*!< Event Mask on line 46 */
10319#define EXTI_EMR2_EM47_Pos (15U)
10320#define EXTI_EMR2_EM47_Msk (0x1UL << EXTI_EMR2_EM47_Pos) /*!< 0x00008000 */
10321#define EXTI_EMR2_EM47 EXTI_EMR2_EM47_Msk /*!< Event Mask on line 47 */
10322#define EXTI_EMR2_EM48_Pos (16U)
10323#define EXTI_EMR2_EM48_Msk (0x1UL << EXTI_EMR2_EM48_Pos) /*!< 0x00010000 */
10324#define EXTI_EMR2_EM48 EXTI_EMR2_EM48_Msk /*!< Event Mask on line 48 */
10325#define EXTI_EMR2_EM49_Pos (17U)
10326#define EXTI_EMR2_EM49_Msk (0x1UL << EXTI_EMR2_EM49_Pos) /*!< 0x00020000 */
10327#define EXTI_EMR2_EM49 EXTI_EMR2_EM49_Msk /*!< Event Mask on line 49 */
10328#define EXTI_EMR2_EM50_Pos (18U)
10329#define EXTI_EMR2_EM50_Msk (0x1UL << EXTI_EMR2_EM50_Pos) /*!< 0x00040000 */
10330#define EXTI_EMR2_EM50 EXTI_EMR2_EM50_Msk /*!< Event Mask on line 50 */
10331#define EXTI_EMR2_EM51_Pos (19U)
10332#define EXTI_EMR2_EM51_Msk (0x1UL << EXTI_EMR2_EM51_Pos) /*!< 0x00080000 */
10333#define EXTI_EMR2_EM51 EXTI_EMR2_EM51_Msk /*!< Event Mask on line 51 */
10334#define EXTI_EMR2_EM52_Pos (20U)
10335#define EXTI_EMR2_EM52_Msk (0x1UL << EXTI_EMR2_EM52_Pos) /*!< 0x00100000 */
10336#define EXTI_EMR2_EM52 EXTI_EMR2_EM52_Msk /*!< Event Mask on line 52 */
10337#define EXTI_EMR2_EM53_Pos (21U)
10338#define EXTI_EMR2_EM53_Msk (0x1UL << EXTI_EMR2_EM53_Pos) /*!< 0x00200000 */
10339#define EXTI_EMR2_EM53 EXTI_EMR2_EM53_Msk /*!< Event Mask on line 53 */
10340#define EXTI_EMR2_EM54_Pos (22U)
10341#define EXTI_EMR2_EM54_Msk (0x1UL << EXTI_EMR2_EM54_Pos) /*!< 0x00400000 */
10342#define EXTI_EMR2_EM54 EXTI_EMR2_EM54_Msk /*!< Event Mask on line 54 */
10343#define EXTI_EMR2_EM55_Pos (23U)
10344#define EXTI_EMR2_EM55_Msk (0x1UL << EXTI_EMR2_EM55_Pos) /*!< 0x00800000 */
10345#define EXTI_EMR2_EM55 EXTI_EMR2_EM55_Msk /*!< Event Mask on line 55 */
10346#define EXTI_EMR2_EM56_Pos (24U)
10347#define EXTI_EMR2_EM56_Msk (0x1UL << EXTI_EMR2_EM56_Pos) /*!< 0x01000000 */
10348#define EXTI_EMR2_EM56 EXTI_EMR2_EM56_Msk /*!< Event Mask on line 56 */
10349#define EXTI_EMR2_EM57_Pos (25U)
10350#define EXTI_EMR2_EM57_Msk (0x1UL << EXTI_EMR2_EM57_Pos) /*!< 0x02000000 */
10351#define EXTI_EMR2_EM57 EXTI_EMR2_EM57_Msk /*!< Event Mask on line 57 */
10352#define EXTI_EMR2_EM58_Pos (26U)
10353#define EXTI_EMR2_EM58_Msk (0x1UL << EXTI_EMR2_EM58_Pos) /*!< 0x04000000 */
10354#define EXTI_EMR2_EM58 EXTI_EMR2_EM58_Msk /*!< Event Mask on line 58 */
10355#define EXTI_EMR2_EM59_Pos (27U)
10356#define EXTI_EMR2_EM59_Msk (0x1UL << EXTI_EMR2_EM59_Pos) /*!< 0x08000000 */
10357#define EXTI_EMR2_EM59 EXTI_EMR2_EM59_Msk /*!< Event Mask on line 59 */
10358#define EXTI_EMR2_EM60_Pos (28U)
10359#define EXTI_EMR2_EM60_Msk (0x1UL << EXTI_EMR2_EM60_Pos) /*!< 0x10000000 */
10360#define EXTI_EMR2_EM60 EXTI_EMR2_EM60_Msk /*!< Event Mask on line 60 */
10361#define EXTI_EMR2_EM61_Pos (29U)
10362#define EXTI_EMR2_EM61_Msk (0x1UL << EXTI_EMR2_EM61_Pos) /*!< 0x20000000 */
10363#define EXTI_EMR2_EM61 EXTI_EMR2_EM61_Msk /*!< Event Mask on line 61 */
10364#define EXTI_EMR2_EM62_Pos (30U)
10365#define EXTI_EMR2_EM62_Msk (0x1UL << EXTI_EMR2_EM62_Pos) /*!< 0x40000000 */
10366#define EXTI_EMR2_EM62 EXTI_EMR2_EM62_Msk /*!< Event Mask on line 62 */
10367#define EXTI_EMR2_EM63_Pos (31U)
10368#define EXTI_EMR2_EM63_Msk (0x1UL << EXTI_EMR2_EM63_Pos) /*!< 0x80000000 */
10369#define EXTI_EMR2_EM63 EXTI_EMR2_EM63_Msk /*!< Event Mask on line 63 */
10370
10371/******************* Bit definition for EXTI_PR2 register ********************/
10372#define EXTI_PR2_PR_Pos (17U)
10373#define EXTI_PR2_PR_Msk (0x5UL << EXTI_PR2_PR_Pos) /*!< 0x000A0000 */
10374#define EXTI_PR2_PR EXTI_PR2_PR_Msk /*!< Pending bit */
10375#define EXTI_PR2_PR49_Pos (17U)
10376#define EXTI_PR2_PR49_Msk (0x1UL << EXTI_PR2_PR49_Pos) /*!< 0x00020000 */
10377#define EXTI_PR2_PR49 EXTI_PR2_PR49_Msk /*!< Pending bit for line 49 */
10378#define EXTI_PR2_PR51_Pos (19U)
10379#define EXTI_PR2_PR51_Msk (0x1UL << EXTI_PR2_PR51_Pos) /*!< 0x00080000 */
10380#define EXTI_PR2_PR51 EXTI_PR2_PR51_Msk /*!< Pending bit for line 51 */
10381
10382/******************* Bit definition for EXTI_IMR3 register *******************/
10383#define EXTI_IMR3_IM_Pos (0U)
10384#define EXTI_IMR3_IM_Msk (0x00F5FFFFUL << EXTI_IMR3_IM_Pos) /*!< 0x00F5FFFF */
10385#define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */
10386#define EXTI_IMR3_IM64_Pos (0U)
10387#define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */
10388#define EXTI_IMR3_IM64 EXTI_IMR3_IM64_Msk /*!< Interrupt Mask on line 64 */
10389#define EXTI_IMR3_IM65_Pos (1U)
10390#define EXTI_IMR3_IM65_Msk (0x1UL << EXTI_IMR3_IM65_Pos) /*!< 0x00000002 */
10391#define EXTI_IMR3_IM65 EXTI_IMR3_IM65_Msk /*!< Interrupt Mask on line 65 */
10392#define EXTI_IMR3_IM66_Pos (2U)
10393#define EXTI_IMR3_IM66_Msk (0x1UL << EXTI_IMR3_IM66_Pos) /*!< 0x00000004 */
10394#define EXTI_IMR3_IM66 EXTI_IMR3_IM66_Msk /*!< Interrupt Mask on line 66 */
10395#define EXTI_IMR3_IM67_Pos (3U)
10396#define EXTI_IMR3_IM67_Msk (0x1UL << EXTI_IMR3_IM67_Pos) /*!< 0x00000008 */
10397#define EXTI_IMR3_IM67 EXTI_IMR3_IM67_Msk /*!< Interrupt Mask on line 67 */
10398#define EXTI_IMR3_IM68_Pos (4U)
10399#define EXTI_IMR3_IM68_Msk (0x1UL << EXTI_IMR3_IM68_Pos) /*!< 0x00000010 */
10400#define EXTI_IMR3_IM68 EXTI_IMR3_IM68_Msk /*!< Interrupt Mask on line 68 */
10401#define EXTI_IMR3_IM69_Pos (5U)
10402#define EXTI_IMR3_IM69_Msk (0x1UL << EXTI_IMR3_IM69_Pos) /*!< 0x00000020 */
10403#define EXTI_IMR3_IM69 EXTI_IMR3_IM69_Msk /*!< Interrupt Mask on line 69 */
10404#define EXTI_IMR3_IM70_Pos (6U)
10405#define EXTI_IMR3_IM70_Msk (0x1UL << EXTI_IMR3_IM70_Pos) /*!< 0x00000040 */
10406#define EXTI_IMR3_IM70 EXTI_IMR3_IM70_Msk /*!< Interrupt Mask on line 70 */
10407#define EXTI_IMR3_IM71_Pos (7U)
10408#define EXTI_IMR3_IM71_Msk (0x1UL << EXTI_IMR3_IM71_Pos) /*!< 0x00000080 */
10409#define EXTI_IMR3_IM71 EXTI_IMR3_IM71_Msk /*!< Interrupt Mask on line 71 */
10410#define EXTI_IMR3_IM72_Pos (8U)
10411#define EXTI_IMR3_IM72_Msk (0x1UL << EXTI_IMR3_IM72_Pos) /*!< 0x00000100 */
10412#define EXTI_IMR3_IM72 EXTI_IMR3_IM72_Msk /*!< Interrupt Mask on line 72 */
10413#define EXTI_IMR3_IM73_Pos (9U)
10414#define EXTI_IMR3_IM73_Msk (0x1UL << EXTI_IMR3_IM73_Pos) /*!< 0x00000200 */
10415#define EXTI_IMR3_IM73 EXTI_IMR3_IM73_Msk /*!< Interrupt Mask on line 73 */
10416#define EXTI_IMR3_IM74_Pos (10U)
10417#define EXTI_IMR3_IM74_Msk (0x1UL << EXTI_IMR3_IM74_Pos) /*!< 0x00000400 */
10418#define EXTI_IMR3_IM74 EXTI_IMR3_IM74_Msk /*!< Interrupt Mask on line 74 */
10419#define EXTI_IMR3_IM75_Pos (11U)
10420#define EXTI_IMR3_IM75_Msk (0x1UL << EXTI_IMR3_IM75_Pos) /*!< 0x00000800 */
10421#define EXTI_IMR3_IM75 EXTI_IMR3_IM75_Msk /*!< Interrupt Mask on line 75 */
10422#define EXTI_IMR3_IM76_Pos (12U)
10423#define EXTI_IMR3_IM76_Msk (0x1UL << EXTI_IMR3_IM76_Pos) /*!< 0x00001000 */
10424#define EXTI_IMR3_IM76 EXTI_IMR3_IM76_Msk /*!< Interrupt Mask on line 76 */
10425#define EXTI_IMR3_IM77_Pos (13U)
10426#define EXTI_IMR3_IM77_Msk (0x1UL << EXTI_IMR3_IM77_Pos) /*!< 0x00002000 */
10427#define EXTI_IMR3_IM77 EXTI_IMR3_IM77_Msk /*!< Interrupt Mask on line 77 */
10428#define EXTI_IMR3_IM78_Pos (14U)
10429#define EXTI_IMR3_IM78_Msk (0x1UL << EXTI_IMR3_IM78_Pos) /*!< 0x00004000 */
10430#define EXTI_IMR3_IM78 EXTI_IMR3_IM78_Msk /*!< Interrupt Mask on line 78 */
10431#define EXTI_IMR3_IM79_Pos (15U)
10432#define EXTI_IMR3_IM79_Msk (0x1UL << EXTI_IMR3_IM79_Pos) /*!< 0x00008000 */
10433#define EXTI_IMR3_IM79 EXTI_IMR3_IM79_Msk /*!< Interrupt Mask on line 79 */
10434#define EXTI_IMR3_IM80_Pos (16U)
10435#define EXTI_IMR3_IM80_Msk (0x1UL << EXTI_IMR3_IM80_Pos) /*!< 0x00010000 */
10436#define EXTI_IMR3_IM80 EXTI_IMR3_IM80_Msk /*!< Interrupt Mask on line 80 */
10437#define EXTI_IMR3_IM82_Pos (18U)
10438#define EXTI_IMR3_IM82_Msk (0x1UL << EXTI_IMR3_IM82_Pos) /*!< 0x00040000 */
10439#define EXTI_IMR3_IM82 EXTI_IMR3_IM82_Msk /*!< Interrupt Mask on line 82 */
10440#define EXTI_IMR3_IM84_Pos (20U)
10441#define EXTI_IMR3_IM84_Msk (0x1UL << EXTI_IMR3_IM84_Pos) /*!< 0x00100000 */
10442#define EXTI_IMR3_IM84 EXTI_IMR3_IM84_Msk /*!< Interrupt Mask on line 84 */
10443#define EXTI_IMR3_IM85_Pos (21U)
10444#define EXTI_IMR3_IM85_Msk (0x1UL << EXTI_IMR3_IM85_Pos) /*!< 0x00200000 */
10445#define EXTI_IMR3_IM85 EXTI_IMR3_IM85_Msk /*!< Interrupt Mask on line 85 */
10446#define EXTI_IMR3_IM86_Pos (22U)
10447#define EXTI_IMR3_IM86_Msk (0x1UL << EXTI_IMR3_IM86_Pos) /*!< 0x00400000 */
10448#define EXTI_IMR3_IM86 EXTI_IMR3_IM86_Msk /*!< Interrupt Mask on line 86 */
10449#define EXTI_IMR3_IM87_Pos (23U)
10450#define EXTI_IMR3_IM87_Msk (0x1UL << EXTI_IMR3_IM87_Pos) /*!< 0x00800000 */
10451#define EXTI_IMR3_IM87 EXTI_IMR3_IM87_Msk /*!< Interrupt Mask on line 87 */
10452
10453
10454/******************* Bit definition for EXTI_EMR3 register *******************/
10455#define EXTI_EMR3_EM_Pos (0U)
10456#define EXTI_EMR3_EM_Msk (0x00F5FFFFUL << EXTI_EMR3_EM_Pos) /*!< 0x00F5FFFF */
10457#define EXTI_EMR3_EM EXTI_EMR3_EM_Msk /*!< Event Mask */
10458#define EXTI_EMR3_EM64_Pos (0U)
10459#define EXTI_EMR3_EM64_Msk (0x1UL << EXTI_EMR3_EM64_Pos) /*!< 0x00000001 */
10460#define EXTI_EMR3_EM64 EXTI_EMR3_EM64_Msk /*!< Event Mask on line 64*/
10461#define EXTI_EMR3_EM65_Pos (1U)
10462#define EXTI_EMR3_EM65_Msk (0x1UL << EXTI_EMR3_EM65_Pos) /*!< 0x00000002 */
10463#define EXTI_EMR3_EM65 EXTI_EMR3_EM65_Msk /*!< Event Mask on line 65*/
10464#define EXTI_EMR3_EM66_Pos (2U)
10465#define EXTI_EMR3_EM66_Msk (0x1UL << EXTI_EMR3_EM66_Pos) /*!< 0x00000004 */
10466#define EXTI_EMR3_EM66 EXTI_EMR3_EM66_Msk /*!< Event Mask on line 66*/
10467#define EXTI_EMR3_EM67_Pos (3U)
10468#define EXTI_EMR3_EM67_Msk (0x1UL << EXTI_EMR3_EM67_Pos) /*!< 0x00000008 */
10469#define EXTI_EMR3_EM67 EXTI_EMR3_EM67_Msk /*!< Event Mask on line 67*/
10470#define EXTI_EMR3_EM68_Pos (4U)
10471#define EXTI_EMR3_EM68_Msk (0x1UL << EXTI_EMR3_EM68_Pos) /*!< 0x00000010 */
10472#define EXTI_EMR3_EM68 EXTI_EMR3_EM68_Msk /*!< Event Mask on line 68*/
10473#define EXTI_EMR3_EM69_Pos (5U)
10474#define EXTI_EMR3_EM69_Msk (0x1UL << EXTI_EMR3_EM69_Pos) /*!< 0x00000020 */
10475#define EXTI_EMR3_EM69 EXTI_EMR3_EM69_Msk /*!< Event Mask on line 69*/
10476#define EXTI_EMR3_EM70_Pos (6U)
10477#define EXTI_EMR3_EM70_Msk (0x1UL << EXTI_EMR3_EM70_Pos) /*!< 0x00000040 */
10478#define EXTI_EMR3_EM70 EXTI_EMR3_EM70_Msk /*!< Event Mask on line 70*/
10479#define EXTI_EMR3_EM71_Pos (7U)
10480#define EXTI_EMR3_EM71_Msk (0x1UL << EXTI_EMR3_EM71_Pos) /*!< 0x00000080 */
10481#define EXTI_EMR3_EM71 EXTI_EMR3_EM71_Msk /*!< Event Mask on line 71*/
10482#define EXTI_EMR3_EM72_Pos (8U)
10483#define EXTI_EMR3_EM72_Msk (0x1UL << EXTI_EMR3_EM72_Pos) /*!< 0x00000100 */
10484#define EXTI_EMR3_EM72 EXTI_EMR3_EM72_Msk /*!< Event Mask on line 72*/
10485#define EXTI_EMR3_EM73_Pos (9U)
10486#define EXTI_EMR3_EM73_Msk (0x1UL << EXTI_EMR3_EM73_Pos) /*!< 0x00000200 */
10487#define EXTI_EMR3_EM73 EXTI_EMR3_EM73_Msk /*!< Event Mask on line 73*/
10488#define EXTI_EMR3_EM74_Pos (10U)
10489#define EXTI_EMR3_EM74_Msk (0x1UL << EXTI_EMR3_EM74_Pos) /*!< 0x00000400 */
10490#define EXTI_EMR3_EM74 EXTI_EMR3_EM74_Msk /*!< Event Mask on line 74 */
10491#define EXTI_EMR3_EM75_Pos (11U)
10492#define EXTI_EMR3_EM75_Msk (0x1UL << EXTI_EMR3_EM75_Pos) /*!< 0x00000800 */
10493#define EXTI_EMR3_EM75 EXTI_EMR3_EM75_Msk /*!< Event Mask on line 75 */
10494#define EXTI_EMR3_EM76_Pos (12U)
10495#define EXTI_EMR3_EM76_Msk (0x1UL << EXTI_EMR3_EM76_Pos) /*!< 0x00001000 */
10496#define EXTI_EMR3_EM76 EXTI_EMR3_EM76_Msk /*!< Event Mask on line 76 */
10497#define EXTI_EMR3_EM77_Pos (13U)
10498#define EXTI_EMR3_EM77_Msk (0x1UL << EXTI_EMR3_EM77_Pos) /*!< 0x00002000 */
10499#define EXTI_EMR3_EM77 EXTI_EMR3_EM77_Msk /*!< Event Mask on line 77 */
10500#define EXTI_EMR3_EM78_Pos (14U)
10501#define EXTI_EMR3_EM78_Msk (0x1UL << EXTI_EMR3_EM78_Pos) /*!< 0x00004000 */
10502#define EXTI_EMR3_EM78 EXTI_EMR3_EM78_Msk /*!< Event Mask on line 78 */
10503#define EXTI_EMR3_EM79_Pos (15U)
10504#define EXTI_EMR3_EM79_Msk (0x1UL << EXTI_EMR3_EM79_Pos) /*!< 0x00008000 */
10505#define EXTI_EMR3_EM79 EXTI_EMR3_EM79_Msk /*!< Event Mask on line 79 */
10506#define EXTI_EMR3_EM80_Pos (16U)
10507#define EXTI_EMR3_EM80_Msk (0x1UL << EXTI_EMR3_EM80_Pos) /*!< 0x00010000 */
10508#define EXTI_EMR3_EM80 EXTI_EMR3_EM80_Msk /*!< Event Mask on line 80 */
10509#define EXTI_EMR3_EM81_Pos (17U)
10510#define EXTI_EMR3_EM81_Msk (0x1UL << EXTI_EMR3_EM81_Pos) /*!< 0x00020000 */
10511#define EXTI_EMR3_EM81 EXTI_EMR3_EM81_Msk /*!< Event Mask on line 81 */
10512#define EXTI_EMR3_EM82_Pos (18U)
10513#define EXTI_EMR3_EM82_Msk (0x1UL << EXTI_EMR3_EM82_Pos) /*!< 0x00040000 */
10514#define EXTI_EMR3_EM82 EXTI_EMR3_EM82_Msk /*!< Event Mask on line 82 */
10515#define EXTI_EMR3_EM84_Pos (20U)
10516#define EXTI_EMR3_EM84_Msk (0x1UL << EXTI_EMR3_EM84_Pos) /*!< 0x00100000 */
10517#define EXTI_EMR3_EM84 EXTI_EMR3_EM84_Msk /*!< Event Mask on line 84 */
10518#define EXTI_EMR3_EM85_Pos (21U)
10519#define EXTI_EMR3_EM85_Msk (0x1UL << EXTI_EMR3_EM85_Pos) /*!< 0x00200000 */
10520#define EXTI_EMR3_EM85 EXTI_EMR3_EM85_Msk /*!< Event Mask on line 85 */
10521#define EXTI_EMR3_EM86_Pos (22U)
10522#define EXTI_EMR3_EM86_Msk (0x1UL << EXTI_EMR3_EM86_Pos) /*!< 0x00400000 */
10523#define EXTI_EMR3_EM86 EXTI_EMR3_EM86_Msk /*!< Event Mask on line 86 */
10524#define EXTI_EMR3_EM87_Pos (23U)
10525#define EXTI_EMR3_EM87_Msk (0x1UL << EXTI_EMR3_EM87_Pos) /*!< 0x00800000 */
10526#define EXTI_EMR3_EM87 EXTI_EMR3_EM87_Msk /*!< Event Mask on line 87 */
10527
10528/******************* Bit definition for EXTI_PR3 register ********************/
10529#define EXTI_PR3_PR_Pos (18U)
10530#define EXTI_PR3_PR_Msk (0x1DUL << EXTI_PR3_PR_Pos) /*!< 0x00740000 */
10531#define EXTI_PR3_PR EXTI_PR3_PR_Msk /*!< Pending bit */
10532#define EXTI_PR3_PR82_Pos (18U)
10533#define EXTI_PR3_PR82_Msk (0x1UL << EXTI_PR3_PR82_Pos) /*!< 0x00040000 */
10534#define EXTI_PR3_PR82 EXTI_PR3_PR82_Msk /*!< Pending bit for line 82 */
10535#define EXTI_PR3_PR84_Pos (20U)
10536#define EXTI_PR3_PR84_Msk (0x1UL << EXTI_PR3_PR84_Pos) /*!< 0x00100000 */
10537#define EXTI_PR3_PR84 EXTI_PR3_PR84_Msk /*!< Pending bit for line 84 */
10538#define EXTI_PR3_PR85_Pos (21U)
10539#define EXTI_PR3_PR85_Msk (0x1UL << EXTI_PR3_PR85_Pos) /*!< 0x00200000 */
10540#define EXTI_PR3_PR85 EXTI_PR3_PR85_Msk /*!< Pending bit for line 85 */
10541#define EXTI_PR3_PR86_Pos (22U)
10542#define EXTI_PR3_PR86_Msk (0x1UL << EXTI_PR3_PR86_Pos) /*!< 0x00400000 */
10543#define EXTI_PR3_PR86 EXTI_PR3_PR86_Msk /*!< Pending bit for line 86 */
10544/******************************************************************************/
10545/* */
10546/* FLASH */
10547/* */
10548/******************************************************************************/
10549/*
10550* @brief FLASH Global Defines
10551*/
10552#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
10553#define FLASH_SIZE 0x200000UL /* 2 MB */
10554#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
10555#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
10556#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
10557#define FLASH_NB_32BITWORD_IN_FLASHWORD 8U /* 256 bits */
10558#define DUAL_BANK /* Dual-bank Flash */
10559
10560/******************* Bits definition for FLASH_ACR register **********************/
10561#define FLASH_ACR_LATENCY_Pos (0U)
10562#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
10563#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
10564#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
10565#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
10566#define FLASH_ACR_LATENCY_2WS (0x00000002UL)
10567#define FLASH_ACR_LATENCY_3WS (0x00000003UL)
10568#define FLASH_ACR_LATENCY_4WS (0x00000004UL)
10569#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
10570#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
10571#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
10572#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
10573#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
10574#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
10575#define FLASH_ACR_LATENCY_11WS (0x0000000BUL)
10576#define FLASH_ACR_LATENCY_12WS (0x0000000CUL)
10577#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
10578#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
10579#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
10580#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
10581#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
10582#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
10583#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
10584#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
10585
10586/******************* Bits definition for FLASH_CR register ***********************/
10587#define FLASH_CR_LOCK_Pos (0U)
10588#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
10589#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */
10590#define FLASH_CR_PG_Pos (1U)
10591#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */
10592#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Internal buffer control bit */
10593#define FLASH_CR_SER_Pos (2U)
10594#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */
10595#define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */
10596#define FLASH_CR_BER_Pos (3U)
10597#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */
10598#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */
10599#define FLASH_CR_PSIZE_Pos (4U)
10600#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000030 */
10601#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk /*!< Program size */
10602#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000010 */
10603#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000020 */
10604#define FLASH_CR_FW_Pos (6U)
10605#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000040 */
10606#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */
10607#define FLASH_CR_START_Pos (7U)
10608#define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000080 */
10609#define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */
10610#define FLASH_CR_SNB_Pos (8U)
10611#define FLASH_CR_SNB_Msk (0x7UL << FLASH_CR_SNB_Pos) /*!< 0x00000700 */
10612#define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */
10613#define FLASH_CR_SNB_0 (0x1UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */
10614#define FLASH_CR_SNB_1 (0x2UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */
10615#define FLASH_CR_SNB_2 (0x4UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */
10616#define FLASH_CR_CRC_EN_Pos (15U)
10617#define FLASH_CR_CRC_EN_Msk (0x1UL << FLASH_CR_CRC_EN_Pos) /*!< 0x00008000 */
10618#define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk /*!< CRC control bit */
10619#define FLASH_CR_EOPIE_Pos (16U)
10620#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */
10621#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-program interrupt control bit */
10622#define FLASH_CR_WRPERRIE_Pos (17U)
10623#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */
10624#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */
10625#define FLASH_CR_PGSERRIE_Pos (18U)
10626#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */
10627#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */
10628#define FLASH_CR_STRBERRIE_Pos (19U)
10629#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */
10630#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */
10631#define FLASH_CR_INCERRIE_Pos (21U)
10632#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00200000 */
10633#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */
10634#define FLASH_CR_OPERRIE_Pos (22U)
10635#define FLASH_CR_OPERRIE_Msk (0x1UL << FLASH_CR_OPERRIE_Pos) /*!< 0x00400000 */
10636#define FLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk /*!< Write/erase error interrupt enable bit */
10637#define FLASH_CR_RDPERRIE_Pos (23U)
10638#define FLASH_CR_RDPERRIE_Msk (0x1UL << FLASH_CR_RDPERRIE_Pos) /*!< 0x00800000 */
10639#define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk /*!< Read protection error interrupt enable bit */
10640#define FLASH_CR_RDSERRIE_Pos (24U)
10641#define FLASH_CR_RDSERRIE_Msk (0x1UL << FLASH_CR_RDSERRIE_Pos) /*!< 0x01000000 */
10642#define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk /*!< Secure error interrupt enable bit */
10643#define FLASH_CR_SNECCERRIE_Pos (25U)
10644#define FLASH_CR_SNECCERRIE_Msk (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */
10645#define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk /*!< ECC single correction error interrupt enable bit */
10646#define FLASH_CR_DBECCERRIE_Pos (26U)
10647#define FLASH_CR_DBECCERRIE_Msk (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */
10648#define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk /*!< ECC double detection error interrupt enable bit */
10649#define FLASH_CR_CRCENDIE_Pos (27U)
10650#define FLASH_CR_CRCENDIE_Msk (0x1UL << FLASH_CR_CRCENDIE_Pos) /*!< 0x08000000 */
10651#define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk /*!< CRC end of calculation interrupt enable bit */
10652#define FLASH_CR_CRCRDERRIE_Pos (28U)
10653#define FLASH_CR_CRCRDERRIE_Msk (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */
10654#define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk /*!< CRC read error interrupt enable bit */
10655
10656/******************* Bits definition for FLASH_SR register ***********************/
10657#define FLASH_SR_BSY_Pos (0U)
10658#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
10659#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */
10660#define FLASH_SR_WBNE_Pos (1U)
10661#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */
10662#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */
10663#define FLASH_SR_QW_Pos (2U)
10664#define FLASH_SR_QW_Msk (0x1UL << FLASH_SR_QW_Pos) /*!< 0x00000004 */
10665#define FLASH_SR_QW FLASH_SR_QW_Msk /*!< Wait queue flag */
10666#define FLASH_SR_CRC_BUSY_Pos (3U)
10667#define FLASH_SR_CRC_BUSY_Msk (0x1UL << FLASH_SR_CRC_BUSY_Pos) /*!< 0x00000008 */
10668#define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk /*!< CRC busy flag */
10669#define FLASH_SR_EOP_Pos (16U)
10670#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */
10671#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */
10672#define FLASH_SR_WRPERR_Pos (17U)
10673#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */
10674#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */
10675#define FLASH_SR_PGSERR_Pos (18U)
10676#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */
10677#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */
10678#define FLASH_SR_STRBERR_Pos (19U)
10679#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */
10680#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */
10681#define FLASH_SR_INCERR_Pos (21U)
10682#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00200000 */
10683#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */
10684#define FLASH_SR_OPERR_Pos (22U)
10685#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00400000 */
10686#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk /*!< Write/erase error flag */
10687#define FLASH_SR_RDPERR_Pos (23U)
10688#define FLASH_SR_RDPERR_Msk (0x1UL << FLASH_SR_RDPERR_Pos) /*!< 0x00800000 */
10689#define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk /*!< Read protection error flag */
10690#define FLASH_SR_RDSERR_Pos (24U)
10691#define FLASH_SR_RDSERR_Msk (0x1UL << FLASH_SR_RDSERR_Pos) /*!< 0x01000000 */
10692#define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk /*!< Secure error flag */
10693#define FLASH_SR_SNECCERR_Pos (25U)
10694#define FLASH_SR_SNECCERR_Msk (0x1UL << FLASH_SR_SNECCERR_Pos) /*!< 0x02000000 */
10695#define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk /*!< Single correction error flag */
10696#define FLASH_SR_DBECCERR_Pos (26U)
10697#define FLASH_SR_DBECCERR_Msk (0x1UL << FLASH_SR_DBECCERR_Pos) /*!< 0x04000000 */
10698#define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk /*!< ECC double detection error flag */
10699#define FLASH_SR_CRCEND_Pos (27U)
10700#define FLASH_SR_CRCEND_Msk (0x1UL << FLASH_SR_CRCEND_Pos) /*!< 0x08000000 */
10701#define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk /*!< CRC end of calculation flag */
10702#define FLASH_SR_CRCRDERR_Pos (28U)
10703#define FLASH_SR_CRCRDERR_Msk (0x1UL << FLASH_SR_CRCRDERR_Pos) /*!< 0x10000000 */
10704#define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk /*!< CRC read error flag */
10705
10706/******************* Bits definition for FLASH_CCR register *******************/
10707#define FLASH_CCR_CLR_EOP_Pos (16U)
10708#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */
10709#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */
10710#define FLASH_CCR_CLR_WRPERR_Pos (17U)
10711#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */
10712#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */
10713#define FLASH_CCR_CLR_PGSERR_Pos (18U)
10714#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */
10715#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */
10716#define FLASH_CCR_CLR_STRBERR_Pos (19U)
10717#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */
10718#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */
10719#define FLASH_CCR_CLR_INCERR_Pos (21U)
10720#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */
10721#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */
10722#define FLASH_CCR_CLR_OPERR_Pos (22U)
10723#define FLASH_CCR_CLR_OPERR_Msk (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */
10724#define FLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk /*!< OPERR flag clear bit */
10725#define FLASH_CCR_CLR_RDPERR_Pos (23U)
10726#define FLASH_CCR_CLR_RDPERR_Msk (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */
10727#define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk /*!< RDPERR flag clear bit */
10728#define FLASH_CCR_CLR_RDSERR_Pos (24U)
10729#define FLASH_CCR_CLR_RDSERR_Msk (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */
10730#define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk /*!< RDSERR flag clear bit */
10731#define FLASH_CCR_CLR_SNECCERR_Pos (25U)
10732#define FLASH_CCR_CLR_SNECCERR_Msk (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */
10733#define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk /*!< SNECCERR flag clear bit */
10734#define FLASH_CCR_CLR_DBECCERR_Pos (26U)
10735#define FLASH_CCR_CLR_DBECCERR_Msk (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */
10736#define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk /*!< DBECCERR flag clear bit */
10737#define FLASH_CCR_CLR_CRCEND_Pos (27U)
10738#define FLASH_CCR_CLR_CRCEND_Msk (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */
10739#define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk /*!< CRCEND flag clear bit */
10740#define FLASH_CCR_CLR_CRCRDERR_Pos (28U)
10741#define FLASH_CCR_CLR_CRCRDERR_Msk (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */
10742#define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk /*!< CRCRDERR flag clear bit */
10743
10744/******************* Bits definition for FLASH_OPTCR register *******************/
10745#define FLASH_OPTCR_OPTLOCK_Pos (0U)
10746#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
10747#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */
10748#define FLASH_OPTCR_OPTSTART_Pos (1U)
10749#define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */
10750#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */
10751#define FLASH_OPTCR_MER_Pos (4U)
10752#define FLASH_OPTCR_MER_Msk (0x1UL << FLASH_OPTCR_MER_Pos) /*!< 0x00000010 */
10753#define FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk /*!< Mass erase request */
10754#define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U)
10755#define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */
10756#define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */
10757#define FLASH_OPTCR_SWAP_BANK_Pos (31U)
10758#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */
10759#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */
10760
10761/******************* Bits definition for FLASH_OPTSR register ***************/
10762#define FLASH_OPTSR_OPT_BUSY_Pos (0U)
10763#define FLASH_OPTSR_OPT_BUSY_Msk (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */
10764#define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk /*!< Option byte change ongoing flag */
10765#define FLASH_OPTSR_BOR_LEV_Pos (2U)
10766#define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */
10767#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option status bit */
10768#define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */
10769#define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */
10770#define FLASH_OPTSR_IWDG1_SW_Pos (4U)
10771#define FLASH_OPTSR_IWDG1_SW_Msk (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */
10772#define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk /*!< IWDG1 control mode option status bit */
10773#define FLASH_OPTSR_NRST_STOP_D1_Pos (6U)
10774#define FLASH_OPTSR_NRST_STOP_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */
10775#define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk /*!< D1 domain DStop entry reset option status bit */
10776#define FLASH_OPTSR_NRST_STBY_D1_Pos (7U)
10777#define FLASH_OPTSR_NRST_STBY_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */
10778#define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk /*!< D1 domain DStandby entry reset option status bit */
10779#define FLASH_OPTSR_RDP_Pos (8U)
10780#define FLASH_OPTSR_RDP_Msk (0xFFUL << FLASH_OPTSR_RDP_Pos) /*!< 0x0000FF00 */
10781#define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk /*!< Readout protection level option status byte */
10782#define FLASH_OPTSR_FZ_IWDG_STOP_Pos (17U)
10783#define FLASH_OPTSR_FZ_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */
10784#define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk /*!< IWDG Stop mode freeze option status bit */
10785#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos (18U)
10786#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */
10787#define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk /*!< IWDG Standby mode freeze option status bit */
10788#define FLASH_OPTSR_ST_RAM_SIZE_Pos (19U)
10789#define FLASH_OPTSR_ST_RAM_SIZE_Msk (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */
10790#define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk /*!< ST RAM size option status */
10791#define FLASH_OPTSR_ST_RAM_SIZE_0 (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */
10792#define FLASH_OPTSR_ST_RAM_SIZE_1 (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */
10793#define FLASH_OPTSR_SECURITY_Pos (21U)
10794#define FLASH_OPTSR_SECURITY_Msk (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */
10795#define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk /*!< Security enable option status bit */
10796#define FLASH_OPTSR_IO_HSLV_Pos (29U)
10797#define FLASH_OPTSR_IO_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */
10798#define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk /*!< I/O high-speed at low-voltage status bit */
10799#define FLASH_OPTSR_OPTCHANGEERR_Pos (30U)
10800#define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
10801#define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk /*!< Option byte change error flag */
10802#define FLASH_OPTSR_SWAP_BANK_OPT_Pos (31U)
10803#define FLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */
10804#define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk /*!< Bank swapping option status bit */
10805
10806/******************* Bits definition for FLASH_OPTCCR register *******************/
10807#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U)
10808#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
10809#define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk /*!< OPTCHANGEERR reset bit */
10810
10811/******************* Bits definition for FLASH_PRAR register *********************/
10812#define FLASH_PRAR_PROT_AREA_START_Pos (0U)
10813#define FLASH_PRAR_PROT_AREA_START_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */
10814#define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk /*!< PCROP area start status bits */
10815#define FLASH_PRAR_PROT_AREA_END_Pos (16U)
10816#define FLASH_PRAR_PROT_AREA_END_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */
10817#define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk /*!< PCROP area end status bits */
10818#define FLASH_PRAR_DMEP_Pos (31U)
10819#define FLASH_PRAR_DMEP_Msk (0x1UL << FLASH_PRAR_DMEP_Pos) /*!< 0x80000000 */
10820#define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk /*!< PCROP protected erase enable option status bit */
10821
10822/******************* Bits definition for FLASH_SCAR register *********************/
10823#define FLASH_SCAR_SEC_AREA_START_Pos (0U)
10824#define FLASH_SCAR_SEC_AREA_START_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */
10825#define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk /*!< Secure-only area start status bits */
10826#define FLASH_SCAR_SEC_AREA_END_Pos (16U)
10827#define FLASH_SCAR_SEC_AREA_END_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */
10828#define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk /*!< Secure-only area end status bits */
10829#define FLASH_SCAR_DMES_Pos (31U)
10830#define FLASH_SCAR_DMES_Msk (0x1UL << FLASH_SCAR_DMES_Pos) /*!< 0x80000000 */
10831#define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk /*!< Secure access protected erase enable option status bit */
10832
10833/******************* Bits definition for FLASH_WPSN register *********************/
10834#define FLASH_WPSN_WRPSN_Pos (0U)
10835#define FLASH_WPSN_WRPSN_Msk (0xFFUL << FLASH_WPSN_WRPSN_Pos) /*!< 0x000000FF */
10836#define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk /*!< Sector write protection option status byte */
10837
10838/******************* Bits definition for FLASH_BOOT_CUR register ****************/
10839#define FLASH_BOOT_ADD0_Pos (0U)
10840#define FLASH_BOOT_ADD0_Msk (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */
10841#define FLASH_BOOT_ADD0 FLASH_BOOT_ADD0_Msk /*!< Arm Cortex-M7 boot address 0 */
10842#define FLASH_BOOT_ADD1_Pos (16U)
10843#define FLASH_BOOT_ADD1_Msk (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */
10844#define FLASH_BOOT_ADD1 FLASH_BOOT_ADD1_Msk /*!< Arm Cortex-M7 boot address 1 */
10845
10846
10847/******************* Bits definition for FLASH_CRCCR register ********************/
10848#define FLASH_CRCCR_CRC_SECT_Pos (0U)
10849#define FLASH_CRCCR_CRC_SECT_Msk (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */
10850#define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk /*!< CRC sector number */
10851#define FLASH_CRCCR_CRC_BY_SECT_Pos (8U)
10852#define FLASH_CRCCR_CRC_BY_SECT_Msk (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */
10853#define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk /*!< CRC sector mode select bit */
10854#define FLASH_CRCCR_ADD_SECT_Pos (9U)
10855#define FLASH_CRCCR_ADD_SECT_Msk (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */
10856#define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk /*!< CRC sector select bit */
10857#define FLASH_CRCCR_CLEAN_SECT_Pos (10U)
10858#define FLASH_CRCCR_CLEAN_SECT_Msk (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */
10859#define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk /*!< CRC sector list clear bit */
10860#define FLASH_CRCCR_START_CRC_Pos (16U)
10861#define FLASH_CRCCR_START_CRC_Msk (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */
10862#define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk /*!< CRC start bit */
10863#define FLASH_CRCCR_CLEAN_CRC_Pos (17U)
10864#define FLASH_CRCCR_CLEAN_CRC_Msk (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */
10865#define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk /*!< CRC clear bit */
10866#define FLASH_CRCCR_CRC_BURST_Pos (20U)
10867#define FLASH_CRCCR_CRC_BURST_Msk (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */
10868#define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk /*!< CRC burst size */
10869#define FLASH_CRCCR_CRC_BURST_0 (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */
10870#define FLASH_CRCCR_CRC_BURST_1 (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */
10871#define FLASH_CRCCR_ALL_BANK_Pos (22U)
10872#define FLASH_CRCCR_ALL_BANK_Msk (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */
10873#define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk /*!< CRC select bit */
10874
10875/******************* Bits definition for FLASH_CRCSADD register ****************/
10876#define FLASH_CRCSADD_CRC_START_ADDR_Pos (0U)
10877#define FLASH_CRCSADD_CRC_START_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */
10878#define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk /*!< CRC start address */
10879
10880/******************* Bits definition for FLASH_CRCEADD register ****************/
10881#define FLASH_CRCEADD_CRC_END_ADDR_Pos (0U)
10882#define FLASH_CRCEADD_CRC_END_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */
10883#define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk /*!< CRC end address */
10884
10885/******************* Bits definition for FLASH_CRCDATA register ***************/
10886#define FLASH_CRCDATA_CRC_DATA_Pos (0U)
10887#define FLASH_CRCDATA_CRC_DATA_Msk (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */
10888#define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk /*!< CRC result */
10889
10890/******************* Bits definition for FLASH_ECC_FA register *******************/
10891#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos (0U)
10892#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */
10893#define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk /*!< ECC error address */
10894
10895/******************************************************************************/
10896/* */
10897/* Flexible Memory Controller */
10898/* */
10899/******************************************************************************/
10900/****************** Bit definition for FMC_BCR1 register *******************/
10901#define FMC_BCR1_CCLKEN_Pos (20U)
10902#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
10903#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
10904#define FMC_BCR1_WFDIS_Pos (21U)
10905#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
10906#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
10907
10908#define FMC_BCR1_BMAP_Pos (24U)
10909#define FMC_BCR1_BMAP_Msk (0x3UL << FMC_BCR1_BMAP_Pos) /*!< 0x03000000 */
10910#define FMC_BCR1_BMAP FMC_BCR1_BMAP_Msk /*!<BMAP[1:0] FMC bank mapping */
10911#define FMC_BCR1_BMAP_0 (0x1UL << FMC_BCR1_BMAP_Pos) /*!< 0x01000000 */
10912#define FMC_BCR1_BMAP_1 (0x2UL << FMC_BCR1_BMAP_Pos) /*!< 0x02000000 */
10913
10914#define FMC_BCR1_FMCEN_Pos (31U)
10915#define FMC_BCR1_FMCEN_Msk (0x1UL << FMC_BCR1_FMCEN_Pos) /*!< 0x80000000 */
10916#define FMC_BCR1_FMCEN FMC_BCR1_FMCEN_Msk /*!<FMC controller Enable */
10917/****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
10918#define FMC_BCRx_MBKEN_Pos (0U)
10919#define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
10920#define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk /*!<Memory bank enable bit */
10921#define FMC_BCRx_MUXEN_Pos (1U)
10922#define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
10923#define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk /*!<Address/data multiplexing enable bit */
10924
10925#define FMC_BCRx_MTYP_Pos (2U)
10926#define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
10927#define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
10928#define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
10929#define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
10930
10931#define FMC_BCRx_MWID_Pos (4U)
10932#define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos) /*!< 0x00000030 */
10933#define FMC_BCRx_MWID FMC_BCRx_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
10934#define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos) /*!< 0x00000010 */
10935#define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos) /*!< 0x00000020 */
10936
10937#define FMC_BCRx_FACCEN_Pos (6U)
10938#define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
10939#define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk /*!<Flash access enable */
10940#define FMC_BCRx_BURSTEN_Pos (8U)
10941#define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
10942#define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk /*!<Burst enable bit */
10943#define FMC_BCRx_WAITPOL_Pos (9U)
10944#define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
10945#define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk /*!<Wait signal polarity bit */
10946#define FMC_BCRx_WAITCFG_Pos (11U)
10947#define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
10948#define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk /*!<Wait timing configuration */
10949#define FMC_BCRx_WREN_Pos (12U)
10950#define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos) /*!< 0x00001000 */
10951#define FMC_BCRx_WREN FMC_BCRx_WREN_Msk /*!<Write enable bit */
10952#define FMC_BCRx_WAITEN_Pos (13U)
10953#define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
10954#define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk /*!<Wait enable bit */
10955#define FMC_BCRx_EXTMOD_Pos (14U)
10956#define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
10957#define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk /*!<Extended mode enable */
10958#define FMC_BCRx_ASYNCWAIT_Pos (15U)
10959#define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
10960#define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk /*!<Asynchronous wait */
10961
10962#define FMC_BCRx_CPSIZE_Pos (16U)
10963#define FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */
10964#define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk /*!<PSIZE[2:0] bits CRAM Page Size */
10965#define FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */
10966#define FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */
10967#define FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */
10968
10969#define FMC_BCRx_CBURSTRW_Pos (19U)
10970#define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
10971#define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk /*!<Write burst enable */
10972
10973/****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
10974#define FMC_BTRx_ADDSET_Pos (0U)
10975#define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
10976#define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
10977#define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
10978#define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
10979#define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
10980#define FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
10981
10982#define FMC_BTRx_ADDHLD_Pos (4U)
10983#define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
10984#define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
10985#define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
10986#define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
10987#define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
10988#define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
10989
10990#define FMC_BTRx_DATAST_Pos (8U)
10991#define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
10992#define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
10993#define FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
10994#define FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
10995#define FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
10996#define FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
10997#define FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
10998#define FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
10999#define FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
11000#define FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
11001
11002#define FMC_BTRx_BUSTURN_Pos (16U)
11003#define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
11004#define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
11005#define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
11006#define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
11007#define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
11008#define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
11009
11010#define FMC_BTRx_CLKDIV_Pos (20U)
11011#define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
11012#define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
11013#define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
11014#define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
11015#define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
11016#define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
11017
11018#define FMC_BTRx_DATLAT_Pos (24U)
11019#define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
11020#define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
11021#define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
11022#define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
11023#define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
11024#define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
11025
11026#define FMC_BTRx_ACCMOD_Pos (28U)
11027#define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
11028#define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
11029#define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
11030#define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
11031
11032/****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
11033#define FMC_BWTRx_ADDSET_Pos (0U)
11034#define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
11035#define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
11036#define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
11037#define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
11038#define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
11039#define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
11040
11041#define FMC_BWTRx_ADDHLD_Pos (4U)
11042#define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
11043#define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
11044#define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
11045#define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
11046#define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
11047#define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
11048
11049#define FMC_BWTRx_DATAST_Pos (8U)
11050#define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
11051#define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
11052#define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
11053#define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
11054#define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
11055#define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
11056#define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
11057#define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
11058#define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
11059#define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
11060
11061#define FMC_BWTRx_BUSTURN_Pos (16U)
11062#define FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */
11063#define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
11064#define FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */
11065#define FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */
11066#define FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */
11067#define FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */
11068
11069#define FMC_BWTRx_ACCMOD_Pos (28U)
11070#define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
11071#define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
11072#define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
11073#define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
11074
11075/****************** Bit definition for FMC_PCR register *******************/
11076#define FMC_PCR_PWAITEN_Pos (1U)
11077#define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
11078#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
11079#define FMC_PCR_PBKEN_Pos (2U)
11080#define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
11081#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<NAND Flash memory bank enable bit */
11082
11083#define FMC_PCR_PWID_Pos (4U)
11084#define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
11085#define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
11086#define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
11087#define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
11088
11089#define FMC_PCR_ECCEN_Pos (6U)
11090#define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
11091#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
11092
11093#define FMC_PCR_TCLR_Pos (9U)
11094#define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
11095#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
11096#define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
11097#define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
11098#define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
11099#define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
11100
11101#define FMC_PCR_TAR_Pos (13U)
11102#define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
11103#define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
11104#define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
11105#define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
11106#define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
11107#define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
11108
11109#define FMC_PCR_ECCPS_Pos (17U)
11110#define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
11111#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
11112#define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
11113#define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
11114#define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
11115
11116/******************* Bit definition for FMC_SR register *******************/
11117#define FMC_SR_IRS_Pos (0U)
11118#define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos) /*!< 0x00000001 */
11119#define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
11120#define FMC_SR_ILS_Pos (1U)
11121#define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos) /*!< 0x00000002 */
11122#define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
11123#define FMC_SR_IFS_Pos (2U)
11124#define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos) /*!< 0x00000004 */
11125#define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
11126#define FMC_SR_IREN_Pos (3U)
11127#define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos) /*!< 0x00000008 */
11128#define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
11129#define FMC_SR_ILEN_Pos (4U)
11130#define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
11131#define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
11132#define FMC_SR_IFEN_Pos (5U)
11133#define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
11134#define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
11135#define FMC_SR_FEMPT_Pos (6U)
11136#define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
11137#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
11138
11139/****************** Bit definition for FMC_PMEM register ******************/
11140#define FMC_PMEM_MEMSET_Pos (0U)
11141#define FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos) /*!< 0x000000FF */
11142#define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk /*!<MEMSET[7:0] bits (Common memory setup time) */
11143#define FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000001 */
11144#define FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000002 */
11145#define FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000004 */
11146#define FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000008 */
11147#define FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000010 */
11148#define FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000020 */
11149#define FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000040 */
11150#define FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000080 */
11151
11152#define FMC_PMEM_MEMWAIT_Pos (8U)
11153#define FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x0000FF00 */
11154#define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk /*!<MEMWAIT[7:0] bits (Common memory wait time) */
11155#define FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000100 */
11156#define FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000200 */
11157#define FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000400 */
11158#define FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000800 */
11159#define FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00001000 */
11160#define FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00002000 */
11161#define FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00004000 */
11162#define FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00008000 */
11163
11164#define FMC_PMEM_MEMHOLD_Pos (16U)
11165#define FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00FF0000 */
11166#define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk /*!<MEMHOLD[7:0] bits (Common memory hold time) */
11167#define FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00010000 */
11168#define FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00020000 */
11169#define FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00040000 */
11170#define FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00080000 */
11171#define FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00100000 */
11172#define FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00200000 */
11173#define FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00400000 */
11174#define FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00800000 */
11175
11176#define FMC_PMEM_MEMHIZ_Pos (24U)
11177#define FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos) /*!< 0xFF000000 */
11178#define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
11179#define FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x01000000 */
11180#define FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x02000000 */
11181#define FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x04000000 */
11182#define FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x08000000 */
11183#define FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x10000000 */
11184#define FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x20000000 */
11185#define FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x40000000 */
11186#define FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x80000000 */
11187
11188/****************** Bit definition for FMC_PATT register ******************/
11189#define FMC_PATT_ATTSET_Pos (0U)
11190#define FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos) /*!< 0x000000FF */
11191#define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk /*!<ATTSET[7:0] bits (Attribute memory setup time) */
11192#define FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000001 */
11193#define FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000002 */
11194#define FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000004 */
11195#define FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000008 */
11196#define FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000010 */
11197#define FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000020 */
11198#define FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000040 */
11199#define FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000080 */
11200
11201#define FMC_PATT_ATTWAIT_Pos (8U)
11202#define FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos) /*!< 0x0000FF00 */
11203#define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
11204#define FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000100 */
11205#define FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000200 */
11206#define FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000400 */
11207#define FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000800 */
11208#define FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00001000 */
11209#define FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00002000 */
11210#define FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00004000 */
11211#define FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00008000 */
11212
11213#define FMC_PATT_ATTHOLD_Pos (16U)
11214#define FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00FF0000 */
11215#define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
11216#define FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00010000 */
11217#define FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00020000 */
11218#define FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00040000 */
11219#define FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00080000 */
11220#define FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00100000 */
11221#define FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00200000 */
11222#define FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00400000 */
11223#define FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00800000 */
11224
11225#define FMC_PATT_ATTHIZ_Pos (24U)
11226#define FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos) /*!< 0xFF000000 */
11227#define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
11228#define FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x01000000 */
11229#define FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x02000000 */
11230#define FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x04000000 */
11231#define FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x08000000 */
11232#define FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x10000000 */
11233#define FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x20000000 */
11234#define FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x40000000 */
11235#define FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x80000000 */
11236
11237/****************** Bit definition for FMC_ECCR3 register ******************/
11238#define FMC_ECCR3_ECC3_Pos (0U)
11239#define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
11240#define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk /*!<ECC result */
11241
11242/****************** Bit definition for FMC_SDCRx registers (x=1..4) *********/
11243#define FMC_SDCRx_NC_Pos (0U)
11244#define FMC_SDCRx_NC_Msk (0x3UL << FMC_SDCRx_NC_Pos) /*!< 0x00000003 */
11245#define FMC_SDCRx_NC FMC_SDCRx_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
11246#define FMC_SDCRx_NC_0 (0x1UL << FMC_SDCRx_NC_Pos) /*!< 0x00000001 */
11247#define FMC_SDCRx_NC_1 (0x2UL << FMC_SDCRx_NC_Pos) /*!< 0x00000002 */
11248
11249#define FMC_SDCRx_NR_Pos (2U)
11250#define FMC_SDCRx_NR_Msk (0x3UL << FMC_SDCRx_NR_Pos) /*!< 0x0000000C */
11251#define FMC_SDCRx_NR FMC_SDCRx_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
11252#define FMC_SDCRx_NR_0 (0x1UL << FMC_SDCRx_NR_Pos) /*!< 0x00000004 */
11253#define FMC_SDCRx_NR_1 (0x2UL << FMC_SDCRx_NR_Pos) /*!< 0x00000008 */
11254
11255#define FMC_SDCRx_MWID_Pos (4U)
11256#define FMC_SDCRx_MWID_Msk (0x3UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000030 */
11257#define FMC_SDCRx_MWID FMC_SDCRx_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
11258#define FMC_SDCRx_MWID_0 (0x1UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000010 */
11259#define FMC_SDCRx_MWID_1 (0x2UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000020 */
11260
11261#define FMC_SDCRx_NB_Pos (6U)
11262#define FMC_SDCRx_NB_Msk (0x1UL << FMC_SDCRx_NB_Pos) /*!< 0x00000040 */
11263#define FMC_SDCRx_NB FMC_SDCRx_NB_Msk /*!<Number of internal bank */
11264
11265#define FMC_SDCRx_CAS_Pos (7U)
11266#define FMC_SDCRx_CAS_Msk (0x3UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000180 */
11267#define FMC_SDCRx_CAS FMC_SDCRx_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
11268#define FMC_SDCRx_CAS_0 (0x1UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000080 */
11269#define FMC_SDCRx_CAS_1 (0x2UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000100 */
11270
11271#define FMC_SDCRx_WP_Pos (9U)
11272#define FMC_SDCRx_WP_Msk (0x1UL << FMC_SDCRx_WP_Pos) /*!< 0x00000200 */
11273#define FMC_SDCRx_WP FMC_SDCRx_WP_Msk /*!<Write protection */
11274
11275#define FMC_SDCRx_SDCLK_Pos (10U)
11276#define FMC_SDCRx_SDCLK_Msk (0x3UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000C00 */
11277#define FMC_SDCRx_SDCLK FMC_SDCRx_SDCLK_Msk /*!<SDRAM clock configuration */
11278#define FMC_SDCRx_SDCLK_0 (0x1UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000400 */
11279#define FMC_SDCRx_SDCLK_1 (0x2UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000800 */
11280
11281#define FMC_SDCRx_RBURST_Pos (12U)
11282#define FMC_SDCRx_RBURST_Msk (0x1UL << FMC_SDCRx_RBURST_Pos) /*!< 0x00001000 */
11283#define FMC_SDCRx_RBURST FMC_SDCRx_RBURST_Msk /*!<Read burst */
11284
11285#define FMC_SDCRx_RPIPE_Pos (13U)
11286#define FMC_SDCRx_RPIPE_Msk (0x3UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00006000 */
11287#define FMC_SDCRx_RPIPE FMC_SDCRx_RPIPE_Msk /*!<Write protection */
11288#define FMC_SDCRx_RPIPE_0 (0x1UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00002000 */
11289#define FMC_SDCRx_RPIPE_1 (0x2UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00004000 */
11290
11291/****************** Bit definition for FMC_SDTRx(1,2) register ******************/
11292#define FMC_SDTRx_TMRD_Pos (0U)
11293#define FMC_SDTRx_TMRD_Msk (0xFUL << FMC_SDTRx_TMRD_Pos) /*!< 0x0000000F */
11294#define FMC_SDTRx_TMRD FMC_SDTRx_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
11295#define FMC_SDTRx_TMRD_0 (0x1UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000001 */
11296#define FMC_SDTRx_TMRD_1 (0x2UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000002 */
11297#define FMC_SDTRx_TMRD_2 (0x4UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000004 */
11298#define FMC_SDTRx_TMRD_3 (0x8UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000008 */
11299
11300#define FMC_SDTRx_TXSR_Pos (4U)
11301#define FMC_SDTRx_TXSR_Msk (0xFUL << FMC_SDTRx_TXSR_Pos) /*!< 0x000000F0 */
11302#define FMC_SDTRx_TXSR FMC_SDTRx_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
11303#define FMC_SDTRx_TXSR_0 (0x1UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000010 */
11304#define FMC_SDTRx_TXSR_1 (0x2UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000020 */
11305#define FMC_SDTRx_TXSR_2 (0x4UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000040 */
11306#define FMC_SDTRx_TXSR_3 (0x8UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000080 */
11307
11308#define FMC_SDTRx_TRAS_Pos (8U)
11309#define FMC_SDTRx_TRAS_Msk (0xFUL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000F00 */
11310#define FMC_SDTRx_TRAS FMC_SDTRx_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
11311#define FMC_SDTRx_TRAS_0 (0x1UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000100 */
11312#define FMC_SDTRx_TRAS_1 (0x2UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000200 */
11313#define FMC_SDTRx_TRAS_2 (0x4UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000400 */
11314#define FMC_SDTRx_TRAS_3 (0x8UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000800 */
11315
11316#define FMC_SDTRx_TRC_Pos (12U)
11317#define FMC_SDTRx_TRC_Msk (0xFUL << FMC_SDTRx_TRC_Pos) /*!< 0x0000F000 */
11318#define FMC_SDTRx_TRC FMC_SDTRx_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
11319#define FMC_SDTRx_TRC_0 (0x1UL << FMC_SDTRx_TRC_Pos) /*!< 0x00001000 */
11320#define FMC_SDTRx_TRC_1 (0x2UL << FMC_SDTRx_TRC_Pos) /*!< 0x00002000 */
11321#define FMC_SDTRx_TRC_2 (0x4UL << FMC_SDTRx_TRC_Pos) /*!< 0x00004000 */
11322
11323#define FMC_SDTRx_TWR_Pos (16U)
11324#define FMC_SDTRx_TWR_Msk (0xFUL << FMC_SDTRx_TWR_Pos) /*!< 0x000F0000 */
11325#define FMC_SDTRx_TWR FMC_SDTRx_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
11326#define FMC_SDTRx_TWR_0 (0x1UL << FMC_SDTRx_TWR_Pos) /*!< 0x00010000 */
11327#define FMC_SDTRx_TWR_1 (0x2UL << FMC_SDTRx_TWR_Pos) /*!< 0x00020000 */
11328#define FMC_SDTRx_TWR_2 (0x4UL << FMC_SDTRx_TWR_Pos) /*!< 0x00040000 */
11329
11330#define FMC_SDTRx_TRP_Pos (20U)
11331#define FMC_SDTRx_TRP_Msk (0xFUL << FMC_SDTRx_TRP_Pos) /*!< 0x00F00000 */
11332#define FMC_SDTRx_TRP FMC_SDTRx_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
11333#define FMC_SDTRx_TRP_0 (0x1UL << FMC_SDTRx_TRP_Pos) /*!< 0x00100000 */
11334#define FMC_SDTRx_TRP_1 (0x2UL << FMC_SDTRx_TRP_Pos) /*!< 0x00200000 */
11335#define FMC_SDTRx_TRP_2 (0x4UL << FMC_SDTRx_TRP_Pos) /*!< 0x00400000 */
11336
11337#define FMC_SDTRx_TRCD_Pos (24U)
11338#define FMC_SDTRx_TRCD_Msk (0xFUL << FMC_SDTRx_TRCD_Pos) /*!< 0x0F000000 */
11339#define FMC_SDTRx_TRCD FMC_SDTRx_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
11340#define FMC_SDTRx_TRCD_0 (0x1UL << FMC_SDTRx_TRCD_Pos) /*!< 0x01000000 */
11341#define FMC_SDTRx_TRCD_1 (0x2UL << FMC_SDTRx_TRCD_Pos) /*!< 0x02000000 */
11342#define FMC_SDTRx_TRCD_2 (0x4UL << FMC_SDTRx_TRCD_Pos) /*!< 0x04000000 */
11343
11344/****************** Bit definition for FMC_SDCMR register ******************/
11345#define FMC_SDCMR_MODE_Pos (0U)
11346#define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
11347#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
11348#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
11349#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
11350#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
11351
11352#define FMC_SDCMR_CTB2_Pos (3U)
11353#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
11354#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
11355
11356#define FMC_SDCMR_CTB1_Pos (4U)
11357#define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
11358#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
11359
11360#define FMC_SDCMR_NRFS_Pos (5U)
11361#define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
11362#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
11363#define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
11364#define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
11365#define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
11366#define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
11367
11368#define FMC_SDCMR_MRD_Pos (9U)
11369#define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
11370#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
11371
11372/****************** Bit definition for FMC_SDRTR register ******************/
11373#define FMC_SDRTR_CRE_Pos (0U)
11374#define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
11375#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
11376
11377#define FMC_SDRTR_COUNT_Pos (1U)
11378#define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
11379#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
11380
11381#define FMC_SDRTR_REIE_Pos (14U)
11382#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
11383#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
11384
11385/****************** Bit definition for FMC_SDSR register ******************/
11386#define FMC_SDSR_RE_Pos (0U)
11387#define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
11388#define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
11389
11390#define FMC_SDSR_MODES1_Pos (1U)
11391#define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
11392#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
11393#define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
11394#define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
11395
11396#define FMC_SDSR_MODES2_Pos (3U)
11397#define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
11398#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
11399#define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
11400#define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
11401
11402/******************************************************************************/
11403/* */
11404/* General Purpose I/O */
11405/* */
11406/******************************************************************************/
11407/****************** Bits definition for GPIO_MODER register *****************/
11408#define GPIO_MODER_MODE0_Pos (0U)
11409#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
11410#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
11411#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
11412#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
11413
11414#define GPIO_MODER_MODE1_Pos (2U)
11415#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
11416#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
11417#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
11418#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
11419
11420#define GPIO_MODER_MODE2_Pos (4U)
11421#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
11422#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
11423#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
11424#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
11425
11426#define GPIO_MODER_MODE3_Pos (6U)
11427#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
11428#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
11429#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
11430#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
11431
11432#define GPIO_MODER_MODE4_Pos (8U)
11433#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
11434#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
11435#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
11436#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
11437
11438#define GPIO_MODER_MODE5_Pos (10U)
11439#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
11440#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
11441#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
11442#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
11443
11444#define GPIO_MODER_MODE6_Pos (12U)
11445#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
11446#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
11447#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
11448#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
11449
11450#define GPIO_MODER_MODE7_Pos (14U)
11451#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
11452#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
11453#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
11454#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
11455
11456#define GPIO_MODER_MODE8_Pos (16U)
11457#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
11458#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
11459#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
11460#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
11461
11462#define GPIO_MODER_MODE9_Pos (18U)
11463#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
11464#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
11465#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
11466#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
11467
11468#define GPIO_MODER_MODE10_Pos (20U)
11469#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
11470#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
11471#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
11472#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
11473
11474#define GPIO_MODER_MODE11_Pos (22U)
11475#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
11476#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
11477#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
11478#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
11479
11480#define GPIO_MODER_MODE12_Pos (24U)
11481#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
11482#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
11483#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
11484#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
11485
11486#define GPIO_MODER_MODE13_Pos (26U)
11487#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
11488#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
11489#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
11490#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
11491
11492#define GPIO_MODER_MODE14_Pos (28U)
11493#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
11494#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
11495#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
11496#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
11497
11498#define GPIO_MODER_MODE15_Pos (30U)
11499#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
11500#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
11501#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
11502#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
11503
11504/****************** Bits definition for GPIO_OTYPER register ****************/
11505#define GPIO_OTYPER_OT0_Pos (0U)
11506#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
11507#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
11508#define GPIO_OTYPER_OT1_Pos (1U)
11509#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
11510#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
11511#define GPIO_OTYPER_OT2_Pos (2U)
11512#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
11513#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
11514#define GPIO_OTYPER_OT3_Pos (3U)
11515#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
11516#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
11517#define GPIO_OTYPER_OT4_Pos (4U)
11518#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
11519#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
11520#define GPIO_OTYPER_OT5_Pos (5U)
11521#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
11522#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
11523#define GPIO_OTYPER_OT6_Pos (6U)
11524#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
11525#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
11526#define GPIO_OTYPER_OT7_Pos (7U)
11527#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
11528#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
11529#define GPIO_OTYPER_OT8_Pos (8U)
11530#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
11531#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
11532#define GPIO_OTYPER_OT9_Pos (9U)
11533#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
11534#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
11535#define GPIO_OTYPER_OT10_Pos (10U)
11536#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
11537#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
11538#define GPIO_OTYPER_OT11_Pos (11U)
11539#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
11540#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
11541#define GPIO_OTYPER_OT12_Pos (12U)
11542#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
11543#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
11544#define GPIO_OTYPER_OT13_Pos (13U)
11545#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
11546#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
11547#define GPIO_OTYPER_OT14_Pos (14U)
11548#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
11549#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
11550#define GPIO_OTYPER_OT15_Pos (15U)
11551#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
11552#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
11553
11554/****************** Bits definition for GPIO_OSPEEDR register ***************/
11555#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
11556#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
11557#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
11558#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
11559#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
11560
11561#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
11562#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
11563#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
11564#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
11565#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
11566
11567#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
11568#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
11569#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
11570#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
11571#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
11572
11573#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
11574#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
11575#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
11576#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
11577#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
11578
11579#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
11580#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
11581#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
11582#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
11583#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
11584
11585#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
11586#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
11587#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
11588#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
11589#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
11590
11591#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
11592#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
11593#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
11594#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
11595#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
11596
11597#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
11598#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
11599#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
11600#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
11601#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
11602
11603#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
11604#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
11605#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
11606#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
11607#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
11608
11609#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
11610#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
11611#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
11612#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
11613#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
11614
11615#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
11616#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
11617#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
11618#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
11619#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
11620
11621#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
11622#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
11623#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
11624#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
11625#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
11626
11627#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
11628#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
11629#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
11630#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
11631#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
11632
11633#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
11634#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
11635#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
11636#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
11637#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
11638
11639#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
11640#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
11641#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
11642#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
11643#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
11644
11645#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
11646#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
11647#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
11648#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
11649#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
11650
11651/****************** Bits definition for GPIO_PUPDR register *****************/
11652#define GPIO_PUPDR_PUPD0_Pos (0U)
11653#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
11654#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
11655#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
11656#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
11657
11658#define GPIO_PUPDR_PUPD1_Pos (2U)
11659#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
11660#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
11661#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
11662#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
11663
11664#define GPIO_PUPDR_PUPD2_Pos (4U)
11665#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
11666#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
11667#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
11668#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
11669
11670#define GPIO_PUPDR_PUPD3_Pos (6U)
11671#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
11672#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
11673#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
11674#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
11675
11676#define GPIO_PUPDR_PUPD4_Pos (8U)
11677#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
11678#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
11679#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
11680#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
11681
11682#define GPIO_PUPDR_PUPD5_Pos (10U)
11683#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
11684#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
11685#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
11686#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
11687
11688#define GPIO_PUPDR_PUPD6_Pos (12U)
11689#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
11690#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
11691#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
11692#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
11693
11694#define GPIO_PUPDR_PUPD7_Pos (14U)
11695#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
11696#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
11697#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
11698#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
11699
11700#define GPIO_PUPDR_PUPD8_Pos (16U)
11701#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
11702#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
11703#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
11704#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
11705
11706#define GPIO_PUPDR_PUPD9_Pos (18U)
11707#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
11708#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
11709#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
11710#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
11711
11712#define GPIO_PUPDR_PUPD10_Pos (20U)
11713#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
11714#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
11715#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
11716#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
11717
11718#define GPIO_PUPDR_PUPD11_Pos (22U)
11719#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
11720#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
11721#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
11722#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
11723
11724#define GPIO_PUPDR_PUPD12_Pos (24U)
11725#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
11726#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
11727#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
11728#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
11729
11730#define GPIO_PUPDR_PUPD13_Pos (26U)
11731#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
11732#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
11733#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
11734#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
11735
11736#define GPIO_PUPDR_PUPD14_Pos (28U)
11737#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
11738#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
11739#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
11740#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
11741
11742#define GPIO_PUPDR_PUPD15_Pos (30U)
11743#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
11744#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
11745#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
11746#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
11747
11748/****************** Bits definition for GPIO_IDR register *******************/
11749#define GPIO_IDR_ID0_Pos (0U)
11750#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
11751#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
11752#define GPIO_IDR_ID1_Pos (1U)
11753#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
11754#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
11755#define GPIO_IDR_ID2_Pos (2U)
11756#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
11757#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
11758#define GPIO_IDR_ID3_Pos (3U)
11759#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
11760#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
11761#define GPIO_IDR_ID4_Pos (4U)
11762#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
11763#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
11764#define GPIO_IDR_ID5_Pos (5U)
11765#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
11766#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
11767#define GPIO_IDR_ID6_Pos (6U)
11768#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
11769#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
11770#define GPIO_IDR_ID7_Pos (7U)
11771#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
11772#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
11773#define GPIO_IDR_ID8_Pos (8U)
11774#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
11775#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
11776#define GPIO_IDR_ID9_Pos (9U)
11777#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
11778#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
11779#define GPIO_IDR_ID10_Pos (10U)
11780#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
11781#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
11782#define GPIO_IDR_ID11_Pos (11U)
11783#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
11784#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
11785#define GPIO_IDR_ID12_Pos (12U)
11786#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
11787#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
11788#define GPIO_IDR_ID13_Pos (13U)
11789#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
11790#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
11791#define GPIO_IDR_ID14_Pos (14U)
11792#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
11793#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
11794#define GPIO_IDR_ID15_Pos (15U)
11795#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
11796#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
11797
11798/****************** Bits definition for GPIO_ODR register *******************/
11799#define GPIO_ODR_OD0_Pos (0U)
11800#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
11801#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
11802#define GPIO_ODR_OD1_Pos (1U)
11803#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
11804#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
11805#define GPIO_ODR_OD2_Pos (2U)
11806#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
11807#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
11808#define GPIO_ODR_OD3_Pos (3U)
11809#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
11810#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
11811#define GPIO_ODR_OD4_Pos (4U)
11812#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
11813#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
11814#define GPIO_ODR_OD5_Pos (5U)
11815#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
11816#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
11817#define GPIO_ODR_OD6_Pos (6U)
11818#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
11819#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
11820#define GPIO_ODR_OD7_Pos (7U)
11821#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
11822#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
11823#define GPIO_ODR_OD8_Pos (8U)
11824#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
11825#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
11826#define GPIO_ODR_OD9_Pos (9U)
11827#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
11828#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
11829#define GPIO_ODR_OD10_Pos (10U)
11830#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
11831#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
11832#define GPIO_ODR_OD11_Pos (11U)
11833#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
11834#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
11835#define GPIO_ODR_OD12_Pos (12U)
11836#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
11837#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
11838#define GPIO_ODR_OD13_Pos (13U)
11839#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
11840#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
11841#define GPIO_ODR_OD14_Pos (14U)
11842#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
11843#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
11844#define GPIO_ODR_OD15_Pos (15U)
11845#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
11846#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
11847
11848/****************** Bits definition for GPIO_BSRR register ******************/
11849#define GPIO_BSRR_BS0_Pos (0U)
11850#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
11851#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
11852#define GPIO_BSRR_BS1_Pos (1U)
11853#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
11854#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
11855#define GPIO_BSRR_BS2_Pos (2U)
11856#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
11857#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
11858#define GPIO_BSRR_BS3_Pos (3U)
11859#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
11860#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
11861#define GPIO_BSRR_BS4_Pos (4U)
11862#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
11863#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
11864#define GPIO_BSRR_BS5_Pos (5U)
11865#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
11866#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
11867#define GPIO_BSRR_BS6_Pos (6U)
11868#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
11869#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
11870#define GPIO_BSRR_BS7_Pos (7U)
11871#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
11872#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
11873#define GPIO_BSRR_BS8_Pos (8U)
11874#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
11875#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
11876#define GPIO_BSRR_BS9_Pos (9U)
11877#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
11878#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
11879#define GPIO_BSRR_BS10_Pos (10U)
11880#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
11881#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
11882#define GPIO_BSRR_BS11_Pos (11U)
11883#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
11884#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
11885#define GPIO_BSRR_BS12_Pos (12U)
11886#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
11887#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
11888#define GPIO_BSRR_BS13_Pos (13U)
11889#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
11890#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
11891#define GPIO_BSRR_BS14_Pos (14U)
11892#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
11893#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
11894#define GPIO_BSRR_BS15_Pos (15U)
11895#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
11896#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
11897#define GPIO_BSRR_BR0_Pos (16U)
11898#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
11899#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
11900#define GPIO_BSRR_BR1_Pos (17U)
11901#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
11902#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
11903#define GPIO_BSRR_BR2_Pos (18U)
11904#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
11905#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
11906#define GPIO_BSRR_BR3_Pos (19U)
11907#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
11908#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
11909#define GPIO_BSRR_BR4_Pos (20U)
11910#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
11911#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
11912#define GPIO_BSRR_BR5_Pos (21U)
11913#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
11914#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
11915#define GPIO_BSRR_BR6_Pos (22U)
11916#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
11917#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
11918#define GPIO_BSRR_BR7_Pos (23U)
11919#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
11920#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
11921#define GPIO_BSRR_BR8_Pos (24U)
11922#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
11923#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
11924#define GPIO_BSRR_BR9_Pos (25U)
11925#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
11926#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
11927#define GPIO_BSRR_BR10_Pos (26U)
11928#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
11929#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
11930#define GPIO_BSRR_BR11_Pos (27U)
11931#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
11932#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
11933#define GPIO_BSRR_BR12_Pos (28U)
11934#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
11935#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
11936#define GPIO_BSRR_BR13_Pos (29U)
11937#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
11938#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
11939#define GPIO_BSRR_BR14_Pos (30U)
11940#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
11941#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
11942#define GPIO_BSRR_BR15_Pos (31U)
11943#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
11944#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
11945
11946/****************** Bit definition for GPIO_LCKR register *********************/
11947#define GPIO_LCKR_LCK0_Pos (0U)
11948#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
11949#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
11950#define GPIO_LCKR_LCK1_Pos (1U)
11951#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
11952#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
11953#define GPIO_LCKR_LCK2_Pos (2U)
11954#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
11955#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
11956#define GPIO_LCKR_LCK3_Pos (3U)
11957#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
11958#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
11959#define GPIO_LCKR_LCK4_Pos (4U)
11960#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
11961#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
11962#define GPIO_LCKR_LCK5_Pos (5U)
11963#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
11964#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
11965#define GPIO_LCKR_LCK6_Pos (6U)
11966#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
11967#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
11968#define GPIO_LCKR_LCK7_Pos (7U)
11969#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
11970#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
11971#define GPIO_LCKR_LCK8_Pos (8U)
11972#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
11973#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
11974#define GPIO_LCKR_LCK9_Pos (9U)
11975#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
11976#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
11977#define GPIO_LCKR_LCK10_Pos (10U)
11978#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
11979#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
11980#define GPIO_LCKR_LCK11_Pos (11U)
11981#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
11982#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
11983#define GPIO_LCKR_LCK12_Pos (12U)
11984#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
11985#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
11986#define GPIO_LCKR_LCK13_Pos (13U)
11987#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
11988#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
11989#define GPIO_LCKR_LCK14_Pos (14U)
11990#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
11991#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
11992#define GPIO_LCKR_LCK15_Pos (15U)
11993#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
11994#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
11995#define GPIO_LCKR_LCKK_Pos (16U)
11996#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
11997#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
11998
11999/****************** Bit definition for GPIO_AFRL register ********************/
12000#define GPIO_AFRL_AFSEL0_Pos (0U)
12001#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
12002#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
12003#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
12004#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
12005#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
12006#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
12007#define GPIO_AFRL_AFSEL1_Pos (4U)
12008#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
12009#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
12010#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
12011#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
12012#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
12013#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
12014#define GPIO_AFRL_AFSEL2_Pos (8U)
12015#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
12016#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
12017#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
12018#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
12019#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
12020#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
12021#define GPIO_AFRL_AFSEL3_Pos (12U)
12022#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
12023#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
12024#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
12025#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
12026#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
12027#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
12028#define GPIO_AFRL_AFSEL4_Pos (16U)
12029#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
12030#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
12031#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
12032#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
12033#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
12034#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
12035#define GPIO_AFRL_AFSEL5_Pos (20U)
12036#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
12037#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
12038#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
12039#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
12040#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
12041#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
12042#define GPIO_AFRL_AFSEL6_Pos (24U)
12043#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
12044#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
12045#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
12046#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
12047#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
12048#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
12049#define GPIO_AFRL_AFSEL7_Pos (28U)
12050#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
12051#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
12052#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
12053#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
12054#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
12055#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
12056
12057/* Legacy defines */
12058#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
12059#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
12060#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
12061#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
12062#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
12063#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
12064#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
12065#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
12066
12067/****************** Bit definition for GPIO_AFRH register ********************/
12068#define GPIO_AFRH_AFSEL8_Pos (0U)
12069#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
12070#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
12071#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
12072#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
12073#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
12074#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
12075#define GPIO_AFRH_AFSEL9_Pos (4U)
12076#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
12077#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
12078#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
12079#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
12080#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
12081#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
12082#define GPIO_AFRH_AFSEL10_Pos (8U)
12083#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
12084#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
12085#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
12086#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
12087#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
12088#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
12089#define GPIO_AFRH_AFSEL11_Pos (12U)
12090#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
12091#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
12092#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
12093#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
12094#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
12095#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
12096#define GPIO_AFRH_AFSEL12_Pos (16U)
12097#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
12098#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
12099#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
12100#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
12101#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
12102#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
12103#define GPIO_AFRH_AFSEL13_Pos (20U)
12104#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
12105#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
12106#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
12107#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
12108#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
12109#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
12110#define GPIO_AFRH_AFSEL14_Pos (24U)
12111#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
12112#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
12113#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
12114#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
12115#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
12116#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
12117#define GPIO_AFRH_AFSEL15_Pos (28U)
12118#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
12119#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
12120#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
12121#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
12122#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
12123#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
12124
12125/* Legacy defines */
12126#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
12127#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
12128#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
12129#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
12130#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
12131#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
12132#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
12133#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
12134
12135/******************************************************************************/
12136/* */
12137/* HSEM HW Semaphore */
12138/* */
12139/******************************************************************************/
12140/******************** Bit definition for HSEM_R register ********************/
12141#define HSEM_R_PROCID_Pos (0U)
12142#define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) /*!< 0x000000FF */
12143#define HSEM_R_PROCID HSEM_R_PROCID_Msk /*!<Semaphore ProcessID */
12144#define HSEM_R_COREID_Pos (8U)
12145#define HSEM_R_COREID_Msk (0xFFUL << HSEM_R_COREID_Pos) /*!< 0x0000FF00 */
12146#define HSEM_R_COREID HSEM_R_COREID_Msk /*!<Semaphore CoreID. */
12147#define HSEM_R_LOCK_Pos (31U)
12148#define HSEM_R_LOCK_Msk (0x1UL << HSEM_R_LOCK_Pos) /*!< 0x80000000 */
12149#define HSEM_R_LOCK HSEM_R_LOCK_Msk /*!<Lock indication. */
12150
12151/******************** Bit definition for HSEM_RLR register ******************/
12152#define HSEM_RLR_PROCID_Pos (0U)
12153#define HSEM_RLR_PROCID_Msk (0xFFUL << HSEM_RLR_PROCID_Pos) /*!< 0x000000FF */
12154#define HSEM_RLR_PROCID HSEM_RLR_PROCID_Msk /*!<Semaphore ProcessID */
12155#define HSEM_RLR_COREID_Pos (8U)
12156#define HSEM_RLR_COREID_Msk (0xFFUL << HSEM_RLR_COREID_Pos) /*!< 0x0000FF00 */
12157#define HSEM_RLR_COREID HSEM_RLR_COREID_Msk /*!<Semaphore CoreID. */
12158#define HSEM_RLR_LOCK_Pos (31U)
12159#define HSEM_RLR_LOCK_Msk (0x1UL << HSEM_RLR_LOCK_Pos) /*!< 0x80000000 */
12160#define HSEM_RLR_LOCK HSEM_RLR_LOCK_Msk /*!<Lock indication. */
12161
12162/******************** Bit definition for HSEM_C1IER register *****************/
12163#define HSEM_C1IER_ISE0_Pos (0U)
12164#define HSEM_C1IER_ISE0_Msk (0x1UL << HSEM_C1IER_ISE0_Pos) /*!< 0x00000001 */
12165#define HSEM_C1IER_ISE0 HSEM_C1IER_ISE0_Msk /*!<semaphore 0 , interrupt 0 enable bit. */
12166#define HSEM_C1IER_ISE1_Pos (1U)
12167#define HSEM_C1IER_ISE1_Msk (0x1UL << HSEM_C1IER_ISE1_Pos) /*!< 0x00000002 */
12168#define HSEM_C1IER_ISE1 HSEM_C1IER_ISE1_Msk /*!<semaphore 1 , interrupt 0 enable bit. */
12169#define HSEM_C1IER_ISE2_Pos (2U)
12170#define HSEM_C1IER_ISE2_Msk (0x1UL << HSEM_C1IER_ISE2_Pos) /*!< 0x00000004 */
12171#define HSEM_C1IER_ISE2 HSEM_C1IER_ISE2_Msk /*!<semaphore 2 , interrupt 0 enable bit. */
12172#define HSEM_C1IER_ISE3_Pos (3U)
12173#define HSEM_C1IER_ISE3_Msk (0x1UL << HSEM_C1IER_ISE3_Pos) /*!< 0x00000008 */
12174#define HSEM_C1IER_ISE3 HSEM_C1IER_ISE3_Msk /*!<semaphore 3 , interrupt 0 enable bit. */
12175#define HSEM_C1IER_ISE4_Pos (4U)
12176#define HSEM_C1IER_ISE4_Msk (0x1UL << HSEM_C1IER_ISE4_Pos) /*!< 0x00000010 */
12177#define HSEM_C1IER_ISE4 HSEM_C1IER_ISE4_Msk /*!<semaphore 4 , interrupt 0 enable bit. */
12178#define HSEM_C1IER_ISE5_Pos (5U)
12179#define HSEM_C1IER_ISE5_Msk (0x1UL << HSEM_C1IER_ISE5_Pos) /*!< 0x00000020 */
12180#define HSEM_C1IER_ISE5 HSEM_C1IER_ISE5_Msk /*!<semaphore 5 interrupt 0 enable bit. */
12181#define HSEM_C1IER_ISE6_Pos (6U)
12182#define HSEM_C1IER_ISE6_Msk (0x1UL << HSEM_C1IER_ISE6_Pos) /*!< 0x00000040 */
12183#define HSEM_C1IER_ISE6 HSEM_C1IER_ISE6_Msk /*!<semaphore 6 interrupt 0 enable bit. */
12184#define HSEM_C1IER_ISE7_Pos (7U)
12185#define HSEM_C1IER_ISE7_Msk (0x1UL << HSEM_C1IER_ISE7_Pos) /*!< 0x00000080 */
12186#define HSEM_C1IER_ISE7 HSEM_C1IER_ISE7_Msk /*!<semaphore 7 interrupt 0 enable bit. */
12187#define HSEM_C1IER_ISE8_Pos (8U)
12188#define HSEM_C1IER_ISE8_Msk (0x1UL << HSEM_C1IER_ISE8_Pos) /*!< 0x00000100 */
12189#define HSEM_C1IER_ISE8 HSEM_C1IER_ISE8_Msk /*!<semaphore 8 interrupt 0 enable bit. */
12190#define HSEM_C1IER_ISE9_Pos (9U)
12191#define HSEM_C1IER_ISE9_Msk (0x1UL << HSEM_C1IER_ISE9_Pos) /*!< 0x00000200 */
12192#define HSEM_C1IER_ISE9 HSEM_C1IER_ISE9_Msk /*!<semaphore 9 interrupt 0 enable bit. */
12193#define HSEM_C1IER_ISE10_Pos (10U)
12194#define HSEM_C1IER_ISE10_Msk (0x1UL << HSEM_C1IER_ISE10_Pos) /*!< 0x00000400 */
12195#define HSEM_C1IER_ISE10 HSEM_C1IER_ISE10_Msk /*!<semaphore 10 interrupt 0 enable bit. */
12196#define HSEM_C1IER_ISE11_Pos (11U)
12197#define HSEM_C1IER_ISE11_Msk (0x1UL << HSEM_C1IER_ISE11_Pos) /*!< 0x00000800 */
12198#define HSEM_C1IER_ISE11 HSEM_C1IER_ISE11_Msk /*!<semaphore 11 interrupt 0 enable bit. */
12199#define HSEM_C1IER_ISE12_Pos (12U)
12200#define HSEM_C1IER_ISE12_Msk (0x1UL << HSEM_C1IER_ISE12_Pos) /*!< 0x00001000 */
12201#define HSEM_C1IER_ISE12 HSEM_C1IER_ISE12_Msk /*!<semaphore 12 interrupt 0 enable bit. */
12202#define HSEM_C1IER_ISE13_Pos (13U)
12203#define HSEM_C1IER_ISE13_Msk (0x1UL << HSEM_C1IER_ISE13_Pos) /*!< 0x00002000 */
12204#define HSEM_C1IER_ISE13 HSEM_C1IER_ISE13_Msk /*!<semaphore 13 interrupt 0 enable bit. */
12205#define HSEM_C1IER_ISE14_Pos (14U)
12206#define HSEM_C1IER_ISE14_Msk (0x1UL << HSEM_C1IER_ISE14_Pos) /*!< 0x00004000 */
12207#define HSEM_C1IER_ISE14 HSEM_C1IER_ISE14_Msk /*!<semaphore 14 interrupt 0 enable bit. */
12208#define HSEM_C1IER_ISE15_Pos (15U)
12209#define HSEM_C1IER_ISE15_Msk (0x1UL << HSEM_C1IER_ISE15_Pos) /*!< 0x00008000 */
12210#define HSEM_C1IER_ISE15 HSEM_C1IER_ISE15_Msk /*!<semaphore 15 interrupt 0 enable bit. */
12211#define HSEM_C1IER_ISE16_Pos (16U)
12212#define HSEM_C1IER_ISE16_Msk (0x1UL << HSEM_C1IER_ISE16_Pos) /*!< 0x00010000 */
12213#define HSEM_C1IER_ISE16 HSEM_C1IER_ISE16_Msk /*!<semaphore 16 interrupt 0 enable bit. */
12214#define HSEM_C1IER_ISE17_Pos (17U)
12215#define HSEM_C1IER_ISE17_Msk (0x1UL << HSEM_C1IER_ISE17_Pos) /*!< 0x00020000 */
12216#define HSEM_C1IER_ISE17 HSEM_C1IER_ISE17_Msk /*!<semaphore 17 interrupt 0 enable bit. */
12217#define HSEM_C1IER_ISE18_Pos (18U)
12218#define HSEM_C1IER_ISE18_Msk (0x1UL << HSEM_C1IER_ISE18_Pos) /*!< 0x00040000 */
12219#define HSEM_C1IER_ISE18 HSEM_C1IER_ISE18_Msk /*!<semaphore 18 interrupt 0 enable bit. */
12220#define HSEM_C1IER_ISE19_Pos (19U)
12221#define HSEM_C1IER_ISE19_Msk (0x1UL << HSEM_C1IER_ISE19_Pos) /*!< 0x00080000 */
12222#define HSEM_C1IER_ISE19 HSEM_C1IER_ISE19_Msk /*!<semaphore 19 interrupt 0 enable bit. */
12223#define HSEM_C1IER_ISE20_Pos (20U)
12224#define HSEM_C1IER_ISE20_Msk (0x1UL << HSEM_C1IER_ISE20_Pos) /*!< 0x00100000 */
12225#define HSEM_C1IER_ISE20 HSEM_C1IER_ISE20_Msk /*!<semaphore 20 interrupt 0 enable bit. */
12226#define HSEM_C1IER_ISE21_Pos (21U)
12227#define HSEM_C1IER_ISE21_Msk (0x1UL << HSEM_C1IER_ISE21_Pos) /*!< 0x00200000 */
12228#define HSEM_C1IER_ISE21 HSEM_C1IER_ISE21_Msk /*!<semaphore 21 interrupt 0 enable bit. */
12229#define HSEM_C1IER_ISE22_Pos (22U)
12230#define HSEM_C1IER_ISE22_Msk (0x1UL << HSEM_C1IER_ISE22_Pos) /*!< 0x00400000 */
12231#define HSEM_C1IER_ISE22 HSEM_C1IER_ISE22_Msk /*!<semaphore 22 interrupt 0 enable bit. */
12232#define HSEM_C1IER_ISE23_Pos (23U)
12233#define HSEM_C1IER_ISE23_Msk (0x1UL << HSEM_C1IER_ISE23_Pos) /*!< 0x00800000 */
12234#define HSEM_C1IER_ISE23 HSEM_C1IER_ISE23_Msk /*!<semaphore 23 interrupt 0 enable bit. */
12235#define HSEM_C1IER_ISE24_Pos (24U)
12236#define HSEM_C1IER_ISE24_Msk (0x1UL << HSEM_C1IER_ISE24_Pos) /*!< 0x01000000 */
12237#define HSEM_C1IER_ISE24 HSEM_C1IER_ISE24_Msk /*!<semaphore 24 interrupt 0 enable bit. */
12238#define HSEM_C1IER_ISE25_Pos (25U)
12239#define HSEM_C1IER_ISE25_Msk (0x1UL << HSEM_C1IER_ISE25_Pos) /*!< 0x02000000 */
12240#define HSEM_C1IER_ISE25 HSEM_C1IER_ISE25_Msk /*!<semaphore 25 interrupt 0 enable bit. */
12241#define HSEM_C1IER_ISE26_Pos (26U)
12242#define HSEM_C1IER_ISE26_Msk (0x1UL << HSEM_C1IER_ISE26_Pos) /*!< 0x04000000 */
12243#define HSEM_C1IER_ISE26 HSEM_C1IER_ISE26_Msk /*!<semaphore 26 interrupt 0 enable bit. */
12244#define HSEM_C1IER_ISE27_Pos (27U)
12245#define HSEM_C1IER_ISE27_Msk (0x1UL << HSEM_C1IER_ISE27_Pos) /*!< 0x08000000 */
12246#define HSEM_C1IER_ISE27 HSEM_C1IER_ISE27_Msk /*!<semaphore 27 interrupt 0 enable bit. */
12247#define HSEM_C1IER_ISE28_Pos (28U)
12248#define HSEM_C1IER_ISE28_Msk (0x1UL << HSEM_C1IER_ISE28_Pos) /*!< 0x10000000 */
12249#define HSEM_C1IER_ISE28 HSEM_C1IER_ISE28_Msk /*!<semaphore 28 interrupt 0 enable bit. */
12250#define HSEM_C1IER_ISE29_Pos (29U)
12251#define HSEM_C1IER_ISE29_Msk (0x1UL << HSEM_C1IER_ISE29_Pos) /*!< 0x20000000 */
12252#define HSEM_C1IER_ISE29 HSEM_C1IER_ISE29_Msk /*!<semaphore 29 interrupt 0 enable bit. */
12253#define HSEM_C1IER_ISE30_Pos (30U)
12254#define HSEM_C1IER_ISE30_Msk (0x1UL << HSEM_C1IER_ISE30_Pos) /*!< 0x40000000 */
12255#define HSEM_C1IER_ISE30 HSEM_C1IER_ISE30_Msk /*!<semaphore 30 interrupt 0 enable bit. */
12256#define HSEM_C1IER_ISE31_Pos (31U)
12257#define HSEM_C1IER_ISE31_Msk (0x1UL << HSEM_C1IER_ISE31_Pos) /*!< 0x80000000 */
12258#define HSEM_C1IER_ISE31 HSEM_C1IER_ISE31_Msk /*!<semaphore 31 interrupt 0 enable bit. */
12259
12260/******************** Bit definition for HSEM_C1ICR register *****************/
12261#define HSEM_C1ICR_ISC0_Pos (0U)
12262#define HSEM_C1ICR_ISC0_Msk (0x1UL << HSEM_C1ICR_ISC0_Pos) /*!< 0x00000001 */
12263#define HSEM_C1ICR_ISC0 HSEM_C1ICR_ISC0_Msk /*!<semaphore 0 , interrupt 0 clear bit. */
12264#define HSEM_C1ICR_ISC1_Pos (1U)
12265#define HSEM_C1ICR_ISC1_Msk (0x1UL << HSEM_C1ICR_ISC1_Pos) /*!< 0x00000002 */
12266#define HSEM_C1ICR_ISC1 HSEM_C1ICR_ISC1_Msk /*!<semaphore 1 , interrupt 0 clear bit. */
12267#define HSEM_C1ICR_ISC2_Pos (2U)
12268#define HSEM_C1ICR_ISC2_Msk (0x1UL << HSEM_C1ICR_ISC2_Pos) /*!< 0x00000004 */
12269#define HSEM_C1ICR_ISC2 HSEM_C1ICR_ISC2_Msk /*!<semaphore 2 , interrupt 0 clear bit. */
12270#define HSEM_C1ICR_ISC3_Pos (3U)
12271#define HSEM_C1ICR_ISC3_Msk (0x1UL << HSEM_C1ICR_ISC3_Pos) /*!< 0x00000008 */
12272#define HSEM_C1ICR_ISC3 HSEM_C1ICR_ISC3_Msk /*!<semaphore 3 , interrupt 0 clear bit. */
12273#define HSEM_C1ICR_ISC4_Pos (4U)
12274#define HSEM_C1ICR_ISC4_Msk (0x1UL << HSEM_C1ICR_ISC4_Pos) /*!< 0x00000010 */
12275#define HSEM_C1ICR_ISC4 HSEM_C1ICR_ISC4_Msk /*!<semaphore 4 , interrupt 0 clear bit. */
12276#define HSEM_C1ICR_ISC5_Pos (5U)
12277#define HSEM_C1ICR_ISC5_Msk (0x1UL << HSEM_C1ICR_ISC5_Pos) /*!< 0x00000020 */
12278#define HSEM_C1ICR_ISC5 HSEM_C1ICR_ISC5_Msk /*!<semaphore 5 interrupt 0 clear bit. */
12279#define HSEM_C1ICR_ISC6_Pos (6U)
12280#define HSEM_C1ICR_ISC6_Msk (0x1UL << HSEM_C1ICR_ISC6_Pos) /*!< 0x00000040 */
12281#define HSEM_C1ICR_ISC6 HSEM_C1ICR_ISC6_Msk /*!<semaphore 6 interrupt 0 clear bit. */
12282#define HSEM_C1ICR_ISC7_Pos (7U)
12283#define HSEM_C1ICR_ISC7_Msk (0x1UL << HSEM_C1ICR_ISC7_Pos) /*!< 0x00000080 */
12284#define HSEM_C1ICR_ISC7 HSEM_C1ICR_ISC7_Msk /*!<semaphore 7 interrupt 0 clear bit. */
12285#define HSEM_C1ICR_ISC8_Pos (8U)
12286#define HSEM_C1ICR_ISC8_Msk (0x1UL << HSEM_C1ICR_ISC8_Pos) /*!< 0x00000100 */
12287#define HSEM_C1ICR_ISC8 HSEM_C1ICR_ISC8_Msk /*!<semaphore 8 interrupt 0 clear bit. */
12288#define HSEM_C1ICR_ISC9_Pos (9U)
12289#define HSEM_C1ICR_ISC9_Msk (0x1UL << HSEM_C1ICR_ISC9_Pos) /*!< 0x00000200 */
12290#define HSEM_C1ICR_ISC9 HSEM_C1ICR_ISC9_Msk /*!<semaphore 9 interrupt 0 clear bit. */
12291#define HSEM_C1ICR_ISC10_Pos (10U)
12292#define HSEM_C1ICR_ISC10_Msk (0x1UL << HSEM_C1ICR_ISC10_Pos) /*!< 0x00000400 */
12293#define HSEM_C1ICR_ISC10 HSEM_C1ICR_ISC10_Msk /*!<semaphore 10 interrupt 0 clear bit. */
12294#define HSEM_C1ICR_ISC11_Pos (11U)
12295#define HSEM_C1ICR_ISC11_Msk (0x1UL << HSEM_C1ICR_ISC11_Pos) /*!< 0x00000800 */
12296#define HSEM_C1ICR_ISC11 HSEM_C1ICR_ISC11_Msk /*!<semaphore 11 interrupt 0 clear bit. */
12297#define HSEM_C1ICR_ISC12_Pos (12U)
12298#define HSEM_C1ICR_ISC12_Msk (0x1UL << HSEM_C1ICR_ISC12_Pos) /*!< 0x00001000 */
12299#define HSEM_C1ICR_ISC12 HSEM_C1ICR_ISC12_Msk /*!<semaphore 12 interrupt 0 clear bit. */
12300#define HSEM_C1ICR_ISC13_Pos (13U)
12301#define HSEM_C1ICR_ISC13_Msk (0x1UL << HSEM_C1ICR_ISC13_Pos) /*!< 0x00002000 */
12302#define HSEM_C1ICR_ISC13 HSEM_C1ICR_ISC13_Msk /*!<semaphore 13 interrupt 0 clear bit. */
12303#define HSEM_C1ICR_ISC14_Pos (14U)
12304#define HSEM_C1ICR_ISC14_Msk (0x1UL << HSEM_C1ICR_ISC14_Pos) /*!< 0x00004000 */
12305#define HSEM_C1ICR_ISC14 HSEM_C1ICR_ISC14_Msk /*!<semaphore 14 interrupt 0 clear bit. */
12306#define HSEM_C1ICR_ISC15_Pos (15U)
12307#define HSEM_C1ICR_ISC15_Msk (0x1UL << HSEM_C1ICR_ISC15_Pos) /*!< 0x00008000 */
12308#define HSEM_C1ICR_ISC15 HSEM_C1ICR_ISC15_Msk /*!<semaphore 15 interrupt 0 clear bit. */
12309#define HSEM_C1ICR_ISC16_Pos (16U)
12310#define HSEM_C1ICR_ISC16_Msk (0x1UL << HSEM_C1ICR_ISC16_Pos) /*!< 0x00010000 */
12311#define HSEM_C1ICR_ISC16 HSEM_C1ICR_ISC16_Msk /*!<semaphore 16 interrupt 0 clear bit. */
12312#define HSEM_C1ICR_ISC17_Pos (17U)
12313#define HSEM_C1ICR_ISC17_Msk (0x1UL << HSEM_C1ICR_ISC17_Pos) /*!< 0x00020000 */
12314#define HSEM_C1ICR_ISC17 HSEM_C1ICR_ISC17_Msk /*!<semaphore 17 interrupt 0 clear bit. */
12315#define HSEM_C1ICR_ISC18_Pos (18U)
12316#define HSEM_C1ICR_ISC18_Msk (0x1UL << HSEM_C1ICR_ISC18_Pos) /*!< 0x00040000 */
12317#define HSEM_C1ICR_ISC18 HSEM_C1ICR_ISC18_Msk /*!<semaphore 18 interrupt 0 clear bit. */
12318#define HSEM_C1ICR_ISC19_Pos (19U)
12319#define HSEM_C1ICR_ISC19_Msk (0x1UL << HSEM_C1ICR_ISC19_Pos) /*!< 0x00080000 */
12320#define HSEM_C1ICR_ISC19 HSEM_C1ICR_ISC19_Msk /*!<semaphore 19 interrupt 0 clear bit. */
12321#define HSEM_C1ICR_ISC20_Pos (20U)
12322#define HSEM_C1ICR_ISC20_Msk (0x1UL << HSEM_C1ICR_ISC20_Pos) /*!< 0x00100000 */
12323#define HSEM_C1ICR_ISC20 HSEM_C1ICR_ISC20_Msk /*!<semaphore 20 interrupt 0 clear bit. */
12324#define HSEM_C1ICR_ISC21_Pos (21U)
12325#define HSEM_C1ICR_ISC21_Msk (0x1UL << HSEM_C1ICR_ISC21_Pos) /*!< 0x00200000 */
12326#define HSEM_C1ICR_ISC21 HSEM_C1ICR_ISC21_Msk /*!<semaphore 21 interrupt 0 clear bit. */
12327#define HSEM_C1ICR_ISC22_Pos (22U)
12328#define HSEM_C1ICR_ISC22_Msk (0x1UL << HSEM_C1ICR_ISC22_Pos) /*!< 0x00400000 */
12329#define HSEM_C1ICR_ISC22 HSEM_C1ICR_ISC22_Msk /*!<semaphore 22 interrupt 0 clear bit. */
12330#define HSEM_C1ICR_ISC23_Pos (23U)
12331#define HSEM_C1ICR_ISC23_Msk (0x1UL << HSEM_C1ICR_ISC23_Pos) /*!< 0x00800000 */
12332#define HSEM_C1ICR_ISC23 HSEM_C1ICR_ISC23_Msk /*!<semaphore 23 interrupt 0 clear bit. */
12333#define HSEM_C1ICR_ISC24_Pos (24U)
12334#define HSEM_C1ICR_ISC24_Msk (0x1UL << HSEM_C1ICR_ISC24_Pos) /*!< 0x01000000 */
12335#define HSEM_C1ICR_ISC24 HSEM_C1ICR_ISC24_Msk /*!<semaphore 24 interrupt 0 clear bit. */
12336#define HSEM_C1ICR_ISC25_Pos (25U)
12337#define HSEM_C1ICR_ISC25_Msk (0x1UL << HSEM_C1ICR_ISC25_Pos) /*!< 0x02000000 */
12338#define HSEM_C1ICR_ISC25 HSEM_C1ICR_ISC25_Msk /*!<semaphore 25 interrupt 0 clear bit. */
12339#define HSEM_C1ICR_ISC26_Pos (26U)
12340#define HSEM_C1ICR_ISC26_Msk (0x1UL << HSEM_C1ICR_ISC26_Pos) /*!< 0x04000000 */
12341#define HSEM_C1ICR_ISC26 HSEM_C1ICR_ISC26_Msk /*!<semaphore 26 interrupt 0 clear bit. */
12342#define HSEM_C1ICR_ISC27_Pos (27U)
12343#define HSEM_C1ICR_ISC27_Msk (0x1UL << HSEM_C1ICR_ISC27_Pos) /*!< 0x08000000 */
12344#define HSEM_C1ICR_ISC27 HSEM_C1ICR_ISC27_Msk /*!<semaphore 27 interrupt 0 clear bit. */
12345#define HSEM_C1ICR_ISC28_Pos (28U)
12346#define HSEM_C1ICR_ISC28_Msk (0x1UL << HSEM_C1ICR_ISC28_Pos) /*!< 0x10000000 */
12347#define HSEM_C1ICR_ISC28 HSEM_C1ICR_ISC28_Msk /*!<semaphore 28 interrupt 0 clear bit. */
12348#define HSEM_C1ICR_ISC29_Pos (29U)
12349#define HSEM_C1ICR_ISC29_Msk (0x1UL << HSEM_C1ICR_ISC29_Pos) /*!< 0x20000000 */
12350#define HSEM_C1ICR_ISC29 HSEM_C1ICR_ISC29_Msk /*!<semaphore 29 interrupt 0 clear bit. */
12351#define HSEM_C1ICR_ISC30_Pos (30U)
12352#define HSEM_C1ICR_ISC30_Msk (0x1UL << HSEM_C1ICR_ISC30_Pos) /*!< 0x40000000 */
12353#define HSEM_C1ICR_ISC30 HSEM_C1ICR_ISC30_Msk /*!<semaphore 30 interrupt 0 clear bit. */
12354#define HSEM_C1ICR_ISC31_Pos (31U)
12355#define HSEM_C1ICR_ISC31_Msk (0x1UL << HSEM_C1ICR_ISC31_Pos) /*!< 0x80000000 */
12356#define HSEM_C1ICR_ISC31 HSEM_C1ICR_ISC31_Msk /*!<semaphore 31 interrupt 0 clear bit. */
12357
12358/******************** Bit definition for HSEM_C1ISR register *****************/
12359#define HSEM_C1ISR_ISF0_Pos (0U)
12360#define HSEM_C1ISR_ISF0_Msk (0x1UL << HSEM_C1ISR_ISF0_Pos) /*!< 0x00000001 */
12361#define HSEM_C1ISR_ISF0 HSEM_C1ISR_ISF0_Msk /*!<semaphore 0 interrupt 0 status bit. */
12362#define HSEM_C1ISR_ISF1_Pos (1U)
12363#define HSEM_C1ISR_ISF1_Msk (0x1UL << HSEM_C1ISR_ISF1_Pos) /*!< 0x00000002 */
12364#define HSEM_C1ISR_ISF1 HSEM_C1ISR_ISF1_Msk /*!<semaphore 1 interrupt 0 status bit. */
12365#define HSEM_C1ISR_ISF2_Pos (2U)
12366#define HSEM_C1ISR_ISF2_Msk (0x1UL << HSEM_C1ISR_ISF2_Pos) /*!< 0x00000004 */
12367#define HSEM_C1ISR_ISF2 HSEM_C1ISR_ISF2_Msk /*!<semaphore 2 interrupt 0 status bit. */
12368#define HSEM_C1ISR_ISF3_Pos (3U)
12369#define HSEM_C1ISR_ISF3_Msk (0x1UL << HSEM_C1ISR_ISF3_Pos) /*!< 0x00000008 */
12370#define HSEM_C1ISR_ISF3 HSEM_C1ISR_ISF3_Msk /*!<semaphore 3 interrupt 0 status bit. */
12371#define HSEM_C1ISR_ISF4_Pos (4U)
12372#define HSEM_C1ISR_ISF4_Msk (0x1UL << HSEM_C1ISR_ISF4_Pos) /*!< 0x00000010 */
12373#define HSEM_C1ISR_ISF4 HSEM_C1ISR_ISF4_Msk /*!<semaphore 4 interrupt 0 status bit. */
12374#define HSEM_C1ISR_ISF5_Pos (5U)
12375#define HSEM_C1ISR_ISF5_Msk (0x1UL << HSEM_C1ISR_ISF5_Pos) /*!< 0x00000020 */
12376#define HSEM_C1ISR_ISF5 HSEM_C1ISR_ISF5_Msk /*!<semaphore 5 interrupt 0 status bit. */
12377#define HSEM_C1ISR_ISF6_Pos (6U)
12378#define HSEM_C1ISR_ISF6_Msk (0x1UL << HSEM_C1ISR_ISF6_Pos) /*!< 0x00000040 */
12379#define HSEM_C1ISR_ISF6 HSEM_C1ISR_ISF6_Msk /*!<semaphore 6 interrupt 0 status bit. */
12380#define HSEM_C1ISR_ISF7_Pos (7U)
12381#define HSEM_C1ISR_ISF7_Msk (0x1UL << HSEM_C1ISR_ISF7_Pos) /*!< 0x00000080 */
12382#define HSEM_C1ISR_ISF7 HSEM_C1ISR_ISF7_Msk /*!<semaphore 7 interrupt 0 status bit. */
12383#define HSEM_C1ISR_ISF8_Pos (8U)
12384#define HSEM_C1ISR_ISF8_Msk (0x1UL << HSEM_C1ISR_ISF8_Pos) /*!< 0x00000100 */
12385#define HSEM_C1ISR_ISF8 HSEM_C1ISR_ISF8_Msk /*!<semaphore 8 interrupt 0 status bit. */
12386#define HSEM_C1ISR_ISF9_Pos (9U)
12387#define HSEM_C1ISR_ISF9_Msk (0x1UL << HSEM_C1ISR_ISF9_Pos) /*!< 0x00000200 */
12388#define HSEM_C1ISR_ISF9 HSEM_C1ISR_ISF9_Msk /*!<semaphore 9 interrupt 0 status bit. */
12389#define HSEM_C1ISR_ISF10_Pos (10U)
12390#define HSEM_C1ISR_ISF10_Msk (0x1UL << HSEM_C1ISR_ISF10_Pos) /*!< 0x00000400 */
12391#define HSEM_C1ISR_ISF10 HSEM_C1ISR_ISF10_Msk /*!<semaphore 10 interrupt 0 status bit. */
12392#define HSEM_C1ISR_ISF11_Pos (11U)
12393#define HSEM_C1ISR_ISF11_Msk (0x1UL << HSEM_C1ISR_ISF11_Pos) /*!< 0x00000800 */
12394#define HSEM_C1ISR_ISF11 HSEM_C1ISR_ISF11_Msk /*!<semaphore 11 interrupt 0 status bit. */
12395#define HSEM_C1ISR_ISF12_Pos (12U)
12396#define HSEM_C1ISR_ISF12_Msk (0x1UL << HSEM_C1ISR_ISF12_Pos) /*!< 0x00001000 */
12397#define HSEM_C1ISR_ISF12 HSEM_C1ISR_ISF12_Msk /*!<semaphore 12 interrupt 0 status bit. */
12398#define HSEM_C1ISR_ISF13_Pos (13U)
12399#define HSEM_C1ISR_ISF13_Msk (0x1UL << HSEM_C1ISR_ISF13_Pos) /*!< 0x00002000 */
12400#define HSEM_C1ISR_ISF13 HSEM_C1ISR_ISF13_Msk /*!<semaphore 13 interrupt 0 status bit. */
12401#define HSEM_C1ISR_ISF14_Pos (14U)
12402#define HSEM_C1ISR_ISF14_Msk (0x1UL << HSEM_C1ISR_ISF14_Pos) /*!< 0x00004000 */
12403#define HSEM_C1ISR_ISF14 HSEM_C1ISR_ISF14_Msk /*!<semaphore 14 interrupt 0 status bit. */
12404#define HSEM_C1ISR_ISF15_Pos (15U)
12405#define HSEM_C1ISR_ISF15_Msk (0x1UL << HSEM_C1ISR_ISF15_Pos) /*!< 0x00008000 */
12406#define HSEM_C1ISR_ISF15 HSEM_C1ISR_ISF15_Msk /*!<semaphore 15 interrupt 0 status bit. */
12407#define HSEM_C1ISR_ISF16_Pos (16U)
12408#define HSEM_C1ISR_ISF16_Msk (0x1UL << HSEM_C1ISR_ISF16_Pos) /*!< 0x00010000 */
12409#define HSEM_C1ISR_ISF16 HSEM_C1ISR_ISF16_Msk /*!<semaphore 16 interrupt 0 status bit. */
12410#define HSEM_C1ISR_ISF17_Pos (17U)
12411#define HSEM_C1ISR_ISF17_Msk (0x1UL << HSEM_C1ISR_ISF17_Pos) /*!< 0x00020000 */
12412#define HSEM_C1ISR_ISF17 HSEM_C1ISR_ISF17_Msk /*!<semaphore 17 interrupt 0 status bit. */
12413#define HSEM_C1ISR_ISF18_Pos (18U)
12414#define HSEM_C1ISR_ISF18_Msk (0x1UL << HSEM_C1ISR_ISF18_Pos) /*!< 0x00040000 */
12415#define HSEM_C1ISR_ISF18 HSEM_C1ISR_ISF18_Msk /*!<semaphore 18 interrupt 0 status bit. */
12416#define HSEM_C1ISR_ISF19_Pos (19U)
12417#define HSEM_C1ISR_ISF19_Msk (0x1UL << HSEM_C1ISR_ISF19_Pos) /*!< 0x00080000 */
12418#define HSEM_C1ISR_ISF19 HSEM_C1ISR_ISF19_Msk /*!<semaphore 19 interrupt 0 status bit. */
12419#define HSEM_C1ISR_ISF20_Pos (20U)
12420#define HSEM_C1ISR_ISF20_Msk (0x1UL << HSEM_C1ISR_ISF20_Pos) /*!< 0x00100000 */
12421#define HSEM_C1ISR_ISF20 HSEM_C1ISR_ISF20_Msk /*!<semaphore 20 interrupt 0 status bit. */
12422#define HSEM_C1ISR_ISF21_Pos (21U)
12423#define HSEM_C1ISR_ISF21_Msk (0x1UL << HSEM_C1ISR_ISF21_Pos) /*!< 0x00200000 */
12424#define HSEM_C1ISR_ISF21 HSEM_C1ISR_ISF21_Msk /*!<semaphore 21 interrupt 0 status bit. */
12425#define HSEM_C1ISR_ISF22_Pos (22U)
12426#define HSEM_C1ISR_ISF22_Msk (0x1UL << HSEM_C1ISR_ISF22_Pos) /*!< 0x00400000 */
12427#define HSEM_C1ISR_ISF22 HSEM_C1ISR_ISF22_Msk /*!<semaphore 22 interrupt 0 status bit. */
12428#define HSEM_C1ISR_ISF23_Pos (23U)
12429#define HSEM_C1ISR_ISF23_Msk (0x1UL << HSEM_C1ISR_ISF23_Pos) /*!< 0x00800000 */
12430#define HSEM_C1ISR_ISF23 HSEM_C1ISR_ISF23_Msk /*!<semaphore 23 interrupt 0 status bit. */
12431#define HSEM_C1ISR_ISF24_Pos (24U)
12432#define HSEM_C1ISR_ISF24_Msk (0x1UL << HSEM_C1ISR_ISF24_Pos) /*!< 0x01000000 */
12433#define HSEM_C1ISR_ISF24 HSEM_C1ISR_ISF24_Msk /*!<semaphore 24 interrupt 0 status bit. */
12434#define HSEM_C1ISR_ISF25_Pos (25U)
12435#define HSEM_C1ISR_ISF25_Msk (0x1UL << HSEM_C1ISR_ISF25_Pos) /*!< 0x02000000 */
12436#define HSEM_C1ISR_ISF25 HSEM_C1ISR_ISF25_Msk /*!<semaphore 25 interrupt 0 status bit. */
12437#define HSEM_C1ISR_ISF26_Pos (26U)
12438#define HSEM_C1ISR_ISF26_Msk (0x1UL << HSEM_C1ISR_ISF26_Pos) /*!< 0x04000000 */
12439#define HSEM_C1ISR_ISF26 HSEM_C1ISR_ISF26_Msk /*!<semaphore 26 interrupt 0 status bit. */
12440#define HSEM_C1ISR_ISF27_Pos (27U)
12441#define HSEM_C1ISR_ISF27_Msk (0x1UL << HSEM_C1ISR_ISF27_Pos) /*!< 0x08000000 */
12442#define HSEM_C1ISR_ISF27 HSEM_C1ISR_ISF27_Msk /*!<semaphore 27 interrupt 0 status bit. */
12443#define HSEM_C1ISR_ISF28_Pos (28U)
12444#define HSEM_C1ISR_ISF28_Msk (0x1UL << HSEM_C1ISR_ISF28_Pos) /*!< 0x10000000 */
12445#define HSEM_C1ISR_ISF28 HSEM_C1ISR_ISF28_Msk /*!<semaphore 28 interrupt 0 status bit. */
12446#define HSEM_C1ISR_ISF29_Pos (29U)
12447#define HSEM_C1ISR_ISF29_Msk (0x1UL << HSEM_C1ISR_ISF29_Pos) /*!< 0x20000000 */
12448#define HSEM_C1ISR_ISF29 HSEM_C1ISR_ISF29_Msk /*!<semaphore 29 interrupt 0 status bit. */
12449#define HSEM_C1ISR_ISF30_Pos (30U)
12450#define HSEM_C1ISR_ISF30_Msk (0x1UL << HSEM_C1ISR_ISF30_Pos) /*!< 0x40000000 */
12451#define HSEM_C1ISR_ISF30 HSEM_C1ISR_ISF30_Msk /*!<semaphore 30 interrupt 0 status bit. */
12452#define HSEM_C1ISR_ISF31_Pos (31U)
12453#define HSEM_C1ISR_ISF31_Msk (0x1UL << HSEM_C1ISR_ISF31_Pos) /*!< 0x80000000 */
12454#define HSEM_C1ISR_ISF31 HSEM_C1ISR_ISF31_Msk /*!<semaphore 31 interrupt 0 status bit. */
12455
12456/******************** Bit definition for HSEM_C1MISR register *****************/
12457#define HSEM_C1MISR_MISF0_Pos (0U)
12458#define HSEM_C1MISR_MISF0_Msk (0x1UL << HSEM_C1MISR_MISF0_Pos) /*!< 0x00000001 */
12459#define HSEM_C1MISR_MISF0 HSEM_C1MISR_MISF0_Msk /*!<semaphore 0 interrupt 0 masked status bit. */
12460#define HSEM_C1MISR_MISF1_Pos (1U)
12461#define HSEM_C1MISR_MISF1_Msk (0x1UL << HSEM_C1MISR_MISF1_Pos) /*!< 0x00000002 */
12462#define HSEM_C1MISR_MISF1 HSEM_C1MISR_MISF1_Msk /*!<semaphore 1 interrupt 0 masked status bit. */
12463#define HSEM_C1MISR_MISF2_Pos (2U)
12464#define HSEM_C1MISR_MISF2_Msk (0x1UL << HSEM_C1MISR_MISF2_Pos) /*!< 0x00000004 */
12465#define HSEM_C1MISR_MISF2 HSEM_C1MISR_MISF2_Msk /*!<semaphore 2 interrupt 0 masked status bit. */
12466#define HSEM_C1MISR_MISF3_Pos (3U)
12467#define HSEM_C1MISR_MISF3_Msk (0x1UL << HSEM_C1MISR_MISF3_Pos) /*!< 0x00000008 */
12468#define HSEM_C1MISR_MISF3 HSEM_C1MISR_MISF3_Msk /*!<semaphore 3 interrupt 0 masked status bit. */
12469#define HSEM_C1MISR_MISF4_Pos (4U)
12470#define HSEM_C1MISR_MISF4_Msk (0x1UL << HSEM_C1MISR_MISF4_Pos) /*!< 0x00000010 */
12471#define HSEM_C1MISR_MISF4 HSEM_C1MISR_MISF4_Msk /*!<semaphore 4 interrupt 0 masked status bit. */
12472#define HSEM_C1MISR_MISF5_Pos (5U)
12473#define HSEM_C1MISR_MISF5_Msk (0x1UL << HSEM_C1MISR_MISF5_Pos) /*!< 0x00000020 */
12474#define HSEM_C1MISR_MISF5 HSEM_C1MISR_MISF5_Msk /*!<semaphore 5 interrupt 0 masked status bit. */
12475#define HSEM_C1MISR_MISF6_Pos (6U)
12476#define HSEM_C1MISR_MISF6_Msk (0x1UL << HSEM_C1MISR_MISF6_Pos) /*!< 0x00000040 */
12477#define HSEM_C1MISR_MISF6 HSEM_C1MISR_MISF6_Msk /*!<semaphore 6 interrupt 0 masked status bit. */
12478#define HSEM_C1MISR_MISF7_Pos (7U)
12479#define HSEM_C1MISR_MISF7_Msk (0x1UL << HSEM_C1MISR_MISF7_Pos) /*!< 0x00000080 */
12480#define HSEM_C1MISR_MISF7 HSEM_C1MISR_MISF7_Msk /*!<semaphore 7 interrupt 0 masked status bit. */
12481#define HSEM_C1MISR_MISF8_Pos (8U)
12482#define HSEM_C1MISR_MISF8_Msk (0x1UL << HSEM_C1MISR_MISF8_Pos) /*!< 0x00000100 */
12483#define HSEM_C1MISR_MISF8 HSEM_C1MISR_MISF8_Msk /*!<semaphore 8 interrupt 0 masked status bit. */
12484#define HSEM_C1MISR_MISF9_Pos (9U)
12485#define HSEM_C1MISR_MISF9_Msk (0x1UL << HSEM_C1MISR_MISF9_Pos) /*!< 0x00000200 */
12486#define HSEM_C1MISR_MISF9 HSEM_C1MISR_MISF9_Msk /*!<semaphore 9 interrupt 0 masked status bit. */
12487#define HSEM_C1MISR_MISF10_Pos (10U)
12488#define HSEM_C1MISR_MISF10_Msk (0x1UL << HSEM_C1MISR_MISF10_Pos) /*!< 0x00000400 */
12489#define HSEM_C1MISR_MISF10 HSEM_C1MISR_MISF10_Msk /*!<semaphore 10 interrupt 0 masked status bit. */
12490#define HSEM_C1MISR_MISF11_Pos (11U)
12491#define HSEM_C1MISR_MISF11_Msk (0x1UL << HSEM_C1MISR_MISF11_Pos) /*!< 0x00000800 */
12492#define HSEM_C1MISR_MISF11 HSEM_C1MISR_MISF11_Msk /*!<semaphore 11 interrupt 0 masked status bit. */
12493#define HSEM_C1MISR_MISF12_Pos (12U)
12494#define HSEM_C1MISR_MISF12_Msk (0x1UL << HSEM_C1MISR_MISF12_Pos) /*!< 0x00001000 */
12495#define HSEM_C1MISR_MISF12 HSEM_C1MISR_MISF12_Msk /*!<semaphore 12 interrupt 0 masked status bit. */
12496#define HSEM_C1MISR_MISF13_Pos (13U)
12497#define HSEM_C1MISR_MISF13_Msk (0x1UL << HSEM_C1MISR_MISF13_Pos) /*!< 0x00002000 */
12498#define HSEM_C1MISR_MISF13 HSEM_C1MISR_MISF13_Msk /*!<semaphore 13 interrupt 0 masked status bit. */
12499#define HSEM_C1MISR_MISF14_Pos (14U)
12500#define HSEM_C1MISR_MISF14_Msk (0x1UL << HSEM_C1MISR_MISF14_Pos) /*!< 0x00004000 */
12501#define HSEM_C1MISR_MISF14 HSEM_C1MISR_MISF14_Msk /*!<semaphore 14 interrupt 0 masked status bit. */
12502#define HSEM_C1MISR_MISF15_Pos (15U)
12503#define HSEM_C1MISR_MISF15_Msk (0x1UL << HSEM_C1MISR_MISF15_Pos) /*!< 0x00008000 */
12504#define HSEM_C1MISR_MISF15 HSEM_C1MISR_MISF15_Msk /*!<semaphore 15 interrupt 0 masked status bit. */
12505#define HSEM_C1MISR_MISF16_Pos (16U)
12506#define HSEM_C1MISR_MISF16_Msk (0x1UL << HSEM_C1MISR_MISF16_Pos) /*!< 0x00010000 */
12507#define HSEM_C1MISR_MISF16 HSEM_C1MISR_MISF16_Msk /*!<semaphore 16 interrupt 0 masked status bit. */
12508#define HSEM_C1MISR_MISF17_Pos (17U)
12509#define HSEM_C1MISR_MISF17_Msk (0x1UL << HSEM_C1MISR_MISF17_Pos) /*!< 0x00020000 */
12510#define HSEM_C1MISR_MISF17 HSEM_C1MISR_MISF17_Msk /*!<semaphore 17 interrupt 0 masked status bit. */
12511#define HSEM_C1MISR_MISF18_Pos (18U)
12512#define HSEM_C1MISR_MISF18_Msk (0x1UL << HSEM_C1MISR_MISF18_Pos) /*!< 0x00040000 */
12513#define HSEM_C1MISR_MISF18 HSEM_C1MISR_MISF18_Msk /*!<semaphore 18 interrupt 0 masked status bit. */
12514#define HSEM_C1MISR_MISF19_Pos (19U)
12515#define HSEM_C1MISR_MISF19_Msk (0x1UL << HSEM_C1MISR_MISF19_Pos) /*!< 0x00080000 */
12516#define HSEM_C1MISR_MISF19 HSEM_C1MISR_MISF19_Msk /*!<semaphore 19 interrupt 0 masked status bit. */
12517#define HSEM_C1MISR_MISF20_Pos (20U)
12518#define HSEM_C1MISR_MISF20_Msk (0x1UL << HSEM_C1MISR_MISF20_Pos) /*!< 0x00100000 */
12519#define HSEM_C1MISR_MISF20 HSEM_C1MISR_MISF20_Msk /*!<semaphore 20 interrupt 0 masked status bit. */
12520#define HSEM_C1MISR_MISF21_Pos (21U)
12521#define HSEM_C1MISR_MISF21_Msk (0x1UL << HSEM_C1MISR_MISF21_Pos) /*!< 0x00200000 */
12522#define HSEM_C1MISR_MISF21 HSEM_C1MISR_MISF21_Msk /*!<semaphore 21 interrupt 0 masked status bit. */
12523#define HSEM_C1MISR_MISF22_Pos (22U)
12524#define HSEM_C1MISR_MISF22_Msk (0x1UL << HSEM_C1MISR_MISF22_Pos) /*!< 0x00400000 */
12525#define HSEM_C1MISR_MISF22 HSEM_C1MISR_MISF22_Msk /*!<semaphore 22 interrupt 0 masked status bit. */
12526#define HSEM_C1MISR_MISF23_Pos (23U)
12527#define HSEM_C1MISR_MISF23_Msk (0x1UL << HSEM_C1MISR_MISF23_Pos) /*!< 0x00800000 */
12528#define HSEM_C1MISR_MISF23 HSEM_C1MISR_MISF23_Msk /*!<semaphore 23 interrupt 0 masked status bit. */
12529#define HSEM_C1MISR_MISF24_Pos (24U)
12530#define HSEM_C1MISR_MISF24_Msk (0x1UL << HSEM_C1MISR_MISF24_Pos) /*!< 0x01000000 */
12531#define HSEM_C1MISR_MISF24 HSEM_C1MISR_MISF24_Msk /*!<semaphore 24 interrupt 0 masked status bit. */
12532#define HSEM_C1MISR_MISF25_Pos (25U)
12533#define HSEM_C1MISR_MISF25_Msk (0x1UL << HSEM_C1MISR_MISF25_Pos) /*!< 0x02000000 */
12534#define HSEM_C1MISR_MISF25 HSEM_C1MISR_MISF25_Msk /*!<semaphore 25 interrupt 0 masked status bit. */
12535#define HSEM_C1MISR_MISF26_Pos (26U)
12536#define HSEM_C1MISR_MISF26_Msk (0x1UL << HSEM_C1MISR_MISF26_Pos) /*!< 0x04000000 */
12537#define HSEM_C1MISR_MISF26 HSEM_C1MISR_MISF26_Msk /*!<semaphore 26 interrupt 0 masked status bit. */
12538#define HSEM_C1MISR_MISF27_Pos (27U)
12539#define HSEM_C1MISR_MISF27_Msk (0x1UL << HSEM_C1MISR_MISF27_Pos) /*!< 0x08000000 */
12540#define HSEM_C1MISR_MISF27 HSEM_C1MISR_MISF27_Msk /*!<semaphore 27 interrupt 0 masked status bit. */
12541#define HSEM_C1MISR_MISF28_Pos (28U)
12542#define HSEM_C1MISR_MISF28_Msk (0x1UL << HSEM_C1MISR_MISF28_Pos) /*!< 0x10000000 */
12543#define HSEM_C1MISR_MISF28 HSEM_C1MISR_MISF28_Msk /*!<semaphore 28 interrupt 0 masked status bit. */
12544#define HSEM_C1MISR_MISF29_Pos (29U)
12545#define HSEM_C1MISR_MISF29_Msk (0x1UL << HSEM_C1MISR_MISF29_Pos) /*!< 0x20000000 */
12546#define HSEM_C1MISR_MISF29 HSEM_C1MISR_MISF29_Msk /*!<semaphore 29 interrupt 0 masked status bit. */
12547#define HSEM_C1MISR_MISF30_Pos (30U)
12548#define HSEM_C1MISR_MISF30_Msk (0x1UL << HSEM_C1MISR_MISF30_Pos) /*!< 0x40000000 */
12549#define HSEM_C1MISR_MISF30 HSEM_C1MISR_MISF30_Msk /*!<semaphore 30 interrupt 0 masked status bit. */
12550#define HSEM_C1MISR_MISF31_Pos (31U)
12551#define HSEM_C1MISR_MISF31_Msk (0x1UL << HSEM_C1MISR_MISF31_Pos) /*!< 0x80000000 */
12552#define HSEM_C1MISR_MISF31 HSEM_C1MISR_MISF31_Msk /*!<semaphore 31 interrupt 0 masked status bit. */
12553
12554/******************** Bit definition for HSEM_CR register *****************/
12555#define HSEM_CR_COREID_Pos (8U)
12556#define HSEM_CR_COREID_Msk (0xFFUL << HSEM_CR_COREID_Pos) /*!< 0x0000FF00 */
12557#define HSEM_CR_COREID HSEM_CR_COREID_Msk /*!<CoreID of semaphores to be cleared. */
12558#define HSEM_CR_KEY_Pos (16U)
12559#define HSEM_CR_KEY_Msk (0xFFFFUL << HSEM_CR_KEY_Pos) /*!< 0xFFFF0000 */
12560#define HSEM_CR_KEY HSEM_CR_KEY_Msk /*!<semaphores clear key. */
12561
12562/******************** Bit definition for HSEM_KEYR register *****************/
12563#define HSEM_KEYR_KEY_Pos (16U)
12564#define HSEM_KEYR_KEY_Msk (0xFFFFUL << HSEM_KEYR_KEY_Pos) /*!< 0xFFFF0000 */
12565#define HSEM_KEYR_KEY HSEM_KEYR_KEY_Msk /*!<semaphores clear key. */
12566
12567/******************************************************************************/
12568/* */
12569/* Inter-integrated Circuit Interface (I2C) */
12570/* */
12571/******************************************************************************/
12572/******************* Bit definition for I2C_CR1 register *******************/
12573#define I2C_CR1_PE_Pos (0U)
12574#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
12575#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
12576#define I2C_CR1_TXIE_Pos (1U)
12577#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
12578#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
12579#define I2C_CR1_RXIE_Pos (2U)
12580#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
12581#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
12582#define I2C_CR1_ADDRIE_Pos (3U)
12583#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
12584#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
12585#define I2C_CR1_NACKIE_Pos (4U)
12586#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
12587#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
12588#define I2C_CR1_STOPIE_Pos (5U)
12589#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
12590#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
12591#define I2C_CR1_TCIE_Pos (6U)
12592#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
12593#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
12594#define I2C_CR1_ERRIE_Pos (7U)
12595#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
12596#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
12597#define I2C_CR1_DNF_Pos (8U)
12598#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
12599#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
12600#define I2C_CR1_ANFOFF_Pos (12U)
12601#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
12602#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
12603#define I2C_CR1_TXDMAEN_Pos (14U)
12604#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
12605#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
12606#define I2C_CR1_RXDMAEN_Pos (15U)
12607#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
12608#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
12609#define I2C_CR1_SBC_Pos (16U)
12610#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
12611#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
12612#define I2C_CR1_NOSTRETCH_Pos (17U)
12613#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
12614#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
12615#define I2C_CR1_WUPEN_Pos (18U)
12616#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
12617#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
12618#define I2C_CR1_GCEN_Pos (19U)
12619#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
12620#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
12621#define I2C_CR1_SMBHEN_Pos (20U)
12622#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
12623#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
12624#define I2C_CR1_SMBDEN_Pos (21U)
12625#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
12626#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
12627#define I2C_CR1_ALERTEN_Pos (22U)
12628#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
12629#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
12630#define I2C_CR1_PECEN_Pos (23U)
12631#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
12632#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
12633
12634/****************** Bit definition for I2C_CR2 register ********************/
12635#define I2C_CR2_SADD_Pos (0U)
12636#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
12637#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
12638#define I2C_CR2_RD_WRN_Pos (10U)
12639#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
12640#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
12641#define I2C_CR2_ADD10_Pos (11U)
12642#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
12643#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
12644#define I2C_CR2_HEAD10R_Pos (12U)
12645#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
12646#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
12647#define I2C_CR2_START_Pos (13U)
12648#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
12649#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
12650#define I2C_CR2_STOP_Pos (14U)
12651#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
12652#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
12653#define I2C_CR2_NACK_Pos (15U)
12654#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
12655#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
12656#define I2C_CR2_NBYTES_Pos (16U)
12657#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
12658#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
12659#define I2C_CR2_RELOAD_Pos (24U)
12660#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
12661#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
12662#define I2C_CR2_AUTOEND_Pos (25U)
12663#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
12664#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
12665#define I2C_CR2_PECBYTE_Pos (26U)
12666#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
12667#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
12668
12669/******************* Bit definition for I2C_OAR1 register ******************/
12670#define I2C_OAR1_OA1_Pos (0U)
12671#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
12672#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
12673#define I2C_OAR1_OA1MODE_Pos (10U)
12674#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
12675#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
12676#define I2C_OAR1_OA1EN_Pos (15U)
12677#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
12678#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
12679
12680/******************* Bit definition for I2C_OAR2 register ******************/
12681#define I2C_OAR2_OA2_Pos (1U)
12682#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
12683#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
12684#define I2C_OAR2_OA2MSK_Pos (8U)
12685#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
12686#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
12687#define I2C_OAR2_OA2NOMASK 0x00000000UL /*!< No mask */
12688#define I2C_OAR2_OA2MASK01_Pos (8U)
12689#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
12690#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
12691#define I2C_OAR2_OA2MASK02_Pos (9U)
12692#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
12693#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
12694#define I2C_OAR2_OA2MASK03_Pos (8U)
12695#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
12696#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
12697#define I2C_OAR2_OA2MASK04_Pos (10U)
12698#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
12699#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
12700#define I2C_OAR2_OA2MASK05_Pos (8U)
12701#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
12702#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
12703#define I2C_OAR2_OA2MASK06_Pos (9U)
12704#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
12705#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
12706#define I2C_OAR2_OA2MASK07_Pos (8U)
12707#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
12708#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
12709#define I2C_OAR2_OA2EN_Pos (15U)
12710#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
12711#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
12712
12713/******************* Bit definition for I2C_TIMINGR register *******************/
12714#define I2C_TIMINGR_SCLL_Pos (0U)
12715#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
12716#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
12717#define I2C_TIMINGR_SCLH_Pos (8U)
12718#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
12719#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
12720#define I2C_TIMINGR_SDADEL_Pos (16U)
12721#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
12722#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
12723#define I2C_TIMINGR_SCLDEL_Pos (20U)
12724#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
12725#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
12726#define I2C_TIMINGR_PRESC_Pos (28U)
12727#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
12728#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
12729
12730/******************* Bit definition for I2C_TIMEOUTR register *******************/
12731#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
12732#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
12733#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
12734#define I2C_TIMEOUTR_TIDLE_Pos (12U)
12735#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
12736#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
12737#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
12738#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
12739#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
12740#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
12741#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
12742#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
12743#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
12744#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
12745#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
12746
12747/****************** Bit definition for I2C_ISR register *********************/
12748#define I2C_ISR_TXE_Pos (0U)
12749#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
12750#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
12751#define I2C_ISR_TXIS_Pos (1U)
12752#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
12753#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
12754#define I2C_ISR_RXNE_Pos (2U)
12755#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
12756#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
12757#define I2C_ISR_ADDR_Pos (3U)
12758#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
12759#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
12760#define I2C_ISR_NACKF_Pos (4U)
12761#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
12762#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
12763#define I2C_ISR_STOPF_Pos (5U)
12764#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
12765#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
12766#define I2C_ISR_TC_Pos (6U)
12767#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
12768#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
12769#define I2C_ISR_TCR_Pos (7U)
12770#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
12771#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
12772#define I2C_ISR_BERR_Pos (8U)
12773#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
12774#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
12775#define I2C_ISR_ARLO_Pos (9U)
12776#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
12777#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
12778#define I2C_ISR_OVR_Pos (10U)
12779#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
12780#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
12781#define I2C_ISR_PECERR_Pos (11U)
12782#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
12783#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
12784#define I2C_ISR_TIMEOUT_Pos (12U)
12785#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
12786#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
12787#define I2C_ISR_ALERT_Pos (13U)
12788#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
12789#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
12790#define I2C_ISR_BUSY_Pos (15U)
12791#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
12792#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
12793#define I2C_ISR_DIR_Pos (16U)
12794#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
12795#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
12796#define I2C_ISR_ADDCODE_Pos (17U)
12797#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
12798#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
12799
12800/****************** Bit definition for I2C_ICR register *********************/
12801#define I2C_ICR_ADDRCF_Pos (3U)
12802#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
12803#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
12804#define I2C_ICR_NACKCF_Pos (4U)
12805#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
12806#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
12807#define I2C_ICR_STOPCF_Pos (5U)
12808#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
12809#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
12810#define I2C_ICR_BERRCF_Pos (8U)
12811#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
12812#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
12813#define I2C_ICR_ARLOCF_Pos (9U)
12814#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
12815#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
12816#define I2C_ICR_OVRCF_Pos (10U)
12817#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
12818#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
12819#define I2C_ICR_PECCF_Pos (11U)
12820#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
12821#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
12822#define I2C_ICR_TIMOUTCF_Pos (12U)
12823#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
12824#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
12825#define I2C_ICR_ALERTCF_Pos (13U)
12826#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
12827#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
12828
12829/****************** Bit definition for I2C_PECR register *********************/
12830#define I2C_PECR_PEC_Pos (0U)
12831#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
12832#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
12833
12834/****************** Bit definition for I2C_RXDR register *********************/
12835#define I2C_RXDR_RXDATA_Pos (0U)
12836#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
12837#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
12838
12839/****************** Bit definition for I2C_TXDR register *********************/
12840#define I2C_TXDR_TXDATA_Pos (0U)
12841#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
12842#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
12843
12844/******************************************************************************/
12845/* */
12846/* Independent WATCHDOG */
12847/* */
12848/******************************************************************************/
12849/******************* Bit definition for IWDG_KR register ********************/
12850#define IWDG_KR_KEY_Pos (0U)
12851#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
12852#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
12853
12854/******************* Bit definition for IWDG_PR register ********************/
12855#define IWDG_PR_PR_Pos (0U)
12856#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
12857#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
12858#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
12859#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
12860#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
12861
12862/******************* Bit definition for IWDG_RLR register *******************/
12863#define IWDG_RLR_RL_Pos (0U)
12864#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
12865#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
12866
12867/******************* Bit definition for IWDG_SR register ********************/
12868#define IWDG_SR_PVU_Pos (0U)
12869#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
12870#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
12871#define IWDG_SR_RVU_Pos (1U)
12872#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
12873#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
12874#define IWDG_SR_WVU_Pos (2U)
12875#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
12876#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
12877
12878/******************* Bit definition for IWDG_KR register ********************/
12879#define IWDG_WINR_WIN_Pos (0U)
12880#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
12881#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
12882
12883/******************************************************************************/
12884/* */
12885/* JPEG Encoder/Decoder */
12886/* */
12887/******************************************************************************/
12888/******************** Bit definition for CONFR0 register ********************/
12889#define JPEG_CONFR0_START_Pos (0U)
12890#define JPEG_CONFR0_START_Msk (0x1UL << JPEG_CONFR0_START_Pos) /*!< 0x00000001 */
12891#define JPEG_CONFR0_START JPEG_CONFR0_START_Msk /*!<Start/Stop bit */
12892
12893/******************** Bit definition for CONFR1 register ********************/
12894#define JPEG_CONFR1_NF_Pos (0U)
12895#define JPEG_CONFR1_NF_Msk (0x3UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000003 */
12896#define JPEG_CONFR1_NF JPEG_CONFR1_NF_Msk /*!<Number of color components */
12897#define JPEG_CONFR1_NF_0 (0x1UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000001 */
12898#define JPEG_CONFR1_NF_1 (0x2UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000002 */
12899#define JPEG_CONFR1_DE_Pos (3U)
12900#define JPEG_CONFR1_DE_Msk (0x1UL << JPEG_CONFR1_DE_Pos) /*!< 0x00000008 */
12901#define JPEG_CONFR1_DE JPEG_CONFR1_DE_Msk /*!<Decoding Enable */
12902#define JPEG_CONFR1_COLORSPACE_Pos (4U)
12903#define JPEG_CONFR1_COLORSPACE_Msk (0x3UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000030 */
12904#define JPEG_CONFR1_COLORSPACE JPEG_CONFR1_COLORSPACE_Msk /*!<Color Space */
12905#define JPEG_CONFR1_COLORSPACE_0 (0x1UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000010 */
12906#define JPEG_CONFR1_COLORSPACE_1 (0x2UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000020 */
12907#define JPEG_CONFR1_NS_Pos (6U)
12908#define JPEG_CONFR1_NS_Msk (0x3UL << JPEG_CONFR1_NS_Pos) /*!< 0x000000C0 */
12909#define JPEG_CONFR1_NS JPEG_CONFR1_NS_Msk /*!<Number of components for Scan */
12910#define JPEG_CONFR1_NS_0 (0x1UL << JPEG_CONFR1_NS_Pos) /*!< 0x00000040 */
12911#define JPEG_CONFR1_NS_1 (0x2UL << JPEG_CONFR1_NS_Pos) /*!< 0x00000080 */
12912#define JPEG_CONFR1_HDR_Pos (8U)
12913#define JPEG_CONFR1_HDR_Msk (0x1UL << JPEG_CONFR1_HDR_Pos) /*!< 0x00000100 */
12914#define JPEG_CONFR1_HDR JPEG_CONFR1_HDR_Msk /*!<Header Processing On/Off */
12915#define JPEG_CONFR1_YSIZE_Pos (16U)
12916#define JPEG_CONFR1_YSIZE_Msk (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos) /*!< 0xFFFF0000 */
12917#define JPEG_CONFR1_YSIZE JPEG_CONFR1_YSIZE_Msk /*!<Number of lines in source image */
12918
12919/******************** Bit definition for CONFR2 register ********************/
12920#define JPEG_CONFR2_NMCU_Pos (0U)
12921#define JPEG_CONFR2_NMCU_Msk (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos) /*!< 0x03FFFFFF */
12922#define JPEG_CONFR2_NMCU JPEG_CONFR2_NMCU_Msk /*!<Number of MCU units minus 1 to encode */
12923
12924/******************** Bit definition for CONFR3 register ********************/
12925#define JPEG_CONFR3_XSIZE_Pos (16U)
12926#define JPEG_CONFR3_XSIZE_Msk (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos) /*!< 0xFFFF0000 */
12927#define JPEG_CONFR3_XSIZE JPEG_CONFR3_XSIZE_Msk /*!<Number of pixels per line */
12928
12929/******************** Bit definition for CONFR4 register ********************/
12930#define JPEG_CONFR4_HD_Pos (0U)
12931#define JPEG_CONFR4_HD_Msk (0x1UL << JPEG_CONFR4_HD_Pos) /*!< 0x00000001 */
12932#define JPEG_CONFR4_HD JPEG_CONFR4_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
12933#define JPEG_CONFR4_HA_Pos (1U)
12934#define JPEG_CONFR4_HA_Msk (0x1UL << JPEG_CONFR4_HA_Pos) /*!< 0x00000002 */
12935#define JPEG_CONFR4_HA JPEG_CONFR4_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
12936#define JPEG_CONFR4_QT_Pos (2U)
12937#define JPEG_CONFR4_QT_Msk (0x3UL << JPEG_CONFR4_QT_Pos) /*!< 0x0000000C */
12938#define JPEG_CONFR4_QT JPEG_CONFR4_QT_Msk /*!<Selects quantization table associated with a color component */
12939#define JPEG_CONFR4_QT_0 (0x1UL << JPEG_CONFR4_QT_Pos) /*!< 0x00000004 */
12940#define JPEG_CONFR4_QT_1 (0x2UL << JPEG_CONFR4_QT_Pos) /*!< 0x00000008 */
12941#define JPEG_CONFR4_NB_Pos (4U)
12942#define JPEG_CONFR4_NB_Msk (0xFUL << JPEG_CONFR4_NB_Pos) /*!< 0x000000F0 */
12943#define JPEG_CONFR4_NB JPEG_CONFR4_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
12944#define JPEG_CONFR4_NB_0 (0x1UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000010 */
12945#define JPEG_CONFR4_NB_1 (0x2UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000020 */
12946#define JPEG_CONFR4_NB_2 (0x4UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000040 */
12947#define JPEG_CONFR4_NB_3 (0x8UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000080 */
12948#define JPEG_CONFR4_VSF_Pos (8U)
12949#define JPEG_CONFR4_VSF_Msk (0xFUL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000F00 */
12950#define JPEG_CONFR4_VSF JPEG_CONFR4_VSF_Msk /*!<Vertical sampling factor for component 1 */
12951#define JPEG_CONFR4_VSF_0 (0x1UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000100 */
12952#define JPEG_CONFR4_VSF_1 (0x2UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000200 */
12953#define JPEG_CONFR4_VSF_2 (0x4UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000400 */
12954#define JPEG_CONFR4_VSF_3 (0x8UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000800 */
12955#define JPEG_CONFR4_HSF_Pos (12U)
12956#define JPEG_CONFR4_HSF_Msk (0xFUL << JPEG_CONFR4_HSF_Pos) /*!< 0x0000F000 */
12957#define JPEG_CONFR4_HSF JPEG_CONFR4_HSF_Msk /*!<Horizontal sampling factor for component 1 */
12958#define JPEG_CONFR4_HSF_0 (0x1UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00001000 */
12959#define JPEG_CONFR4_HSF_1 (0x2UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00002000 */
12960#define JPEG_CONFR4_HSF_2 (0x4UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00004000 */
12961#define JPEG_CONFR4_HSF_3 (0x8UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00008000 */
12962
12963/******************** Bit definition for CONFR5 register ********************/
12964#define JPEG_CONFR5_HD_Pos (0U)
12965#define JPEG_CONFR5_HD_Msk (0x1UL << JPEG_CONFR5_HD_Pos) /*!< 0x00000001 */
12966#define JPEG_CONFR5_HD JPEG_CONFR5_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
12967#define JPEG_CONFR5_HA_Pos (1U)
12968#define JPEG_CONFR5_HA_Msk (0x1UL << JPEG_CONFR5_HA_Pos) /*!< 0x00000002 */
12969#define JPEG_CONFR5_HA JPEG_CONFR5_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
12970#define JPEG_CONFR5_QT_Pos (2U)
12971#define JPEG_CONFR5_QT_Msk (0x3UL << JPEG_CONFR5_QT_Pos) /*!< 0x0000000C */
12972#define JPEG_CONFR5_QT JPEG_CONFR5_QT_Msk /*!<Selects quantization table associated with a color component */
12973#define JPEG_CONFR5_QT_0 (0x1UL << JPEG_CONFR5_QT_Pos) /*!< 0x00000004 */
12974#define JPEG_CONFR5_QT_1 (0x2UL << JPEG_CONFR5_QT_Pos) /*!< 0x00000008 */
12975#define JPEG_CONFR5_NB_Pos (4U)
12976#define JPEG_CONFR5_NB_Msk (0xFUL << JPEG_CONFR5_NB_Pos) /*!< 0x000000F0 */
12977#define JPEG_CONFR5_NB JPEG_CONFR5_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
12978#define JPEG_CONFR5_NB_0 (0x1UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000010 */
12979#define JPEG_CONFR5_NB_1 (0x2UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000020 */
12980#define JPEG_CONFR5_NB_2 (0x4UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000040 */
12981#define JPEG_CONFR5_NB_3 (0x8UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000080 */
12982#define JPEG_CONFR5_VSF_Pos (8U)
12983#define JPEG_CONFR5_VSF_Msk (0xFUL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000F00 */
12984#define JPEG_CONFR5_VSF JPEG_CONFR5_VSF_Msk /*!<Vertical sampling factor for component 2 */
12985#define JPEG_CONFR5_VSF_0 (0x1UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000100 */
12986#define JPEG_CONFR5_VSF_1 (0x2UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000200 */
12987#define JPEG_CONFR5_VSF_2 (0x4UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000400 */
12988#define JPEG_CONFR5_VSF_3 (0x8UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000800 */
12989#define JPEG_CONFR5_HSF_Pos (12U)
12990#define JPEG_CONFR5_HSF_Msk (0xFUL << JPEG_CONFR5_HSF_Pos) /*!< 0x0000F000 */
12991#define JPEG_CONFR5_HSF JPEG_CONFR5_HSF_Msk /*!<Horizontal sampling factor for component 2 */
12992#define JPEG_CONFR5_HSF_0 (0x1UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00001000 */
12993#define JPEG_CONFR5_HSF_1 (0x2UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00002000 */
12994#define JPEG_CONFR5_HSF_2 (0x4UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00004000 */
12995#define JPEG_CONFR5_HSF_3 (0x8UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00008000 */
12996
12997/******************** Bit definition for CONFR6 register ********************/
12998#define JPEG_CONFR6_HD_Pos (0U)
12999#define JPEG_CONFR6_HD_Msk (0x1UL << JPEG_CONFR6_HD_Pos) /*!< 0x00000001 */
13000#define JPEG_CONFR6_HD JPEG_CONFR6_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
13001#define JPEG_CONFR6_HA_Pos (1U)
13002#define JPEG_CONFR6_HA_Msk (0x1UL << JPEG_CONFR6_HA_Pos) /*!< 0x00000002 */
13003#define JPEG_CONFR6_HA JPEG_CONFR6_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
13004#define JPEG_CONFR6_QT_Pos (2U)
13005#define JPEG_CONFR6_QT_Msk (0x3UL << JPEG_CONFR6_QT_Pos) /*!< 0x0000000C */
13006#define JPEG_CONFR6_QT JPEG_CONFR6_QT_Msk /*!<Selects quantization table associated with a color component */
13007#define JPEG_CONFR6_QT_0 (0x1UL << JPEG_CONFR6_QT_Pos) /*!< 0x00000004 */
13008#define JPEG_CONFR6_QT_1 (0x2UL << JPEG_CONFR6_QT_Pos) /*!< 0x00000008 */
13009#define JPEG_CONFR6_NB_Pos (4U)
13010#define JPEG_CONFR6_NB_Msk (0xFUL << JPEG_CONFR6_NB_Pos) /*!< 0x000000F0 */
13011#define JPEG_CONFR6_NB JPEG_CONFR6_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
13012#define JPEG_CONFR6_NB_0 (0x1UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000010 */
13013#define JPEG_CONFR6_NB_1 (0x2UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000020 */
13014#define JPEG_CONFR6_NB_2 (0x4UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000040 */
13015#define JPEG_CONFR6_NB_3 (0x8UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000080 */
13016#define JPEG_CONFR6_VSF_Pos (8U)
13017#define JPEG_CONFR6_VSF_Msk (0xFUL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000F00 */
13018#define JPEG_CONFR6_VSF JPEG_CONFR6_VSF_Msk /*!<Vertical sampling factor for component 2 */
13019#define JPEG_CONFR6_VSF_0 (0x1UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000100 */
13020#define JPEG_CONFR6_VSF_1 (0x2UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000200 */
13021#define JPEG_CONFR6_VSF_2 (0x4UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000400 */
13022#define JPEG_CONFR6_VSF_3 (0x8UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000800 */
13023#define JPEG_CONFR6_HSF_Pos (12U)
13024#define JPEG_CONFR6_HSF_Msk (0xFUL << JPEG_CONFR6_HSF_Pos) /*!< 0x0000F000 */
13025#define JPEG_CONFR6_HSF JPEG_CONFR6_HSF_Msk /*!<Horizontal sampling factor for component 2 */
13026#define JPEG_CONFR6_HSF_0 (0x1UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00001000 */
13027#define JPEG_CONFR6_HSF_1 (0x2UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00002000 */
13028#define JPEG_CONFR6_HSF_2 (0x4UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00004000 */
13029#define JPEG_CONFR6_HSF_3 (0x8UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00008000 */
13030
13031/******************** Bit definition for CONFR7 register ********************/
13032#define JPEG_CONFR7_HD_Pos (0U)
13033#define JPEG_CONFR7_HD_Msk (0x1UL << JPEG_CONFR7_HD_Pos) /*!< 0x00000001 */
13034#define JPEG_CONFR7_HD JPEG_CONFR7_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
13035#define JPEG_CONFR7_HA_Pos (1U)
13036#define JPEG_CONFR7_HA_Msk (0x1UL << JPEG_CONFR7_HA_Pos) /*!< 0x00000002 */
13037#define JPEG_CONFR7_HA JPEG_CONFR7_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
13038#define JPEG_CONFR7_QT_Pos (2U)
13039#define JPEG_CONFR7_QT_Msk (0x3UL << JPEG_CONFR7_QT_Pos) /*!< 0x0000000C */
13040#define JPEG_CONFR7_QT JPEG_CONFR7_QT_Msk /*!<Selects quantization table associated with a color component */
13041#define JPEG_CONFR7_QT_0 (0x1UL << JPEG_CONFR7_QT_Pos) /*!< 0x00000004 */
13042#define JPEG_CONFR7_QT_1 (0x2UL << JPEG_CONFR7_QT_Pos) /*!< 0x00000008 */
13043#define JPEG_CONFR7_NB_Pos (4U)
13044#define JPEG_CONFR7_NB_Msk (0xFUL << JPEG_CONFR7_NB_Pos) /*!< 0x000000F0 */
13045#define JPEG_CONFR7_NB JPEG_CONFR7_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
13046#define JPEG_CONFR7_NB_0 (0x1UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000010 */
13047#define JPEG_CONFR7_NB_1 (0x2UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000020 */
13048#define JPEG_CONFR7_NB_2 (0x4UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000040 */
13049#define JPEG_CONFR7_NB_3 (0x8UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000080 */
13050#define JPEG_CONFR7_VSF_Pos (8U)
13051#define JPEG_CONFR7_VSF_Msk (0xFUL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000F00 */
13052#define JPEG_CONFR7_VSF JPEG_CONFR7_VSF_Msk /*!<Vertical sampling factor for component 2 */
13053#define JPEG_CONFR7_VSF_0 (0x1UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000100 */
13054#define JPEG_CONFR7_VSF_1 (0x2UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000200 */
13055#define JPEG_CONFR7_VSF_2 (0x4UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000400 */
13056#define JPEG_CONFR7_VSF_3 (0x8UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000800 */
13057#define JPEG_CONFR7_HSF_Pos (12U)
13058#define JPEG_CONFR7_HSF_Msk (0xFUL << JPEG_CONFR7_HSF_Pos) /*!< 0x0000F000 */
13059#define JPEG_CONFR7_HSF JPEG_CONFR7_HSF_Msk /*!<Horizontal sampling factor for component 2 */
13060#define JPEG_CONFR7_HSF_0 (0x1UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00001000 */
13061#define JPEG_CONFR7_HSF_1 (0x2UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00002000 */
13062#define JPEG_CONFR7_HSF_2 (0x4UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00004000 */
13063#define JPEG_CONFR7_HSF_3 (0x8UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00008000 */
13064
13065/******************** Bit definition for CR register ********************/
13066#define JPEG_CR_JCEN_Pos (0U)
13067#define JPEG_CR_JCEN_Msk (0x1UL << JPEG_CR_JCEN_Pos) /*!< 0x00000001 */
13068#define JPEG_CR_JCEN JPEG_CR_JCEN_Msk /*!<Enable the JPEG Codec Core */
13069#define JPEG_CR_IFTIE_Pos (1U)
13070#define JPEG_CR_IFTIE_Msk (0x1UL << JPEG_CR_IFTIE_Pos) /*!< 0x00000002 */
13071#define JPEG_CR_IFTIE JPEG_CR_IFTIE_Msk /*!<Input FIFO Threshold Interrupt Enable */
13072#define JPEG_CR_IFNFIE_Pos (2U)
13073#define JPEG_CR_IFNFIE_Msk (0x1UL << JPEG_CR_IFNFIE_Pos) /*!< 0x00000004 */
13074#define JPEG_CR_IFNFIE JPEG_CR_IFNFIE_Msk /*!<Input FIFO Not Full Interrupt Enable */
13075#define JPEG_CR_OFTIE_Pos (3U)
13076#define JPEG_CR_OFTIE_Msk (0x1UL << JPEG_CR_OFTIE_Pos) /*!< 0x00000008 */
13077#define JPEG_CR_OFTIE JPEG_CR_OFTIE_Msk /*!<Output FIFO Threshold Interrupt Enable */
13078#define JPEG_CR_OFNEIE_Pos (4U)
13079#define JPEG_CR_OFNEIE_Msk (0x1UL << JPEG_CR_OFNEIE_Pos) /*!< 0x00000010 */
13080#define JPEG_CR_OFNEIE JPEG_CR_OFNEIE_Msk /*!<Output FIFO Not Empty Interrupt Enable */
13081#define JPEG_CR_EOCIE_Pos (5U)
13082#define JPEG_CR_EOCIE_Msk (0x1UL << JPEG_CR_EOCIE_Pos) /*!< 0x00000020 */
13083#define JPEG_CR_EOCIE JPEG_CR_EOCIE_Msk /*!<End of Conversion Interrupt Enable */
13084#define JPEG_CR_HPDIE_Pos (6U)
13085#define JPEG_CR_HPDIE_Msk (0x1UL << JPEG_CR_HPDIE_Pos) /*!< 0x00000040 */
13086#define JPEG_CR_HPDIE JPEG_CR_HPDIE_Msk /*!<Header Parsing Done Interrupt Enable */
13087#define JPEG_CR_IFF_Pos (13U)
13088#define JPEG_CR_IFF_Msk (0x1UL << JPEG_CR_IFF_Pos) /*!< 0x00002000 */
13089#define JPEG_CR_IFF JPEG_CR_IFF_Msk /*!<Flush the input FIFO */
13090#define JPEG_CR_OFF_Pos (14U)
13091#define JPEG_CR_OFF_Msk (0x1UL << JPEG_CR_OFF_Pos) /*!< 0x00004000 */
13092#define JPEG_CR_OFF JPEG_CR_OFF_Msk /*!<Flush the output FIFO */
13093
13094/******************** Bit definition for SR register ********************/
13095#define JPEG_SR_IFTF_Pos (1U)
13096#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
13097#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
13098#define JPEG_SR_IFNFF_Pos (2U)
13099#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
13100#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
13101#define JPEG_SR_OFTF_Pos (3U)
13102#define JPEG_SR_OFTF_Msk (0x1UL << JPEG_SR_OFTF_Pos) /*!< 0x00000008 */
13103#define JPEG_SR_OFTF JPEG_SR_OFTF_Msk /*!<Output FIFO is not empty and has reach its threshold */
13104#define JPEG_SR_OFNEF_Pos (4U)
13105#define JPEG_SR_OFNEF_Msk (0x1UL << JPEG_SR_OFNEF_Pos) /*!< 0x00000010 */
13106#define JPEG_SR_OFNEF JPEG_SR_OFNEF_Msk /*!<Output FIFO is not empty, a data is available */
13107#define JPEG_SR_EOCF_Pos (5U)
13108#define JPEG_SR_EOCF_Msk (0x1UL << JPEG_SR_EOCF_Pos) /*!< 0x00000020 */
13109#define JPEG_SR_EOCF JPEG_SR_EOCF_Msk /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
13110#define JPEG_SR_HPDF_Pos (6U)
13111#define JPEG_SR_HPDF_Msk (0x1UL << JPEG_SR_HPDF_Pos) /*!< 0x00000040 */
13112#define JPEG_SR_HPDF JPEG_SR_HPDF_Msk /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
13113#define JPEG_SR_COF_Pos (7U)
13114#define JPEG_SR_COF_Msk (0x1UL << JPEG_SR_COF_Pos) /*!< 0x00000080 */
13115#define JPEG_SR_COF JPEG_SR_COF_Msk /*!<JPEG Codec operation on going flag */
13116
13117/******************** Bit definition for CFR register ********************/
13118#define JPEG_CFR_CEOCF_Pos (4U)
13119#define JPEG_CFR_CEOCF_Msk (0x1UL << JPEG_CFR_CEOCF_Pos) /*!< 0x00000010 */
13120#define JPEG_CFR_CEOCF JPEG_CFR_CEOCF_Msk /*!<Clear End of Conversion Flag */
13121#define JPEG_CFR_CHPDF_Pos (5U)
13122#define JPEG_CFR_CHPDF_Msk (0x1UL << JPEG_CFR_CHPDF_Pos) /*!< 0x00000020 */
13123#define JPEG_CFR_CHPDF JPEG_CFR_CHPDF_Msk /*!<Clear Header Parsing Done Flag */
13124
13125/******************** Bit definition for DIR register ********************/
13126#define JPEG_DIR_DATAIN_Pos (0U)
13127#define JPEG_DIR_DATAIN_Msk (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos) /*!< 0xFFFFFFFF */
13128#define JPEG_DIR_DATAIN JPEG_DIR_DATAIN_Msk /*!<Data Input FIFO */
13129
13130/******************** Bit definition for DOR register ********************/
13131#define JPEG_DOR_DATAOUT_Pos (0U)
13132#define JPEG_DOR_DATAOUT_Msk (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */
13133#define JPEG_DOR_DATAOUT JPEG_DOR_DATAOUT_Msk /*!<Data Output FIFO */
13134
13135/******************************************************************************/
13136/* */
13137/* LCD-TFT Display Controller (LTDC) */
13138/* */
13139/******************************************************************************/
13140
13141/******************** Bit definition for LTDC_SSCR register *****************/
13142
13143#define LTDC_SSCR_VSH_Pos (0U)
13144#define LTDC_SSCR_VSH_Msk (0x7FFUL << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
13145#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
13146#define LTDC_SSCR_HSW_Pos (16U)
13147#define LTDC_SSCR_HSW_Msk (0xFFFUL << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
13148#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
13149
13150/******************** Bit definition for LTDC_BPCR register *****************/
13151
13152#define LTDC_BPCR_AVBP_Pos (0U)
13153#define LTDC_BPCR_AVBP_Msk (0x7FFUL << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
13154#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
13155#define LTDC_BPCR_AHBP_Pos (16U)
13156#define LTDC_BPCR_AHBP_Msk (0xFFFUL << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
13157#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
13158
13159/******************** Bit definition for LTDC_AWCR register *****************/
13160
13161#define LTDC_AWCR_AAH_Pos (0U)
13162#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
13163#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
13164#define LTDC_AWCR_AAW_Pos (16U)
13165#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
13166#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
13167
13168/******************** Bit definition for LTDC_TWCR register *****************/
13169
13170#define LTDC_TWCR_TOTALH_Pos (0U)
13171#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
13172#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
13173#define LTDC_TWCR_TOTALW_Pos (16U)
13174#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
13175#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
13176
13177/******************** Bit definition for LTDC_GCR register ******************/
13178
13179#define LTDC_GCR_LTDCEN_Pos (0U)
13180#define LTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
13181#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
13182#define LTDC_GCR_DBW_Pos (4U)
13183#define LTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
13184#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
13185#define LTDC_GCR_DGW_Pos (8U)
13186#define LTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
13187#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
13188#define LTDC_GCR_DRW_Pos (12U)
13189#define LTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
13190#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
13191#define LTDC_GCR_DEN_Pos (16U)
13192#define LTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
13193#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
13194#define LTDC_GCR_PCPOL_Pos (28U)
13195#define LTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
13196#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
13197#define LTDC_GCR_DEPOL_Pos (29U)
13198#define LTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
13199#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
13200#define LTDC_GCR_VSPOL_Pos (30U)
13201#define LTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
13202#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
13203#define LTDC_GCR_HSPOL_Pos (31U)
13204#define LTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
13205#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
13206
13207
13208/******************** Bit definition for LTDC_SRCR register *****************/
13209
13210#define LTDC_SRCR_IMR_Pos (0U)
13211#define LTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
13212#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
13213#define LTDC_SRCR_VBR_Pos (1U)
13214#define LTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
13215#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
13216
13217/******************** Bit definition for LTDC_BCCR register *****************/
13218
13219#define LTDC_BCCR_BCBLUE_Pos (0U)
13220#define LTDC_BCCR_BCBLUE_Msk (0xFFUL << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
13221#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
13222#define LTDC_BCCR_BCGREEN_Pos (8U)
13223#define LTDC_BCCR_BCGREEN_Msk (0xFFUL << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
13224#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
13225#define LTDC_BCCR_BCRED_Pos (16U)
13226#define LTDC_BCCR_BCRED_Msk (0xFFUL << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
13227#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
13228
13229/******************** Bit definition for LTDC_IER register ******************/
13230
13231#define LTDC_IER_LIE_Pos (0U)
13232#define LTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
13233#define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
13234#define LTDC_IER_FUIE_Pos (1U)
13235#define LTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
13236#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
13237#define LTDC_IER_TERRIE_Pos (2U)
13238#define LTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
13239#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
13240#define LTDC_IER_RRIE_Pos (3U)
13241#define LTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
13242#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
13243
13244/******************** Bit definition for LTDC_ISR register ******************/
13245
13246#define LTDC_ISR_LIF_Pos (0U)
13247#define LTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
13248#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
13249#define LTDC_ISR_FUIF_Pos (1U)
13250#define LTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
13251#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
13252#define LTDC_ISR_TERRIF_Pos (2U)
13253#define LTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
13254#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
13255#define LTDC_ISR_RRIF_Pos (3U)
13256#define LTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
13257#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
13258
13259/******************** Bit definition for LTDC_ICR register ******************/
13260
13261#define LTDC_ICR_CLIF_Pos (0U)
13262#define LTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
13263#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
13264#define LTDC_ICR_CFUIF_Pos (1U)
13265#define LTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
13266#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
13267#define LTDC_ICR_CTERRIF_Pos (2U)
13268#define LTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
13269#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
13270#define LTDC_ICR_CRRIF_Pos (3U)
13271#define LTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
13272#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
13273
13274/******************** Bit definition for LTDC_LIPCR register ****************/
13275
13276#define LTDC_LIPCR_LIPOS_Pos (0U)
13277#define LTDC_LIPCR_LIPOS_Msk (0x7FFUL << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
13278#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
13279
13280/******************** Bit definition for LTDC_CPSR register *****************/
13281
13282#define LTDC_CPSR_CYPOS_Pos (0U)
13283#define LTDC_CPSR_CYPOS_Msk (0xFFFFUL << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
13284#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
13285#define LTDC_CPSR_CXPOS_Pos (16U)
13286#define LTDC_CPSR_CXPOS_Msk (0xFFFFUL << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
13287#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
13288
13289/******************** Bit definition for LTDC_CDSR register *****************/
13290
13291#define LTDC_CDSR_VDES_Pos (0U)
13292#define LTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
13293#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
13294#define LTDC_CDSR_HDES_Pos (1U)
13295#define LTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
13296#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
13297#define LTDC_CDSR_VSYNCS_Pos (2U)
13298#define LTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
13299#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
13300#define LTDC_CDSR_HSYNCS_Pos (3U)
13301#define LTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
13302#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
13303
13304/******************** Bit definition for LTDC_LxCR register *****************/
13305
13306#define LTDC_LxCR_LEN_Pos (0U)
13307#define LTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
13308#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
13309#define LTDC_LxCR_COLKEN_Pos (1U)
13310#define LTDC_LxCR_COLKEN_Msk (0x1UL << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
13311#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
13312#define LTDC_LxCR_CLUTEN_Pos (4U)
13313#define LTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
13314#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
13315
13316/******************** Bit definition for LTDC_LxWHPCR register **************/
13317
13318#define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
13319#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
13320#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
13321#define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
13322#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */
13323#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
13324
13325/******************** Bit definition for LTDC_LxWVPCR register **************/
13326
13327#define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
13328#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
13329#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
13330#define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
13331#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */
13332#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
13333
13334/******************** Bit definition for LTDC_LxCKCR register ***************/
13335
13336#define LTDC_LxCKCR_CKBLUE_Pos (0U)
13337#define LTDC_LxCKCR_CKBLUE_Msk (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
13338#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
13339#define LTDC_LxCKCR_CKGREEN_Pos (8U)
13340#define LTDC_LxCKCR_CKGREEN_Msk (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
13341#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
13342#define LTDC_LxCKCR_CKRED_Pos (16U)
13343#define LTDC_LxCKCR_CKRED_Msk (0xFFUL << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
13344#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
13345
13346/******************** Bit definition for LTDC_LxPFCR register ***************/
13347
13348#define LTDC_LxPFCR_PF_Pos (0U)
13349#define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
13350#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
13351
13352/******************** Bit definition for LTDC_LxCACR register ***************/
13353
13354#define LTDC_LxCACR_CONSTA_Pos (0U)
13355#define LTDC_LxCACR_CONSTA_Msk (0xFFUL << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
13356#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
13357
13358/******************** Bit definition for LTDC_LxDCCR register ***************/
13359
13360#define LTDC_LxDCCR_DCBLUE_Pos (0U)
13361#define LTDC_LxDCCR_DCBLUE_Msk (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
13362#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
13363#define LTDC_LxDCCR_DCGREEN_Pos (8U)
13364#define LTDC_LxDCCR_DCGREEN_Msk (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
13365#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
13366#define LTDC_LxDCCR_DCRED_Pos (16U)
13367#define LTDC_LxDCCR_DCRED_Msk (0xFFUL << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
13368#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
13369#define LTDC_LxDCCR_DCALPHA_Pos (24U)
13370#define LTDC_LxDCCR_DCALPHA_Msk (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
13371#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
13372
13373/******************** Bit definition for LTDC_LxBFCR register ***************/
13374
13375#define LTDC_LxBFCR_BF2_Pos (0U)
13376#define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
13377#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
13378#define LTDC_LxBFCR_BF1_Pos (8U)
13379#define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
13380#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
13381
13382/******************** Bit definition for LTDC_LxCFBAR register **************/
13383
13384#define LTDC_LxCFBAR_CFBADD_Pos (0U)
13385#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
13386#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
13387
13388/******************** Bit definition for LTDC_LxCFBLR register **************/
13389
13390#define LTDC_LxCFBLR_CFBLL_Pos (0U)
13391#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
13392#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
13393#define LTDC_LxCFBLR_CFBP_Pos (16U)
13394#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
13395#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
13396
13397/******************** Bit definition for LTDC_LxCFBLNR register *************/
13398
13399#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
13400#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
13401#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
13402
13403/******************** Bit definition for LTDC_LxCLUTWR register *************/
13404
13405#define LTDC_LxCLUTWR_BLUE_Pos (0U)
13406#define LTDC_LxCLUTWR_BLUE_Msk (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
13407#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
13408#define LTDC_LxCLUTWR_GREEN_Pos (8U)
13409#define LTDC_LxCLUTWR_GREEN_Msk (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
13410#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
13411#define LTDC_LxCLUTWR_RED_Pos (16U)
13412#define LTDC_LxCLUTWR_RED_Msk (0xFFUL << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
13413#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
13414#define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
13415#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
13416#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
13417
13418/******************************************************************************/
13419/* */
13420/* MDMA */
13421/* */
13422/******************************************************************************/
13423/******************** Bit definition for MDMA_GISR0 register ****************/
13424#define MDMA_GISR0_GIF0_Pos (0U)
13425#define MDMA_GISR0_GIF0_Msk (0x1UL << MDMA_GISR0_GIF0_Pos) /*!< 0x00000001 */
13426#define MDMA_GISR0_GIF0 MDMA_GISR0_GIF0_Msk /*!< Channel 0 global interrupt flag */
13427#define MDMA_GISR0_GIF1_Pos (1U)
13428#define MDMA_GISR0_GIF1_Msk (0x1UL << MDMA_GISR0_GIF1_Pos) /*!< 0x00000002 */
13429#define MDMA_GISR0_GIF1 MDMA_GISR0_GIF1_Msk /*!< Channel 1 global interrupt flag */
13430#define MDMA_GISR0_GIF2_Pos (2U)
13431#define MDMA_GISR0_GIF2_Msk (0x1UL << MDMA_GISR0_GIF2_Pos) /*!< 0x00000004 */
13432#define MDMA_GISR0_GIF2 MDMA_GISR0_GIF2_Msk /*!< Channel 2 global interrupt flag */
13433#define MDMA_GISR0_GIF3_Pos (3U)
13434#define MDMA_GISR0_GIF3_Msk (0x1UL << MDMA_GISR0_GIF3_Pos) /*!< 0x00000008 */
13435#define MDMA_GISR0_GIF3 MDMA_GISR0_GIF3_Msk /*!< Channel 3 global interrupt flag */
13436#define MDMA_GISR0_GIF4_Pos (4U)
13437#define MDMA_GISR0_GIF4_Msk (0x1UL << MDMA_GISR0_GIF4_Pos) /*!< 0x00000010 */
13438#define MDMA_GISR0_GIF4 MDMA_GISR0_GIF4_Msk /*!< Channel 4 global interrupt flag */
13439#define MDMA_GISR0_GIF5_Pos (5U)
13440#define MDMA_GISR0_GIF5_Msk (0x1UL << MDMA_GISR0_GIF5_Pos) /*!< 0x00000020 */
13441#define MDMA_GISR0_GIF5 MDMA_GISR0_GIF5_Msk /*!< Channel 5 global interrupt flag */
13442#define MDMA_GISR0_GIF6_Pos (6U)
13443#define MDMA_GISR0_GIF6_Msk (0x1UL << MDMA_GISR0_GIF6_Pos) /*!< 0x00000040 */
13444#define MDMA_GISR0_GIF6 MDMA_GISR0_GIF6_Msk /*!< Channel 6 global interrupt flag */
13445#define MDMA_GISR0_GIF7_Pos (7U)
13446#define MDMA_GISR0_GIF7_Msk (0x1UL << MDMA_GISR0_GIF7_Pos) /*!< 0x00000080 */
13447#define MDMA_GISR0_GIF7 MDMA_GISR0_GIF7_Msk /*!< Channel 7 global interrupt flag */
13448#define MDMA_GISR0_GIF8_Pos (8U)
13449#define MDMA_GISR0_GIF8_Msk (0x1UL << MDMA_GISR0_GIF8_Pos) /*!< 0x00000100 */
13450#define MDMA_GISR0_GIF8 MDMA_GISR0_GIF8_Msk /*!< Channel 8 global interrupt flag */
13451#define MDMA_GISR0_GIF9_Pos (9U)
13452#define MDMA_GISR0_GIF9_Msk (0x1UL << MDMA_GISR0_GIF9_Pos) /*!< 0x00000200 */
13453#define MDMA_GISR0_GIF9 MDMA_GISR0_GIF9_Msk /*!< Channel 9 global interrupt flag */
13454#define MDMA_GISR0_GIF10_Pos (10U)
13455#define MDMA_GISR0_GIF10_Msk (0x1UL << MDMA_GISR0_GIF10_Pos) /*!< 0x00000400 */
13456#define MDMA_GISR0_GIF10 MDMA_GISR0_GIF10_Msk /*!< Channel 10 global interrupt flag */
13457#define MDMA_GISR0_GIF11_Pos (11U)
13458#define MDMA_GISR0_GIF11_Msk (0x1UL << MDMA_GISR0_GIF11_Pos) /*!< 0x00000800 */
13459#define MDMA_GISR0_GIF11 MDMA_GISR0_GIF11_Msk /*!< Channel 11 global interrupt flag */
13460#define MDMA_GISR0_GIF12_Pos (12U)
13461#define MDMA_GISR0_GIF12_Msk (0x1UL << MDMA_GISR0_GIF12_Pos) /*!< 0x00001000 */
13462#define MDMA_GISR0_GIF12 MDMA_GISR0_GIF12_Msk /*!< Channel 12 global interrupt flag */
13463#define MDMA_GISR0_GIF13_Pos (13U)
13464#define MDMA_GISR0_GIF13_Msk (0x1UL << MDMA_GISR0_GIF13_Pos) /*!< 0x00002000 */
13465#define MDMA_GISR0_GIF13 MDMA_GISR0_GIF13_Msk /*!< Channel 13 global interrupt flag */
13466#define MDMA_GISR0_GIF14_Pos (14U)
13467#define MDMA_GISR0_GIF14_Msk (0x1UL << MDMA_GISR0_GIF14_Pos) /*!< 0x00004000 */
13468#define MDMA_GISR0_GIF14 MDMA_GISR0_GIF14_Msk /*!< Channel 14 global interrupt flag */
13469#define MDMA_GISR0_GIF15_Pos (15U)
13470#define MDMA_GISR0_GIF15_Msk (0x1UL << MDMA_GISR0_GIF15_Pos) /*!< 0x00008000 */
13471#define MDMA_GISR0_GIF15 MDMA_GISR0_GIF15_Msk /*!< Channel 15 global interrupt flag */
13472
13473/******************** Bit definition for MDMA_CxISR register ****************/
13474#define MDMA_CISR_TEIF_Pos (0U)
13475#define MDMA_CISR_TEIF_Msk (0x1UL << MDMA_CISR_TEIF_Pos) /*!< 0x00000001 */
13476#define MDMA_CISR_TEIF MDMA_CISR_TEIF_Msk /*!< Channel x transfer error interrupt flag */
13477#define MDMA_CISR_CTCIF_Pos (1U)
13478#define MDMA_CISR_CTCIF_Msk (0x1UL << MDMA_CISR_CTCIF_Pos) /*!< 0x00000002 */
13479#define MDMA_CISR_CTCIF MDMA_CISR_CTCIF_Msk /*!< Channel x Channel Transfer Complete interrupt flag */
13480#define MDMA_CISR_BRTIF_Pos (2U)
13481#define MDMA_CISR_BRTIF_Msk (0x1UL << MDMA_CISR_BRTIF_Pos) /*!< 0x00000004 */
13482#define MDMA_CISR_BRTIF MDMA_CISR_BRTIF_Msk /*!< Channel x block repeat transfer complete interrupt flag */
13483#define MDMA_CISR_BTIF_Pos (3U)
13484#define MDMA_CISR_BTIF_Msk (0x1UL << MDMA_CISR_BTIF_Pos) /*!< 0x00000008 */
13485#define MDMA_CISR_BTIF MDMA_CISR_BTIF_Msk /*!< Channel x block transfer complete interrupt flag */
13486#define MDMA_CISR_TCIF_Pos (4U)
13487#define MDMA_CISR_TCIF_Msk (0x1UL << MDMA_CISR_TCIF_Pos) /*!< 0x00000010 */
13488#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
13489#define MDMA_CISR_CRQA_Pos (16U)
13490#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
13491#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
13492
13493/******************** Bit definition for MDMA_CxIFCR register ****************/
13494#define MDMA_CIFCR_CTEIF_Pos (0U)
13495#define MDMA_CIFCR_CTEIF_Msk (0x1UL << MDMA_CIFCR_CTEIF_Pos) /*!< 0x00000001 */
13496#define MDMA_CIFCR_CTEIF MDMA_CIFCR_CTEIF_Msk /*!< Channel x clear transfer error interrupt flag */
13497#define MDMA_CIFCR_CCTCIF_Pos (1U)
13498#define MDMA_CIFCR_CCTCIF_Msk (0x1UL << MDMA_CIFCR_CCTCIF_Pos) /*!< 0x00000002 */
13499#define MDMA_CIFCR_CCTCIF MDMA_CIFCR_CCTCIF_Msk /*!< Clear Channel transfer complete interrupt flag for channel x */
13500#define MDMA_CIFCR_CBRTIF_Pos (2U)
13501#define MDMA_CIFCR_CBRTIF_Msk (0x1UL << MDMA_CIFCR_CBRTIF_Pos) /*!< 0x00000004 */
13502#define MDMA_CIFCR_CBRTIF MDMA_CIFCR_CBRTIF_Msk /*!< Channel x clear block repeat transfer complete interrupt flag */
13503#define MDMA_CIFCR_CBTIF_Pos (3U)
13504#define MDMA_CIFCR_CBTIF_Msk (0x1UL << MDMA_CIFCR_CBTIF_Pos) /*!< 0x00000008 */
13505#define MDMA_CIFCR_CBTIF MDMA_CIFCR_CBTIF_Msk /*!< Channel x Clear block transfer complete interrupt flag */
13506#define MDMA_CIFCR_CLTCIF_Pos (4U)
13507#define MDMA_CIFCR_CLTCIF_Msk (0x1UL << MDMA_CIFCR_CLTCIF_Pos) /*!< 0x00000010 */
13508#define MDMA_CIFCR_CLTCIF MDMA_CIFCR_CLTCIF_Msk /*!< CLear Transfer buffer Complete Interrupt Flag for channel */
13509
13510/******************** Bit definition for MDMA_CxESR register ****************/
13511#define MDMA_CESR_TEA_Pos (0U)
13512#define MDMA_CESR_TEA_Msk (0x7FUL << MDMA_CESR_TEA_Pos) /*!< 0x0000007F */
13513#define MDMA_CESR_TEA MDMA_CESR_TEA_Msk /*!< Transfer Error Address */
13514#define MDMA_CESR_TED_Pos (7U)
13515#define MDMA_CESR_TED_Msk (0x1UL << MDMA_CESR_TED_Pos) /*!< 0x00000080 */
13516#define MDMA_CESR_TED MDMA_CESR_TED_Msk /*!< Transfer Error Direction */
13517#define MDMA_CESR_TELD_Pos (8U)
13518#define MDMA_CESR_TELD_Msk (0x1UL << MDMA_CESR_TELD_Pos) /*!< 0x00000100 */
13519#define MDMA_CESR_TELD MDMA_CESR_TELD_Msk /*!< Transfer Error Link Data */
13520#define MDMA_CESR_TEMD_Pos (9U)
13521#define MDMA_CESR_TEMD_Msk (0x1UL << MDMA_CESR_TEMD_Pos) /*!< 0x00000200 */
13522#define MDMA_CESR_TEMD MDMA_CESR_TEMD_Msk /*!< Transfer Error Mask Data */
13523#define MDMA_CESR_ASE_Pos (10U)
13524#define MDMA_CESR_ASE_Msk (0x1UL << MDMA_CESR_ASE_Pos) /*!< 0x00000400 */
13525#define MDMA_CESR_ASE MDMA_CESR_ASE_Msk /*!< Address/Size Error */
13526#define MDMA_CESR_BSE_Pos (11U)
13527#define MDMA_CESR_BSE_Msk (0x1UL << MDMA_CESR_BSE_Pos) /*!< 0x00000800 */
13528#define MDMA_CESR_BSE MDMA_CESR_BSE_Msk /*!< Block Size Error */
13529
13530/******************** Bit definition for MDMA_CxCR register ****************/
13531#define MDMA_CCR_EN_Pos (0U)
13532#define MDMA_CCR_EN_Msk (0x1UL << MDMA_CCR_EN_Pos) /*!< 0x00000001 */
13533#define MDMA_CCR_EN MDMA_CCR_EN_Msk /*!< Channel enable / flag channel ready when read low */
13534#define MDMA_CCR_TEIE_Pos (1U)
13535#define MDMA_CCR_TEIE_Msk (0x1UL << MDMA_CCR_TEIE_Pos) /*!< 0x00000002 */
13536#define MDMA_CCR_TEIE MDMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
13537#define MDMA_CCR_CTCIE_Pos (2U)
13538#define MDMA_CCR_CTCIE_Msk (0x1UL << MDMA_CCR_CTCIE_Pos) /*!< 0x00000004 */
13539#define MDMA_CCR_CTCIE MDMA_CCR_CTCIE_Msk /*!< Channel Transfer Complete interrupt enable */
13540#define MDMA_CCR_BRTIE_Pos (3U)
13541#define MDMA_CCR_BRTIE_Msk (0x1UL << MDMA_CCR_BRTIE_Pos) /*!< 0x00000008 */
13542#define MDMA_CCR_BRTIE MDMA_CCR_BRTIE_Msk /*!< Block Repeat transfer interrupt enable */
13543#define MDMA_CCR_BTIE_Pos (4U)
13544#define MDMA_CCR_BTIE_Msk (0x1UL << MDMA_CCR_BTIE_Pos) /*!< 0x00000010 */
13545#define MDMA_CCR_BTIE MDMA_CCR_BTIE_Msk /*!< Block Transfer interrupt enable */
13546#define MDMA_CCR_TCIE_Pos (5U)
13547#define MDMA_CCR_TCIE_Msk (0x1UL << MDMA_CCR_TCIE_Pos) /*!< 0x00000020 */
13548#define MDMA_CCR_TCIE MDMA_CCR_TCIE_Msk /*!< buffer Transfer Complete interrupt enable */
13549#define MDMA_CCR_PL_Pos (6U)
13550#define MDMA_CCR_PL_Msk (0x3UL << MDMA_CCR_PL_Pos) /*!< 0x000000C0 */
13551#define MDMA_CCR_PL MDMA_CCR_PL_Msk /*!< Priority level */
13552#define MDMA_CCR_PL_0 (0x1UL << MDMA_CCR_PL_Pos) /*!< 0x00000040 */
13553#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
13554#define MDMA_CCR_BEX_Pos (12U)
13555#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
13556#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
13557#define MDMA_CCR_HEX_Pos (13U)
13558#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
13559#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
13560#define MDMA_CCR_WEX_Pos (14U)
13561#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
13562#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
13563#define MDMA_CCR_SWRQ_Pos (16U)
13564#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
13565#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
13566
13567/******************** Bit definition for MDMA_CxTCR register ****************/
13568#define MDMA_CTCR_SINC_Pos (0U)
13569#define MDMA_CTCR_SINC_Msk (0x3UL << MDMA_CTCR_SINC_Pos) /*!< 0x00000003 */
13570#define MDMA_CTCR_SINC MDMA_CTCR_SINC_Msk /*!< Source increment mode */
13571#define MDMA_CTCR_SINC_0 (0x1UL << MDMA_CTCR_SINC_Pos) /*!< 0x00000001 */
13572#define MDMA_CTCR_SINC_1 (0x2UL << MDMA_CTCR_SINC_Pos) /*!< 0x00000002 */
13573#define MDMA_CTCR_DINC_Pos (2U)
13574#define MDMA_CTCR_DINC_Msk (0x3UL << MDMA_CTCR_DINC_Pos) /*!< 0x0000000C */
13575#define MDMA_CTCR_DINC MDMA_CTCR_DINC_Msk /*!< Source increment mode */
13576#define MDMA_CTCR_DINC_0 (0x1UL << MDMA_CTCR_DINC_Pos) /*!< 0x00000004 */
13577#define MDMA_CTCR_DINC_1 (0x2UL << MDMA_CTCR_DINC_Pos) /*!< 0x00000008 */
13578#define MDMA_CTCR_SSIZE_Pos (4U)
13579#define MDMA_CTCR_SSIZE_Msk (0x3UL << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000030 */
13580#define MDMA_CTCR_SSIZE MDMA_CTCR_SSIZE_Msk /*!< Source data size */
13581#define MDMA_CTCR_SSIZE_0 (0x1UL << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000010 */
13582#define MDMA_CTCR_SSIZE_1 (0x2UL << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000020 */
13583#define MDMA_CTCR_DSIZE_Pos (6U)
13584#define MDMA_CTCR_DSIZE_Msk (0x3UL << MDMA_CTCR_DSIZE_Pos) /*!< 0x000000C0 */
13585#define MDMA_CTCR_DSIZE MDMA_CTCR_DSIZE_Msk /*!< Destination data size */
13586#define MDMA_CTCR_DSIZE_0 (0x1UL << MDMA_CTCR_DSIZE_Pos) /*!< 0x00000040 */
13587#define MDMA_CTCR_DSIZE_1 (0x2UL << MDMA_CTCR_DSIZE_Pos) /*!< 0x00000080 */
13588#define MDMA_CTCR_SINCOS_Pos (8U)
13589#define MDMA_CTCR_SINCOS_Msk (0x3UL << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000300 */
13590#define MDMA_CTCR_SINCOS MDMA_CTCR_SINCOS_Msk /*!< Source increment offset size */
13591#define MDMA_CTCR_SINCOS_0 (0x1UL << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000100 */
13592#define MDMA_CTCR_SINCOS_1 (0x2UL << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000200 */
13593#define MDMA_CTCR_DINCOS_Pos (10U)
13594#define MDMA_CTCR_DINCOS_Msk (0x3UL << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000C00 */
13595#define MDMA_CTCR_DINCOS MDMA_CTCR_DINCOS_Msk /*!< Destination increment offset size */
13596#define MDMA_CTCR_DINCOS_0 (0x1UL << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000400 */
13597#define MDMA_CTCR_DINCOS_1 (0x2UL << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000800 */
13598#define MDMA_CTCR_SBURST_Pos (12U)
13599#define MDMA_CTCR_SBURST_Msk (0x7UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00007000 */
13600#define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */
13601#define MDMA_CTCR_SBURST_0 (0x1UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */
13602#define MDMA_CTCR_SBURST_1 (0x2UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */
13603#define MDMA_CTCR_SBURST_2 (0x4UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */
13604#define MDMA_CTCR_DBURST_Pos (15U)
13605#define MDMA_CTCR_DBURST_Msk (0x7UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */
13606#define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */
13607#define MDMA_CTCR_DBURST_0 (0x1UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00008000 */
13608#define MDMA_CTCR_DBURST_1 (0x2UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00010000 */
13609#define MDMA_CTCR_DBURST_2 (0x4UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00020000 */
13610#define MDMA_CTCR_TLEN_Pos (18U)
13611#define MDMA_CTCR_TLEN_Msk (0x7FUL << MDMA_CTCR_TLEN_Pos) /*!< 0x01FC0000 */
13612#define MDMA_CTCR_TLEN MDMA_CTCR_TLEN_Msk /*!< buffer Transfer Length (number of bytes - 1) */
13613#define MDMA_CTCR_PKE_Pos (25U)
13614#define MDMA_CTCR_PKE_Msk (0x1UL << MDMA_CTCR_PKE_Pos) /*!< 0x02000000 */
13615#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
13616#define MDMA_CTCR_PAM_Pos (26U)
13617#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
13618#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
13619#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
13620#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
13621#define MDMA_CTCR_TRGM_Pos (28U)
13622#define MDMA_CTCR_TRGM_Msk (0x3UL << MDMA_CTCR_TRGM_Pos) /*!< 0x30000000 */
13623#define MDMA_CTCR_TRGM MDMA_CTCR_TRGM_Msk /*!< Trigger Mode */
13624#define MDMA_CTCR_TRGM_0 (0x1UL << MDMA_CTCR_TRGM_Pos) /*!< 0x10000000 */
13625#define MDMA_CTCR_TRGM_1 (0x2UL << MDMA_CTCR_TRGM_Pos) /*!< 0x20000000 */
13626#define MDMA_CTCR_SWRM_Pos (30U)
13627#define MDMA_CTCR_SWRM_Msk (0x1UL << MDMA_CTCR_SWRM_Pos) /*!< 0x40000000 */
13628#define MDMA_CTCR_SWRM MDMA_CTCR_SWRM_Msk /*!< SW Request Mode */
13629#define MDMA_CTCR_BWM_Pos (31U)
13630#define MDMA_CTCR_BWM_Msk (0x1UL << MDMA_CTCR_BWM_Pos) /*!< 0x80000000 */
13631#define MDMA_CTCR_BWM MDMA_CTCR_BWM_Msk /*!< Bufferable Write Mode */
13632
13633/******************** Bit definition for MDMA_CxBNDTR register ****************/
13634#define MDMA_CBNDTR_BNDT_Pos (0U)
13635#define MDMA_CBNDTR_BNDT_Msk (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos) /*!< 0x0001FFFF */
13636#define MDMA_CBNDTR_BNDT MDMA_CBNDTR_BNDT_Msk /*!< Block Number of data bytes to transfer */
13637#define MDMA_CBNDTR_BRSUM_Pos (18U)
13638#define MDMA_CBNDTR_BRSUM_Msk (0x1UL << MDMA_CBNDTR_BRSUM_Pos) /*!< 0x00040000 */
13639#define MDMA_CBNDTR_BRSUM MDMA_CBNDTR_BRSUM_Msk /*!< Block Repeat Source address Update Mode */
13640#define MDMA_CBNDTR_BRDUM_Pos (19U)
13641#define MDMA_CBNDTR_BRDUM_Msk (0x1UL << MDMA_CBNDTR_BRDUM_Pos) /*!< 0x00080000 */
13642#define MDMA_CBNDTR_BRDUM MDMA_CBNDTR_BRDUM_Msk /*!< Block Repeat Destination address Update Mode */
13643#define MDMA_CBNDTR_BRC_Pos (20U)
13644#define MDMA_CBNDTR_BRC_Msk (0xFFFUL << MDMA_CBNDTR_BRC_Pos) /*!< 0xFFF00000 */
13645#define MDMA_CBNDTR_BRC MDMA_CBNDTR_BRC_Msk /*!< Block Repeat Count */
13646
13647/******************** Bit definition for MDMA_CxSAR register ****************/
13648#define MDMA_CSAR_SAR_Pos (0U)
13649#define MDMA_CSAR_SAR_Msk (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos) /*!< 0xFFFFFFFF */
13650#define MDMA_CSAR_SAR MDMA_CSAR_SAR_Msk /*!< Source address */
13651
13652/******************** Bit definition for MDMA_CxDAR register ****************/
13653#define MDMA_CDAR_DAR_Pos (0U)
13654#define MDMA_CDAR_DAR_Msk (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos) /*!< 0xFFFFFFFF */
13655#define MDMA_CDAR_DAR MDMA_CDAR_DAR_Msk /*!< Destination address */
13656
13657/******************** Bit definition for MDMA_CxBRUR ************************/
13658#define MDMA_CBRUR_SUV_Pos (0U)
13659#define MDMA_CBRUR_SUV_Msk (0xFFFFUL << MDMA_CBRUR_SUV_Pos) /*!< 0x0000FFFF */
13660#define MDMA_CBRUR_SUV MDMA_CBRUR_SUV_Msk /*!< Source address Update Value */
13661#define MDMA_CBRUR_DUV_Pos (16U)
13662#define MDMA_CBRUR_DUV_Msk (0xFFFFUL << MDMA_CBRUR_DUV_Pos) /*!< 0xFFFF0000 */
13663#define MDMA_CBRUR_DUV MDMA_CBRUR_DUV_Msk /*!< Destination address Update Value */
13664
13665/******************** Bit definition for MDMA_CxLAR *************************/
13666#define MDMA_CLAR_LAR_Pos (0U)
13667#define MDMA_CLAR_LAR_Msk (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos) /*!< 0xFFFFFFFF */
13668#define MDMA_CLAR_LAR MDMA_CLAR_LAR_Msk /*!< Link Address Register */
13669
13670/******************** Bit definition for MDMA_CxTBR) ************************/
13671#define MDMA_CTBR_TSEL_Pos (0U)
13672#define MDMA_CTBR_TSEL_Msk (0xFFUL << MDMA_CTBR_TSEL_Pos) /*!< 0x000000FF */
13673#define MDMA_CTBR_TSEL MDMA_CTBR_TSEL_Msk /*!< Trigger SELection */
13674#define MDMA_CTBR_SBUS_Pos (16U)
13675#define MDMA_CTBR_SBUS_Msk (0x1UL << MDMA_CTBR_SBUS_Pos) /*!< 0x00010000 */
13676#define MDMA_CTBR_SBUS MDMA_CTBR_SBUS_Msk /*!< Source BUS select */
13677#define MDMA_CTBR_DBUS_Pos (17U)
13678#define MDMA_CTBR_DBUS_Msk (0x1UL << MDMA_CTBR_DBUS_Pos) /*!< 0x00020000 */
13679#define MDMA_CTBR_DBUS MDMA_CTBR_DBUS_Msk /*!< Destination BUS select */
13680
13681/******************** Bit definition for MDMA_CxMAR) ************************/
13682#define MDMA_CMAR_MAR_Pos (0U)
13683#define MDMA_CMAR_MAR_Msk (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos) /*!< 0xFFFFFFFF */
13684#define MDMA_CMAR_MAR MDMA_CMAR_MAR_Msk /*!< Mask address */
13685
13686/******************** Bit definition for MDMA_CxMDR) ************************/
13687#define MDMA_CMDR_MDR_Pos (0U)
13688#define MDMA_CMDR_MDR_Msk (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos) /*!< 0xFFFFFFFF */
13689#define MDMA_CMDR_MDR MDMA_CMDR_MDR_Msk /*!< Mask Data */
13690
13691/******************************************************************************/
13692/* */
13693/* Operational Amplifier (OPAMP) */
13694/* */
13695/******************************************************************************/
13696/********************* Bit definition for OPAMPx_CSR register ***************/
13697#define OPAMP_CSR_OPAMPxEN_Pos (0U)
13698#define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
13699#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
13700#define OPAMP_CSR_FORCEVP_Pos (1U)
13701#define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */
13702#define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
13703
13704#define OPAMP_CSR_VPSEL_Pos (2U)
13705#define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
13706#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */
13707#define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
13708#define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
13709
13710#define OPAMP_CSR_VMSEL_Pos (5U)
13711#define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */
13712#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
13713#define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */
13714#define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */
13715
13716#define OPAMP_CSR_OPAHSM_Pos (8U)
13717#define OPAMP_CSR_OPAHSM_Msk (0x1UL << OPAMP_CSR_OPAHSM_Pos) /*!< 0x00000100 */
13718#define OPAMP_CSR_OPAHSM OPAMP_CSR_OPAHSM_Msk /*!< Operational amplifier high speed mode */
13719#define OPAMP_CSR_CALON_Pos (11U)
13720#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */
13721#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
13722
13723#define OPAMP_CSR_CALSEL_Pos (12U)
13724#define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */
13725#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
13726#define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */
13727#define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
13728
13729#define OPAMP_CSR_PGGAIN_Pos (14U)
13730#define OPAMP_CSR_PGGAIN_Msk (0xFUL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
13731#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */
13732#define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */
13733#define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */
13734#define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */
13735#define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */
13736
13737#define OPAMP_CSR_USERTRIM_Pos (18U)
13738#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00040000 */
13739#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
13740#define OPAMP_CSR_TSTREF_Pos (29U)
13741#define OPAMP_CSR_TSTREF_Msk (0x1UL << OPAMP_CSR_TSTREF_Pos) /*!< 0x20000000 */
13742#define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
13743#define OPAMP_CSR_CALOUT_Pos (30U)
13744#define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos) /*!< 0x40000000 */
13745#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier calibration output */
13746
13747/********************* Bit definition for OPAMP1_CSR register ***************/
13748#define OPAMP1_CSR_OPAEN_Pos (0U)
13749#define OPAMP1_CSR_OPAEN_Msk (0x1UL << OPAMP1_CSR_OPAEN_Pos) /*!< 0x00000001 */
13750#define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk /*!< Operational amplifier1 Enable */
13751#define OPAMP1_CSR_FORCEVP_Pos (1U)
13752#define OPAMP1_CSR_FORCEVP_Msk (0x1UL << OPAMP1_CSR_FORCEVP_Pos) /*!< 0x00000002 */
13753#define OPAMP1_CSR_FORCEVP OPAMP1_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
13754
13755#define OPAMP1_CSR_VPSEL_Pos (2U)
13756#define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
13757#define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverted input selection */
13758#define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
13759#define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
13760
13761#define OPAMP1_CSR_VMSEL_Pos (5U)
13762#define OPAMP1_CSR_VMSEL_Msk (0x3UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000060 */
13763#define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */
13764#define OPAMP1_CSR_VMSEL_0 (0x1UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000020 */
13765#define OPAMP1_CSR_VMSEL_1 (0x2UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000040 */
13766
13767#define OPAMP1_CSR_OPAHSM_Pos (8U)
13768#define OPAMP1_CSR_OPAHSM_Msk (0x1UL << OPAMP1_CSR_OPAHSM_Pos) /*!< 0x00000100 */
13769#define OPAMP1_CSR_OPAHSM OPAMP1_CSR_OPAHSM_Msk /*!< Operational amplifier1 high speed mode */
13770#define OPAMP1_CSR_CALON_Pos (11U)
13771#define OPAMP1_CSR_CALON_Msk (0x1UL << OPAMP1_CSR_CALON_Pos) /*!< 0x00000800 */
13772#define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */
13773
13774#define OPAMP1_CSR_CALSEL_Pos (12U)
13775#define OPAMP1_CSR_CALSEL_Msk (0x3UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00003000 */
13776#define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */
13777#define OPAMP1_CSR_CALSEL_0 (0x1UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00001000 */
13778#define OPAMP1_CSR_CALSEL_1 (0x2UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */
13779
13780#define OPAMP1_CSR_PGGAIN_Pos (14U)
13781#define OPAMP1_CSR_PGGAIN_Msk (0xFUL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
13782#define OPAMP1_CSR_PGGAIN OPAMP1_CSR_PGGAIN_Msk /*!< Operational amplifier1 Programmable amplifier gain value */
13783#define OPAMP1_CSR_PGGAIN_0 (0x1UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00004000 */
13784#define OPAMP1_CSR_PGGAIN_1 (0x2UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00008000 */
13785#define OPAMP1_CSR_PGGAIN_2 (0x4UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00010000 */
13786#define OPAMP1_CSR_PGGAIN_3 (0x8UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00020000 */
13787
13788#define OPAMP1_CSR_USERTRIM_Pos (18U)
13789#define OPAMP1_CSR_USERTRIM_Msk (0x1UL << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00040000 */
13790#define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */
13791#define OPAMP1_CSR_TSTREF_Pos (29U)
13792#define OPAMP1_CSR_TSTREF_Msk (0x1UL << OPAMP1_CSR_TSTREF_Pos) /*!< 0x20000000 */
13793#define OPAMP1_CSR_TSTREF OPAMP1_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
13794#define OPAMP1_CSR_CALOUT_Pos (30U)
13795#define OPAMP1_CSR_CALOUT_Msk (0x1UL << OPAMP1_CSR_CALOUT_Pos) /*!< 0x40000000 */
13796#define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
13797
13798/********************* Bit definition for OPAMP2_CSR register ***************/
13799#define OPAMP2_CSR_OPAEN_Pos (0U)
13800#define OPAMP2_CSR_OPAEN_Msk (0x1UL << OPAMP2_CSR_OPAEN_Pos) /*!< 0x00000001 */
13801#define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk /*!< Operational amplifier2 Enable */
13802#define OPAMP2_CSR_FORCEVP_Pos (1U)
13803#define OPAMP2_CSR_FORCEVP_Msk (0x1UL << OPAMP2_CSR_FORCEVP_Pos) /*!< 0x00000002 */
13804#define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
13805
13806#define OPAMP2_CSR_VPSEL_Pos (2U)
13807#define OPAMP2_CSR_VPSEL_Msk (0x3UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x0000000C */
13808#define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverted input selection */
13809#define OPAMP2_CSR_VPSEL_0 (0x1UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000004 */
13810#define OPAMP2_CSR_VPSEL_1 (0x2UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000008 */
13811
13812#define OPAMP2_CSR_VMSEL_Pos (5U)
13813#define OPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000060 */
13814#define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */
13815#define OPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000020 */
13816#define OPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000040 */
13817
13818#define OPAMP2_CSR_OPAHSM_Pos (8U)
13819#define OPAMP2_CSR_OPAHSM_Msk (0x1UL << OPAMP2_CSR_OPAHSM_Pos) /*!< 0x00000100 */
13820#define OPAMP2_CSR_OPAHSM OPAMP2_CSR_OPAHSM_Msk /*!< Operational amplifier2 high speed mode */
13821#define OPAMP2_CSR_CALON_Pos (11U)
13822#define OPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos) /*!< 0x00000800 */
13823#define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */
13824
13825#define OPAMP2_CSR_CALSEL_Pos (12U)
13826#define OPAMP2_CSR_CALSEL_Msk (0x3UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00003000 */
13827#define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */
13828#define OPAMP2_CSR_CALSEL_0 (0x1UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00001000 */
13829#define OPAMP2_CSR_CALSEL_1 (0x2UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */
13830
13831#define OPAMP2_CSR_PGGAIN_Pos (14U)
13832#define OPAMP2_CSR_PGGAIN_Msk (0xFUL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
13833#define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk /*!< Operational amplifier2 Programmable amplifier gain value */
13834#define OPAMP2_CSR_PGGAIN_0 (0x1UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00004000 */
13835#define OPAMP2_CSR_PGGAIN_1 (0x2UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00008000 */
13836#define OPAMP2_CSR_PGGAIN_2 (0x4UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00010000 */
13837#define OPAMP2_CSR_PGGAIN_3 (0x8UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00020000 */
13838
13839#define OPAMP2_CSR_USERTRIM_Pos (18U)
13840#define OPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00040000 */
13841#define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */
13842#define OPAMP2_CSR_TSTREF_Pos (29U)
13843#define OPAMP2_CSR_TSTREF_Msk (0x1UL << OPAMP2_CSR_TSTREF_Pos) /*!< 0x20000000 */
13844#define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
13845#define OPAMP2_CSR_CALOUT_Pos (30U)
13846#define OPAMP2_CSR_CALOUT_Msk (0x1UL << OPAMP2_CSR_CALOUT_Pos) /*!< 0x40000000 */
13847#define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk /*!< Operational amplifier2 calibration output */
13848
13849/******************* Bit definition for OPAMP_OTR register ******************/
13850#define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
13851#define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
13852#define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
13853#define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
13854#define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
13855#define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
13856
13857/******************* Bit definition for OPAMP1_OTR register ******************/
13858#define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
13859#define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
13860#define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
13861#define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
13862#define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
13863#define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
13864
13865/******************* Bit definition for OPAMP2_OTR register ******************/
13866#define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
13867#define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
13868#define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
13869#define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
13870#define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
13871#define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
13872
13873/******************* Bit definition for OPAMP_HSOTR register ****************/
13874#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos (0U)
13875#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
13876#define OPAMP_HSOTR_TRIMHSOFFSETN OPAMP_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
13877#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos (8U)
13878#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
13879#define OPAMP_HSOTR_TRIMHSOFFSETP OPAMP_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
13880
13881/******************* Bit definition for OPAMP1_HSOTR register ****************/
13882#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos (0U)
13883#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
13884#define OPAMP1_HSOTR_TRIMHSOFFSETN OPAMP1_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
13885#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos (8U)
13886#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
13887#define OPAMP1_HSOTR_TRIMHSOFFSETP OPAMP1_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
13888
13889/******************* Bit definition for OPAMP2_HSOTR register ****************/
13890#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos (0U)
13891#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
13892#define OPAMP2_HSOTR_TRIMHSOFFSETN OPAMP2_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
13893#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos (8U)
13894#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
13895#define OPAMP2_HSOTR_TRIMHSOFFSETP OPAMP2_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
13896
13897/******************************************************************************/
13898/* */
13899/* Power Control */
13900/* */
13901/******************************************************************************/
13902/************************* NUMBER OF POWER DOMAINS **************************/
13903#define POWER_DOMAINS_NUMBER 3U /*!< 3 Domains */
13904
13905/******************** Bit definition for PWR_CR1 register *******************/
13906#define PWR_CR1_ALS_Pos (17U)
13907#define PWR_CR1_ALS_Msk (0x3UL << PWR_CR1_ALS_Pos) /*!< 0x00060000 */
13908#define PWR_CR1_ALS PWR_CR1_ALS_Msk /*!< Analog Voltage Detector level selection */
13909#define PWR_CR1_ALS_0 (0x1UL << PWR_CR1_ALS_Pos) /*!< 0x00020000 */
13910#define PWR_CR1_ALS_1 (0x2UL << PWR_CR1_ALS_Pos) /*!< 0x00040000 */
13911#define PWR_CR1_AVDEN_Pos (16U)
13912#define PWR_CR1_AVDEN_Msk (0x1UL << PWR_CR1_AVDEN_Pos) /*!< 0x00010000 */
13913#define PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk /*!< Analog Voltage Detector Enable */
13914#define PWR_CR1_SVOS_Pos (14U)
13915#define PWR_CR1_SVOS_Msk (0x3UL << PWR_CR1_SVOS_Pos) /*!< 0x0000C000 */
13916#define PWR_CR1_SVOS PWR_CR1_SVOS_Msk /*!< System STOP mode Voltage Scaling selection */
13917#define PWR_CR1_SVOS_0 (0x1UL << PWR_CR1_SVOS_Pos) /*!< 0x00004000 */
13918#define PWR_CR1_SVOS_1 (0x2UL << PWR_CR1_SVOS_Pos) /*!< 0x00008000 */
13919#define PWR_CR1_FLPS_Pos (9U)
13920#define PWR_CR1_FLPS_Msk (0x1UL << PWR_CR1_FLPS_Pos) /*!< 0x00000200 */
13921#define PWR_CR1_FLPS PWR_CR1_FLPS_Msk /*!< Flash low power mode in DSTOP */
13922#define PWR_CR1_DBP_Pos (8U)
13923#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
13924#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
13925#define PWR_CR1_PLS_Pos (5U)
13926#define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos) /*!< 0x000000E0 */
13927#define PWR_CR1_PLS PWR_CR1_PLS_Msk /*!< Programmable Voltage Detector level selection */
13928#define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos) /*!< 0x00000020 */
13929#define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos) /*!< 0x00000040 */
13930#define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos) /*!< 0x00000080 */
13931#define PWR_CR1_PVDEN_Pos (4U)
13932#define PWR_CR1_PVDEN_Msk (0x1UL << PWR_CR1_PVDEN_Pos) /*!< 0x00000010 */
13933#define PWR_CR1_PVDEN PWR_CR1_PVDEN_Msk /*!< Programmable Voltage detector enable */
13934#define PWR_CR1_LPDS_Pos (0U)
13935#define PWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos) /*!< 0x00000001 */
13936#define PWR_CR1_LPDS PWR_CR1_LPDS_Msk /*!< Low Power Deepsleep with SVOS3 */
13937
13938/*!< PVD level configuration */
13939#define PWR_CR1_PLS_LEV0 (0UL) /*!< PVD level 0 */
13940#define PWR_CR1_PLS_LEV1_Pos (5U)
13941#define PWR_CR1_PLS_LEV1_Msk (0x1UL << PWR_CR1_PLS_LEV1_Pos) /*!< 0x00000020 */
13942#define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk /*!< PVD level 1 */
13943#define PWR_CR1_PLS_LEV2_Pos (6U)
13944#define PWR_CR1_PLS_LEV2_Msk (0x1UL << PWR_CR1_PLS_LEV2_Pos) /*!< 0x00000040 */
13945#define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk /*!< PVD level 2 */
13946#define PWR_CR1_PLS_LEV3_Pos (5U)
13947#define PWR_CR1_PLS_LEV3_Msk (0x3UL << PWR_CR1_PLS_LEV3_Pos) /*!< 0x00000060 */
13948#define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk /*!< PVD level 3 */
13949#define PWR_CR1_PLS_LEV4_Pos (7U)
13950#define PWR_CR1_PLS_LEV4_Msk (0x1UL << PWR_CR1_PLS_LEV4_Pos) /*!< 0x00000080 */
13951#define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk /*!< PVD level 4 */
13952#define PWR_CR1_PLS_LEV5_Pos (5U)
13953#define PWR_CR1_PLS_LEV5_Msk (0x5UL << PWR_CR1_PLS_LEV5_Pos) /*!< 0x000000A0 */
13954#define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk /*!< PVD level 5 */
13955#define PWR_CR1_PLS_LEV6_Pos (6U)
13956#define PWR_CR1_PLS_LEV6_Msk (0x3UL << PWR_CR1_PLS_LEV6_Pos) /*!< 0x000000C0 */
13957#define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk /*!< PVD level 6 */
13958#define PWR_CR1_PLS_LEV7_Pos (5U)
13959#define PWR_CR1_PLS_LEV7_Msk (0x7UL << PWR_CR1_PLS_LEV7_Pos) /*!< 0x000000E0 */
13960#define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk /*!< PVD level 7 */
13961
13962/*!< AVD level configuration */
13963#define PWR_CR1_ALS_LEV0 (0UL) /*!< AVD level 0 */
13964#define PWR_CR1_ALS_LEV1_Pos (17U)
13965#define PWR_CR1_ALS_LEV1_Msk (0x1UL << PWR_CR1_ALS_LEV1_Pos) /*!< 0x00020000 */
13966#define PWR_CR1_ALS_LEV1 PWR_CR1_ALS_LEV1_Msk /*!< AVD level 1 */
13967#define PWR_CR1_ALS_LEV2_Pos (18U)
13968#define PWR_CR1_ALS_LEV2_Msk (0x1UL << PWR_CR1_ALS_LEV2_Pos) /*!< 0x00040000 */
13969#define PWR_CR1_ALS_LEV2 PWR_CR1_ALS_LEV2_Msk /*!< AVD level 2 */
13970#define PWR_CR1_ALS_LEV3_Pos (17U)
13971#define PWR_CR1_ALS_LEV3_Msk (0x3UL << PWR_CR1_ALS_LEV3_Pos) /*!< 0x00060000 */
13972#define PWR_CR1_ALS_LEV3 PWR_CR1_ALS_LEV3_Msk /*!< AVD level 3 */
13973
13974/******************** Bit definition for PWR_CSR1 register ******************/
13975#define PWR_CSR1_AVDO_Pos (16U)
13976#define PWR_CSR1_AVDO_Msk (0x1UL << PWR_CSR1_AVDO_Pos) /*!< 0x00010000 */
13977#define PWR_CSR1_AVDO PWR_CSR1_AVDO_Msk /*!< Analog Voltage Detect Output */
13978#define PWR_CSR1_ACTVOS_Pos (14U)
13979#define PWR_CSR1_ACTVOS_Msk (0x3UL << PWR_CSR1_ACTVOS_Pos) /*!< 0x0000C000 */
13980#define PWR_CSR1_ACTVOS PWR_CSR1_ACTVOS_Msk /*!< Current actual used VOS for VDD11 Voltage Scaling */
13981#define PWR_CSR1_ACTVOS_0 (0x1UL << PWR_CSR1_ACTVOS_Pos) /*!< 0x00004000 */
13982#define PWR_CSR1_ACTVOS_1 (0x2UL << PWR_CSR1_ACTVOS_Pos) /*!< 0x00008000 */
13983#define PWR_CSR1_ACTVOSRDY_Pos (13U)
13984#define PWR_CSR1_ACTVOSRDY_Msk (0x1UL << PWR_CSR1_ACTVOSRDY_Pos) /*!< 0x00002000 */
13985#define PWR_CSR1_ACTVOSRDY PWR_CSR1_ACTVOSRDY_Msk /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling */
13986#define PWR_CSR1_PVDO_Pos (4U)
13987#define PWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos) /*!< 0x00000010 */
13988#define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk /*!< Programmable Voltage Detect Output */
13989
13990/******************** Bit definition for PWR_CR2 register *******************/
13991#define PWR_CR2_TEMPH_Pos (23U)
13992#define PWR_CR2_TEMPH_Msk (0x1UL << PWR_CR2_TEMPH_Pos) /*!< 0x00800000 */
13993#define PWR_CR2_TEMPH PWR_CR2_TEMPH_Msk /*!< Monitored temperature level above high threshold */
13994#define PWR_CR2_TEMPL_Pos (22U)
13995#define PWR_CR2_TEMPL_Msk (0x1UL << PWR_CR2_TEMPL_Pos) /*!< 0x00400000 */
13996#define PWR_CR2_TEMPL PWR_CR2_TEMPL_Msk /*!< Monitored temperature level above low threshold */
13997#define PWR_CR2_VBATH_Pos (21U)
13998#define PWR_CR2_VBATH_Msk (0x1UL << PWR_CR2_VBATH_Pos) /*!< 0x00200000 */
13999#define PWR_CR2_VBATH PWR_CR2_VBATH_Msk /*!< Monitored VBAT level above high threshold */
14000#define PWR_CR2_VBATL_Pos (20U)
14001#define PWR_CR2_VBATL_Msk (0x1UL << PWR_CR2_VBATL_Pos) /*!< 0x00100000 */
14002#define PWR_CR2_VBATL PWR_CR2_VBATL_Msk /*!< Monitored VBAT level above low threshold */
14003#define PWR_CR2_BRRDY_Pos (16U)
14004#define PWR_CR2_BRRDY_Msk (0x1UL << PWR_CR2_BRRDY_Pos) /*!< 0x00010000 */
14005#define PWR_CR2_BRRDY PWR_CR2_BRRDY_Msk /*!< Backup regulator ready */
14006#define PWR_CR2_MONEN_Pos (4U)
14007#define PWR_CR2_MONEN_Msk (0x1UL << PWR_CR2_MONEN_Pos) /*!< 0x00000010 */
14008#define PWR_CR2_MONEN PWR_CR2_MONEN_Msk /*!< VBAT and temperature monitoring enable */
14009#define PWR_CR2_BREN_Pos (0U)
14010#define PWR_CR2_BREN_Msk (0x1UL << PWR_CR2_BREN_Pos) /*!< 0x00000001 */
14011#define PWR_CR2_BREN PWR_CR2_BREN_Msk /*!< Backup regulator enable */
14012
14013/******************** Bit definition for PWR_CR3 register *******************/
14014#define PWR_CR3_USB33RDY_Pos (26U)
14015#define PWR_CR3_USB33RDY_Msk (0x1UL << PWR_CR3_USB33RDY_Pos) /*!< 0x04000000 */
14016#define PWR_CR3_USB33RDY PWR_CR3_USB33RDY_Msk /*!< USB supply ready */
14017#define PWR_CR3_USBREGEN_Pos (25U)
14018#define PWR_CR3_USBREGEN_Msk (0x1UL << PWR_CR3_USBREGEN_Pos) /*!< 0x02000000 */
14019#define PWR_CR3_USBREGEN PWR_CR3_USBREGEN_Msk /*!< USB regulator enable */
14020#define PWR_CR3_USB33DEN_Pos (24U)
14021#define PWR_CR3_USB33DEN_Msk (0x1UL << PWR_CR3_USB33DEN_Pos) /*!< 0x01000000 */
14022#define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk /*!< VDD33_USB voltage level detector enable */
14023#define PWR_CR3_VBRS_Pos (9U)
14024#define PWR_CR3_VBRS_Msk (0x1UL << PWR_CR3_VBRS_Pos) /*!< 0x00000200 */
14025#define PWR_CR3_VBRS PWR_CR3_VBRS_Msk /*!< VBAT charging resistor selection */
14026#define PWR_CR3_VBE_Pos (8U)
14027#define PWR_CR3_VBE_Msk (0x1UL << PWR_CR3_VBE_Pos) /*!< 0x00000100 */
14028#define PWR_CR3_VBE PWR_CR3_VBE_Msk /*!< VBAT charging enable */
14029#define PWR_CR3_SCUEN_Pos (2U)
14030#define PWR_CR3_SCUEN_Msk (0x1UL << PWR_CR3_SCUEN_Pos) /*!< 0x00000004 */
14031#define PWR_CR3_SCUEN PWR_CR3_SCUEN_Msk /*!< Supply configuration update enable */
14032#define PWR_CR3_LDOEN_Pos (1U)
14033#define PWR_CR3_LDOEN_Msk (0x1UL << PWR_CR3_LDOEN_Pos) /*!< 0x00000002 */
14034#define PWR_CR3_LDOEN PWR_CR3_LDOEN_Msk /*!< Low Drop Output regulator enable */
14035#define PWR_CR3_BYPASS_Pos (0U)
14036#define PWR_CR3_BYPASS_Msk (0x1UL << PWR_CR3_BYPASS_Pos) /*!< 0x00000001 */
14037#define PWR_CR3_BYPASS PWR_CR3_BYPASS_Msk /*!< Power Management Unit bypass */
14038
14039/******************** Bit definition for PWR_CPUCR register *****************/
14040#define PWR_CPUCR_RUN_D3_Pos (11U)
14041#define PWR_CPUCR_RUN_D3_Msk (0x1UL << PWR_CPUCR_RUN_D3_Pos) /*!< 0x00000800 */
14042#define PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_D3_Msk /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */
14043#define PWR_CPUCR_CSSF_Pos (9U)
14044#define PWR_CPUCR_CSSF_Msk (0x1UL << PWR_CPUCR_CSSF_Pos) /*!< 0x00000200 */
14045#define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */
14046#define PWR_CPUCR_SBF_D2_Pos (8U)
14047#define PWR_CPUCR_SBF_D2_Msk (0x1UL << PWR_CPUCR_SBF_D2_Pos) /*!< 0x00000100 */
14048#define PWR_CPUCR_SBF_D2 PWR_CPUCR_SBF_D2_Msk /*!< D2 domain DSTANDBY Flag */
14049#define PWR_CPUCR_SBF_D1_Pos (7U)
14050#define PWR_CPUCR_SBF_D1_Msk (0x1UL << PWR_CPUCR_SBF_D1_Pos) /*!< 0x00000080 */
14051#define PWR_CPUCR_SBF_D1 PWR_CPUCR_SBF_D1_Msk /*!< D1 domain DSTANDBY Flag */
14052#define PWR_CPUCR_SBF_Pos (6U)
14053#define PWR_CPUCR_SBF_Msk (0x1UL << PWR_CPUCR_SBF_Pos) /*!< 0x00000040 */
14054#define PWR_CPUCR_SBF PWR_CPUCR_SBF_Msk /*!< System STANDBY Flag */
14055#define PWR_CPUCR_STOPF_Pos (5U)
14056#define PWR_CPUCR_STOPF_Msk (0x1UL << PWR_CPUCR_STOPF_Pos) /*!< 0x00000020 */
14057#define PWR_CPUCR_STOPF PWR_CPUCR_STOPF_Msk /*!< STOP Flag */
14058#define PWR_CPUCR_PDDS_D3_Pos (2U)
14059#define PWR_CPUCR_PDDS_D3_Msk (0x1UL << PWR_CPUCR_PDDS_D3_Pos) /*!< 0x00000004 */
14060#define PWR_CPUCR_PDDS_D3 PWR_CPUCR_PDDS_D3_Msk /*!< System D3 domain Power Down Deepsleep */
14061#define PWR_CPUCR_PDDS_D2_Pos (1U)
14062#define PWR_CPUCR_PDDS_D2_Msk (0x1UL << PWR_CPUCR_PDDS_D2_Pos) /*!< 0x00000002 */
14063#define PWR_CPUCR_PDDS_D2 PWR_CPUCR_PDDS_D2_Msk /*!< D2 domain Power Down Deepsleep */
14064#define PWR_CPUCR_PDDS_D1_Pos (0U)
14065#define PWR_CPUCR_PDDS_D1_Msk (0x1UL << PWR_CPUCR_PDDS_D1_Pos) /*!< 0x00000001 */
14066#define PWR_CPUCR_PDDS_D1 PWR_CPUCR_PDDS_D1_Msk /*!< D1 domain Power Down Deepsleep selection */
14067
14068
14069/******************** Bit definition for PWR_D3CR register ******************/
14070#define PWR_D3CR_VOS_Pos (14U)
14071#define PWR_D3CR_VOS_Msk (0x3UL << PWR_D3CR_VOS_Pos) /*!< 0x0000C000 */
14072#define PWR_D3CR_VOS PWR_D3CR_VOS_Msk /*!< Voltage Scaling selection according performance */
14073#define PWR_D3CR_VOS_0 (0x1UL << PWR_D3CR_VOS_Pos) /*!< 0x00004000 */
14074#define PWR_D3CR_VOS_1 (0x2UL << PWR_D3CR_VOS_Pos) /*!< 0x00008000 */
14075#define PWR_D3CR_VOSRDY_Pos (13U)
14076#define PWR_D3CR_VOSRDY_Msk (0x1UL << PWR_D3CR_VOSRDY_Pos) /*!< 0x00002000 */
14077#define PWR_D3CR_VOSRDY PWR_D3CR_VOSRDY_Msk /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */
14078
14079/****************** Bit definition for PWR_WKUPCR register ******************/
14080#define PWR_WKUPCR_WKUPC6_Pos (5U)
14081#define PWR_WKUPCR_WKUPC6_Msk (0x1UL << PWR_WKUPCR_WKUPC6_Pos) /*!< 0x00000020 */
14082#define PWR_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6_Msk /*!< Clear Wakeup Pin Flag 6 */
14083#define PWR_WKUPCR_WKUPC5_Pos (4U)
14084#define PWR_WKUPCR_WKUPC5_Msk (0x1UL << PWR_WKUPCR_WKUPC5_Pos) /*!< 0x00000010 */
14085#define PWR_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5_Msk /*!< Clear Wakeup Pin Flag 5 */
14086#define PWR_WKUPCR_WKUPC4_Pos (3U)
14087#define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos) /*!< 0x00000008 */
14088#define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk /*!< Clear Wakeup Pin Flag 4 */
14089#define PWR_WKUPCR_WKUPC3_Pos (2U)
14090#define PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos) /*!< 0x00000004 */
14091#define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk /*!< Clear Wakeup Pin Flag 3 */
14092#define PWR_WKUPCR_WKUPC2_Pos (1U)
14093#define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos) /*!< 0x00000002 */
14094#define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk /*!< Clear Wakeup Pin Flag 2 */
14095#define PWR_WKUPCR_WKUPC1_Pos (0U)
14096#define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */
14097#define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Pin Flag 1 */
14098
14099/******************** Bit definition for PWR_WKUPFR register ****************/
14100#define PWR_WKUPFR_WKUPF6_Pos (5U)
14101#define PWR_WKUPFR_WKUPF6_Msk (0x1UL << PWR_WKUPFR_WKUPF6_Pos) /*!< 0x00000020 */
14102#define PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6_Msk /*!< Wakeup Pin Flag 6 */
14103#define PWR_WKUPFR_WKUPF5_Pos (4U)
14104#define PWR_WKUPFR_WKUPF5_Msk (0x1UL << PWR_WKUPFR_WKUPF5_Pos) /*!< 0x00000010 */
14105#define PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5_Msk /*!< Wakeup Pin Flag 5 */
14106#define PWR_WKUPFR_WKUPF4_Pos (3U)
14107#define PWR_WKUPFR_WKUPF4_Msk (0x1UL << PWR_WKUPFR_WKUPF4_Pos) /*!< 0x00000008 */
14108#define PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4_Msk /*!< Wakeup Pin Flag 4 */
14109#define PWR_WKUPFR_WKUPF3_Pos (2U)
14110#define PWR_WKUPFR_WKUPF3_Msk (0x1UL << PWR_WKUPFR_WKUPF3_Pos) /*!< 0x00000004 */
14111#define PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3_Msk /*!< Wakeup Pin Flag 3 */
14112#define PWR_WKUPFR_WKUPF2_Pos (1U)
14113#define PWR_WKUPFR_WKUPF2_Msk (0x1UL << PWR_WKUPFR_WKUPF2_Pos) /*!< 0x00000002 */
14114#define PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2_Msk /*!< Wakeup Pin Flag 2 */
14115#define PWR_WKUPFR_WKUPF1_Pos (0U)
14116#define PWR_WKUPFR_WKUPF1_Msk (0x1UL << PWR_WKUPFR_WKUPF1_Pos) /*!< 0x00000001 */
14117#define PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk /*!< Wakeup Pin Flag 1 */
14118
14119/****************** Bit definition for PWR_WKUPEPR register *****************/
14120#define PWR_WKUPEPR_WKUPPUPD6_Pos (26U)
14121#define PWR_WKUPEPR_WKUPPUPD6_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x0C000000 */
14122#define PWR_WKUPEPR_WKUPPUPD6 PWR_WKUPEPR_WKUPPUPD6_Msk /*!< Wakeup Pin pull configuration for WKUP6 */
14123#define PWR_WKUPEPR_WKUPPUPD6_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x04000000 */
14124#define PWR_WKUPEPR_WKUPPUPD6_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x08000000 */
14125#define PWR_WKUPEPR_WKUPPUPD5_Pos (24U)
14126#define PWR_WKUPEPR_WKUPPUPD5_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x03000000 */
14127#define PWR_WKUPEPR_WKUPPUPD5 PWR_WKUPEPR_WKUPPUPD5_Msk /*!< Wakeup Pin pull configuration for WKUP5 */
14128#define PWR_WKUPEPR_WKUPPUPD5_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x01000000 */
14129#define PWR_WKUPEPR_WKUPPUPD5_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x02000000 */
14130#define PWR_WKUPEPR_WKUPPUPD4_Pos (22U)
14131#define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00C00000 */
14132#define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk /*!< Wakeup Pin pull configuration for WKUP4 */
14133#define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00400000 */
14134#define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00800000 */
14135#define PWR_WKUPEPR_WKUPPUPD3_Pos (20U)
14136#define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00300000 */
14137#define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk /*!< Wakeup Pin pull configuration for WKUP3 */
14138#define PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00100000 */
14139#define PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00200000 */
14140#define PWR_WKUPEPR_WKUPPUPD2_Pos (18U)
14141#define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x000C0000 */
14142#define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk /*!< Wakeup Pin pull configuration for WKUP2 */
14143#define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00040000 */
14144#define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00080000 */
14145#define PWR_WKUPEPR_WKUPPUPD1_Pos (16U)
14146#define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00030000 */
14147#define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk /*!< Wakeup Pin pull configuration for WKUP1 */
14148#define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00010000 */
14149#define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00020000 */
14150#define PWR_WKUPEPR_WKUPP6_Pos (13U)
14151#define PWR_WKUPEPR_WKUPP6_Msk (0x1UL << PWR_WKUPEPR_WKUPP6_Pos) /*!< 0x00002000 */
14152#define PWR_WKUPEPR_WKUPP6 PWR_WKUPEPR_WKUPP6_Msk /*!< Wakeup Pin Polarity for WKUP6 */
14153#define PWR_WKUPEPR_WKUPP5_Pos (12U)
14154#define PWR_WKUPEPR_WKUPP5_Msk (0x1UL << PWR_WKUPEPR_WKUPP5_Pos) /*!< 0x00001000 */
14155#define PWR_WKUPEPR_WKUPP5 PWR_WKUPEPR_WKUPP5_Msk /*!< Wakeup Pin Polarity for WKUP5 */
14156#define PWR_WKUPEPR_WKUPP4_Pos (11U)
14157#define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos) /*!< 0x00000800 */
14158#define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk /*!< Wakeup Pin Polarity for WKUP4 */
14159#define PWR_WKUPEPR_WKUPP3_Pos (10U)
14160#define PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos) /*!< 0x00000400 */
14161#define PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk /*!< Wakeup Pin Polarity for WKUP3 */
14162#define PWR_WKUPEPR_WKUPP2_Pos (9U)
14163#define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos) /*!< 0x00000200 */
14164#define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk /*!< Wakeup Pin Polarity for WKUP2 */
14165#define PWR_WKUPEPR_WKUPP1_Pos (8U)
14166#define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos) /*!< 0x00000100 */
14167#define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk /*!< Wakeup Pin Polarity for WKUP1 */
14168#define PWR_WKUPEPR_WKUPEN6_Pos (5U)
14169#define PWR_WKUPEPR_WKUPEN6_Msk (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos) /*!< 0x00000020 */
14170#define PWR_WKUPEPR_WKUPEN6 PWR_WKUPEPR_WKUPEN6_Msk /*!< Enable Wakeup Pin WKUP6 */
14171#define PWR_WKUPEPR_WKUPEN5_Pos (4U)
14172#define PWR_WKUPEPR_WKUPEN5_Msk (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos) /*!< 0x00000010 */
14173#define PWR_WKUPEPR_WKUPEN5 PWR_WKUPEPR_WKUPEN5_Msk /*!< Enable Wakeup Pin WKUP5 */
14174#define PWR_WKUPEPR_WKUPEN4_Pos (3U)
14175#define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos) /*!< 0x00000008 */
14176#define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk /*!< Enable Wakeup Pin WKUP4 */
14177#define PWR_WKUPEPR_WKUPEN3_Pos (2U)
14178#define PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos) /*!< 0x00000004 */
14179#define PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk /*!< Enable Wakeup Pin WKUP3 */
14180#define PWR_WKUPEPR_WKUPEN2_Pos (1U)
14181#define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos) /*!< 0x00000002 */
14182#define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk /*!< Enable Wakeup Pin WKUP2 */
14183#define PWR_WKUPEPR_WKUPEN1_Pos (0U)
14184#define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos) /*!< 0x00000001 */
14185#define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk /*!< Enable Wakeup Pin WKUP1 */
14186#define PWR_WKUPEPR_WKUPEN_Pos (0U)
14187#define PWR_WKUPEPR_WKUPEN_Msk (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos) /*!< 0x0000003F */
14188#define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk /*!< Enable all Wakeup Pin */
14189
14190/******************************************************************************/
14191/* */
14192/* Reset and Clock Control */
14193/* */
14194/******************************************************************************/
14195/******************************* RCC VERSION ********************************/
14196#define RCC_VER_X
14197
14198/******************** Bit definition for RCC_CR register ********************/
14199#define RCC_CR_HSION_Pos (0U)
14200#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
14201#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
14202#define RCC_CR_HSIKERON_Pos (1U)
14203#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
14204#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
14205#define RCC_CR_HSIRDY_Pos (2U)
14206#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
14207#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
14208#define RCC_CR_HSIDIV_Pos (3U)
14209#define RCC_CR_HSIDIV_Msk (0x3UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000018 */
14210#define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk /*!< Internal High Speed clock divider selection */
14211#define RCC_CR_HSIDIV_1 (0x0UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000000 */
14212#define RCC_CR_HSIDIV_2 (0x1UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000008 */
14213#define RCC_CR_HSIDIV_4 (0x2UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000010 */
14214#define RCC_CR_HSIDIV_8 (0x3UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000018 */
14215
14216#define RCC_CR_HSIDIVF_Pos (5U)
14217#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000020 */
14218#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< HSI Divider flag */
14219#define RCC_CR_CSION_Pos (7U)
14220#define RCC_CR_CSION_Msk (0x1UL << RCC_CR_CSION_Pos) /*!< 0x00000080 */
14221#define RCC_CR_CSION RCC_CR_CSION_Msk /*!< The Internal RC 4MHz oscillator clock enable */
14222#define RCC_CR_CSIRDY_Pos (8U)
14223#define RCC_CR_CSIRDY_Msk (0x1UL << RCC_CR_CSIRDY_Pos) /*!< 0x00000100 */
14224#define RCC_CR_CSIRDY RCC_CR_CSIRDY_Msk /*!< The Internal RC 4MHz oscillator clock ready */
14225#define RCC_CR_CSIKERON_Pos (9U)
14226#define RCC_CR_CSIKERON_Msk (0x1UL << RCC_CR_CSIKERON_Pos) /*!< 0x00000200 */
14227#define RCC_CR_CSIKERON RCC_CR_CSIKERON_Msk /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */
14228#define RCC_CR_HSI48ON_Pos (12U)
14229#define RCC_CR_HSI48ON_Msk (0x1UL << RCC_CR_HSI48ON_Pos) /*!< 0x00001000 */
14230#define RCC_CR_HSI48ON RCC_CR_HSI48ON_Msk /*!< HSI48 clock enable clock enable */
14231#define RCC_CR_HSI48RDY_Pos (13U)
14232#define RCC_CR_HSI48RDY_Msk (0x1UL << RCC_CR_HSI48RDY_Pos) /*!< 0x00002000 */
14233#define RCC_CR_HSI48RDY RCC_CR_HSI48RDY_Msk /*!< HSI48 clock ready */
14234
14235#define RCC_CR_D1CKRDY_Pos (14U)
14236#define RCC_CR_D1CKRDY_Msk (0x1UL << RCC_CR_D1CKRDY_Pos) /*!< 0x00004000 */
14237#define RCC_CR_D1CKRDY RCC_CR_D1CKRDY_Msk /*!< D1 domain clocks ready flag */
14238#define RCC_CR_D2CKRDY_Pos (15U)
14239#define RCC_CR_D2CKRDY_Msk (0x1UL << RCC_CR_D2CKRDY_Pos) /*!< 0x00008000 */
14240#define RCC_CR_D2CKRDY RCC_CR_D2CKRDY_Msk /*!< D2 domain clocks ready flag */
14241
14242#define RCC_CR_HSEON_Pos (16U)
14243#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
14244#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
14245#define RCC_CR_HSERDY_Pos (17U)
14246#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
14247#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready */
14248#define RCC_CR_HSEBYP_Pos (18U)
14249#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
14250#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
14251#define RCC_CR_CSSHSEON_Pos (19U)
14252#define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
14253#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock security System enable */
14254
14255
14256#define RCC_CR_PLL1ON_Pos (24U)
14257#define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x01000000 */
14258#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< System PLL1 clock enable */
14259#define RCC_CR_PLL1RDY_Pos (25U)
14260#define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos) /*!< 0x02000000 */
14261#define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk /*!< System PLL1 clock ready */
14262#define RCC_CR_PLL2ON_Pos (26U)
14263#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */
14264#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< System PLL2 clock enable */
14265#define RCC_CR_PLL2RDY_Pos (27U)
14266#define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */
14267#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< System PLL2 clock ready */
14268#define RCC_CR_PLL3ON_Pos (28U)
14269#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */
14270#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< System PLL3 clock enable */
14271#define RCC_CR_PLL3RDY_Pos (29U)
14272#define RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos) /*!< 0x20000000 */
14273#define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk /*!< System PLL3 clock ready */
14274
14275/*Legacy */
14276#define RCC_CR_PLLON_Pos (24U)
14277#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
14278#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
14279#define RCC_CR_PLLRDY_Pos (25U)
14280#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
14281#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
14282
14283/******************** Bit definition for RCC_HSICFGR register ***************/
14284/*!< HSICAL configuration */
14285#define RCC_HSICFGR_HSICAL_Pos (0U)
14286#define RCC_HSICFGR_HSICAL_Msk (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */
14287#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSICAL[11:0] bits */
14288#define RCC_HSICFGR_HSICAL_0 (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */
14289#define RCC_HSICFGR_HSICAL_1 (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */
14290#define RCC_HSICFGR_HSICAL_2 (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */
14291#define RCC_HSICFGR_HSICAL_3 (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */
14292#define RCC_HSICFGR_HSICAL_4 (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */
14293#define RCC_HSICFGR_HSICAL_5 (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */
14294#define RCC_HSICFGR_HSICAL_6 (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */
14295#define RCC_HSICFGR_HSICAL_7 (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */
14296#define RCC_HSICFGR_HSICAL_8 (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */
14297#define RCC_HSICFGR_HSICAL_9 (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */
14298#define RCC_HSICFGR_HSICAL_10 (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */
14299#define RCC_HSICFGR_HSICAL_11 (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */
14300
14301/*!< HSITRIM configuration */
14302#define RCC_HSICFGR_HSITRIM_Pos (24U)
14303#define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */
14304#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
14305#define RCC_HSICFGR_HSITRIM_0 (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */
14306#define RCC_HSICFGR_HSITRIM_1 (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */
14307#define RCC_HSICFGR_HSITRIM_2 (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */
14308#define RCC_HSICFGR_HSITRIM_3 (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */
14309#define RCC_HSICFGR_HSITRIM_4 (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */
14310#define RCC_HSICFGR_HSITRIM_5 (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */
14311#define RCC_HSICFGR_HSITRIM_6 (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */
14312
14313
14314/******************** Bit definition for RCC_CRRCR register *****************/
14315
14316/*!< HSI48CAL configuration */
14317#define RCC_CRRCR_HSI48CAL_Pos (0U)
14318#define RCC_CRRCR_HSI48CAL_Msk (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */
14319#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[9:0] bits */
14320#define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */
14321#define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */
14322#define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */
14323#define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */
14324#define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */
14325#define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */
14326#define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */
14327#define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
14328#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
14329#define RCC_CRRCR_HSI48CAL_9 (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
14330
14331
14332/******************** Bit definition for RCC_CSICFGR register *****************/
14333/*!< CSICAL configuration */
14334#define RCC_CSICFGR_CSICAL_Pos (0U)
14335#define RCC_CSICFGR_CSICAL_Msk (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */
14336#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSICAL[7:0] bits */
14337#define RCC_CSICFGR_CSICAL_0 (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */
14338#define RCC_CSICFGR_CSICAL_1 (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */
14339#define RCC_CSICFGR_CSICAL_2 (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */
14340#define RCC_CSICFGR_CSICAL_3 (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */
14341#define RCC_CSICFGR_CSICAL_4 (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */
14342#define RCC_CSICFGR_CSICAL_5 (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */
14343#define RCC_CSICFGR_CSICAL_6 (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */
14344#define RCC_CSICFGR_CSICAL_7 (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */
14345
14346/*!< CSITRIM configuration */
14347#define RCC_CSICFGR_CSITRIM_Pos (24U)
14348#define RCC_CSICFGR_CSITRIM_Msk (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */
14349#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSITRIM[5:0] bits */
14350#define RCC_CSICFGR_CSITRIM_0 (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */
14351#define RCC_CSICFGR_CSITRIM_1 (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */
14352#define RCC_CSICFGR_CSITRIM_2 (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */
14353#define RCC_CSICFGR_CSITRIM_3 (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */
14354#define RCC_CSICFGR_CSITRIM_4 (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */
14355#define RCC_CSICFGR_CSITRIM_5 (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */
14356
14357/******************** Bit definition for RCC_CFGR register ******************/
14358/*!< SW configuration */
14359#define RCC_CFGR_SW_Pos (0U)
14360#define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos) /*!< 0x00000007 */
14361#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[2:0] bits (System clock Switch) */
14362#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
14363#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
14364#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */
14365
14366#define RCC_CFGR_SW_HSI (0x00000000UL) /*!< HSI selection as system clock */
14367#define RCC_CFGR_SW_CSI (0x00000001UL) /*!< CSI selection as system clock */
14368#define RCC_CFGR_SW_HSE (0x00000002UL) /*!< HSE selection as system clock */
14369#define RCC_CFGR_SW_PLL1 (0x00000003UL) /*!< PLL1 selection as system clock */
14370
14371/*!< SWS configuration */
14372#define RCC_CFGR_SWS_Pos (3U)
14373#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */
14374#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[2:0] bits (System Clock Switch Status) */
14375#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
14376#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */
14377#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */
14378
14379#define RCC_CFGR_SWS_HSI (0x00000000UL) /*!< HSI used as system clock */
14380#define RCC_CFGR_SWS_CSI (0x00000008UL) /*!< CSI used as system clock */
14381#define RCC_CFGR_SWS_HSE (0x00000010UL) /*!< HSE used as system clock */
14382#define RCC_CFGR_SWS_PLL1 (0x00000018UL) /*!< PLL1 used as system clock */
14383
14384#define RCC_CFGR_STOPWUCK_Pos (6U)
14385#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00000040 */
14386#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */
14387
14388#define RCC_CFGR_STOPKERWUCK_Pos (7U)
14389#define RCC_CFGR_STOPKERWUCK_Msk (0x1UL << RCC_CFGR_STOPKERWUCK_Pos) /*!< 0x00000080 */
14390#define RCC_CFGR_STOPKERWUCK RCC_CFGR_STOPKERWUCK_Msk /*!< Kernel Clock Selection after a Wake Up from STOP */
14391
14392/*!< RTCPRE configuration */
14393#define RCC_CFGR_RTCPRE_Pos (8U)
14394#define RCC_CFGR_RTCPRE_Msk (0x3FUL << RCC_CFGR_RTCPRE_Pos)
14395#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk /*!< 0x00003F00 */
14396#define RCC_CFGR_RTCPRE_0 (0x1UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000100 */
14397#define RCC_CFGR_RTCPRE_1 (0x2UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000200 */
14398#define RCC_CFGR_RTCPRE_2 (0x4UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000400 */
14399#define RCC_CFGR_RTCPRE_3 (0x8UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000800 */
14400#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00001000 */
14401#define RCC_CFGR_RTCPRE_5 (0x20UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00002000 */
14402
14403/*!< HRTIMSEL configuration */
14404#define RCC_CFGR_HRTIMSEL_Pos (14U)
14405#define RCC_CFGR_HRTIMSEL_Msk (0x1UL << RCC_CFGR_HRTIMSEL_Pos)
14406#define RCC_CFGR_HRTIMSEL RCC_CFGR_HRTIMSEL_Msk /*!< 0x00004000 */
14407
14408/*!< TIMPRE configuration */
14409#define RCC_CFGR_TIMPRE_Pos (15U)
14410#define RCC_CFGR_TIMPRE_Msk (0x1UL << RCC_CFGR_TIMPRE_Pos)
14411#define RCC_CFGR_TIMPRE RCC_CFGR_TIMPRE_Msk /*!< 0x00008000 */
14412
14413/*!< MCO1 configuration */
14414#define RCC_CFGR_MCO1_Pos (22U)
14415#define RCC_CFGR_MCO1_Msk (0x7UL << RCC_CFGR_MCO1_Pos)
14416#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk /*!< 0x01C00000 */
14417#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
14418#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos) /*!< 0x00800000 */
14419#define RCC_CFGR_MCO1_2 (0x4UL << RCC_CFGR_MCO1_Pos) /*!< 0x01000000 */
14420
14421#define RCC_CFGR_MCO1PRE_Pos (18U)
14422#define RCC_CFGR_MCO1PRE_Msk (0xFUL << RCC_CFGR_MCO1PRE_Pos)
14423#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk /*!< 0x003C0000 */
14424#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00040000 */
14425#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00080000 */
14426#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00100000 */
14427#define RCC_CFGR_MCO1PRE_3 (0x8UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00200000 */
14428
14429#define RCC_CFGR_MCO2PRE_Pos (25U)
14430#define RCC_CFGR_MCO2PRE_Msk (0xFUL << RCC_CFGR_MCO2PRE_Pos)
14431#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk /*!< 0x1E000000 */
14432#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x02000000 */
14433#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x04000000 */
14434#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
14435#define RCC_CFGR_MCO2PRE_3 (0x8UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
14436
14437#define RCC_CFGR_MCO2_Pos (29U)
14438#define RCC_CFGR_MCO2_Msk (0x7UL << RCC_CFGR_MCO2_Pos)
14439#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk /*!< 0xE0000000 */
14440#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos) /*!< 0x20000000 */
14441#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
14442#define RCC_CFGR_MCO2_2 (0x4UL << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
14443
14444/******************** Bit definition for RCC_D1CFGR register ******************/
14445/*!< D1HPRE configuration */
14446#define RCC_D1CFGR_HPRE_Pos (0U)
14447#define RCC_D1CFGR_HPRE_Msk (0xFUL << RCC_D1CFGR_HPRE_Pos) /*!< 0x0000000F */
14448#define RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB3 prescaler) */
14449#define RCC_D1CFGR_HPRE_0 (0x1UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000001 */
14450#define RCC_D1CFGR_HPRE_1 (0x2UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000002 */
14451#define RCC_D1CFGR_HPRE_2 (0x4UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000004 */
14452#define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */
14453
14454
14455#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
14456#define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
14457#define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
14458#define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
14459#define RCC_D1CFGR_HPRE_DIV4_Pos (0U)
14460#define RCC_D1CFGR_HPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos) /*!< 0x00000009 */
14461#define RCC_D1CFGR_HPRE_DIV4 RCC_D1CFGR_HPRE_DIV4_Msk /*!< AHB3 Clock divided by 4 */
14462#define RCC_D1CFGR_HPRE_DIV8_Pos (1U)
14463#define RCC_D1CFGR_HPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos) /*!< 0x0000000A */
14464#define RCC_D1CFGR_HPRE_DIV8 RCC_D1CFGR_HPRE_DIV8_Msk /*!< AHB3 Clock divided by 8 */
14465#define RCC_D1CFGR_HPRE_DIV16_Pos (0U)
14466#define RCC_D1CFGR_HPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos) /*!< 0x0000000B */
14467#define RCC_D1CFGR_HPRE_DIV16 RCC_D1CFGR_HPRE_DIV16_Msk /*!< AHB3 Clock divided by 16 */
14468#define RCC_D1CFGR_HPRE_DIV64_Pos (2U)
14469#define RCC_D1CFGR_HPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos) /*!< 0x0000000C */
14470#define RCC_D1CFGR_HPRE_DIV64 RCC_D1CFGR_HPRE_DIV64_Msk /*!< AHB3 Clock divided by 64 */
14471#define RCC_D1CFGR_HPRE_DIV128_Pos (0U)
14472#define RCC_D1CFGR_HPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos) /*!< 0x0000000D */
14473#define RCC_D1CFGR_HPRE_DIV128 RCC_D1CFGR_HPRE_DIV128_Msk /*!< AHB3 Clock divided by 128 */
14474#define RCC_D1CFGR_HPRE_DIV256_Pos (1U)
14475#define RCC_D1CFGR_HPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos) /*!< 0x0000000E */
14476#define RCC_D1CFGR_HPRE_DIV256 RCC_D1CFGR_HPRE_DIV256_Msk /*!< AHB3 Clock divided by 256 */
14477#define RCC_D1CFGR_HPRE_DIV512_Pos (0U)
14478#define RCC_D1CFGR_HPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos) /*!< 0x0000000F */
14479#define RCC_D1CFGR_HPRE_DIV512 RCC_D1CFGR_HPRE_DIV512_Msk /*!< AHB3 Clock divided by 512 */
14480
14481/*!< D1PPRE configuration */
14482#define RCC_D1CFGR_D1PPRE_Pos (4U)
14483#define RCC_D1CFGR_D1PPRE_Msk (0x7UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000070 */
14484#define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk /*!< D1PRE[2:0] bits (APB3 prescaler) */
14485#define RCC_D1CFGR_D1PPRE_0 (0x1UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000010 */
14486#define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
14487#define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
14488
14489#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
14490#define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
14491#define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
14492#define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
14493#define RCC_D1CFGR_D1PPRE_DIV4_Pos (4U)
14494#define RCC_D1CFGR_D1PPRE_DIV4_Msk (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos) /*!< 0x00000050 */
14495#define RCC_D1CFGR_D1PPRE_DIV4 RCC_D1CFGR_D1PPRE_DIV4_Msk /*!< APB3 clock divided by 4 */
14496#define RCC_D1CFGR_D1PPRE_DIV8_Pos (5U)
14497#define RCC_D1CFGR_D1PPRE_DIV8_Msk (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos) /*!< 0x00000060 */
14498#define RCC_D1CFGR_D1PPRE_DIV8 RCC_D1CFGR_D1PPRE_DIV8_Msk /*!< APB3 clock divided by 8 */
14499#define RCC_D1CFGR_D1PPRE_DIV16_Pos (4U)
14500#define RCC_D1CFGR_D1PPRE_DIV16_Msk (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos) /*!< 0x00000070 */
14501#define RCC_D1CFGR_D1PPRE_DIV16 RCC_D1CFGR_D1PPRE_DIV16_Msk /*!< APB3 clock divided by 16 */
14502
14503#define RCC_D1CFGR_D1CPRE_Pos (8U)
14504#define RCC_D1CFGR_D1CPRE_Msk (0xFUL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000F00 */
14505#define RCC_D1CFGR_D1CPRE RCC_D1CFGR_D1CPRE_Msk /*!< D1CPRE[2:0] bits (Domain 1 Core prescaler) */
14506#define RCC_D1CFGR_D1CPRE_0 (0x1UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000100 */
14507#define RCC_D1CFGR_D1CPRE_1 (0x2UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000200 */
14508#define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
14509#define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
14510
14511#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
14512#define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
14513#define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
14514#define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
14515#define RCC_D1CFGR_D1CPRE_DIV4_Pos (8U)
14516#define RCC_D1CFGR_D1CPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos) /*!< 0x00000900 */
14517#define RCC_D1CFGR_D1CPRE_DIV4 RCC_D1CFGR_D1CPRE_DIV4_Msk /*!< Domain 1 Core clock divided by 4 */
14518#define RCC_D1CFGR_D1CPRE_DIV8_Pos (9U)
14519#define RCC_D1CFGR_D1CPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos) /*!< 0x00000A00 */
14520#define RCC_D1CFGR_D1CPRE_DIV8 RCC_D1CFGR_D1CPRE_DIV8_Msk /*!< Domain 1 Core clock divided by 8 */
14521#define RCC_D1CFGR_D1CPRE_DIV16_Pos (8U)
14522#define RCC_D1CFGR_D1CPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos) /*!< 0x00000B00 */
14523#define RCC_D1CFGR_D1CPRE_DIV16 RCC_D1CFGR_D1CPRE_DIV16_Msk /*!< Domain 1 Core clock divided by 16 */
14524#define RCC_D1CFGR_D1CPRE_DIV64_Pos (10U)
14525#define RCC_D1CFGR_D1CPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos) /*!< 0x00000C00 */
14526#define RCC_D1CFGR_D1CPRE_DIV64 RCC_D1CFGR_D1CPRE_DIV64_Msk /*!< Domain 1 Core clock divided by 64 */
14527#define RCC_D1CFGR_D1CPRE_DIV128_Pos (8U)
14528#define RCC_D1CFGR_D1CPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos) /*!< 0x00000D00 */
14529#define RCC_D1CFGR_D1CPRE_DIV128 RCC_D1CFGR_D1CPRE_DIV128_Msk /*!< Domain 1 Core clock divided by 128 */
14530#define RCC_D1CFGR_D1CPRE_DIV256_Pos (9U)
14531#define RCC_D1CFGR_D1CPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos) /*!< 0x00000E00 */
14532#define RCC_D1CFGR_D1CPRE_DIV256 RCC_D1CFGR_D1CPRE_DIV256_Msk /*!< Domain 1 Core clock divided by 256 */
14533#define RCC_D1CFGR_D1CPRE_DIV512_Pos (8U)
14534#define RCC_D1CFGR_D1CPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos) /*!< 0x00000F00 */
14535#define RCC_D1CFGR_D1CPRE_DIV512 RCC_D1CFGR_D1CPRE_DIV512_Msk /*!< Domain 1 Core clock divided by 512 */
14536
14537/******************** Bit definition for RCC_D2CFGR register ******************/
14538/*!< D2PPRE1 configuration */
14539#define RCC_D2CFGR_D2PPRE1_Pos (4U)
14540#define RCC_D2CFGR_D2PPRE1_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000070 */
14541#define RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_Msk /*!< D1PPRE1[2:0] bits (APB1 prescaler) */
14542#define RCC_D2CFGR_D2PPRE1_0 (0x1UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000010 */
14543#define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
14544#define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
14545
14546#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
14547#define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
14548#define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
14549#define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
14550#define RCC_D2CFGR_D2PPRE1_DIV4_Pos (4U)
14551#define RCC_D2CFGR_D2PPRE1_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos) /*!< 0x00000050 */
14552#define RCC_D2CFGR_D2PPRE1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4_Msk /*!< APB1 clock divided by 4 */
14553#define RCC_D2CFGR_D2PPRE1_DIV8_Pos (5U)
14554#define RCC_D2CFGR_D2PPRE1_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos) /*!< 0x00000060 */
14555#define RCC_D2CFGR_D2PPRE1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8_Msk /*!< APB1 clock divided by 8 */
14556#define RCC_D2CFGR_D2PPRE1_DIV16_Pos (4U)
14557#define RCC_D2CFGR_D2PPRE1_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos) /*!< 0x00000070 */
14558#define RCC_D2CFGR_D2PPRE1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16_Msk /*!< APB1 clock divided by 16 */
14559
14560/*!< D2PPRE2 configuration */
14561#define RCC_D2CFGR_D2PPRE2_Pos (8U)
14562#define RCC_D2CFGR_D2PPRE2_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000700 */
14563#define RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_Msk /*!< D2PPRE2[2:0] bits (APB2 prescaler) */
14564#define RCC_D2CFGR_D2PPRE2_0 (0x1UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000100 */
14565#define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
14566#define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
14567
14568#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
14569#define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
14570#define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
14571#define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
14572#define RCC_D2CFGR_D2PPRE2_DIV4_Pos (8U)
14573#define RCC_D2CFGR_D2PPRE2_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos) /*!< 0x00000500 */
14574#define RCC_D2CFGR_D2PPRE2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4_Msk /*!< APB2 clock divided by 4 */
14575#define RCC_D2CFGR_D2PPRE2_DIV8_Pos (9U)
14576#define RCC_D2CFGR_D2PPRE2_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos) /*!< 0x00000600 */
14577#define RCC_D2CFGR_D2PPRE2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8_Msk /*!< APB2 clock divided by 8 */
14578#define RCC_D2CFGR_D2PPRE2_DIV16_Pos (8U)
14579#define RCC_D2CFGR_D2PPRE2_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos) /*!< 0x00000700 */
14580#define RCC_D2CFGR_D2PPRE2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16_Msk /*!< APB2 clock divided by 16 */
14581
14582/******************** Bit definition for RCC_D3CFGR register ******************/
14583/*!< D3PPRE configuration */
14584#define RCC_D3CFGR_D3PPRE_Pos (4U)
14585#define RCC_D3CFGR_D3PPRE_Msk (0x7UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000070 */
14586#define RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_Msk /*!< D3PPRE1[2:0] bits (APB4 prescaler) */
14587#define RCC_D3CFGR_D3PPRE_0 (0x1UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000010 */
14588#define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
14589#define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
14590
14591#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
14592#define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
14593#define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
14594#define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
14595#define RCC_D3CFGR_D3PPRE_DIV4_Pos (4U)
14596#define RCC_D3CFGR_D3PPRE_DIV4_Msk (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos) /*!< 0x00000050 */
14597#define RCC_D3CFGR_D3PPRE_DIV4 RCC_D3CFGR_D3PPRE_DIV4_Msk /*!< APB4 clock divided by 4 */
14598#define RCC_D3CFGR_D3PPRE_DIV8_Pos (5U)
14599#define RCC_D3CFGR_D3PPRE_DIV8_Msk (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos) /*!< 0x00000060 */
14600#define RCC_D3CFGR_D3PPRE_DIV8 RCC_D3CFGR_D3PPRE_DIV8_Msk /*!< APB4 clock divided by 8 */
14601#define RCC_D3CFGR_D3PPRE_DIV16_Pos (4U)
14602#define RCC_D3CFGR_D3PPRE_DIV16_Msk (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos) /*!< 0x00000070 */
14603#define RCC_D3CFGR_D3PPRE_DIV16 RCC_D3CFGR_D3PPRE_DIV16_Msk /*!< APB4 clock divided by 16 */
14604
14605/******************** Bit definition for RCC_PLLCKSELR register *************/
14606
14607#define RCC_PLLCKSELR_PLLSRC_Pos (0U)
14608#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
14609#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
14610
14611#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
14612#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
14613#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
14614#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
14615#define RCC_PLLCKSELR_PLLSRC_HSE_Pos (1U)
14616#define RCC_PLLCKSELR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */
14617#define RCC_PLLCKSELR_PLLSRC_HSE RCC_PLLCKSELR_PLLSRC_HSE_Msk /*!< HSE source clock selected */
14618#define RCC_PLLCKSELR_PLLSRC_NONE_Pos (0U)
14619#define RCC_PLLCKSELR_PLLSRC_NONE_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */
14620#define RCC_PLLCKSELR_PLLSRC_NONE RCC_PLLCKSELR_PLLSRC_NONE_Msk /*!< No source clock selected */
14621
14622#define RCC_PLLCKSELR_DIVM1_Pos (4U)
14623#define RCC_PLLCKSELR_DIVM1_Msk (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */
14624#define RCC_PLLCKSELR_DIVM1 RCC_PLLCKSELR_DIVM1_Msk
14625#define RCC_PLLCKSELR_DIVM1_0 (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */
14626#define RCC_PLLCKSELR_DIVM1_1 (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */
14627#define RCC_PLLCKSELR_DIVM1_2 (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */
14628#define RCC_PLLCKSELR_DIVM1_3 (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */
14629#define RCC_PLLCKSELR_DIVM1_4 (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */
14630#define RCC_PLLCKSELR_DIVM1_5 (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */
14631
14632#define RCC_PLLCKSELR_DIVM2_Pos (12U)
14633#define RCC_PLLCKSELR_DIVM2_Msk (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */
14634#define RCC_PLLCKSELR_DIVM2 RCC_PLLCKSELR_DIVM2_Msk
14635#define RCC_PLLCKSELR_DIVM2_0 (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */
14636#define RCC_PLLCKSELR_DIVM2_1 (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */
14637#define RCC_PLLCKSELR_DIVM2_2 (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */
14638#define RCC_PLLCKSELR_DIVM2_3 (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */
14639#define RCC_PLLCKSELR_DIVM2_4 (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */
14640#define RCC_PLLCKSELR_DIVM2_5 (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */
14641
14642#define RCC_PLLCKSELR_DIVM3_Pos (20U)
14643#define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */
14644#define RCC_PLLCKSELR_DIVM3 RCC_PLLCKSELR_DIVM3_Msk
14645#define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */
14646#define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */
14647#define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */
14648#define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */
14649#define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */
14650#define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */
14651
14652/******************** Bit definition for RCC_PLLCFGR register ***************/
14653
14654#define RCC_PLLCFGR_PLL1FRACEN_Pos (0U)
14655#define RCC_PLLCFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */
14656#define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_Msk
14657#define RCC_PLLCFGR_PLL1VCOSEL_Pos (1U)
14658#define RCC_PLLCFGR_PLL1VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */
14659#define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_Msk
14660#define RCC_PLLCFGR_PLL1RGE_Pos (2U)
14661#define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
14662#define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_Msk
14663#define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
14664#define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
14665#define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
14666#define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
14667
14668#define RCC_PLLCFGR_PLL2FRACEN_Pos (4U)
14669#define RCC_PLLCFGR_PLL2FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */
14670#define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_Msk
14671#define RCC_PLLCFGR_PLL2VCOSEL_Pos (5U)
14672#define RCC_PLLCFGR_PLL2VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */
14673#define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_Msk
14674#define RCC_PLLCFGR_PLL2RGE_Pos (6U)
14675#define RCC_PLLCFGR_PLL2RGE_Msk (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
14676#define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_Msk
14677#define RCC_PLLCFGR_PLL2RGE_0 (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */
14678#define RCC_PLLCFGR_PLL2RGE_1 (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */
14679#define RCC_PLLCFGR_PLL2RGE_2 (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */
14680#define RCC_PLLCFGR_PLL2RGE_3 (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
14681
14682#define RCC_PLLCFGR_PLL3FRACEN_Pos (8U)
14683#define RCC_PLLCFGR_PLL3FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */
14684#define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_Msk
14685#define RCC_PLLCFGR_PLL3VCOSEL_Pos (9U)
14686#define RCC_PLLCFGR_PLL3VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */
14687#define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_Msk
14688#define RCC_PLLCFGR_PLL3RGE_Pos (10U)
14689#define RCC_PLLCFGR_PLL3RGE_Msk (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
14690#define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_Msk
14691#define RCC_PLLCFGR_PLL3RGE_0 (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */
14692#define RCC_PLLCFGR_PLL3RGE_1 (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */
14693#define RCC_PLLCFGR_PLL3RGE_2 (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */
14694#define RCC_PLLCFGR_PLL3RGE_3 (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
14695
14696#define RCC_PLLCFGR_DIVP1EN_Pos (16U)
14697#define RCC_PLLCFGR_DIVP1EN_Msk (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */
14698#define RCC_PLLCFGR_DIVP1EN RCC_PLLCFGR_DIVP1EN_Msk
14699#define RCC_PLLCFGR_DIVQ1EN_Pos (17U)
14700#define RCC_PLLCFGR_DIVQ1EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */
14701#define RCC_PLLCFGR_DIVQ1EN RCC_PLLCFGR_DIVQ1EN_Msk
14702#define RCC_PLLCFGR_DIVR1EN_Pos (18U)
14703#define RCC_PLLCFGR_DIVR1EN_Msk (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */
14704#define RCC_PLLCFGR_DIVR1EN RCC_PLLCFGR_DIVR1EN_Msk
14705
14706#define RCC_PLLCFGR_DIVP2EN_Pos (19U)
14707#define RCC_PLLCFGR_DIVP2EN_Msk (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */
14708#define RCC_PLLCFGR_DIVP2EN RCC_PLLCFGR_DIVP2EN_Msk
14709#define RCC_PLLCFGR_DIVQ2EN_Pos (20U)
14710#define RCC_PLLCFGR_DIVQ2EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */
14711#define RCC_PLLCFGR_DIVQ2EN RCC_PLLCFGR_DIVQ2EN_Msk
14712#define RCC_PLLCFGR_DIVR2EN_Pos (21U)
14713#define RCC_PLLCFGR_DIVR2EN_Msk (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */
14714#define RCC_PLLCFGR_DIVR2EN RCC_PLLCFGR_DIVR2EN_Msk
14715
14716#define RCC_PLLCFGR_DIVP3EN_Pos (22U)
14717#define RCC_PLLCFGR_DIVP3EN_Msk (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */
14718#define RCC_PLLCFGR_DIVP3EN RCC_PLLCFGR_DIVP3EN_Msk
14719#define RCC_PLLCFGR_DIVQ3EN_Pos (23U)
14720#define RCC_PLLCFGR_DIVQ3EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */
14721#define RCC_PLLCFGR_DIVQ3EN RCC_PLLCFGR_DIVQ3EN_Msk
14722#define RCC_PLLCFGR_DIVR3EN_Pos (24U)
14723#define RCC_PLLCFGR_DIVR3EN_Msk (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */
14724#define RCC_PLLCFGR_DIVR3EN RCC_PLLCFGR_DIVR3EN_Msk
14725
14726
14727/******************** Bit definition for RCC_PLL1DIVR register ***************/
14728#define RCC_PLL1DIVR_N1_Pos (0U)
14729#define RCC_PLL1DIVR_N1_Msk (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */
14730#define RCC_PLL1DIVR_N1 RCC_PLL1DIVR_N1_Msk
14731#define RCC_PLL1DIVR_P1_Pos (9U)
14732#define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
14733#define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk
14734#define RCC_PLL1DIVR_Q1_Pos (16U)
14735#define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
14736#define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
14737#define RCC_PLL1DIVR_R1_Pos (24U)
14738#define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
14739#define RCC_PLL1DIVR_R1 RCC_PLL1DIVR_R1_Msk
14740
14741/******************** Bit definition for RCC_PLL1FRACR register ***************/
14742#define RCC_PLL1FRACR_FRACN1_Pos (3U)
14743#define RCC_PLL1FRACR_FRACN1_Msk (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */
14744#define RCC_PLL1FRACR_FRACN1 RCC_PLL1FRACR_FRACN1_Msk
14745
14746/******************** Bit definition for RCC_PLL2DIVR register ***************/
14747#define RCC_PLL2DIVR_N2_Pos (0U)
14748#define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
14749#define RCC_PLL2DIVR_N2 RCC_PLL2DIVR_N2_Msk
14750#define RCC_PLL2DIVR_P2_Pos (9U)
14751#define RCC_PLL2DIVR_P2_Msk (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */
14752#define RCC_PLL2DIVR_P2 RCC_PLL2DIVR_P2_Msk
14753#define RCC_PLL2DIVR_Q2_Pos (16U)
14754#define RCC_PLL2DIVR_Q2_Msk (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */
14755#define RCC_PLL2DIVR_Q2 RCC_PLL2DIVR_Q2_Msk
14756#define RCC_PLL2DIVR_R2_Pos (24U)
14757#define RCC_PLL2DIVR_R2_Msk (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */
14758#define RCC_PLL2DIVR_R2 RCC_PLL2DIVR_R2_Msk
14759
14760/******************** Bit definition for RCC_PLL2FRACR register ***************/
14761#define RCC_PLL2FRACR_FRACN2_Pos (3U)
14762#define RCC_PLL2FRACR_FRACN2_Msk (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */
14763#define RCC_PLL2FRACR_FRACN2 RCC_PLL2FRACR_FRACN2_Msk
14764
14765/******************** Bit definition for RCC_PLL3DIVR register ***************/
14766#define RCC_PLL3DIVR_N3_Pos (0U)
14767#define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
14768#define RCC_PLL3DIVR_N3 RCC_PLL3DIVR_N3_Msk
14769#define RCC_PLL3DIVR_P3_Pos (9U)
14770#define RCC_PLL3DIVR_P3_Msk (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */
14771#define RCC_PLL3DIVR_P3 RCC_PLL3DIVR_P3_Msk
14772#define RCC_PLL3DIVR_Q3_Pos (16U)
14773#define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
14774#define RCC_PLL3DIVR_Q3 RCC_PLL3DIVR_Q3_Msk
14775#define RCC_PLL3DIVR_R3_Pos (24U)
14776#define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
14777#define RCC_PLL3DIVR_R3 RCC_PLL3DIVR_R3_Msk
14778
14779/******************** Bit definition for RCC_PLL3FRACR register ***************/
14780#define RCC_PLL3FRACR_FRACN3_Pos (3U)
14781#define RCC_PLL3FRACR_FRACN3_Msk (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */
14782#define RCC_PLL3FRACR_FRACN3 RCC_PLL3FRACR_FRACN3_Msk
14783
14784/******************** Bit definition for RCC_D1CCIPR register ***************/
14785#define RCC_D1CCIPR_FMCSEL_Pos (0U)
14786#define RCC_D1CCIPR_FMCSEL_Msk (0x3UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000003 */
14787#define RCC_D1CCIPR_FMCSEL RCC_D1CCIPR_FMCSEL_Msk
14788#define RCC_D1CCIPR_FMCSEL_0 (0x1UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000001 */
14789#define RCC_D1CCIPR_FMCSEL_1 (0x2UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000002 */
14790#define RCC_D1CCIPR_QSPISEL_Pos (4U)
14791#define RCC_D1CCIPR_QSPISEL_Msk (0x3UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000030 */
14792#define RCC_D1CCIPR_QSPISEL RCC_D1CCIPR_QSPISEL_Msk
14793#define RCC_D1CCIPR_QSPISEL_0 (0x1UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000010 */
14794#define RCC_D1CCIPR_QSPISEL_1 (0x2UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000020 */
14795#define RCC_D1CCIPR_SDMMCSEL_Pos (16U)
14796#define RCC_D1CCIPR_SDMMCSEL_Msk (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */
14797#define RCC_D1CCIPR_SDMMCSEL RCC_D1CCIPR_SDMMCSEL_Msk
14798#define RCC_D1CCIPR_CKPERSEL_Pos (28U)
14799#define RCC_D1CCIPR_CKPERSEL_Msk (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x30000000 */
14800#define RCC_D1CCIPR_CKPERSEL RCC_D1CCIPR_CKPERSEL_Msk
14801#define RCC_D1CCIPR_CKPERSEL_0 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x10000000 */
14802#define RCC_D1CCIPR_CKPERSEL_1 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x20000000 */
14803
14804/******************** Bit definition for RCC_D2CCIP1R register ***************/
14805#define RCC_D2CCIP1R_SAI1SEL_Pos (0U)
14806#define RCC_D2CCIP1R_SAI1SEL_Msk (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */
14807#define RCC_D2CCIP1R_SAI1SEL RCC_D2CCIP1R_SAI1SEL_Msk
14808#define RCC_D2CCIP1R_SAI1SEL_0 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */
14809#define RCC_D2CCIP1R_SAI1SEL_1 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */
14810#define RCC_D2CCIP1R_SAI1SEL_2 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */
14811
14812#define RCC_D2CCIP1R_SAI23SEL_Pos (6U)
14813#define RCC_D2CCIP1R_SAI23SEL_Msk (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x000001C0 */
14814#define RCC_D2CCIP1R_SAI23SEL RCC_D2CCIP1R_SAI23SEL_Msk
14815#define RCC_D2CCIP1R_SAI23SEL_0 (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000040 */
14816#define RCC_D2CCIP1R_SAI23SEL_1 (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000080 */
14817#define RCC_D2CCIP1R_SAI23SEL_2 (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000100 */
14818
14819#define RCC_D2CCIP1R_SPI123SEL_Pos (12U)
14820#define RCC_D2CCIP1R_SPI123SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */
14821#define RCC_D2CCIP1R_SPI123SEL RCC_D2CCIP1R_SPI123SEL_Msk
14822#define RCC_D2CCIP1R_SPI123SEL_0 (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */
14823#define RCC_D2CCIP1R_SPI123SEL_1 (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */
14824#define RCC_D2CCIP1R_SPI123SEL_2 (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */
14825
14826#define RCC_D2CCIP1R_SPI45SEL_Pos (16U)
14827#define RCC_D2CCIP1R_SPI45SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */
14828#define RCC_D2CCIP1R_SPI45SEL RCC_D2CCIP1R_SPI45SEL_Msk
14829#define RCC_D2CCIP1R_SPI45SEL_0 (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */
14830#define RCC_D2CCIP1R_SPI45SEL_1 (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */
14831#define RCC_D2CCIP1R_SPI45SEL_2 (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */
14832
14833#define RCC_D2CCIP1R_SPDIFSEL_Pos (20U)
14834#define RCC_D2CCIP1R_SPDIFSEL_Msk (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */
14835#define RCC_D2CCIP1R_SPDIFSEL RCC_D2CCIP1R_SPDIFSEL_Msk
14836#define RCC_D2CCIP1R_SPDIFSEL_0 (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */
14837#define RCC_D2CCIP1R_SPDIFSEL_1 (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */
14838
14839#define RCC_D2CCIP1R_DFSDM1SEL_Pos (24U)
14840#define RCC_D2CCIP1R_DFSDM1SEL_Msk (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */
14841#define RCC_D2CCIP1R_DFSDM1SEL RCC_D2CCIP1R_DFSDM1SEL_Msk
14842
14843#define RCC_D2CCIP1R_FDCANSEL_Pos (28U)
14844#define RCC_D2CCIP1R_FDCANSEL_Msk (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */
14845#define RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_Msk
14846#define RCC_D2CCIP1R_FDCANSEL_0 (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */
14847#define RCC_D2CCIP1R_FDCANSEL_1 (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */
14848
14849#define RCC_D2CCIP1R_SWPSEL_Pos (31U)
14850#define RCC_D2CCIP1R_SWPSEL_Msk (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos) /*!< 0x80000000 */
14851#define RCC_D2CCIP1R_SWPSEL RCC_D2CCIP1R_SWPSEL_Msk
14852
14853/******************** Bit definition for RCC_D2CCIP2R register ***************/
14854#define RCC_D2CCIP2R_USART16SEL_Pos (3U)
14855#define RCC_D2CCIP2R_USART16SEL_Msk (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000038 */
14856#define RCC_D2CCIP2R_USART16SEL RCC_D2CCIP2R_USART16SEL_Msk
14857#define RCC_D2CCIP2R_USART16SEL_0 (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000008 */
14858#define RCC_D2CCIP2R_USART16SEL_1 (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000010 */
14859#define RCC_D2CCIP2R_USART16SEL_2 (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000020 */
14860
14861#define RCC_D2CCIP2R_USART28SEL_Pos (0U)
14862#define RCC_D2CCIP2R_USART28SEL_Msk (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000007 */
14863#define RCC_D2CCIP2R_USART28SEL RCC_D2CCIP2R_USART28SEL_Msk
14864#define RCC_D2CCIP2R_USART28SEL_0 (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000001 */
14865#define RCC_D2CCIP2R_USART28SEL_1 (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000002 */
14866#define RCC_D2CCIP2R_USART28SEL_2 (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000004 */
14867
14868#define RCC_D2CCIP2R_RNGSEL_Pos (8U)
14869#define RCC_D2CCIP2R_RNGSEL_Msk (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000300 */
14870#define RCC_D2CCIP2R_RNGSEL RCC_D2CCIP2R_RNGSEL_Msk
14871#define RCC_D2CCIP2R_RNGSEL_0 (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000100 */
14872#define RCC_D2CCIP2R_RNGSEL_1 (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000200 */
14873
14874#define RCC_D2CCIP2R_I2C123SEL_Pos (12U)
14875#define RCC_D2CCIP2R_I2C123SEL_Msk (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00003000 */
14876#define RCC_D2CCIP2R_I2C123SEL RCC_D2CCIP2R_I2C123SEL_Msk
14877#define RCC_D2CCIP2R_I2C123SEL_0 (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00001000 */
14878#define RCC_D2CCIP2R_I2C123SEL_1 (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00002000 */
14879
14880#define RCC_D2CCIP2R_USBSEL_Pos (20U)
14881#define RCC_D2CCIP2R_USBSEL_Msk (0x3UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00300000 */
14882#define RCC_D2CCIP2R_USBSEL RCC_D2CCIP2R_USBSEL_Msk
14883#define RCC_D2CCIP2R_USBSEL_0 (0x1UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00100000 */
14884#define RCC_D2CCIP2R_USBSEL_1 (0x2UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00200000 */
14885
14886#define RCC_D2CCIP2R_CECSEL_Pos (22U)
14887#define RCC_D2CCIP2R_CECSEL_Msk (0x3UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00C00000 */
14888#define RCC_D2CCIP2R_CECSEL RCC_D2CCIP2R_CECSEL_Msk
14889#define RCC_D2CCIP2R_CECSEL_0 (0x1UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00400000 */
14890#define RCC_D2CCIP2R_CECSEL_1 (0x2UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00800000 */
14891
14892#define RCC_D2CCIP2R_LPTIM1SEL_Pos (28U)
14893#define RCC_D2CCIP2R_LPTIM1SEL_Msk (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */
14894#define RCC_D2CCIP2R_LPTIM1SEL RCC_D2CCIP2R_LPTIM1SEL_Msk
14895#define RCC_D2CCIP2R_LPTIM1SEL_0 (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */
14896#define RCC_D2CCIP2R_LPTIM1SEL_1 (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */
14897#define RCC_D2CCIP2R_LPTIM1SEL_2 (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */
14898
14899/******************** Bit definition for RCC_D3CCIPR register ***************/
14900#define RCC_D3CCIPR_LPUART1SEL_Pos (0U)
14901#define RCC_D3CCIPR_LPUART1SEL_Msk (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */
14902#define RCC_D3CCIPR_LPUART1SEL RCC_D3CCIPR_LPUART1SEL_Msk
14903#define RCC_D3CCIPR_LPUART1SEL_0 (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */
14904#define RCC_D3CCIPR_LPUART1SEL_1 (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */
14905#define RCC_D3CCIPR_LPUART1SEL_2 (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */
14906
14907#define RCC_D3CCIPR_I2C4SEL_Pos (8U)
14908#define RCC_D3CCIPR_I2C4SEL_Msk (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000300 */
14909#define RCC_D3CCIPR_I2C4SEL RCC_D3CCIPR_I2C4SEL_Msk
14910#define RCC_D3CCIPR_I2C4SEL_0 (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000100 */
14911#define RCC_D3CCIPR_I2C4SEL_1 (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000200 */
14912
14913#define RCC_D3CCIPR_LPTIM2SEL_Pos (10U)
14914#define RCC_D3CCIPR_LPTIM2SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */
14915#define RCC_D3CCIPR_LPTIM2SEL RCC_D3CCIPR_LPTIM2SEL_Msk
14916#define RCC_D3CCIPR_LPTIM2SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */
14917#define RCC_D3CCIPR_LPTIM2SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */
14918#define RCC_D3CCIPR_LPTIM2SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */
14919
14920#define RCC_D3CCIPR_LPTIM345SEL_Pos (13U)
14921#define RCC_D3CCIPR_LPTIM345SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x0000E000 */
14922#define RCC_D3CCIPR_LPTIM345SEL RCC_D3CCIPR_LPTIM345SEL_Msk
14923#define RCC_D3CCIPR_LPTIM345SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00002000 */
14924#define RCC_D3CCIPR_LPTIM345SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00004000 */
14925#define RCC_D3CCIPR_LPTIM345SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00008000 */
14926
14927#define RCC_D3CCIPR_SAI4ASEL_Pos (21U)
14928#define RCC_D3CCIPR_SAI4ASEL_Msk (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00E00000 */
14929#define RCC_D3CCIPR_SAI4ASEL RCC_D3CCIPR_SAI4ASEL_Msk
14930#define RCC_D3CCIPR_SAI4ASEL_0 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00200000 */
14931#define RCC_D3CCIPR_SAI4ASEL_1 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00400000 */
14932#define RCC_D3CCIPR_SAI4ASEL_2 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00800000 */
14933
14934#define RCC_D3CCIPR_SAI4BSEL_Pos (24U)
14935#define RCC_D3CCIPR_SAI4BSEL_Msk (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x07000000 */
14936#define RCC_D3CCIPR_SAI4BSEL RCC_D3CCIPR_SAI4BSEL_Msk
14937#define RCC_D3CCIPR_SAI4BSEL_0 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x01000000 */
14938#define RCC_D3CCIPR_SAI4BSEL_1 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x02000000 */
14939#define RCC_D3CCIPR_SAI4BSEL_2 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x04000000 */
14940
14941#define RCC_D3CCIPR_ADCSEL_Pos (16U)
14942#define RCC_D3CCIPR_ADCSEL_Msk (0x3UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00030000 */
14943#define RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_Msk
14944#define RCC_D3CCIPR_ADCSEL_0 (0x1UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00010000 */
14945#define RCC_D3CCIPR_ADCSEL_1 (0x2UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00020000 */
14946
14947#define RCC_D3CCIPR_SPI6SEL_Pos (28U)
14948#define RCC_D3CCIPR_SPI6SEL_Msk (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x70000000 */
14949#define RCC_D3CCIPR_SPI6SEL RCC_D3CCIPR_SPI6SEL_Msk
14950#define RCC_D3CCIPR_SPI6SEL_0 (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x10000000 */
14951#define RCC_D3CCIPR_SPI6SEL_1 (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x20000000 */
14952#define RCC_D3CCIPR_SPI6SEL_2 (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x40000000 */
14953/******************** Bit definition for RCC_CIER register ******************/
14954#define RCC_CIER_LSIRDYIE_Pos (0U)
14955#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
14956#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
14957#define RCC_CIER_LSERDYIE_Pos (1U)
14958#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
14959#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
14960#define RCC_CIER_HSIRDYIE_Pos (2U)
14961#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
14962#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
14963#define RCC_CIER_HSERDYIE_Pos (3U)
14964#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
14965#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
14966#define RCC_CIER_CSIRDYIE_Pos (4U)
14967#define RCC_CIER_CSIRDYIE_Msk (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */
14968#define RCC_CIER_CSIRDYIE RCC_CIER_CSIRDYIE_Msk
14969#define RCC_CIER_HSI48RDYIE_Pos (5U)
14970#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */
14971#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
14972#define RCC_CIER_PLL1RDYIE_Pos (6U)
14973#define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */
14974#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk
14975#define RCC_CIER_PLL2RDYIE_Pos (7U)
14976#define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */
14977#define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk
14978#define RCC_CIER_PLL3RDYIE_Pos (8U)
14979#define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */
14980#define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk
14981#define RCC_CIER_LSECSSIE_Pos (9U)
14982#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
14983#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
14984
14985/******************** Bit definition for RCC_CIFR register ******************/
14986#define RCC_CIFR_LSIRDYF_Pos (0U)
14987#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
14988#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
14989#define RCC_CIFR_LSERDYF_Pos (1U)
14990#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
14991#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
14992#define RCC_CIFR_HSIRDYF_Pos (2U)
14993#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
14994#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
14995#define RCC_CIFR_HSERDYF_Pos (3U)
14996#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
14997#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
14998#define RCC_CIFR_CSIRDYF_Pos (4U)
14999#define RCC_CIFR_CSIRDYF_Msk (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */
15000#define RCC_CIFR_CSIRDYF RCC_CIFR_CSIRDYF_Msk
15001#define RCC_CIFR_HSI48RDYF_Pos (5U)
15002#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */
15003#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
15004#define RCC_CIFR_PLLRDYF_Pos (6U)
15005#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */
15006#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
15007#define RCC_CIFR_PLL2RDYF_Pos (7U)
15008#define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */
15009#define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk
15010#define RCC_CIFR_PLL3RDYF_Pos (8U)
15011#define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */
15012#define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk
15013#define RCC_CIFR_LSECSSF_Pos (9U)
15014#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
15015#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
15016#define RCC_CIFR_HSECSSF_Pos (10U)
15017#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */
15018#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk
15019
15020/******************** Bit definition for RCC_CICR register ******************/
15021#define RCC_CICR_LSIRDYC_Pos (0U)
15022#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
15023#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
15024#define RCC_CICR_LSERDYC_Pos (1U)
15025#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
15026#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
15027#define RCC_CICR_HSIRDYC_Pos (2U)
15028#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
15029#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
15030#define RCC_CICR_HSERDYC_Pos (3U)
15031#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
15032#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
15033#define RCC_CICR_CSIRDYC_Pos (4U)
15034#define RCC_CICR_CSIRDYC_Msk (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */
15035#define RCC_CICR_CSIRDYC RCC_CICR_CSIRDYC_Msk
15036#define RCC_CICR_HSI48RDYC_Pos (5U)
15037#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */
15038#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
15039#define RCC_CICR_PLLRDYC_Pos (6U)
15040#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */
15041#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
15042#define RCC_CICR_PLL2RDYC_Pos (7U)
15043#define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */
15044#define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk
15045#define RCC_CICR_PLL3RDYC_Pos (8U)
15046#define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */
15047#define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk
15048#define RCC_CICR_LSECSSC_Pos (9U)
15049#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
15050#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
15051#define RCC_CICR_HSECSSC_Pos (10U)
15052#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */
15053#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk
15054
15055/******************** Bit definition for RCC_BDCR register ******************/
15056#define RCC_BDCR_LSEON_Pos (0U)
15057#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
15058#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
15059#define RCC_BDCR_LSERDY_Pos (1U)
15060#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
15061#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
15062#define RCC_BDCR_LSEBYP_Pos (2U)
15063#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
15064#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
15065
15066#define RCC_BDCR_LSEDRV_Pos (3U)
15067#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
15068#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
15069#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
15070#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
15071
15072#define RCC_BDCR_LSECSSON_Pos (5U)
15073#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
15074#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
15075#define RCC_BDCR_LSECSSD_Pos (6U)
15076#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
15077#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
15078
15079#define RCC_BDCR_RTCSEL_Pos (8U)
15080#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
15081#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
15082#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
15083#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
15084
15085#define RCC_BDCR_RTCEN_Pos (15U)
15086#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
15087#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
15088#define RCC_BDCR_BDRST_Pos (16U)
15089#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
15090#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
15091/******************** Bit definition for RCC_CSR register *******************/
15092#define RCC_CSR_LSION_Pos (0U)
15093#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
15094#define RCC_CSR_LSION RCC_CSR_LSION_Msk
15095#define RCC_CSR_LSIRDY_Pos (1U)
15096#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
15097#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
15098
15099
15100/******************** Bit definition for RCC_AHB3ENR register **************/
15101#define RCC_AHB3ENR_MDMAEN_Pos (0U)
15102#define RCC_AHB3ENR_MDMAEN_Msk (0x1UL << RCC_AHB3ENR_MDMAEN_Pos) /*!< 0x00000001 */
15103#define RCC_AHB3ENR_MDMAEN RCC_AHB3ENR_MDMAEN_Msk
15104#define RCC_AHB3ENR_DMA2DEN_Pos (4U)
15105#define RCC_AHB3ENR_DMA2DEN_Msk (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos) /*!< 0x00000010 */
15106#define RCC_AHB3ENR_DMA2DEN RCC_AHB3ENR_DMA2DEN_Msk
15107#define RCC_AHB3ENR_JPGDECEN_Pos (5U)
15108#define RCC_AHB3ENR_JPGDECEN_Msk (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos) /*!< 0x00000020 */
15109#define RCC_AHB3ENR_JPGDECEN RCC_AHB3ENR_JPGDECEN_Msk
15110#define RCC_AHB3ENR_FMCEN_Pos (12U)
15111#define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00001000 */
15112#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
15113#define RCC_AHB3ENR_QSPIEN_Pos (14U)
15114#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00004000 */
15115#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
15116#define RCC_AHB3ENR_SDMMC1EN_Pos (16U)
15117#define RCC_AHB3ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos) /*!< 0x00010000 */
15118#define RCC_AHB3ENR_SDMMC1EN RCC_AHB3ENR_SDMMC1EN_Msk
15119
15120/******************** Bit definition for RCC_AHB1ENR register ***************/
15121#define RCC_AHB1ENR_DMA1EN_Pos (0U)
15122#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
15123#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
15124#define RCC_AHB1ENR_DMA2EN_Pos (1U)
15125#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
15126#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
15127#define RCC_AHB1ENR_ADC12EN_Pos (5U)
15128#define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos) /*!< 0x00000020 */
15129#define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk
15130#define RCC_AHB1ENR_ETH1MACEN_Pos (15U)
15131#define RCC_AHB1ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos) /*!< 0x00008000 */
15132#define RCC_AHB1ENR_ETH1MACEN RCC_AHB1ENR_ETH1MACEN_Msk
15133#define RCC_AHB1ENR_ETH1TXEN_Pos (16U)
15134#define RCC_AHB1ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos) /*!< 0x00010000 */
15135#define RCC_AHB1ENR_ETH1TXEN RCC_AHB1ENR_ETH1TXEN_Msk
15136#define RCC_AHB1ENR_ETH1RXEN_Pos (17U)
15137#define RCC_AHB1ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos) /*!< 0x00020000 */
15138#define RCC_AHB1ENR_ETH1RXEN RCC_AHB1ENR_ETH1RXEN_Msk
15139#define RCC_AHB1ENR_USB1OTGHSEN_Pos (25U)
15140#define RCC_AHB1ENR_USB1OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos) /*!< 0x02000000 */
15141#define RCC_AHB1ENR_USB1OTGHSEN RCC_AHB1ENR_USB1OTGHSEN_Msk
15142#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos (26U)
15143#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */
15144#define RCC_AHB1ENR_USB1OTGHSULPIEN RCC_AHB1ENR_USB1OTGHSULPIEN_Msk
15145#define RCC_AHB1ENR_USB2OTGFSEN_Pos (27U)
15146#define RCC_AHB1ENR_USB2OTGFSEN_Msk (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos) /*!< 0x08000000 */
15147#define RCC_AHB1ENR_USB2OTGFSEN RCC_AHB1ENR_USB2OTGFSEN_Msk
15148#define RCC_AHB1ENR_USB2OTGFSULPIEN_Pos (28U)
15149#define RCC_AHB1ENR_USB2OTGFSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos) /*!< 0x10000000 */
15150#define RCC_AHB1ENR_USB2OTGFSULPIEN RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
15151
15152/* Legacy define */
15153#define RCC_AHB1ENR_USB2OTGHSEN_Pos RCC_AHB1ENR_USB2OTGFSEN_Pos
15154#define RCC_AHB1ENR_USB2OTGHSEN_Msk RCC_AHB1ENR_USB2OTGFSEN_Msk
15155#define RCC_AHB1ENR_USB2OTGHSEN RCC_AHB1ENR_USB2OTGFSEN
15156#define RCC_AHB1ENR_USB2OTGHSULPIEN_Pos RCC_AHB1ENR_USB2OTGFSULPIEN_Pos
15157#define RCC_AHB1ENR_USB2OTGHSULPIEN_Msk RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
15158#define RCC_AHB1ENR_USB2OTGHSULPIEN RCC_AHB1ENR_USB2OTGFSULPIEN
15159
15160
15161/******************** Bit definition for RCC_AHB2ENR register ***************/
15162#define RCC_AHB2ENR_DCMIEN_Pos (0U)
15163#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
15164#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
15165#define RCC_AHB2ENR_CRYPEN_Pos (4U)
15166#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
15167#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
15168#define RCC_AHB2ENR_HASHEN_Pos (5U)
15169#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
15170#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
15171#define RCC_AHB2ENR_RNGEN_Pos (6U)
15172#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
15173#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
15174#define RCC_AHB2ENR_SDMMC2EN_Pos (9U)
15175#define RCC_AHB2ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos) /*!< 0x00000200 */
15176#define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk
15177#define RCC_AHB2ENR_SRAM1EN_Pos (29U)
15178#define RCC_AHB2ENR_SRAM1EN_Msk (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos) /*!< 0x20000000 */
15179#define RCC_AHB2ENR_SRAM1EN RCC_AHB2ENR_SRAM1EN_Msk
15180#define RCC_AHB2ENR_SRAM2EN_Pos (30U)
15181#define RCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos) /*!< 0x40000000 */
15182#define RCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk
15183#define RCC_AHB2ENR_SRAM3EN_Pos (31U)
15184#define RCC_AHB2ENR_SRAM3EN_Msk (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos) /*!< 0x80000000 */
15185#define RCC_AHB2ENR_SRAM3EN RCC_AHB2ENR_SRAM3EN_Msk
15186
15187/* Legacy define */
15188#define RCC_AHB2ENR_D2SRAM1EN_Pos RCC_AHB2ENR_SRAM1EN_Pos
15189#define RCC_AHB2ENR_D2SRAM1EN_Msk RCC_AHB2ENR_SRAM1EN_Msk
15190#define RCC_AHB2ENR_D2SRAM1EN RCC_AHB2ENR_SRAM1EN
15191#define RCC_AHB2ENR_D2SRAM2EN_Pos RCC_AHB2ENR_SRAM2EN_Pos
15192#define RCC_AHB2ENR_D2SRAM2EN_Msk RCC_AHB2ENR_SRAM2EN_Msk
15193#define RCC_AHB2ENR_D2SRAM2EN RCC_AHB2ENR_SRAM2EN
15194#define RCC_AHB2ENR_D2SRAM3EN_Pos RCC_AHB2ENR_SRAM3EN_Pos
15195#define RCC_AHB2ENR_D2SRAM3EN_Msk RCC_AHB2ENR_SRAM3EN_Msk
15196#define RCC_AHB2ENR_D2SRAM3EN RCC_AHB2ENR_SRAM3EN
15197
15198/******************** Bit definition for RCC_AHB4ENR register ******************/
15199#define RCC_AHB4ENR_GPIOAEN_Pos (0U)
15200#define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos) /*!< 0x00000001 */
15201#define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk
15202#define RCC_AHB4ENR_GPIOBEN_Pos (1U)
15203#define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos) /*!< 0x00000002 */
15204#define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk
15205#define RCC_AHB4ENR_GPIOCEN_Pos (2U)
15206#define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos) /*!< 0x00000004 */
15207#define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk
15208#define RCC_AHB4ENR_GPIODEN_Pos (3U)
15209#define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos) /*!< 0x00000008 */
15210#define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk
15211#define RCC_AHB4ENR_GPIOEEN_Pos (4U)
15212#define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos) /*!< 0x00000010 */
15213#define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk
15214#define RCC_AHB4ENR_GPIOFEN_Pos (5U)
15215#define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos) /*!< 0x00000020 */
15216#define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk
15217#define RCC_AHB4ENR_GPIOGEN_Pos (6U)
15218#define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos) /*!< 0x00000040 */
15219#define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk
15220#define RCC_AHB4ENR_GPIOHEN_Pos (7U)
15221#define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos) /*!< 0x00000080 */
15222#define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk
15223#define RCC_AHB4ENR_GPIOIEN_Pos (8U)
15224#define RCC_AHB4ENR_GPIOIEN_Msk (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos) /*!< 0x00000100 */
15225#define RCC_AHB4ENR_GPIOIEN RCC_AHB4ENR_GPIOIEN_Msk
15226#define RCC_AHB4ENR_GPIOJEN_Pos (9U)
15227#define RCC_AHB4ENR_GPIOJEN_Msk (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos) /*!< 0x00000200 */
15228#define RCC_AHB4ENR_GPIOJEN RCC_AHB4ENR_GPIOJEN_Msk
15229#define RCC_AHB4ENR_GPIOKEN_Pos (10U)
15230#define RCC_AHB4ENR_GPIOKEN_Msk (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos) /*!< 0x00000400 */
15231#define RCC_AHB4ENR_GPIOKEN RCC_AHB4ENR_GPIOKEN_Msk
15232#define RCC_AHB4ENR_CRCEN_Pos (19U)
15233#define RCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos) /*!< 0x00080000 */
15234#define RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk
15235#define RCC_AHB4ENR_BDMAEN_Pos (21U)
15236#define RCC_AHB4ENR_BDMAEN_Msk (0x1UL << RCC_AHB4ENR_BDMAEN_Pos) /*!< 0x00200000 */
15237#define RCC_AHB4ENR_BDMAEN RCC_AHB4ENR_BDMAEN_Msk
15238#define RCC_AHB4ENR_ADC3EN_Pos (24U)
15239#define RCC_AHB4ENR_ADC3EN_Msk (0x1UL << RCC_AHB4ENR_ADC3EN_Pos) /*!< 0x01000000 */
15240#define RCC_AHB4ENR_ADC3EN RCC_AHB4ENR_ADC3EN_Msk
15241#define RCC_AHB4ENR_HSEMEN_Pos (25U)
15242#define RCC_AHB4ENR_HSEMEN_Msk (0x1UL << RCC_AHB4ENR_HSEMEN_Pos) /*!< 0x02000000 */
15243#define RCC_AHB4ENR_HSEMEN RCC_AHB4ENR_HSEMEN_Msk
15244#define RCC_AHB4ENR_BKPRAMEN_Pos (28U)
15245#define RCC_AHB4ENR_BKPRAMEN_Msk (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos) /*!< 0x10000000 */
15246#define RCC_AHB4ENR_BKPRAMEN RCC_AHB4ENR_BKPRAMEN_Msk
15247
15248/******************** Bit definition for RCC_APB3ENR register ******************/
15249#define RCC_APB3ENR_LTDCEN_Pos (3U)
15250#define RCC_APB3ENR_LTDCEN_Msk (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */
15251#define RCC_APB3ENR_LTDCEN RCC_APB3ENR_LTDCEN_Msk
15252#define RCC_APB3ENR_WWDG1EN_Pos (6U)
15253#define RCC_APB3ENR_WWDG1EN_Msk (0x1UL << RCC_APB3ENR_WWDG1EN_Pos) /*!< 0x00000040 */
15254#define RCC_APB3ENR_WWDG1EN RCC_APB3ENR_WWDG1EN_Msk
15255
15256/******************** Bit definition for RCC_APB1LENR register ******************/
15257
15258#define RCC_APB1LENR_TIM2EN_Pos (0U)
15259#define RCC_APB1LENR_TIM2EN_Msk (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */
15260#define RCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk
15261#define RCC_APB1LENR_TIM3EN_Pos (1U)
15262#define RCC_APB1LENR_TIM3EN_Msk (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */
15263#define RCC_APB1LENR_TIM3EN RCC_APB1LENR_TIM3EN_Msk
15264#define RCC_APB1LENR_TIM4EN_Pos (2U)
15265#define RCC_APB1LENR_TIM4EN_Msk (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */
15266#define RCC_APB1LENR_TIM4EN RCC_APB1LENR_TIM4EN_Msk
15267#define RCC_APB1LENR_TIM5EN_Pos (3U)
15268#define RCC_APB1LENR_TIM5EN_Msk (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */
15269#define RCC_APB1LENR_TIM5EN RCC_APB1LENR_TIM5EN_Msk
15270#define RCC_APB1LENR_TIM6EN_Pos (4U)
15271#define RCC_APB1LENR_TIM6EN_Msk (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */
15272#define RCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk
15273#define RCC_APB1LENR_TIM7EN_Pos (5U)
15274#define RCC_APB1LENR_TIM7EN_Msk (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */
15275#define RCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk
15276#define RCC_APB1LENR_TIM12EN_Pos (6U)
15277#define RCC_APB1LENR_TIM12EN_Msk (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */
15278#define RCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk
15279#define RCC_APB1LENR_TIM13EN_Pos (7U)
15280#define RCC_APB1LENR_TIM13EN_Msk (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */
15281#define RCC_APB1LENR_TIM13EN RCC_APB1LENR_TIM13EN_Msk
15282#define RCC_APB1LENR_TIM14EN_Pos (8U)
15283#define RCC_APB1LENR_TIM14EN_Msk (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */
15284#define RCC_APB1LENR_TIM14EN RCC_APB1LENR_TIM14EN_Msk
15285#define RCC_APB1LENR_LPTIM1EN_Pos (9U)
15286#define RCC_APB1LENR_LPTIM1EN_Msk (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */
15287#define RCC_APB1LENR_LPTIM1EN RCC_APB1LENR_LPTIM1EN_Msk
15288
15289
15290#define RCC_APB1LENR_SPI2EN_Pos (14U)
15291#define RCC_APB1LENR_SPI2EN_Msk (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */
15292#define RCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk
15293#define RCC_APB1LENR_SPI3EN_Pos (15U)
15294#define RCC_APB1LENR_SPI3EN_Msk (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */
15295#define RCC_APB1LENR_SPI3EN RCC_APB1LENR_SPI3EN_Msk
15296#define RCC_APB1LENR_SPDIFRXEN_Pos (16U)
15297#define RCC_APB1LENR_SPDIFRXEN_Msk (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */
15298#define RCC_APB1LENR_SPDIFRXEN RCC_APB1LENR_SPDIFRXEN_Msk
15299#define RCC_APB1LENR_USART2EN_Pos (17U)
15300#define RCC_APB1LENR_USART2EN_Msk (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */
15301#define RCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk
15302#define RCC_APB1LENR_USART3EN_Pos (18U)
15303#define RCC_APB1LENR_USART3EN_Msk (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */
15304#define RCC_APB1LENR_USART3EN RCC_APB1LENR_USART3EN_Msk
15305#define RCC_APB1LENR_UART4EN_Pos (19U)
15306#define RCC_APB1LENR_UART4EN_Msk (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */
15307#define RCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk
15308#define RCC_APB1LENR_UART5EN_Pos (20U)
15309#define RCC_APB1LENR_UART5EN_Msk (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */
15310#define RCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk
15311#define RCC_APB1LENR_I2C1EN_Pos (21U)
15312#define RCC_APB1LENR_I2C1EN_Msk (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */
15313#define RCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk
15314#define RCC_APB1LENR_I2C2EN_Pos (22U)
15315#define RCC_APB1LENR_I2C2EN_Msk (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */
15316#define RCC_APB1LENR_I2C2EN RCC_APB1LENR_I2C2EN_Msk
15317#define RCC_APB1LENR_I2C3EN_Pos (23U)
15318#define RCC_APB1LENR_I2C3EN_Msk (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */
15319#define RCC_APB1LENR_I2C3EN RCC_APB1LENR_I2C3EN_Msk
15320#define RCC_APB1LENR_CECEN_Pos (27U)
15321#define RCC_APB1LENR_CECEN_Msk (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */
15322#define RCC_APB1LENR_CECEN RCC_APB1LENR_CECEN_Msk
15323#define RCC_APB1LENR_DAC12EN_Pos (29U)
15324#define RCC_APB1LENR_DAC12EN_Msk (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */
15325#define RCC_APB1LENR_DAC12EN RCC_APB1LENR_DAC12EN_Msk
15326#define RCC_APB1LENR_UART7EN_Pos (30U)
15327#define RCC_APB1LENR_UART7EN_Msk (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */
15328#define RCC_APB1LENR_UART7EN RCC_APB1LENR_UART7EN_Msk
15329#define RCC_APB1LENR_UART8EN_Pos (31U)
15330#define RCC_APB1LENR_UART8EN_Msk (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */
15331#define RCC_APB1LENR_UART8EN RCC_APB1LENR_UART8EN_Msk
15332
15333/* Legacy define */
15334#define RCC_APB1LENR_HDMICECEN_Pos RCC_APB1LENR_CECEN_Pos
15335#define RCC_APB1LENR_HDMICECEN_Msk RCC_APB1LENR_CECEN_Msk
15336#define RCC_APB1LENR_HDMICECEN RCC_APB1LENR_CECEN
15337/******************** Bit definition for RCC_APB1HENR register ******************/
15338#define RCC_APB1HENR_CRSEN_Pos (1U)
15339#define RCC_APB1HENR_CRSEN_Msk (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */
15340#define RCC_APB1HENR_CRSEN RCC_APB1HENR_CRSEN_Msk
15341#define RCC_APB1HENR_SWPMIEN_Pos (2U)
15342#define RCC_APB1HENR_SWPMIEN_Msk (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */
15343#define RCC_APB1HENR_SWPMIEN RCC_APB1HENR_SWPMIEN_Msk
15344#define RCC_APB1HENR_OPAMPEN_Pos (4U)
15345#define RCC_APB1HENR_OPAMPEN_Msk (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */
15346#define RCC_APB1HENR_OPAMPEN RCC_APB1HENR_OPAMPEN_Msk
15347#define RCC_APB1HENR_MDIOSEN_Pos (5U)
15348#define RCC_APB1HENR_MDIOSEN_Msk (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */
15349#define RCC_APB1HENR_MDIOSEN RCC_APB1HENR_MDIOSEN_Msk
15350#define RCC_APB1HENR_FDCANEN_Pos (8U)
15351#define RCC_APB1HENR_FDCANEN_Msk (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */
15352#define RCC_APB1HENR_FDCANEN RCC_APB1HENR_FDCANEN_Msk
15353
15354/******************** Bit definition for RCC_APB2ENR register ******************/
15355#define RCC_APB2ENR_TIM1EN_Pos (0U)
15356#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
15357#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
15358#define RCC_APB2ENR_TIM8EN_Pos (1U)
15359#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
15360#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
15361#define RCC_APB2ENR_USART1EN_Pos (4U)
15362#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
15363#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
15364#define RCC_APB2ENR_USART6EN_Pos (5U)
15365#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
15366#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
15367#define RCC_APB2ENR_SPI1EN_Pos (12U)
15368#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
15369#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
15370#define RCC_APB2ENR_SPI4EN_Pos (13U)
15371#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
15372#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
15373#define RCC_APB2ENR_TIM15EN_Pos (16U)
15374#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
15375#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
15376#define RCC_APB2ENR_TIM16EN_Pos (17U)
15377#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
15378#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
15379#define RCC_APB2ENR_TIM17EN_Pos (18U)
15380#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
15381#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
15382#define RCC_APB2ENR_SPI5EN_Pos (20U)
15383#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
15384#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
15385#define RCC_APB2ENR_SAI1EN_Pos (22U)
15386#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
15387#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
15388#define RCC_APB2ENR_SAI2EN_Pos (23U)
15389#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */
15390#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
15391#define RCC_APB2ENR_SAI3EN_Pos (24U)
15392#define RCC_APB2ENR_SAI3EN_Msk (0x1UL << RCC_APB2ENR_SAI3EN_Pos) /*!< 0x01000000 */
15393#define RCC_APB2ENR_SAI3EN RCC_APB2ENR_SAI3EN_Msk
15394#define RCC_APB2ENR_DFSDM1EN_Pos (28U)
15395#define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x10000000 */
15396#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
15397#define RCC_APB2ENR_HRTIMEN_Pos (29U)
15398#define RCC_APB2ENR_HRTIMEN_Msk (0x1UL << RCC_APB2ENR_HRTIMEN_Pos) /*!< 0x20000000 */
15399#define RCC_APB2ENR_HRTIMEN RCC_APB2ENR_HRTIMEN_Msk
15400
15401/******************** Bit definition for RCC_APB4ENR register ******************/
15402#define RCC_APB4ENR_SYSCFGEN_Pos (1U)
15403#define RCC_APB4ENR_SYSCFGEN_Msk (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */
15404#define RCC_APB4ENR_SYSCFGEN RCC_APB4ENR_SYSCFGEN_Msk
15405#define RCC_APB4ENR_LPUART1EN_Pos (3U)
15406#define RCC_APB4ENR_LPUART1EN_Msk (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */
15407#define RCC_APB4ENR_LPUART1EN RCC_APB4ENR_LPUART1EN_Msk
15408#define RCC_APB4ENR_SPI6EN_Pos (5U)
15409#define RCC_APB4ENR_SPI6EN_Msk (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */
15410#define RCC_APB4ENR_SPI6EN RCC_APB4ENR_SPI6EN_Msk
15411#define RCC_APB4ENR_I2C4EN_Pos (7U)
15412#define RCC_APB4ENR_I2C4EN_Msk (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */
15413#define RCC_APB4ENR_I2C4EN RCC_APB4ENR_I2C4EN_Msk
15414#define RCC_APB4ENR_LPTIM2EN_Pos (9U)
15415#define RCC_APB4ENR_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */
15416#define RCC_APB4ENR_LPTIM2EN RCC_APB4ENR_LPTIM2EN_Msk
15417#define RCC_APB4ENR_LPTIM3EN_Pos (10U)
15418#define RCC_APB4ENR_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */
15419#define RCC_APB4ENR_LPTIM3EN RCC_APB4ENR_LPTIM3EN_Msk
15420#define RCC_APB4ENR_LPTIM4EN_Pos (11U)
15421#define RCC_APB4ENR_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */
15422#define RCC_APB4ENR_LPTIM4EN RCC_APB4ENR_LPTIM4EN_Msk
15423#define RCC_APB4ENR_LPTIM5EN_Pos (12U)
15424#define RCC_APB4ENR_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */
15425#define RCC_APB4ENR_LPTIM5EN RCC_APB4ENR_LPTIM5EN_Msk
15426#define RCC_APB4ENR_COMP12EN_Pos (14U)
15427#define RCC_APB4ENR_COMP12EN_Msk (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */
15428#define RCC_APB4ENR_COMP12EN RCC_APB4ENR_COMP12EN_Msk
15429#define RCC_APB4ENR_VREFEN_Pos (15U)
15430#define RCC_APB4ENR_VREFEN_Msk (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */
15431#define RCC_APB4ENR_VREFEN RCC_APB4ENR_VREFEN_Msk
15432#define RCC_APB4ENR_RTCAPBEN_Pos (16U)
15433#define RCC_APB4ENR_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */
15434#define RCC_APB4ENR_RTCAPBEN RCC_APB4ENR_RTCAPBEN_Msk
15435#define RCC_APB4ENR_SAI4EN_Pos (21U)
15436#define RCC_APB4ENR_SAI4EN_Msk (0x1UL << RCC_APB4ENR_SAI4EN_Pos) /*!< 0x00200000 */
15437#define RCC_APB4ENR_SAI4EN RCC_APB4ENR_SAI4EN_Msk
15438
15439
15440/******************** Bit definition for RCC_AHB3RSTR register ***************/
15441#define RCC_AHB3RSTR_MDMARST_Pos (0U)
15442#define RCC_AHB3RSTR_MDMARST_Msk (0x1UL << RCC_AHB3RSTR_MDMARST_Pos) /*!< 0x00000001 */
15443#define RCC_AHB3RSTR_MDMARST RCC_AHB3RSTR_MDMARST_Msk
15444#define RCC_AHB3RSTR_DMA2DRST_Pos (4U)
15445#define RCC_AHB3RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos) /*!< 0x00000010 */
15446#define RCC_AHB3RSTR_DMA2DRST RCC_AHB3RSTR_DMA2DRST_Msk
15447#define RCC_AHB3RSTR_JPGDECRST_Pos (5U)
15448#define RCC_AHB3RSTR_JPGDECRST_Msk (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos) /*!< 0x00000020 */
15449#define RCC_AHB3RSTR_JPGDECRST RCC_AHB3RSTR_JPGDECRST_Msk
15450#define RCC_AHB3RSTR_FMCRST_Pos (12U)
15451#define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00001000 */
15452#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
15453#define RCC_AHB3RSTR_QSPIRST_Pos (14U)
15454#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00004000 */
15455#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
15456#define RCC_AHB3RSTR_SDMMC1RST_Pos (16U)
15457#define RCC_AHB3RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos) /*!< 0x00010000 */
15458#define RCC_AHB3RSTR_SDMMC1RST RCC_AHB3RSTR_SDMMC1RST_Msk
15459
15460
15461/******************** Bit definition for RCC_AHB1RSTR register ***************/
15462#define RCC_AHB1RSTR_DMA1RST_Pos (0U)
15463#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
15464#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
15465#define RCC_AHB1RSTR_DMA2RST_Pos (1U)
15466#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
15467#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
15468#define RCC_AHB1RSTR_ADC12RST_Pos (5U)
15469#define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos) /*!< 0x00000020 */
15470#define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk
15471#define RCC_AHB1RSTR_ETH1MACRST_Pos (15U)
15472#define RCC_AHB1RSTR_ETH1MACRST_Msk (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos) /*!< 0x00008000 */
15473#define RCC_AHB1RSTR_ETH1MACRST RCC_AHB1RSTR_ETH1MACRST_Msk
15474#define RCC_AHB1RSTR_USB1OTGHSRST_Pos (25U)
15475#define RCC_AHB1RSTR_USB1OTGHSRST_Msk (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */
15476#define RCC_AHB1RSTR_USB1OTGHSRST RCC_AHB1RSTR_USB1OTGHSRST_Msk
15477#define RCC_AHB1RSTR_USB2OTGFSRST_Pos (27U)
15478#define RCC_AHB1RSTR_USB2OTGFSRST_Msk (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos) /*!< 0x08000000 */
15479#define RCC_AHB1RSTR_USB2OTGFSRST RCC_AHB1RSTR_USB2OTGFSRST_Msk
15480
15481/* Legacy define */
15482#define RCC_AHB1RSTR_USB2OTGHSRST_Pos RCC_AHB1RSTR_USB2OTGFSRST_Pos
15483#define RCC_AHB1RSTR_USB2OTGHSRST_Msk RCC_AHB1RSTR_USB2OTGFSRST_Msk
15484#define RCC_AHB1RSTR_USB2OTGHSRST RCC_AHB1RSTR_USB2OTGFSRST
15485
15486/******************** Bit definition for RCC_AHB2RSTR register ***************/
15487#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
15488#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
15489#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
15490#define RCC_AHB2RSTR_CRYPRST_Pos (4U)
15491#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
15492#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
15493#define RCC_AHB2RSTR_HASHRST_Pos (5U)
15494#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
15495#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
15496#define RCC_AHB2RSTR_RNGRST_Pos (6U)
15497#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
15498#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
15499#define RCC_AHB2RSTR_SDMMC2RST_Pos (9U)
15500#define RCC_AHB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos) /*!< 0x00000200 */
15501#define RCC_AHB2RSTR_SDMMC2RST RCC_AHB2RSTR_SDMMC2RST_Msk
15502
15503/******************** Bit definition for RCC_AHB4RSTR register ******************/
15504#define RCC_AHB4RSTR_GPIOARST_Pos (0U)
15505#define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos) /*!< 0x00000001 */
15506#define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk
15507#define RCC_AHB4RSTR_GPIOBRST_Pos (1U)
15508#define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
15509#define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk
15510#define RCC_AHB4RSTR_GPIOCRST_Pos (2U)
15511#define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
15512#define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk
15513#define RCC_AHB4RSTR_GPIODRST_Pos (3U)
15514#define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos) /*!< 0x00000008 */
15515#define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk
15516#define RCC_AHB4RSTR_GPIOERST_Pos (4U)
15517#define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos) /*!< 0x00000010 */
15518#define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk
15519#define RCC_AHB4RSTR_GPIOFRST_Pos (5U)
15520#define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
15521#define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk
15522#define RCC_AHB4RSTR_GPIOGRST_Pos (6U)
15523#define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
15524#define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk
15525#define RCC_AHB4RSTR_GPIOHRST_Pos (7U)
15526#define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
15527#define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk
15528#define RCC_AHB4RSTR_GPIOIRST_Pos (8U)
15529#define RCC_AHB4RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
15530#define RCC_AHB4RSTR_GPIOIRST RCC_AHB4RSTR_GPIOIRST_Msk
15531#define RCC_AHB4RSTR_GPIOJRST_Pos (9U)
15532#define RCC_AHB4RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
15533#define RCC_AHB4RSTR_GPIOJRST RCC_AHB4RSTR_GPIOJRST_Msk
15534#define RCC_AHB4RSTR_GPIOKRST_Pos (10U)
15535#define RCC_AHB4RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
15536#define RCC_AHB4RSTR_GPIOKRST RCC_AHB4RSTR_GPIOKRST_Msk
15537#define RCC_AHB4RSTR_CRCRST_Pos (19U)
15538#define RCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos) /*!< 0x00080000 */
15539#define RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk
15540#define RCC_AHB4RSTR_BDMARST_Pos (21U)
15541#define RCC_AHB4RSTR_BDMARST_Msk (0x1UL << RCC_AHB4RSTR_BDMARST_Pos) /*!< 0x00200000 */
15542#define RCC_AHB4RSTR_BDMARST RCC_AHB4RSTR_BDMARST_Msk
15543#define RCC_AHB4RSTR_ADC3RST_Pos (24U)
15544#define RCC_AHB4RSTR_ADC3RST_Msk (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos) /*!< 0x01000000 */
15545#define RCC_AHB4RSTR_ADC3RST RCC_AHB4RSTR_ADC3RST_Msk
15546#define RCC_AHB4RSTR_HSEMRST_Pos (25U)
15547#define RCC_AHB4RSTR_HSEMRST_Msk (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos) /*!< 0x02000000 */
15548#define RCC_AHB4RSTR_HSEMRST RCC_AHB4RSTR_HSEMRST_Msk
15549
15550
15551/******************** Bit definition for RCC_APB3RSTR register ******************/
15552#define RCC_APB3RSTR_LTDCRST_Pos (3U)
15553#define RCC_APB3RSTR_LTDCRST_Msk (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */
15554#define RCC_APB3RSTR_LTDCRST RCC_APB3RSTR_LTDCRST_Msk
15555
15556/******************** Bit definition for RCC_APB1LRSTR register ******************/
15557
15558#define RCC_APB1LRSTR_TIM2RST_Pos (0U)
15559#define RCC_APB1LRSTR_TIM2RST_Msk (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */
15560#define RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk
15561#define RCC_APB1LRSTR_TIM3RST_Pos (1U)
15562#define RCC_APB1LRSTR_TIM3RST_Msk (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */
15563#define RCC_APB1LRSTR_TIM3RST RCC_APB1LRSTR_TIM3RST_Msk
15564#define RCC_APB1LRSTR_TIM4RST_Pos (2U)
15565#define RCC_APB1LRSTR_TIM4RST_Msk (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */
15566#define RCC_APB1LRSTR_TIM4RST RCC_APB1LRSTR_TIM4RST_Msk
15567#define RCC_APB1LRSTR_TIM5RST_Pos (3U)
15568#define RCC_APB1LRSTR_TIM5RST_Msk (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */
15569#define RCC_APB1LRSTR_TIM5RST RCC_APB1LRSTR_TIM5RST_Msk
15570#define RCC_APB1LRSTR_TIM6RST_Pos (4U)
15571#define RCC_APB1LRSTR_TIM6RST_Msk (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */
15572#define RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk
15573#define RCC_APB1LRSTR_TIM7RST_Pos (5U)
15574#define RCC_APB1LRSTR_TIM7RST_Msk (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */
15575#define RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk
15576#define RCC_APB1LRSTR_TIM12RST_Pos (6U)
15577#define RCC_APB1LRSTR_TIM12RST_Msk (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */
15578#define RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk
15579#define RCC_APB1LRSTR_TIM13RST_Pos (7U)
15580#define RCC_APB1LRSTR_TIM13RST_Msk (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */
15581#define RCC_APB1LRSTR_TIM13RST RCC_APB1LRSTR_TIM13RST_Msk
15582#define RCC_APB1LRSTR_TIM14RST_Pos (8U)
15583#define RCC_APB1LRSTR_TIM14RST_Msk (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */
15584#define RCC_APB1LRSTR_TIM14RST RCC_APB1LRSTR_TIM14RST_Msk
15585#define RCC_APB1LRSTR_LPTIM1RST_Pos (9U)
15586#define RCC_APB1LRSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
15587#define RCC_APB1LRSTR_LPTIM1RST RCC_APB1LRSTR_LPTIM1RST_Msk
15588#define RCC_APB1LRSTR_SPI2RST_Pos (14U)
15589#define RCC_APB1LRSTR_SPI2RST_Msk (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */
15590#define RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk
15591#define RCC_APB1LRSTR_SPI3RST_Pos (15U)
15592#define RCC_APB1LRSTR_SPI3RST_Msk (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */
15593#define RCC_APB1LRSTR_SPI3RST RCC_APB1LRSTR_SPI3RST_Msk
15594#define RCC_APB1LRSTR_SPDIFRXRST_Pos (16U)
15595#define RCC_APB1LRSTR_SPDIFRXRST_Msk (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */
15596#define RCC_APB1LRSTR_SPDIFRXRST RCC_APB1LRSTR_SPDIFRXRST_Msk
15597#define RCC_APB1LRSTR_USART2RST_Pos (17U)
15598#define RCC_APB1LRSTR_USART2RST_Msk (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */
15599#define RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk
15600#define RCC_APB1LRSTR_USART3RST_Pos (18U)
15601#define RCC_APB1LRSTR_USART3RST_Msk (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */
15602#define RCC_APB1LRSTR_USART3RST RCC_APB1LRSTR_USART3RST_Msk
15603#define RCC_APB1LRSTR_UART4RST_Pos (19U)
15604#define RCC_APB1LRSTR_UART4RST_Msk (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */
15605#define RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk
15606#define RCC_APB1LRSTR_UART5RST_Pos (20U)
15607#define RCC_APB1LRSTR_UART5RST_Msk (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */
15608#define RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk
15609#define RCC_APB1LRSTR_I2C1RST_Pos (21U)
15610#define RCC_APB1LRSTR_I2C1RST_Msk (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */
15611#define RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk
15612#define RCC_APB1LRSTR_I2C2RST_Pos (22U)
15613#define RCC_APB1LRSTR_I2C2RST_Msk (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */
15614#define RCC_APB1LRSTR_I2C2RST RCC_APB1LRSTR_I2C2RST_Msk
15615#define RCC_APB1LRSTR_I2C3RST_Pos (23U)
15616#define RCC_APB1LRSTR_I2C3RST_Msk (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */
15617#define RCC_APB1LRSTR_I2C3RST RCC_APB1LRSTR_I2C3RST_Msk
15618#define RCC_APB1LRSTR_CECRST_Pos (27U)
15619#define RCC_APB1LRSTR_CECRST_Msk (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */
15620#define RCC_APB1LRSTR_CECRST RCC_APB1LRSTR_CECRST_Msk
15621#define RCC_APB1LRSTR_DAC12RST_Pos (29U)
15622#define RCC_APB1LRSTR_DAC12RST_Msk (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */
15623#define RCC_APB1LRSTR_DAC12RST RCC_APB1LRSTR_DAC12RST_Msk
15624#define RCC_APB1LRSTR_UART7RST_Pos (30U)
15625#define RCC_APB1LRSTR_UART7RST_Msk (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */
15626#define RCC_APB1LRSTR_UART7RST RCC_APB1LRSTR_UART7RST_Msk
15627#define RCC_APB1LRSTR_UART8RST_Pos (31U)
15628#define RCC_APB1LRSTR_UART8RST_Msk (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */
15629#define RCC_APB1LRSTR_UART8RST RCC_APB1LRSTR_UART8RST_Msk
15630
15631/* Legacy define */
15632#define RCC_APB1LRSTR_HDMICECRST_Pos RCC_APB1LRSTR_CECRST_Pos
15633#define RCC_APB1LRSTR_HDMICECRST_Msk RCC_APB1LRSTR_CECRST_Msk
15634#define RCC_APB1LRSTR_HDMICECRST RCC_APB1LRSTR_CECRST
15635/******************** Bit definition for RCC_APB1HRSTR register ******************/
15636#define RCC_APB1HRSTR_CRSRST_Pos (1U)
15637#define RCC_APB1HRSTR_CRSRST_Msk (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */
15638#define RCC_APB1HRSTR_CRSRST RCC_APB1HRSTR_CRSRST_Msk
15639#define RCC_APB1HRSTR_SWPMIRST_Pos (2U)
15640#define RCC_APB1HRSTR_SWPMIRST_Msk (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */
15641#define RCC_APB1HRSTR_SWPMIRST RCC_APB1HRSTR_SWPMIRST_Msk
15642#define RCC_APB1HRSTR_OPAMPRST_Pos (4U)
15643#define RCC_APB1HRSTR_OPAMPRST_Msk (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */
15644#define RCC_APB1HRSTR_OPAMPRST RCC_APB1HRSTR_OPAMPRST_Msk
15645#define RCC_APB1HRSTR_MDIOSRST_Pos (5U)
15646#define RCC_APB1HRSTR_MDIOSRST_Msk (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */
15647#define RCC_APB1HRSTR_MDIOSRST RCC_APB1HRSTR_MDIOSRST_Msk
15648#define RCC_APB1HRSTR_FDCANRST_Pos (8U)
15649#define RCC_APB1HRSTR_FDCANRST_Msk (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */
15650#define RCC_APB1HRSTR_FDCANRST RCC_APB1HRSTR_FDCANRST_Msk
15651
15652/******************** Bit definition for RCC_APB2RSTR register ******************/
15653#define RCC_APB2RSTR_TIM1RST_Pos (0U)
15654#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
15655#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
15656#define RCC_APB2RSTR_TIM8RST_Pos (1U)
15657#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
15658#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
15659#define RCC_APB2RSTR_USART1RST_Pos (4U)
15660#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
15661#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
15662#define RCC_APB2RSTR_USART6RST_Pos (5U)
15663#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
15664#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
15665#define RCC_APB2RSTR_SPI1RST_Pos (12U)
15666#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
15667#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
15668#define RCC_APB2RSTR_SPI4RST_Pos (13U)
15669#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
15670#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
15671#define RCC_APB2RSTR_TIM15RST_Pos (16U)
15672#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
15673#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
15674#define RCC_APB2RSTR_TIM16RST_Pos (17U)
15675#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
15676#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
15677#define RCC_APB2RSTR_TIM17RST_Pos (18U)
15678#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
15679#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
15680#define RCC_APB2RSTR_SPI5RST_Pos (20U)
15681#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
15682#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
15683#define RCC_APB2RSTR_SAI1RST_Pos (22U)
15684#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
15685#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
15686#define RCC_APB2RSTR_SAI2RST_Pos (23U)
15687#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */
15688#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
15689#define RCC_APB2RSTR_SAI3RST_Pos (24U)
15690#define RCC_APB2RSTR_SAI3RST_Msk (0x1UL << RCC_APB2RSTR_SAI3RST_Pos) /*!< 0x01000000 */
15691#define RCC_APB2RSTR_SAI3RST RCC_APB2RSTR_SAI3RST_Msk
15692#define RCC_APB2RSTR_DFSDM1RST_Pos (28U)
15693#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */
15694#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
15695#define RCC_APB2RSTR_HRTIMRST_Pos (29U)
15696#define RCC_APB2RSTR_HRTIMRST_Msk (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos) /*!< 0x20000000 */
15697#define RCC_APB2RSTR_HRTIMRST RCC_APB2RSTR_HRTIMRST_Msk
15698
15699/******************** Bit definition for RCC_APB4RSTR register ******************/
15700#define RCC_APB4RSTR_SYSCFGRST_Pos (1U)
15701#define RCC_APB4RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */
15702#define RCC_APB4RSTR_SYSCFGRST RCC_APB4RSTR_SYSCFGRST_Msk
15703#define RCC_APB4RSTR_LPUART1RST_Pos (3U)
15704#define RCC_APB4RSTR_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */
15705#define RCC_APB4RSTR_LPUART1RST RCC_APB4RSTR_LPUART1RST_Msk
15706#define RCC_APB4RSTR_SPI6RST_Pos (5U)
15707#define RCC_APB4RSTR_SPI6RST_Msk (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */
15708#define RCC_APB4RSTR_SPI6RST RCC_APB4RSTR_SPI6RST_Msk
15709#define RCC_APB4RSTR_I2C4RST_Pos (7U)
15710#define RCC_APB4RSTR_I2C4RST_Msk (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */
15711#define RCC_APB4RSTR_I2C4RST RCC_APB4RSTR_I2C4RST_Msk
15712#define RCC_APB4RSTR_LPTIM2RST_Pos (9U)
15713#define RCC_APB4RSTR_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */
15714#define RCC_APB4RSTR_LPTIM2RST RCC_APB4RSTR_LPTIM2RST_Msk
15715#define RCC_APB4RSTR_LPTIM3RST_Pos (10U)
15716#define RCC_APB4RSTR_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */
15717#define RCC_APB4RSTR_LPTIM3RST RCC_APB4RSTR_LPTIM3RST_Msk
15718#define RCC_APB4RSTR_LPTIM4RST_Pos (11U)
15719#define RCC_APB4RSTR_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */
15720#define RCC_APB4RSTR_LPTIM4RST RCC_APB4RSTR_LPTIM4RST_Msk
15721#define RCC_APB4RSTR_LPTIM5RST_Pos (12U)
15722#define RCC_APB4RSTR_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */
15723#define RCC_APB4RSTR_LPTIM5RST RCC_APB4RSTR_LPTIM5RST_Msk
15724#define RCC_APB4RSTR_COMP12RST_Pos (14U)
15725#define RCC_APB4RSTR_COMP12RST_Msk (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */
15726#define RCC_APB4RSTR_COMP12RST RCC_APB4RSTR_COMP12RST_Msk
15727#define RCC_APB4RSTR_VREFRST_Pos (15U)
15728#define RCC_APB4RSTR_VREFRST_Msk (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */
15729#define RCC_APB4RSTR_VREFRST RCC_APB4RSTR_VREFRST_Msk
15730#define RCC_APB4RSTR_SAI4RST_Pos (21U)
15731#define RCC_APB4RSTR_SAI4RST_Msk (0x1UL << RCC_APB4RSTR_SAI4RST_Pos) /*!< 0x00200000 */
15732#define RCC_APB4RSTR_SAI4RST RCC_APB4RSTR_SAI4RST_Msk
15733
15734
15735/******************** Bit definition for RCC_GCR register ********************/
15736#define RCC_GCR_WW1RSC_Pos (0U)
15737#define RCC_GCR_WW1RSC_Msk (0x1UL << RCC_GCR_WW1RSC_Pos) /*!< 0x00000001 */
15738#define RCC_GCR_WW1RSC RCC_GCR_WW1RSC_Msk
15739
15740/******************** Bit definition for RCC_D3AMR register ********************/
15741#define RCC_D3AMR_BDMAAMEN_Pos (0U)
15742#define RCC_D3AMR_BDMAAMEN_Msk (0x1UL << RCC_D3AMR_BDMAAMEN_Pos) /*!< 0x00000001 */
15743#define RCC_D3AMR_BDMAAMEN RCC_D3AMR_BDMAAMEN_Msk
15744#define RCC_D3AMR_LPUART1AMEN_Pos (3U)
15745#define RCC_D3AMR_LPUART1AMEN_Msk (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos) /*!< 0x00000008 */
15746#define RCC_D3AMR_LPUART1AMEN RCC_D3AMR_LPUART1AMEN_Msk
15747#define RCC_D3AMR_SPI6AMEN_Pos (5U)
15748#define RCC_D3AMR_SPI6AMEN_Msk (0x1UL << RCC_D3AMR_SPI6AMEN_Pos) /*!< 0x00000020 */
15749#define RCC_D3AMR_SPI6AMEN RCC_D3AMR_SPI6AMEN_Msk
15750#define RCC_D3AMR_I2C4AMEN_Pos (7U)
15751#define RCC_D3AMR_I2C4AMEN_Msk (0x1UL << RCC_D3AMR_I2C4AMEN_Pos) /*!< 0x00000080 */
15752#define RCC_D3AMR_I2C4AMEN RCC_D3AMR_I2C4AMEN_Msk
15753#define RCC_D3AMR_LPTIM2AMEN_Pos (9U)
15754#define RCC_D3AMR_LPTIM2AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */
15755#define RCC_D3AMR_LPTIM2AMEN RCC_D3AMR_LPTIM2AMEN_Msk
15756#define RCC_D3AMR_LPTIM3AMEN_Pos (10U)
15757#define RCC_D3AMR_LPTIM3AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */
15758#define RCC_D3AMR_LPTIM3AMEN RCC_D3AMR_LPTIM3AMEN_Msk
15759#define RCC_D3AMR_LPTIM4AMEN_Pos (11U)
15760#define RCC_D3AMR_LPTIM4AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos) /*!< 0x00000800 */
15761#define RCC_D3AMR_LPTIM4AMEN RCC_D3AMR_LPTIM4AMEN_Msk
15762#define RCC_D3AMR_LPTIM5AMEN_Pos (12U)
15763#define RCC_D3AMR_LPTIM5AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos) /*!< 0x00001000 */
15764#define RCC_D3AMR_LPTIM5AMEN RCC_D3AMR_LPTIM5AMEN_Msk
15765#define RCC_D3AMR_COMP12AMEN_Pos (14U)
15766#define RCC_D3AMR_COMP12AMEN_Msk (0x1UL << RCC_D3AMR_COMP12AMEN_Pos) /*!< 0x00004000 */
15767#define RCC_D3AMR_COMP12AMEN RCC_D3AMR_COMP12AMEN_Msk
15768#define RCC_D3AMR_VREFAMEN_Pos (15U)
15769#define RCC_D3AMR_VREFAMEN_Msk (0x1UL << RCC_D3AMR_VREFAMEN_Pos) /*!< 0x00008000 */
15770#define RCC_D3AMR_VREFAMEN RCC_D3AMR_VREFAMEN_Msk
15771#define RCC_D3AMR_RTCAMEN_Pos (16U)
15772#define RCC_D3AMR_RTCAMEN_Msk (0x1UL << RCC_D3AMR_RTCAMEN_Pos) /*!< 0x00010000 */
15773#define RCC_D3AMR_RTCAMEN RCC_D3AMR_RTCAMEN_Msk
15774#define RCC_D3AMR_CRCAMEN_Pos (19U)
15775#define RCC_D3AMR_CRCAMEN_Msk (0x1UL << RCC_D3AMR_CRCAMEN_Pos) /*!< 0x00080000 */
15776#define RCC_D3AMR_CRCAMEN RCC_D3AMR_CRCAMEN_Msk
15777#define RCC_D3AMR_SAI4AMEN_Pos (21U)
15778#define RCC_D3AMR_SAI4AMEN_Msk (0x1UL << RCC_D3AMR_SAI4AMEN_Pos) /*!< 0x00200000 */
15779#define RCC_D3AMR_SAI4AMEN RCC_D3AMR_SAI4AMEN_Msk
15780#define RCC_D3AMR_ADC3AMEN_Pos (24U)
15781#define RCC_D3AMR_ADC3AMEN_Msk (0x1UL << RCC_D3AMR_ADC3AMEN_Pos) /*!< 0x01000000 */
15782#define RCC_D3AMR_ADC3AMEN RCC_D3AMR_ADC3AMEN_Msk
15783
15784
15785#define RCC_D3AMR_BKPRAMAMEN_Pos (28U)
15786#define RCC_D3AMR_BKPRAMAMEN_Msk (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */
15787#define RCC_D3AMR_BKPRAMAMEN RCC_D3AMR_BKPRAMAMEN_Msk
15788#define RCC_D3AMR_SRAM4AMEN_Pos (29U)
15789#define RCC_D3AMR_SRAM4AMEN_Msk (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos) /*!< 0x20000000 */
15790#define RCC_D3AMR_SRAM4AMEN RCC_D3AMR_SRAM4AMEN_Msk
15791/******************** Bit definition for RCC_AHB3LPENR register **************/
15792#define RCC_AHB3LPENR_MDMALPEN_Pos (0U)
15793#define RCC_AHB3LPENR_MDMALPEN_Msk (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos) /*!< 0x00000001 */
15794#define RCC_AHB3LPENR_MDMALPEN RCC_AHB3LPENR_MDMALPEN_Msk
15795#define RCC_AHB3LPENR_DMA2DLPEN_Pos (4U)
15796#define RCC_AHB3LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos) /*!< 0x00000010 */
15797#define RCC_AHB3LPENR_DMA2DLPEN RCC_AHB3LPENR_DMA2DLPEN_Msk
15798#define RCC_AHB3LPENR_JPGDECLPEN_Pos (5U)
15799#define RCC_AHB3LPENR_JPGDECLPEN_Msk (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos) /*!< 0x00000020 */
15800#define RCC_AHB3LPENR_JPGDECLPEN RCC_AHB3LPENR_JPGDECLPEN_Msk
15801#define RCC_AHB3LPENR_FLASHLPEN_Pos (8U)
15802#define RCC_AHB3LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos) /*!< 0x00000100 */
15803#define RCC_AHB3LPENR_FLASHLPEN RCC_AHB3LPENR_FLASHLPEN_Msk
15804#define RCC_AHB3LPENR_FMCLPEN_Pos (12U)
15805#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00001000 */
15806#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
15807#define RCC_AHB3LPENR_QSPILPEN_Pos (14U)
15808#define RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00004000 */
15809#define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
15810#define RCC_AHB3LPENR_SDMMC1LPEN_Pos (16U)
15811#define RCC_AHB3LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos) /*!< 0x00010000 */
15812#define RCC_AHB3LPENR_SDMMC1LPEN RCC_AHB3LPENR_SDMMC1LPEN_Msk
15813#define RCC_AHB3LPENR_DTCM1LPEN_Pos (28U)
15814#define RCC_AHB3LPENR_DTCM1LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos) /*!< 0x10000000 */
15815#define RCC_AHB3LPENR_DTCM1LPEN RCC_AHB3LPENR_DTCM1LPEN_Msk
15816#define RCC_AHB3LPENR_DTCM2LPEN_Pos (29U)
15817#define RCC_AHB3LPENR_DTCM2LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos) /*!< 0x20000000 */
15818#define RCC_AHB3LPENR_DTCM2LPEN RCC_AHB3LPENR_DTCM2LPEN_Msk
15819#define RCC_AHB3LPENR_ITCMLPEN_Pos (30U)
15820#define RCC_AHB3LPENR_ITCMLPEN_Msk (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos) /*!< 0x40000000 */
15821#define RCC_AHB3LPENR_ITCMLPEN RCC_AHB3LPENR_ITCMLPEN_Msk
15822#define RCC_AHB3LPENR_AXISRAMLPEN_Pos (31U)
15823#define RCC_AHB3LPENR_AXISRAMLPEN_Msk (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos) /*!< 0x80000000 */
15824#define RCC_AHB3LPENR_AXISRAMLPEN RCC_AHB3LPENR_AXISRAMLPEN_Msk
15825
15826
15827/******************** Bit definition for RCC_AHB1LPENR register ***************/
15828#define RCC_AHB1LPENR_DMA1LPEN_Pos (0U)
15829#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */
15830#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
15831#define RCC_AHB1LPENR_DMA2LPEN_Pos (1U)
15832#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */
15833#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
15834#define RCC_AHB1LPENR_ADC12LPEN_Pos (5U)
15835#define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */
15836#define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk
15837#define RCC_AHB1LPENR_ETH1MACLPEN_Pos (15U)
15838#define RCC_AHB1LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */
15839#define RCC_AHB1LPENR_ETH1MACLPEN RCC_AHB1LPENR_ETH1MACLPEN_Msk
15840#define RCC_AHB1LPENR_ETH1TXLPEN_Pos (16U)
15841#define RCC_AHB1LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */
15842#define RCC_AHB1LPENR_ETH1TXLPEN RCC_AHB1LPENR_ETH1TXLPEN_Msk
15843#define RCC_AHB1LPENR_ETH1RXLPEN_Pos (17U)
15844#define RCC_AHB1LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */
15845#define RCC_AHB1LPENR_ETH1RXLPEN RCC_AHB1LPENR_ETH1RXLPEN_Msk
15846#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos (25U)
15847#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */
15848#define RCC_AHB1LPENR_USB1OTGHSLPEN RCC_AHB1LPENR_USB1OTGHSLPEN_Msk
15849#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos (26U)
15850#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */
15851#define RCC_AHB1LPENR_USB1OTGHSULPILPEN RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk
15852#define RCC_AHB1LPENR_USB2OTGFSLPEN_Pos (27U)
15853#define RCC_AHB1LPENR_USB2OTGFSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos) /*!< 0x08000000 */
15854#define RCC_AHB1LPENR_USB2OTGFSLPEN RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
15855#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos (28U)
15856#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos) /*!< 0x10000000 */
15857#define RCC_AHB1LPENR_USB2OTGFSULPILPEN RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
15858
15859/* Legacy define */
15860#define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos RCC_AHB1LPENR_USB2OTGFSLPEN_Pos
15861#define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
15862#define RCC_AHB1LPENR_USB2OTGHSLPEN RCC_AHB1LPENR_USB2OTGFSLPEN
15863#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos
15864#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
15865#define RCC_AHB1LPENR_USB2OTGHSULPILPEN RCC_AHB1LPENR_USB2OTGFSULPILPEN
15866
15867/******************** Bit definition for RCC_AHB2LPENR register ***************/
15868#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
15869#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
15870#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
15871#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
15872#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
15873#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
15874#define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
15875#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
15876#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
15877#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
15878#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
15879#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
15880#define RCC_AHB2LPENR_SDMMC2LPEN_Pos (9U)
15881#define RCC_AHB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */
15882#define RCC_AHB2LPENR_SDMMC2LPEN RCC_AHB2LPENR_SDMMC2LPEN_Msk
15883#define RCC_AHB2LPENR_SRAM1LPEN_Pos (29U)
15884#define RCC_AHB2LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */
15885#define RCC_AHB2LPENR_SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN_Msk
15886#define RCC_AHB2LPENR_SRAM2LPEN_Pos (30U)
15887#define RCC_AHB2LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */
15888#define RCC_AHB2LPENR_SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN_Msk
15889#define RCC_AHB2LPENR_SRAM3LPEN_Pos (31U)
15890#define RCC_AHB2LPENR_SRAM3LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos) /*!< 0x80000000 */
15891#define RCC_AHB2LPENR_SRAM3LPEN RCC_AHB2LPENR_SRAM3LPEN_Msk
15892
15893/* Legacy define */
15894#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos RCC_AHB2LPENR_SRAM1LPEN_Pos
15895#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk RCC_AHB2LPENR_SRAM1LPEN_Msk
15896#define RCC_AHB2LPENR_D2SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN
15897#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos RCC_AHB2LPENR_SRAM2LPEN_Pos
15898#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk RCC_AHB2LPENR_SRAM2LPEN_Msk
15899#define RCC_AHB2LPENR_D2SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN
15900#define RCC_AHB2LPENR_D2SRAM3LPEN_Pos RCC_AHB2LPENR_SRAM3LPEN_Pos
15901#define RCC_AHB2LPENR_D2SRAM3LPEN_Msk RCC_AHB2LPENR_SRAM3LPEN_Msk
15902#define RCC_AHB2LPENR_D2SRAM3LPEN RCC_AHB2LPENR_SRAM3LPEN
15903
15904/******************** Bit definition for RCC_AHB4LPENR register ******************/
15905#define RCC_AHB4LPENR_GPIOALPEN_Pos (0U)
15906#define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
15907#define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk
15908#define RCC_AHB4LPENR_GPIOBLPEN_Pos (1U)
15909#define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
15910#define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk
15911#define RCC_AHB4LPENR_GPIOCLPEN_Pos (2U)
15912#define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
15913#define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk
15914#define RCC_AHB4LPENR_GPIODLPEN_Pos (3U)
15915#define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
15916#define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk
15917#define RCC_AHB4LPENR_GPIOELPEN_Pos (4U)
15918#define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
15919#define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk
15920#define RCC_AHB4LPENR_GPIOFLPEN_Pos (5U)
15921#define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
15922#define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk
15923#define RCC_AHB4LPENR_GPIOGLPEN_Pos (6U)
15924#define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
15925#define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk
15926#define RCC_AHB4LPENR_GPIOHLPEN_Pos (7U)
15927#define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
15928#define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk
15929#define RCC_AHB4LPENR_GPIOILPEN_Pos (8U)
15930#define RCC_AHB4LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
15931#define RCC_AHB4LPENR_GPIOILPEN RCC_AHB4LPENR_GPIOILPEN_Msk
15932#define RCC_AHB4LPENR_GPIOJLPEN_Pos (9U)
15933#define RCC_AHB4LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
15934#define RCC_AHB4LPENR_GPIOJLPEN RCC_AHB4LPENR_GPIOJLPEN_Msk
15935#define RCC_AHB4LPENR_GPIOKLPEN_Pos (10U)
15936#define RCC_AHB4LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
15937#define RCC_AHB4LPENR_GPIOKLPEN RCC_AHB4LPENR_GPIOKLPEN_Msk
15938#define RCC_AHB4LPENR_CRCLPEN_Pos (19U)
15939#define RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */
15940#define RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk
15941#define RCC_AHB4LPENR_BDMALPEN_Pos (21U)
15942#define RCC_AHB4LPENR_BDMALPEN_Msk (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos) /*!< 0x00200000 */
15943#define RCC_AHB4LPENR_BDMALPEN RCC_AHB4LPENR_BDMALPEN_Msk
15944#define RCC_AHB4LPENR_ADC3LPEN_Pos (24U)
15945#define RCC_AHB4LPENR_ADC3LPEN_Msk (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */
15946#define RCC_AHB4LPENR_ADC3LPEN RCC_AHB4LPENR_ADC3LPEN_Msk
15947#define RCC_AHB4LPENR_BKPRAMLPEN_Pos (28U)
15948#define RCC_AHB4LPENR_BKPRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */
15949#define RCC_AHB4LPENR_BKPRAMLPEN RCC_AHB4LPENR_BKPRAMLPEN_Msk
15950#define RCC_AHB4LPENR_SRAM4LPEN_Pos (29U)
15951#define RCC_AHB4LPENR_SRAM4LPEN_Msk (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos) /*!< 0x20000000 */
15952#define RCC_AHB4LPENR_SRAM4LPEN RCC_AHB4LPENR_SRAM4LPEN_Msk
15953
15954/* Legacy define */
15955#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos RCC_AHB4LPENR_SRAM4LPEN_Pos
15956#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk RCC_AHB4LPENR_SRAM4LPEN_Msk
15957#define RCC_AHB4LPENR_D3SRAM1LPEN RCC_AHB4LPENR_SRAM4LPEN
15958/******************** Bit definition for RCC_APB3LPENR register ******************/
15959#define RCC_APB3LPENR_LTDCLPEN_Pos (3U)
15960#define RCC_APB3LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */
15961#define RCC_APB3LPENR_LTDCLPEN RCC_APB3LPENR_LTDCLPEN_Msk
15962#define RCC_APB3LPENR_WWDG1LPEN_Pos (6U)
15963#define RCC_APB3LPENR_WWDG1LPEN_Msk (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos) /*!< 0x00000040 */
15964#define RCC_APB3LPENR_WWDG1LPEN RCC_APB3LPENR_WWDG1LPEN_Msk
15965
15966/******************** Bit definition for RCC_APB1LLPENR register ******************/
15967
15968#define RCC_APB1LLPENR_TIM2LPEN_Pos (0U)
15969#define RCC_APB1LLPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
15970#define RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk
15971#define RCC_APB1LLPENR_TIM3LPEN_Pos (1U)
15972#define RCC_APB1LLPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
15973#define RCC_APB1LLPENR_TIM3LPEN RCC_APB1LLPENR_TIM3LPEN_Msk
15974#define RCC_APB1LLPENR_TIM4LPEN_Pos (2U)
15975#define RCC_APB1LLPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
15976#define RCC_APB1LLPENR_TIM4LPEN RCC_APB1LLPENR_TIM4LPEN_Msk
15977#define RCC_APB1LLPENR_TIM5LPEN_Pos (3U)
15978#define RCC_APB1LLPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
15979#define RCC_APB1LLPENR_TIM5LPEN RCC_APB1LLPENR_TIM5LPEN_Msk
15980#define RCC_APB1LLPENR_TIM6LPEN_Pos (4U)
15981#define RCC_APB1LLPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
15982#define RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk
15983#define RCC_APB1LLPENR_TIM7LPEN_Pos (5U)
15984#define RCC_APB1LLPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
15985#define RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk
15986#define RCC_APB1LLPENR_TIM12LPEN_Pos (6U)
15987#define RCC_APB1LLPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
15988#define RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk
15989#define RCC_APB1LLPENR_TIM13LPEN_Pos (7U)
15990#define RCC_APB1LLPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
15991#define RCC_APB1LLPENR_TIM13LPEN RCC_APB1LLPENR_TIM13LPEN_Msk
15992#define RCC_APB1LLPENR_TIM14LPEN_Pos (8U)
15993#define RCC_APB1LLPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
15994#define RCC_APB1LLPENR_TIM14LPEN RCC_APB1LLPENR_TIM14LPEN_Msk
15995#define RCC_APB1LLPENR_LPTIM1LPEN_Pos (9U)
15996#define RCC_APB1LLPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
15997#define RCC_APB1LLPENR_LPTIM1LPEN RCC_APB1LLPENR_LPTIM1LPEN_Msk
15998
15999
16000#define RCC_APB1LLPENR_SPI2LPEN_Pos (14U)
16001#define RCC_APB1LLPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
16002#define RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk
16003#define RCC_APB1LLPENR_SPI3LPEN_Pos (15U)
16004#define RCC_APB1LLPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
16005#define RCC_APB1LLPENR_SPI3LPEN RCC_APB1LLPENR_SPI3LPEN_Msk
16006#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos (16U)
16007#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */
16008#define RCC_APB1LLPENR_SPDIFRXLPEN RCC_APB1LLPENR_SPDIFRXLPEN_Msk
16009#define RCC_APB1LLPENR_USART2LPEN_Pos (17U)
16010#define RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */
16011#define RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk
16012#define RCC_APB1LLPENR_USART3LPEN_Pos (18U)
16013#define RCC_APB1LLPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */
16014#define RCC_APB1LLPENR_USART3LPEN RCC_APB1LLPENR_USART3LPEN_Msk
16015#define RCC_APB1LLPENR_UART4LPEN_Pos (19U)
16016#define RCC_APB1LLPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */
16017#define RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk
16018#define RCC_APB1LLPENR_UART5LPEN_Pos (20U)
16019#define RCC_APB1LLPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */
16020#define RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk
16021#define RCC_APB1LLPENR_I2C1LPEN_Pos (21U)
16022#define RCC_APB1LLPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
16023#define RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk
16024#define RCC_APB1LLPENR_I2C2LPEN_Pos (22U)
16025#define RCC_APB1LLPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
16026#define RCC_APB1LLPENR_I2C2LPEN RCC_APB1LLPENR_I2C2LPEN_Msk
16027#define RCC_APB1LLPENR_I2C3LPEN_Pos (23U)
16028#define RCC_APB1LLPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
16029#define RCC_APB1LLPENR_I2C3LPEN RCC_APB1LLPENR_I2C3LPEN_Msk
16030#define RCC_APB1LLPENR_CECLPEN_Pos (27U)
16031#define RCC_APB1LLPENR_CECLPEN_Msk (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */
16032#define RCC_APB1LLPENR_CECLPEN RCC_APB1LLPENR_CECLPEN_Msk
16033#define RCC_APB1LLPENR_DAC12LPEN_Pos (29U)
16034#define RCC_APB1LLPENR_DAC12LPEN_Msk (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */
16035#define RCC_APB1LLPENR_DAC12LPEN RCC_APB1LLPENR_DAC12LPEN_Msk
16036#define RCC_APB1LLPENR_UART7LPEN_Pos (30U)
16037#define RCC_APB1LLPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */
16038#define RCC_APB1LLPENR_UART7LPEN RCC_APB1LLPENR_UART7LPEN_Msk
16039#define RCC_APB1LLPENR_UART8LPEN_Pos (31U)
16040#define RCC_APB1LLPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */
16041#define RCC_APB1LLPENR_UART8LPEN RCC_APB1LLPENR_UART8LPEN_Msk
16042
16043/* Legacy define */
16044#define RCC_APB1LLPENR_HDMICECEN_Pos RCC_APB1LLPENR_CECLPEN_Pos
16045#define RCC_APB1LLPENR_HDMICECEN_Msk RCC_APB1LLPENR_CECLPEN_Msk
16046#define RCC_APB1LLPENR_HDMICECEN RCC_APB1LLPENR_CECLPEN
16047/******************** Bit definition for RCC_APB1HLPENR register ******************/
16048#define RCC_APB1HLPENR_CRSLPEN_Pos (1U)
16049#define RCC_APB1HLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */
16050#define RCC_APB1HLPENR_CRSLPEN RCC_APB1HLPENR_CRSLPEN_Msk
16051#define RCC_APB1HLPENR_SWPMILPEN_Pos (2U)
16052#define RCC_APB1HLPENR_SWPMILPEN_Msk (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */
16053#define RCC_APB1HLPENR_SWPMILPEN RCC_APB1HLPENR_SWPMILPEN_Msk
16054#define RCC_APB1HLPENR_OPAMPLPEN_Pos (4U)
16055#define RCC_APB1HLPENR_OPAMPLPEN_Msk (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */
16056#define RCC_APB1HLPENR_OPAMPLPEN RCC_APB1HLPENR_OPAMPLPEN_Msk
16057#define RCC_APB1HLPENR_MDIOSLPEN_Pos (5U)
16058#define RCC_APB1HLPENR_MDIOSLPEN_Msk (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */
16059#define RCC_APB1HLPENR_MDIOSLPEN RCC_APB1HLPENR_MDIOSLPEN_Msk
16060#define RCC_APB1HLPENR_FDCANLPEN_Pos (8U)
16061#define RCC_APB1HLPENR_FDCANLPEN_Msk (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */
16062#define RCC_APB1HLPENR_FDCANLPEN RCC_APB1HLPENR_FDCANLPEN_Msk
16063
16064/******************** Bit definition for RCC_APB2LPENR register ******************/
16065#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
16066#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
16067#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
16068#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
16069#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
16070#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
16071#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
16072#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
16073#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
16074#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
16075#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
16076#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
16077#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
16078#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
16079#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
16080#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
16081#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
16082#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
16083#define RCC_APB2LPENR_TIM15LPEN_Pos (16U)
16084#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */
16085#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk
16086#define RCC_APB2LPENR_TIM16LPEN_Pos (17U)
16087#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */
16088#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk
16089#define RCC_APB2LPENR_TIM17LPEN_Pos (18U)
16090#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */
16091#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk
16092#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
16093#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
16094#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
16095#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
16096#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
16097#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
16098#define RCC_APB2LPENR_SAI2LPEN_Pos (23U)
16099#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */
16100#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk
16101#define RCC_APB2LPENR_SAI3LPEN_Pos (24U)
16102#define RCC_APB2LPENR_SAI3LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos) /*!< 0x01000000 */
16103#define RCC_APB2LPENR_SAI3LPEN RCC_APB2LPENR_SAI3LPEN_Msk
16104#define RCC_APB2LPENR_DFSDM1LPEN_Pos (28U)
16105#define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x10000000 */
16106#define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
16107#define RCC_APB2LPENR_HRTIMLPEN_Pos (29U)
16108#define RCC_APB2LPENR_HRTIMLPEN_Msk (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos) /*!< 0x20000000 */
16109#define RCC_APB2LPENR_HRTIMLPEN RCC_APB2LPENR_HRTIMLPEN_Msk
16110
16111/******************** Bit definition for RCC_APB4LPENR register ******************/
16112#define RCC_APB4LPENR_SYSCFGLPEN_Pos (1U)
16113#define RCC_APB4LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */
16114#define RCC_APB4LPENR_SYSCFGLPEN RCC_APB4LPENR_SYSCFGLPEN_Msk
16115#define RCC_APB4LPENR_LPUART1LPEN_Pos (3U)
16116#define RCC_APB4LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */
16117#define RCC_APB4LPENR_LPUART1LPEN RCC_APB4LPENR_LPUART1LPEN_Msk
16118#define RCC_APB4LPENR_SPI6LPEN_Pos (5U)
16119#define RCC_APB4LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */
16120#define RCC_APB4LPENR_SPI6LPEN RCC_APB4LPENR_SPI6LPEN_Msk
16121#define RCC_APB4LPENR_I2C4LPEN_Pos (7U)
16122#define RCC_APB4LPENR_I2C4LPEN_Msk (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */
16123#define RCC_APB4LPENR_I2C4LPEN RCC_APB4LPENR_I2C4LPEN_Msk
16124#define RCC_APB4LPENR_LPTIM2LPEN_Pos (9U)
16125#define RCC_APB4LPENR_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */
16126#define RCC_APB4LPENR_LPTIM2LPEN RCC_APB4LPENR_LPTIM2LPEN_Msk
16127#define RCC_APB4LPENR_LPTIM3LPEN_Pos (10U)
16128#define RCC_APB4LPENR_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */
16129#define RCC_APB4LPENR_LPTIM3LPEN RCC_APB4LPENR_LPTIM3LPEN_Msk
16130#define RCC_APB4LPENR_LPTIM4LPEN_Pos (11U)
16131#define RCC_APB4LPENR_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */
16132#define RCC_APB4LPENR_LPTIM4LPEN RCC_APB4LPENR_LPTIM4LPEN_Msk
16133#define RCC_APB4LPENR_LPTIM5LPEN_Pos (12U)
16134#define RCC_APB4LPENR_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */
16135#define RCC_APB4LPENR_LPTIM5LPEN RCC_APB4LPENR_LPTIM5LPEN_Msk
16136#define RCC_APB4LPENR_COMP12LPEN_Pos (14U)
16137#define RCC_APB4LPENR_COMP12LPEN_Msk (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */
16138#define RCC_APB4LPENR_COMP12LPEN RCC_APB4LPENR_COMP12LPEN_Msk
16139#define RCC_APB4LPENR_VREFLPEN_Pos (15U)
16140#define RCC_APB4LPENR_VREFLPEN_Msk (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */
16141#define RCC_APB4LPENR_VREFLPEN RCC_APB4LPENR_VREFLPEN_Msk
16142#define RCC_APB4LPENR_RTCAPBLPEN_Pos (16U)
16143#define RCC_APB4LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */
16144#define RCC_APB4LPENR_RTCAPBLPEN RCC_APB4LPENR_RTCAPBLPEN_Msk
16145#define RCC_APB4LPENR_SAI4LPEN_Pos (21U)
16146#define RCC_APB4LPENR_SAI4LPEN_Msk (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */
16147#define RCC_APB4LPENR_SAI4LPEN RCC_APB4LPENR_SAI4LPEN_Msk
16148
16149
16150/******************** Bit definition for RCC_RSR register *******************/
16151#define RCC_RSR_RMVF_Pos (16U)
16152#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00010000 */
16153#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk
16154#define RCC_RSR_CPURSTF_Pos (17U)
16155#define RCC_RSR_CPURSTF_Msk (0x1UL << RCC_RSR_CPURSTF_Pos) /*!< 0x00020000 */
16156#define RCC_RSR_CPURSTF RCC_RSR_CPURSTF_Msk
16157#define RCC_RSR_D1RSTF_Pos (19U)
16158#define RCC_RSR_D1RSTF_Msk (0x1UL << RCC_RSR_D1RSTF_Pos) /*!< 0x00080000 */
16159#define RCC_RSR_D1RSTF RCC_RSR_D1RSTF_Msk
16160#define RCC_RSR_D2RSTF_Pos (20U)
16161#define RCC_RSR_D2RSTF_Msk (0x1UL << RCC_RSR_D2RSTF_Pos) /*!< 0x00100000 */
16162#define RCC_RSR_D2RSTF RCC_RSR_D2RSTF_Msk
16163#define RCC_RSR_BORRSTF_Pos (21U)
16164#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x00200000 */
16165#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk
16166#define RCC_RSR_PINRSTF_Pos (22U)
16167#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x00400000 */
16168#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk
16169#define RCC_RSR_PORRSTF_Pos (23U)
16170#define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos) /*!< 0x00800000 */
16171#define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk
16172#define RCC_RSR_SFTRSTF_Pos (24U)
16173#define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x01000000 */
16174#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk
16175#define RCC_RSR_IWDG1RSTF_Pos (26U)
16176#define RCC_RSR_IWDG1RSTF_Msk (0x1UL << RCC_RSR_IWDG1RSTF_Pos) /*!< 0x04000000 */
16177#define RCC_RSR_IWDG1RSTF RCC_RSR_IWDG1RSTF_Msk
16178#define RCC_RSR_WWDG1RSTF_Pos (28U)
16179#define RCC_RSR_WWDG1RSTF_Msk (0x1UL << RCC_RSR_WWDG1RSTF_Pos) /*!< 0x10000000 */
16180#define RCC_RSR_WWDG1RSTF RCC_RSR_WWDG1RSTF_Msk
16181
16182#define RCC_RSR_LPWRRSTF_Pos (30U)
16183#define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */
16184#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk
16185
16186
16187/******************************************************************************/
16188/* */
16189/* RNG */
16190/* */
16191/******************************************************************************/
16192/******************** Bits definition for RNG_CR register *******************/
16193#define RNG_CR_RNGEN_Pos (2U)
16194#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
16195#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
16196#define RNG_CR_IE_Pos (3U)
16197#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
16198#define RNG_CR_IE RNG_CR_IE_Msk
16199#define RNG_CR_CED_Pos (5U)
16200#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
16201#define RNG_CR_CED RNG_CR_CED_Msk
16202
16203/******************** Bits definition for RNG_SR register *******************/
16204#define RNG_SR_DRDY_Pos (0U)
16205#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
16206#define RNG_SR_DRDY RNG_SR_DRDY_Msk
16207#define RNG_SR_CECS_Pos (1U)
16208#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
16209#define RNG_SR_CECS RNG_SR_CECS_Msk
16210#define RNG_SR_SECS_Pos (2U)
16211#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
16212#define RNG_SR_SECS RNG_SR_SECS_Msk
16213#define RNG_SR_CEIS_Pos (5U)
16214#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
16215#define RNG_SR_CEIS RNG_SR_CEIS_Msk
16216#define RNG_SR_SEIS_Pos (6U)
16217#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
16218#define RNG_SR_SEIS RNG_SR_SEIS_Msk
16219
16220/******************************************************************************/
16221/* */
16222/* Real-Time Clock (RTC) */
16223/* */
16224/******************************************************************************/
16225/******************** Bits definition for RTC_TR register *******************/
16226#define RTC_TR_PM_Pos (22U)
16227#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
16228#define RTC_TR_PM RTC_TR_PM_Msk
16229#define RTC_TR_HT_Pos (20U)
16230#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
16231#define RTC_TR_HT RTC_TR_HT_Msk
16232#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
16233#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
16234#define RTC_TR_HU_Pos (16U)
16235#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
16236#define RTC_TR_HU RTC_TR_HU_Msk
16237#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
16238#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
16239#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
16240#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
16241#define RTC_TR_MNT_Pos (12U)
16242#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
16243#define RTC_TR_MNT RTC_TR_MNT_Msk
16244#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
16245#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
16246#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
16247#define RTC_TR_MNU_Pos (8U)
16248#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
16249#define RTC_TR_MNU RTC_TR_MNU_Msk
16250#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
16251#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
16252#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
16253#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
16254#define RTC_TR_ST_Pos (4U)
16255#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
16256#define RTC_TR_ST RTC_TR_ST_Msk
16257#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
16258#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
16259#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
16260#define RTC_TR_SU_Pos (0U)
16261#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
16262#define RTC_TR_SU RTC_TR_SU_Msk
16263#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
16264#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
16265#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
16266#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
16267
16268/******************** Bits definition for RTC_DR register *******************/
16269#define RTC_DR_YT_Pos (20U)
16270#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
16271#define RTC_DR_YT RTC_DR_YT_Msk
16272#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
16273#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
16274#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
16275#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
16276#define RTC_DR_YU_Pos (16U)
16277#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
16278#define RTC_DR_YU RTC_DR_YU_Msk
16279#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
16280#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
16281#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
16282#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
16283#define RTC_DR_WDU_Pos (13U)
16284#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
16285#define RTC_DR_WDU RTC_DR_WDU_Msk
16286#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
16287#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
16288#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
16289#define RTC_DR_MT_Pos (12U)
16290#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
16291#define RTC_DR_MT RTC_DR_MT_Msk
16292#define RTC_DR_MU_Pos (8U)
16293#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
16294#define RTC_DR_MU RTC_DR_MU_Msk
16295#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
16296#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
16297#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
16298#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
16299#define RTC_DR_DT_Pos (4U)
16300#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
16301#define RTC_DR_DT RTC_DR_DT_Msk
16302#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
16303#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
16304#define RTC_DR_DU_Pos (0U)
16305#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
16306#define RTC_DR_DU RTC_DR_DU_Msk
16307#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
16308#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
16309#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
16310#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
16311
16312/******************** Bits definition for RTC_CR register *******************/
16313#define RTC_CR_ITSE_Pos (24U)
16314#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
16315#define RTC_CR_ITSE RTC_CR_ITSE_Msk
16316#define RTC_CR_COE_Pos (23U)
16317#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
16318#define RTC_CR_COE RTC_CR_COE_Msk
16319#define RTC_CR_OSEL_Pos (21U)
16320#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
16321#define RTC_CR_OSEL RTC_CR_OSEL_Msk
16322#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
16323#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
16324#define RTC_CR_POL_Pos (20U)
16325#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
16326#define RTC_CR_POL RTC_CR_POL_Msk
16327#define RTC_CR_COSEL_Pos (19U)
16328#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
16329#define RTC_CR_COSEL RTC_CR_COSEL_Msk
16330#define RTC_CR_BKP_Pos (18U)
16331#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
16332#define RTC_CR_BKP RTC_CR_BKP_Msk
16333#define RTC_CR_SUB1H_Pos (17U)
16334#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
16335#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
16336#define RTC_CR_ADD1H_Pos (16U)
16337#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
16338#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
16339#define RTC_CR_TSIE_Pos (15U)
16340#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
16341#define RTC_CR_TSIE RTC_CR_TSIE_Msk
16342#define RTC_CR_WUTIE_Pos (14U)
16343#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
16344#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
16345#define RTC_CR_ALRBIE_Pos (13U)
16346#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
16347#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
16348#define RTC_CR_ALRAIE_Pos (12U)
16349#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
16350#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
16351#define RTC_CR_TSE_Pos (11U)
16352#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
16353#define RTC_CR_TSE RTC_CR_TSE_Msk
16354#define RTC_CR_WUTE_Pos (10U)
16355#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
16356#define RTC_CR_WUTE RTC_CR_WUTE_Msk
16357#define RTC_CR_ALRBE_Pos (9U)
16358#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
16359#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
16360#define RTC_CR_ALRAE_Pos (8U)
16361#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
16362#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
16363#define RTC_CR_FMT_Pos (6U)
16364#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
16365#define RTC_CR_FMT RTC_CR_FMT_Msk
16366#define RTC_CR_BYPSHAD_Pos (5U)
16367#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
16368#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
16369#define RTC_CR_REFCKON_Pos (4U)
16370#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
16371#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
16372#define RTC_CR_TSEDGE_Pos (3U)
16373#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
16374#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
16375#define RTC_CR_WUCKSEL_Pos (0U)
16376#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
16377#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
16378#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
16379#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
16380#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
16381
16382/******************** Bits definition for RTC_ISR register ******************/
16383#define RTC_ISR_ITSF_Pos (17U)
16384#define RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */
16385#define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
16386#define RTC_ISR_RECALPF_Pos (16U)
16387#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
16388#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
16389#define RTC_ISR_TAMP3F_Pos (15U)
16390#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
16391#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
16392#define RTC_ISR_TAMP2F_Pos (14U)
16393#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
16394#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
16395#define RTC_ISR_TAMP1F_Pos (13U)
16396#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
16397#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
16398#define RTC_ISR_TSOVF_Pos (12U)
16399#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
16400#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
16401#define RTC_ISR_TSF_Pos (11U)
16402#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
16403#define RTC_ISR_TSF RTC_ISR_TSF_Msk
16404#define RTC_ISR_WUTF_Pos (10U)
16405#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
16406#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
16407#define RTC_ISR_ALRBF_Pos (9U)
16408#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
16409#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
16410#define RTC_ISR_ALRAF_Pos (8U)
16411#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
16412#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
16413#define RTC_ISR_INIT_Pos (7U)
16414#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
16415#define RTC_ISR_INIT RTC_ISR_INIT_Msk
16416#define RTC_ISR_INITF_Pos (6U)
16417#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
16418#define RTC_ISR_INITF RTC_ISR_INITF_Msk
16419#define RTC_ISR_RSF_Pos (5U)
16420#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
16421#define RTC_ISR_RSF RTC_ISR_RSF_Msk
16422#define RTC_ISR_INITS_Pos (4U)
16423#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
16424#define RTC_ISR_INITS RTC_ISR_INITS_Msk
16425#define RTC_ISR_SHPF_Pos (3U)
16426#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
16427#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
16428#define RTC_ISR_WUTWF_Pos (2U)
16429#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
16430#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
16431#define RTC_ISR_ALRBWF_Pos (1U)
16432#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
16433#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
16434#define RTC_ISR_ALRAWF_Pos (0U)
16435#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
16436#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
16437
16438/******************** Bits definition for RTC_PRER register *****************/
16439#define RTC_PRER_PREDIV_A_Pos (16U)
16440#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
16441#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
16442#define RTC_PRER_PREDIV_S_Pos (0U)
16443#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
16444#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
16445
16446/******************** Bits definition for RTC_WUTR register *****************/
16447#define RTC_WUTR_WUT_Pos (0U)
16448#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
16449#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
16450
16451/******************** Bits definition for RTC_ALRMAR register ***************/
16452#define RTC_ALRMAR_MSK4_Pos (31U)
16453#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
16454#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
16455#define RTC_ALRMAR_WDSEL_Pos (30U)
16456#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
16457#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
16458#define RTC_ALRMAR_DT_Pos (28U)
16459#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
16460#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
16461#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
16462#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
16463#define RTC_ALRMAR_DU_Pos (24U)
16464#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
16465#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
16466#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
16467#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
16468#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
16469#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
16470#define RTC_ALRMAR_MSK3_Pos (23U)
16471#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
16472#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
16473#define RTC_ALRMAR_PM_Pos (22U)
16474#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
16475#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
16476#define RTC_ALRMAR_HT_Pos (20U)
16477#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
16478#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
16479#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
16480#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
16481#define RTC_ALRMAR_HU_Pos (16U)
16482#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
16483#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
16484#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
16485#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
16486#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
16487#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
16488#define RTC_ALRMAR_MSK2_Pos (15U)
16489#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
16490#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
16491#define RTC_ALRMAR_MNT_Pos (12U)
16492#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
16493#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
16494#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
16495#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
16496#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
16497#define RTC_ALRMAR_MNU_Pos (8U)
16498#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
16499#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
16500#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
16501#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
16502#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
16503#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
16504#define RTC_ALRMAR_MSK1_Pos (7U)
16505#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
16506#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
16507#define RTC_ALRMAR_ST_Pos (4U)
16508#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
16509#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
16510#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
16511#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
16512#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
16513#define RTC_ALRMAR_SU_Pos (0U)
16514#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
16515#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
16516#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
16517#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
16518#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
16519#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
16520
16521/******************** Bits definition for RTC_ALRMBR register ***************/
16522#define RTC_ALRMBR_MSK4_Pos (31U)
16523#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
16524#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
16525#define RTC_ALRMBR_WDSEL_Pos (30U)
16526#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
16527#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
16528#define RTC_ALRMBR_DT_Pos (28U)
16529#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
16530#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
16531#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
16532#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
16533#define RTC_ALRMBR_DU_Pos (24U)
16534#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
16535#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
16536#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
16537#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
16538#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
16539#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
16540#define RTC_ALRMBR_MSK3_Pos (23U)
16541#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
16542#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
16543#define RTC_ALRMBR_PM_Pos (22U)
16544#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
16545#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
16546#define RTC_ALRMBR_HT_Pos (20U)
16547#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
16548#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
16549#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
16550#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
16551#define RTC_ALRMBR_HU_Pos (16U)
16552#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
16553#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
16554#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
16555#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
16556#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
16557#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
16558#define RTC_ALRMBR_MSK2_Pos (15U)
16559#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
16560#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
16561#define RTC_ALRMBR_MNT_Pos (12U)
16562#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
16563#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
16564#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
16565#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
16566#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
16567#define RTC_ALRMBR_MNU_Pos (8U)
16568#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
16569#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
16570#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
16571#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
16572#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
16573#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
16574#define RTC_ALRMBR_MSK1_Pos (7U)
16575#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
16576#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
16577#define RTC_ALRMBR_ST_Pos (4U)
16578#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
16579#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
16580#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
16581#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
16582#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
16583#define RTC_ALRMBR_SU_Pos (0U)
16584#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
16585#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
16586#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
16587#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
16588#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
16589#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
16590
16591/******************** Bits definition for RTC_WPR register ******************/
16592#define RTC_WPR_KEY_Pos (0U)
16593#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
16594#define RTC_WPR_KEY RTC_WPR_KEY_Msk
16595
16596/******************** Bits definition for RTC_SSR register ******************/
16597#define RTC_SSR_SS_Pos (0U)
16598#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
16599#define RTC_SSR_SS RTC_SSR_SS_Msk
16600
16601/******************** Bits definition for RTC_SHIFTR register ***************/
16602#define RTC_SHIFTR_SUBFS_Pos (0U)
16603#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
16604#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
16605#define RTC_SHIFTR_ADD1S_Pos (31U)
16606#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
16607#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
16608
16609/******************** Bits definition for RTC_TSTR register *****************/
16610#define RTC_TSTR_PM_Pos (22U)
16611#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
16612#define RTC_TSTR_PM RTC_TSTR_PM_Msk
16613#define RTC_TSTR_HT_Pos (20U)
16614#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
16615#define RTC_TSTR_HT RTC_TSTR_HT_Msk
16616#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
16617#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
16618#define RTC_TSTR_HU_Pos (16U)
16619#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
16620#define RTC_TSTR_HU RTC_TSTR_HU_Msk
16621#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
16622#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
16623#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
16624#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
16625#define RTC_TSTR_MNT_Pos (12U)
16626#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
16627#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
16628#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
16629#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
16630#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
16631#define RTC_TSTR_MNU_Pos (8U)
16632#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
16633#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
16634#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
16635#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
16636#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
16637#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
16638#define RTC_TSTR_ST_Pos (4U)
16639#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
16640#define RTC_TSTR_ST RTC_TSTR_ST_Msk
16641#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
16642#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
16643#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
16644#define RTC_TSTR_SU_Pos (0U)
16645#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
16646#define RTC_TSTR_SU RTC_TSTR_SU_Msk
16647#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
16648#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
16649#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
16650#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
16651
16652/******************** Bits definition for RTC_TSDR register *****************/
16653#define RTC_TSDR_WDU_Pos (13U)
16654#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
16655#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
16656#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
16657#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
16658#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
16659#define RTC_TSDR_MT_Pos (12U)
16660#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
16661#define RTC_TSDR_MT RTC_TSDR_MT_Msk
16662#define RTC_TSDR_MU_Pos (8U)
16663#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
16664#define RTC_TSDR_MU RTC_TSDR_MU_Msk
16665#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
16666#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
16667#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
16668#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
16669#define RTC_TSDR_DT_Pos (4U)
16670#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
16671#define RTC_TSDR_DT RTC_TSDR_DT_Msk
16672#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
16673#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
16674#define RTC_TSDR_DU_Pos (0U)
16675#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
16676#define RTC_TSDR_DU RTC_TSDR_DU_Msk
16677#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
16678#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
16679#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
16680#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
16681
16682/******************** Bits definition for RTC_TSSSR register ****************/
16683#define RTC_TSSSR_SS_Pos (0U)
16684#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
16685#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
16686
16687/******************** Bits definition for RTC_CALR register *****************/
16688#define RTC_CALR_CALP_Pos (15U)
16689#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
16690#define RTC_CALR_CALP RTC_CALR_CALP_Msk
16691#define RTC_CALR_CALW8_Pos (14U)
16692#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
16693#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
16694#define RTC_CALR_CALW16_Pos (13U)
16695#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
16696#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
16697#define RTC_CALR_CALM_Pos (0U)
16698#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
16699#define RTC_CALR_CALM RTC_CALR_CALM_Msk
16700#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
16701#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
16702#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
16703#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
16704#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
16705#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
16706#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
16707#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
16708#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
16709
16710/******************** Bits definition for RTC_TAMPCR register ***************/
16711#define RTC_TAMPCR_TAMP3MF_Pos (24U)
16712#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
16713#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
16714#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
16715#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
16716#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
16717#define RTC_TAMPCR_TAMP3IE_Pos (22U)
16718#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
16719#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
16720#define RTC_TAMPCR_TAMP2MF_Pos (21U)
16721#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
16722#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
16723#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
16724#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
16725#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
16726#define RTC_TAMPCR_TAMP2IE_Pos (19U)
16727#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
16728#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
16729#define RTC_TAMPCR_TAMP1MF_Pos (18U)
16730#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
16731#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
16732#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
16733#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
16734#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
16735#define RTC_TAMPCR_TAMP1IE_Pos (16U)
16736#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
16737#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
16738#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
16739#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
16740#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
16741#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
16742#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
16743#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
16744#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
16745#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
16746#define RTC_TAMPCR_TAMPFLT_Pos (11U)
16747#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
16748#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
16749#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
16750#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
16751#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
16752#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
16753#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
16754#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
16755#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
16756#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
16757#define RTC_TAMPCR_TAMPTS_Pos (7U)
16758#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
16759#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
16760#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
16761#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
16762#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
16763#define RTC_TAMPCR_TAMP3E_Pos (5U)
16764#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
16765#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
16766#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
16767#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
16768#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
16769#define RTC_TAMPCR_TAMP2E_Pos (3U)
16770#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
16771#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
16772#define RTC_TAMPCR_TAMPIE_Pos (2U)
16773#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
16774#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
16775#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
16776#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
16777#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
16778#define RTC_TAMPCR_TAMP1E_Pos (0U)
16779#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
16780#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
16781
16782/******************** Bits definition for RTC_ALRMASSR register *************/
16783#define RTC_ALRMASSR_MASKSS_Pos (24U)
16784#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
16785#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
16786#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
16787#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
16788#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
16789#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
16790#define RTC_ALRMASSR_SS_Pos (0U)
16791#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
16792#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
16793
16794/******************** Bits definition for RTC_ALRMBSSR register *************/
16795#define RTC_ALRMBSSR_MASKSS_Pos (24U)
16796#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
16797#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
16798#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
16799#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
16800#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
16801#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
16802#define RTC_ALRMBSSR_SS_Pos (0U)
16803#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
16804#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
16805
16806/******************** Bits definition for RTC_OR register *******************/
16807#define RTC_OR_OUT_RMP_Pos (1U)
16808#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
16809#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
16810#define RTC_OR_ALARMOUTTYPE_Pos (0U)
16811#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
16812#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
16813
16814/******************** Bits definition for RTC_BKP0R register ****************/
16815#define RTC_BKP0R_Pos (0U)
16816#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
16817#define RTC_BKP0R RTC_BKP0R_Msk
16818
16819/******************** Bits definition for RTC_BKP1R register ****************/
16820#define RTC_BKP1R_Pos (0U)
16821#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
16822#define RTC_BKP1R RTC_BKP1R_Msk
16823
16824/******************** Bits definition for RTC_BKP2R register ****************/
16825#define RTC_BKP2R_Pos (0U)
16826#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
16827#define RTC_BKP2R RTC_BKP2R_Msk
16828
16829/******************** Bits definition for RTC_BKP3R register ****************/
16830#define RTC_BKP3R_Pos (0U)
16831#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
16832#define RTC_BKP3R RTC_BKP3R_Msk
16833
16834/******************** Bits definition for RTC_BKP4R register ****************/
16835#define RTC_BKP4R_Pos (0U)
16836#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
16837#define RTC_BKP4R RTC_BKP4R_Msk
16838
16839/******************** Bits definition for RTC_BKP5R register ****************/
16840#define RTC_BKP5R_Pos (0U)
16841#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
16842#define RTC_BKP5R RTC_BKP5R_Msk
16843
16844/******************** Bits definition for RTC_BKP6R register ****************/
16845#define RTC_BKP6R_Pos (0U)
16846#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
16847#define RTC_BKP6R RTC_BKP6R_Msk
16848
16849/******************** Bits definition for RTC_BKP7R register ****************/
16850#define RTC_BKP7R_Pos (0U)
16851#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
16852#define RTC_BKP7R RTC_BKP7R_Msk
16853
16854/******************** Bits definition for RTC_BKP8R register ****************/
16855#define RTC_BKP8R_Pos (0U)
16856#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
16857#define RTC_BKP8R RTC_BKP8R_Msk
16858
16859/******************** Bits definition for RTC_BKP9R register ****************/
16860#define RTC_BKP9R_Pos (0U)
16861#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
16862#define RTC_BKP9R RTC_BKP9R_Msk
16863
16864/******************** Bits definition for RTC_BKP10R register ***************/
16865#define RTC_BKP10R_Pos (0U)
16866#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
16867#define RTC_BKP10R RTC_BKP10R_Msk
16868
16869/******************** Bits definition for RTC_BKP11R register ***************/
16870#define RTC_BKP11R_Pos (0U)
16871#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
16872#define RTC_BKP11R RTC_BKP11R_Msk
16873
16874/******************** Bits definition for RTC_BKP12R register ***************/
16875#define RTC_BKP12R_Pos (0U)
16876#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
16877#define RTC_BKP12R RTC_BKP12R_Msk
16878
16879/******************** Bits definition for RTC_BKP13R register ***************/
16880#define RTC_BKP13R_Pos (0U)
16881#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
16882#define RTC_BKP13R RTC_BKP13R_Msk
16883
16884/******************** Bits definition for RTC_BKP14R register ***************/
16885#define RTC_BKP14R_Pos (0U)
16886#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
16887#define RTC_BKP14R RTC_BKP14R_Msk
16888
16889/******************** Bits definition for RTC_BKP15R register ***************/
16890#define RTC_BKP15R_Pos (0U)
16891#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
16892#define RTC_BKP15R RTC_BKP15R_Msk
16893
16894/******************** Bits definition for RTC_BKP16R register ***************/
16895#define RTC_BKP16R_Pos (0U)
16896#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
16897#define RTC_BKP16R RTC_BKP16R_Msk
16898
16899/******************** Bits definition for RTC_BKP17R register ***************/
16900#define RTC_BKP17R_Pos (0U)
16901#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
16902#define RTC_BKP17R RTC_BKP17R_Msk
16903
16904/******************** Bits definition for RTC_BKP18R register ***************/
16905#define RTC_BKP18R_Pos (0U)
16906#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
16907#define RTC_BKP18R RTC_BKP18R_Msk
16908
16909/******************** Bits definition for RTC_BKP19R register ***************/
16910#define RTC_BKP19R_Pos (0U)
16911#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
16912#define RTC_BKP19R RTC_BKP19R_Msk
16913
16914/******************** Bits definition for RTC_BKP20R register ***************/
16915#define RTC_BKP20R_Pos (0U)
16916#define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
16917#define RTC_BKP20R RTC_BKP20R_Msk
16918
16919/******************** Bits definition for RTC_BKP21R register ***************/
16920#define RTC_BKP21R_Pos (0U)
16921#define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
16922#define RTC_BKP21R RTC_BKP21R_Msk
16923
16924/******************** Bits definition for RTC_BKP22R register ***************/
16925#define RTC_BKP22R_Pos (0U)
16926#define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
16927#define RTC_BKP22R RTC_BKP22R_Msk
16928
16929/******************** Bits definition for RTC_BKP23R register ***************/
16930#define RTC_BKP23R_Pos (0U)
16931#define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
16932#define RTC_BKP23R RTC_BKP23R_Msk
16933
16934/******************** Bits definition for RTC_BKP24R register ***************/
16935#define RTC_BKP24R_Pos (0U)
16936#define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
16937#define RTC_BKP24R RTC_BKP24R_Msk
16938
16939/******************** Bits definition for RTC_BKP25R register ***************/
16940#define RTC_BKP25R_Pos (0U)
16941#define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
16942#define RTC_BKP25R RTC_BKP25R_Msk
16943
16944/******************** Bits definition for RTC_BKP26R register ***************/
16945#define RTC_BKP26R_Pos (0U)
16946#define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
16947#define RTC_BKP26R RTC_BKP26R_Msk
16948
16949/******************** Bits definition for RTC_BKP27R register ***************/
16950#define RTC_BKP27R_Pos (0U)
16951#define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
16952#define RTC_BKP27R RTC_BKP27R_Msk
16953
16954/******************** Bits definition for RTC_BKP28R register ***************/
16955#define RTC_BKP28R_Pos (0U)
16956#define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
16957#define RTC_BKP28R RTC_BKP28R_Msk
16958
16959/******************** Bits definition for RTC_BKP29R register ***************/
16960#define RTC_BKP29R_Pos (0U)
16961#define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
16962#define RTC_BKP29R RTC_BKP29R_Msk
16963
16964/******************** Bits definition for RTC_BKP30R register ***************/
16965#define RTC_BKP30R_Pos (0U)
16966#define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
16967#define RTC_BKP30R RTC_BKP30R_Msk
16968
16969/******************** Bits definition for RTC_BKP31R register ***************/
16970#define RTC_BKP31R_Pos (0U)
16971#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
16972#define RTC_BKP31R RTC_BKP31R_Msk
16973
16974/******************** Number of backup registers ******************************/
16975#define RTC_BKP_NUMBER_Pos (5U)
16976#define RTC_BKP_NUMBER_Msk (0x1UL << RTC_BKP_NUMBER_Pos) /*!< 0x00000020 */
16977#define RTC_BKP_NUMBER RTC_BKP_NUMBER_Msk
16978
16979/******************************************************************************/
16980/* */
16981/* SPDIF-RX Interface */
16982/* */
16983/******************************************************************************/
16984/******************** Bit definition for SPDIF_CR register ******************/
16985#define SPDIFRX_CR_SPDIFEN_Pos (0U)
16986#define SPDIFRX_CR_SPDIFEN_Msk (0x3UL << SPDIFRX_CR_SPDIFEN_Pos) /*!< 0x00000003 */
16987#define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk /*!<Peripheral Block Enable */
16988#define SPDIFRX_CR_RXDMAEN_Pos (2U)
16989#define SPDIFRX_CR_RXDMAEN_Msk (0x1UL << SPDIFRX_CR_RXDMAEN_Pos) /*!< 0x00000004 */
16990#define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk /*!<Receiver DMA Enable for data flow */
16991#define SPDIFRX_CR_RXSTEO_Pos (3U)
16992#define SPDIFRX_CR_RXSTEO_Msk (0x1UL << SPDIFRX_CR_RXSTEO_Pos) /*!< 0x00000008 */
16993#define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk /*!<Stereo Mode */
16994#define SPDIFRX_CR_DRFMT_Pos (4U)
16995#define SPDIFRX_CR_DRFMT_Msk (0x3UL << SPDIFRX_CR_DRFMT_Pos) /*!< 0x00000030 */
16996#define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk /*!<RX Data format */
16997#define SPDIFRX_CR_PMSK_Pos (6U)
16998#define SPDIFRX_CR_PMSK_Msk (0x1UL << SPDIFRX_CR_PMSK_Pos) /*!< 0x00000040 */
16999#define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk /*!<Mask Parity error bit */
17000#define SPDIFRX_CR_VMSK_Pos (7U)
17001#define SPDIFRX_CR_VMSK_Msk (0x1UL << SPDIFRX_CR_VMSK_Pos) /*!< 0x00000080 */
17002#define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk /*!<Mask of Validity bit */
17003#define SPDIFRX_CR_CUMSK_Pos (8U)
17004#define SPDIFRX_CR_CUMSK_Msk (0x1UL << SPDIFRX_CR_CUMSK_Pos) /*!< 0x00000100 */
17005#define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk /*!<Mask of channel status and user bits */
17006#define SPDIFRX_CR_PTMSK_Pos (9U)
17007#define SPDIFRX_CR_PTMSK_Msk (0x1UL << SPDIFRX_CR_PTMSK_Pos) /*!< 0x00000200 */
17008#define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk /*!<Mask of Preamble Type bits */
17009#define SPDIFRX_CR_CBDMAEN_Pos (10U)
17010#define SPDIFRX_CR_CBDMAEN_Msk (0x1UL << SPDIFRX_CR_CBDMAEN_Pos) /*!< 0x00000400 */
17011#define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk /*!<Control Buffer DMA ENable for control flow */
17012#define SPDIFRX_CR_CHSEL_Pos (11U)
17013#define SPDIFRX_CR_CHSEL_Msk (0x1UL << SPDIFRX_CR_CHSEL_Pos) /*!< 0x00000800 */
17014#define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk /*!<Channel Selection */
17015#define SPDIFRX_CR_NBTR_Pos (12U)
17016#define SPDIFRX_CR_NBTR_Msk (0x3UL << SPDIFRX_CR_NBTR_Pos) /*!< 0x00003000 */
17017#define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchronization phase */
17018#define SPDIFRX_CR_WFA_Pos (14U)
17019#define SPDIFRX_CR_WFA_Msk (0x1UL << SPDIFRX_CR_WFA_Pos) /*!< 0x00004000 */
17020#define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk /*!<Wait For Activity */
17021#define SPDIFRX_CR_INSEL_Pos (16U)
17022#define SPDIFRX_CR_INSEL_Msk (0x7UL << SPDIFRX_CR_INSEL_Pos) /*!< 0x00070000 */
17023#define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk /*!<SPDIF input selection */
17024#define SPDIFRX_CR_CKSEN_Pos (20U)
17025#define SPDIFRX_CR_CKSEN_Msk (0x1UL << SPDIFRX_CR_CKSEN_Pos) /*!< 0x00100000 */
17026#define SPDIFRX_CR_CKSEN SPDIFRX_CR_CKSEN_Msk /*!<Symbol Clock Enable */
17027#define SPDIFRX_CR_CKSBKPEN_Pos (21U)
17028#define SPDIFRX_CR_CKSBKPEN_Msk (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos) /*!< 0x00200000 */
17029#define SPDIFRX_CR_CKSBKPEN SPDIFRX_CR_CKSBKPEN_Msk /*!<Backup Symbol Clock Enable */
17030
17031/******************* Bit definition for SPDIFRX_IMR register *******************/
17032#define SPDIFRX_IMR_RXNEIE_Pos (0U)
17033#define SPDIFRX_IMR_RXNEIE_Msk (0x1UL << SPDIFRX_IMR_RXNEIE_Pos) /*!< 0x00000001 */
17034#define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk /*!<RXNE interrupt enable */
17035#define SPDIFRX_IMR_CSRNEIE_Pos (1U)
17036#define SPDIFRX_IMR_CSRNEIE_Msk (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos) /*!< 0x00000002 */
17037#define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk /*!<Control Buffer Ready Interrupt Enable */
17038#define SPDIFRX_IMR_PERRIE_Pos (2U)
17039#define SPDIFRX_IMR_PERRIE_Msk (0x1UL << SPDIFRX_IMR_PERRIE_Pos) /*!< 0x00000004 */
17040#define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk /*!<Parity error interrupt enable */
17041#define SPDIFRX_IMR_OVRIE_Pos (3U)
17042#define SPDIFRX_IMR_OVRIE_Msk (0x1UL << SPDIFRX_IMR_OVRIE_Pos) /*!< 0x00000008 */
17043#define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk /*!<Overrun error Interrupt Enable */
17044#define SPDIFRX_IMR_SBLKIE_Pos (4U)
17045#define SPDIFRX_IMR_SBLKIE_Msk (0x1UL << SPDIFRX_IMR_SBLKIE_Pos) /*!< 0x00000010 */
17046#define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk /*!<Synchronization Block Detected Interrupt Enable */
17047#define SPDIFRX_IMR_SYNCDIE_Pos (5U)
17048#define SPDIFRX_IMR_SYNCDIE_Msk (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos) /*!< 0x00000020 */
17049#define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk /*!<Synchronization Done */
17050#define SPDIFRX_IMR_IFEIE_Pos (6U)
17051#define SPDIFRX_IMR_IFEIE_Msk (0x1UL << SPDIFRX_IMR_IFEIE_Pos) /*!< 0x00000040 */
17052#define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk /*!<Serial Interface Error Interrupt Enable */
17053
17054/******************* Bit definition for SPDIFRX_SR register *******************/
17055#define SPDIFRX_SR_RXNE_Pos (0U)
17056#define SPDIFRX_SR_RXNE_Msk (0x1UL << SPDIFRX_SR_RXNE_Pos) /*!< 0x00000001 */
17057#define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk /*!<Read data register not empty */
17058#define SPDIFRX_SR_CSRNE_Pos (1U)
17059#define SPDIFRX_SR_CSRNE_Msk (0x1UL << SPDIFRX_SR_CSRNE_Pos) /*!< 0x00000002 */
17060#define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk /*!<The Control Buffer register is not empty */
17061#define SPDIFRX_SR_PERR_Pos (2U)
17062#define SPDIFRX_SR_PERR_Msk (0x1UL << SPDIFRX_SR_PERR_Pos) /*!< 0x00000004 */
17063#define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk /*!<Parity error */
17064#define SPDIFRX_SR_OVR_Pos (3U)
17065#define SPDIFRX_SR_OVR_Msk (0x1UL << SPDIFRX_SR_OVR_Pos) /*!< 0x00000008 */
17066#define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk /*!<Overrun error */
17067#define SPDIFRX_SR_SBD_Pos (4U)
17068#define SPDIFRX_SR_SBD_Msk (0x1UL << SPDIFRX_SR_SBD_Pos) /*!< 0x00000010 */
17069#define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk /*!<Synchronization Block Detected */
17070#define SPDIFRX_SR_SYNCD_Pos (5U)
17071#define SPDIFRX_SR_SYNCD_Msk (0x1UL << SPDIFRX_SR_SYNCD_Pos) /*!< 0x00000020 */
17072#define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk /*!<Synchronization Done */
17073#define SPDIFRX_SR_FERR_Pos (6U)
17074#define SPDIFRX_SR_FERR_Msk (0x1UL << SPDIFRX_SR_FERR_Pos) /*!< 0x00000040 */
17075#define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk /*!<Framing error */
17076#define SPDIFRX_SR_SERR_Pos (7U)
17077#define SPDIFRX_SR_SERR_Msk (0x1UL << SPDIFRX_SR_SERR_Pos) /*!< 0x00000080 */
17078#define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk /*!<Synchronization error */
17079#define SPDIFRX_SR_TERR_Pos (8U)
17080#define SPDIFRX_SR_TERR_Msk (0x1UL << SPDIFRX_SR_TERR_Pos) /*!< 0x00000100 */
17081#define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error */
17082#define SPDIFRX_SR_WIDTH5_Pos (16U)
17083#define SPDIFRX_SR_WIDTH5_Msk (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos) /*!< 0x7FFF0000 */
17084#define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk /*!<Duration of 5 symbols counted with spdif_clk */
17085
17086/******************* Bit definition for SPDIFRX_IFCR register *******************/
17087#define SPDIFRX_IFCR_PERRCF_Pos (2U)
17088#define SPDIFRX_IFCR_PERRCF_Msk (0x1UL << SPDIFRX_IFCR_PERRCF_Pos) /*!< 0x00000004 */
17089#define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk /*!<Clears the Parity error flag */
17090#define SPDIFRX_IFCR_OVRCF_Pos (3U)
17091#define SPDIFRX_IFCR_OVRCF_Msk (0x1UL << SPDIFRX_IFCR_OVRCF_Pos) /*!< 0x00000008 */
17092#define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk /*!<Clears the Overrun error flag */
17093#define SPDIFRX_IFCR_SBDCF_Pos (4U)
17094#define SPDIFRX_IFCR_SBDCF_Msk (0x1UL << SPDIFRX_IFCR_SBDCF_Pos) /*!< 0x00000010 */
17095#define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk /*!<Clears the Synchronization Block Detected flag */
17096#define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
17097#define SPDIFRX_IFCR_SYNCDCF_Msk (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos) /*!< 0x00000020 */
17098#define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk /*!<Clears the Synchronization Done flag */
17099
17100/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
17101#define SPDIFRX_DR0_DR_Pos (0U)
17102#define SPDIFRX_DR0_DR_Msk (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos) /*!< 0x00FFFFFF */
17103#define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk /*!<Data value */
17104#define SPDIFRX_DR0_PE_Pos (24U)
17105#define SPDIFRX_DR0_PE_Msk (0x1UL << SPDIFRX_DR0_PE_Pos) /*!< 0x01000000 */
17106#define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk /*!<Parity Error bit */
17107#define SPDIFRX_DR0_V_Pos (25U)
17108#define SPDIFRX_DR0_V_Msk (0x1UL << SPDIFRX_DR0_V_Pos) /*!< 0x02000000 */
17109#define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk /*!<Validity bit */
17110#define SPDIFRX_DR0_U_Pos (26U)
17111#define SPDIFRX_DR0_U_Msk (0x1UL << SPDIFRX_DR0_U_Pos) /*!< 0x04000000 */
17112#define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk /*!<User bit */
17113#define SPDIFRX_DR0_C_Pos (27U)
17114#define SPDIFRX_DR0_C_Msk (0x1UL << SPDIFRX_DR0_C_Pos) /*!< 0x08000000 */
17115#define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk /*!<Channel Status bit */
17116#define SPDIFRX_DR0_PT_Pos (28U)
17117#define SPDIFRX_DR0_PT_Msk (0x3UL << SPDIFRX_DR0_PT_Pos) /*!< 0x30000000 */
17118#define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk /*!<Preamble Type */
17119
17120/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
17121#define SPDIFRX_DR1_DR_Pos (8U)
17122#define SPDIFRX_DR1_DR_Msk (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos) /*!< 0xFFFFFF00 */
17123#define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk /*!<Data value */
17124#define SPDIFRX_DR1_PT_Pos (4U)
17125#define SPDIFRX_DR1_PT_Msk (0x3UL << SPDIFRX_DR1_PT_Pos) /*!< 0x00000030 */
17126#define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk /*!<Preamble Type */
17127#define SPDIFRX_DR1_C_Pos (3U)
17128#define SPDIFRX_DR1_C_Msk (0x1UL << SPDIFRX_DR1_C_Pos) /*!< 0x00000008 */
17129#define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk /*!<Channel Status bit */
17130#define SPDIFRX_DR1_U_Pos (2U)
17131#define SPDIFRX_DR1_U_Msk (0x1UL << SPDIFRX_DR1_U_Pos) /*!< 0x00000004 */
17132#define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk /*!<User bit */
17133#define SPDIFRX_DR1_V_Pos (1U)
17134#define SPDIFRX_DR1_V_Msk (0x1UL << SPDIFRX_DR1_V_Pos) /*!< 0x00000002 */
17135#define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk /*!<Validity bit */
17136#define SPDIFRX_DR1_PE_Pos (0U)
17137#define SPDIFRX_DR1_PE_Msk (0x1UL << SPDIFRX_DR1_PE_Pos) /*!< 0x00000001 */
17138#define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk /*!<Parity Error bit */
17139
17140/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
17141#define SPDIFRX_DR1_DRNL1_Pos (16U)
17142#define SPDIFRX_DR1_DRNL1_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos) /*!< 0xFFFF0000 */
17143#define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk /*!<Data value Channel B */
17144#define SPDIFRX_DR1_DRNL2_Pos (0U)
17145#define SPDIFRX_DR1_DRNL2_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos) /*!< 0x0000FFFF */
17146#define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk /*!<Data value Channel A */
17147
17148/******************* Bit definition for SPDIFRX_CSR register *******************/
17149#define SPDIFRX_CSR_USR_Pos (0U)
17150#define SPDIFRX_CSR_USR_Msk (0xFFFFUL << SPDIFRX_CSR_USR_Pos) /*!< 0x0000FFFF */
17151#define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk /*!<User data information */
17152#define SPDIFRX_CSR_CS_Pos (16U)
17153#define SPDIFRX_CSR_CS_Msk (0xFFUL << SPDIFRX_CSR_CS_Pos) /*!< 0x00FF0000 */
17154#define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk /*!<Channel A status information */
17155#define SPDIFRX_CSR_SOB_Pos (24U)
17156#define SPDIFRX_CSR_SOB_Msk (0x1UL << SPDIFRX_CSR_SOB_Pos) /*!< 0x01000000 */
17157#define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk /*!<Start Of Block */
17158
17159/******************* Bit definition for SPDIFRX_DIR register *******************/
17160#define SPDIFRX_DIR_THI_Pos (0U)
17161#define SPDIFRX_DIR_THI_Msk (0x1FFFUL << SPDIFRX_DIR_THI_Pos) /*!< 0x00001FFF */
17162#define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk /*!<Threshold LOW */
17163#define SPDIFRX_DIR_TLO_Pos (16U)
17164#define SPDIFRX_DIR_TLO_Msk (0x1FFFUL << SPDIFRX_DIR_TLO_Pos) /*!< 0x1FFF0000 */
17165#define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk /*!<Threshold HIGH */
17166
17167/******************* Bit definition for SPDIFRX_VERR register *******************/
17168#define SPDIFRX_VERR_MINREV_Pos (0U)
17169#define SPDIFRX_VERR_MINREV_Msk (0xFUL << SPDIFRX_VERR_MINREV_Pos) /*!< 0x0000000F */
17170#define SPDIFRX_VERR_MINREV SPDIFRX_VERR_MINREV_Msk /*!<SPDIFRX Minor revision */
17171#define SPDIFRX_VERR_MAJREV_Pos (4U)
17172#define SPDIFRX_VERR_MAJREV_Msk (0xFUL << SPDIFRX_VERR_MAJREV_Pos) /*!< 0x000000F0 */
17173#define SPDIFRX_VERR_MAJREV SPDIFRX_VERR_MAJREV_Msk /*!<SPDIFRX Major revision */
17174
17175/******************* Bit definition for SPDIFRX_IDR register *******************/
17176#define SPDIFRX_IDR_ID_Pos (0U)
17177#define SPDIFRX_IDR_ID_Msk (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos) /*!< 0xFFFFFFFF */
17178#define SPDIFRX_IDR_ID SPDIFRX_IDR_ID_Msk /*!<SPDIFRX identifier */
17179
17180/******************* Bit definition for SPDIFRX_SIDR register *******************/
17181#define SPDIFRX_SIDR_SID_Pos (0U)
17182#define SPDIFRX_SIDR_SID_Msk (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
17183#define SPDIFRX_SIDR_SID SPDIFRX_SIDR_SID_Msk /*!<Size of the memory region allocated to SPDIFRX registers */
17184
17185/******************************************************************************/
17186/* */
17187/* Serial Audio Interface */
17188/* */
17189/******************************************************************************/
17190/******************************* SAI VERSION ********************************/
17191#define SAI_VER_V2_X
17192
17193/******************** Bit definition for SAI_GCR register *******************/
17194#define SAI_GCR_SYNCIN_Pos (0U)
17195#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
17196#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
17197#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
17198#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
17199
17200#define SAI_GCR_SYNCOUT_Pos (4U)
17201#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
17202#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
17203#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
17204#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
17205
17206/******************* Bit definition for SAI_xCR1 register *******************/
17207#define SAI_xCR1_MODE_Pos (0U)
17208#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
17209#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
17210#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
17211#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
17212
17213#define SAI_xCR1_PRTCFG_Pos (2U)
17214#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
17215#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
17216#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
17217#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
17218
17219#define SAI_xCR1_DS_Pos (5U)
17220#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
17221#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
17222#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
17223#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
17224#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
17225
17226#define SAI_xCR1_LSBFIRST_Pos (8U)
17227#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
17228#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
17229#define SAI_xCR1_CKSTR_Pos (9U)
17230#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
17231#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
17232
17233#define SAI_xCR1_SYNCEN_Pos (10U)
17234#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
17235#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
17236#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
17237#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
17238
17239#define SAI_xCR1_MONO_Pos (12U)
17240#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
17241#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
17242#define SAI_xCR1_OUTDRIV_Pos (13U)
17243#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
17244#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
17245#define SAI_xCR1_SAIEN_Pos (16U)
17246#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
17247#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
17248#define SAI_xCR1_DMAEN_Pos (17U)
17249#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
17250#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
17251#define SAI_xCR1_NODIV_Pos (19U)
17252#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
17253#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
17254
17255#define SAI_xCR1_MCKDIV_Pos (20U)
17256#define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */
17257#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[5:0] (Master ClocK Divider) */
17258#define SAI_xCR1_MCKDIV_0 (0x01UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
17259#define SAI_xCR1_MCKDIV_1 (0x02UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
17260#define SAI_xCR1_MCKDIV_2 (0x04UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
17261#define SAI_xCR1_MCKDIV_3 (0x08UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
17262#define SAI_xCR1_MCKDIV_4 (0x10UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x01000000 */
17263#define SAI_xCR1_MCKDIV_5 (0x20UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x02000000 */
17264
17265#define SAI_xCR1_MCKEN_Pos (27U)
17266#define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos) /*!< 0x08000000 */
17267#define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk /*!<Master ClocK enable */
17268
17269#define SAI_xCR1_OSR_Pos (26U)
17270#define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */
17271#define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<OverSampling Ratio for master clock */
17272
17273/* Legacy define */
17274#define SAI_xCR1_NOMCK SAI_xCR1_NODIV
17275
17276/******************* Bit definition for SAI_xCR2 register *******************/
17277#define SAI_xCR2_FTH_Pos (0U)
17278#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
17279#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
17280#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
17281#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
17282#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
17283
17284#define SAI_xCR2_FFLUSH_Pos (3U)
17285#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
17286#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
17287#define SAI_xCR2_TRIS_Pos (4U)
17288#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
17289#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
17290#define SAI_xCR2_MUTE_Pos (5U)
17291#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
17292#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
17293#define SAI_xCR2_MUTEVAL_Pos (6U)
17294#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
17295#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
17296
17297#define SAI_xCR2_MUTECNT_Pos (7U)
17298#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
17299#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
17300#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
17301#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
17302#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
17303#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
17304#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
17305#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
17306
17307#define SAI_xCR2_CPL_Pos (13U)
17308#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
17309#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
17310
17311#define SAI_xCR2_COMP_Pos (14U)
17312#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
17313#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
17314#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
17315#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
17316
17317/****************** Bit definition for SAI_xFRCR register *******************/
17318#define SAI_xFRCR_FRL_Pos (0U)
17319#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
17320#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](FRame Length) */
17321#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
17322#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
17323#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
17324#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
17325#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
17326#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
17327#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
17328#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
17329
17330#define SAI_xFRCR_FSALL_Pos (8U)
17331#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
17332#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FSALL[6:0] (Frame Synchronization Active Level Length) */
17333#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
17334#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
17335#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
17336#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
17337#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
17338#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
17339#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
17340
17341#define SAI_xFRCR_FSDEF_Pos (16U)
17342#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
17343#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!<Frame Synchronization Definition */
17344#define SAI_xFRCR_FSPOL_Pos (17U)
17345#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
17346#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
17347#define SAI_xFRCR_FSOFF_Pos (18U)
17348#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
17349#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
17350
17351/* Legacy define */
17352#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
17353
17354/****************** Bit definition for SAI_xSLOTR register *******************/
17355#define SAI_xSLOTR_FBOFF_Pos (0U)
17356#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
17357#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FBOFF[4:0](First Bit Offset) */
17358#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
17359#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
17360#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
17361#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
17362#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
17363
17364#define SAI_xSLOTR_SLOTSZ_Pos (6U)
17365#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
17366#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
17367#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
17368#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
17369
17370#define SAI_xSLOTR_NBSLOT_Pos (8U)
17371#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
17372#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
17373#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
17374#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
17375#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
17376#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
17377
17378#define SAI_xSLOTR_SLOTEN_Pos (16U)
17379#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
17380#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
17381
17382/******************* Bit definition for SAI_xIMR register *******************/
17383#define SAI_xIMR_OVRUDRIE_Pos (0U)
17384#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
17385#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
17386#define SAI_xIMR_MUTEDETIE_Pos (1U)
17387#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
17388#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
17389#define SAI_xIMR_WCKCFGIE_Pos (2U)
17390#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
17391#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
17392#define SAI_xIMR_FREQIE_Pos (3U)
17393#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
17394#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
17395#define SAI_xIMR_CNRDYIE_Pos (4U)
17396#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
17397#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
17398#define SAI_xIMR_AFSDETIE_Pos (5U)
17399#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
17400#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
17401#define SAI_xIMR_LFSDETIE_Pos (6U)
17402#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
17403#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
17404
17405/******************** Bit definition for SAI_xSR register *******************/
17406#define SAI_xSR_OVRUDR_Pos (0U)
17407#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
17408#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
17409#define SAI_xSR_MUTEDET_Pos (1U)
17410#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
17411#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
17412#define SAI_xSR_WCKCFG_Pos (2U)
17413#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
17414#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
17415#define SAI_xSR_FREQ_Pos (3U)
17416#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
17417#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
17418#define SAI_xSR_CNRDY_Pos (4U)
17419#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
17420#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
17421#define SAI_xSR_AFSDET_Pos (5U)
17422#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
17423#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
17424#define SAI_xSR_LFSDET_Pos (6U)
17425#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
17426#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
17427
17428#define SAI_xSR_FLVL_Pos (16U)
17429#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
17430#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
17431#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
17432#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
17433#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
17434
17435/****************** Bit definition for SAI_xCLRFR register ******************/
17436#define SAI_xCLRFR_COVRUDR_Pos (0U)
17437#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
17438#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
17439#define SAI_xCLRFR_CMUTEDET_Pos (1U)
17440#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
17441#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
17442#define SAI_xCLRFR_CWCKCFG_Pos (2U)
17443#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
17444#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
17445#define SAI_xCLRFR_CFREQ_Pos (3U)
17446#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
17447#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
17448#define SAI_xCLRFR_CCNRDY_Pos (4U)
17449#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
17450#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
17451#define SAI_xCLRFR_CAFSDET_Pos (5U)
17452#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
17453#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
17454#define SAI_xCLRFR_CLFSDET_Pos (6U)
17455#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
17456#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
17457
17458/****************** Bit definition for SAI_xDR register *********************/
17459#define SAI_xDR_DATA_Pos (0U)
17460#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
17461#define SAI_xDR_DATA SAI_xDR_DATA_Msk
17462
17463/******************* Bit definition for SAI_PDMCR register ******************/
17464#define SAI_PDMCR_PDMEN_Pos (0U)
17465#define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos) /*!< 0x00000001 */
17466#define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk /*!<PDM Enable */
17467
17468#define SAI_PDMCR_MICNBR_Pos (4U)
17469#define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000030 */
17470#define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk /*!<Number of microphones */
17471#define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000010 */
17472#define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000020 */
17473
17474#define SAI_PDMCR_CKEN1_Pos (8U)
17475#define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos) /*!< 0x00000100 */
17476#define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk /*!<Clock enable of bitstream clock number 1 */
17477#define SAI_PDMCR_CKEN2_Pos (9U)
17478#define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos) /*!< 0x00000200 */
17479#define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk /*!<Clock enable of bitstream clock number 2 */
17480#define SAI_PDMCR_CKEN3_Pos (10U)
17481#define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos) /*!< 0x00000400 */
17482#define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk /*!<Clock enable of bitstream clock number 3 */
17483#define SAI_PDMCR_CKEN4_Pos (11U)
17484#define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos) /*!< 0x00000800 */
17485#define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk /*!<Clock enable of bitstream clock number 4 */
17486
17487/****************** Bit definition for SAI_PDMDLY register ******************/
17488#define SAI_PDMDLY_DLYM1L_Pos (0U)
17489#define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000007 */
17490#define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
17491#define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000001 */
17492#define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000002 */
17493#define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000004 */
17494
17495#define SAI_PDMDLY_DLYM1R_Pos (4U)
17496#define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000070 */
17497#define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
17498#define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000010 */
17499#define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000020 */
17500#define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000040 */
17501
17502#define SAI_PDMDLY_DLYM2L_Pos (8U)
17503#define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000700 */
17504#define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
17505#define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000100 */
17506#define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000200 */
17507#define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000400 */
17508
17509#define SAI_PDMDLY_DLYM2R_Pos (12U)
17510#define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00007000 */
17511#define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/
17512#define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00001000 */
17513#define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00002000 */
17514#define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00004000 */
17515
17516#define SAI_PDMDLY_DLYM3L_Pos (16U)
17517#define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00070000 */
17518#define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/
17519#define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00010000 */
17520#define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00020000 */
17521#define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00040000 */
17522
17523#define SAI_PDMDLY_DLYM3R_Pos (20U)
17524#define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00700000 */
17525#define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/
17526#define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00100000 */
17527#define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00200000 */
17528#define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00400000 */
17529
17530#define SAI_PDMDLY_DLYM4L_Pos (24U)
17531#define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x07000000 */
17532#define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/
17533#define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x01000000 */
17534#define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x02000000 */
17535#define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x04000000 */
17536
17537#define SAI_PDMDLY_DLYM4R_Pos (28U)
17538#define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x70000000 */
17539#define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/
17540#define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x10000000 */
17541#define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */
17542#define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */
17543
17544/******************************************************************************/
17545/* */
17546/* SDMMC Interface */
17547/* */
17548/******************************************************************************/
17549/****************** Bit definition for SDMMC_POWER register ******************/
17550#define SDMMC_POWER_PWRCTRL_Pos (0U)
17551#define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
17552#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
17553#define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000001 */
17554#define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000002 */
17555#define SDMMC_POWER_VSWITCH_Pos (2U)
17556#define SDMMC_POWER_VSWITCH_Msk (0x1UL << SDMMC_POWER_VSWITCH_Pos) /*!< 0x00000004 */
17557#define SDMMC_POWER_VSWITCH SDMMC_POWER_VSWITCH_Msk /*!<Voltage switch sequence start */
17558#define SDMMC_POWER_VSWITCHEN_Pos (3U)
17559#define SDMMC_POWER_VSWITCHEN_Msk (0x1UL << SDMMC_POWER_VSWITCHEN_Pos) /*!< 0x00000008 */
17560#define SDMMC_POWER_VSWITCHEN SDMMC_POWER_VSWITCHEN_Msk /*!<Voltage switch procedure enable */
17561#define SDMMC_POWER_DIRPOL_Pos (4U)
17562#define SDMMC_POWER_DIRPOL_Msk (0x1UL << SDMMC_POWER_DIRPOL_Pos) /*!< 0x00000010 */
17563#define SDMMC_POWER_DIRPOL SDMMC_POWER_DIRPOL_Msk /*!<Data and Command direction signals polarity selection */
17564
17565/****************** Bit definition for SDMMC_CLKCR register ******************/
17566#define SDMMC_CLKCR_CLKDIV_Pos (0U)
17567#define SDMMC_CLKCR_CLKDIV_Msk (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000003FF */
17568#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
17569#define SDMMC_CLKCR_PWRSAV_Pos (12U)
17570#define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00001000 */
17571#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
17572
17573#define SDMMC_CLKCR_WIDBUS_Pos (14U)
17574#define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x0000C000 */
17575#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
17576#define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00004000 */
17577#define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00008000 */
17578
17579#define SDMMC_CLKCR_NEGEDGE_Pos (16U)
17580#define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00010000 */
17581#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */
17582#define SDMMC_CLKCR_HWFC_EN_Pos (17U)
17583#define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00020000 */
17584#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
17585#define SDMMC_CLKCR_DDR_Pos (18U)
17586#define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
17587#define SDMMC_CLKCR_DDR SDMMC_CLKCR_DDR_Msk /*!<Data rate signaling selection */
17588#define SDMMC_CLKCR_BUSSPEED_Pos (19U)
17589#define SDMMC_CLKCR_BUSSPEED_Msk (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos) /*!< 0x00080000 */
17590#define SDMMC_CLKCR_BUSSPEED SDMMC_CLKCR_BUSSPEED_Msk /*!<Bus speed mode selection */
17591#define SDMMC_CLKCR_SELCLKRX_Pos (20U)
17592#define SDMMC_CLKCR_SELCLKRX_Msk (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00300000 */
17593#define SDMMC_CLKCR_SELCLKRX SDMMC_CLKCR_SELCLKRX_Msk /*!<SELCLKRX[1:0] bits (Receive clock selection) */
17594#define SDMMC_CLKCR_SELCLKRX_0 (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00100000 */
17595#define SDMMC_CLKCR_SELCLKRX_1 (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00200000 */
17596
17597/******************* Bit definition for SDMMC_ARG register *******************/
17598#define SDMMC_ARG_CMDARG_Pos (0U)
17599#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
17600#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */
17601
17602/******************* Bit definition for SDMMC_CMD register *******************/
17603#define SDMMC_CMD_CMDINDEX_Pos (0U)
17604#define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
17605#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */
17606#define SDMMC_CMD_CMDTRANS_Pos (6U)
17607#define SDMMC_CMD_CMDTRANS_Msk (0x1UL << SDMMC_CMD_CMDTRANS_Pos) /*!< 0x00000040 */
17608#define SDMMC_CMD_CMDTRANS SDMMC_CMD_CMDTRANS_Msk /*!<CPSM Treats command as a Data Transfer */
17609#define SDMMC_CMD_CMDSTOP_Pos (7U)
17610#define SDMMC_CMD_CMDSTOP_Msk (0x1UL << SDMMC_CMD_CMDSTOP_Pos) /*!< 0x00000080 */
17611#define SDMMC_CMD_CMDSTOP SDMMC_CMD_CMDSTOP_Msk /*!<CPSM Treats command as a Stop */
17612
17613#define SDMMC_CMD_WAITRESP_Pos (8U)
17614#define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000300 */
17615#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
17616#define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000100 */
17617#define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000200 */
17618
17619#define SDMMC_CMD_WAITINT_Pos (10U)
17620#define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000400 */
17621#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
17622#define SDMMC_CMD_WAITPEND_Pos (11U)
17623#define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000800 */
17624#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
17625#define SDMMC_CMD_CPSMEN_Pos (12U)
17626#define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00001000 */
17627#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
17628#define SDMMC_CMD_DTHOLD_Pos (13U)
17629#define SDMMC_CMD_DTHOLD_Msk (0x1UL << SDMMC_CMD_DTHOLD_Pos) /*!< 0x00002000 */
17630#define SDMMC_CMD_DTHOLD SDMMC_CMD_DTHOLD_Msk /*!<Hold new data block transmission and reception in the DPSM */
17631#define SDMMC_CMD_BOOTMODE_Pos (14U)
17632#define SDMMC_CMD_BOOTMODE_Msk (0x1UL << SDMMC_CMD_BOOTMODE_Pos) /*!< 0x00004000 */
17633#define SDMMC_CMD_BOOTMODE SDMMC_CMD_BOOTMODE_Msk /*!<Boot mode */
17634#define SDMMC_CMD_BOOTEN_Pos (15U)
17635#define SDMMC_CMD_BOOTEN_Msk (0x1UL << SDMMC_CMD_BOOTEN_Pos) /*!< 0x00008000 */
17636#define SDMMC_CMD_BOOTEN SDMMC_CMD_BOOTEN_Msk /*!<Enable Boot mode procedure */
17637#define SDMMC_CMD_CMDSUSPEND_Pos (16U)
17638#define SDMMC_CMD_CMDSUSPEND_Msk (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos) /*!< 0x00010000 */
17639#define SDMMC_CMD_CMDSUSPEND SDMMC_CMD_CMDSUSPEND_Msk /*!<CPSM Treats command as a Suspend or Resume command */
17640
17641/***************** Bit definition for SDMMC_RESPCMD register *****************/
17642#define SDMMC_RESPCMD_RESPCMD_Pos (0U)
17643#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
17644#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */
17645
17646/****************** Bit definition for SDMMC_RESP0 register ******************/
17647#define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
17648#define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
17649#define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk /*!<Card Status */
17650
17651/****************** Bit definition for SDMMC_RESP1 register ******************/
17652#define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
17653#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
17654#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */
17655
17656/****************** Bit definition for SDMMC_RESP2 register ******************/
17657#define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
17658#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
17659#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */
17660
17661/****************** Bit definition for SDMMC_RESP3 register ******************/
17662#define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
17663#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
17664#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */
17665
17666/****************** Bit definition for SDMMC_RESP4 register ******************/
17667#define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
17668#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
17669#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */
17670
17671/****************** Bit definition for SDMMC_DTIMER register *****************/
17672#define SDMMC_DTIMER_DATATIME_Pos (0U)
17673#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
17674#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */
17675
17676/****************** Bit definition for SDMMC_DLEN register *******************/
17677#define SDMMC_DLEN_DATALENGTH_Pos (0U)
17678#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
17679#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */
17680
17681/****************** Bit definition for SDMMC_DCTRL register ******************/
17682#define SDMMC_DCTRL_DTEN_Pos (0U)
17683#define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */
17684#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
17685#define SDMMC_DCTRL_DTDIR_Pos (1U)
17686#define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
17687#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
17688#define SDMMC_DCTRL_DTMODE_Pos (2U)
17689#define SDMMC_DCTRL_DTMODE_Msk (0x3UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x0000000C */
17690#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<DTMODE[1:0] Data transfer mode selection */
17691#define SDMMC_DCTRL_DTMODE_0 (0x1UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
17692#define SDMMC_DCTRL_DTMODE_1 (0x2UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000008 */
17693
17694#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
17695#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
17696#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
17697#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */
17698#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */
17699#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */
17700#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */
17701
17702#define SDMMC_DCTRL_RWSTART_Pos (8U)
17703#define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
17704#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */
17705#define SDMMC_DCTRL_RWSTOP_Pos (9U)
17706#define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
17707#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */
17708#define SDMMC_DCTRL_RWMOD_Pos (10U)
17709#define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
17710#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */
17711#define SDMMC_DCTRL_SDIOEN_Pos (11U)
17712#define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
17713#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
17714#define SDMMC_DCTRL_BOOTACKEN_Pos (12U)
17715#define SDMMC_DCTRL_BOOTACKEN_Msk (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos) /*!< 0x00001000 */
17716#define SDMMC_DCTRL_BOOTACKEN SDMMC_DCTRL_BOOTACKEN_Msk /*!<Enable the reception of the Boot Acknowledgment */
17717#define SDMMC_DCTRL_FIFORST_Pos (13U)
17718#define SDMMC_DCTRL_FIFORST_Msk (0x1UL << SDMMC_DCTRL_FIFORST_Pos) /*!< 0x00002000 */
17719#define SDMMC_DCTRL_FIFORST SDMMC_DCTRL_FIFORST_Msk /*!<FIFO reset */
17720
17721/****************** Bit definition for SDMMC_DCOUNT register *****************/
17722#define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
17723#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
17724#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
17725
17726/****************** Bit definition for SDMMC_STA register ********************/
17727#define SDMMC_STA_CCRCFAIL_Pos (0U)
17728#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
17729#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
17730#define SDMMC_STA_DCRCFAIL_Pos (1U)
17731#define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
17732#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
17733#define SDMMC_STA_CTIMEOUT_Pos (2U)
17734#define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
17735#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */
17736#define SDMMC_STA_DTIMEOUT_Pos (3U)
17737#define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
17738#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */
17739#define SDMMC_STA_TXUNDERR_Pos (4U)
17740#define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */
17741#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
17742#define SDMMC_STA_RXOVERR_Pos (5U)
17743#define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */
17744#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
17745#define SDMMC_STA_CMDREND_Pos (6U)
17746#define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */
17747#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
17748#define SDMMC_STA_CMDSENT_Pos (7U)
17749#define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */
17750#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */
17751#define SDMMC_STA_DATAEND_Pos (8U)
17752#define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
17753#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
17754#define SDMMC_STA_DHOLD_Pos (9U)
17755#define SDMMC_STA_DHOLD_Msk (0x1UL << SDMMC_STA_DHOLD_Pos) /*!< 0x00000200 */
17756#define SDMMC_STA_DHOLD SDMMC_STA_DHOLD_Msk /*!<Data transfer Hold */
17757#define SDMMC_STA_DBCKEND_Pos (10U)
17758#define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
17759#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
17760#define SDMMC_STA_DABORT_Pos (11U)
17761#define SDMMC_STA_DABORT_Msk (0x1UL << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
17762#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
17763#define SDMMC_STA_DPSMACT_Pos (12U)
17764#define SDMMC_STA_DPSMACT_Msk (0x1UL << SDMMC_STA_DPSMACT_Pos) /*!< 0x00001000 */
17765#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Data path state machine active */
17766#define SDMMC_STA_CPSMACT_Pos (13U)
17767#define SDMMC_STA_CPSMACT_Msk (0x1UL << SDMMC_STA_CPSMACT_Pos) /*!< 0x00002000 */
17768#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Command path state machine active */
17769#define SDMMC_STA_TXFIFOHE_Pos (14U)
17770#define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
17771#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
17772#define SDMMC_STA_RXFIFOHF_Pos (15U)
17773#define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
17774#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
17775#define SDMMC_STA_TXFIFOF_Pos (16U)
17776#define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */
17777#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
17778#define SDMMC_STA_RXFIFOF_Pos (17U)
17779#define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */
17780#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */
17781#define SDMMC_STA_TXFIFOE_Pos (18U)
17782#define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */
17783#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
17784#define SDMMC_STA_RXFIFOE_Pos (19U)
17785#define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */
17786#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
17787#define SDMMC_STA_BUSYD0_Pos (20U)
17788#define SDMMC_STA_BUSYD0_Msk (0x1UL << SDMMC_STA_BUSYD0_Pos) /*!< 0x00100000 */
17789#define SDMMC_STA_BUSYD0 SDMMC_STA_BUSYD0_Msk /*!<Inverted value of SDMMC_D0 line (Busy) */
17790#define SDMMC_STA_BUSYD0END_Pos (21U)
17791#define SDMMC_STA_BUSYD0END_Msk (0x1UL << SDMMC_STA_BUSYD0END_Pos) /*!< 0x00200000 */
17792#define SDMMC_STA_BUSYD0END SDMMC_STA_BUSYD0END_Msk /*!<End of SDMMC_D0 Busy following a CMD response detected */
17793#define SDMMC_STA_SDIOIT_Pos (22U)
17794#define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
17795#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDIO interrupt received */
17796#define SDMMC_STA_ACKFAIL_Pos (23U)
17797#define SDMMC_STA_ACKFAIL_Msk (0x1UL << SDMMC_STA_ACKFAIL_Pos) /*!< 0x00800000 */
17798#define SDMMC_STA_ACKFAIL SDMMC_STA_ACKFAIL_Msk /*!<Boot Acknowledgment received (BootAck check fail) */
17799#define SDMMC_STA_ACKTIMEOUT_Pos (24U)
17800#define SDMMC_STA_ACKTIMEOUT_Msk (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos) /*!< 0x01000000 */
17801#define SDMMC_STA_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT_Msk /*!<Boot Acknowledgment timeout */
17802#define SDMMC_STA_VSWEND_Pos (25U)
17803#define SDMMC_STA_VSWEND_Msk (0x1UL << SDMMC_STA_VSWEND_Pos) /*!< 0x02000000 */
17804#define SDMMC_STA_VSWEND SDMMC_STA_VSWEND_Msk /*!<Voltage switch critical timing section completion */
17805#define SDMMC_STA_CKSTOP_Pos (26U)
17806#define SDMMC_STA_CKSTOP_Msk (0x1UL << SDMMC_STA_CKSTOP_Pos) /*!< 0x04000000 */
17807#define SDMMC_STA_CKSTOP SDMMC_STA_CKSTOP_Msk /*!<SDMMC_CK stopped in Voltage switch procedure */
17808#define SDMMC_STA_IDMATE_Pos (27U)
17809#define SDMMC_STA_IDMATE_Msk (0x1UL << SDMMC_STA_IDMATE_Pos) /*!< 0x08000000 */
17810#define SDMMC_STA_IDMATE SDMMC_STA_IDMATE_Msk /*!<IDMA transfer error */
17811#define SDMMC_STA_IDMABTC_Pos (28U)
17812#define SDMMC_STA_IDMABTC_Msk (0x1UL << SDMMC_STA_IDMABTC_Pos) /*!< 0x10000000 */
17813#define SDMMC_STA_IDMABTC SDMMC_STA_IDMABTC_Msk /*!<IDMA buffer transfer complete */
17814
17815/******************* Bit definition for SDMMC_ICR register *******************/
17816#define SDMMC_ICR_CCRCFAILC_Pos (0U)
17817#define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
17818#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
17819#define SDMMC_ICR_DCRCFAILC_Pos (1U)
17820#define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
17821#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
17822#define SDMMC_ICR_CTIMEOUTC_Pos (2U)
17823#define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
17824#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
17825#define SDMMC_ICR_DTIMEOUTC_Pos (3U)
17826#define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
17827#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
17828#define SDMMC_ICR_TXUNDERRC_Pos (4U)
17829#define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
17830#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
17831#define SDMMC_ICR_RXOVERRC_Pos (5U)
17832#define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
17833#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
17834#define SDMMC_ICR_CMDRENDC_Pos (6U)
17835#define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
17836#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
17837#define SDMMC_ICR_CMDSENTC_Pos (7U)
17838#define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
17839#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
17840#define SDMMC_ICR_DATAENDC_Pos (8U)
17841#define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */
17842#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
17843#define SDMMC_ICR_DHOLDC_Pos (9U)
17844#define SDMMC_ICR_DHOLDC_Msk (0x1UL << SDMMC_ICR_DHOLDC_Pos) /*!< 0x00000200 */
17845#define SDMMC_ICR_DHOLDC SDMMC_ICR_DHOLDC_Msk /*!<DHOLD flag clear bit */
17846#define SDMMC_ICR_DBCKENDC_Pos (10U)
17847#define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
17848#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
17849#define SDMMC_ICR_DABORTC_Pos (11U)
17850#define SDMMC_ICR_DABORTC_Msk (0x1UL << SDMMC_ICR_DABORTC_Pos) /*!< 0x00000800 */
17851#define SDMMC_ICR_DABORTC SDMMC_ICR_DABORTC_Msk /*!<DABORTC flag clear bit */
17852#define SDMMC_ICR_BUSYD0ENDC_Pos (21U)
17853#define SDMMC_ICR_BUSYD0ENDC_Msk (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos) /*!< 0x00200000 */
17854#define SDMMC_ICR_BUSYD0ENDC SDMMC_ICR_BUSYD0ENDC_Msk /*!<BUSYD0ENDC flag clear bit */
17855#define SDMMC_ICR_SDIOITC_Pos (22U)
17856#define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */
17857#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
17858#define SDMMC_ICR_ACKFAILC_Pos (23U)
17859#define SDMMC_ICR_ACKFAILC_Msk (0x1UL << SDMMC_ICR_ACKFAILC_Pos) /*!< 0x00800000 */
17860#define SDMMC_ICR_ACKFAILC SDMMC_ICR_ACKFAILC_Msk /*!<ACKFAILC flag clear bit */
17861#define SDMMC_ICR_ACKTIMEOUTC_Pos (24U)
17862#define SDMMC_ICR_ACKTIMEOUTC_Msk (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos) /*!< 0x01000000 */
17863#define SDMMC_ICR_ACKTIMEOUTC SDMMC_ICR_ACKTIMEOUTC_Msk /*!<ACKTIMEOUTC flag clear bit */
17864#define SDMMC_ICR_VSWENDC_Pos (25U)
17865#define SDMMC_ICR_VSWENDC_Msk (0x1UL << SDMMC_ICR_VSWENDC_Pos) /*!< 0x02000000 */
17866#define SDMMC_ICR_VSWENDC SDMMC_ICR_VSWENDC_Msk /*!<VSWENDC flag clear bit */
17867#define SDMMC_ICR_CKSTOPC_Pos (26U)
17868#define SDMMC_ICR_CKSTOPC_Msk (0x1UL << SDMMC_ICR_CKSTOPC_Pos) /*!< 0x04000000 */
17869#define SDMMC_ICR_CKSTOPC SDMMC_ICR_CKSTOPC_Msk /*!<CKSTOPC flag clear bit */
17870#define SDMMC_ICR_IDMATEC_Pos (27U)
17871#define SDMMC_ICR_IDMATEC_Msk (0x1UL << SDMMC_ICR_IDMATEC_Pos) /*!< 0x08000000 */
17872#define SDMMC_ICR_IDMATEC SDMMC_ICR_IDMATEC_Msk /*!<IDMATEC flag clear bit */
17873#define SDMMC_ICR_IDMABTCC_Pos (28U)
17874#define SDMMC_ICR_IDMABTCC_Msk (0x1UL << SDMMC_ICR_IDMABTCC_Pos) /*!< 0x10000000 */
17875#define SDMMC_ICR_IDMABTCC SDMMC_ICR_IDMABTCC_Msk /*!<IDMABTCC flag clear bit */
17876
17877/****************** Bit definition for SDMMC_MASK register *******************/
17878#define SDMMC_MASK_CCRCFAILIE_Pos (0U)
17879#define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
17880#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
17881#define SDMMC_MASK_DCRCFAILIE_Pos (1U)
17882#define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
17883#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
17884#define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
17885#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
17886#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
17887#define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
17888#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
17889#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
17890#define SDMMC_MASK_TXUNDERRIE_Pos (4U)
17891#define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
17892#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
17893#define SDMMC_MASK_RXOVERRIE_Pos (5U)
17894#define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
17895#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
17896#define SDMMC_MASK_CMDRENDIE_Pos (6U)
17897#define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
17898#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
17899#define SDMMC_MASK_CMDSENTIE_Pos (7U)
17900#define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
17901#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
17902#define SDMMC_MASK_DATAENDIE_Pos (8U)
17903#define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
17904#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
17905#define SDMMC_MASK_DHOLDIE_Pos (9U)
17906#define SDMMC_MASK_DHOLDIE_Msk (0x1UL << SDMMC_MASK_DHOLDIE_Pos) /*!< 0x00000200 */
17907#define SDMMC_MASK_DHOLDIE SDMMC_MASK_DHOLDIE_Msk /*!<Data Hold Interrupt Enable */
17908#define SDMMC_MASK_DBCKENDIE_Pos (10U)
17909#define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
17910#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
17911#define SDMMC_MASK_DABORTIE_Pos (11U)
17912#define SDMMC_MASK_DABORTIE_Msk (0x1UL << SDMMC_MASK_DABORTIE_Pos) /*!< 0x00000800 */
17913#define SDMMC_MASK_DABORTIE SDMMC_MASK_DABORTIE_Msk /*!<Data transfer aborted interrupt enable */
17914
17915#define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
17916#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
17917#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
17918#define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
17919#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
17920#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
17921
17922#define SDMMC_MASK_RXFIFOFIE_Pos (17U)
17923#define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
17924#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
17925#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
17926#define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
17927#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
17928
17929#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
17930#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
17931#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0ENDIE interrupt Enable */
17932#define SDMMC_MASK_SDIOITIE_Pos (22U)
17933#define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
17934#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDMMC Mode Interrupt Received interrupt Enable */
17935#define SDMMC_MASK_ACKFAILIE_Pos (23U)
17936#define SDMMC_MASK_ACKFAILIE_Msk (0x1UL << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
17937#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
17938#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
17939#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
17940#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
17941#define SDMMC_MASK_VSWENDIE_Pos (25U)
17942#define SDMMC_MASK_VSWENDIE_Msk (0x1UL << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
17943#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
17944#define SDMMC_MASK_CKSTOPIE_Pos (26U)
17945#define SDMMC_MASK_CKSTOPIE_Msk (0x1UL << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x04000000 */
17946#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
17947#define SDMMC_MASK_IDMABTCIE_Pos (28U)
17948#define SDMMC_MASK_IDMABTCIE_Msk (0x1UL << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
17949#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
17950
17951/***************** Bit definition for SDMMC_ACKTIME register *****************/
17952#define SDMMC_ACKTIME_ACKTIME_Pos (0U)
17953#define SDMMC_ACKTIME_ACKTIME_Msk (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */
17954#define SDMMC_ACKTIME_ACKTIME SDMMC_ACKTIME_ACKTIME_Msk /*!<Boot acknowledgment timeout period */
17955
17956/****************** Bit definition for SDMMC_FIFO register *******************/
17957#define SDMMC_FIFO_FIFODATA_Pos (0U)
17958#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
17959#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
17960
17961/****************** Bit definition for SDMMC_IDMACTRL register ****************/
17962#define SDMMC_IDMA_IDMAEN_Pos (0U)
17963#define SDMMC_IDMA_IDMAEN_Msk (0x1UL << SDMMC_IDMA_IDMAEN_Pos) /*!< 0x00000001 */
17964#define SDMMC_IDMA_IDMAEN SDMMC_IDMA_IDMAEN_Msk /*!< Enable the internal DMA of the SDMMC peripheral */
17965#define SDMMC_IDMA_IDMABMODE_Pos (1U)
17966#define SDMMC_IDMA_IDMABMODE_Msk (0x1UL << SDMMC_IDMA_IDMABMODE_Pos) /*!< 0x00000002 */
17967#define SDMMC_IDMA_IDMABMODE SDMMC_IDMA_IDMABMODE_Msk /*!< Enable double buffer mode for IDMA */
17968#define SDMMC_IDMA_IDMABACT_Pos (2U)
17969#define SDMMC_IDMA_IDMABACT_Msk (0x1UL << SDMMC_IDMA_IDMABACT_Pos) /*!< 0x00000004 */
17970#define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk /*!< Uses buffer 1 when double buffer mode is selected */
17971
17972/***************** Bit definition for SDMMC_IDMABSIZE register ***************/
17973#define SDMMC_IDMABSIZE_IDMABNDT_Pos (5U)
17974#define SDMMC_IDMABSIZE_IDMABNDT_Msk (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */
17975#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
17976
17977/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
17978#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
17979
17980/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
17981#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
17982
17983/******************************************************************************/
17984/* */
17985/* Delay Block Interface (DLYB) */
17986/* */
17987/******************************************************************************/
17988/******************* Bit definition for DLYB_CR register ********************/
17989#define DLYB_CR_DEN_Pos (0U)
17990#define DLYB_CR_DEN_Msk (0x1UL << DLYB_CR_DEN_Pos) /*!< 0x00000001 */
17991#define DLYB_CR_DEN DLYB_CR_DEN_Msk /*!<Delay Block enable */
17992#define DLYB_CR_SEN_Pos (1U)
17993#define DLYB_CR_SEN_Msk (0x1UL << DLYB_CR_SEN_Pos) /*!< 0x00000002 */
17994#define DLYB_CR_SEN DLYB_CR_SEN_Msk /*!<Sampler length enable */
17995
17996
17997/******************* Bit definition for DLYB_CFGR register ********************/
17998#define DLYB_CFGR_SEL_Pos (0U)
17999#define DLYB_CFGR_SEL_Msk (0xFUL << DLYB_CFGR_SEL_Pos) /*!< 0x0000000F */
18000#define DLYB_CFGR_SEL DLYB_CFGR_SEL_Msk /*!<Select the phase for the Output clock[3:0] */
18001#define DLYB_CFGR_SEL_0 (0x1UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000001 */
18002#define DLYB_CFGR_SEL_1 (0x2UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000002 */
18003#define DLYB_CFGR_SEL_2 (0x3UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000003 */
18004#define DLYB_CFGR_SEL_3 (0x8UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000008 */
18005
18006#define DLYB_CFGR_UNIT_Pos (8U)
18007#define DLYB_CFGR_UNIT_Msk (0x7FUL << DLYB_CFGR_UNIT_Pos) /*!< 0x00007F00 */
18008#define DLYB_CFGR_UNIT DLYB_CFGR_UNIT_Msk /*!<Delay Defines the delay of a Unit delay cell[6:0] */
18009#define DLYB_CFGR_UNIT_0 (0x01UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000100 */
18010#define DLYB_CFGR_UNIT_1 (0x02UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000200 */
18011#define DLYB_CFGR_UNIT_2 (0x04UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000400 */
18012#define DLYB_CFGR_UNIT_3 (0x08UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000800 */
18013#define DLYB_CFGR_UNIT_4 (0x10UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00001000 */
18014#define DLYB_CFGR_UNIT_5 (0x20UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00002000 */
18015#define DLYB_CFGR_UNIT_6 (0x40UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00004000 */
18016
18017#define DLYB_CFGR_LNG_Pos (16U)
18018#define DLYB_CFGR_LNG_Msk (0xFFFUL << DLYB_CFGR_LNG_Pos) /*!< 0x0FFF0000 */
18019#define DLYB_CFGR_LNG DLYB_CFGR_LNG_Msk /*!<Delay line length value[11:0] */
18020#define DLYB_CFGR_LNG_0 (0x001UL << DLYB_CFGR_LNG_Pos) /*!< 0x00010000 */
18021#define DLYB_CFGR_LNG_1 (0x002UL << DLYB_CFGR_LNG_Pos) /*!< 0x00020000 */
18022#define DLYB_CFGR_LNG_2 (0x004UL << DLYB_CFGR_LNG_Pos) /*!< 0x00040000 */
18023#define DLYB_CFGR_LNG_3 (0x008UL << DLYB_CFGR_LNG_Pos) /*!< 0x00080000 */
18024#define DLYB_CFGR_LNG_4 (0x010UL << DLYB_CFGR_LNG_Pos) /*!< 0x00100000 */
18025#define DLYB_CFGR_LNG_5 (0x020UL << DLYB_CFGR_LNG_Pos) /*!< 0x00200000 */
18026#define DLYB_CFGR_LNG_6 (0x040UL << DLYB_CFGR_LNG_Pos) /*!< 0x00400000 */
18027#define DLYB_CFGR_LNG_7 (0x080UL << DLYB_CFGR_LNG_Pos) /*!< 0x00800000 */
18028#define DLYB_CFGR_LNG_8 (0x100UL << DLYB_CFGR_LNG_Pos) /*!< 0x01000000 */
18029#define DLYB_CFGR_LNG_9 (0x200UL << DLYB_CFGR_LNG_Pos) /*!< 0x02000000 */
18030#define DLYB_CFGR_LNG_10 (0x400UL << DLYB_CFGR_LNG_Pos) /*!< 0x04000000 */
18031#define DLYB_CFGR_LNG_11 (0x800UL << DLYB_CFGR_LNG_Pos) /*!< 0x08000000 */
18032
18033#define DLYB_CFGR_LNGF_Pos (31U)
18034#define DLYB_CFGR_LNGF_Msk (0x1UL << DLYB_CFGR_LNGF_Pos) /*!< 0x80000000 */
18035#define DLYB_CFGR_LNGF DLYB_CFGR_LNGF_Msk /*!<Length valid flag */
18036
18037/******************************************************************************/
18038/* */
18039/* Serial Peripheral Interface (SPI/I2S) */
18040/* */
18041/******************************************************************************/
18042/******************* Bit definition for SPI_CR1 register ********************/
18043#define SPI_CR1_SPE_Pos (0U)
18044#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */
18045#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<Serial Peripheral Enable */
18046#define SPI_CR1_MASRX_Pos (8U)
18047#define SPI_CR1_MASRX_Msk (0x1UL << SPI_CR1_MASRX_Pos) /*!< 0x00000100 */
18048#define SPI_CR1_MASRX SPI_CR1_MASRX_Msk /*!<Master automatic SUSP in Receive mode */
18049#define SPI_CR1_CSTART_Pos (9U)
18050#define SPI_CR1_CSTART_Msk (0x1UL << SPI_CR1_CSTART_Pos) /*!< 0x00000200 */
18051#define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master transfer start */
18052#define SPI_CR1_CSUSP_Pos (10U)
18053#define SPI_CR1_CSUSP_Msk (0x1UL << SPI_CR1_CSUSP_Pos) /*!< 0x00000400 */
18054#define SPI_CR1_CSUSP SPI_CR1_CSUSP_Msk /*!<Master SUSPend request */
18055#define SPI_CR1_HDDIR_Pos (11U)
18056#define SPI_CR1_HDDIR_Msk (0x1UL << SPI_CR1_HDDIR_Pos) /*!< 0x00000800 */
18057#define SPI_CR1_HDDIR SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode */
18058#define SPI_CR1_SSI_Pos (12U)
18059#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00001000 */
18060#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal SS signal input level */
18061#define SPI_CR1_CRC33_17_Pos (13U)
18062#define SPI_CR1_CRC33_17_Msk (0x1UL << SPI_CR1_CRC33_17_Pos) /*!< 0x00002000 */
18063#define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk /*!<32-bit CRC polynomial configuration */
18064#define SPI_CR1_RCRCINI_Pos (14U)
18065#define SPI_CR1_RCRCINI_Msk (0x1UL << SPI_CR1_RCRCINI_Pos) /*!< 0x00004000 */
18066#define SPI_CR1_RCRCINI SPI_CR1_RCRCINI_Msk /*!<CRC init pattern control for receiver */
18067#define SPI_CR1_TCRCINI_Pos (15U)
18068#define SPI_CR1_TCRCINI_Msk (0x1UL << SPI_CR1_TCRCINI_Pos) /*!< 0x00008000 */
18069#define SPI_CR1_TCRCINI SPI_CR1_TCRCINI_Msk /*!<CRC init pattern control for transmitter */
18070#define SPI_CR1_IOLOCK_Pos (16U)
18071#define SPI_CR1_IOLOCK_Msk (0x1UL << SPI_CR1_IOLOCK_Pos) /*!< 0x00010000 */
18072#define SPI_CR1_IOLOCK SPI_CR1_IOLOCK_Msk /*!<Locking the AF configuration of associated IOs */
18073
18074/******************* Bit definition for SPI_CR2 register ********************/
18075#define SPI_CR2_TSER_Pos (16U)
18076#define SPI_CR2_TSER_Msk (0xFFFFUL << SPI_CR2_TSER_Pos) /*!< 0xFFFF0000 */
18077#define SPI_CR2_TSER SPI_CR2_TSER_Msk /*!<Number of data transfer extension */
18078#define SPI_CR2_TSIZE_Pos (0U)
18079#define SPI_CR2_TSIZE_Msk (0xFFFFUL << SPI_CR2_TSIZE_Pos) /*!< 0x0000FFFF */
18080#define SPI_CR2_TSIZE SPI_CR2_TSIZE_Msk /*!<Number of data at current transfer */
18081
18082/******************* Bit definition for SPI_CFG1 register ********************/
18083#define SPI_CFG1_DSIZE_Pos (0U)
18084#define SPI_CFG1_DSIZE_Msk (0x1FUL << SPI_CFG1_DSIZE_Pos) /*!< 0x0000001F */
18085#define SPI_CFG1_DSIZE SPI_CFG1_DSIZE_Msk /*!<DSIZE[4:0]: Bits number in single SPI data frame */
18086#define SPI_CFG1_DSIZE_0 (0x01UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000001 */
18087#define SPI_CFG1_DSIZE_1 (0x02UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000002 */
18088#define SPI_CFG1_DSIZE_2 (0x04UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000004 */
18089#define SPI_CFG1_DSIZE_3 (0x08UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000008 */
18090#define SPI_CFG1_DSIZE_4 (0x10UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000010 */
18091
18092#define SPI_CFG1_FTHLV_Pos (5U)
18093#define SPI_CFG1_FTHLV_Msk (0xFUL << SPI_CFG1_FTHLV_Pos) /*!< 0x000001E0 */
18094#define SPI_CFG1_FTHLV SPI_CFG1_FTHLV_Msk /*!<FTHVL [3:0]: FIFO threshold level*/
18095#define SPI_CFG1_FTHLV_0 (0x1UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000020 */
18096#define SPI_CFG1_FTHLV_1 (0x2UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000040 */
18097#define SPI_CFG1_FTHLV_2 (0x4UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000080 */
18098#define SPI_CFG1_FTHLV_3 (0x8UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000100 */
18099
18100#define SPI_CFG1_UDRCFG_Pos (9U)
18101#define SPI_CFG1_UDRCFG_Msk (0x3UL << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000600 */
18102#define SPI_CFG1_UDRCFG SPI_CFG1_UDRCFG_Msk /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */
18103#define SPI_CFG1_UDRCFG_0 (0x1UL << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000200 */
18104#define SPI_CFG1_UDRCFG_1 (0x2UL << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000400 */
18105
18106
18107#define SPI_CFG1_UDRDET_Pos (11U)
18108#define SPI_CFG1_UDRDET_Msk (0x3UL << SPI_CFG1_UDRDET_Pos) /*!< 0x00001800 */
18109#define SPI_CFG1_UDRDET SPI_CFG1_UDRDET_Msk /*!<UDRDET[1:0]: Detection of underrun condition */
18110#define SPI_CFG1_UDRDET_0 (0x1UL << SPI_CFG1_UDRDET_Pos) /*!< 0x00000800 */
18111#define SPI_CFG1_UDRDET_1 (0x2UL << SPI_CFG1_UDRDET_Pos) /*!< 0x00001000 */
18112
18113#define SPI_CFG1_RXDMAEN_Pos (14U)
18114#define SPI_CFG1_RXDMAEN_Msk (0x1UL << SPI_CFG1_RXDMAEN_Pos) /*!< 0x00004000 */
18115#define SPI_CFG1_RXDMAEN SPI_CFG1_RXDMAEN_Msk /*!<Rx DMA stream enable */
18116#define SPI_CFG1_TXDMAEN_Pos (15U)
18117#define SPI_CFG1_TXDMAEN_Msk (0x1UL << SPI_CFG1_TXDMAEN_Pos) /*!< 0x00008000 */
18118#define SPI_CFG1_TXDMAEN SPI_CFG1_TXDMAEN_Msk /*!<Tx DMA stream enable */
18119
18120#define SPI_CFG1_CRCSIZE_Pos (16U)
18121#define SPI_CFG1_CRCSIZE_Msk (0x1FUL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x001F0000 */
18122#define SPI_CFG1_CRCSIZE SPI_CFG1_CRCSIZE_Msk /*!<CRCSIZE [4:0]: Length of CRC frame*/
18123#define SPI_CFG1_CRCSIZE_0 (0x01UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00010000 */
18124#define SPI_CFG1_CRCSIZE_1 (0x02UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00020000 */
18125#define SPI_CFG1_CRCSIZE_2 (0x04UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00040000 */
18126#define SPI_CFG1_CRCSIZE_3 (0x08UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00080000 */
18127#define SPI_CFG1_CRCSIZE_4 (0x10UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00100000 */
18128
18129#define SPI_CFG1_CRCEN_Pos (22U)
18130#define SPI_CFG1_CRCEN_Msk (0x1UL << SPI_CFG1_CRCEN_Pos) /*!< 0x00400000 */
18131#define SPI_CFG1_CRCEN SPI_CFG1_CRCEN_Msk /*!<Hardware CRC computation enable */
18132
18133#define SPI_CFG1_MBR_Pos (28U)
18134#define SPI_CFG1_MBR_Msk (0x7UL << SPI_CFG1_MBR_Pos) /*!< 0x70000000 */
18135#define SPI_CFG1_MBR SPI_CFG1_MBR_Msk /*!<Master baud rate */
18136#define SPI_CFG1_MBR_0 (0x1UL << SPI_CFG1_MBR_Pos) /*!< 0x10000000 */
18137#define SPI_CFG1_MBR_1 (0x2UL << SPI_CFG1_MBR_Pos) /*!< 0x20000000 */
18138#define SPI_CFG1_MBR_2 (0x4UL << SPI_CFG1_MBR_Pos) /*!< 0x40000000 */
18139
18140/******************* Bit definition for SPI_CFG2 register ********************/
18141#define SPI_CFG2_MSSI_Pos (0U)
18142#define SPI_CFG2_MSSI_Msk (0xFUL << SPI_CFG2_MSSI_Pos) /*!< 0x0000000F */
18143#define SPI_CFG2_MSSI SPI_CFG2_MSSI_Msk /*!<Master SS Idleness */
18144#define SPI_CFG2_MSSI_0 (0x1UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000001 */
18145#define SPI_CFG2_MSSI_1 (0x2UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000002 */
18146#define SPI_CFG2_MSSI_2 (0x4UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000004 */
18147#define SPI_CFG2_MSSI_3 (0x8UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000008 */
18148
18149#define SPI_CFG2_MIDI_Pos (4U)
18150#define SPI_CFG2_MIDI_Msk (0xFUL << SPI_CFG2_MIDI_Pos) /*!< 0x000000F0 */
18151#define SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Data Idleness */
18152#define SPI_CFG2_MIDI_0 (0x1UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000010 */
18153#define SPI_CFG2_MIDI_1 (0x2UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000020 */
18154#define SPI_CFG2_MIDI_2 (0x4UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000040 */
18155#define SPI_CFG2_MIDI_3 (0x8UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000080 */
18156
18157#define SPI_CFG2_IOSWP_Pos (15U)
18158#define SPI_CFG2_IOSWP_Msk (0x1UL << SPI_CFG2_IOSWP_Pos) /*!< 0x00008000 */
18159#define SPI_CFG2_IOSWP SPI_CFG2_IOSWP_Msk /*!<Swap functionality of MISO and MOSI pins */
18160
18161#define SPI_CFG2_COMM_Pos (17U)
18162#define SPI_CFG2_COMM_Msk (0x3UL << SPI_CFG2_COMM_Pos) /*!< 0x00060000 */
18163#define SPI_CFG2_COMM SPI_CFG2_COMM_Msk /*!<COMM [1:0]: SPI Communication Mode*/
18164#define SPI_CFG2_COMM_0 (0x1UL << SPI_CFG2_COMM_Pos) /*!< 0x00020000 */
18165#define SPI_CFG2_COMM_1 (0x2UL << SPI_CFG2_COMM_Pos) /*!< 0x00040000 */
18166
18167#define SPI_CFG2_SP_Pos (19U)
18168#define SPI_CFG2_SP_Msk (0x7UL << SPI_CFG2_SP_Pos) /*!< 0x00380000 */
18169#define SPI_CFG2_SP SPI_CFG2_SP_Msk /*!<SP[2:0]: Serial Protocol */
18170#define SPI_CFG2_SP_0 (0x1UL << SPI_CFG2_SP_Pos) /*!< 0x00080000 */
18171#define SPI_CFG2_SP_1 (0x2UL << SPI_CFG2_SP_Pos) /*!< 0x00100000 */
18172#define SPI_CFG2_SP_2 (0x4UL << SPI_CFG2_SP_Pos) /*!< 0x00200000 */
18173
18174#define SPI_CFG2_MASTER_Pos (22U)
18175#define SPI_CFG2_MASTER_Msk (0x1UL << SPI_CFG2_MASTER_Pos) /*!< 0x00400000 */
18176#define SPI_CFG2_MASTER SPI_CFG2_MASTER_Msk /*!<SPI Master */
18177#define SPI_CFG2_LSBFRST_Pos (23U)
18178#define SPI_CFG2_LSBFRST_Msk (0x1UL << SPI_CFG2_LSBFRST_Pos) /*!< 0x00800000 */
18179#define SPI_CFG2_LSBFRST SPI_CFG2_LSBFRST_Msk /*!<Data frame format */
18180#define SPI_CFG2_CPHA_Pos (24U)
18181#define SPI_CFG2_CPHA_Msk (0x1UL << SPI_CFG2_CPHA_Pos) /*!< 0x01000000 */
18182#define SPI_CFG2_CPHA SPI_CFG2_CPHA_Msk /*!<Clock Phase */
18183#define SPI_CFG2_CPOL_Pos (25U)
18184#define SPI_CFG2_CPOL_Msk (0x1UL << SPI_CFG2_CPOL_Pos) /*!< 0x02000000 */
18185#define SPI_CFG2_CPOL SPI_CFG2_CPOL_Msk /*!<Clock Polarity */
18186#define SPI_CFG2_SSM_Pos (26U)
18187#define SPI_CFG2_SSM_Msk (0x1UL << SPI_CFG2_SSM_Pos) /*!< 0x04000000 */
18188#define SPI_CFG2_SSM SPI_CFG2_SSM_Msk /*!<Software slave management */
18189
18190#define SPI_CFG2_SSIOP_Pos (28U)
18191#define SPI_CFG2_SSIOP_Msk (0x1UL << SPI_CFG2_SSIOP_Pos) /*!< 0x10000000 */
18192#define SPI_CFG2_SSIOP SPI_CFG2_SSIOP_Msk /*!<SS input/output polarity */
18193#define SPI_CFG2_SSOE_Pos (29U)
18194#define SPI_CFG2_SSOE_Msk (0x1UL << SPI_CFG2_SSOE_Pos) /*!< 0x20000000 */
18195#define SPI_CFG2_SSOE SPI_CFG2_SSOE_Msk /*!<SS output enable */
18196#define SPI_CFG2_SSOM_Pos (30U)
18197#define SPI_CFG2_SSOM_Msk (0x1UL << SPI_CFG2_SSOM_Pos) /*!< 0x40000000 */
18198#define SPI_CFG2_SSOM SPI_CFG2_SSOM_Msk /*!<SS output management in master mode */
18199
18200#define SPI_CFG2_AFCNTR_Pos (31U)
18201#define SPI_CFG2_AFCNTR_Msk (0x1UL << SPI_CFG2_AFCNTR_Pos) /*!< 0x80000000 */
18202#define SPI_CFG2_AFCNTR SPI_CFG2_AFCNTR_Msk /*!<Alternate function GPIOs control */
18203
18204/******************* Bit definition for SPI_IER register ********************/
18205#define SPI_IER_RXPIE_Pos (0U)
18206#define SPI_IER_RXPIE_Msk (0x1UL << SPI_IER_RXPIE_Pos) /*!< 0x00000001 */
18207#define SPI_IER_RXPIE SPI_IER_RXPIE_Msk /*!<RXP Interrupt Enable */
18208#define SPI_IER_TXPIE_Pos (1U)
18209#define SPI_IER_TXPIE_Msk (0x1UL << SPI_IER_TXPIE_Pos) /*!< 0x00000002 */
18210#define SPI_IER_TXPIE SPI_IER_TXPIE_Msk /*!<TXP interrupt enable */
18211#define SPI_IER_DXPIE_Pos (2U)
18212#define SPI_IER_DXPIE_Msk (0x1UL << SPI_IER_DXPIE_Pos) /*!< 0x00000004 */
18213#define SPI_IER_DXPIE SPI_IER_DXPIE_Msk /*!<DXP interrupt enable */
18214#define SPI_IER_EOTIE_Pos (3U)
18215#define SPI_IER_EOTIE_Msk (0x1UL << SPI_IER_EOTIE_Pos) /*!< 0x00000008 */
18216#define SPI_IER_EOTIE SPI_IER_EOTIE_Msk /*!<EOT/SUSP/TXC interrupt enable */
18217#define SPI_IER_TXTFIE_Pos (4U)
18218#define SPI_IER_TXTFIE_Msk (0x1UL << SPI_IER_TXTFIE_Pos) /*!< 0x00000010 */
18219#define SPI_IER_TXTFIE SPI_IER_TXTFIE_Msk /*!<TXTF interrupt enable */
18220#define SPI_IER_UDRIE_Pos (5U)
18221#define SPI_IER_UDRIE_Msk (0x1UL << SPI_IER_UDRIE_Pos) /*!< 0x00000020 */
18222#define SPI_IER_UDRIE SPI_IER_UDRIE_Msk /*!<UDR interrupt enable */
18223#define SPI_IER_OVRIE_Pos (6U)
18224#define SPI_IER_OVRIE_Msk (0x1UL << SPI_IER_OVRIE_Pos) /*!< 0x00000040 */
18225#define SPI_IER_OVRIE SPI_IER_OVRIE_Msk /*!<OVR interrupt enable */
18226#define SPI_IER_CRCEIE_Pos (7U)
18227#define SPI_IER_CRCEIE_Msk (0x1UL << SPI_IER_CRCEIE_Pos) /*!< 0x00000080 */
18228#define SPI_IER_CRCEIE SPI_IER_CRCEIE_Msk /*!<CRCE interrupt enable */
18229#define SPI_IER_TIFREIE_Pos (8U)
18230#define SPI_IER_TIFREIE_Msk (0x1UL << SPI_IER_TIFREIE_Pos) /*!< 0x00000100 */
18231#define SPI_IER_TIFREIE SPI_IER_TIFREIE_Msk /*!<TI Frame Error interrupt enable */
18232#define SPI_IER_MODFIE_Pos (9U)
18233#define SPI_IER_MODFIE_Msk (0x1UL << SPI_IER_MODFIE_Pos) /*!< 0x00000200 */
18234#define SPI_IER_MODFIE SPI_IER_MODFIE_Msk /*!<MODF interrupt enable */
18235#define SPI_IER_TSERFIE_Pos (10U)
18236#define SPI_IER_TSERFIE_Msk (0x1UL << SPI_IER_TSERFIE_Pos) /*!< 0x00000400 */
18237#define SPI_IER_TSERFIE SPI_IER_TSERFIE_Msk /*!<TSERF interrupt enable */
18238
18239/******************* Bit definition for SPI_SR register ********************/
18240#define SPI_SR_RXP_Pos (0U)
18241#define SPI_SR_RXP_Msk (0x1UL << SPI_SR_RXP_Pos) /*!< 0x00000001 */
18242#define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet available */
18243#define SPI_SR_TXP_Pos (1U)
18244#define SPI_SR_TXP_Msk (0x1UL << SPI_SR_TXP_Pos) /*!< 0x00000002 */
18245#define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet space available */
18246#define SPI_SR_DXP_Pos (2U)
18247#define SPI_SR_DXP_Msk (0x1UL << SPI_SR_DXP_Pos) /*!< 0x00000004 */
18248#define SPI_SR_DXP SPI_SR_DXP_Msk /*!<Duplex Packet available */
18249#define SPI_SR_EOT_Pos (3U)
18250#define SPI_SR_EOT_Msk (0x1UL << SPI_SR_EOT_Pos) /*!< 0x00000008 */
18251#define SPI_SR_EOT SPI_SR_EOT_Msk /*!<Duplex Packet available */
18252#define SPI_SR_TXTF_Pos (4U)
18253#define SPI_SR_TXTF_Msk (0x1UL << SPI_SR_TXTF_Pos) /*!< 0x00000010 */
18254#define SPI_SR_TXTF SPI_SR_TXTF_Msk /*!<Transmission Transfer Filled */
18255#define SPI_SR_UDR_Pos (5U)
18256#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000020 */
18257#define SPI_SR_UDR SPI_SR_UDR_Msk /*!<UDR at Slave transmission */
18258#define SPI_SR_OVR_Pos (6U)
18259#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
18260#define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet available */
18261#define SPI_SR_CRCE_Pos (7U)
18262#define SPI_SR_CRCE_Msk (0x1UL << SPI_SR_CRCE_Pos) /*!< 0x00000080 */
18263#define SPI_SR_CRCE SPI_SR_CRCE_Msk /*!<CRC Error Detected */
18264#define SPI_SR_TIFRE_Pos (8U)
18265#define SPI_SR_TIFRE_Msk (0x1UL << SPI_SR_TIFRE_Pos) /*!< 0x00000100 */
18266#define SPI_SR_TIFRE SPI_SR_TIFRE_Msk /*!<TI frame format error Detected */
18267#define SPI_SR_MODF_Pos (9U)
18268#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000200 */
18269#define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode Fault Detected */
18270#define SPI_SR_TSERF_Pos (10U)
18271#define SPI_SR_TSERF_Msk (0x1UL << SPI_SR_TSERF_Pos) /*!< 0x00000400 */
18272#define SPI_SR_TSERF SPI_SR_TSERF_Msk /*!<Number of SPI data to be transacted reloaded */
18273#define SPI_SR_SUSP_Pos (11U)
18274#define SPI_SR_SUSP_Msk (0x1UL << SPI_SR_SUSP_Pos) /*!< 0x00000800 */
18275#define SPI_SR_SUSP SPI_SR_SUSP_Msk /*!<SUSP is set by hardware */
18276#define SPI_SR_TXC_Pos (12U)
18277#define SPI_SR_TXC_Msk (0x1UL << SPI_SR_TXC_Pos) /*!< 0x00001000 */
18278#define SPI_SR_TXC SPI_SR_TXC_Msk /*!<TxFIFO transmission complete */
18279#define SPI_SR_RXPLVL_Pos (13U)
18280#define SPI_SR_RXPLVL_Msk (0x3UL << SPI_SR_RXPLVL_Pos) /*!< 0x00006000 */
18281#define SPI_SR_RXPLVL SPI_SR_RXPLVL_Msk /*!<RxFIFO Packing Level */
18282#define SPI_SR_RXPLVL_0 (0x1UL << SPI_SR_RXPLVL_Pos) /*!< 0x00002000 */
18283#define SPI_SR_RXPLVL_1 (0x2UL << SPI_SR_RXPLVL_Pos) /*!< 0x00004000 */
18284#define SPI_SR_RXWNE_Pos (15U)
18285#define SPI_SR_RXWNE_Msk (0x1UL << SPI_SR_RXWNE_Pos) /*!< 0x00008000 */
18286#define SPI_SR_RXWNE SPI_SR_RXWNE_Msk /*!<Rx FIFO Word Not Empty */
18287#define SPI_SR_CTSIZE_Pos (16U)
18288#define SPI_SR_CTSIZE_Msk (0xFFFFUL << SPI_SR_CTSIZE_Pos) /*!< 0xFFFF0000 */
18289#define SPI_SR_CTSIZE SPI_SR_CTSIZE_Msk /*!<Number of data frames remaining in TSIZE */
18290
18291/******************* Bit definition for SPI_IFCR register ********************/
18292#define SPI_IFCR_EOTC_Pos (3U)
18293#define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008 */
18294#define SPI_IFCR_EOTC SPI_IFCR_EOTC_Msk /*!<End Of Transfer flag clear */
18295#define SPI_IFCR_TXTFC_Pos (4U)
18296#define SPI_IFCR_TXTFC_Msk (0x1UL << SPI_IFCR_TXTFC_Pos) /*!< 0x00000010 */
18297#define SPI_IFCR_TXTFC SPI_IFCR_TXTFC_Msk /*!<Transmission Transfer Filled flag clear */
18298#define SPI_IFCR_UDRC_Pos (5U)
18299#define SPI_IFCR_UDRC_Msk (0x1UL << SPI_IFCR_UDRC_Pos) /*!< 0x00000020 */
18300#define SPI_IFCR_UDRC SPI_IFCR_UDRC_Msk /*!<Underrun flag clear */
18301#define SPI_IFCR_OVRC_Pos (6U)
18302#define SPI_IFCR_OVRC_Msk (0x1UL << SPI_IFCR_OVRC_Pos) /*!< 0x00000040 */
18303#define SPI_IFCR_OVRC SPI_IFCR_OVRC_Msk /*!<Overrun flag clear */
18304#define SPI_IFCR_CRCEC_Pos (7U)
18305#define SPI_IFCR_CRCEC_Msk (0x1UL << SPI_IFCR_CRCEC_Pos) /*!< 0x00000080 */
18306#define SPI_IFCR_CRCEC SPI_IFCR_CRCEC_Msk /*!<CRC Error flag clear */
18307#define SPI_IFCR_TIFREC_Pos (8U)
18308#define SPI_IFCR_TIFREC_Msk (0x1UL << SPI_IFCR_TIFREC_Pos) /*!< 0x00000100 */
18309#define SPI_IFCR_TIFREC SPI_IFCR_TIFREC_Msk /*!<TI frame format error flag clear */
18310#define SPI_IFCR_MODFC_Pos (9U)
18311#define SPI_IFCR_MODFC_Msk (0x1UL << SPI_IFCR_MODFC_Pos) /*!< 0x00000200 */
18312#define SPI_IFCR_MODFC SPI_IFCR_MODFC_Msk /*!<Mode Fault flag clear */
18313#define SPI_IFCR_TSERFC_Pos (10U)
18314#define SPI_IFCR_TSERFC_Msk (0x1UL << SPI_IFCR_TSERFC_Pos) /*!< 0x00000400 */
18315#define SPI_IFCR_TSERFC SPI_IFCR_TSERFC_Msk /*!<TSERFC flag clear */
18316#define SPI_IFCR_SUSPC_Pos (11U)
18317#define SPI_IFCR_SUSPC_Msk (0x1UL << SPI_IFCR_SUSPC_Pos) /*!< 0x00000800 */
18318#define SPI_IFCR_SUSPC SPI_IFCR_SUSPC_Msk /*!<SUSPend flag clear */
18319
18320/******************* Bit definition for SPI_TXDR register ********************/
18321#define SPI_TXDR_TXDR_Pos (0U)
18322#define SPI_TXDR_TXDR_Msk (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos) /*!< 0xFFFFFFFF */
18323#define SPI_TXDR_TXDR SPI_TXDR_TXDR_Msk /* Transmit Data Register */
18324
18325/******************* Bit definition for SPI_RXDR register ********************/
18326#define SPI_RXDR_RXDR_Pos (0U)
18327#define SPI_RXDR_RXDR_Msk (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos) /*!< 0xFFFFFFFF */
18328#define SPI_RXDR_RXDR SPI_RXDR_RXDR_Msk /* Receive Data Register */
18329
18330/******************* Bit definition for SPI_CRCPOLY register ********************/
18331#define SPI_CRCPOLY_CRCPOLY_Pos (0U)
18332#define SPI_CRCPOLY_CRCPOLY_Msk (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
18333#define SPI_CRCPOLY_CRCPOLY SPI_CRCPOLY_CRCPOLY_Msk /* CRC Polynomial register */
18334
18335/******************* Bit definition for SPI_TXCRC register ********************/
18336#define SPI_TXCRC_TXCRC_Pos (0U)
18337#define SPI_TXCRC_TXCRC_Msk (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos) /*!< 0xFFFFFFFF */
18338#define SPI_TXCRC_TXCRC SPI_TXCRC_TXCRC_Msk /* CRCRegister for transmitter */
18339
18340/******************* Bit definition for SPI_RXCRC register ********************/
18341#define SPI_RXCRC_RXCRC_Pos (0U)
18342#define SPI_RXCRC_RXCRC_Msk (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos) /*!< 0xFFFFFFFF */
18343#define SPI_RXCRC_RXCRC SPI_RXCRC_RXCRC_Msk /* CRCRegister for receiver */
18344
18345/******************* Bit definition for SPI_UDRDR register ********************/
18346#define SPI_UDRDR_UDRDR_Pos (0U)
18347#define SPI_UDRDR_UDRDR_Msk (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos) /*!< 0xFFFFFFFF */
18348#define SPI_UDRDR_UDRDR SPI_UDRDR_UDRDR_Msk /* Data at slave underrun condition */
18349
18350/****************** Bit definition for SPI_I2SCFGR register *****************/
18351#define SPI_I2SCFGR_I2SMOD_Pos (0U)
18352#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000001 */
18353#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
18354#define SPI_I2SCFGR_I2SCFG_Pos (1U)
18355#define SPI_I2SCFGR_I2SCFG_Msk (0x7UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x0000000E */
18356#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[2:0] I2S configuration mode */
18357#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000002 */
18358#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000004 */
18359#define SPI_I2SCFGR_I2SCFG_2 (0x4UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000008 */
18360#define SPI_I2SCFGR_I2SSTD_Pos (4U)
18361#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
18362#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] I2S standard selection */
18363#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
18364#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
18365#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
18366#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
18367#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
18368#define SPI_I2SCFGR_DATLEN_Pos (8U)
18369#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000300 */
18370#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] Data length to be transferred */
18371#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000100 */
18372#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000200 */
18373#define SPI_I2SCFGR_CHLEN_Pos (10U)
18374#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000400 */
18375#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
18376#define SPI_I2SCFGR_CKPOL_Pos (11U)
18377#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000800 */
18378#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<Steady state clock polarity */
18379#define SPI_I2SCFGR_FIXCH_Pos (12U)
18380#define SPI_I2SCFGR_FIXCH_Msk (0x1UL << SPI_I2SCFGR_FIXCH_Pos) /*!< 0x00001000 */
18381#define SPI_I2SCFGR_FIXCH SPI_I2SCFGR_FIXCH_Msk /*!<Fixed channel length in SLAVE */
18382#define SPI_I2SCFGR_WSINV_Pos (13U)
18383#define SPI_I2SCFGR_WSINV_Msk (0x1UL << SPI_I2SCFGR_WSINV_Pos) /*!< 0x00002000 */
18384#define SPI_I2SCFGR_WSINV SPI_I2SCFGR_WSINV_Msk /*!<Word select inversion */
18385#define SPI_I2SCFGR_DATFMT_Pos (14U)
18386#define SPI_I2SCFGR_DATFMT_Msk (0x1UL << SPI_I2SCFGR_DATFMT_Pos) /*!< 0x00004000 */
18387#define SPI_I2SCFGR_DATFMT SPI_I2SCFGR_DATFMT_Msk /*!<Data format */
18388#define SPI_I2SCFGR_I2SDIV_Pos (16U)
18389#define SPI_I2SCFGR_I2SDIV_Msk (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos) /*!< 0x00FF0000 */
18390#define SPI_I2SCFGR_I2SDIV SPI_I2SCFGR_I2SDIV_Msk /*!<I2S Linear prescaler */
18391#define SPI_I2SCFGR_ODD_Pos (24U)
18392#define SPI_I2SCFGR_ODD_Msk (0x1UL << SPI_I2SCFGR_ODD_Pos) /*!< 0x01000000 */
18393#define SPI_I2SCFGR_ODD SPI_I2SCFGR_ODD_Msk /*!<Odd factor for the prescaler */
18394#define SPI_I2SCFGR_MCKOE_Pos (25U)
18395#define SPI_I2SCFGR_MCKOE_Msk (0x1UL << SPI_I2SCFGR_MCKOE_Pos) /*!< 0x02000000 */
18396#define SPI_I2SCFGR_MCKOE SPI_I2SCFGR_MCKOE_Msk /*!<Master Clock Output Enable */
18397
18398
18399/******************************************************************************/
18400/* */
18401/* QUADSPI */
18402/* */
18403/******************************************************************************/
18404/***************** Bit definition for QUADSPI_CR register *******************/
18405#define QUADSPI_CR_EN_Pos (0U)
18406#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
18407#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
18408#define QUADSPI_CR_ABORT_Pos (1U)
18409#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
18410#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
18411#define QUADSPI_CR_DMAEN_Pos (2U)
18412#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
18413#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
18414#define QUADSPI_CR_TCEN_Pos (3U)
18415#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
18416#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
18417#define QUADSPI_CR_SSHIFT_Pos (4U)
18418#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
18419#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< SSHIFT Sample Shift */
18420#define QUADSPI_CR_DFM_Pos (6U)
18421#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
18422#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
18423#define QUADSPI_CR_FSEL_Pos (7U)
18424#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
18425#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
18426#define QUADSPI_CR_FTHRES_Pos (8U)
18427#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
18428#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
18429#define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
18430#define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
18431#define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
18432#define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
18433#define QUADSPI_CR_TEIE_Pos (16U)
18434#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
18435#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
18436#define QUADSPI_CR_TCIE_Pos (17U)
18437#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
18438#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
18439#define QUADSPI_CR_FTIE_Pos (18U)
18440#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
18441#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
18442#define QUADSPI_CR_SMIE_Pos (19U)
18443#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
18444#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
18445#define QUADSPI_CR_TOIE_Pos (20U)
18446#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
18447#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
18448#define QUADSPI_CR_APMS_Pos (22U)
18449#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
18450#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
18451#define QUADSPI_CR_PMM_Pos (23U)
18452#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
18453#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
18454#define QUADSPI_CR_PRESCALER_Pos (24U)
18455#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
18456#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
18457#define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
18458#define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
18459#define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
18460#define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
18461#define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
18462#define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
18463#define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
18464#define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
18465
18466/***************** Bit definition for QUADSPI_DCR register ******************/
18467#define QUADSPI_DCR_CKMODE_Pos (0U)
18468#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
18469#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
18470#define QUADSPI_DCR_CSHT_Pos (8U)
18471#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
18472#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
18473#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
18474#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
18475#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
18476#define QUADSPI_DCR_FSIZE_Pos (16U)
18477#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
18478#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
18479#define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
18480#define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
18481#define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
18482#define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
18483#define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
18484
18485/****************** Bit definition for QUADSPI_SR register *******************/
18486#define QUADSPI_SR_TEF_Pos (0U)
18487#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
18488#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
18489#define QUADSPI_SR_TCF_Pos (1U)
18490#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
18491#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
18492#define QUADSPI_SR_FTF_Pos (2U)
18493#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
18494#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
18495#define QUADSPI_SR_SMF_Pos (3U)
18496#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
18497#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
18498#define QUADSPI_SR_TOF_Pos (4U)
18499#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
18500#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
18501#define QUADSPI_SR_BUSY_Pos (5U)
18502#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
18503#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
18504#define QUADSPI_SR_FLEVEL_Pos (8U)
18505#define QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
18506#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
18507#define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
18508#define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
18509#define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
18510#define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
18511#define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
18512#define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */
18513
18514/****************** Bit definition for QUADSPI_FCR register ******************/
18515#define QUADSPI_FCR_CTEF_Pos (0U)
18516#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
18517#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
18518#define QUADSPI_FCR_CTCF_Pos (1U)
18519#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
18520#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
18521#define QUADSPI_FCR_CSMF_Pos (3U)
18522#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
18523#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
18524#define QUADSPI_FCR_CTOF_Pos (4U)
18525#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
18526#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
18527
18528/****************** Bit definition for QUADSPI_DLR register ******************/
18529#define QUADSPI_DLR_DL_Pos (0U)
18530#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
18531#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
18532
18533/****************** Bit definition for QUADSPI_CCR register ******************/
18534#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
18535#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
18536#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
18537#define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
18538#define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
18539#define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
18540#define QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
18541#define QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
18542#define QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
18543#define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
18544#define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
18545#define QUADSPI_CCR_IMODE_Pos (8U)
18546#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
18547#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
18548#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
18549#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
18550#define QUADSPI_CCR_ADMODE_Pos (10U)
18551#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
18552#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
18553#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
18554#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
18555#define QUADSPI_CCR_ADSIZE_Pos (12U)
18556#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
18557#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
18558#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
18559#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
18560#define QUADSPI_CCR_ABMODE_Pos (14U)
18561#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
18562#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
18563#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
18564#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
18565#define QUADSPI_CCR_ABSIZE_Pos (16U)
18566#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
18567#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
18568#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
18569#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
18570#define QUADSPI_CCR_DCYC_Pos (18U)
18571#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
18572#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
18573#define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
18574#define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
18575#define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
18576#define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
18577#define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
18578#define QUADSPI_CCR_DMODE_Pos (24U)
18579#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
18580#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
18581#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
18582#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
18583#define QUADSPI_CCR_FMODE_Pos (26U)
18584#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
18585#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
18586#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
18587#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
18588#define QUADSPI_CCR_SIOO_Pos (28U)
18589#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
18590#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
18591#define QUADSPI_CCR_DHHC_Pos (30U)
18592#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
18593#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold half cycle */
18594#define QUADSPI_CCR_DDRM_Pos (31U)
18595#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
18596#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
18597
18598/****************** Bit definition for QUADSPI_AR register *******************/
18599#define QUADSPI_AR_ADDRESS_Pos (0U)
18600#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
18601#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
18602
18603/****************** Bit definition for QUADSPI_ABR register ******************/
18604#define QUADSPI_ABR_ALTERNATE_Pos (0U)
18605#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
18606#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
18607
18608/****************** Bit definition for QUADSPI_DR register *******************/
18609#define QUADSPI_DR_DATA_Pos (0U)
18610#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
18611#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
18612
18613/****************** Bit definition for QUADSPI_PSMKR register ****************/
18614#define QUADSPI_PSMKR_MASK_Pos (0U)
18615#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
18616#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
18617
18618/****************** Bit definition for QUADSPI_PSMAR register ****************/
18619#define QUADSPI_PSMAR_MATCH_Pos (0U)
18620#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
18621#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
18622
18623/****************** Bit definition for QUADSPI_PIR register *****************/
18624#define QUADSPI_PIR_INTERVAL_Pos (0U)
18625#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
18626#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
18627
18628/****************** Bit definition for QUADSPI_LPTR register *****************/
18629#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
18630#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
18631#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
18632
18633/******************************************************************************/
18634/* */
18635/* SYSCFG */
18636/* */
18637/******************************************************************************/
18638
18639/****************** Bit definition for SYSCFG_PMCR register ******************/
18640#define SYSCFG_PMCR_I2C1_FMP_Pos (0U)
18641#define SYSCFG_PMCR_I2C1_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos) /*!< 0x00000001 */
18642#define SYSCFG_PMCR_I2C1_FMP SYSCFG_PMCR_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
18643#define SYSCFG_PMCR_I2C2_FMP_Pos (1U)
18644#define SYSCFG_PMCR_I2C2_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos) /*!< 0x00000002 */
18645#define SYSCFG_PMCR_I2C2_FMP SYSCFG_PMCR_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
18646#define SYSCFG_PMCR_I2C3_FMP_Pos (2U)
18647#define SYSCFG_PMCR_I2C3_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos) /*!< 0x00000004 */
18648#define SYSCFG_PMCR_I2C3_FMP SYSCFG_PMCR_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
18649#define SYSCFG_PMCR_I2C4_FMP_Pos (3U)
18650#define SYSCFG_PMCR_I2C4_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos) /*!< 0x00000008 */
18651#define SYSCFG_PMCR_I2C4_FMP SYSCFG_PMCR_I2C4_FMP_Msk /*!< I2C4 Fast mode plus */
18652#define SYSCFG_PMCR_I2C_PB6_FMP_Pos (4U)
18653#define SYSCFG_PMCR_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
18654#define SYSCFG_PMCR_I2C_PB6_FMP SYSCFG_PMCR_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
18655#define SYSCFG_PMCR_I2C_PB7_FMP_Pos (5U)
18656#define SYSCFG_PMCR_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
18657#define SYSCFG_PMCR_I2C_PB7_FMP SYSCFG_PMCR_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
18658#define SYSCFG_PMCR_I2C_PB8_FMP_Pos (6U)
18659#define SYSCFG_PMCR_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
18660#define SYSCFG_PMCR_I2C_PB8_FMP SYSCFG_PMCR_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
18661#define SYSCFG_PMCR_I2C_PB9_FMP_Pos (7U)
18662#define SYSCFG_PMCR_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
18663#define SYSCFG_PMCR_I2C_PB9_FMP SYSCFG_PMCR_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
18664#define SYSCFG_PMCR_BOOSTEN_Pos (8U)
18665#define SYSCFG_PMCR_BOOSTEN_Msk (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos) /*!< 0x00000100 */
18666#define SYSCFG_PMCR_BOOSTEN SYSCFG_PMCR_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
18667
18668#define SYSCFG_PMCR_BOOSTVDDSEL_Pos (9U)
18669#define SYSCFG_PMCR_BOOSTVDDSEL_Msk (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) /*!< 0x00000200 */
18670#define SYSCFG_PMCR_BOOSTVDDSEL SYSCFG_PMCR_BOOSTVDDSEL_Msk /*!< Analog switch supply source selection : VDD/VDDA */
18671
18672#define SYSCFG_PMCR_EPIS_SEL_Pos (21U)
18673#define SYSCFG_PMCR_EPIS_SEL_Msk (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00E00000 */
18674#define SYSCFG_PMCR_EPIS_SEL SYSCFG_PMCR_EPIS_SEL_Msk /*!< Ethernet PHY Interface Selection */
18675#define SYSCFG_PMCR_EPIS_SEL_0 (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00200000 */
18676#define SYSCFG_PMCR_EPIS_SEL_1 (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00400000 */
18677#define SYSCFG_PMCR_EPIS_SEL_2 (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00800000 */
18678#define SYSCFG_PMCR_PA0SO_Pos (24U)
18679#define SYSCFG_PMCR_PA0SO_Msk (0x1UL << SYSCFG_PMCR_PA0SO_Pos) /*!< 0x01000000 */
18680#define SYSCFG_PMCR_PA0SO SYSCFG_PMCR_PA0SO_Msk /*!< PA0 Switch Open */
18681#define SYSCFG_PMCR_PA1SO_Pos (25U)
18682#define SYSCFG_PMCR_PA1SO_Msk (0x1UL << SYSCFG_PMCR_PA1SO_Pos) /*!< 0x02000000 */
18683#define SYSCFG_PMCR_PA1SO SYSCFG_PMCR_PA1SO_Msk /*!< PA1 Switch Open */
18684#define SYSCFG_PMCR_PC2SO_Pos (26U)
18685#define SYSCFG_PMCR_PC2SO_Msk (0x1UL << SYSCFG_PMCR_PC2SO_Pos) /*!< 0x04000000 */
18686#define SYSCFG_PMCR_PC2SO SYSCFG_PMCR_PC2SO_Msk /*!< PC2 Switch Open */
18687#define SYSCFG_PMCR_PC3SO_Pos (27U)
18688#define SYSCFG_PMCR_PC3SO_Msk (0x1UL << SYSCFG_PMCR_PC3SO_Pos) /*!< 0x08000000 */
18689#define SYSCFG_PMCR_PC3SO SYSCFG_PMCR_PC3SO_Msk /*!< PC3 Switch Open */
18690
18691/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
18692#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
18693#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
18694#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
18695#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
18696#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
18697#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
18698#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
18699#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
18700#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
18701#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
18702#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
18703#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
18704/**
18705 * @brief EXTI0 configuration
18706 */
18707#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
18708#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
18709#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
18710#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
18711#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
18712#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
18713#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
18714#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
18715#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
18716#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
18717#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
18718
18719/**
18720 * @brief EXTI1 configuration
18721 */
18722#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
18723#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
18724#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
18725#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
18726#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
18727#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
18728#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
18729#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
18730#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
18731#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
18732#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
18733/**
18734 * @brief EXTI2 configuration
18735 */
18736#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
18737#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
18738#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
18739#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
18740#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
18741#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
18742#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
18743#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
18744#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
18745#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
18746#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
18747
18748/**
18749 * @brief EXTI3 configuration
18750 */
18751#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
18752#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
18753#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
18754#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
18755#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
18756#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
18757#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
18758#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
18759#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
18760#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
18761#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
18762
18763/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
18764#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
18765#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
18766#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
18767#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
18768#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
18769#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
18770#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
18771#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
18772#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
18773#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
18774#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
18775#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
18776/**
18777 * @brief EXTI4 configuration
18778 */
18779#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
18780#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
18781#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
18782#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
18783#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
18784#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
18785#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
18786#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
18787#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
18788#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
18789#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
18790/**
18791 * @brief EXTI5 configuration
18792 */
18793#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
18794#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
18795#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
18796#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
18797#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
18798#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
18799#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
18800#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
18801#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
18802#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
18803#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
18804/**
18805 * @brief EXTI6 configuration
18806 */
18807#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
18808#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
18809#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
18810#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
18811#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
18812#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
18813#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
18814#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
18815#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
18816#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
18817#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
18818
18819/**
18820 * @brief EXTI7 configuration
18821 */
18822#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
18823#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
18824#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
18825#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
18826#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
18827#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
18828#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
18829#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
18830#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
18831#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
18832#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
18833
18834/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
18835#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
18836#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
18837#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
18838#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
18839#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
18840#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
18841#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
18842#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
18843#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
18844#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
18845#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
18846#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
18847
18848/**
18849 * @brief EXTI8 configuration
18850 */
18851#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
18852#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
18853#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
18854#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
18855#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
18856#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
18857#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
18858#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
18859#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
18860#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
18861#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
18862
18863/**
18864 * @brief EXTI9 configuration
18865 */
18866#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
18867#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
18868#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
18869#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
18870#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
18871#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
18872#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
18873#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
18874#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
18875#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
18876#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
18877
18878/**
18879 * @brief EXTI10 configuration
18880 */
18881#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
18882#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
18883#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
18884#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
18885#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
18886#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
18887#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
18888#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
18889#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
18890#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
18891#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
18892
18893/**
18894 * @brief EXTI11 configuration
18895 */
18896#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
18897#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
18898#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
18899#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
18900#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
18901#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
18902#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
18903#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
18904#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
18905#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
18906#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
18907
18908/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
18909#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
18910#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
18911#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
18912#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
18913#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
18914#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
18915#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
18916#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
18917#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
18918#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
18919#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
18920#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
18921/**
18922 * @brief EXTI12 configuration
18923 */
18924#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
18925#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
18926#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
18927#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
18928#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
18929#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
18930#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
18931#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
18932#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
18933#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
18934#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
18935/**
18936 * @brief EXTI13 configuration
18937 */
18938#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
18939#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
18940#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
18941#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
18942#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
18943#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
18944#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
18945#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
18946#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
18947#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
18948#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
18949/**
18950 * @brief EXTI14 configuration
18951 */
18952#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
18953#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
18954#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
18955#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
18956#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
18957#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
18958#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
18959#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
18960#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
18961#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
18962#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
18963/**
18964 * @brief EXTI15 configuration
18965 */
18966#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
18967#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
18968#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
18969#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
18970#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
18971#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
18972#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
18973#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
18974#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
18975#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
18976#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
18977
18978/****************** Bit definition for SYSCFG_CFGR register ******************/
18979#define SYSCFG_CFGR_PVDL_Pos (2U)
18980#define SYSCFG_CFGR_PVDL_Msk (0x1UL << SYSCFG_CFGR_PVDL_Pos) /*!< 0x00000004 */
18981#define SYSCFG_CFGR_PVDL SYSCFG_CFGR_PVDL_Msk /*!<PVD lock enable bit */
18982#define SYSCFG_CFGR_FLASHL_Pos (3U)
18983#define SYSCFG_CFGR_FLASHL_Msk (0x1UL << SYSCFG_CFGR_FLASHL_Pos) /*!< 0x00000008 */
18984#define SYSCFG_CFGR_FLASHL SYSCFG_CFGR_FLASHL_Msk /*!<FLASH double ECC error lock bit */
18985#define SYSCFG_CFGR_CM7L_Pos (6U)
18986#define SYSCFG_CFGR_CM7L_Msk (0x1UL << SYSCFG_CFGR_CM7L_Pos) /*!< 0x00000040 */
18987#define SYSCFG_CFGR_CM7L SYSCFG_CFGR_CM7L_Msk /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */
18988#define SYSCFG_CFGR_BKRAML_Pos (7U)
18989#define SYSCFG_CFGR_BKRAML_Msk (0x1UL << SYSCFG_CFGR_BKRAML_Pos) /*!< 0x00000080 */
18990#define SYSCFG_CFGR_BKRAML SYSCFG_CFGR_BKRAML_Msk /*!<Backup SRAM double ECC error lock bit */
18991#define SYSCFG_CFGR_SRAM4L_Pos (9U)
18992#define SYSCFG_CFGR_SRAM4L_Msk (0x1UL << SYSCFG_CFGR_SRAM4L_Pos) /*!< 0x00000200 */
18993#define SYSCFG_CFGR_SRAM4L SYSCFG_CFGR_SRAM4L_Msk /*!<SRAM4 double ECC error lock bit */
18994#define SYSCFG_CFGR_SRAM3L_Pos (10U)
18995#define SYSCFG_CFGR_SRAM3L_Msk (0x1UL << SYSCFG_CFGR_SRAM3L_Pos) /*!< 0x00000400 */
18996#define SYSCFG_CFGR_SRAM3L SYSCFG_CFGR_SRAM3L_Msk /*!<SRAM3 double ECC error lock bit */
18997#define SYSCFG_CFGR_SRAM2L_Pos (11U)
18998#define SYSCFG_CFGR_SRAM2L_Msk (0x1UL << SYSCFG_CFGR_SRAM2L_Pos) /*!< 0x00000800 */
18999#define SYSCFG_CFGR_SRAM2L SYSCFG_CFGR_SRAM2L_Msk /*!<SRAM2 double ECC error lock bit */
19000#define SYSCFG_CFGR_SRAM1L_Pos (12U)
19001#define SYSCFG_CFGR_SRAM1L_Msk (0x1UL << SYSCFG_CFGR_SRAM1L_Pos) /*!< 0x00001000 */
19002#define SYSCFG_CFGR_SRAM1L SYSCFG_CFGR_SRAM1L_Msk /*!<SRAM1 double ECC error lock bit */
19003#define SYSCFG_CFGR_DTCML_Pos (13U)
19004#define SYSCFG_CFGR_DTCML_Msk (0x1UL << SYSCFG_CFGR_DTCML_Pos) /*!< 0x00002000 */
19005#define SYSCFG_CFGR_DTCML SYSCFG_CFGR_DTCML_Msk /*!<DTCM double ECC error lock bit */
19006#define SYSCFG_CFGR_ITCML_Pos (14U)
19007#define SYSCFG_CFGR_ITCML_Msk (0x1UL << SYSCFG_CFGR_ITCML_Pos) /*!< 0x00004000 */
19008#define SYSCFG_CFGR_ITCML SYSCFG_CFGR_ITCML_Msk /*!<ITCM double ECC error lock bit */
19009#define SYSCFG_CFGR_AXISRAML_Pos (15U)
19010#define SYSCFG_CFGR_AXISRAML_Msk (0x1UL << SYSCFG_CFGR_AXISRAML_Pos) /*!< 0x00008000 */
19011#define SYSCFG_CFGR_AXISRAML SYSCFG_CFGR_AXISRAML_Msk /*!<AXISRAM double ECC error lock bit */
19012
19013/****************** Bit definition for SYSCFG_CCCSR register ******************/
19014#define SYSCFG_CCCSR_EN_Pos (0U)
19015#define SYSCFG_CCCSR_EN_Msk (0x1UL << SYSCFG_CCCSR_EN_Pos) /*!< 0x00000001 */
19016#define SYSCFG_CCCSR_EN SYSCFG_CCCSR_EN_Msk /*!< I/O compensation cell enable */
19017#define SYSCFG_CCCSR_CS_Pos (1U)
19018#define SYSCFG_CCCSR_CS_Msk (0x1UL << SYSCFG_CCCSR_CS_Pos) /*!< 0x00000002 */
19019#define SYSCFG_CCCSR_CS SYSCFG_CCCSR_CS_Msk /*!< I/O compensation cell code selection */
19020#define SYSCFG_CCCSR_READY_Pos (8U)
19021#define SYSCFG_CCCSR_READY_Msk (0x1UL << SYSCFG_CCCSR_READY_Pos) /*!< 0x00000100 */
19022#define SYSCFG_CCCSR_READY SYSCFG_CCCSR_READY_Msk /*!< I/O compensation cell ready flag */
19023#define SYSCFG_CCCSR_HSLV_Pos (16U)
19024#define SYSCFG_CCCSR_HSLV_Msk (0x1UL << SYSCFG_CCCSR_HSLV_Pos) /*!< 0x00010000 */
19025#define SYSCFG_CCCSR_HSLV SYSCFG_CCCSR_HSLV_Msk /*!< High-speed at low-voltage */
19026
19027/****************** Bit definition for SYSCFG_CCVR register *******************/
19028#define SYSCFG_CCVR_NCV_Pos (0U)
19029#define SYSCFG_CCVR_NCV_Msk (0xFUL << SYSCFG_CCVR_NCV_Pos) /*!< 0x0000000F */
19030#define SYSCFG_CCVR_NCV SYSCFG_CCVR_NCV_Msk /*!< NMOS compensation value */
19031#define SYSCFG_CCVR_PCV_Pos (4U)
19032#define SYSCFG_CCVR_PCV_Msk (0xFUL << SYSCFG_CCVR_PCV_Pos) /*!< 0x000000F0 */
19033#define SYSCFG_CCVR_PCV SYSCFG_CCVR_PCV_Msk /*!< PMOS compensation value */
19034
19035/****************** Bit definition for SYSCFG_CCCR register *******************/
19036#define SYSCFG_CCCR_NCC_Pos (0U)
19037#define SYSCFG_CCCR_NCC_Msk (0xFUL << SYSCFG_CCCR_NCC_Pos) /*!< 0x0000000F */
19038#define SYSCFG_CCCR_NCC SYSCFG_CCCR_NCC_Msk /*!< NMOS compensation code */
19039#define SYSCFG_CCCR_PCC_Pos (4U)
19040#define SYSCFG_CCCR_PCC_Msk (0xFUL << SYSCFG_CCCR_PCC_Pos) /*!< 0x000000F0 */
19041#define SYSCFG_CCCR_PCC SYSCFG_CCCR_PCC_Msk /*!< PMOS compensation code */
19042/****************** Bit definition for SYSCFG_PWRCR register *******************/
19043#define SYSCFG_PWRCR_ODEN_Pos (0U)
19044#define SYSCFG_PWRCR_ODEN_Msk (0x1UL << SYSCFG_PWRCR_ODEN_Pos) /*!< 0x00000001 */
19045#define SYSCFG_PWRCR_ODEN SYSCFG_PWRCR_ODEN_Msk /*!< PWR overdrive enable */
19046
19047/****************** Bit definition for SYSCFG_PKGR register *******************/
19048#define SYSCFG_PKGR_PKG_Pos (0U)
19049#define SYSCFG_PKGR_PKG_Msk (0xFUL << SYSCFG_PKGR_PKG_Pos) /*!< 0x0000000F */
19050#define SYSCFG_PKGR_PKG SYSCFG_PKGR_PKG_Msk /*!< Package type */
19051
19052/****************** Bit definition for SYSCFG_UR0 register *******************/
19053#define SYSCFG_UR0_BKS_Pos (0U)
19054#define SYSCFG_UR0_BKS_Msk (0x1UL << SYSCFG_UR0_BKS_Pos) /*!< 0x00000001 */
19055#define SYSCFG_UR0_BKS SYSCFG_UR0_BKS_Msk /*!< Bank Swap */
19056#define SYSCFG_UR0_RDP_Pos (16U)
19057#define SYSCFG_UR0_RDP_Msk (0xFFUL << SYSCFG_UR0_RDP_Pos) /*!< 0x00FF0000 */
19058#define SYSCFG_UR0_RDP SYSCFG_UR0_RDP_Msk /*!< Readout protection */
19059
19060/****************** Bit definition for SYSCFG_UR2 register *******************/
19061#define SYSCFG_UR2_BORH_Pos (0U)
19062#define SYSCFG_UR2_BORH_Msk (0x3UL << SYSCFG_UR2_BORH_Pos) /*!< 0x00000003 */
19063#define SYSCFG_UR2_BORH SYSCFG_UR2_BORH_Msk /*!< Brown Out Reset High level */
19064#define SYSCFG_UR2_BORH_0 (0x1UL << SYSCFG_UR2_BORH_Pos) /*!< 0x00000001 */
19065#define SYSCFG_UR2_BORH_1 (0x2UL << SYSCFG_UR2_BORH_Pos) /*!< 0x00000002 */
19066#define SYSCFG_UR2_BOOT_ADD0_Pos (16U)
19067#define SYSCFG_UR2_BOOT_ADD0_Msk (0xFFFFUL << SYSCFG_UR2_BOOT_ADD0_Pos) /*!< 0xFFFF0000 */
19068#define SYSCFG_UR2_BOOT_ADD0 SYSCFG_UR2_BOOT_ADD0_Msk /*!< Core Boot Address 0 */
19069/****************** Bit definition for SYSCFG_UR3 register *******************/
19070#define SYSCFG_UR3_BOOT_ADD1_Pos (0U)
19071#define SYSCFG_UR3_BOOT_ADD1_Msk (0xFFFFUL << SYSCFG_UR3_BOOT_ADD1_Pos) /*!< 0x0000FFFF */
19072#define SYSCFG_UR3_BOOT_ADD1 SYSCFG_UR3_BOOT_ADD1_Msk /*!< Core Boot Address 1 */
19073
19074 /****************** Bit definition for SYSCFG_UR4 register *******************/
19075
19076#define SYSCFG_UR4_MEPAD_BANK1_Pos (16U)
19077#define SYSCFG_UR4_MEPAD_BANK1_Msk (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos) /*!< 0x00010000 */
19078#define SYSCFG_UR4_MEPAD_BANK1 SYSCFG_UR4_MEPAD_BANK1_Msk /*!< Mass Erase Protected Area Disabled for bank 1 */
19079
19080/****************** Bit definition for SYSCFG_UR5 register *******************/
19081#define SYSCFG_UR5_MESAD_BANK1_Pos (0U)
19082#define SYSCFG_UR5_MESAD_BANK1_Msk (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos) /*!< 0x00000001 */
19083#define SYSCFG_UR5_MESAD_BANK1 SYSCFG_UR5_MESAD_BANK1_Msk /*!< Mass erase secured area disabled for bank 1 */
19084#define SYSCFG_UR5_WRPN_BANK1_Pos (16U)
19085#define SYSCFG_UR5_WRPN_BANK1_Msk (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos) /*!< 0x00FF0000 */
19086#define SYSCFG_UR5_WRPN_BANK1 SYSCFG_UR5_WRPN_BANK1_Msk /*!< Write protection for flash bank 1 */
19087
19088/****************** Bit definition for SYSCFG_UR6 register *******************/
19089#define SYSCFG_UR6_PABEG_BANK1_Pos (0U)
19090#define SYSCFG_UR6_PABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos) /*!< 0x00000FFF */
19091#define SYSCFG_UR6_PABEG_BANK1 SYSCFG_UR6_PABEG_BANK1_Msk /*!< Protected area start address for bank 1 */
19092#define SYSCFG_UR6_PAEND_BANK1_Pos (16U)
19093#define SYSCFG_UR6_PAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos) /*!< 0x0FFF0000 */
19094#define SYSCFG_UR6_PAEND_BANK1 SYSCFG_UR6_PAEND_BANK1_Msk /*!< Protected area end address for bank 1 */
19095
19096/****************** Bit definition for SYSCFG_UR7 register *******************/
19097#define SYSCFG_UR7_SABEG_BANK1_Pos (0U)
19098#define SYSCFG_UR7_SABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos) /*!< 0x00000FFF */
19099#define SYSCFG_UR7_SABEG_BANK1 SYSCFG_UR7_SABEG_BANK1_Msk /*!< Secured area start address for bank 1 */
19100#define SYSCFG_UR7_SAEND_BANK1_Pos (16U)
19101#define SYSCFG_UR7_SAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos) /*!< 0x0FFF0000 */
19102#define SYSCFG_UR7_SAEND_BANK1 SYSCFG_UR7_SAEND_BANK1_Msk /*!< Secured area end address for bank 1 */
19103
19104/****************** Bit definition for SYSCFG_UR8 register *******************/
19105#define SYSCFG_UR8_MEPAD_BANK2_Pos (0U)
19106#define SYSCFG_UR8_MEPAD_BANK2_Msk (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos) /*!< 0x00000001 */
19107#define SYSCFG_UR8_MEPAD_BANK2 SYSCFG_UR8_MEPAD_BANK2_Msk /*!< Mass erase Protected area disabled for bank 2 */
19108#define SYSCFG_UR8_MESAD_BANK2_Pos (16U)
19109#define SYSCFG_UR8_MESAD_BANK2_Msk (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos) /*!< 0x00010000 */
19110#define SYSCFG_UR8_MESAD_BANK2 SYSCFG_UR8_MESAD_BANK2_Msk /*!< Mass Erase Secured Area Disabled for bank 2 */
19111
19112/****************** Bit definition for SYSCFG_UR9 register *******************/
19113#define SYSCFG_UR9_WRPN_BANK2_Pos (0U)
19114#define SYSCFG_UR9_WRPN_BANK2_Msk (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos) /*!< 0x000000FF */
19115#define SYSCFG_UR9_WRPN_BANK2 SYSCFG_UR9_WRPN_BANK2_Msk /*!< Write protection for flash bank 2 */
19116#define SYSCFG_UR9_PABEG_BANK2_Pos (16U)
19117#define SYSCFG_UR9_PABEG_BANK2_Msk (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos) /*!< 0x0FFF0000 */
19118#define SYSCFG_UR9_PABEG_BANK2 SYSCFG_UR9_PABEG_BANK2_Msk /*!< Protected area start address for bank 2 */
19119
19120/****************** Bit definition for SYSCFG_UR10 register *******************/
19121#define SYSCFG_UR10_PAEND_BANK2_Pos (0U)
19122#define SYSCFG_UR10_PAEND_BANK2_Msk (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos) /*!< 0x00000FFF */
19123#define SYSCFG_UR10_PAEND_BANK2 SYSCFG_UR10_PAEND_BANK2_Msk /*!< Protected area end address for bank 2 */
19124#define SYSCFG_UR10_SABEG_BANK2_Pos (16U)
19125#define SYSCFG_UR10_SABEG_BANK2_Msk (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos) /*!< 0x0FFF0000 */
19126#define SYSCFG_UR10_SABEG_BANK2 SYSCFG_UR10_SABEG_BANK2_Msk /*!< Secured area start address for bank 2 */
19127
19128/****************** Bit definition for SYSCFG_UR11 register *******************/
19129#define SYSCFG_UR11_SAEND_BANK2_Pos (0U)
19130#define SYSCFG_UR11_SAEND_BANK2_Msk (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos) /*!< 0x00000FFF */
19131#define SYSCFG_UR11_SAEND_BANK2 SYSCFG_UR11_SAEND_BANK2_Msk /*!< Secured area end address for bank 2 */
19132#define SYSCFG_UR11_IWDG1M_Pos (16U)
19133#define SYSCFG_UR11_IWDG1M_Msk (0x1UL << SYSCFG_UR11_IWDG1M_Pos) /*!< 0x00010000 */
19134#define SYSCFG_UR11_IWDG1M SYSCFG_UR11_IWDG1M_Msk /*!< Independent Watchdog 1 mode (SW or HW) */
19135
19136/****************** Bit definition for SYSCFG_UR12 register *******************/
19137
19138#define SYSCFG_UR12_SECURE_Pos (16U)
19139#define SYSCFG_UR12_SECURE_Msk (0x1UL << SYSCFG_UR12_SECURE_Pos) /*!< 0x00010000 */
19140#define SYSCFG_UR12_SECURE SYSCFG_UR12_SECURE_Msk /*!< Secure mode status */
19141
19142/****************** Bit definition for SYSCFG_UR13 register *******************/
19143#define SYSCFG_UR13_SDRS_Pos (0U)
19144#define SYSCFG_UR13_SDRS_Msk (0x3UL << SYSCFG_UR13_SDRS_Pos) /*!< 0x00000003 */
19145#define SYSCFG_UR13_SDRS SYSCFG_UR13_SDRS_Msk /*!< Secured DTCM RAM Size */
19146#define SYSCFG_UR13_D1SBRST_Pos (16U)
19147#define SYSCFG_UR13_D1SBRST_Msk (0x1UL << SYSCFG_UR13_D1SBRST_Pos) /*!< 0x00010000 */
19148#define SYSCFG_UR13_D1SBRST SYSCFG_UR13_D1SBRST_Msk /*!< D1 Standby reset */
19149
19150/****************** Bit definition for SYSCFG_UR14 register *******************/
19151#define SYSCFG_UR14_D1STPRST_Pos (0U)
19152#define SYSCFG_UR14_D1STPRST_Msk (0x1UL << SYSCFG_UR14_D1STPRST_Pos) /*!< 0x00000001 */
19153#define SYSCFG_UR14_D1STPRST SYSCFG_UR14_D1STPRST_Msk /*!< D1 Stop Reset */
19154
19155/****************** Bit definition for SYSCFG_UR15 register *******************/
19156#define SYSCFG_UR15_FZIWDGSTB_Pos (16U)
19157#define SYSCFG_UR15_FZIWDGSTB_Msk (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos) /*!< 0x00010000 */
19158#define SYSCFG_UR15_FZIWDGSTB SYSCFG_UR15_FZIWDGSTB_Msk /*!< Freeze independent watchdogs in Standby mode */
19159
19160/****************** Bit definition for SYSCFG_UR16 register *******************/
19161#define SYSCFG_UR16_FZIWDGSTP_Pos (0U)
19162#define SYSCFG_UR16_FZIWDGSTP_Msk (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos) /*!< 0x00000001 */
19163#define SYSCFG_UR16_FZIWDGSTP SYSCFG_UR16_FZIWDGSTP_Msk /*!< Freeze independent watchdogs in Stop mode */
19164#define SYSCFG_UR16_PKP_Pos (16U)
19165#define SYSCFG_UR16_PKP_Msk (0x1UL << SYSCFG_UR16_PKP_Pos) /*!< 0x00010000 */
19166#define SYSCFG_UR16_PKP SYSCFG_UR16_PKP_Msk /*!< Private key programmed */
19167
19168/****************** Bit definition for SYSCFG_UR17 register *******************/
19169#define SYSCFG_UR17_IOHSLV_Pos (0U)
19170#define SYSCFG_UR17_IOHSLV_Msk (0x1UL << SYSCFG_UR17_IOHSLV_Pos) /*!< 0x00000001 */
19171#define SYSCFG_UR17_IOHSLV SYSCFG_UR17_IOHSLV_Msk /*!< I/O high speed / low voltage */
19172
19173
19174/******************************************************************************/
19175/* */
19176/* TIM */
19177/* */
19178/******************************************************************************/
19179#define TIM_BREAK_INPUT_SUPPORT /*!<TIM Break input feature */
19180
19181/******************* Bit definition for TIM_CR1 register ********************/
19182#define TIM_CR1_CEN_Pos (0U)
19183#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
19184#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
19185#define TIM_CR1_UDIS_Pos (1U)
19186#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
19187#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
19188#define TIM_CR1_URS_Pos (2U)
19189#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
19190#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
19191#define TIM_CR1_OPM_Pos (3U)
19192#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
19193#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
19194#define TIM_CR1_DIR_Pos (4U)
19195#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
19196#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
19197
19198#define TIM_CR1_CMS_Pos (5U)
19199#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
19200#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
19201#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
19202#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
19203
19204#define TIM_CR1_ARPE_Pos (7U)
19205#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
19206#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
19207
19208#define TIM_CR1_CKD_Pos (8U)
19209#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
19210#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
19211#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
19212#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
19213
19214#define TIM_CR1_UIFREMAP_Pos (11U)
19215#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
19216#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
19217
19218/******************* Bit definition for TIM_CR2 register ********************/
19219#define TIM_CR2_CCPC_Pos (0U)
19220#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
19221#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
19222#define TIM_CR2_CCUS_Pos (2U)
19223#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
19224#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
19225#define TIM_CR2_CCDS_Pos (3U)
19226#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
19227#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
19228
19229#define TIM_CR2_MMS_Pos (4U)
19230#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
19231#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
19232#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
19233#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
19234#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
19235
19236#define TIM_CR2_TI1S_Pos (7U)
19237#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
19238#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
19239#define TIM_CR2_OIS1_Pos (8U)
19240#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
19241#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
19242#define TIM_CR2_OIS1N_Pos (9U)
19243#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
19244#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
19245#define TIM_CR2_OIS2_Pos (10U)
19246#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
19247#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
19248#define TIM_CR2_OIS2N_Pos (11U)
19249#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
19250#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
19251#define TIM_CR2_OIS3_Pos (12U)
19252#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
19253#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
19254#define TIM_CR2_OIS3N_Pos (13U)
19255#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
19256#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
19257#define TIM_CR2_OIS4_Pos (14U)
19258#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
19259#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
19260#define TIM_CR2_OIS5_Pos (16U)
19261#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
19262#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
19263#define TIM_CR2_OIS6_Pos (17U)
19264#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
19265#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
19266
19267#define TIM_CR2_MMS2_Pos (20U)
19268#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
19269#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
19270#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
19271#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
19272#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
19273#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
19274
19275/******************* Bit definition for TIM_SMCR register *******************/
19276#define TIM_SMCR_SMS_Pos (0U)
19277#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
19278#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
19279#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
19280#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
19281#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
19282#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
19283
19284#define TIM_SMCR_TS_Pos (4U)
19285#define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */
19286#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[4:0] bits (Trigger selection) */
19287#define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
19288#define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
19289#define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
19290#define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */
19291#define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */
19292
19293#define TIM_SMCR_MSM_Pos (7U)
19294#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
19295#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
19296
19297#define TIM_SMCR_ETF_Pos (8U)
19298#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
19299#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
19300#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
19301#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
19302#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
19303#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
19304
19305#define TIM_SMCR_ETPS_Pos (12U)
19306#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
19307#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
19308#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
19309#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
19310
19311#define TIM_SMCR_ECE_Pos (14U)
19312#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
19313#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
19314#define TIM_SMCR_ETP_Pos (15U)
19315#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
19316#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
19317
19318/******************* Bit definition for TIM_DIER register *******************/
19319#define TIM_DIER_UIE_Pos (0U)
19320#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
19321#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
19322#define TIM_DIER_CC1IE_Pos (1U)
19323#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
19324#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
19325#define TIM_DIER_CC2IE_Pos (2U)
19326#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
19327#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
19328#define TIM_DIER_CC3IE_Pos (3U)
19329#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
19330#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
19331#define TIM_DIER_CC4IE_Pos (4U)
19332#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
19333#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
19334#define TIM_DIER_COMIE_Pos (5U)
19335#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
19336#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
19337#define TIM_DIER_TIE_Pos (6U)
19338#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
19339#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
19340#define TIM_DIER_BIE_Pos (7U)
19341#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
19342#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
19343#define TIM_DIER_UDE_Pos (8U)
19344#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
19345#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
19346#define TIM_DIER_CC1DE_Pos (9U)
19347#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
19348#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
19349#define TIM_DIER_CC2DE_Pos (10U)
19350#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
19351#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
19352#define TIM_DIER_CC3DE_Pos (11U)
19353#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
19354#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
19355#define TIM_DIER_CC4DE_Pos (12U)
19356#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
19357#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
19358#define TIM_DIER_COMDE_Pos (13U)
19359#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
19360#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
19361#define TIM_DIER_TDE_Pos (14U)
19362#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
19363#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
19364
19365/******************** Bit definition for TIM_SR register ********************/
19366#define TIM_SR_UIF_Pos (0U)
19367#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
19368#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
19369#define TIM_SR_CC1IF_Pos (1U)
19370#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
19371#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
19372#define TIM_SR_CC2IF_Pos (2U)
19373#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
19374#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
19375#define TIM_SR_CC3IF_Pos (3U)
19376#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
19377#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
19378#define TIM_SR_CC4IF_Pos (4U)
19379#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
19380#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
19381#define TIM_SR_COMIF_Pos (5U)
19382#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
19383#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
19384#define TIM_SR_TIF_Pos (6U)
19385#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
19386#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
19387#define TIM_SR_BIF_Pos (7U)
19388#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
19389#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
19390#define TIM_SR_B2IF_Pos (8U)
19391#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
19392#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break2 interrupt Flag */
19393#define TIM_SR_CC1OF_Pos (9U)
19394#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
19395#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
19396#define TIM_SR_CC2OF_Pos (10U)
19397#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
19398#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
19399#define TIM_SR_CC3OF_Pos (11U)
19400#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
19401#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
19402#define TIM_SR_CC4OF_Pos (12U)
19403#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
19404#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
19405#define TIM_SR_CC5IF_Pos (16U)
19406#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
19407#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
19408#define TIM_SR_CC6IF_Pos (17U)
19409#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
19410#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
19411#define TIM_SR_SBIF_Pos (13U)
19412#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
19413#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!< System Break Flag */
19414
19415/******************* Bit definition for TIM_EGR register ********************/
19416#define TIM_EGR_UG_Pos (0U)
19417#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
19418#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
19419#define TIM_EGR_CC1G_Pos (1U)
19420#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
19421#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
19422#define TIM_EGR_CC2G_Pos (2U)
19423#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
19424#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
19425#define TIM_EGR_CC3G_Pos (3U)
19426#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
19427#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
19428#define TIM_EGR_CC4G_Pos (4U)
19429#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
19430#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
19431#define TIM_EGR_COMG_Pos (5U)
19432#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
19433#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
19434#define TIM_EGR_TG_Pos (6U)
19435#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
19436#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
19437#define TIM_EGR_BG_Pos (7U)
19438#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
19439#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
19440#define TIM_EGR_B2G_Pos (8U)
19441#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
19442#define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break Generation */
19443
19444
19445/****************** Bit definition for TIM_CCMR1 register *******************/
19446#define TIM_CCMR1_CC1S_Pos (0U)
19447#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
19448#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
19449#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
19450#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
19451
19452#define TIM_CCMR1_OC1FE_Pos (2U)
19453#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
19454#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
19455#define TIM_CCMR1_OC1PE_Pos (3U)
19456#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
19457#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
19458
19459#define TIM_CCMR1_OC1M_Pos (4U)
19460#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
19461#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
19462#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
19463#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
19464#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
19465#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
19466
19467#define TIM_CCMR1_OC1CE_Pos (7U)
19468#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
19469#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
19470
19471#define TIM_CCMR1_CC2S_Pos (8U)
19472#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
19473#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
19474#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
19475#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
19476
19477#define TIM_CCMR1_OC2FE_Pos (10U)
19478#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
19479#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
19480#define TIM_CCMR1_OC2PE_Pos (11U)
19481#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
19482#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
19483
19484#define TIM_CCMR1_OC2M_Pos (12U)
19485#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
19486#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
19487#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
19488#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
19489#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
19490#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
19491
19492#define TIM_CCMR1_OC2CE_Pos (15U)
19493#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
19494#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
19495
19496/*----------------------------------------------------------------------------*/
19497
19498#define TIM_CCMR1_IC1PSC_Pos (2U)
19499#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
19500#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
19501#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
19502#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
19503
19504#define TIM_CCMR1_IC1F_Pos (4U)
19505#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
19506#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
19507#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
19508#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
19509#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
19510#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
19511
19512#define TIM_CCMR1_IC2PSC_Pos (10U)
19513#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
19514#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
19515#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
19516#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
19517
19518#define TIM_CCMR1_IC2F_Pos (12U)
19519#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
19520#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
19521#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
19522#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
19523#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
19524#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
19525
19526/****************** Bit definition for TIM_CCMR2 register *******************/
19527#define TIM_CCMR2_CC3S_Pos (0U)
19528#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
19529#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
19530#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
19531#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
19532
19533#define TIM_CCMR2_OC3FE_Pos (2U)
19534#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
19535#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
19536#define TIM_CCMR2_OC3PE_Pos (3U)
19537#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
19538#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
19539
19540#define TIM_CCMR2_OC3M_Pos (4U)
19541#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
19542#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
19543#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
19544#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
19545#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
19546#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
19547
19548#define TIM_CCMR2_OC3CE_Pos (7U)
19549#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
19550#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
19551
19552#define TIM_CCMR2_CC4S_Pos (8U)
19553#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
19554#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
19555#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
19556#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
19557
19558#define TIM_CCMR2_OC4FE_Pos (10U)
19559#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
19560#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
19561#define TIM_CCMR2_OC4PE_Pos (11U)
19562#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
19563#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
19564
19565#define TIM_CCMR2_OC4M_Pos (12U)
19566#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
19567#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
19568#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
19569#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
19570#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
19571#define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
19572
19573#define TIM_CCMR2_OC4CE_Pos (15U)
19574#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
19575#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
19576
19577/*----------------------------------------------------------------------------*/
19578
19579#define TIM_CCMR2_IC3PSC_Pos (2U)
19580#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
19581#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
19582#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
19583#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
19584
19585#define TIM_CCMR2_IC3F_Pos (4U)
19586#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
19587#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
19588#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
19589#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
19590#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
19591#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
19592
19593#define TIM_CCMR2_IC4PSC_Pos (10U)
19594#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
19595#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
19596#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
19597#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
19598
19599#define TIM_CCMR2_IC4F_Pos (12U)
19600#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
19601#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
19602#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
19603#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
19604#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
19605#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
19606
19607/******************* Bit definition for TIM_CCER register *******************/
19608#define TIM_CCER_CC1E_Pos (0U)
19609#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
19610#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
19611#define TIM_CCER_CC1P_Pos (1U)
19612#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
19613#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
19614#define TIM_CCER_CC1NE_Pos (2U)
19615#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
19616#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
19617#define TIM_CCER_CC1NP_Pos (3U)
19618#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
19619#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
19620#define TIM_CCER_CC2E_Pos (4U)
19621#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
19622#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
19623#define TIM_CCER_CC2P_Pos (5U)
19624#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
19625#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
19626#define TIM_CCER_CC2NE_Pos (6U)
19627#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
19628#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
19629#define TIM_CCER_CC2NP_Pos (7U)
19630#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
19631#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
19632#define TIM_CCER_CC3E_Pos (8U)
19633#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
19634#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
19635#define TIM_CCER_CC3P_Pos (9U)
19636#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
19637#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
19638#define TIM_CCER_CC3NE_Pos (10U)
19639#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
19640#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
19641#define TIM_CCER_CC3NP_Pos (11U)
19642#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
19643#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
19644#define TIM_CCER_CC4E_Pos (12U)
19645#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
19646#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
19647#define TIM_CCER_CC4P_Pos (13U)
19648#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
19649#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
19650#define TIM_CCER_CC4NP_Pos (15U)
19651#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
19652#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
19653#define TIM_CCER_CC5E_Pos (16U)
19654#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
19655#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
19656#define TIM_CCER_CC5P_Pos (17U)
19657#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
19658#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
19659#define TIM_CCER_CC6E_Pos (20U)
19660#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
19661#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
19662#define TIM_CCER_CC6P_Pos (21U)
19663#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
19664#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
19665/******************* Bit definition for TIM_CNT register ********************/
19666#define TIM_CNT_CNT_Pos (0U)
19667#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
19668#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
19669#define TIM_CNT_UIFCPY_Pos (31U)
19670#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
19671#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy */
19672/******************* Bit definition for TIM_PSC register ********************/
19673#define TIM_PSC_PSC_Pos (0U)
19674#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
19675#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
19676
19677/******************* Bit definition for TIM_ARR register ********************/
19678#define TIM_ARR_ARR_Pos (0U)
19679#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
19680#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
19681
19682/******************* Bit definition for TIM_RCR register ********************/
19683#define TIM_RCR_REP_Pos (0U)
19684#define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */
19685#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
19686
19687/******************* Bit definition for TIM_CCR1 register *******************/
19688#define TIM_CCR1_CCR1_Pos (0U)
19689#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
19690#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
19691
19692/******************* Bit definition for TIM_CCR2 register *******************/
19693#define TIM_CCR2_CCR2_Pos (0U)
19694#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
19695#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
19696
19697/******************* Bit definition for TIM_CCR3 register *******************/
19698#define TIM_CCR3_CCR3_Pos (0U)
19699#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
19700#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
19701
19702/******************* Bit definition for TIM_CCR4 register *******************/
19703#define TIM_CCR4_CCR4_Pos (0U)
19704#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
19705#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
19706
19707/******************* Bit definition for TIM_CCR5 register *******************/
19708#define TIM_CCR5_CCR5_Pos (0U)
19709#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
19710#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
19711#define TIM_CCR5_GC5C1_Pos (29U)
19712#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
19713#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
19714#define TIM_CCR5_GC5C2_Pos (30U)
19715#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
19716#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
19717#define TIM_CCR5_GC5C3_Pos (31U)
19718#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
19719#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
19720
19721/******************* Bit definition for TIM_CCR6 register *******************/
19722#define TIM_CCR6_CCR6_Pos (0U)
19723#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
19724#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
19725
19726/******************* Bit definition for TIM_BDTR register *******************/
19727#define TIM_BDTR_DTG_Pos (0U)
19728#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
19729#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
19730#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
19731#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
19732#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
19733#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
19734#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
19735#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
19736#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
19737#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
19738
19739#define TIM_BDTR_LOCK_Pos (8U)
19740#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
19741#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
19742#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
19743#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
19744
19745#define TIM_BDTR_OSSI_Pos (10U)
19746#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
19747#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
19748#define TIM_BDTR_OSSR_Pos (11U)
19749#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
19750#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
19751#define TIM_BDTR_BKE_Pos (12U)
19752#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
19753#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break1 */
19754#define TIM_BDTR_BKP_Pos (13U)
19755#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
19756#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break1 */
19757#define TIM_BDTR_AOE_Pos (14U)
19758#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
19759#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
19760#define TIM_BDTR_MOE_Pos (15U)
19761#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
19762#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
19763
19764#define TIM_BDTR_BKF_Pos (16U)
19765#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
19766#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break1 */
19767#define TIM_BDTR_BK2F_Pos (20U)
19768#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
19769#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break2 */
19770
19771#define TIM_BDTR_BK2E_Pos (24U)
19772#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
19773#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break2 */
19774#define TIM_BDTR_BK2P_Pos (25U)
19775#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
19776#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
19777
19778/******************* Bit definition for TIM_DCR register ********************/
19779#define TIM_DCR_DBA_Pos (0U)
19780#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
19781#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
19782#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
19783#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
19784#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
19785#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
19786#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
19787
19788#define TIM_DCR_DBL_Pos (8U)
19789#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
19790#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
19791#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
19792#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
19793#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
19794#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
19795#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
19796
19797/******************* Bit definition for TIM_DMAR register *******************/
19798#define TIM_DMAR_DMAB_Pos (0U)
19799#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
19800#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
19801
19802/****************** Bit definition for TIM_CCMR3 register *******************/
19803#define TIM_CCMR3_OC5FE_Pos (2U)
19804#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
19805#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
19806#define TIM_CCMR3_OC5PE_Pos (3U)
19807#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
19808#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
19809
19810#define TIM_CCMR3_OC5M_Pos (4U)
19811#define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
19812#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
19813#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
19814#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
19815#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
19816#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
19817
19818#define TIM_CCMR3_OC5CE_Pos (7U)
19819#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
19820#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
19821
19822#define TIM_CCMR3_OC6FE_Pos (10U)
19823#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
19824#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 4 Fast enable */
19825#define TIM_CCMR3_OC6PE_Pos (11U)
19826#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
19827#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
19828
19829#define TIM_CCMR3_OC6M_Pos (12U)
19830#define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
19831#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
19832#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
19833#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
19834#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
19835#define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
19836
19837#define TIM_CCMR3_OC6CE_Pos (15U)
19838#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
19839#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 4 Clear Enable */
19840/******************* Bit definition for TIM1_AF1 register *********************/
19841#define TIM1_AF1_BKINE_Pos (0U)
19842#define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
19843#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
19844#define TIM1_AF1_BKCMP1E_Pos (1U)
19845#define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
19846#define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
19847#define TIM1_AF1_BKCMP2E_Pos (2U)
19848#define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
19849#define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
19850#define TIM1_AF1_BKDF1BK0E_Pos (8U)
19851#define TIM1_AF1_BKDF1BK0E_Msk (0x1UL << TIM1_AF1_BKDF1BK0E_Pos) /*!< 0x00000100 */
19852#define TIM1_AF1_BKDF1BK0E TIM1_AF1_BKDF1BK0E_Msk /*!<BKDF1BK0E Break input DFSDM Break 0 */
19853#define TIM1_AF1_BKINP_Pos (9U)
19854#define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
19855#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
19856#define TIM1_AF1_BKCMP1P_Pos (10U)
19857#define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
19858#define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
19859#define TIM1_AF1_BKCMP2P_Pos (11U)
19860#define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
19861#define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
19862
19863#define TIM1_AF1_ETRSEL_Pos (14U)
19864#define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
19865#define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */
19866#define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */
19867#define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */
19868#define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */
19869#define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */
19870
19871/******************* Bit definition for TIM1_AF2 register *********************/
19872#define TIM1_AF2_BK2INE_Pos (0U)
19873#define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
19874#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BK2INE Break input 2 enable bit */
19875#define TIM1_AF2_BK2CMP1E_Pos (1U)
19876#define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
19877#define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BK2CMP1E Break2 Compare1 Enable bit */
19878#define TIM1_AF2_BK2CMP2E_Pos (2U)
19879#define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
19880#define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BK2CMP1E Break2 Compare2 Enable bit */
19881#define TIM1_AF2_BK2DFBK1E_Pos (8U)
19882#define TIM1_AF2_BK2DFBK1E_Msk (0x1UL << TIM1_AF2_BK2DFBK1E_Pos) /*!< 0x00000100 */
19883#define TIM1_AF2_BK2DFBK1E TIM1_AF2_BK2DFBK1E_Msk /*!<BK2DFBK1E Break input2 DFSDM Break 1 */
19884#define TIM1_AF2_BK2INP_Pos (9U)
19885#define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
19886#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRKINP Break2 input polarity */
19887#define TIM1_AF2_BK2CMP1P_Pos (10U)
19888#define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
19889#define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BKCMP1P Break2 COMP1 input polarity */
19890#define TIM1_AF2_BK2CMP2P_Pos (11U)
19891#define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
19892#define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BKCMP2P Break2 COMP2 input polarity */
19893
19894/******************* Bit definition for TIM_TISEL register *********************/
19895#define TIM_TISEL_TI1SEL_Pos (0U)
19896#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
19897#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/
19898#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
19899#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
19900#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
19901#define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
19902
19903#define TIM_TISEL_TI2SEL_Pos (8U)
19904#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
19905#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/
19906#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
19907#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
19908#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
19909#define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
19910
19911#define TIM_TISEL_TI3SEL_Pos (16U)
19912#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
19913#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/
19914#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
19915#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
19916#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
19917#define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
19918
19919#define TIM_TISEL_TI4SEL_Pos (24U)
19920#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
19921#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/
19922#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
19923#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
19924#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
19925#define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
19926
19927/******************* Bit definition for TIM8_AF1 register *********************/
19928#define TIM8_AF1_BKINE_Pos (0U)
19929#define TIM8_AF1_BKINE_Msk (0x1UL << TIM8_AF1_BKINE_Pos) /*!< 0x00000001 */
19930#define TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
19931#define TIM8_AF1_BKCMP1E_Pos (1U)
19932#define TIM8_AF1_BKCMP1E_Msk (0x1UL << TIM8_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
19933#define TIM8_AF1_BKCMP1E TIM8_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
19934#define TIM8_AF1_BKCMP2E_Pos (2U)
19935#define TIM8_AF1_BKCMP2E_Msk (0x1UL << TIM8_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
19936#define TIM8_AF1_BKCMP2E TIM8_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
19937#define TIM8_AF1_BKDFBK2E_Pos (8U)
19938#define TIM8_AF1_BKDFBK2E_Msk (0x1UL << TIM8_AF1_BKDFBK2E_Pos) /*!< 0x00000100 */
19939#define TIM8_AF1_BKDFBK2E TIM8_AF1_BKDFBK2E_Msk /*!<BKDFBK2E Break input DFSDM Break 2 */
19940#define TIM8_AF1_BKINP_Pos (9U)
19941#define TIM8_AF1_BKINP_Msk (0x1UL << TIM8_AF1_BKINP_Pos) /*!< 0x00000200 */
19942#define TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
19943#define TIM8_AF1_BKCMP1P_Pos (10U)
19944#define TIM8_AF1_BKCMP1P_Msk (0x1UL << TIM8_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
19945#define TIM8_AF1_BKCMP1P TIM8_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
19946#define TIM8_AF1_BKCMP2P_Pos (11U)
19947#define TIM8_AF1_BKCMP2P_Msk (0x1UL << TIM8_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
19948#define TIM8_AF1_BKCMP2P TIM8_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
19949
19950#define TIM8_AF1_ETRSEL_Pos (14U)
19951#define TIM8_AF1_ETRSEL_Msk (0xFUL << TIM8_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
19952#define TIM8_AF1_ETRSEL TIM8_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */
19953#define TIM8_AF1_ETRSEL_0 (0x1UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00004000 */
19954#define TIM8_AF1_ETRSEL_1 (0x2UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00008000 */
19955#define TIM8_AF1_ETRSEL_2 (0x4UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00010000 */
19956#define TIM8_AF1_ETRSEL_3 (0x8UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00020000 */
19957/******************* Bit definition for TIM8_AF2 register *********************/
19958#define TIM8_AF2_BK2INE_Pos (0U)
19959#define TIM8_AF2_BK2INE_Msk (0x1UL << TIM8_AF2_BK2INE_Pos) /*!< 0x00000001 */
19960#define TIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk /*!<BK2INE Break input 2 enable bit */
19961#define TIM8_AF2_BK2CMP1E_Pos (1U)
19962#define TIM8_AF2_BK2CMP1E_Msk (0x1UL << TIM8_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
19963#define TIM8_AF2_BK2CMP1E TIM8_AF2_BK2CMP1E_Msk /*!<BK2CMP1E Break2 Compare1 Enable bit */
19964#define TIM8_AF2_BK2CMP2E_Pos (2U)
19965#define TIM8_AF2_BK2CMP2E_Msk (0x1UL << TIM8_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
19966#define TIM8_AF2_BK2CMP2E TIM8_AF2_BK2CMP2E_Msk /*!<BK2CMP1E Break2 Compare2 Enable bit */
19967#define TIM8_AF2_BK2DFBK3E_Pos (8U)
19968#define TIM8_AF2_BK2DFBK3E_Msk (0x1UL << TIM8_AF2_BK2DFBK3E_Pos) /*!< 0x00000100 */
19969#define TIM8_AF2_BK2DFBK3E TIM8_AF2_BK2DFBK3E_Msk /*!<BK2DFBK1E Break input2 DFSDM Break 3 */
19970#define TIM8_AF2_BK2INP_Pos (9U)
19971#define TIM8_AF2_BK2INP_Msk (0x1UL << TIM8_AF2_BK2INP_Pos) /*!< 0x00000200 */
19972#define TIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk /*!<BRKINP Break2 input polarity */
19973#define TIM8_AF2_BK2CMP1P_Pos (10U)
19974#define TIM8_AF2_BK2CMP1P_Msk (0x1UL << TIM8_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
19975#define TIM8_AF2_BK2CMP1P TIM8_AF2_BK2CMP1P_Msk /*!<BKCMP1P Break2 COMP1 input polarity */
19976#define TIM8_AF2_BK2CMP2P_Pos (11U)
19977#define TIM8_AF2_BK2CMP2P_Msk (0x1UL << TIM8_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
19978#define TIM8_AF2_BK2CMP2P TIM8_AF2_BK2CMP2P_Msk /*!<BKCMP2P Break2 COMP2 input polarity */
19979
19980/******************* Bit definition for TIM2_AF1 register *********************/
19981#define TIM2_AF1_ETRSEL_Pos (14U)
19982#define TIM2_AF1_ETRSEL_Msk (0xFUL << TIM2_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
19983#define TIM2_AF1_ETRSEL TIM2_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */
19984#define TIM2_AF1_ETRSEL_0 (0x1UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00004000 */
19985#define TIM2_AF1_ETRSEL_1 (0x2UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00008000 */
19986#define TIM2_AF1_ETRSEL_2 (0x4UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00010000 */
19987#define TIM2_AF1_ETRSEL_3 (0x8UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00020000 */
19988
19989/******************* Bit definition for TIM3_AF1 register *********************/
19990#define TIM3_AF1_ETRSEL_Pos (14U)
19991#define TIM3_AF1_ETRSEL_Msk (0xFUL << TIM3_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
19992#define TIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */
19993#define TIM3_AF1_ETRSEL_0 (0x1UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00004000 */
19994#define TIM3_AF1_ETRSEL_1 (0x2UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00008000 */
19995#define TIM3_AF1_ETRSEL_2 (0x4UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00010000 */
19996#define TIM3_AF1_ETRSEL_3 (0x8UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00020000 */
19997
19998/******************* Bit definition for TIM5_AF1 register *********************/
19999#define TIM5_AF1_ETRSEL_Pos (14U)
20000#define TIM5_AF1_ETRSEL_Msk (0xFUL << TIM5_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
20001#define TIM5_AF1_ETRSEL TIM5_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */
20002#define TIM5_AF1_ETRSEL_0 (0x1UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00004000 */
20003#define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */
20004#define TIM5_AF1_ETRSEL_2 (0x4UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00010000 */
20005#define TIM5_AF1_ETRSEL_3 (0x8UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00020000 */
20006
20007/******************* Bit definition for TIM15_AF1 register *********************/
20008#define TIM15_AF1_BKINE_Pos (0U)
20009#define TIM15_AF1_BKINE_Msk (0x1UL << TIM15_AF1_BKINE_Pos) /*!< 0x00000001 */
20010#define TIM15_AF1_BKINE TIM15_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
20011#define TIM15_AF1_BKCMP1E_Pos (1U)
20012#define TIM15_AF1_BKCMP1E_Msk (0x1UL << TIM15_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
20013#define TIM15_AF1_BKCMP1E TIM15_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
20014#define TIM15_AF1_BKCMP2E_Pos (2U)
20015#define TIM15_AF1_BKCMP2E_Msk (0x1UL << TIM15_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
20016#define TIM15_AF1_BKCMP2E TIM15_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
20017#define TIM15_AF1_BKDF1BK2E_Pos (8U)
20018#define TIM15_AF1_BKDF1BK2E_Msk (0x1UL << TIM15_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
20019#define TIM15_AF1_BKDF1BK2E TIM15_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[0] enable */
20020#define TIM15_AF1_BKINP_Pos (9U)
20021#define TIM15_AF1_BKINP_Msk (0x1UL << TIM15_AF1_BKINP_Pos) /*!< 0x00000200 */
20022#define TIM15_AF1_BKINP TIM15_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
20023#define TIM15_AF1_BKCMP1P_Pos (10U)
20024#define TIM15_AF1_BKCMP1P_Msk (0x1UL << TIM15_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
20025#define TIM15_AF1_BKCMP1P TIM15_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
20026#define TIM15_AF1_BKCMP2P_Pos (11U)
20027#define TIM15_AF1_BKCMP2P_Msk (0x1UL << TIM15_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
20028#define TIM15_AF1_BKCMP2P TIM15_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
20029
20030/******************* Bit definition for TIM16_ register *********************/
20031#define TIM16_AF1_BKINE_Pos (0U)
20032#define TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos) /*!< 0x00000001 */
20033#define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
20034#define TIM16_AF1_BKCMP1E_Pos (1U)
20035#define TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
20036#define TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
20037#define TIM16_AF1_BKCMP2E_Pos (2U)
20038#define TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
20039#define TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
20040#define TIM16_AF1_BKDF1BK2E_Pos (8U)
20041#define TIM16_AF1_BKDF1BK2E_Msk (0x1UL << TIM16_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
20042#define TIM16_AF1_BKDF1BK2E TIM16_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[1] enable */
20043#define TIM16_AF1_BKINP_Pos (9U)
20044#define TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos) /*!< 0x00000200 */
20045#define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
20046#define TIM16_AF1_BKCMP1P_Pos (10U)
20047#define TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
20048#define TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
20049#define TIM16_AF1_BKCMP2P_Pos (11U)
20050#define TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
20051#define TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
20052
20053/******************* Bit definition for TIM17_AF1 register *********************/
20054#define TIM17_AF1_BKINE_Pos (0U)
20055#define TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos) /*!< 0x00000001 */
20056#define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
20057#define TIM17_AF1_BKCMP1E_Pos (1U)
20058#define TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
20059#define TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
20060#define TIM17_AF1_BKCMP2E_Pos (2U)
20061#define TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
20062#define TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
20063#define TIM17_AF1_BKDF1BK2E_Pos (8U)
20064#define TIM17_AF1_BKDF1BK2E_Msk (0x1UL << TIM17_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
20065#define TIM17_AF1_BKDF1BK2E TIM17_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[2] enable */
20066#define TIM17_AF1_BKINP_Pos (9U)
20067#define TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos) /*!< 0x00000200 */
20068#define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
20069#define TIM17_AF1_BKCMP1P_Pos (10U)
20070#define TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
20071#define TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
20072#define TIM17_AF1_BKCMP2P_Pos (11U)
20073#define TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
20074#define TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
20075
20076/******************************************************************************/
20077/* */
20078/* Low Power Timer (LPTTIM) */
20079/* */
20080/******************************************************************************/
20081/****************** Bit definition for LPTIM_ISR register *******************/
20082#define LPTIM_ISR_CMPM_Pos (0U)
20083#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
20084#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
20085#define LPTIM_ISR_ARRM_Pos (1U)
20086#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
20087#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
20088#define LPTIM_ISR_EXTTRIG_Pos (2U)
20089#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
20090#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
20091#define LPTIM_ISR_CMPOK_Pos (3U)
20092#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
20093#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
20094#define LPTIM_ISR_ARROK_Pos (4U)
20095#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
20096#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
20097#define LPTIM_ISR_UP_Pos (5U)
20098#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
20099#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
20100#define LPTIM_ISR_DOWN_Pos (6U)
20101#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
20102#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
20103
20104/****************** Bit definition for LPTIM_ICR register *******************/
20105#define LPTIM_ICR_CMPMCF_Pos (0U)
20106#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
20107#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
20108#define LPTIM_ICR_ARRMCF_Pos (1U)
20109#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
20110#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
20111#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
20112#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
20113#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
20114#define LPTIM_ICR_CMPOKCF_Pos (3U)
20115#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
20116#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
20117#define LPTIM_ICR_ARROKCF_Pos (4U)
20118#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
20119#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
20120#define LPTIM_ICR_UPCF_Pos (5U)
20121#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
20122#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
20123#define LPTIM_ICR_DOWNCF_Pos (6U)
20124#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
20125#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
20126
20127/****************** Bit definition for LPTIM_IER register ********************/
20128#define LPTIM_IER_CMPMIE_Pos (0U)
20129#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
20130#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
20131#define LPTIM_IER_ARRMIE_Pos (1U)
20132#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
20133#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
20134#define LPTIM_IER_EXTTRIGIE_Pos (2U)
20135#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
20136#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
20137#define LPTIM_IER_CMPOKIE_Pos (3U)
20138#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
20139#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
20140#define LPTIM_IER_ARROKIE_Pos (4U)
20141#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
20142#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
20143#define LPTIM_IER_UPIE_Pos (5U)
20144#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
20145#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
20146#define LPTIM_IER_DOWNIE_Pos (6U)
20147#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
20148#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
20149
20150/****************** Bit definition for LPTIM_CFGR register *******************/
20151#define LPTIM_CFGR_CKSEL_Pos (0U)
20152#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
20153#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
20154
20155#define LPTIM_CFGR_CKPOL_Pos (1U)
20156#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
20157#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
20158#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
20159#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
20160
20161#define LPTIM_CFGR_CKFLT_Pos (3U)
20162#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
20163#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
20164#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
20165#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
20166
20167#define LPTIM_CFGR_TRGFLT_Pos (6U)
20168#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
20169#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
20170#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
20171#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
20172
20173#define LPTIM_CFGR_PRESC_Pos (9U)
20174#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
20175#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
20176#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
20177#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
20178#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
20179
20180#define LPTIM_CFGR_TRIGSEL_Pos (13U)
20181#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
20182#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
20183#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
20184#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
20185#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
20186
20187#define LPTIM_CFGR_TRIGEN_Pos (17U)
20188#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
20189#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
20190#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
20191#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
20192
20193#define LPTIM_CFGR_TIMOUT_Pos (19U)
20194#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
20195#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
20196#define LPTIM_CFGR_WAVE_Pos (20U)
20197#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
20198#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
20199#define LPTIM_CFGR_WAVPOL_Pos (21U)
20200#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
20201#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
20202#define LPTIM_CFGR_PRELOAD_Pos (22U)
20203#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
20204#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
20205#define LPTIM_CFGR_COUNTMODE_Pos (23U)
20206#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
20207#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
20208#define LPTIM_CFGR_ENC_Pos (24U)
20209#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
20210#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
20211
20212/****************** Bit definition for LPTIM_CR register ********************/
20213#define LPTIM_CR_ENABLE_Pos (0U)
20214#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
20215#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
20216#define LPTIM_CR_SNGSTRT_Pos (1U)
20217#define LPTIM_CR_SNGSTRT_Msk (0x40001UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00080002 */
20218#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
20219#define LPTIM_CR_CNTSTRT_Pos (2U)
20220#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
20221#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
20222#define LPTIM_CR_COUNTRST_Pos (3U)
20223#define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
20224#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Timer Counter reset in synchronous mode*/
20225#define LPTIM_CR_RSTARE_Pos (4U)
20226#define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
20227#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Timer Counter reset after read enable (asynchronously)*/
20228
20229
20230/****************** Bit definition for LPTIM_CMP register *******************/
20231#define LPTIM_CMP_CMP_Pos (0U)
20232#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
20233#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
20234
20235/****************** Bit definition for LPTIM_ARR register *******************/
20236#define LPTIM_ARR_ARR_Pos (0U)
20237#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
20238#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
20239
20240/****************** Bit definition for LPTIM_CNT register *******************/
20241#define LPTIM_CNT_CNT_Pos (0U)
20242#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
20243#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
20244
20245/****************** Bit definition for LPTIM_CFGR2 register *****************/
20246#define LPTIM_CFGR2_IN1SEL_Pos (0U)
20247#define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003 */
20248#define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0] bits (Remap selection) */
20249#define LPTIM_CFGR2_IN1SEL_0 (0x1UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000001 */
20250#define LPTIM_CFGR2_IN1SEL_1 (0x2UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000002 */
20251#define LPTIM_CFGR2_IN2SEL_Pos (4U)
20252#define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030 */
20253#define LPTIM_CFGR2_IN2SEL LPTIM_CFGR2_IN2SEL_Msk /*!< IN2SEL[5:4] bits (Remap selection) */
20254#define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
20255#define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */
20256
20257/******************************************************************************/
20258/* */
20259/* Analog Comparators (COMP) */
20260/* */
20261/******************************************************************************/
20262
20263/******************* Bit definition for COMP_SR register ********************/
20264#define COMP_SR_C1VAL_Pos (0U)
20265#define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos) /*!< 0x00000001 */
20266#define COMP_SR_C1VAL COMP_SR_C1VAL_Msk
20267#define COMP_SR_C2VAL_Pos (1U)
20268#define COMP_SR_C2VAL_Msk (0x1UL << COMP_SR_C2VAL_Pos) /*!< 0x00000002 */
20269#define COMP_SR_C2VAL COMP_SR_C2VAL_Msk
20270#define COMP_SR_C1IF_Pos (16U)
20271#define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos) /*!< 0x00010000 */
20272#define COMP_SR_C1IF COMP_SR_C1IF_Msk
20273#define COMP_SR_C2IF_Pos (17U)
20274#define COMP_SR_C2IF_Msk (0x1UL << COMP_SR_C2IF_Pos) /*!< 0x00020000 */
20275#define COMP_SR_C2IF COMP_SR_C2IF_Msk
20276/******************* Bit definition for COMP_ICFR register ********************/
20277#define COMP_ICFR_C1IF_Pos (16U)
20278#define COMP_ICFR_C1IF_Msk (0x1UL << COMP_ICFR_C1IF_Pos) /*!< 0x00010000 */
20279#define COMP_ICFR_C1IF COMP_ICFR_C1IF_Msk
20280#define COMP_ICFR_C2IF_Pos (17U)
20281#define COMP_ICFR_C2IF_Msk (0x1UL << COMP_ICFR_C2IF_Pos) /*!< 0x00020000 */
20282#define COMP_ICFR_C2IF COMP_ICFR_C2IF_Msk
20283/******************* Bit definition for COMP_OR register ********************/
20284#define COMP_OR_AFOPA6_Pos (0U)
20285#define COMP_OR_AFOPA6_Msk (0x1UL << COMP_OR_AFOPA6_Pos) /*!< 0x00000001 */
20286#define COMP_OR_AFOPA6 COMP_OR_AFOPA6_Msk
20287#define COMP_OR_AFOPA8_Pos (1U)
20288#define COMP_OR_AFOPA8_Msk (0x1UL << COMP_OR_AFOPA8_Pos) /*!< 0x00000002 */
20289#define COMP_OR_AFOPA8 COMP_OR_AFOPA8_Msk
20290#define COMP_OR_AFOPB12_Pos (2U)
20291#define COMP_OR_AFOPB12_Msk (0x1UL << COMP_OR_AFOPB12_Pos) /*!< 0x00000004 */
20292#define COMP_OR_AFOPB12 COMP_OR_AFOPB12_Msk
20293#define COMP_OR_AFOPE6_Pos (3U)
20294#define COMP_OR_AFOPE6_Msk (0x1UL << COMP_OR_AFOPE6_Pos) /*!< 0x00000008 */
20295#define COMP_OR_AFOPE6 COMP_OR_AFOPE6_Msk
20296#define COMP_OR_AFOPE15_Pos (4U)
20297#define COMP_OR_AFOPE15_Msk (0x1UL << COMP_OR_AFOPE15_Pos) /*!< 0x00000010 */
20298#define COMP_OR_AFOPE15 COMP_OR_AFOPE15_Msk
20299#define COMP_OR_AFOPG2_Pos (5U)
20300#define COMP_OR_AFOPG2_Msk (0x1UL << COMP_OR_AFOPG2_Pos) /*!< 0x00000020 */
20301#define COMP_OR_AFOPG2 COMP_OR_AFOPG2_Msk
20302#define COMP_OR_AFOPG3_Pos (6U)
20303#define COMP_OR_AFOPG3_Msk (0x1UL << COMP_OR_AFOPG3_Pos) /*!< 0x00000040 */
20304#define COMP_OR_AFOPG3 COMP_OR_AFOPG3_Msk
20305#define COMP_OR_AFOPG4_Pos (7U)
20306#define COMP_OR_AFOPG4_Msk (0x1UL << COMP_OR_AFOPG4_Pos) /*!< 0x00000080 */
20307#define COMP_OR_AFOPG4 COMP_OR_AFOPG4_Msk
20308#define COMP_OR_AFOPI1_Pos (8U)
20309#define COMP_OR_AFOPI1_Msk (0x1UL << COMP_OR_AFOPI1_Pos) /*!< 0x00000100 */
20310#define COMP_OR_AFOPI1 COMP_OR_AFOPI1_Msk
20311#define COMP_OR_AFOPI4_Pos (9U)
20312#define COMP_OR_AFOPI4_Msk (0x1UL << COMP_OR_AFOPI4_Pos) /*!< 0x00000200 */
20313#define COMP_OR_AFOPI4 COMP_OR_AFOPI4_Msk
20314#define COMP_OR_AFOPK2_Pos (10U)
20315#define COMP_OR_AFOPK2_Msk (0x1UL << COMP_OR_AFOPK2_Pos) /*!< 0x00000400 */
20316#define COMP_OR_AFOPK2 COMP_OR_AFOPK2_Msk
20317
20318/*!< ****************** Bit definition for COMP_CFGRx register ********************/
20319#define COMP_CFGRx_EN_Pos (0U)
20320#define COMP_CFGRx_EN_Msk (0x1UL << COMP_CFGRx_EN_Pos) /*!< 0x00000001 */
20321#define COMP_CFGRx_EN COMP_CFGRx_EN_Msk /*!< COMPx enable bit */
20322#define COMP_CFGRx_BRGEN_Pos (1U)
20323#define COMP_CFGRx_BRGEN_Msk (0x1UL << COMP_CFGRx_BRGEN_Pos) /*!< 0x00000002 */
20324#define COMP_CFGRx_BRGEN COMP_CFGRx_BRGEN_Msk /*!< COMPx Scaler bridge enable */
20325#define COMP_CFGRx_SCALEN_Pos (2U)
20326#define COMP_CFGRx_SCALEN_Msk (0x1UL << COMP_CFGRx_SCALEN_Pos) /*!< 0x00000004 */
20327#define COMP_CFGRx_SCALEN COMP_CFGRx_SCALEN_Msk /*!< COMPx Voltage scaler enable bit */
20328#define COMP_CFGRx_POLARITY_Pos (3U)
20329#define COMP_CFGRx_POLARITY_Msk (0x1UL << COMP_CFGRx_POLARITY_Pos) /*!< 0x00000008 */
20330#define COMP_CFGRx_POLARITY COMP_CFGRx_POLARITY_Msk /*!< COMPx polarity selection bit */
20331#define COMP_CFGRx_WINMODE_Pos (4U)
20332#define COMP_CFGRx_WINMODE_Msk (0x1UL << COMP_CFGRx_WINMODE_Pos) /*!< 0x00000010 */
20333#define COMP_CFGRx_WINMODE COMP_CFGRx_WINMODE_Msk /*!< COMPx Windows mode selection bit */
20334#define COMP_CFGRx_ITEN_Pos (6U)
20335#define COMP_CFGRx_ITEN_Msk (0x1UL << COMP_CFGRx_ITEN_Pos) /*!< 0x00000040 */
20336#define COMP_CFGRx_ITEN COMP_CFGRx_ITEN_Msk /*!< COMPx interrupt enable */
20337#define COMP_CFGRx_HYST_Pos (8U)
20338#define COMP_CFGRx_HYST_Msk (0x3UL << COMP_CFGRx_HYST_Pos) /*!< 0x00000300 */
20339#define COMP_CFGRx_HYST COMP_CFGRx_HYST_Msk /*!< COMPx hysteresis selection bits */
20340#define COMP_CFGRx_HYST_0 (0x1UL << COMP_CFGRx_HYST_Pos) /*!< 0x00000100 */
20341#define COMP_CFGRx_HYST_1 (0x2UL << COMP_CFGRx_HYST_Pos) /*!< 0x00000200 */
20342#define COMP_CFGRx_PWRMODE_Pos (12U)
20343#define COMP_CFGRx_PWRMODE_Msk (0x3UL << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00003000 */
20344#define COMP_CFGRx_PWRMODE COMP_CFGRx_PWRMODE_Msk /*!< COMPx Power Mode of the comparator */
20345#define COMP_CFGRx_PWRMODE_0 (0x1UL << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00001000 */
20346#define COMP_CFGRx_PWRMODE_1 (0x2UL << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00002000 */
20347#define COMP_CFGRx_INMSEL_Pos (16U)
20348#define COMP_CFGRx_INMSEL_Msk (0x7UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00070000 */
20349#define COMP_CFGRx_INMSEL COMP_CFGRx_INMSEL_Msk /*!< COMPx input minus selection bit */
20350#define COMP_CFGRx_INMSEL_0 (0x1UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00010000 */
20351#define COMP_CFGRx_INMSEL_1 (0x2UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00020000 */
20352#define COMP_CFGRx_INMSEL_2 (0x4UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00040000 */
20353#define COMP_CFGRx_INPSEL_Pos (20U)
20354#define COMP_CFGRx_INPSEL_Msk (0x1UL << COMP_CFGRx_INPSEL_Pos) /*!< 0x00100000 */
20355#define COMP_CFGRx_INPSEL COMP_CFGRx_INPSEL_Msk /*!< COMPx input plus selection bit */
20356#define COMP_CFGRx_BLANKING_Pos (24U)
20357#define COMP_CFGRx_BLANKING_Msk (0xFUL << COMP_CFGRx_BLANKING_Pos) /*!< 0x0F000000 */
20358#define COMP_CFGRx_BLANKING COMP_CFGRx_BLANKING_Msk /*!< COMPx blanking source selection bits */
20359#define COMP_CFGRx_BLANKING_0 (0x1UL << COMP_CFGRx_BLANKING_Pos) /*!< 0x01000000 */
20360#define COMP_CFGRx_BLANKING_1 (0x2UL << COMP_CFGRx_BLANKING_Pos) /*!< 0x02000000 */
20361#define COMP_CFGRx_BLANKING_2 (0x4UL << COMP_CFGRx_BLANKING_Pos) /*!< 0x04000000 */
20362#define COMP_CFGRx_LOCK_Pos (31U)
20363#define COMP_CFGRx_LOCK_Msk (0x1UL << COMP_CFGRx_LOCK_Pos) /*!< 0x80000000 */
20364#define COMP_CFGRx_LOCK COMP_CFGRx_LOCK_Msk /*!< COMPx Lock Bit */
20365
20366
20367/******************************************************************************/
20368/* */
20369/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
20370/* */
20371/******************************************************************************/
20372/****************** Bit definition for USART_CR1 register *******************/
20373#define USART_CR1_UE_Pos (0U)
20374#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
20375#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
20376#define USART_CR1_UESM_Pos (1U)
20377#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
20378#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
20379#define USART_CR1_RE_Pos (2U)
20380#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
20381#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
20382#define USART_CR1_TE_Pos (3U)
20383#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
20384#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
20385#define USART_CR1_IDLEIE_Pos (4U)
20386#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
20387#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
20388#define USART_CR1_RXNEIE_RXFNEIE_Pos (5U)
20389#define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
20390#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
20391#define USART_CR1_TCIE_Pos (6U)
20392#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
20393#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
20394#define USART_CR1_TXEIE_TXFNFIE_Pos (7U)
20395#define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */
20396#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk /*!< TXE and TX FIFO Not Full Interrupt Enable */
20397#define USART_CR1_PEIE_Pos (8U)
20398#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
20399#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
20400#define USART_CR1_PS_Pos (9U)
20401#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
20402#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
20403#define USART_CR1_PCE_Pos (10U)
20404#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
20405#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
20406#define USART_CR1_WAKE_Pos (11U)
20407#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
20408#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
20409#define USART_CR1_M_Pos (12U)
20410#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
20411#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
20412#define USART_CR1_M0_Pos (12U)
20413#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
20414#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
20415#define USART_CR1_MME_Pos (13U)
20416#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
20417#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
20418#define USART_CR1_CMIE_Pos (14U)
20419#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
20420#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
20421#define USART_CR1_OVER8_Pos (15U)
20422#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
20423#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
20424#define USART_CR1_DEDT_Pos (16U)
20425#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
20426#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
20427#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
20428#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
20429#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
20430#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
20431#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
20432#define USART_CR1_DEAT_Pos (21U)
20433#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
20434#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
20435#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
20436#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
20437#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
20438#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
20439#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
20440#define USART_CR1_RTOIE_Pos (26U)
20441#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
20442#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
20443#define USART_CR1_EOBIE_Pos (27U)
20444#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
20445#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
20446#define USART_CR1_M1_Pos (28U)
20447#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
20448#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
20449#define USART_CR1_FIFOEN_Pos (29U)
20450#define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
20451#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
20452#define USART_CR1_TXFEIE_Pos (30U)
20453#define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
20454#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */
20455#define USART_CR1_RXFFIE_Pos (31U)
20456#define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
20457#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */
20458
20459/* Legacy define */
20460#define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE
20461#define USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE
20462
20463/****************** Bit definition for USART_CR2 register *******************/
20464#define USART_CR2_SLVEN_Pos (0U)
20465#define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
20466#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode Enable */
20467#define USART_CR2_DIS_NSS_Pos (3U)
20468#define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
20469#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Negative Slave Select (NSS) pin management */
20470#define USART_CR2_ADDM7_Pos (4U)
20471#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
20472#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
20473#define USART_CR2_LBDL_Pos (5U)
20474#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
20475#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
20476#define USART_CR2_LBDIE_Pos (6U)
20477#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
20478#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
20479#define USART_CR2_LBCL_Pos (8U)
20480#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
20481#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
20482#define USART_CR2_CPHA_Pos (9U)
20483#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
20484#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
20485#define USART_CR2_CPOL_Pos (10U)
20486#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
20487#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
20488#define USART_CR2_CLKEN_Pos (11U)
20489#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
20490#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
20491#define USART_CR2_STOP_Pos (12U)
20492#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
20493#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
20494#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
20495#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
20496#define USART_CR2_LINEN_Pos (14U)
20497#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
20498#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
20499#define USART_CR2_SWAP_Pos (15U)
20500#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
20501#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
20502#define USART_CR2_RXINV_Pos (16U)
20503#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
20504#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
20505#define USART_CR2_TXINV_Pos (17U)
20506#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
20507#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
20508#define USART_CR2_DATAINV_Pos (18U)
20509#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
20510#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
20511#define USART_CR2_MSBFIRST_Pos (19U)
20512#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
20513#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
20514#define USART_CR2_ABREN_Pos (20U)
20515#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
20516#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
20517#define USART_CR2_ABRMODE_Pos (21U)
20518#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
20519#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
20520#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
20521#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
20522#define USART_CR2_RTOEN_Pos (23U)
20523#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
20524#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
20525#define USART_CR2_ADD_Pos (24U)
20526#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
20527#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
20528
20529/****************** Bit definition for USART_CR3 register *******************/
20530#define USART_CR3_EIE_Pos (0U)
20531#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
20532#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
20533#define USART_CR3_IREN_Pos (1U)
20534#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
20535#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
20536#define USART_CR3_IRLP_Pos (2U)
20537#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
20538#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
20539#define USART_CR3_HDSEL_Pos (3U)
20540#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
20541#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
20542#define USART_CR3_NACK_Pos (4U)
20543#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
20544#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
20545#define USART_CR3_SCEN_Pos (5U)
20546#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
20547#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
20548#define USART_CR3_DMAR_Pos (6U)
20549#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
20550#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
20551#define USART_CR3_DMAT_Pos (7U)
20552#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
20553#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
20554#define USART_CR3_RTSE_Pos (8U)
20555#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
20556#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
20557#define USART_CR3_CTSE_Pos (9U)
20558#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
20559#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
20560#define USART_CR3_CTSIE_Pos (10U)
20561#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
20562#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
20563#define USART_CR3_ONEBIT_Pos (11U)
20564#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
20565#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
20566#define USART_CR3_OVRDIS_Pos (12U)
20567#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
20568#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
20569#define USART_CR3_DDRE_Pos (13U)
20570#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
20571#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
20572#define USART_CR3_DEM_Pos (14U)
20573#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
20574#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
20575#define USART_CR3_DEP_Pos (15U)
20576#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
20577#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
20578#define USART_CR3_SCARCNT_Pos (17U)
20579#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
20580#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
20581#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
20582#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
20583#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
20584#define USART_CR3_WUS_Pos (20U)
20585#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
20586#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
20587#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
20588#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
20589#define USART_CR3_WUFIE_Pos (22U)
20590#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
20591#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
20592#define USART_CR3_TXFTIE_Pos (23U)
20593#define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */
20594#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */
20595#define USART_CR3_TCBGTIE_Pos (24U)
20596#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
20597#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete before guard time, interrupt enable */
20598#define USART_CR3_RXFTCFG_Pos (25U)
20599#define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
20600#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */
20601#define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
20602#define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
20603#define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
20604#define USART_CR3_RXFTIE_Pos (28U)
20605#define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */
20606#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */
20607#define USART_CR3_TXFTCFG_Pos (29U)
20608#define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
20609#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO [2:0] threshold configuration */
20610#define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
20611#define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
20612#define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
20613
20614/****************** Bit definition for USART_BRR register *******************/
20615#define USART_BRR_DIV_FRACTION_Pos (0U)
20616#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
20617#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
20618#define USART_BRR_DIV_MANTISSA_Pos (4U)
20619#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
20620#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
20621
20622/****************** Bit definition for USART_GTPR register ******************/
20623#define USART_GTPR_PSC_Pos (0U)
20624#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
20625#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
20626#define USART_GTPR_GT_Pos (8U)
20627#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
20628#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
20629
20630/******************* Bit definition for USART_RTOR register *****************/
20631#define USART_RTOR_RTO_Pos (0U)
20632#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
20633#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
20634#define USART_RTOR_BLEN_Pos (24U)
20635#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
20636#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
20637
20638/******************* Bit definition for USART_RQR register ******************/
20639#define USART_RQR_ABRRQ_Pos (0U)
20640#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
20641#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
20642#define USART_RQR_SBKRQ_Pos (1U)
20643#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
20644#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
20645#define USART_RQR_MMRQ_Pos (2U)
20646#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
20647#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
20648#define USART_RQR_RXFRQ_Pos (3U)
20649#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
20650#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
20651#define USART_RQR_TXFRQ_Pos (4U)
20652#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
20653#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
20654
20655/******************* Bit definition for USART_ISR register ******************/
20656#define USART_ISR_PE_Pos (0U)
20657#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
20658#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
20659#define USART_ISR_FE_Pos (1U)
20660#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
20661#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
20662#define USART_ISR_NE_Pos (2U)
20663#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
20664#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
20665#define USART_ISR_ORE_Pos (3U)
20666#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
20667#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
20668#define USART_ISR_IDLE_Pos (4U)
20669#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
20670#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
20671#define USART_ISR_RXNE_RXFNE_Pos (5U)
20672#define USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos) /*!< 0x00000020 */
20673#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk /*!< Read Data Register or RX FIFO Not Empty */
20674#define USART_ISR_TC_Pos (6U)
20675#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
20676#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
20677#define USART_ISR_TXE_TXFNF_Pos (7U)
20678#define USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos) /*!< 0x00000080 */
20679#define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
20680#define USART_ISR_LBDF_Pos (8U)
20681#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
20682#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
20683#define USART_ISR_CTSIF_Pos (9U)
20684#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
20685#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
20686#define USART_ISR_CTS_Pos (10U)
20687#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
20688#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
20689#define USART_ISR_RTOF_Pos (11U)
20690#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
20691#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
20692#define USART_ISR_EOBF_Pos (12U)
20693#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
20694#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
20695#define USART_ISR_UDR_Pos (13U)
20696#define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */
20697#define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI slave underrun error flag */
20698#define USART_ISR_ABRE_Pos (14U)
20699#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
20700#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
20701#define USART_ISR_ABRF_Pos (15U)
20702#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
20703#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
20704#define USART_ISR_BUSY_Pos (16U)
20705#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
20706#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
20707#define USART_ISR_CMF_Pos (17U)
20708#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
20709#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
20710#define USART_ISR_SBKF_Pos (18U)
20711#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
20712#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
20713#define USART_ISR_RWU_Pos (19U)
20714#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
20715#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
20716#define USART_ISR_WUF_Pos (20U)
20717#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
20718#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
20719#define USART_ISR_TEACK_Pos (21U)
20720#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
20721#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
20722#define USART_ISR_REACK_Pos (22U)
20723#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
20724#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
20725#define USART_ISR_TXFE_Pos (23U)
20726#define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
20727#define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty */
20728#define USART_ISR_RXFF_Pos (24U)
20729#define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */
20730#define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full Flag */
20731#define USART_ISR_TCBGT_Pos (25U)
20732#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
20733#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission complete before guard time Flag */
20734#define USART_ISR_RXFT_Pos (26U)
20735#define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
20736#define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO threshold Flag */
20737#define USART_ISR_TXFT_Pos (27U)
20738#define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
20739#define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO threshold Flag */
20740
20741/******************* Bit definition for USART_ICR register ******************/
20742#define USART_ICR_PECF_Pos (0U)
20743#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
20744#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
20745#define USART_ICR_FECF_Pos (1U)
20746#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
20747#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
20748#define USART_ICR_NECF_Pos (2U)
20749#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */
20750#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise detected Clear Flag */
20751#define USART_ICR_ORECF_Pos (3U)
20752#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
20753#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
20754#define USART_ICR_IDLECF_Pos (4U)
20755#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
20756#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
20757#define USART_ICR_TXFECF_Pos (5U)
20758#define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
20759#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO empty clear flag */
20760#define USART_ICR_TCCF_Pos (6U)
20761#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
20762#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
20763#define USART_ICR_TCBGTCF_Pos (7U)
20764#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
20765#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission complete before guard time Clear Flag */
20766#define USART_ICR_LBDCF_Pos (8U)
20767#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
20768#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
20769#define USART_ICR_CTSCF_Pos (9U)
20770#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
20771#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
20772#define USART_ICR_RTOCF_Pos (11U)
20773#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
20774#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
20775#define USART_ICR_EOBCF_Pos (12U)
20776#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
20777#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
20778#define USART_ICR_UDRCF_Pos (13U)
20779#define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
20780#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI slave underrun clear flag */
20781#define USART_ICR_CMCF_Pos (17U)
20782#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
20783#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
20784#define USART_ICR_WUCF_Pos (20U)
20785#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
20786#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
20787
20788/******************* Bit definition for USART_RDR register ******************/
20789#define USART_RDR_RDR_Pos (0U)
20790#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
20791#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
20792
20793/******************* Bit definition for USART_TDR register ******************/
20794#define USART_TDR_TDR_Pos (0U)
20795#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
20796#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
20797
20798/******************* Bit definition for USART_PRESC register ******************/
20799#define USART_PRESC_PRESCALER_Pos (0U)
20800#define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
20801#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
20802#define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
20803#define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
20804#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
20805#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
20806
20807/******************************************************************************/
20808/* */
20809/* Single Wire Protocol Master Interface (SWPMI) */
20810/* */
20811/******************************************************************************/
20812
20813/******************* Bit definition for SWPMI_CR register ********************/
20814#define SWPMI_CR_RXDMA_Pos (0U)
20815#define SWPMI_CR_RXDMA_Msk (0x1UL << SWPMI_CR_RXDMA_Pos) /*!< 0x00000001 */
20816#define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk /*!<Reception DMA enable */
20817#define SWPMI_CR_TXDMA_Pos (1U)
20818#define SWPMI_CR_TXDMA_Msk (0x1UL << SWPMI_CR_TXDMA_Pos) /*!< 0x00000002 */
20819#define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk /*!<Transmission DMA enable */
20820#define SWPMI_CR_RXMODE_Pos (2U)
20821#define SWPMI_CR_RXMODE_Msk (0x1UL << SWPMI_CR_RXMODE_Pos) /*!< 0x00000004 */
20822#define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk /*!<Reception buffering mode */
20823#define SWPMI_CR_TXMODE_Pos (3U)
20824#define SWPMI_CR_TXMODE_Msk (0x1UL << SWPMI_CR_TXMODE_Pos) /*!< 0x00000008 */
20825#define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk /*!<Transmission buffering mode */
20826#define SWPMI_CR_LPBK_Pos (4U)
20827#define SWPMI_CR_LPBK_Msk (0x1UL << SWPMI_CR_LPBK_Pos) /*!< 0x00000010 */
20828#define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk /*!<Loopback mode enable */
20829#define SWPMI_CR_SWPACT_Pos (5U)
20830#define SWPMI_CR_SWPACT_Msk (0x1UL << SWPMI_CR_SWPACT_Pos) /*!< 0x00000020 */
20831#define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk /*!<Single wire protocol master interface activate */
20832#define SWPMI_CR_DEACT_Pos (10U)
20833#define SWPMI_CR_DEACT_Msk (0x1UL << SWPMI_CR_DEACT_Pos) /*!< 0x00000400 */
20834#define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk /*!<Single wire protocol master interface deactivate */
20835#define SWPMI_CR_SWPEN_Pos (11U)
20836#define SWPMI_CR_SWPEN_Msk (0x1UL << SWPMI_CR_SWPEN_Pos) /*!< 0x00000800 */
20837#define SWPMI_CR_SWPEN SWPMI_CR_SWPEN_Msk /*!<Single wire protocol master transceiver enable */
20838
20839/******************* Bit definition for SWPMI_BRR register ********************/
20840#define SWPMI_BRR_BR_Pos (0U)
20841#define SWPMI_BRR_BR_Msk (0xFFUL << SWPMI_BRR_BR_Pos) /*!< 0x000000FF */
20842#define SWPMI_BRR_BR SWPMI_BRR_BR_Msk /*!<BR[7:0] bits (Bitrate prescaler) */
20843
20844/******************* Bit definition for SWPMI_ISR register ********************/
20845#define SWPMI_ISR_RXBFF_Pos (0U)
20846#define SWPMI_ISR_RXBFF_Msk (0x1UL << SWPMI_ISR_RXBFF_Pos) /*!< 0x00000001 */
20847#define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk /*!<Receive buffer full flag */
20848#define SWPMI_ISR_TXBEF_Pos (1U)
20849#define SWPMI_ISR_TXBEF_Msk (0x1UL << SWPMI_ISR_TXBEF_Pos) /*!< 0x00000002 */
20850#define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk /*!<Transmit buffer empty flag */
20851#define SWPMI_ISR_RXBERF_Pos (2U)
20852#define SWPMI_ISR_RXBERF_Msk (0x1UL << SWPMI_ISR_RXBERF_Pos) /*!< 0x00000004 */
20853#define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk /*!<Receive CRC error flag */
20854#define SWPMI_ISR_RXOVRF_Pos (3U)
20855#define SWPMI_ISR_RXOVRF_Msk (0x1UL << SWPMI_ISR_RXOVRF_Pos) /*!< 0x00000008 */
20856#define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk /*!<Receive overrun error flag */
20857#define SWPMI_ISR_TXUNRF_Pos (4U)
20858#define SWPMI_ISR_TXUNRF_Msk (0x1UL << SWPMI_ISR_TXUNRF_Pos) /*!< 0x00000010 */
20859#define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk /*!<Transmit underrun error flag */
20860#define SWPMI_ISR_RXNE_Pos (5U)
20861#define SWPMI_ISR_RXNE_Msk (0x1UL << SWPMI_ISR_RXNE_Pos) /*!< 0x00000020 */
20862#define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk /*!<Receive data register not empty */
20863#define SWPMI_ISR_TXE_Pos (6U)
20864#define SWPMI_ISR_TXE_Msk (0x1UL << SWPMI_ISR_TXE_Pos) /*!< 0x00000040 */
20865#define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk /*!<Transmit data register empty */
20866#define SWPMI_ISR_TCF_Pos (7U)
20867#define SWPMI_ISR_TCF_Msk (0x1UL << SWPMI_ISR_TCF_Pos) /*!< 0x00000080 */
20868#define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk /*!<Transfer complete flag */
20869#define SWPMI_ISR_SRF_Pos (8U)
20870#define SWPMI_ISR_SRF_Msk (0x1UL << SWPMI_ISR_SRF_Pos) /*!< 0x00000100 */
20871#define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk /*!<Slave resume flag */
20872#define SWPMI_ISR_SUSP_Pos (9U)
20873#define SWPMI_ISR_SUSP_Msk (0x1UL << SWPMI_ISR_SUSP_Pos) /*!< 0x00000200 */
20874#define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk /*!<SUSPEND flag */
20875#define SWPMI_ISR_DEACTF_Pos (10U)
20876#define SWPMI_ISR_DEACTF_Msk (0x1UL << SWPMI_ISR_DEACTF_Pos) /*!< 0x00000400 */
20877#define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk /*!<DEACTIVATED flag */
20878#define SWPMI_ISR_RDYF_Pos (11U)
20879#define SWPMI_ISR_RDYF_Msk (0x1UL << SWPMI_ISR_RDYF_Pos) /*!< 0x00000800 */
20880#define SWPMI_ISR_RDYF SWPMI_ISR_RDYF_Msk /*!<Transceiver ready flag */
20881
20882/******************* Bit definition for SWPMI_ICR register ********************/
20883#define SWPMI_ICR_CRXBFF_Pos (0U)
20884#define SWPMI_ICR_CRXBFF_Msk (0x1UL << SWPMI_ICR_CRXBFF_Pos) /*!< 0x00000001 */
20885#define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk /*!<Clear receive buffer full flag */
20886#define SWPMI_ICR_CTXBEF_Pos (1U)
20887#define SWPMI_ICR_CTXBEF_Msk (0x1UL << SWPMI_ICR_CTXBEF_Pos) /*!< 0x00000002 */
20888#define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk /*!<Clear transmit buffer empty flag */
20889#define SWPMI_ICR_CRXBERF_Pos (2U)
20890#define SWPMI_ICR_CRXBERF_Msk (0x1UL << SWPMI_ICR_CRXBERF_Pos) /*!< 0x00000004 */
20891#define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk /*!<Clear receive CRC error flag */
20892#define SWPMI_ICR_CRXOVRF_Pos (3U)
20893#define SWPMI_ICR_CRXOVRF_Msk (0x1UL << SWPMI_ICR_CRXOVRF_Pos) /*!< 0x00000008 */
20894#define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk /*!<Clear receive overrun error flag */
20895#define SWPMI_ICR_CTXUNRF_Pos (4U)
20896#define SWPMI_ICR_CTXUNRF_Msk (0x1UL << SWPMI_ICR_CTXUNRF_Pos) /*!< 0x00000010 */
20897#define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk /*!<Clear transmit underrun error flag */
20898#define SWPMI_ICR_CTCF_Pos (7U)
20899#define SWPMI_ICR_CTCF_Msk (0x1UL << SWPMI_ICR_CTCF_Pos) /*!< 0x00000080 */
20900#define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk /*!<Clear transfer complete flag */
20901#define SWPMI_ICR_CSRF_Pos (8U)
20902#define SWPMI_ICR_CSRF_Msk (0x1UL << SWPMI_ICR_CSRF_Pos) /*!< 0x00000100 */
20903#define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk /*!<Clear slave resume flag */
20904#define SWPMI_ICR_CRDYF_Pos (11U)
20905#define SWPMI_ICR_CRDYF_Msk (0x1UL << SWPMI_ICR_CRDYF_Pos) /*!< 0x00000800 */
20906#define SWPMI_ICR_CRDYF SWPMI_ICR_CRDYF_Msk /*!<Clear transceiver ready flag */
20907
20908/******************* Bit definition for SWPMI_IER register ********************/
20909#define SWPMI_IER_RXBFIE_Pos (0U)
20910#define SWPMI_IER_RXBFIE_Msk (0x1UL << SWPMI_IER_RXBFIE_Pos) /*!< 0x00000001 */
20911#define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk /*!<Receive buffer full interrupt enable */
20912#define SWPMI_IER_TXBEIE_Pos (1U)
20913#define SWPMI_IER_TXBEIE_Msk (0x1UL << SWPMI_IER_TXBEIE_Pos) /*!< 0x00000002 */
20914#define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk /*!<Transmit buffer empty interrupt enable */
20915#define SWPMI_IER_RXBERIE_Pos (2U)
20916#define SWPMI_IER_RXBERIE_Msk (0x1UL << SWPMI_IER_RXBERIE_Pos) /*!< 0x00000004 */
20917#define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk /*!<Receive CRC error interrupt enable */
20918#define SWPMI_IER_RXOVRIE_Pos (3U)
20919#define SWPMI_IER_RXOVRIE_Msk (0x1UL << SWPMI_IER_RXOVRIE_Pos) /*!< 0x00000008 */
20920#define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk /*!<Receive overrun error interrupt enable */
20921#define SWPMI_IER_TXUNRIE_Pos (4U)
20922#define SWPMI_IER_TXUNRIE_Msk (0x1UL << SWPMI_IER_TXUNRIE_Pos) /*!< 0x00000010 */
20923#define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk /*!<Transmit underrun error interrupt enable */
20924#define SWPMI_IER_RIE_Pos (5U)
20925#define SWPMI_IER_RIE_Msk (0x1UL << SWPMI_IER_RIE_Pos) /*!< 0x00000020 */
20926#define SWPMI_IER_RIE SWPMI_IER_RIE_Msk /*!<Receive interrupt enable */
20927#define SWPMI_IER_TIE_Pos (6U)
20928#define SWPMI_IER_TIE_Msk (0x1UL << SWPMI_IER_TIE_Pos) /*!< 0x00000040 */
20929#define SWPMI_IER_TIE SWPMI_IER_TIE_Msk /*!<Transmit interrupt enable */
20930#define SWPMI_IER_TCIE_Pos (7U)
20931#define SWPMI_IER_TCIE_Msk (0x1UL << SWPMI_IER_TCIE_Pos) /*!< 0x00000080 */
20932#define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk /*!<Transmit complete interrupt enable */
20933#define SWPMI_IER_SRIE_Pos (8U)
20934#define SWPMI_IER_SRIE_Msk (0x1UL << SWPMI_IER_SRIE_Pos) /*!< 0x00000100 */
20935#define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk /*!<Slave resume interrupt enable */
20936#define SWPMI_IER_RDYIE_Pos (11U)
20937#define SWPMI_IER_RDYIE_Msk (0x1UL << SWPMI_IER_RDYIE_Pos) /*!< 0x00000800 */
20938#define SWPMI_IER_RDYIE SWPMI_IER_RDYIE_Msk /*!<Transceiver ready interrupt enable */
20939
20940/******************* Bit definition for SWPMI_RFL register ********************/
20941#define SWPMI_RFL_RFL_Pos (0U)
20942#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
20943#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
20944#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
20945
20946/******************* Bit definition for SWPMI_TDR register ********************/
20947#define SWPMI_TDR_TD_Pos (0U)
20948#define SWPMI_TDR_TD_Msk (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos) /*!< 0xFFFFFFFF */
20949#define SWPMI_TDR_TD SWPMI_TDR_TD_Msk /*!<Transmit Data Register */
20950
20951/******************* Bit definition for SWPMI_RDR register ********************/
20952#define SWPMI_RDR_RD_Pos (0U)
20953#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
20954#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
20955
20956
20957/******************* Bit definition for SWPMI_OR register ********************/
20958#define SWPMI_OR_TBYP_Pos (0U)
20959#define SWPMI_OR_TBYP_Msk (0x1UL << SWPMI_OR_TBYP_Pos) /*!< 0x00000001 */
20960#define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk /*!<SWP Transceiver Bypass */
20961#define SWPMI_OR_CLASS_Pos (1U)
20962#define SWPMI_OR_CLASS_Msk (0x1UL << SWPMI_OR_CLASS_Pos) /*!< 0x00000002 */
20963#define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk /*!<SWP CLASS selection */
20964
20965/******************************************************************************/
20966/* */
20967/* Window WATCHDOG */
20968/* */
20969/******************************************************************************/
20970/******************* Bit definition for WWDG_CR register ********************/
20971#define WWDG_CR_T_Pos (0U)
20972#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
20973#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
20974#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
20975#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
20976#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
20977#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
20978#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
20979#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
20980#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
20981
20982#define WWDG_CR_WDGA_Pos (7U)
20983#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
20984#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
20985
20986/******************* Bit definition for WWDG_CFR register *******************/
20987#define WWDG_CFR_W_Pos (0U)
20988#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
20989#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
20990#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
20991#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
20992#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
20993#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
20994#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
20995#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
20996#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
20997
20998#define WWDG_CFR_EWI_Pos (9U)
20999#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
21000#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
21001
21002#define WWDG_CFR_WDGTB_Pos (11U)
21003#define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */
21004#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */
21005#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */
21006#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */
21007#define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */
21008
21009/******************* Bit definition for WWDG_SR register ********************/
21010#define WWDG_SR_EWIF_Pos (0U)
21011#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
21012#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
21013
21014
21015/******************************************************************************/
21016/* */
21017/* DBG */
21018/* */
21019/******************************************************************************/
21020
21021/******************** Bit definition for DBGMCU_IDCODE register *************/
21022#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
21023#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
21024#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
21025#define DBGMCU_IDCODE_REV_ID_Pos (16U)
21026#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
21027#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
21028
21029/******************** Bit definition for DBGMCU_CR register *****************/
21030#define DBGMCU_CR_DBG_SLEEPD1_Pos (0U)
21031#define DBGMCU_CR_DBG_SLEEPD1_Msk (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos) /*!< 0x00000001 */
21032#define DBGMCU_CR_DBG_SLEEPD1 DBGMCU_CR_DBG_SLEEPD1_Msk
21033#define DBGMCU_CR_DBG_STOPD1_Pos (1U)
21034#define DBGMCU_CR_DBG_STOPD1_Msk (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos) /*!< 0x00000002 */
21035#define DBGMCU_CR_DBG_STOPD1 DBGMCU_CR_DBG_STOPD1_Msk
21036#define DBGMCU_CR_DBG_STANDBYD1_Pos (2U)
21037#define DBGMCU_CR_DBG_STANDBYD1_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */
21038#define DBGMCU_CR_DBG_STANDBYD1 DBGMCU_CR_DBG_STANDBYD1_Msk
21039#define DBGMCU_CR_DBG_STOPD3_Pos (7U)
21040#define DBGMCU_CR_DBG_STOPD3_Msk (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos) /*!< 0x00000080 */
21041#define DBGMCU_CR_DBG_STOPD3 DBGMCU_CR_DBG_STOPD3_Msk
21042#define DBGMCU_CR_DBG_STANDBYD3_Pos (8U)
21043#define DBGMCU_CR_DBG_STANDBYD3_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */
21044#define DBGMCU_CR_DBG_STANDBYD3 DBGMCU_CR_DBG_STANDBYD3_Msk
21045#define DBGMCU_CR_DBG_TRACECKEN_Pos (20U)
21046#define DBGMCU_CR_DBG_TRACECKEN_Msk (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */
21047#define DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk
21048#define DBGMCU_CR_DBG_CKD1EN_Pos (21U)
21049#define DBGMCU_CR_DBG_CKD1EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos) /*!< 0x00200000 */
21050#define DBGMCU_CR_DBG_CKD1EN DBGMCU_CR_DBG_CKD1EN_Msk
21051#define DBGMCU_CR_DBG_CKD3EN_Pos (22U)
21052#define DBGMCU_CR_DBG_CKD3EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos) /*!< 0x00400000 */
21053#define DBGMCU_CR_DBG_CKD3EN DBGMCU_CR_DBG_CKD3EN_Msk
21054#define DBGMCU_CR_DBG_TRGOEN_Pos (28U)
21055#define DBGMCU_CR_DBG_TRGOEN_Msk (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos) /*!< 0x10000000 */
21056#define DBGMCU_CR_DBG_TRGOEN DBGMCU_CR_DBG_TRGOEN_Msk
21057
21058/******************** Bit definition for APB3FZ1 register ************/
21059#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos (6U)
21060#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */
21061#define DBGMCU_APB3FZ1_DBG_WWDG1 DBGMCU_APB3FZ1_DBG_WWDG1_Msk
21062/******************** Bit definition for APB1LFZ1 register ************/
21063#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos (0U)
21064#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */
21065#define DBGMCU_APB1LFZ1_DBG_TIM2 DBGMCU_APB1LFZ1_DBG_TIM2_Msk
21066#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos (1U)
21067#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */
21068#define DBGMCU_APB1LFZ1_DBG_TIM3 DBGMCU_APB1LFZ1_DBG_TIM3_Msk
21069#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos (2U)
21070#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */
21071#define DBGMCU_APB1LFZ1_DBG_TIM4 DBGMCU_APB1LFZ1_DBG_TIM4_Msk
21072#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos (3U)
21073#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */
21074#define DBGMCU_APB1LFZ1_DBG_TIM5 DBGMCU_APB1LFZ1_DBG_TIM5_Msk
21075#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos (4U)
21076#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */
21077#define DBGMCU_APB1LFZ1_DBG_TIM6 DBGMCU_APB1LFZ1_DBG_TIM6_Msk
21078#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos (5U)
21079#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */
21080#define DBGMCU_APB1LFZ1_DBG_TIM7 DBGMCU_APB1LFZ1_DBG_TIM7_Msk
21081#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos (6U)
21082#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */
21083#define DBGMCU_APB1LFZ1_DBG_TIM12 DBGMCU_APB1LFZ1_DBG_TIM12_Msk
21084#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos (7U)
21085#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */
21086#define DBGMCU_APB1LFZ1_DBG_TIM13 DBGMCU_APB1LFZ1_DBG_TIM13_Msk
21087#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos (8U)
21088#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */
21089#define DBGMCU_APB1LFZ1_DBG_TIM14 DBGMCU_APB1LFZ1_DBG_TIM14_Msk
21090#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos (9U)
21091#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */
21092#define DBGMCU_APB1LFZ1_DBG_LPTIM1 DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk
21093#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos (21U)
21094#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */
21095#define DBGMCU_APB1LFZ1_DBG_I2C1 DBGMCU_APB1LFZ1_DBG_I2C1_Msk
21096#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos (22U)
21097#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */
21098#define DBGMCU_APB1LFZ1_DBG_I2C2 DBGMCU_APB1LFZ1_DBG_I2C2_Msk
21099#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos (23U)
21100#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */
21101#define DBGMCU_APB1LFZ1_DBG_I2C3 DBGMCU_APB1LFZ1_DBG_I2C3_Msk
21102
21103/******************** Bit definition for APB1HFZ1 register ************/
21104#define DBGMCU_APB1HFZ1_DBG_FDCAN_Pos (8U)
21105#define DBGMCU_APB1HFZ1_DBG_FDCAN_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos) /*!< 0x00000100 */
21106#define DBGMCU_APB1HFZ1_DBG_FDCAN DBGMCU_APB1HFZ1_DBG_FDCAN_Msk
21107/******************** Bit definition for APB2FZ1 register ************/
21108#define DBGMCU_APB2FZ1_DBG_TIM1_Pos (0U)
21109#define DBGMCU_APB2FZ1_DBG_TIM1_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */
21110#define DBGMCU_APB2FZ1_DBG_TIM1 DBGMCU_APB2FZ1_DBG_TIM1_Msk
21111#define DBGMCU_APB2FZ1_DBG_TIM8_Pos (1U)
21112#define DBGMCU_APB2FZ1_DBG_TIM8_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */
21113#define DBGMCU_APB2FZ1_DBG_TIM8 DBGMCU_APB2FZ1_DBG_TIM8_Msk
21114#define DBGMCU_APB2FZ1_DBG_TIM15_Pos (16U)
21115#define DBGMCU_APB2FZ1_DBG_TIM15_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */
21116#define DBGMCU_APB2FZ1_DBG_TIM15 DBGMCU_APB2FZ1_DBG_TIM15_Msk
21117#define DBGMCU_APB2FZ1_DBG_TIM16_Pos (17U)
21118#define DBGMCU_APB2FZ1_DBG_TIM16_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */
21119#define DBGMCU_APB2FZ1_DBG_TIM16 DBGMCU_APB2FZ1_DBG_TIM16_Msk
21120#define DBGMCU_APB2FZ1_DBG_TIM17_Pos (18U)
21121#define DBGMCU_APB2FZ1_DBG_TIM17_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */
21122#define DBGMCU_APB2FZ1_DBG_TIM17 DBGMCU_APB2FZ1_DBG_TIM17_Msk
21123#define DBGMCU_APB2FZ1_DBG_HRTIM_Pos (29U)
21124#define DBGMCU_APB2FZ1_DBG_HRTIM_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos) /*!< 0x20000000 */
21125#define DBGMCU_APB2FZ1_DBG_HRTIM DBGMCU_APB2FZ1_DBG_HRTIM_Msk
21126
21127/******************** Bit definition for APB4FZ1 register ************/
21128#define DBGMCU_APB4FZ1_DBG_I2C4_Pos (7U)
21129#define DBGMCU_APB4FZ1_DBG_I2C4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */
21130#define DBGMCU_APB4FZ1_DBG_I2C4 DBGMCU_APB4FZ1_DBG_I2C4_Msk
21131#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos (9U)
21132#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */
21133#define DBGMCU_APB4FZ1_DBG_LPTIM2 DBGMCU_APB4FZ1_DBG_LPTIM2_Msk
21134#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos (10U)
21135#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */
21136#define DBGMCU_APB4FZ1_DBG_LPTIM3 DBGMCU_APB4FZ1_DBG_LPTIM3_Msk
21137#define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos (11U)
21138#define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) /*!< 0x00000800 */
21139#define DBGMCU_APB4FZ1_DBG_LPTIM4 DBGMCU_APB4FZ1_DBG_LPTIM4_Msk
21140#define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos (12U)
21141#define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) /*!< 0x00001000 */
21142#define DBGMCU_APB4FZ1_DBG_LPTIM5 DBGMCU_APB4FZ1_DBG_LPTIM5_Msk
21143#define DBGMCU_APB4FZ1_DBG_RTC_Pos (16U)
21144#define DBGMCU_APB4FZ1_DBG_RTC_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */
21145#define DBGMCU_APB4FZ1_DBG_RTC DBGMCU_APB4FZ1_DBG_RTC_Msk
21146#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos (18U)
21147#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */
21148#define DBGMCU_APB4FZ1_DBG_IWDG1 DBGMCU_APB4FZ1_DBG_IWDG1_Msk
21149/******************************************************************************/
21150/* */
21151/* High Resolution Timer (HRTIM) */
21152/* */
21153/******************************************************************************/
21154/******************** Master Timer control register ***************************/
21155#define HRTIM_MCR_CK_PSC_Pos (0U)
21156#define HRTIM_MCR_CK_PSC_Msk (0x7UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000007 */
21157#define HRTIM_MCR_CK_PSC HRTIM_MCR_CK_PSC_Msk /*!< Prescaler mask */
21158#define HRTIM_MCR_CK_PSC_0 (0x1UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000001 */
21159#define HRTIM_MCR_CK_PSC_1 (0x2UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000002 */
21160#define HRTIM_MCR_CK_PSC_2 (0x4UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000004 */
21161
21162#define HRTIM_MCR_CONT_Pos (3U)
21163#define HRTIM_MCR_CONT_Msk (0x1UL << HRTIM_MCR_CONT_Pos) /*!< 0x00000008 */
21164#define HRTIM_MCR_CONT HRTIM_MCR_CONT_Msk /*!< Continuous mode */
21165#define HRTIM_MCR_RETRIG_Pos (4U)
21166#define HRTIM_MCR_RETRIG_Msk (0x1UL << HRTIM_MCR_RETRIG_Pos) /*!< 0x00000010 */
21167#define HRTIM_MCR_RETRIG HRTIM_MCR_RETRIG_Msk /*!< Rettrigreable mode */
21168#define HRTIM_MCR_HALF_Pos (5U)
21169#define HRTIM_MCR_HALF_Msk (0x1UL << HRTIM_MCR_HALF_Pos) /*!< 0x00000020 */
21170#define HRTIM_MCR_HALF HRTIM_MCR_HALF_Msk /*!< Half mode */
21171
21172#define HRTIM_MCR_SYNC_IN_Pos (8U)
21173#define HRTIM_MCR_SYNC_IN_Msk (0x3UL << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000300 */
21174#define HRTIM_MCR_SYNC_IN HRTIM_MCR_SYNC_IN_Msk /*!< Synchronization input master */
21175#define HRTIM_MCR_SYNC_IN_0 (0x1UL << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000100 */
21176#define HRTIM_MCR_SYNC_IN_1 (0x2UL << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000200 */
21177#define HRTIM_MCR_SYNCRSTM_Pos (10U)
21178#define HRTIM_MCR_SYNCRSTM_Msk (0x1UL << HRTIM_MCR_SYNCRSTM_Pos) /*!< 0x00000400 */
21179#define HRTIM_MCR_SYNCRSTM HRTIM_MCR_SYNCRSTM_Msk /*!< Synchronization reset master */
21180#define HRTIM_MCR_SYNCSTRTM_Pos (11U)
21181#define HRTIM_MCR_SYNCSTRTM_Msk (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos) /*!< 0x00000800 */
21182#define HRTIM_MCR_SYNCSTRTM HRTIM_MCR_SYNCSTRTM_Msk /*!< Synchronization start master */
21183#define HRTIM_MCR_SYNC_OUT_Pos (12U)
21184#define HRTIM_MCR_SYNC_OUT_Msk (0x3UL << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00003000 */
21185#define HRTIM_MCR_SYNC_OUT HRTIM_MCR_SYNC_OUT_Msk /*!< Synchronization output master */
21186#define HRTIM_MCR_SYNC_OUT_0 (0x1UL << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00001000 */
21187#define HRTIM_MCR_SYNC_OUT_1 (0x2UL << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00002000 */
21188#define HRTIM_MCR_SYNC_SRC_Pos (14U)
21189#define HRTIM_MCR_SYNC_SRC_Msk (0x3UL << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x0000C000 */
21190#define HRTIM_MCR_SYNC_SRC HRTIM_MCR_SYNC_SRC_Msk /*!< Synchronization source */
21191#define HRTIM_MCR_SYNC_SRC_0 (0x1UL << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x00004000 */
21192#define HRTIM_MCR_SYNC_SRC_1 (0x2UL << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x00008000 */
21193
21194#define HRTIM_MCR_MCEN_Pos (16U)
21195#define HRTIM_MCR_MCEN_Msk (0x1UL << HRTIM_MCR_MCEN_Pos) /*!< 0x00010000 */
21196#define HRTIM_MCR_MCEN HRTIM_MCR_MCEN_Msk /*!< Master counter enable */
21197#define HRTIM_MCR_TACEN_Pos (17U)
21198#define HRTIM_MCR_TACEN_Msk (0x1UL << HRTIM_MCR_TACEN_Pos) /*!< 0x00020000 */
21199#define HRTIM_MCR_TACEN HRTIM_MCR_TACEN_Msk /*!< Timer A counter enable */
21200#define HRTIM_MCR_TBCEN_Pos (18U)
21201#define HRTIM_MCR_TBCEN_Msk (0x1UL << HRTIM_MCR_TBCEN_Pos) /*!< 0x00040000 */
21202#define HRTIM_MCR_TBCEN HRTIM_MCR_TBCEN_Msk /*!< Timer B counter enable */
21203#define HRTIM_MCR_TCCEN_Pos (19U)
21204#define HRTIM_MCR_TCCEN_Msk (0x1UL << HRTIM_MCR_TCCEN_Pos) /*!< 0x00080000 */
21205#define HRTIM_MCR_TCCEN HRTIM_MCR_TCCEN_Msk /*!< Timer C counter enable */
21206#define HRTIM_MCR_TDCEN_Pos (20U)
21207#define HRTIM_MCR_TDCEN_Msk (0x1UL << HRTIM_MCR_TDCEN_Pos) /*!< 0x00100000 */
21208#define HRTIM_MCR_TDCEN HRTIM_MCR_TDCEN_Msk /*!< Timer D counter enable */
21209#define HRTIM_MCR_TECEN_Pos (21U)
21210#define HRTIM_MCR_TECEN_Msk (0x1UL << HRTIM_MCR_TECEN_Pos) /*!< 0x00200000 */
21211#define HRTIM_MCR_TECEN HRTIM_MCR_TECEN_Msk /*!< Timer E counter enable */
21212
21213#define HRTIM_MCR_DACSYNC_Pos (25U)
21214#define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */
21215#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */
21216#define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */
21217#define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */
21218
21219#define HRTIM_MCR_PREEN_Pos (27U)
21220#define HRTIM_MCR_PREEN_Msk (0x1UL << HRTIM_MCR_PREEN_Pos) /*!< 0x08000000 */
21221#define HRTIM_MCR_PREEN HRTIM_MCR_PREEN_Msk /*!< Master preload enable */
21222#define HRTIM_MCR_MREPU_Pos (29U)
21223#define HRTIM_MCR_MREPU_Msk (0x1UL << HRTIM_MCR_MREPU_Pos) /*!< 0x20000000 */
21224#define HRTIM_MCR_MREPU HRTIM_MCR_MREPU_Msk /*!< Master repetition update */
21225
21226#define HRTIM_MCR_BRSTDMA_Pos (30U)
21227#define HRTIM_MCR_BRSTDMA_Msk (0x3UL << HRTIM_MCR_BRSTDMA_Pos) /*!< 0xC0000000 */
21228#define HRTIM_MCR_BRSTDMA HRTIM_MCR_BRSTDMA_Msk /*!< Burst DMA update */
21229#define HRTIM_MCR_BRSTDMA_0 (0x1UL << HRTIM_MCR_BRSTDMA_Pos) /*!< 0x40000000 */
21230#define HRTIM_MCR_BRSTDMA_1 (0x2UL << HRTIM_MCR_BRSTDMA_Pos) /*!< 0x80000000 */
21231
21232/******************** Master Timer Interrupt status register ******************/
21233#define HRTIM_MISR_MCMP1_Pos (0U)
21234#define HRTIM_MISR_MCMP1_Msk (0x1UL << HRTIM_MISR_MCMP1_Pos) /*!< 0x00000001 */
21235#define HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1_Msk /*!< Master compare 1 interrupt flag */
21236#define HRTIM_MISR_MCMP2_Pos (1U)
21237#define HRTIM_MISR_MCMP2_Msk (0x1UL << HRTIM_MISR_MCMP2_Pos) /*!< 0x00000002 */
21238#define HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2_Msk /*!< Master compare 2 interrupt flag */
21239#define HRTIM_MISR_MCMP3_Pos (2U)
21240#define HRTIM_MISR_MCMP3_Msk (0x1UL << HRTIM_MISR_MCMP3_Pos) /*!< 0x00000004 */
21241#define HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3_Msk /*!< Master compare 3 interrupt flag */
21242#define HRTIM_MISR_MCMP4_Pos (3U)
21243#define HRTIM_MISR_MCMP4_Msk (0x1UL << HRTIM_MISR_MCMP4_Pos) /*!< 0x00000008 */
21244#define HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4_Msk /*!< Master compare 4 interrupt flag */
21245#define HRTIM_MISR_MREP_Pos (4U)
21246#define HRTIM_MISR_MREP_Msk (0x1UL << HRTIM_MISR_MREP_Pos) /*!< 0x00000010 */
21247#define HRTIM_MISR_MREP HRTIM_MISR_MREP_Msk /*!< Master Repetition interrupt flag */
21248#define HRTIM_MISR_SYNC_Pos (5U)
21249#define HRTIM_MISR_SYNC_Msk (0x1UL << HRTIM_MISR_SYNC_Pos) /*!< 0x00000020 */
21250#define HRTIM_MISR_SYNC HRTIM_MISR_SYNC_Msk /*!< Synchronization input interrupt flag */
21251#define HRTIM_MISR_MUPD_Pos (6U)
21252#define HRTIM_MISR_MUPD_Msk (0x1UL << HRTIM_MISR_MUPD_Pos) /*!< 0x00000040 */
21253#define HRTIM_MISR_MUPD HRTIM_MISR_MUPD_Msk /*!< Master update interrupt flag */
21254
21255/******************** Master Timer Interrupt clear register *******************/
21256#define HRTIM_MICR_MCMP1_Pos (0U)
21257#define HRTIM_MICR_MCMP1_Msk (0x1UL << HRTIM_MICR_MCMP1_Pos) /*!< 0x00000001 */
21258#define HRTIM_MICR_MCMP1 HRTIM_MICR_MCMP1_Msk /*!< Master compare 1 interrupt flag clear */
21259#define HRTIM_MICR_MCMP2_Pos (1U)
21260#define HRTIM_MICR_MCMP2_Msk (0x1UL << HRTIM_MICR_MCMP2_Pos) /*!< 0x00000002 */
21261#define HRTIM_MICR_MCMP2 HRTIM_MICR_MCMP2_Msk /*!< Master compare 2 interrupt flag clear */
21262#define HRTIM_MICR_MCMP3_Pos (2U)
21263#define HRTIM_MICR_MCMP3_Msk (0x1UL << HRTIM_MICR_MCMP3_Pos) /*!< 0x00000004 */
21264#define HRTIM_MICR_MCMP3 HRTIM_MICR_MCMP3_Msk /*!< Master compare 3 interrupt flag clear */
21265#define HRTIM_MICR_MCMP4_Pos (3U)
21266#define HRTIM_MICR_MCMP4_Msk (0x1UL << HRTIM_MICR_MCMP4_Pos) /*!< 0x00000008 */
21267#define HRTIM_MICR_MCMP4 HRTIM_MICR_MCMP4_Msk /*!< Master compare 4 interrupt flag clear */
21268#define HRTIM_MICR_MREP_Pos (4U)
21269#define HRTIM_MICR_MREP_Msk (0x1UL << HRTIM_MICR_MREP_Pos) /*!< 0x00000010 */
21270#define HRTIM_MICR_MREP HRTIM_MICR_MREP_Msk /*!< Master Repetition interrupt flag clear */
21271#define HRTIM_MICR_SYNC_Pos (5U)
21272#define HRTIM_MICR_SYNC_Msk (0x1UL << HRTIM_MICR_SYNC_Pos) /*!< 0x00000020 */
21273#define HRTIM_MICR_SYNC HRTIM_MICR_SYNC_Msk /*!< Synchronization input interrupt flag clear */
21274#define HRTIM_MICR_MUPD_Pos (6U)
21275#define HRTIM_MICR_MUPD_Msk (0x1UL << HRTIM_MICR_MUPD_Pos) /*!< 0x00000040 */
21276#define HRTIM_MICR_MUPD HRTIM_MICR_MUPD_Msk /*!< Master update interrupt flag clear */
21277
21278/******************** Master Timer DMA/Interrupt enable register **************/
21279#define HRTIM_MDIER_MCMP1IE_Pos (0U)
21280#define HRTIM_MDIER_MCMP1IE_Msk (0x1UL << HRTIM_MDIER_MCMP1IE_Pos) /*!< 0x00000001 */
21281#define HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE_Msk /*!< Master compare 1 interrupt enable */
21282#define HRTIM_MDIER_MCMP2IE_Pos (1U)
21283#define HRTIM_MDIER_MCMP2IE_Msk (0x1UL << HRTIM_MDIER_MCMP2IE_Pos) /*!< 0x00000002 */
21284#define HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE_Msk /*!< Master compare 2 interrupt enable */
21285#define HRTIM_MDIER_MCMP3IE_Pos (2U)
21286#define HRTIM_MDIER_MCMP3IE_Msk (0x1UL << HRTIM_MDIER_MCMP3IE_Pos) /*!< 0x00000004 */
21287#define HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE_Msk /*!< Master compare 3 interrupt enable */
21288#define HRTIM_MDIER_MCMP4IE_Pos (3U)
21289#define HRTIM_MDIER_MCMP4IE_Msk (0x1UL << HRTIM_MDIER_MCMP4IE_Pos) /*!< 0x00000008 */
21290#define HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE_Msk /*!< Master compare 4 interrupt enable */
21291#define HRTIM_MDIER_MREPIE_Pos (4U)
21292#define HRTIM_MDIER_MREPIE_Msk (0x1UL << HRTIM_MDIER_MREPIE_Pos) /*!< 0x00000010 */
21293#define HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE_Msk /*!< Master Repetition interrupt enable */
21294#define HRTIM_MDIER_SYNCIE_Pos (5U)
21295#define HRTIM_MDIER_SYNCIE_Msk (0x1UL << HRTIM_MDIER_SYNCIE_Pos) /*!< 0x00000020 */
21296#define HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE_Msk /*!< Synchronization input interrupt enable */
21297#define HRTIM_MDIER_MUPDIE_Pos (6U)
21298#define HRTIM_MDIER_MUPDIE_Msk (0x1UL << HRTIM_MDIER_MUPDIE_Pos) /*!< 0x00000040 */
21299#define HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE_Msk /*!< Master update interrupt enable */
21300
21301#define HRTIM_MDIER_MCMP1DE_Pos (16U)
21302#define HRTIM_MDIER_MCMP1DE_Msk (0x1UL << HRTIM_MDIER_MCMP1DE_Pos) /*!< 0x00010000 */
21303#define HRTIM_MDIER_MCMP1DE HRTIM_MDIER_MCMP1DE_Msk /*!< Master compare 1 DMA enable */
21304#define HRTIM_MDIER_MCMP2DE_Pos (17U)
21305#define HRTIM_MDIER_MCMP2DE_Msk (0x1UL << HRTIM_MDIER_MCMP2DE_Pos) /*!< 0x00020000 */
21306#define HRTIM_MDIER_MCMP2DE HRTIM_MDIER_MCMP2DE_Msk /*!< Master compare 2 DMA enable */
21307#define HRTIM_MDIER_MCMP3DE_Pos (18U)
21308#define HRTIM_MDIER_MCMP3DE_Msk (0x1UL << HRTIM_MDIER_MCMP3DE_Pos) /*!< 0x00040000 */
21309#define HRTIM_MDIER_MCMP3DE HRTIM_MDIER_MCMP3DE_Msk /*!< Master compare 3 DMA enable */
21310#define HRTIM_MDIER_MCMP4DE_Pos (19U)
21311#define HRTIM_MDIER_MCMP4DE_Msk (0x1UL << HRTIM_MDIER_MCMP4DE_Pos) /*!< 0x00080000 */
21312#define HRTIM_MDIER_MCMP4DE HRTIM_MDIER_MCMP4DE_Msk /*!< Master compare 4 DMA enable */
21313#define HRTIM_MDIER_MREPDE_Pos (20U)
21314#define HRTIM_MDIER_MREPDE_Msk (0x1UL << HRTIM_MDIER_MREPDE_Pos) /*!< 0x00100000 */
21315#define HRTIM_MDIER_MREPDE HRTIM_MDIER_MREPDE_Msk /*!< Master Repetition DMA enable */
21316#define HRTIM_MDIER_SYNCDE_Pos (21U)
21317#define HRTIM_MDIER_SYNCDE_Msk (0x1UL << HRTIM_MDIER_SYNCDE_Pos) /*!< 0x00200000 */
21318#define HRTIM_MDIER_SYNCDE HRTIM_MDIER_SYNCDE_Msk /*!< Synchronization input DMA enable */
21319#define HRTIM_MDIER_MUPDDE_Pos (22U)
21320#define HRTIM_MDIER_MUPDDE_Msk (0x1UL << HRTIM_MDIER_MUPDDE_Pos) /*!< 0x00400000 */
21321#define HRTIM_MDIER_MUPDDE HRTIM_MDIER_MUPDDE_Msk /*!< Master update DMA enable */
21322
21323/******************* Bit definition for HRTIM_MCNTR register ****************/
21324#define HRTIM_MCNTR_MCNTR_Pos (0U)
21325#define HRTIM_MCNTR_MCNTR_Msk (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos) /*!< 0x0000FFFF */
21326#define HRTIM_MCNTR_MCNTR HRTIM_MCNTR_MCNTR_Msk /*!<Counter Value */
21327
21328/******************* Bit definition for HRTIM_MPER register *****************/
21329#define HRTIM_MPER_MPER_Pos (0U)
21330#define HRTIM_MPER_MPER_Msk (0xFFFFUL << HRTIM_MPER_MPER_Pos) /*!< 0x0000FFFF */
21331#define HRTIM_MPER_MPER HRTIM_MPER_MPER_Msk /*!< Period Value */
21332
21333/******************* Bit definition for HRTIM_MREP register *****************/
21334#define HRTIM_MREP_MREP_Pos (0U)
21335#define HRTIM_MREP_MREP_Msk (0xFFUL << HRTIM_MREP_MREP_Pos) /*!< 0x000000FF */
21336#define HRTIM_MREP_MREP HRTIM_MREP_MREP_Msk /*!<Repetition Value */
21337
21338/******************* Bit definition for HRTIM_MCMP1R register *****************/
21339#define HRTIM_MCMP1R_MCMP1R_Pos (0U)
21340#define HRTIM_MCMP1R_MCMP1R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos) /*!< 0x0000FFFF */
21341#define HRTIM_MCMP1R_MCMP1R HRTIM_MCMP1R_MCMP1R_Msk /*!<Compare Value */
21342
21343/******************* Bit definition for HRTIM_MCMP2R register *****************/
21344#define HRTIM_MCMP1R_MCMP2R_Pos (0U)
21345#define HRTIM_MCMP1R_MCMP2R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos) /*!< 0x0000FFFF */
21346#define HRTIM_MCMP1R_MCMP2R HRTIM_MCMP1R_MCMP2R_Msk /*!<Compare Value */
21347
21348/******************* Bit definition for HRTIM_MCMP3R register *****************/
21349#define HRTIM_MCMP1R_MCMP3R_Pos (0U)
21350#define HRTIM_MCMP1R_MCMP3R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos) /*!< 0x0000FFFF */
21351#define HRTIM_MCMP1R_MCMP3R HRTIM_MCMP1R_MCMP3R_Msk /*!<Compare Value */
21352
21353/******************* Bit definition for HRTIM_MCMP4R register *****************/
21354#define HRTIM_MCMP1R_MCMP4R_Pos (0U)
21355#define HRTIM_MCMP1R_MCMP4R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos) /*!< 0x0000FFFF */
21356#define HRTIM_MCMP1R_MCMP4R HRTIM_MCMP1R_MCMP4R_Msk /*!<Compare Value */
21357
21358/******************** Slave control register **********************************/
21359#define HRTIM_TIMCR_CK_PSC_Pos (0U)
21360#define HRTIM_TIMCR_CK_PSC_Msk (0x7UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000007 */
21361#define HRTIM_TIMCR_CK_PSC HRTIM_TIMCR_CK_PSC_Msk /*!< Slave prescaler mask*/
21362#define HRTIM_TIMCR_CK_PSC_0 (0x1UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000001 */
21363#define HRTIM_TIMCR_CK_PSC_1 (0x2UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000002 */
21364#define HRTIM_TIMCR_CK_PSC_2 (0x4UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000004 */
21365
21366#define HRTIM_TIMCR_CONT_Pos (3U)
21367#define HRTIM_TIMCR_CONT_Msk (0x1UL << HRTIM_TIMCR_CONT_Pos) /*!< 0x00000008 */
21368#define HRTIM_TIMCR_CONT HRTIM_TIMCR_CONT_Msk /*!< Slave continuous mode */
21369#define HRTIM_TIMCR_RETRIG_Pos (4U)
21370#define HRTIM_TIMCR_RETRIG_Msk (0x1UL << HRTIM_TIMCR_RETRIG_Pos) /*!< 0x00000010 */
21371#define HRTIM_TIMCR_RETRIG HRTIM_TIMCR_RETRIG_Msk /*!< Slave Retrigreable mode */
21372#define HRTIM_TIMCR_HALF_Pos (5U)
21373#define HRTIM_TIMCR_HALF_Msk (0x1UL << HRTIM_TIMCR_HALF_Pos) /*!< 0x00000020 */
21374#define HRTIM_TIMCR_HALF HRTIM_TIMCR_HALF_Msk /*!< Slave Half mode */
21375#define HRTIM_TIMCR_PSHPLL_Pos (6U)
21376#define HRTIM_TIMCR_PSHPLL_Msk (0x1UL << HRTIM_TIMCR_PSHPLL_Pos) /*!< 0x00000040 */
21377#define HRTIM_TIMCR_PSHPLL HRTIM_TIMCR_PSHPLL_Msk /*!< Slave push-pull mode */
21378
21379#define HRTIM_TIMCR_SYNCRST_Pos (10U)
21380#define HRTIM_TIMCR_SYNCRST_Msk (0x1UL << HRTIM_TIMCR_SYNCRST_Pos) /*!< 0x00000400 */
21381#define HRTIM_TIMCR_SYNCRST HRTIM_TIMCR_SYNCRST_Msk /*!< Slave synchronization resets */
21382#define HRTIM_TIMCR_SYNCSTRT_Pos (11U)
21383#define HRTIM_TIMCR_SYNCSTRT_Msk (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos) /*!< 0x00000800 */
21384#define HRTIM_TIMCR_SYNCSTRT HRTIM_TIMCR_SYNCSTRT_Msk /*!< Slave synchronization starts */
21385
21386#define HRTIM_TIMCR_DELCMP2_Pos (12U)
21387#define HRTIM_TIMCR_DELCMP2_Msk (0x3UL << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00003000 */
21388#define HRTIM_TIMCR_DELCMP2 HRTIM_TIMCR_DELCMP2_Msk /*!< Slave delayed compartor 2 mode mask */
21389#define HRTIM_TIMCR_DELCMP2_0 (0x1UL << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00001000 */
21390#define HRTIM_TIMCR_DELCMP2_1 (0x2UL << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00002000 */
21391#define HRTIM_TIMCR_DELCMP4_Pos (14U)
21392#define HRTIM_TIMCR_DELCMP4_Msk (0x3UL << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x0000C000 */
21393#define HRTIM_TIMCR_DELCMP4 HRTIM_TIMCR_DELCMP4_Msk /*!< Slave delayed compartor 4 mode mask */
21394#define HRTIM_TIMCR_DELCMP4_0 (0x1UL << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x00004000 */
21395#define HRTIM_TIMCR_DELCMP4_1 (0x2UL << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x00008000 */
21396
21397#define HRTIM_TIMCR_TREPU_Pos (17U)
21398#define HRTIM_TIMCR_TREPU_Msk (0x1UL << HRTIM_TIMCR_TREPU_Pos) /*!< 0x00020000 */
21399#define HRTIM_TIMCR_TREPU HRTIM_TIMCR_TREPU_Msk /*!< Slave repetition update */
21400#define HRTIM_TIMCR_TRSTU_Pos (18U)
21401#define HRTIM_TIMCR_TRSTU_Msk (0x1UL << HRTIM_TIMCR_TRSTU_Pos) /*!< 0x00040000 */
21402#define HRTIM_TIMCR_TRSTU HRTIM_TIMCR_TRSTU_Msk /*!< Slave reset update */
21403#define HRTIM_TIMCR_TAU_Pos (19U)
21404#define HRTIM_TIMCR_TAU_Msk (0x1UL << HRTIM_TIMCR_TAU_Pos) /*!< 0x00080000 */
21405#define HRTIM_TIMCR_TAU HRTIM_TIMCR_TAU_Msk /*!< Slave Timer A update reserved for TIM A */
21406#define HRTIM_TIMCR_TBU_Pos (20U)
21407#define HRTIM_TIMCR_TBU_Msk (0x1UL << HRTIM_TIMCR_TBU_Pos) /*!< 0x00100000 */
21408#define HRTIM_TIMCR_TBU HRTIM_TIMCR_TBU_Msk /*!< Slave Timer B update reserved for TIM B */
21409#define HRTIM_TIMCR_TCU_Pos (21U)
21410#define HRTIM_TIMCR_TCU_Msk (0x1UL << HRTIM_TIMCR_TCU_Pos) /*!< 0x00200000 */
21411#define HRTIM_TIMCR_TCU HRTIM_TIMCR_TCU_Msk /*!< Slave Timer C update reserved for TIM C */
21412#define HRTIM_TIMCR_TDU_Pos (22U)
21413#define HRTIM_TIMCR_TDU_Msk (0x1UL << HRTIM_TIMCR_TDU_Pos) /*!< 0x00400000 */
21414#define HRTIM_TIMCR_TDU HRTIM_TIMCR_TDU_Msk /*!< Slave Timer D update reserved for TIM D */
21415#define HRTIM_TIMCR_TEU_Pos (23U)
21416#define HRTIM_TIMCR_TEU_Msk (0x1UL << HRTIM_TIMCR_TEU_Pos) /*!< 0x00800000 */
21417#define HRTIM_TIMCR_TEU HRTIM_TIMCR_TEU_Msk /*!< Slave Timer E update reserved for TIM E */
21418#define HRTIM_TIMCR_MSTU_Pos (24U)
21419#define HRTIM_TIMCR_MSTU_Msk (0x1UL << HRTIM_TIMCR_MSTU_Pos) /*!< 0x01000000 */
21420#define HRTIM_TIMCR_MSTU HRTIM_TIMCR_MSTU_Msk /*!< Master Update */
21421
21422#define HRTIM_TIMCR_DACSYNC_Pos (25U)
21423#define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */
21424#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */
21425#define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */
21426#define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */
21427#define HRTIM_TIMCR_PREEN_Pos (27U)
21428#define HRTIM_TIMCR_PREEN_Msk (0x1UL << HRTIM_TIMCR_PREEN_Pos) /*!< 0x08000000 */
21429#define HRTIM_TIMCR_PREEN HRTIM_TIMCR_PREEN_Msk /*!< Slave preload enable */
21430
21431#define HRTIM_TIMCR_UPDGAT_Pos (28U)
21432#define HRTIM_TIMCR_UPDGAT_Msk (0xFUL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0xF0000000 */
21433#define HRTIM_TIMCR_UPDGAT HRTIM_TIMCR_UPDGAT_Msk /*!< Slave update gating mask */
21434#define HRTIM_TIMCR_UPDGAT_0 (0x1UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x10000000 */
21435#define HRTIM_TIMCR_UPDGAT_1 (0x2UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x20000000 */
21436#define HRTIM_TIMCR_UPDGAT_2 (0x4UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x40000000 */
21437#define HRTIM_TIMCR_UPDGAT_3 (0x8UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x80000000 */
21438
21439/******************** Slave Interrupt status register **************************/
21440#define HRTIM_TIMISR_CMP1_Pos (0U)
21441#define HRTIM_TIMISR_CMP1_Msk (0x1UL << HRTIM_TIMISR_CMP1_Pos) /*!< 0x00000001 */
21442#define HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1_Msk /*!< Slave compare 1 interrupt flag */
21443#define HRTIM_TIMISR_CMP2_Pos (1U)
21444#define HRTIM_TIMISR_CMP2_Msk (0x1UL << HRTIM_TIMISR_CMP2_Pos) /*!< 0x00000002 */
21445#define HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2_Msk /*!< Slave compare 2 interrupt flag */
21446#define HRTIM_TIMISR_CMP3_Pos (2U)
21447#define HRTIM_TIMISR_CMP3_Msk (0x1UL << HRTIM_TIMISR_CMP3_Pos) /*!< 0x00000004 */
21448#define HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3_Msk /*!< Slave compare 3 interrupt flag */
21449#define HRTIM_TIMISR_CMP4_Pos (3U)
21450#define HRTIM_TIMISR_CMP4_Msk (0x1UL << HRTIM_TIMISR_CMP4_Pos) /*!< 0x00000008 */
21451#define HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4_Msk /*!< Slave compare 4 interrupt flag */
21452#define HRTIM_TIMISR_REP_Pos (4U)
21453#define HRTIM_TIMISR_REP_Msk (0x1UL << HRTIM_TIMISR_REP_Pos) /*!< 0x00000010 */
21454#define HRTIM_TIMISR_REP HRTIM_TIMISR_REP_Msk /*!< Slave repetition interrupt flag */
21455#define HRTIM_TIMISR_UPD_Pos (6U)
21456#define HRTIM_TIMISR_UPD_Msk (0x1UL << HRTIM_TIMISR_UPD_Pos) /*!< 0x00000040 */
21457#define HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD_Msk /*!< Slave update interrupt flag */
21458#define HRTIM_TIMISR_CPT1_Pos (7U)
21459#define HRTIM_TIMISR_CPT1_Msk (0x1UL << HRTIM_TIMISR_CPT1_Pos) /*!< 0x00000080 */
21460#define HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1_Msk /*!< Slave capture 1 interrupt flag */
21461#define HRTIM_TIMISR_CPT2_Pos (8U)
21462#define HRTIM_TIMISR_CPT2_Msk (0x1UL << HRTIM_TIMISR_CPT2_Pos) /*!< 0x00000100 */
21463#define HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2_Msk /*!< Slave capture 2 interrupt flag */
21464#define HRTIM_TIMISR_SET1_Pos (9U)
21465#define HRTIM_TIMISR_SET1_Msk (0x1UL << HRTIM_TIMISR_SET1_Pos) /*!< 0x00000200 */
21466#define HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1_Msk /*!< Slave output 1 set interrupt flag */
21467#define HRTIM_TIMISR_RST1_Pos (10U)
21468#define HRTIM_TIMISR_RST1_Msk (0x1UL << HRTIM_TIMISR_RST1_Pos) /*!< 0x00000400 */
21469#define HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1_Msk /*!< Slave output 1 reset interrupt flag */
21470#define HRTIM_TIMISR_SET2_Pos (11U)
21471#define HRTIM_TIMISR_SET2_Msk (0x1UL << HRTIM_TIMISR_SET2_Pos) /*!< 0x00000800 */
21472#define HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2_Msk /*!< Slave output 2 set interrupt flag */
21473#define HRTIM_TIMISR_RST2_Pos (12U)
21474#define HRTIM_TIMISR_RST2_Msk (0x1UL << HRTIM_TIMISR_RST2_Pos) /*!< 0x00001000 */
21475#define HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2_Msk /*!< Slave output 2 reset interrupt flag */
21476#define HRTIM_TIMISR_RST_Pos (13U)
21477#define HRTIM_TIMISR_RST_Msk (0x1UL << HRTIM_TIMISR_RST_Pos) /*!< 0x00002000 */
21478#define HRTIM_TIMISR_RST HRTIM_TIMISR_RST_Msk /*!< Slave reset interrupt flag */
21479#define HRTIM_TIMISR_DLYPRT_Pos (14U)
21480#define HRTIM_TIMISR_DLYPRT_Msk (0x1UL << HRTIM_TIMISR_DLYPRT_Pos) /*!< 0x00004000 */
21481#define HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT_Msk /*!< Slave output 1 delay protection interrupt flag */
21482#define HRTIM_TIMISR_CPPSTAT_Pos (16U)
21483#define HRTIM_TIMISR_CPPSTAT_Msk (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos) /*!< 0x00010000 */
21484#define HRTIM_TIMISR_CPPSTAT HRTIM_TIMISR_CPPSTAT_Msk /*!< Slave current push-pull flag */
21485#define HRTIM_TIMISR_IPPSTAT_Pos (17U)
21486#define HRTIM_TIMISR_IPPSTAT_Msk (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos) /*!< 0x00020000 */
21487#define HRTIM_TIMISR_IPPSTAT HRTIM_TIMISR_IPPSTAT_Msk /*!< Slave idle push-pull flag */
21488#define HRTIM_TIMISR_O1STAT_Pos (18U)
21489#define HRTIM_TIMISR_O1STAT_Msk (0x1UL << HRTIM_TIMISR_O1STAT_Pos) /*!< 0x00040000 */
21490#define HRTIM_TIMISR_O1STAT HRTIM_TIMISR_O1STAT_Msk /*!< Slave output 1 state flag */
21491#define HRTIM_TIMISR_O2STAT_Pos (19U)
21492#define HRTIM_TIMISR_O2STAT_Msk (0x1UL << HRTIM_TIMISR_O2STAT_Pos) /*!< 0x00080000 */
21493#define HRTIM_TIMISR_O2STAT HRTIM_TIMISR_O2STAT_Msk /*!< Slave output 2 state flag */
21494#define HRTIM_TIMISR_O1CPY_Pos (20U)
21495#define HRTIM_TIMISR_O1CPY_Msk (0x1UL << HRTIM_TIMISR_O1CPY_Pos) /*!< 0x00100000 */
21496#define HRTIM_TIMISR_O1CPY HRTIM_TIMISR_O1CPY_Msk /*!< Slave output 1 copy flag */
21497#define HRTIM_TIMISR_O2CPY_Pos (21U)
21498#define HRTIM_TIMISR_O2CPY_Msk (0x1UL << HRTIM_TIMISR_O2CPY_Pos) /*!< 0x00200000 */
21499#define HRTIM_TIMISR_O2CPY HRTIM_TIMISR_O2CPY_Msk /*!< Slave output 2 copy flag */
21500
21501/******************** Slave Interrupt clear register **************************/
21502#define HRTIM_TIMICR_CMP1C_Pos (0U)
21503#define HRTIM_TIMICR_CMP1C_Msk (0x1UL << HRTIM_TIMICR_CMP1C_Pos) /*!< 0x00000001 */
21504#define HRTIM_TIMICR_CMP1C HRTIM_TIMICR_CMP1C_Msk /*!< Slave compare 1 clear flag */
21505#define HRTIM_TIMICR_CMP2C_Pos (1U)
21506#define HRTIM_TIMICR_CMP2C_Msk (0x1UL << HRTIM_TIMICR_CMP2C_Pos) /*!< 0x00000002 */
21507#define HRTIM_TIMICR_CMP2C HRTIM_TIMICR_CMP2C_Msk /*!< Slave compare 2 clear flag */
21508#define HRTIM_TIMICR_CMP3C_Pos (2U)
21509#define HRTIM_TIMICR_CMP3C_Msk (0x1UL << HRTIM_TIMICR_CMP3C_Pos) /*!< 0x00000004 */
21510#define HRTIM_TIMICR_CMP3C HRTIM_TIMICR_CMP3C_Msk /*!< Slave compare 3 clear flag */
21511#define HRTIM_TIMICR_CMP4C_Pos (3U)
21512#define HRTIM_TIMICR_CMP4C_Msk (0x1UL << HRTIM_TIMICR_CMP4C_Pos) /*!< 0x00000008 */
21513#define HRTIM_TIMICR_CMP4C HRTIM_TIMICR_CMP4C_Msk /*!< Slave compare 4 clear flag */
21514#define HRTIM_TIMICR_REPC_Pos (4U)
21515#define HRTIM_TIMICR_REPC_Msk (0x1UL << HRTIM_TIMICR_REPC_Pos) /*!< 0x00000010 */
21516#define HRTIM_TIMICR_REPC HRTIM_TIMICR_REPC_Msk /*!< Slave repetition clear flag */
21517#define HRTIM_TIMICR_UPDC_Pos (6U)
21518#define HRTIM_TIMICR_UPDC_Msk (0x1UL << HRTIM_TIMICR_UPDC_Pos) /*!< 0x00000040 */
21519#define HRTIM_TIMICR_UPDC HRTIM_TIMICR_UPDC_Msk /*!< Slave update clear flag */
21520#define HRTIM_TIMICR_CPT1C_Pos (7U)
21521#define HRTIM_TIMICR_CPT1C_Msk (0x1UL << HRTIM_TIMICR_CPT1C_Pos) /*!< 0x00000080 */
21522#define HRTIM_TIMICR_CPT1C HRTIM_TIMICR_CPT1C_Msk /*!< Slave capture 1 clear flag */
21523#define HRTIM_TIMICR_CPT2C_Pos (8U)
21524#define HRTIM_TIMICR_CPT2C_Msk (0x1UL << HRTIM_TIMICR_CPT2C_Pos) /*!< 0x00000100 */
21525#define HRTIM_TIMICR_CPT2C HRTIM_TIMICR_CPT2C_Msk /*!< Slave capture 2 clear flag */
21526#define HRTIM_TIMICR_SET1C_Pos (9U)
21527#define HRTIM_TIMICR_SET1C_Msk (0x1UL << HRTIM_TIMICR_SET1C_Pos) /*!< 0x00000200 */
21528#define HRTIM_TIMICR_SET1C HRTIM_TIMICR_SET1C_Msk /*!< Slave output 1 set clear flag */
21529#define HRTIM_TIMICR_RST1C_Pos (10U)
21530#define HRTIM_TIMICR_RST1C_Msk (0x1UL << HRTIM_TIMICR_RST1C_Pos) /*!< 0x00000400 */
21531#define HRTIM_TIMICR_RST1C HRTIM_TIMICR_RST1C_Msk /*!< Slave output 1 reset clear flag */
21532#define HRTIM_TIMICR_SET2C_Pos (11U)
21533#define HRTIM_TIMICR_SET2C_Msk (0x1UL << HRTIM_TIMICR_SET2C_Pos) /*!< 0x00000800 */
21534#define HRTIM_TIMICR_SET2C HRTIM_TIMICR_SET2C_Msk /*!< Slave output 2 set clear flag */
21535#define HRTIM_TIMICR_RST2C_Pos (12U)
21536#define HRTIM_TIMICR_RST2C_Msk (0x1UL << HRTIM_TIMICR_RST2C_Pos) /*!< 0x00001000 */
21537#define HRTIM_TIMICR_RST2C HRTIM_TIMICR_RST2C_Msk /*!< Slave output 2 reset clear flag */
21538#define HRTIM_TIMICR_RSTC_Pos (13U)
21539#define HRTIM_TIMICR_RSTC_Msk (0x1UL << HRTIM_TIMICR_RSTC_Pos) /*!< 0x00002000 */
21540#define HRTIM_TIMICR_RSTC HRTIM_TIMICR_RSTC_Msk /*!< Slave reset clear flag */
21541#define HRTIM_TIMICR_DLYPRTC_Pos (14U)
21542#define HRTIM_TIMICR_DLYPRTC_Msk (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos) /*!< 0x00004000 */
21543#define HRTIM_TIMICR_DLYPRTC HRTIM_TIMICR_DLYPRTC_Msk /*!< Slave output 1 delay protection clear flag */
21544
21545/******************** Slave DMA/Interrupt enable register *********************/
21546#define HRTIM_TIMDIER_CMP1IE_Pos (0U)
21547#define HRTIM_TIMDIER_CMP1IE_Msk (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos) /*!< 0x00000001 */
21548#define HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE_Msk /*!< Slave compare 1 interrupt enable */
21549#define HRTIM_TIMDIER_CMP2IE_Pos (1U)
21550#define HRTIM_TIMDIER_CMP2IE_Msk (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos) /*!< 0x00000002 */
21551#define HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE_Msk /*!< Slave compare 2 interrupt enable */
21552#define HRTIM_TIMDIER_CMP3IE_Pos (2U)
21553#define HRTIM_TIMDIER_CMP3IE_Msk (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos) /*!< 0x00000004 */
21554#define HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE_Msk /*!< Slave compare 3 interrupt enable */
21555#define HRTIM_TIMDIER_CMP4IE_Pos (3U)
21556#define HRTIM_TIMDIER_CMP4IE_Msk (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos) /*!< 0x00000008 */
21557#define HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE_Msk /*!< Slave compare 4 interrupt enable */
21558#define HRTIM_TIMDIER_REPIE_Pos (4U)
21559#define HRTIM_TIMDIER_REPIE_Msk (0x1UL << HRTIM_TIMDIER_REPIE_Pos) /*!< 0x00000010 */
21560#define HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE_Msk /*!< Slave repetition interrupt enable */
21561#define HRTIM_TIMDIER_UPDIE_Pos (6U)
21562#define HRTIM_TIMDIER_UPDIE_Msk (0x1UL << HRTIM_TIMDIER_UPDIE_Pos) /*!< 0x00000040 */
21563#define HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE_Msk /*!< Slave update interrupt enable */
21564#define HRTIM_TIMDIER_CPT1IE_Pos (7U)
21565#define HRTIM_TIMDIER_CPT1IE_Msk (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos) /*!< 0x00000080 */
21566#define HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE_Msk /*!< Slave capture 1 interrupt enable */
21567#define HRTIM_TIMDIER_CPT2IE_Pos (8U)
21568#define HRTIM_TIMDIER_CPT2IE_Msk (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos) /*!< 0x00000100 */
21569#define HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE_Msk /*!< Slave capture 2 interrupt enable */
21570#define HRTIM_TIMDIER_SET1IE_Pos (9U)
21571#define HRTIM_TIMDIER_SET1IE_Msk (0x1UL << HRTIM_TIMDIER_SET1IE_Pos) /*!< 0x00000200 */
21572#define HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE_Msk /*!< Slave output 1 set interrupt enable */
21573#define HRTIM_TIMDIER_RST1IE_Pos (10U)
21574#define HRTIM_TIMDIER_RST1IE_Msk (0x1UL << HRTIM_TIMDIER_RST1IE_Pos) /*!< 0x00000400 */
21575#define HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE_Msk /*!< Slave output 1 reset interrupt enable */
21576#define HRTIM_TIMDIER_SET2IE_Pos (11U)
21577#define HRTIM_TIMDIER_SET2IE_Msk (0x1UL << HRTIM_TIMDIER_SET2IE_Pos) /*!< 0x00000800 */
21578#define HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE_Msk /*!< Slave output 2 set interrupt enable */
21579#define HRTIM_TIMDIER_RST2IE_Pos (12U)
21580#define HRTIM_TIMDIER_RST2IE_Msk (0x1UL << HRTIM_TIMDIER_RST2IE_Pos) /*!< 0x00001000 */
21581#define HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE_Msk /*!< Slave output 2 reset interrupt enable */
21582#define HRTIM_TIMDIER_RSTIE_Pos (13U)
21583#define HRTIM_TIMDIER_RSTIE_Msk (0x1UL << HRTIM_TIMDIER_RSTIE_Pos) /*!< 0x00002000 */
21584#define HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE_Msk /*!< Slave reset interrupt enable */
21585#define HRTIM_TIMDIER_DLYPRTIE_Pos (14U)
21586#define HRTIM_TIMDIER_DLYPRTIE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos) /*!< 0x00004000 */
21587#define HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE_Msk /*!< Slave delay protection interrupt enable */
21588
21589#define HRTIM_TIMDIER_CMP1DE_Pos (16U)
21590#define HRTIM_TIMDIER_CMP1DE_Msk (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos) /*!< 0x00010000 */
21591#define HRTIM_TIMDIER_CMP1DE HRTIM_TIMDIER_CMP1DE_Msk /*!< Slave compare 1 request enable */
21592#define HRTIM_TIMDIER_CMP2DE_Pos (17U)
21593#define HRTIM_TIMDIER_CMP2DE_Msk (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos) /*!< 0x00020000 */
21594#define HRTIM_TIMDIER_CMP2DE HRTIM_TIMDIER_CMP2DE_Msk /*!< Slave compare 2 request enable */
21595#define HRTIM_TIMDIER_CMP3DE_Pos (18U)
21596#define HRTIM_TIMDIER_CMP3DE_Msk (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos) /*!< 0x00040000 */
21597#define HRTIM_TIMDIER_CMP3DE HRTIM_TIMDIER_CMP3DE_Msk /*!< Slave compare 3 request enable */
21598#define HRTIM_TIMDIER_CMP4DE_Pos (19U)
21599#define HRTIM_TIMDIER_CMP4DE_Msk (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos) /*!< 0x00080000 */
21600#define HRTIM_TIMDIER_CMP4DE HRTIM_TIMDIER_CMP4DE_Msk /*!< Slave compare 4 request enable */
21601#define HRTIM_TIMDIER_REPDE_Pos (20U)
21602#define HRTIM_TIMDIER_REPDE_Msk (0x1UL << HRTIM_TIMDIER_REPDE_Pos) /*!< 0x00100000 */
21603#define HRTIM_TIMDIER_REPDE HRTIM_TIMDIER_REPDE_Msk /*!< Slave repetition request enable */
21604#define HRTIM_TIMDIER_UPDDE_Pos (22U)
21605#define HRTIM_TIMDIER_UPDDE_Msk (0x1UL << HRTIM_TIMDIER_UPDDE_Pos) /*!< 0x00400000 */
21606#define HRTIM_TIMDIER_UPDDE HRTIM_TIMDIER_UPDDE_Msk /*!< Slave update request enable */
21607#define HRTIM_TIMDIER_CPT1DE_Pos (23U)
21608#define HRTIM_TIMDIER_CPT1DE_Msk (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos) /*!< 0x00800000 */
21609#define HRTIM_TIMDIER_CPT1DE HRTIM_TIMDIER_CPT1DE_Msk /*!< Slave capture 1 request enable */
21610#define HRTIM_TIMDIER_CPT2DE_Pos (24U)
21611#define HRTIM_TIMDIER_CPT2DE_Msk (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos) /*!< 0x01000000 */
21612#define HRTIM_TIMDIER_CPT2DE HRTIM_TIMDIER_CPT2DE_Msk /*!< Slave capture 2 request enable */
21613#define HRTIM_TIMDIER_SET1DE_Pos (25U)
21614#define HRTIM_TIMDIER_SET1DE_Msk (0x1UL << HRTIM_TIMDIER_SET1DE_Pos) /*!< 0x02000000 */
21615#define HRTIM_TIMDIER_SET1DE HRTIM_TIMDIER_SET1DE_Msk /*!< Slave output 1 set request enable */
21616#define HRTIM_TIMDIER_RST1DE_Pos (26U)
21617#define HRTIM_TIMDIER_RST1DE_Msk (0x1UL << HRTIM_TIMDIER_RST1DE_Pos) /*!< 0x04000000 */
21618#define HRTIM_TIMDIER_RST1DE HRTIM_TIMDIER_RST1DE_Msk /*!< Slave output 1 reset request enable */
21619#define HRTIM_TIMDIER_SET2DE_Pos (27U)
21620#define HRTIM_TIMDIER_SET2DE_Msk (0x1UL << HRTIM_TIMDIER_SET2DE_Pos) /*!< 0x08000000 */
21621#define HRTIM_TIMDIER_SET2DE HRTIM_TIMDIER_SET2DE_Msk /*!< Slave output 2 set request enable */
21622#define HRTIM_TIMDIER_RST2DE_Pos (28U)
21623#define HRTIM_TIMDIER_RST2DE_Msk (0x1UL << HRTIM_TIMDIER_RST2DE_Pos) /*!< 0x10000000 */
21624#define HRTIM_TIMDIER_RST2DE HRTIM_TIMDIER_RST2DE_Msk /*!< Slave output 2 reset request enable */
21625#define HRTIM_TIMDIER_RSTDE_Pos (29U)
21626#define HRTIM_TIMDIER_RSTDE_Msk (0x1UL << HRTIM_TIMDIER_RSTDE_Pos) /*!< 0x20000000 */
21627#define HRTIM_TIMDIER_RSTDE HRTIM_TIMDIER_RSTDE_Msk /*!< Slave reset request enable */
21628#define HRTIM_TIMDIER_DLYPRTDE_Pos (30U)
21629#define HRTIM_TIMDIER_DLYPRTDE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos) /*!< 0x40000000 */
21630#define HRTIM_TIMDIER_DLYPRTDE HRTIM_TIMDIER_DLYPRTDE_Msk /*!< Slavedelay protection request enable */
21631
21632/****************** Bit definition for HRTIM_CNTR register ****************/
21633#define HRTIM_CNTR_CNTR_Pos (0U)
21634#define HRTIM_CNTR_CNTR_Msk (0xFFFFUL << HRTIM_CNTR_CNTR_Pos) /*!< 0x0000FFFF */
21635#define HRTIM_CNTR_CNTR HRTIM_CNTR_CNTR_Msk /*!< Counter Value */
21636
21637/******************* Bit definition for HRTIM_PER register *****************/
21638#define HRTIM_PER_PER_Pos (0U)
21639#define HRTIM_PER_PER_Msk (0xFFFFUL << HRTIM_PER_PER_Pos) /*!< 0x0000FFFF */
21640#define HRTIM_PER_PER HRTIM_PER_PER_Msk /*!< Period Value */
21641
21642/******************* Bit definition for HRTIM_REP register *****************/
21643#define HRTIM_REP_REP_Pos (0U)
21644#define HRTIM_REP_REP_Msk (0xFFUL << HRTIM_REP_REP_Pos) /*!< 0x000000FF */
21645#define HRTIM_REP_REP HRTIM_REP_REP_Msk /*!< Repetition Value */
21646
21647/******************* Bit definition for HRTIM_CMP1R register *****************/
21648#define HRTIM_CMP1R_CMP1R_Pos (0U)
21649#define HRTIM_CMP1R_CMP1R_Msk (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos) /*!< 0x0000FFFF */
21650#define HRTIM_CMP1R_CMP1R HRTIM_CMP1R_CMP1R_Msk /*!< Compare Value */
21651
21652/******************* Bit definition for HRTIM_CMP1CR register *****************/
21653#define HRTIM_CMP1CR_CMP1CR_Pos (0U)
21654#define HRTIM_CMP1CR_CMP1CR_Msk (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos) /*!< 0xFFFFFFFF */
21655#define HRTIM_CMP1CR_CMP1CR HRTIM_CMP1CR_CMP1CR_Msk /*!< Compare Value */
21656
21657/******************* Bit definition for HRTIM_CMP2R register *****************/
21658#define HRTIM_CMP2R_CMP2R_Pos (0U)
21659#define HRTIM_CMP2R_CMP2R_Msk (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos) /*!< 0x0000FFFF */
21660#define HRTIM_CMP2R_CMP2R HRTIM_CMP2R_CMP2R_Msk /*!< Compare Value */
21661
21662/******************* Bit definition for HRTIM_CMP3R register *****************/
21663#define HRTIM_CMP3R_CMP3R_Pos (0U)
21664#define HRTIM_CMP3R_CMP3R_Msk (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos) /*!< 0x0000FFFF */
21665#define HRTIM_CMP3R_CMP3R HRTIM_CMP3R_CMP3R_Msk /*!< Compare Value */
21666
21667/******************* Bit definition for HRTIM_CMP4R register *****************/
21668#define HRTIM_CMP4R_CMP4R_Pos (0U)
21669#define HRTIM_CMP4R_CMP4R_Msk (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos) /*!< 0x0000FFFF */
21670#define HRTIM_CMP4R_CMP4R HRTIM_CMP4R_CMP4R_Msk /*!< Compare Value */
21671
21672/******************* Bit definition for HRTIM_CPT1R register ****************/
21673#define HRTIM_CPT1R_CPT1R_Pos (0U)
21674#define HRTIM_CPT1R_CPT1R_Msk (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos) /*!< 0x0000FFFF */
21675#define HRTIM_CPT1R_CPT1R HRTIM_CPT1R_CPT1R_Msk /*!< Capture Value */
21676
21677/******************* Bit definition for HRTIM_CPT2R register ****************/
21678#define HRTIM_CPT2R_CPT2R_Pos (0U)
21679#define HRTIM_CPT2R_CPT2R_Msk (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos) /*!< 0x0000FFFF */
21680#define HRTIM_CPT2R_CPT2R HRTIM_CPT2R_CPT2R_Msk /*!< Capture Value */
21681
21682/******************** Bit definition for Slave Deadtime register **************/
21683#define HRTIM_DTR_DTR_Pos (0U)
21684#define HRTIM_DTR_DTR_Msk (0x1FFUL << HRTIM_DTR_DTR_Pos) /*!< 0x000001FF */
21685#define HRTIM_DTR_DTR HRTIM_DTR_DTR_Msk /*!< Dead time rising value */
21686#define HRTIM_DTR_DTR_0 (0x001UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000001 */
21687#define HRTIM_DTR_DTR_1 (0x002UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000002 */
21688#define HRTIM_DTR_DTR_2 (0x004UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000004 */
21689#define HRTIM_DTR_DTR_3 (0x008UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000008 */
21690#define HRTIM_DTR_DTR_4 (0x010UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000010 */
21691#define HRTIM_DTR_DTR_5 (0x020UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000020 */
21692#define HRTIM_DTR_DTR_6 (0x040UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000040 */
21693#define HRTIM_DTR_DTR_7 (0x080UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000080 */
21694#define HRTIM_DTR_DTR_8 (0x100UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000100 */
21695#define HRTIM_DTR_SDTR_Pos (9U)
21696#define HRTIM_DTR_SDTR_Msk (0x1UL << HRTIM_DTR_SDTR_Pos) /*!< 0x00000200 */
21697#define HRTIM_DTR_SDTR HRTIM_DTR_SDTR_Msk /*!< Sign dead time rising value */
21698#define HRTIM_DTR_DTPRSC_Pos (10U)
21699#define HRTIM_DTR_DTPRSC_Msk (0x7UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001C00 */
21700#define HRTIM_DTR_DTPRSC HRTIM_DTR_DTPRSC_Msk /*!< Dead time prescaler */
21701#define HRTIM_DTR_DTPRSC_0 (0x1UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000400 */
21702#define HRTIM_DTR_DTPRSC_1 (0x2UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000800 */
21703#define HRTIM_DTR_DTPRSC_2 (0x4UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001000 */
21704#define HRTIM_DTR_DTRSLK_Pos (14U)
21705#define HRTIM_DTR_DTRSLK_Msk (0x1UL << HRTIM_DTR_DTRSLK_Pos) /*!< 0x00004000 */
21706#define HRTIM_DTR_DTRSLK HRTIM_DTR_DTRSLK_Msk /*!< Dead time rising sign lock */
21707#define HRTIM_DTR_DTRLK_Pos (15U)
21708#define HRTIM_DTR_DTRLK_Msk (0x1UL << HRTIM_DTR_DTRLK_Pos) /*!< 0x00008000 */
21709#define HRTIM_DTR_DTRLK HRTIM_DTR_DTRLK_Msk /*!< Dead time rising lock */
21710#define HRTIM_DTR_DTF_Pos (16U)
21711#define HRTIM_DTR_DTF_Msk (0x1FFUL << HRTIM_DTR_DTF_Pos) /*!< 0x01FF0000 */
21712#define HRTIM_DTR_DTF HRTIM_DTR_DTF_Msk /*!< Dead time falling value */
21713#define HRTIM_DTR_DTF_0 (0x001UL << HRTIM_DTR_DTF_Pos) /*!< 0x00010000 */
21714#define HRTIM_DTR_DTF_1 (0x002UL << HRTIM_DTR_DTF_Pos) /*!< 0x00020000 */
21715#define HRTIM_DTR_DTF_2 (0x004UL << HRTIM_DTR_DTF_Pos) /*!< 0x00040000 */
21716#define HRTIM_DTR_DTF_3 (0x008UL << HRTIM_DTR_DTF_Pos) /*!< 0x00080000 */
21717#define HRTIM_DTR_DTF_4 (0x010UL << HRTIM_DTR_DTF_Pos) /*!< 0x00100000 */
21718#define HRTIM_DTR_DTF_5 (0x020UL << HRTIM_DTR_DTF_Pos) /*!< 0x00200000 */
21719#define HRTIM_DTR_DTF_6 (0x040UL << HRTIM_DTR_DTF_Pos) /*!< 0x00400000 */
21720#define HRTIM_DTR_DTF_7 (0x080UL << HRTIM_DTR_DTF_Pos) /*!< 0x00800000 */
21721#define HRTIM_DTR_DTF_8 (0x100UL << HRTIM_DTR_DTF_Pos) /*!< 0x01000000 */
21722#define HRTIM_DTR_SDTF_Pos (25U)
21723#define HRTIM_DTR_SDTF_Msk (0x1UL << HRTIM_DTR_SDTF_Pos) /*!< 0x02000000 */
21724#define HRTIM_DTR_SDTF HRTIM_DTR_SDTF_Msk /*!< Sign dead time falling value */
21725#define HRTIM_DTR_DTFSLK_Pos (30U)
21726#define HRTIM_DTR_DTFSLK_Msk (0x1UL << HRTIM_DTR_DTFSLK_Pos) /*!< 0x40000000 */
21727#define HRTIM_DTR_DTFSLK HRTIM_DTR_DTFSLK_Msk /*!< Dead time falling sign lock */
21728#define HRTIM_DTR_DTFLK_Pos (31U)
21729#define HRTIM_DTR_DTFLK_Msk (0x1UL << HRTIM_DTR_DTFLK_Pos) /*!< 0x80000000 */
21730#define HRTIM_DTR_DTFLK HRTIM_DTR_DTFLK_Msk /*!< Dead time falling lock */
21731
21732/**** Bit definition for Slave Output 1 set register **************************/
21733#define HRTIM_SET1R_SST_Pos (0U)
21734#define HRTIM_SET1R_SST_Msk (0x1UL << HRTIM_SET1R_SST_Pos) /*!< 0x00000001 */
21735#define HRTIM_SET1R_SST HRTIM_SET1R_SST_Msk /*!< software set trigger */
21736#define HRTIM_SET1R_RESYNC_Pos (1U)
21737#define HRTIM_SET1R_RESYNC_Msk (0x1UL << HRTIM_SET1R_RESYNC_Pos) /*!< 0x00000002 */
21738#define HRTIM_SET1R_RESYNC HRTIM_SET1R_RESYNC_Msk /*!< Timer A resynchronization */
21739#define HRTIM_SET1R_PER_Pos (2U)
21740#define HRTIM_SET1R_PER_Msk (0x1UL << HRTIM_SET1R_PER_Pos) /*!< 0x00000004 */
21741#define HRTIM_SET1R_PER HRTIM_SET1R_PER_Msk /*!< Timer A period */
21742#define HRTIM_SET1R_CMP1_Pos (3U)
21743#define HRTIM_SET1R_CMP1_Msk (0x1UL << HRTIM_SET1R_CMP1_Pos) /*!< 0x00000008 */
21744#define HRTIM_SET1R_CMP1 HRTIM_SET1R_CMP1_Msk /*!< Timer A compare 1 */
21745#define HRTIM_SET1R_CMP2_Pos (4U)
21746#define HRTIM_SET1R_CMP2_Msk (0x1UL << HRTIM_SET1R_CMP2_Pos) /*!< 0x00000010 */
21747#define HRTIM_SET1R_CMP2 HRTIM_SET1R_CMP2_Msk /*!< Timer A compare 2 */
21748#define HRTIM_SET1R_CMP3_Pos (5U)
21749#define HRTIM_SET1R_CMP3_Msk (0x1UL << HRTIM_SET1R_CMP3_Pos) /*!< 0x00000020 */
21750#define HRTIM_SET1R_CMP3 HRTIM_SET1R_CMP3_Msk /*!< Timer A compare 3 */
21751#define HRTIM_SET1R_CMP4_Pos (6U)
21752#define HRTIM_SET1R_CMP4_Msk (0x1UL << HRTIM_SET1R_CMP4_Pos) /*!< 0x00000040 */
21753#define HRTIM_SET1R_CMP4 HRTIM_SET1R_CMP4_Msk /*!< Timer A compare 4 */
21754
21755#define HRTIM_SET1R_MSTPER_Pos (7U)
21756#define HRTIM_SET1R_MSTPER_Msk (0x1UL << HRTIM_SET1R_MSTPER_Pos) /*!< 0x00000080 */
21757#define HRTIM_SET1R_MSTPER HRTIM_SET1R_MSTPER_Msk /*!< Master period */
21758#define HRTIM_SET1R_MSTCMP1_Pos (8U)
21759#define HRTIM_SET1R_MSTCMP1_Msk (0x1UL << HRTIM_SET1R_MSTCMP1_Pos) /*!< 0x00000100 */
21760#define HRTIM_SET1R_MSTCMP1 HRTIM_SET1R_MSTCMP1_Msk /*!< Master compare 1 */
21761#define HRTIM_SET1R_MSTCMP2_Pos (9U)
21762#define HRTIM_SET1R_MSTCMP2_Msk (0x1UL << HRTIM_SET1R_MSTCMP2_Pos) /*!< 0x00000200 */
21763#define HRTIM_SET1R_MSTCMP2 HRTIM_SET1R_MSTCMP2_Msk /*!< Master compare 2 */
21764#define HRTIM_SET1R_MSTCMP3_Pos (10U)
21765#define HRTIM_SET1R_MSTCMP3_Msk (0x1UL << HRTIM_SET1R_MSTCMP3_Pos) /*!< 0x00000400 */
21766#define HRTIM_SET1R_MSTCMP3 HRTIM_SET1R_MSTCMP3_Msk /*!< Master compare 3 */
21767#define HRTIM_SET1R_MSTCMP4_Pos (11U)
21768#define HRTIM_SET1R_MSTCMP4_Msk (0x1UL << HRTIM_SET1R_MSTCMP4_Pos) /*!< 0x00000800 */
21769#define HRTIM_SET1R_MSTCMP4 HRTIM_SET1R_MSTCMP4_Msk /*!< Master compare 4 */
21770
21771#define HRTIM_SET1R_TIMEVNT1_Pos (12U)
21772#define HRTIM_SET1R_TIMEVNT1_Msk (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos) /*!< 0x00001000 */
21773#define HRTIM_SET1R_TIMEVNT1 HRTIM_SET1R_TIMEVNT1_Msk /*!< Timer event 1 */
21774#define HRTIM_SET1R_TIMEVNT2_Pos (13U)
21775#define HRTIM_SET1R_TIMEVNT2_Msk (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos) /*!< 0x00002000 */
21776#define HRTIM_SET1R_TIMEVNT2 HRTIM_SET1R_TIMEVNT2_Msk /*!< Timer event 2 */
21777#define HRTIM_SET1R_TIMEVNT3_Pos (14U)
21778#define HRTIM_SET1R_TIMEVNT3_Msk (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos) /*!< 0x00004000 */
21779#define HRTIM_SET1R_TIMEVNT3 HRTIM_SET1R_TIMEVNT3_Msk /*!< Timer event 3 */
21780#define HRTIM_SET1R_TIMEVNT4_Pos (15U)
21781#define HRTIM_SET1R_TIMEVNT4_Msk (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos) /*!< 0x00008000 */
21782#define HRTIM_SET1R_TIMEVNT4 HRTIM_SET1R_TIMEVNT4_Msk /*!< Timer event 4 */
21783#define HRTIM_SET1R_TIMEVNT5_Pos (16U)
21784#define HRTIM_SET1R_TIMEVNT5_Msk (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos) /*!< 0x00010000 */
21785#define HRTIM_SET1R_TIMEVNT5 HRTIM_SET1R_TIMEVNT5_Msk /*!< Timer event 5 */
21786#define HRTIM_SET1R_TIMEVNT6_Pos (17U)
21787#define HRTIM_SET1R_TIMEVNT6_Msk (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos) /*!< 0x00020000 */
21788#define HRTIM_SET1R_TIMEVNT6 HRTIM_SET1R_TIMEVNT6_Msk /*!< Timer event 6 */
21789#define HRTIM_SET1R_TIMEVNT7_Pos (18U)
21790#define HRTIM_SET1R_TIMEVNT7_Msk (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos) /*!< 0x00040000 */
21791#define HRTIM_SET1R_TIMEVNT7 HRTIM_SET1R_TIMEVNT7_Msk /*!< Timer event 7 */
21792#define HRTIM_SET1R_TIMEVNT8_Pos (19U)
21793#define HRTIM_SET1R_TIMEVNT8_Msk (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos) /*!< 0x00080000 */
21794#define HRTIM_SET1R_TIMEVNT8 HRTIM_SET1R_TIMEVNT8_Msk /*!< Timer event 8 */
21795#define HRTIM_SET1R_TIMEVNT9_Pos (20U)
21796#define HRTIM_SET1R_TIMEVNT9_Msk (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos) /*!< 0x00100000 */
21797#define HRTIM_SET1R_TIMEVNT9 HRTIM_SET1R_TIMEVNT9_Msk /*!< Timer event 9 */
21798
21799#define HRTIM_SET1R_EXTVNT1_Pos (21U)
21800#define HRTIM_SET1R_EXTVNT1_Msk (0x1UL << HRTIM_SET1R_EXTVNT1_Pos) /*!< 0x00200000 */
21801#define HRTIM_SET1R_EXTVNT1 HRTIM_SET1R_EXTVNT1_Msk /*!< External event 1 */
21802#define HRTIM_SET1R_EXTVNT2_Pos (22U)
21803#define HRTIM_SET1R_EXTVNT2_Msk (0x1UL << HRTIM_SET1R_EXTVNT2_Pos) /*!< 0x00400000 */
21804#define HRTIM_SET1R_EXTVNT2 HRTIM_SET1R_EXTVNT2_Msk /*!< External event 2 */
21805#define HRTIM_SET1R_EXTVNT3_Pos (23U)
21806#define HRTIM_SET1R_EXTVNT3_Msk (0x1UL << HRTIM_SET1R_EXTVNT3_Pos) /*!< 0x00800000 */
21807#define HRTIM_SET1R_EXTVNT3 HRTIM_SET1R_EXTVNT3_Msk /*!< External event 3 */
21808#define HRTIM_SET1R_EXTVNT4_Pos (24U)
21809#define HRTIM_SET1R_EXTVNT4_Msk (0x1UL << HRTIM_SET1R_EXTVNT4_Pos) /*!< 0x01000000 */
21810#define HRTIM_SET1R_EXTVNT4 HRTIM_SET1R_EXTVNT4_Msk /*!< External event 4 */
21811#define HRTIM_SET1R_EXTVNT5_Pos (25U)
21812#define HRTIM_SET1R_EXTVNT5_Msk (0x1UL << HRTIM_SET1R_EXTVNT5_Pos) /*!< 0x02000000 */
21813#define HRTIM_SET1R_EXTVNT5 HRTIM_SET1R_EXTVNT5_Msk /*!< External event 5 */
21814#define HRTIM_SET1R_EXTVNT6_Pos (26U)
21815#define HRTIM_SET1R_EXTVNT6_Msk (0x1UL << HRTIM_SET1R_EXTVNT6_Pos) /*!< 0x04000000 */
21816#define HRTIM_SET1R_EXTVNT6 HRTIM_SET1R_EXTVNT6_Msk /*!< External event 6 */
21817#define HRTIM_SET1R_EXTVNT7_Pos (27U)
21818#define HRTIM_SET1R_EXTVNT7_Msk (0x1UL << HRTIM_SET1R_EXTVNT7_Pos) /*!< 0x08000000 */
21819#define HRTIM_SET1R_EXTVNT7 HRTIM_SET1R_EXTVNT7_Msk /*!< External event 7 */
21820#define HRTIM_SET1R_EXTVNT8_Pos (28U)
21821#define HRTIM_SET1R_EXTVNT8_Msk (0x1UL << HRTIM_SET1R_EXTVNT8_Pos) /*!< 0x10000000 */
21822#define HRTIM_SET1R_EXTVNT8 HRTIM_SET1R_EXTVNT8_Msk /*!< External event 8 */
21823#define HRTIM_SET1R_EXTVNT9_Pos (29U)
21824#define HRTIM_SET1R_EXTVNT9_Msk (0x1UL << HRTIM_SET1R_EXTVNT9_Pos) /*!< 0x20000000 */
21825#define HRTIM_SET1R_EXTVNT9 HRTIM_SET1R_EXTVNT9_Msk /*!< External event 9 */
21826#define HRTIM_SET1R_EXTVNT10_Pos (30U)
21827#define HRTIM_SET1R_EXTVNT10_Msk (0x1UL << HRTIM_SET1R_EXTVNT10_Pos) /*!< 0x40000000 */
21828#define HRTIM_SET1R_EXTVNT10 HRTIM_SET1R_EXTVNT10_Msk /*!< External event 10 */
21829
21830#define HRTIM_SET1R_UPDATE_Pos (31U)
21831#define HRTIM_SET1R_UPDATE_Msk (0x1UL << HRTIM_SET1R_UPDATE_Pos) /*!< 0x80000000 */
21832#define HRTIM_SET1R_UPDATE HRTIM_SET1R_UPDATE_Msk /*!< Register update (transfer preload to active) */
21833
21834/**** Bit definition for Slave Output 1 reset register ************************/
21835#define HRTIM_RST1R_SRT_Pos (0U)
21836#define HRTIM_RST1R_SRT_Msk (0x1UL << HRTIM_RST1R_SRT_Pos) /*!< 0x00000001 */
21837#define HRTIM_RST1R_SRT HRTIM_RST1R_SRT_Msk /*!< software reset trigger */
21838#define HRTIM_RST1R_RESYNC_Pos (1U)
21839#define HRTIM_RST1R_RESYNC_Msk (0x1UL << HRTIM_RST1R_RESYNC_Pos) /*!< 0x00000002 */
21840#define HRTIM_RST1R_RESYNC HRTIM_RST1R_RESYNC_Msk /*!< Timer A resynchronization */
21841#define HRTIM_RST1R_PER_Pos (2U)
21842#define HRTIM_RST1R_PER_Msk (0x1UL << HRTIM_RST1R_PER_Pos) /*!< 0x00000004 */
21843#define HRTIM_RST1R_PER HRTIM_RST1R_PER_Msk /*!< Timer A period */
21844#define HRTIM_RST1R_CMP1_Pos (3U)
21845#define HRTIM_RST1R_CMP1_Msk (0x1UL << HRTIM_RST1R_CMP1_Pos) /*!< 0x00000008 */
21846#define HRTIM_RST1R_CMP1 HRTIM_RST1R_CMP1_Msk /*!< Timer A compare 1 */
21847#define HRTIM_RST1R_CMP2_Pos (4U)
21848#define HRTIM_RST1R_CMP2_Msk (0x1UL << HRTIM_RST1R_CMP2_Pos) /*!< 0x00000010 */
21849#define HRTIM_RST1R_CMP2 HRTIM_RST1R_CMP2_Msk /*!< Timer A compare 2 */
21850#define HRTIM_RST1R_CMP3_Pos (5U)
21851#define HRTIM_RST1R_CMP3_Msk (0x1UL << HRTIM_RST1R_CMP3_Pos) /*!< 0x00000020 */
21852#define HRTIM_RST1R_CMP3 HRTIM_RST1R_CMP3_Msk /*!< Timer A compare 3 */
21853#define HRTIM_RST1R_CMP4_Pos (6U)
21854#define HRTIM_RST1R_CMP4_Msk (0x1UL << HRTIM_RST1R_CMP4_Pos) /*!< 0x00000040 */
21855#define HRTIM_RST1R_CMP4 HRTIM_RST1R_CMP4_Msk /*!< Timer A compare 4 */
21856
21857#define HRTIM_RST1R_MSTPER_Pos (7U)
21858#define HRTIM_RST1R_MSTPER_Msk (0x1UL << HRTIM_RST1R_MSTPER_Pos) /*!< 0x00000080 */
21859#define HRTIM_RST1R_MSTPER HRTIM_RST1R_MSTPER_Msk /*!< Master period */
21860#define HRTIM_RST1R_MSTCMP1_Pos (8U)
21861#define HRTIM_RST1R_MSTCMP1_Msk (0x1UL << HRTIM_RST1R_MSTCMP1_Pos) /*!< 0x00000100 */
21862#define HRTIM_RST1R_MSTCMP1 HRTIM_RST1R_MSTCMP1_Msk /*!< Master compare 1 */
21863#define HRTIM_RST1R_MSTCMP2_Pos (9U)
21864#define HRTIM_RST1R_MSTCMP2_Msk (0x1UL << HRTIM_RST1R_MSTCMP2_Pos) /*!< 0x00000200 */
21865#define HRTIM_RST1R_MSTCMP2 HRTIM_RST1R_MSTCMP2_Msk /*!< Master compare 2 */
21866#define HRTIM_RST1R_MSTCMP3_Pos (10U)
21867#define HRTIM_RST1R_MSTCMP3_Msk (0x1UL << HRTIM_RST1R_MSTCMP3_Pos) /*!< 0x00000400 */
21868#define HRTIM_RST1R_MSTCMP3 HRTIM_RST1R_MSTCMP3_Msk /*!< Master compare 3 */
21869#define HRTIM_RST1R_MSTCMP4_Pos (11U)
21870#define HRTIM_RST1R_MSTCMP4_Msk (0x1UL << HRTIM_RST1R_MSTCMP4_Pos) /*!< 0x00000800 */
21871#define HRTIM_RST1R_MSTCMP4 HRTIM_RST1R_MSTCMP4_Msk /*!< Master compare 4 */
21872
21873#define HRTIM_RST1R_TIMEVNT1_Pos (12U)
21874#define HRTIM_RST1R_TIMEVNT1_Msk (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos) /*!< 0x00001000 */
21875#define HRTIM_RST1R_TIMEVNT1 HRTIM_RST1R_TIMEVNT1_Msk /*!< Timer event 1 */
21876#define HRTIM_RST1R_TIMEVNT2_Pos (13U)
21877#define HRTIM_RST1R_TIMEVNT2_Msk (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos) /*!< 0x00002000 */
21878#define HRTIM_RST1R_TIMEVNT2 HRTIM_RST1R_TIMEVNT2_Msk /*!< Timer event 2 */
21879#define HRTIM_RST1R_TIMEVNT3_Pos (14U)
21880#define HRTIM_RST1R_TIMEVNT3_Msk (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos) /*!< 0x00004000 */
21881#define HRTIM_RST1R_TIMEVNT3 HRTIM_RST1R_TIMEVNT3_Msk /*!< Timer event 3 */
21882#define HRTIM_RST1R_TIMEVNT4_Pos (15U)
21883#define HRTIM_RST1R_TIMEVNT4_Msk (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos) /*!< 0x00008000 */
21884#define HRTIM_RST1R_TIMEVNT4 HRTIM_RST1R_TIMEVNT4_Msk /*!< Timer event 4 */
21885#define HRTIM_RST1R_TIMEVNT5_Pos (16U)
21886#define HRTIM_RST1R_TIMEVNT5_Msk (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos) /*!< 0x00010000 */
21887#define HRTIM_RST1R_TIMEVNT5 HRTIM_RST1R_TIMEVNT5_Msk /*!< Timer event 5 */
21888#define HRTIM_RST1R_TIMEVNT6_Pos (17U)
21889#define HRTIM_RST1R_TIMEVNT6_Msk (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos) /*!< 0x00020000 */
21890#define HRTIM_RST1R_TIMEVNT6 HRTIM_RST1R_TIMEVNT6_Msk /*!< Timer event 6 */
21891#define HRTIM_RST1R_TIMEVNT7_Pos (18U)
21892#define HRTIM_RST1R_TIMEVNT7_Msk (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos) /*!< 0x00040000 */
21893#define HRTIM_RST1R_TIMEVNT7 HRTIM_RST1R_TIMEVNT7_Msk /*!< Timer event 7 */
21894#define HRTIM_RST1R_TIMEVNT8_Pos (19U)
21895#define HRTIM_RST1R_TIMEVNT8_Msk (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos) /*!< 0x00080000 */
21896#define HRTIM_RST1R_TIMEVNT8 HRTIM_RST1R_TIMEVNT8_Msk /*!< Timer event 8 */
21897#define HRTIM_RST1R_TIMEVNT9_Pos (20U)
21898#define HRTIM_RST1R_TIMEVNT9_Msk (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos) /*!< 0x00100000 */
21899#define HRTIM_RST1R_TIMEVNT9 HRTIM_RST1R_TIMEVNT9_Msk /*!< Timer event 9 */
21900
21901#define HRTIM_RST1R_EXTVNT1_Pos (21U)
21902#define HRTIM_RST1R_EXTVNT1_Msk (0x1UL << HRTIM_RST1R_EXTVNT1_Pos) /*!< 0x00200000 */
21903#define HRTIM_RST1R_EXTVNT1 HRTIM_RST1R_EXTVNT1_Msk /*!< External event 1 */
21904#define HRTIM_RST1R_EXTVNT2_Pos (22U)
21905#define HRTIM_RST1R_EXTVNT2_Msk (0x1UL << HRTIM_RST1R_EXTVNT2_Pos) /*!< 0x00400000 */
21906#define HRTIM_RST1R_EXTVNT2 HRTIM_RST1R_EXTVNT2_Msk /*!< External event 2 */
21907#define HRTIM_RST1R_EXTVNT3_Pos (23U)
21908#define HRTIM_RST1R_EXTVNT3_Msk (0x1UL << HRTIM_RST1R_EXTVNT3_Pos) /*!< 0x00800000 */
21909#define HRTIM_RST1R_EXTVNT3 HRTIM_RST1R_EXTVNT3_Msk /*!< External event 3 */
21910#define HRTIM_RST1R_EXTVNT4_Pos (24U)
21911#define HRTIM_RST1R_EXTVNT4_Msk (0x1UL << HRTIM_RST1R_EXTVNT4_Pos) /*!< 0x01000000 */
21912#define HRTIM_RST1R_EXTVNT4 HRTIM_RST1R_EXTVNT4_Msk /*!< External event 4 */
21913#define HRTIM_RST1R_EXTVNT5_Pos (25U)
21914#define HRTIM_RST1R_EXTVNT5_Msk (0x1UL << HRTIM_RST1R_EXTVNT5_Pos) /*!< 0x02000000 */
21915#define HRTIM_RST1R_EXTVNT5 HRTIM_RST1R_EXTVNT5_Msk /*!< External event 5 */
21916#define HRTIM_RST1R_EXTVNT6_Pos (26U)
21917#define HRTIM_RST1R_EXTVNT6_Msk (0x1UL << HRTIM_RST1R_EXTVNT6_Pos) /*!< 0x04000000 */
21918#define HRTIM_RST1R_EXTVNT6 HRTIM_RST1R_EXTVNT6_Msk /*!< External event 6 */
21919#define HRTIM_RST1R_EXTVNT7_Pos (27U)
21920#define HRTIM_RST1R_EXTVNT7_Msk (0x1UL << HRTIM_RST1R_EXTVNT7_Pos) /*!< 0x08000000 */
21921#define HRTIM_RST1R_EXTVNT7 HRTIM_RST1R_EXTVNT7_Msk /*!< External event 7 */
21922#define HRTIM_RST1R_EXTVNT8_Pos (28U)
21923#define HRTIM_RST1R_EXTVNT8_Msk (0x1UL << HRTIM_RST1R_EXTVNT8_Pos) /*!< 0x10000000 */
21924#define HRTIM_RST1R_EXTVNT8 HRTIM_RST1R_EXTVNT8_Msk /*!< External event 8 */
21925#define HRTIM_RST1R_EXTVNT9_Pos (29U)
21926#define HRTIM_RST1R_EXTVNT9_Msk (0x1UL << HRTIM_RST1R_EXTVNT9_Pos) /*!< 0x20000000 */
21927#define HRTIM_RST1R_EXTVNT9 HRTIM_RST1R_EXTVNT9_Msk /*!< External event 9 */
21928#define HRTIM_RST1R_EXTVNT10_Pos (30U)
21929#define HRTIM_RST1R_EXTVNT10_Msk (0x1UL << HRTIM_RST1R_EXTVNT10_Pos) /*!< 0x40000000 */
21930#define HRTIM_RST1R_EXTVNT10 HRTIM_RST1R_EXTVNT10_Msk /*!< External event 10 */
21931
21932#define HRTIM_RST1R_UPDATE_Pos (31U)
21933#define HRTIM_RST1R_UPDATE_Msk (0x1UL << HRTIM_RST1R_UPDATE_Pos) /*!< 0x80000000 */
21934#define HRTIM_RST1R_UPDATE HRTIM_RST1R_UPDATE_Msk /*!< Register update (transfer preload to active) */
21935
21936
21937/**** Bit definition for Slave Output 2 set register **************************/
21938#define HRTIM_SET2R_SST_Pos (0U)
21939#define HRTIM_SET2R_SST_Msk (0x1UL << HRTIM_SET2R_SST_Pos) /*!< 0x00000001 */
21940#define HRTIM_SET2R_SST HRTIM_SET2R_SST_Msk /*!< software set trigger */
21941#define HRTIM_SET2R_RESYNC_Pos (1U)
21942#define HRTIM_SET2R_RESYNC_Msk (0x1UL << HRTIM_SET2R_RESYNC_Pos) /*!< 0x00000002 */
21943#define HRTIM_SET2R_RESYNC HRTIM_SET2R_RESYNC_Msk /*!< Timer A resynchronization */
21944#define HRTIM_SET2R_PER_Pos (2U)
21945#define HRTIM_SET2R_PER_Msk (0x1UL << HRTIM_SET2R_PER_Pos) /*!< 0x00000004 */
21946#define HRTIM_SET2R_PER HRTIM_SET2R_PER_Msk /*!< Timer A period */
21947#define HRTIM_SET2R_CMP1_Pos (3U)
21948#define HRTIM_SET2R_CMP1_Msk (0x1UL << HRTIM_SET2R_CMP1_Pos) /*!< 0x00000008 */
21949#define HRTIM_SET2R_CMP1 HRTIM_SET2R_CMP1_Msk /*!< Timer A compare 1 */
21950#define HRTIM_SET2R_CMP2_Pos (4U)
21951#define HRTIM_SET2R_CMP2_Msk (0x1UL << HRTIM_SET2R_CMP2_Pos) /*!< 0x00000010 */
21952#define HRTIM_SET2R_CMP2 HRTIM_SET2R_CMP2_Msk /*!< Timer A compare 2 */
21953#define HRTIM_SET2R_CMP3_Pos (5U)
21954#define HRTIM_SET2R_CMP3_Msk (0x1UL << HRTIM_SET2R_CMP3_Pos) /*!< 0x00000020 */
21955#define HRTIM_SET2R_CMP3 HRTIM_SET2R_CMP3_Msk /*!< Timer A compare 3 */
21956#define HRTIM_SET2R_CMP4_Pos (6U)
21957#define HRTIM_SET2R_CMP4_Msk (0x1UL << HRTIM_SET2R_CMP4_Pos) /*!< 0x00000040 */
21958#define HRTIM_SET2R_CMP4 HRTIM_SET2R_CMP4_Msk /*!< Timer A compare 4 */
21959
21960#define HRTIM_SET2R_MSTPER_Pos (7U)
21961#define HRTIM_SET2R_MSTPER_Msk (0x1UL << HRTIM_SET2R_MSTPER_Pos) /*!< 0x00000080 */
21962#define HRTIM_SET2R_MSTPER HRTIM_SET2R_MSTPER_Msk /*!< Master period */
21963#define HRTIM_SET2R_MSTCMP1_Pos (8U)
21964#define HRTIM_SET2R_MSTCMP1_Msk (0x1UL << HRTIM_SET2R_MSTCMP1_Pos) /*!< 0x00000100 */
21965#define HRTIM_SET2R_MSTCMP1 HRTIM_SET2R_MSTCMP1_Msk /*!< Master compare 1 */
21966#define HRTIM_SET2R_MSTCMP2_Pos (9U)
21967#define HRTIM_SET2R_MSTCMP2_Msk (0x1UL << HRTIM_SET2R_MSTCMP2_Pos) /*!< 0x00000200 */
21968#define HRTIM_SET2R_MSTCMP2 HRTIM_SET2R_MSTCMP2_Msk /*!< Master compare 2 */
21969#define HRTIM_SET2R_MSTCMP3_Pos (10U)
21970#define HRTIM_SET2R_MSTCMP3_Msk (0x1UL << HRTIM_SET2R_MSTCMP3_Pos) /*!< 0x00000400 */
21971#define HRTIM_SET2R_MSTCMP3 HRTIM_SET2R_MSTCMP3_Msk /*!< Master compare 3 */
21972#define HRTIM_SET2R_MSTCMP4_Pos (11U)
21973#define HRTIM_SET2R_MSTCMP4_Msk (0x1UL << HRTIM_SET2R_MSTCMP4_Pos) /*!< 0x00000800 */
21974#define HRTIM_SET2R_MSTCMP4 HRTIM_SET2R_MSTCMP4_Msk /*!< Master compare 4 */
21975
21976#define HRTIM_SET2R_TIMEVNT1_Pos (12U)
21977#define HRTIM_SET2R_TIMEVNT1_Msk (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos) /*!< 0x00001000 */
21978#define HRTIM_SET2R_TIMEVNT1 HRTIM_SET2R_TIMEVNT1_Msk /*!< Timer event 1 */
21979#define HRTIM_SET2R_TIMEVNT2_Pos (13U)
21980#define HRTIM_SET2R_TIMEVNT2_Msk (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos) /*!< 0x00002000 */
21981#define HRTIM_SET2R_TIMEVNT2 HRTIM_SET2R_TIMEVNT2_Msk /*!< Timer event 2 */
21982#define HRTIM_SET2R_TIMEVNT3_Pos (14U)
21983#define HRTIM_SET2R_TIMEVNT3_Msk (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos) /*!< 0x00004000 */
21984#define HRTIM_SET2R_TIMEVNT3 HRTIM_SET2R_TIMEVNT3_Msk /*!< Timer event 3 */
21985#define HRTIM_SET2R_TIMEVNT4_Pos (15U)
21986#define HRTIM_SET2R_TIMEVNT4_Msk (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos) /*!< 0x00008000 */
21987#define HRTIM_SET2R_TIMEVNT4 HRTIM_SET2R_TIMEVNT4_Msk /*!< Timer event 4 */
21988#define HRTIM_SET2R_TIMEVNT5_Pos (16U)
21989#define HRTIM_SET2R_TIMEVNT5_Msk (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos) /*!< 0x00010000 */
21990#define HRTIM_SET2R_TIMEVNT5 HRTIM_SET2R_TIMEVNT5_Msk /*!< Timer event 5 */
21991#define HRTIM_SET2R_TIMEVNT6_Pos (17U)
21992#define HRTIM_SET2R_TIMEVNT6_Msk (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos) /*!< 0x00020000 */
21993#define HRTIM_SET2R_TIMEVNT6 HRTIM_SET2R_TIMEVNT6_Msk /*!< Timer event 6 */
21994#define HRTIM_SET2R_TIMEVNT7_Pos (18U)
21995#define HRTIM_SET2R_TIMEVNT7_Msk (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos) /*!< 0x00040000 */
21996#define HRTIM_SET2R_TIMEVNT7 HRTIM_SET2R_TIMEVNT7_Msk /*!< Timer event 7 */
21997#define HRTIM_SET2R_TIMEVNT8_Pos (19U)
21998#define HRTIM_SET2R_TIMEVNT8_Msk (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos) /*!< 0x00080000 */
21999#define HRTIM_SET2R_TIMEVNT8 HRTIM_SET2R_TIMEVNT8_Msk /*!< Timer event 8 */
22000#define HRTIM_SET2R_TIMEVNT9_Pos (20U)
22001#define HRTIM_SET2R_TIMEVNT9_Msk (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos) /*!< 0x00100000 */
22002#define HRTIM_SET2R_TIMEVNT9 HRTIM_SET2R_TIMEVNT9_Msk /*!< Timer event 9 */
22003
22004#define HRTIM_SET2R_EXTVNT1_Pos (21U)
22005#define HRTIM_SET2R_EXTVNT1_Msk (0x1UL << HRTIM_SET2R_EXTVNT1_Pos) /*!< 0x00200000 */
22006#define HRTIM_SET2R_EXTVNT1 HRTIM_SET2R_EXTVNT1_Msk /*!< External event 1 */
22007#define HRTIM_SET2R_EXTVNT2_Pos (22U)
22008#define HRTIM_SET2R_EXTVNT2_Msk (0x1UL << HRTIM_SET2R_EXTVNT2_Pos) /*!< 0x00400000 */
22009#define HRTIM_SET2R_EXTVNT2 HRTIM_SET2R_EXTVNT2_Msk /*!< External event 2 */
22010#define HRTIM_SET2R_EXTVNT3_Pos (23U)
22011#define HRTIM_SET2R_EXTVNT3_Msk (0x1UL << HRTIM_SET2R_EXTVNT3_Pos) /*!< 0x00800000 */
22012#define HRTIM_SET2R_EXTVNT3 HRTIM_SET2R_EXTVNT3_Msk /*!< External event 3 */
22013#define HRTIM_SET2R_EXTVNT4_Pos (24U)
22014#define HRTIM_SET2R_EXTVNT4_Msk (0x1UL << HRTIM_SET2R_EXTVNT4_Pos) /*!< 0x01000000 */
22015#define HRTIM_SET2R_EXTVNT4 HRTIM_SET2R_EXTVNT4_Msk /*!< External event 4 */
22016#define HRTIM_SET2R_EXTVNT5_Pos (25U)
22017#define HRTIM_SET2R_EXTVNT5_Msk (0x1UL << HRTIM_SET2R_EXTVNT5_Pos) /*!< 0x02000000 */
22018#define HRTIM_SET2R_EXTVNT5 HRTIM_SET2R_EXTVNT5_Msk /*!< External event 5 */
22019#define HRTIM_SET2R_EXTVNT6_Pos (26U)
22020#define HRTIM_SET2R_EXTVNT6_Msk (0x1UL << HRTIM_SET2R_EXTVNT6_Pos) /*!< 0x04000000 */
22021#define HRTIM_SET2R_EXTVNT6 HRTIM_SET2R_EXTVNT6_Msk /*!< External event 6 */
22022#define HRTIM_SET2R_EXTVNT7_Pos (27U)
22023#define HRTIM_SET2R_EXTVNT7_Msk (0x1UL << HRTIM_SET2R_EXTVNT7_Pos) /*!< 0x08000000 */
22024#define HRTIM_SET2R_EXTVNT7 HRTIM_SET2R_EXTVNT7_Msk /*!< External event 7 */
22025#define HRTIM_SET2R_EXTVNT8_Pos (28U)
22026#define HRTIM_SET2R_EXTVNT8_Msk (0x1UL << HRTIM_SET2R_EXTVNT8_Pos) /*!< 0x10000000 */
22027#define HRTIM_SET2R_EXTVNT8 HRTIM_SET2R_EXTVNT8_Msk /*!< External event 8 */
22028#define HRTIM_SET2R_EXTVNT9_Pos (29U)
22029#define HRTIM_SET2R_EXTVNT9_Msk (0x1UL << HRTIM_SET2R_EXTVNT9_Pos) /*!< 0x20000000 */
22030#define HRTIM_SET2R_EXTVNT9 HRTIM_SET2R_EXTVNT9_Msk /*!< External event 9 */
22031#define HRTIM_SET2R_EXTVNT10_Pos (30U)
22032#define HRTIM_SET2R_EXTVNT10_Msk (0x1UL << HRTIM_SET2R_EXTVNT10_Pos) /*!< 0x40000000 */
22033#define HRTIM_SET2R_EXTVNT10 HRTIM_SET2R_EXTVNT10_Msk /*!< External event 10 */
22034
22035#define HRTIM_SET2R_UPDATE_Pos (31U)
22036#define HRTIM_SET2R_UPDATE_Msk (0x1UL << HRTIM_SET2R_UPDATE_Pos) /*!< 0x80000000 */
22037#define HRTIM_SET2R_UPDATE HRTIM_SET2R_UPDATE_Msk /*!< Register update (transfer preload to active) */
22038
22039/**** Bit definition for Slave Output 2 reset register ************************/
22040#define HRTIM_RST2R_SRT_Pos (0U)
22041#define HRTIM_RST2R_SRT_Msk (0x1UL << HRTIM_RST2R_SRT_Pos) /*!< 0x00000001 */
22042#define HRTIM_RST2R_SRT HRTIM_RST2R_SRT_Msk /*!< software reset trigger */
22043#define HRTIM_RST2R_RESYNC_Pos (1U)
22044#define HRTIM_RST2R_RESYNC_Msk (0x1UL << HRTIM_RST2R_RESYNC_Pos) /*!< 0x00000002 */
22045#define HRTIM_RST2R_RESYNC HRTIM_RST2R_RESYNC_Msk /*!< Timer A resynchronization */
22046#define HRTIM_RST2R_PER_Pos (2U)
22047#define HRTIM_RST2R_PER_Msk (0x1UL << HRTIM_RST2R_PER_Pos) /*!< 0x00000004 */
22048#define HRTIM_RST2R_PER HRTIM_RST2R_PER_Msk /*!< Timer A period */
22049#define HRTIM_RST2R_CMP1_Pos (3U)
22050#define HRTIM_RST2R_CMP1_Msk (0x1UL << HRTIM_RST2R_CMP1_Pos) /*!< 0x00000008 */
22051#define HRTIM_RST2R_CMP1 HRTIM_RST2R_CMP1_Msk /*!< Timer A compare 1 */
22052#define HRTIM_RST2R_CMP2_Pos (4U)
22053#define HRTIM_RST2R_CMP2_Msk (0x1UL << HRTIM_RST2R_CMP2_Pos) /*!< 0x00000010 */
22054#define HRTIM_RST2R_CMP2 HRTIM_RST2R_CMP2_Msk /*!< Timer A compare 2 */
22055#define HRTIM_RST2R_CMP3_Pos (5U)
22056#define HRTIM_RST2R_CMP3_Msk (0x1UL << HRTIM_RST2R_CMP3_Pos) /*!< 0x00000020 */
22057#define HRTIM_RST2R_CMP3 HRTIM_RST2R_CMP3_Msk /*!< Timer A compare 3 */
22058#define HRTIM_RST2R_CMP4_Pos (6U)
22059#define HRTIM_RST2R_CMP4_Msk (0x1UL << HRTIM_RST2R_CMP4_Pos) /*!< 0x00000040 */
22060#define HRTIM_RST2R_CMP4 HRTIM_RST2R_CMP4_Msk /*!< Timer A compare 4 */
22061
22062#define HRTIM_RST2R_MSTPER_Pos (7U)
22063#define HRTIM_RST2R_MSTPER_Msk (0x1UL << HRTIM_RST2R_MSTPER_Pos) /*!< 0x00000080 */
22064#define HRTIM_RST2R_MSTPER HRTIM_RST2R_MSTPER_Msk /*!< Master period */
22065#define HRTIM_RST2R_MSTCMP1_Pos (8U)
22066#define HRTIM_RST2R_MSTCMP1_Msk (0x1UL << HRTIM_RST2R_MSTCMP1_Pos) /*!< 0x00000100 */
22067#define HRTIM_RST2R_MSTCMP1 HRTIM_RST2R_MSTCMP1_Msk /*!< Master compare 1 */
22068#define HRTIM_RST2R_MSTCMP2_Pos (9U)
22069#define HRTIM_RST2R_MSTCMP2_Msk (0x1UL << HRTIM_RST2R_MSTCMP2_Pos) /*!< 0x00000200 */
22070#define HRTIM_RST2R_MSTCMP2 HRTIM_RST2R_MSTCMP2_Msk /*!< Master compare 2 */
22071#define HRTIM_RST2R_MSTCMP3_Pos (10U)
22072#define HRTIM_RST2R_MSTCMP3_Msk (0x1UL << HRTIM_RST2R_MSTCMP3_Pos) /*!< 0x00000400 */
22073#define HRTIM_RST2R_MSTCMP3 HRTIM_RST2R_MSTCMP3_Msk /*!< Master compare 3 */
22074#define HRTIM_RST2R_MSTCMP4_Pos (11U)
22075#define HRTIM_RST2R_MSTCMP4_Msk (0x1UL << HRTIM_RST2R_MSTCMP4_Pos) /*!< 0x00000800 */
22076#define HRTIM_RST2R_MSTCMP4 HRTIM_RST2R_MSTCMP4_Msk /*!< Master compare 4 */
22077
22078#define HRTIM_RST2R_TIMEVNT1_Pos (12U)
22079#define HRTIM_RST2R_TIMEVNT1_Msk (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos) /*!< 0x00001000 */
22080#define HRTIM_RST2R_TIMEVNT1 HRTIM_RST2R_TIMEVNT1_Msk /*!< Timer event 1 */
22081#define HRTIM_RST2R_TIMEVNT2_Pos (13U)
22082#define HRTIM_RST2R_TIMEVNT2_Msk (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos) /*!< 0x00002000 */
22083#define HRTIM_RST2R_TIMEVNT2 HRTIM_RST2R_TIMEVNT2_Msk /*!< Timer event 2 */
22084#define HRTIM_RST2R_TIMEVNT3_Pos (14U)
22085#define HRTIM_RST2R_TIMEVNT3_Msk (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos) /*!< 0x00004000 */
22086#define HRTIM_RST2R_TIMEVNT3 HRTIM_RST2R_TIMEVNT3_Msk /*!< Timer event 3 */
22087#define HRTIM_RST2R_TIMEVNT4_Pos (15U)
22088#define HRTIM_RST2R_TIMEVNT4_Msk (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos) /*!< 0x00008000 */
22089#define HRTIM_RST2R_TIMEVNT4 HRTIM_RST2R_TIMEVNT4_Msk /*!< Timer event 4 */
22090#define HRTIM_RST2R_TIMEVNT5_Pos (16U)
22091#define HRTIM_RST2R_TIMEVNT5_Msk (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos) /*!< 0x00010000 */
22092#define HRTIM_RST2R_TIMEVNT5 HRTIM_RST2R_TIMEVNT5_Msk /*!< Timer event 5 */
22093#define HRTIM_RST2R_TIMEVNT6_Pos (17U)
22094#define HRTIM_RST2R_TIMEVNT6_Msk (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos) /*!< 0x00020000 */
22095#define HRTIM_RST2R_TIMEVNT6 HRTIM_RST2R_TIMEVNT6_Msk /*!< Timer event 6 */
22096#define HRTIM_RST2R_TIMEVNT7_Pos (18U)
22097#define HRTIM_RST2R_TIMEVNT7_Msk (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos) /*!< 0x00040000 */
22098#define HRTIM_RST2R_TIMEVNT7 HRTIM_RST2R_TIMEVNT7_Msk /*!< Timer event 7 */
22099#define HRTIM_RST2R_TIMEVNT8_Pos (19U)
22100#define HRTIM_RST2R_TIMEVNT8_Msk (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos) /*!< 0x00080000 */
22101#define HRTIM_RST2R_TIMEVNT8 HRTIM_RST2R_TIMEVNT8_Msk /*!< Timer event 8 */
22102#define HRTIM_RST2R_TIMEVNT9_Pos (20U)
22103#define HRTIM_RST2R_TIMEVNT9_Msk (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos) /*!< 0x00100000 */
22104#define HRTIM_RST2R_TIMEVNT9 HRTIM_RST2R_TIMEVNT9_Msk /*!< Timer event 9 */
22105
22106#define HRTIM_RST2R_EXTVNT1_Pos (21U)
22107#define HRTIM_RST2R_EXTVNT1_Msk (0x1UL << HRTIM_RST2R_EXTVNT1_Pos) /*!< 0x00200000 */
22108#define HRTIM_RST2R_EXTVNT1 HRTIM_RST2R_EXTVNT1_Msk /*!< External event 1 */
22109#define HRTIM_RST2R_EXTVNT2_Pos (22U)
22110#define HRTIM_RST2R_EXTVNT2_Msk (0x1UL << HRTIM_RST2R_EXTVNT2_Pos) /*!< 0x00400000 */
22111#define HRTIM_RST2R_EXTVNT2 HRTIM_RST2R_EXTVNT2_Msk /*!< External event 2 */
22112#define HRTIM_RST2R_EXTVNT3_Pos (23U)
22113#define HRTIM_RST2R_EXTVNT3_Msk (0x1UL << HRTIM_RST2R_EXTVNT3_Pos) /*!< 0x00800000 */
22114#define HRTIM_RST2R_EXTVNT3 HRTIM_RST2R_EXTVNT3_Msk /*!< External event 3 */
22115#define HRTIM_RST2R_EXTVNT4_Pos (24U)
22116#define HRTIM_RST2R_EXTVNT4_Msk (0x1UL << HRTIM_RST2R_EXTVNT4_Pos) /*!< 0x01000000 */
22117#define HRTIM_RST2R_EXTVNT4 HRTIM_RST2R_EXTVNT4_Msk /*!< External event 4 */
22118#define HRTIM_RST2R_EXTVNT5_Pos (25U)
22119#define HRTIM_RST2R_EXTVNT5_Msk (0x1UL << HRTIM_RST2R_EXTVNT5_Pos) /*!< 0x02000000 */
22120#define HRTIM_RST2R_EXTVNT5 HRTIM_RST2R_EXTVNT5_Msk /*!< External event 5 */
22121#define HRTIM_RST2R_EXTVNT6_Pos (26U)
22122#define HRTIM_RST2R_EXTVNT6_Msk (0x1UL << HRTIM_RST2R_EXTVNT6_Pos) /*!< 0x04000000 */
22123#define HRTIM_RST2R_EXTVNT6 HRTIM_RST2R_EXTVNT6_Msk /*!< External event 6 */
22124#define HRTIM_RST2R_EXTVNT7_Pos (27U)
22125#define HRTIM_RST2R_EXTVNT7_Msk (0x1UL << HRTIM_RST2R_EXTVNT7_Pos) /*!< 0x08000000 */
22126#define HRTIM_RST2R_EXTVNT7 HRTIM_RST2R_EXTVNT7_Msk /*!< External event 7 */
22127#define HRTIM_RST2R_EXTVNT8_Pos (28U)
22128#define HRTIM_RST2R_EXTVNT8_Msk (0x1UL << HRTIM_RST2R_EXTVNT8_Pos) /*!< 0x10000000 */
22129#define HRTIM_RST2R_EXTVNT8 HRTIM_RST2R_EXTVNT8_Msk /*!< External event 8 */
22130#define HRTIM_RST2R_EXTVNT9_Pos (29U)
22131#define HRTIM_RST2R_EXTVNT9_Msk (0x1UL << HRTIM_RST2R_EXTVNT9_Pos) /*!< 0x20000000 */
22132#define HRTIM_RST2R_EXTVNT9 HRTIM_RST2R_EXTVNT9_Msk /*!< External event 9 */
22133#define HRTIM_RST2R_EXTVNT10_Pos (30U)
22134#define HRTIM_RST2R_EXTVNT10_Msk (0x1UL << HRTIM_RST2R_EXTVNT10_Pos) /*!< 0x40000000 */
22135#define HRTIM_RST2R_EXTVNT10 HRTIM_RST2R_EXTVNT10_Msk /*!< External event 10 */
22136
22137#define HRTIM_RST2R_UPDATE_Pos (31U)
22138#define HRTIM_RST2R_UPDATE_Msk (0x1UL << HRTIM_RST2R_UPDATE_Pos) /*!< 0x80000000 */
22139#define HRTIM_RST2R_UPDATE HRTIM_RST2R_UPDATE_Msk /*!< Register update (transfer preload to active) */
22140
22141/**** Bit definition for Slave external event filtering register 1 ***********/
22142#define HRTIM_EEFR1_EE1LTCH_Pos (0U)
22143#define HRTIM_EEFR1_EE1LTCH_Msk (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos) /*!< 0x00000001 */
22144#define HRTIM_EEFR1_EE1LTCH HRTIM_EEFR1_EE1LTCH_Msk /*!< External Event 1 latch */
22145#define HRTIM_EEFR1_EE1FLTR_Pos (1U)
22146#define HRTIM_EEFR1_EE1FLTR_Msk (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x0000001E */
22147#define HRTIM_EEFR1_EE1FLTR HRTIM_EEFR1_EE1FLTR_Msk /*!< External Event 1 filter mask */
22148#define HRTIM_EEFR1_EE1FLTR_0 (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000002 */
22149#define HRTIM_EEFR1_EE1FLTR_1 (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000004 */
22150#define HRTIM_EEFR1_EE1FLTR_2 (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000008 */
22151#define HRTIM_EEFR1_EE1FLTR_3 (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000010 */
22152
22153#define HRTIM_EEFR1_EE2LTCH_Pos (6U)
22154#define HRTIM_EEFR1_EE2LTCH_Msk (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos) /*!< 0x00000040 */
22155#define HRTIM_EEFR1_EE2LTCH HRTIM_EEFR1_EE2LTCH_Msk /*!< External Event 2 latch */
22156#define HRTIM_EEFR1_EE2FLTR_Pos (7U)
22157#define HRTIM_EEFR1_EE2FLTR_Msk (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000780 */
22158#define HRTIM_EEFR1_EE2FLTR HRTIM_EEFR1_EE2FLTR_Msk /*!< External Event 2 filter mask */
22159#define HRTIM_EEFR1_EE2FLTR_0 (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000080 */
22160#define HRTIM_EEFR1_EE2FLTR_1 (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000100 */
22161#define HRTIM_EEFR1_EE2FLTR_2 (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000200 */
22162#define HRTIM_EEFR1_EE2FLTR_3 (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000400 */
22163
22164#define HRTIM_EEFR1_EE3LTCH_Pos (12U)
22165#define HRTIM_EEFR1_EE3LTCH_Msk (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos) /*!< 0x00001000 */
22166#define HRTIM_EEFR1_EE3LTCH HRTIM_EEFR1_EE3LTCH_Msk /*!< External Event 3 latch */
22167#define HRTIM_EEFR1_EE3FLTR_Pos (13U)
22168#define HRTIM_EEFR1_EE3FLTR_Msk (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x0001E000 */
22169#define HRTIM_EEFR1_EE3FLTR HRTIM_EEFR1_EE3FLTR_Msk /*!< External Event 3 filter mask */
22170#define HRTIM_EEFR1_EE3FLTR_0 (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00002000 */
22171#define HRTIM_EEFR1_EE3FLTR_1 (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00004000 */
22172#define HRTIM_EEFR1_EE3FLTR_2 (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00008000 */
22173#define HRTIM_EEFR1_EE3FLTR_3 (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00010000 */
22174
22175#define HRTIM_EEFR1_EE4LTCH_Pos (18U)
22176#define HRTIM_EEFR1_EE4LTCH_Msk (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos) /*!< 0x00040000 */
22177#define HRTIM_EEFR1_EE4LTCH HRTIM_EEFR1_EE4LTCH_Msk /*!< External Event 4 latch */
22178#define HRTIM_EEFR1_EE4FLTR_Pos (19U)
22179#define HRTIM_EEFR1_EE4FLTR_Msk (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00780000 */
22180#define HRTIM_EEFR1_EE4FLTR HRTIM_EEFR1_EE4FLTR_Msk /*!< External Event 4 filter mask */
22181#define HRTIM_EEFR1_EE4FLTR_0 (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00080000 */
22182#define HRTIM_EEFR1_EE4FLTR_1 (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00100000 */
22183#define HRTIM_EEFR1_EE4FLTR_2 (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00200000 */
22184#define HRTIM_EEFR1_EE4FLTR_3 (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00400000 */
22185
22186#define HRTIM_EEFR1_EE5LTCH_Pos (24U)
22187#define HRTIM_EEFR1_EE5LTCH_Msk (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos) /*!< 0x01000000 */
22188#define HRTIM_EEFR1_EE5LTCH HRTIM_EEFR1_EE5LTCH_Msk /*!< External Event 5 latch */
22189#define HRTIM_EEFR1_EE5FLTR_Pos (25U)
22190#define HRTIM_EEFR1_EE5FLTR_Msk (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x1E000000 */
22191#define HRTIM_EEFR1_EE5FLTR HRTIM_EEFR1_EE5FLTR_Msk /*!< External Event 5 filter mask */
22192#define HRTIM_EEFR1_EE5FLTR_0 (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x02000000 */
22193#define HRTIM_EEFR1_EE5FLTR_1 (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x04000000 */
22194#define HRTIM_EEFR1_EE5FLTR_2 (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x08000000 */
22195#define HRTIM_EEFR1_EE5FLTR_3 (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x10000000 */
22196
22197/**** Bit definition for Slave external event filtering register 2 ***********/
22198#define HRTIM_EEFR2_EE6LTCH_Pos (0U)
22199#define HRTIM_EEFR2_EE6LTCH_Msk (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos) /*!< 0x00000001 */
22200#define HRTIM_EEFR2_EE6LTCH HRTIM_EEFR2_EE6LTCH_Msk /*!< External Event 6 latch */
22201#define HRTIM_EEFR2_EE6FLTR_Pos (1U)
22202#define HRTIM_EEFR2_EE6FLTR_Msk (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x0000001E */
22203#define HRTIM_EEFR2_EE6FLTR HRTIM_EEFR2_EE6FLTR_Msk /*!< External Event 6 filter mask */
22204#define HRTIM_EEFR2_EE6FLTR_0 (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000002 */
22205#define HRTIM_EEFR2_EE6FLTR_1 (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000004 */
22206#define HRTIM_EEFR2_EE6FLTR_2 (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000008 */
22207#define HRTIM_EEFR2_EE6FLTR_3 (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000010 */
22208
22209#define HRTIM_EEFR2_EE7LTCH_Pos (6U)
22210#define HRTIM_EEFR2_EE7LTCH_Msk (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos) /*!< 0x00000040 */
22211#define HRTIM_EEFR2_EE7LTCH HRTIM_EEFR2_EE7LTCH_Msk /*!< External Event 7 latch */
22212#define HRTIM_EEFR2_EE7FLTR_Pos (7U)
22213#define HRTIM_EEFR2_EE7FLTR_Msk (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000780 */
22214#define HRTIM_EEFR2_EE7FLTR HRTIM_EEFR2_EE7FLTR_Msk /*!< External Event 7 filter mask */
22215#define HRTIM_EEFR2_EE7FLTR_0 (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000080 */
22216#define HRTIM_EEFR2_EE7FLTR_1 (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000100 */
22217#define HRTIM_EEFR2_EE7FLTR_2 (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000200 */
22218#define HRTIM_EEFR2_EE7FLTR_3 (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000400 */
22219
22220#define HRTIM_EEFR2_EE8LTCH_Pos (12U)
22221#define HRTIM_EEFR2_EE8LTCH_Msk (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos) /*!< 0x00001000 */
22222#define HRTIM_EEFR2_EE8LTCH HRTIM_EEFR2_EE8LTCH_Msk /*!< External Event 8 latch */
22223#define HRTIM_EEFR2_EE8FLTR_Pos (13U)
22224#define HRTIM_EEFR2_EE8FLTR_Msk (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x0001E000 */
22225#define HRTIM_EEFR2_EE8FLTR HRTIM_EEFR2_EE8FLTR_Msk /*!< External Event 8 filter mask */
22226#define HRTIM_EEFR2_EE8FLTR_0 (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00002000 */
22227#define HRTIM_EEFR2_EE8FLTR_1 (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00004000 */
22228#define HRTIM_EEFR2_EE8FLTR_2 (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00008000 */
22229#define HRTIM_EEFR2_EE8FLTR_3 (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00010000 */
22230
22231#define HRTIM_EEFR2_EE9LTCH_Pos (18U)
22232#define HRTIM_EEFR2_EE9LTCH_Msk (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos) /*!< 0x00040000 */
22233#define HRTIM_EEFR2_EE9LTCH HRTIM_EEFR2_EE9LTCH_Msk /*!< External Event 9 latch */
22234#define HRTIM_EEFR2_EE9FLTR_Pos (19U)
22235#define HRTIM_EEFR2_EE9FLTR_Msk (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00780000 */
22236#define HRTIM_EEFR2_EE9FLTR HRTIM_EEFR2_EE9FLTR_Msk /*!< External Event 9 filter mask */
22237#define HRTIM_EEFR2_EE9FLTR_0 (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00080000 */
22238#define HRTIM_EEFR2_EE9FLTR_1 (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00100000 */
22239#define HRTIM_EEFR2_EE9FLTR_2 (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00200000 */
22240#define HRTIM_EEFR2_EE9FLTR_3 (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00400000 */
22241
22242#define HRTIM_EEFR2_EE10LTCH_Pos (24U)
22243#define HRTIM_EEFR2_EE10LTCH_Msk (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos) /*!< 0x01000000 */
22244#define HRTIM_EEFR2_EE10LTCH HRTIM_EEFR2_EE10LTCH_Msk /*!< External Event 10 latch */
22245#define HRTIM_EEFR2_EE10FLTR_Pos (25U)
22246#define HRTIM_EEFR2_EE10FLTR_Msk (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x1E000000 */
22247#define HRTIM_EEFR2_EE10FLTR HRTIM_EEFR2_EE10FLTR_Msk /*!< External Event 10 filter mask */
22248#define HRTIM_EEFR2_EE10FLTR_0 (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x02000000 */
22249#define HRTIM_EEFR2_EE10FLTR_1 (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x04000000 */
22250#define HRTIM_EEFR2_EE10FLTR_2 (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x08000000 */
22251#define HRTIM_EEFR2_EE10FLTR_3 (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x10000000 */
22252
22253/**** Bit definition for Slave Timer reset register ***************************/
22254#define HRTIM_RSTR_UPDATE_Pos (1U)
22255#define HRTIM_RSTR_UPDATE_Msk (0x1UL << HRTIM_RSTR_UPDATE_Pos) /*!< 0x00000002 */
22256#define HRTIM_RSTR_UPDATE HRTIM_RSTR_UPDATE_Msk /*!< Timer update */
22257#define HRTIM_RSTR_CMP2_Pos (2U)
22258#define HRTIM_RSTR_CMP2_Msk (0x1UL << HRTIM_RSTR_CMP2_Pos) /*!< 0x00000004 */
22259#define HRTIM_RSTR_CMP2 HRTIM_RSTR_CMP2_Msk /*!< Timer compare2 */
22260#define HRTIM_RSTR_CMP4_Pos (3U)
22261#define HRTIM_RSTR_CMP4_Msk (0x1UL << HRTIM_RSTR_CMP4_Pos) /*!< 0x00000008 */
22262#define HRTIM_RSTR_CMP4 HRTIM_RSTR_CMP4_Msk /*!< Timer compare4 */
22263
22264#define HRTIM_RSTR_MSTPER_Pos (4U)
22265#define HRTIM_RSTR_MSTPER_Msk (0x1UL << HRTIM_RSTR_MSTPER_Pos) /*!< 0x00000010 */
22266#define HRTIM_RSTR_MSTPER HRTIM_RSTR_MSTPER_Msk /*!< Master period */
22267#define HRTIM_RSTR_MSTCMP1_Pos (5U)
22268#define HRTIM_RSTR_MSTCMP1_Msk (0x1UL << HRTIM_RSTR_MSTCMP1_Pos) /*!< 0x00000020 */
22269#define HRTIM_RSTR_MSTCMP1 HRTIM_RSTR_MSTCMP1_Msk /*!< Master compare1 */
22270#define HRTIM_RSTR_MSTCMP2_Pos (6U)
22271#define HRTIM_RSTR_MSTCMP2_Msk (0x1UL << HRTIM_RSTR_MSTCMP2_Pos) /*!< 0x00000040 */
22272#define HRTIM_RSTR_MSTCMP2 HRTIM_RSTR_MSTCMP2_Msk /*!< Master compare2 */
22273#define HRTIM_RSTR_MSTCMP3_Pos (7U)
22274#define HRTIM_RSTR_MSTCMP3_Msk (0x1UL << HRTIM_RSTR_MSTCMP3_Pos) /*!< 0x00000080 */
22275#define HRTIM_RSTR_MSTCMP3 HRTIM_RSTR_MSTCMP3_Msk /*!< Master compare3 */
22276#define HRTIM_RSTR_MSTCMP4_Pos (8U)
22277#define HRTIM_RSTR_MSTCMP4_Msk (0x1UL << HRTIM_RSTR_MSTCMP4_Pos) /*!< 0x00000100 */
22278#define HRTIM_RSTR_MSTCMP4 HRTIM_RSTR_MSTCMP4_Msk /*!< Master compare4 */
22279
22280#define HRTIM_RSTR_EXTEVNT1_Pos (9U)
22281#define HRTIM_RSTR_EXTEVNT1_Msk (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos) /*!< 0x00000200 */
22282#define HRTIM_RSTR_EXTEVNT1 HRTIM_RSTR_EXTEVNT1_Msk /*!< External event 1 */
22283#define HRTIM_RSTR_EXTEVNT2_Pos (10U)
22284#define HRTIM_RSTR_EXTEVNT2_Msk (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos) /*!< 0x00000400 */
22285#define HRTIM_RSTR_EXTEVNT2 HRTIM_RSTR_EXTEVNT2_Msk /*!< External event 2 */
22286#define HRTIM_RSTR_EXTEVNT3_Pos (11U)
22287#define HRTIM_RSTR_EXTEVNT3_Msk (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos) /*!< 0x00000800 */
22288#define HRTIM_RSTR_EXTEVNT3 HRTIM_RSTR_EXTEVNT3_Msk /*!< External event 3 */
22289#define HRTIM_RSTR_EXTEVNT4_Pos (12U)
22290#define HRTIM_RSTR_EXTEVNT4_Msk (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos) /*!< 0x00001000 */
22291#define HRTIM_RSTR_EXTEVNT4 HRTIM_RSTR_EXTEVNT4_Msk /*!< External event 4 */
22292#define HRTIM_RSTR_EXTEVNT5_Pos (13U)
22293#define HRTIM_RSTR_EXTEVNT5_Msk (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos) /*!< 0x00002000 */
22294#define HRTIM_RSTR_EXTEVNT5 HRTIM_RSTR_EXTEVNT5_Msk /*!< External event 5 */
22295#define HRTIM_RSTR_EXTEVNT6_Pos (14U)
22296#define HRTIM_RSTR_EXTEVNT6_Msk (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos) /*!< 0x00004000 */
22297#define HRTIM_RSTR_EXTEVNT6 HRTIM_RSTR_EXTEVNT6_Msk /*!< External event 6 */
22298#define HRTIM_RSTR_EXTEVNT7_Pos (15U)
22299#define HRTIM_RSTR_EXTEVNT7_Msk (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos) /*!< 0x00008000 */
22300#define HRTIM_RSTR_EXTEVNT7 HRTIM_RSTR_EXTEVNT7_Msk /*!< External event 7 */
22301#define HRTIM_RSTR_EXTEVNT8_Pos (16U)
22302#define HRTIM_RSTR_EXTEVNT8_Msk (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos) /*!< 0x00010000 */
22303#define HRTIM_RSTR_EXTEVNT8 HRTIM_RSTR_EXTEVNT8_Msk /*!< External event 8 */
22304#define HRTIM_RSTR_EXTEVNT9_Pos (17U)
22305#define HRTIM_RSTR_EXTEVNT9_Msk (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos) /*!< 0x00020000 */
22306#define HRTIM_RSTR_EXTEVNT9 HRTIM_RSTR_EXTEVNT9_Msk /*!< External event 9 */
22307#define HRTIM_RSTR_EXTEVNT10_Pos (18U)
22308#define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */
22309#define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */
22310
22311#define HRTIM_RSTR_TIMBCMP1_Pos (19U)
22312#define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */
22313#define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */
22314#define HRTIM_RSTR_TIMBCMP2_Pos (20U)
22315#define HRTIM_RSTR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos) /*!< 0x00100000 */
22316#define HRTIM_RSTR_TIMBCMP2 HRTIM_RSTR_TIMBCMP2_Msk /*!< Timer B compare 2 */
22317#define HRTIM_RSTR_TIMBCMP4_Pos (21U)
22318#define HRTIM_RSTR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos) /*!< 0x00200000 */
22319#define HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk /*!< Timer B compare 4 */
22320
22321#define HRTIM_RSTR_TIMCCMP1_Pos (22U)
22322#define HRTIM_RSTR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos) /*!< 0x00400000 */
22323#define HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk /*!< Timer C compare 1 */
22324#define HRTIM_RSTR_TIMCCMP2_Pos (23U)
22325#define HRTIM_RSTR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos) /*!< 0x00800000 */
22326#define HRTIM_RSTR_TIMCCMP2 HRTIM_RSTR_TIMCCMP2_Msk /*!< Timer C compare 2 */
22327#define HRTIM_RSTR_TIMCCMP4_Pos (24U)
22328#define HRTIM_RSTR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos) /*!< 0x01000000 */
22329#define HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk /*!< Timer C compare 4 */
22330
22331#define HRTIM_RSTR_TIMDCMP1_Pos (25U)
22332#define HRTIM_RSTR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos) /*!< 0x02000000 */
22333#define HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk /*!< Timer D compare 1 */
22334#define HRTIM_RSTR_TIMDCMP2_Pos (26U)
22335#define HRTIM_RSTR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos) /*!< 0x04000000 */
22336#define HRTIM_RSTR_TIMDCMP2 HRTIM_RSTR_TIMDCMP2_Msk /*!< Timer D compare 2 */
22337#define HRTIM_RSTR_TIMDCMP4_Pos (27U)
22338#define HRTIM_RSTR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos) /*!< 0x08000000 */
22339#define HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk /*!< Timer D compare 4 */
22340
22341#define HRTIM_RSTR_TIMECMP1_Pos (28U)
22342#define HRTIM_RSTR_TIMECMP1_Msk (0x1UL << HRTIM_RSTR_TIMECMP1_Pos) /*!< 0x10000000 */
22343#define HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk /*!< Timer E compare 1 */
22344#define HRTIM_RSTR_TIMECMP2_Pos (29U)
22345#define HRTIM_RSTR_TIMECMP2_Msk (0x1UL << HRTIM_RSTR_TIMECMP2_Pos) /*!< 0x20000000 */
22346#define HRTIM_RSTR_TIMECMP2 HRTIM_RSTR_TIMECMP2_Msk /*!< Timer E compare 2 */
22347#define HRTIM_RSTR_TIMECMP4_Pos (30U)
22348#define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */
22349#define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */
22350
22351/**** Bit definition for Slave Timer Chopper register *************************/
22352#define HRTIM_CHPR_CARFRQ_Pos (0U)
22353#define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */
22354#define HRTIM_CHPR_CARFRQ HRTIM_CHPR_CARFRQ_Msk /*!< Timer carrier frequency value */
22355#define HRTIM_CHPR_CARFRQ_0 (0x1UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000001 */
22356#define HRTIM_CHPR_CARFRQ_1 (0x2UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000002 */
22357#define HRTIM_CHPR_CARFRQ_2 (0x4UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000004 */
22358#define HRTIM_CHPR_CARFRQ_3 (0x8UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000008 */
22359
22360#define HRTIM_CHPR_CARDTY_Pos (4U)
22361#define HRTIM_CHPR_CARDTY_Msk (0x7UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000070 */
22362#define HRTIM_CHPR_CARDTY HRTIM_CHPR_CARDTY_Msk /*!< Timer chopper duty cycle value */
22363#define HRTIM_CHPR_CARDTY_0 (0x1UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000010 */
22364#define HRTIM_CHPR_CARDTY_1 (0x2UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000020 */
22365#define HRTIM_CHPR_CARDTY_2 (0x4UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000040 */
22366
22367#define HRTIM_CHPR_STRPW_Pos (7U)
22368#define HRTIM_CHPR_STRPW_Msk (0xFUL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000780 */
22369#define HRTIM_CHPR_STRPW HRTIM_CHPR_STRPW_Msk /*!< Timer start pulse width value */
22370#define HRTIM_CHPR_STRPW_0 (0x1UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000080 */
22371#define HRTIM_CHPR_STRPW_1 (0x2UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000100 */
22372#define HRTIM_CHPR_STRPW_2 (0x4UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000200 */
22373#define HRTIM_CHPR_STRPW_3 (0x8UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000400 */
22374
22375/**** Bit definition for Slave Timer Capture 1 control register ***************/
22376#define HRTIM_CPT1CR_SWCPT_Pos (0U)
22377#define HRTIM_CPT1CR_SWCPT_Msk (0x1UL << HRTIM_CPT1CR_SWCPT_Pos) /*!< 0x00000001 */
22378#define HRTIM_CPT1CR_SWCPT HRTIM_CPT1CR_SWCPT_Msk /*!< Software capture */
22379#define HRTIM_CPT1CR_UPDCPT_Pos (1U)
22380#define HRTIM_CPT1CR_UPDCPT_Msk (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos) /*!< 0x00000002 */
22381#define HRTIM_CPT1CR_UPDCPT HRTIM_CPT1CR_UPDCPT_Msk /*!< Update capture */
22382#define HRTIM_CPT1CR_EXEV1CPT_Pos (2U)
22383#define HRTIM_CPT1CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos) /*!< 0x00000004 */
22384#define HRTIM_CPT1CR_EXEV1CPT HRTIM_CPT1CR_EXEV1CPT_Msk /*!< External event 1 capture */
22385#define HRTIM_CPT1CR_EXEV2CPT_Pos (3U)
22386#define HRTIM_CPT1CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos) /*!< 0x00000008 */
22387#define HRTIM_CPT1CR_EXEV2CPT HRTIM_CPT1CR_EXEV2CPT_Msk /*!< External event 2 capture */
22388#define HRTIM_CPT1CR_EXEV3CPT_Pos (4U)
22389#define HRTIM_CPT1CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos) /*!< 0x00000010 */
22390#define HRTIM_CPT1CR_EXEV3CPT HRTIM_CPT1CR_EXEV3CPT_Msk /*!< External event 3 capture */
22391#define HRTIM_CPT1CR_EXEV4CPT_Pos (5U)
22392#define HRTIM_CPT1CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos) /*!< 0x00000020 */
22393#define HRTIM_CPT1CR_EXEV4CPT HRTIM_CPT1CR_EXEV4CPT_Msk /*!< External event 4 capture */
22394#define HRTIM_CPT1CR_EXEV5CPT_Pos (6U)
22395#define HRTIM_CPT1CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos) /*!< 0x00000040 */
22396#define HRTIM_CPT1CR_EXEV5CPT HRTIM_CPT1CR_EXEV5CPT_Msk /*!< External event 5 capture */
22397#define HRTIM_CPT1CR_EXEV6CPT_Pos (7U)
22398#define HRTIM_CPT1CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos) /*!< 0x00000080 */
22399#define HRTIM_CPT1CR_EXEV6CPT HRTIM_CPT1CR_EXEV6CPT_Msk /*!< External event 6 capture */
22400#define HRTIM_CPT1CR_EXEV7CPT_Pos (8U)
22401#define HRTIM_CPT1CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos) /*!< 0x00000100 */
22402#define HRTIM_CPT1CR_EXEV7CPT HRTIM_CPT1CR_EXEV7CPT_Msk /*!< External event 7 capture */
22403#define HRTIM_CPT1CR_EXEV8CPT_Pos (9U)
22404#define HRTIM_CPT1CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos) /*!< 0x00000200 */
22405#define HRTIM_CPT1CR_EXEV8CPT HRTIM_CPT1CR_EXEV8CPT_Msk /*!< External event 8 capture */
22406#define HRTIM_CPT1CR_EXEV9CPT_Pos (10U)
22407#define HRTIM_CPT1CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos) /*!< 0x00000400 */
22408#define HRTIM_CPT1CR_EXEV9CPT HRTIM_CPT1CR_EXEV9CPT_Msk /*!< External event 9 capture */
22409#define HRTIM_CPT1CR_EXEV10CPT_Pos (11U)
22410#define HRTIM_CPT1CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos) /*!< 0x00000800 */
22411#define HRTIM_CPT1CR_EXEV10CPT HRTIM_CPT1CR_EXEV10CPT_Msk /*!< External event 10 capture */
22412
22413#define HRTIM_CPT1CR_TA1SET_Pos (12U)
22414#define HRTIM_CPT1CR_TA1SET_Msk (0x1UL << HRTIM_CPT1CR_TA1SET_Pos) /*!< 0x00001000 */
22415#define HRTIM_CPT1CR_TA1SET HRTIM_CPT1CR_TA1SET_Msk /*!< Timer A output 1 set */
22416#define HRTIM_CPT1CR_TA1RST_Pos (13U)
22417#define HRTIM_CPT1CR_TA1RST_Msk (0x1UL << HRTIM_CPT1CR_TA1RST_Pos) /*!< 0x00002000 */
22418#define HRTIM_CPT1CR_TA1RST HRTIM_CPT1CR_TA1RST_Msk /*!< Timer A output 1 reset */
22419#define HRTIM_CPT1CR_TIMACMP1_Pos (14U)
22420#define HRTIM_CPT1CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos) /*!< 0x00004000 */
22421#define HRTIM_CPT1CR_TIMACMP1 HRTIM_CPT1CR_TIMACMP1_Msk /*!< Timer A compare 1 */
22422#define HRTIM_CPT1CR_TIMACMP2_Pos (15U)
22423#define HRTIM_CPT1CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos) /*!< 0x00008000 */
22424#define HRTIM_CPT1CR_TIMACMP2 HRTIM_CPT1CR_TIMACMP2_Msk /*!< Timer A compare 2 */
22425
22426#define HRTIM_CPT1CR_TB1SET_Pos (16U)
22427#define HRTIM_CPT1CR_TB1SET_Msk (0x1UL << HRTIM_CPT1CR_TB1SET_Pos) /*!< 0x00010000 */
22428#define HRTIM_CPT1CR_TB1SET HRTIM_CPT1CR_TB1SET_Msk /*!< Timer B output 1 set */
22429#define HRTIM_CPT1CR_TB1RST_Pos (17U)
22430#define HRTIM_CPT1CR_TB1RST_Msk (0x1UL << HRTIM_CPT1CR_TB1RST_Pos) /*!< 0x00020000 */
22431#define HRTIM_CPT1CR_TB1RST HRTIM_CPT1CR_TB1RST_Msk /*!< Timer B output 1 reset */
22432#define HRTIM_CPT1CR_TIMBCMP1_Pos (18U)
22433#define HRTIM_CPT1CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos) /*!< 0x00040000 */
22434#define HRTIM_CPT1CR_TIMBCMP1 HRTIM_CPT1CR_TIMBCMP1_Msk /*!< Timer B compare 1 */
22435#define HRTIM_CPT1CR_TIMBCMP2_Pos (19U)
22436#define HRTIM_CPT1CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos) /*!< 0x00080000 */
22437#define HRTIM_CPT1CR_TIMBCMP2 HRTIM_CPT1CR_TIMBCMP2_Msk /*!< Timer B compare 2 */
22438
22439#define HRTIM_CPT1CR_TC1SET_Pos (20U)
22440#define HRTIM_CPT1CR_TC1SET_Msk (0x1UL << HRTIM_CPT1CR_TC1SET_Pos) /*!< 0x00100000 */
22441#define HRTIM_CPT1CR_TC1SET HRTIM_CPT1CR_TC1SET_Msk /*!< Timer C output 1 set */
22442#define HRTIM_CPT1CR_TC1RST_Pos (21U)
22443#define HRTIM_CPT1CR_TC1RST_Msk (0x1UL << HRTIM_CPT1CR_TC1RST_Pos) /*!< 0x00200000 */
22444#define HRTIM_CPT1CR_TC1RST HRTIM_CPT1CR_TC1RST_Msk /*!< Timer C output 1 reset */
22445#define HRTIM_CPT1CR_TIMCCMP1_Pos (22U)
22446#define HRTIM_CPT1CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos) /*!< 0x00400000 */
22447#define HRTIM_CPT1CR_TIMCCMP1 HRTIM_CPT1CR_TIMCCMP1_Msk /*!< Timer C compare 1 */
22448#define HRTIM_CPT1CR_TIMCCMP2_Pos (23U)
22449#define HRTIM_CPT1CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos) /*!< 0x00800000 */
22450#define HRTIM_CPT1CR_TIMCCMP2 HRTIM_CPT1CR_TIMCCMP2_Msk /*!< Timer C compare 2 */
22451
22452#define HRTIM_CPT1CR_TD1SET_Pos (24U)
22453#define HRTIM_CPT1CR_TD1SET_Msk (0x1UL << HRTIM_CPT1CR_TD1SET_Pos) /*!< 0x01000000 */
22454#define HRTIM_CPT1CR_TD1SET HRTIM_CPT1CR_TD1SET_Msk /*!< Timer D output 1 set */
22455#define HRTIM_CPT1CR_TD1RST_Pos (25U)
22456#define HRTIM_CPT1CR_TD1RST_Msk (0x1UL << HRTIM_CPT1CR_TD1RST_Pos) /*!< 0x02000000 */
22457#define HRTIM_CPT1CR_TD1RST HRTIM_CPT1CR_TD1RST_Msk /*!< Timer D output 1 reset */
22458#define HRTIM_CPT1CR_TIMDCMP1_Pos (26U)
22459#define HRTIM_CPT1CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos) /*!< 0x04000000 */
22460#define HRTIM_CPT1CR_TIMDCMP1 HRTIM_CPT1CR_TIMDCMP1_Msk /*!< Timer D compare 1 */
22461#define HRTIM_CPT1CR_TIMDCMP2_Pos (27U)
22462#define HRTIM_CPT1CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos) /*!< 0x08000000 */
22463#define HRTIM_CPT1CR_TIMDCMP2 HRTIM_CPT1CR_TIMDCMP2_Msk /*!< Timer D compare 2 */
22464
22465#define HRTIM_CPT1CR_TE1SET_Pos (28U)
22466#define HRTIM_CPT1CR_TE1SET_Msk (0x1UL << HRTIM_CPT1CR_TE1SET_Pos) /*!< 0x10000000 */
22467#define HRTIM_CPT1CR_TE1SET HRTIM_CPT1CR_TE1SET_Msk /*!< Timer E output 1 set */
22468#define HRTIM_CPT1CR_TE1RST_Pos (29U)
22469#define HRTIM_CPT1CR_TE1RST_Msk (0x1UL << HRTIM_CPT1CR_TE1RST_Pos) /*!< 0x20000000 */
22470#define HRTIM_CPT1CR_TE1RST HRTIM_CPT1CR_TE1RST_Msk /*!< Timer E output 1 reset */
22471#define HRTIM_CPT1CR_TIMECMP1_Pos (30U)
22472#define HRTIM_CPT1CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos) /*!< 0x40000000 */
22473#define HRTIM_CPT1CR_TIMECMP1 HRTIM_CPT1CR_TIMECMP1_Msk /*!< Timer E compare 1 */
22474#define HRTIM_CPT1CR_TIMECMP2_Pos (31U)
22475#define HRTIM_CPT1CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos) /*!< 0x80000000 */
22476#define HRTIM_CPT1CR_TIMECMP2 HRTIM_CPT1CR_TIMECMP2_Msk /*!< Timer E compare 2 */
22477
22478/**** Bit definition for Slave Timer Capture 2 control register ***************/
22479#define HRTIM_CPT2CR_SWCPT_Pos (0U)
22480#define HRTIM_CPT2CR_SWCPT_Msk (0x1UL << HRTIM_CPT2CR_SWCPT_Pos) /*!< 0x00000001 */
22481#define HRTIM_CPT2CR_SWCPT HRTIM_CPT2CR_SWCPT_Msk /*!< Software capture */
22482#define HRTIM_CPT2CR_UPDCPT_Pos (1U)
22483#define HRTIM_CPT2CR_UPDCPT_Msk (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos) /*!< 0x00000002 */
22484#define HRTIM_CPT2CR_UPDCPT HRTIM_CPT2CR_UPDCPT_Msk /*!< Update capture */
22485#define HRTIM_CPT2CR_EXEV1CPT_Pos (2U)
22486#define HRTIM_CPT2CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos) /*!< 0x00000004 */
22487#define HRTIM_CPT2CR_EXEV1CPT HRTIM_CPT2CR_EXEV1CPT_Msk /*!< External event 1 capture */
22488#define HRTIM_CPT2CR_EXEV2CPT_Pos (3U)
22489#define HRTIM_CPT2CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos) /*!< 0x00000008 */
22490#define HRTIM_CPT2CR_EXEV2CPT HRTIM_CPT2CR_EXEV2CPT_Msk /*!< External event 2 capture */
22491#define HRTIM_CPT2CR_EXEV3CPT_Pos (4U)
22492#define HRTIM_CPT2CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos) /*!< 0x00000010 */
22493#define HRTIM_CPT2CR_EXEV3CPT HRTIM_CPT2CR_EXEV3CPT_Msk /*!< External event 3 capture */
22494#define HRTIM_CPT2CR_EXEV4CPT_Pos (5U)
22495#define HRTIM_CPT2CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos) /*!< 0x00000020 */
22496#define HRTIM_CPT2CR_EXEV4CPT HRTIM_CPT2CR_EXEV4CPT_Msk /*!< External event 4 capture */
22497#define HRTIM_CPT2CR_EXEV5CPT_Pos (6U)
22498#define HRTIM_CPT2CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos) /*!< 0x00000040 */
22499#define HRTIM_CPT2CR_EXEV5CPT HRTIM_CPT2CR_EXEV5CPT_Msk /*!< External event 5 capture */
22500#define HRTIM_CPT2CR_EXEV6CPT_Pos (7U)
22501#define HRTIM_CPT2CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos) /*!< 0x00000080 */
22502#define HRTIM_CPT2CR_EXEV6CPT HRTIM_CPT2CR_EXEV6CPT_Msk /*!< External event 6 capture */
22503#define HRTIM_CPT2CR_EXEV7CPT_Pos (8U)
22504#define HRTIM_CPT2CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos) /*!< 0x00000100 */
22505#define HRTIM_CPT2CR_EXEV7CPT HRTIM_CPT2CR_EXEV7CPT_Msk /*!< External event 7 capture */
22506#define HRTIM_CPT2CR_EXEV8CPT_Pos (9U)
22507#define HRTIM_CPT2CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos) /*!< 0x00000200 */
22508#define HRTIM_CPT2CR_EXEV8CPT HRTIM_CPT2CR_EXEV8CPT_Msk /*!< External event 8 capture */
22509#define HRTIM_CPT2CR_EXEV9CPT_Pos (10U)
22510#define HRTIM_CPT2CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos) /*!< 0x00000400 */
22511#define HRTIM_CPT2CR_EXEV9CPT HRTIM_CPT2CR_EXEV9CPT_Msk /*!< External event 9 capture */
22512#define HRTIM_CPT2CR_EXEV10CPT_Pos (11U)
22513#define HRTIM_CPT2CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos) /*!< 0x00000800 */
22514#define HRTIM_CPT2CR_EXEV10CPT HRTIM_CPT2CR_EXEV10CPT_Msk /*!< External event 10 capture */
22515
22516#define HRTIM_CPT2CR_TA1SET_Pos (12U)
22517#define HRTIM_CPT2CR_TA1SET_Msk (0x1UL << HRTIM_CPT2CR_TA1SET_Pos) /*!< 0x00001000 */
22518#define HRTIM_CPT2CR_TA1SET HRTIM_CPT2CR_TA1SET_Msk /*!< Timer A output 1 set */
22519#define HRTIM_CPT2CR_TA1RST_Pos (13U)
22520#define HRTIM_CPT2CR_TA1RST_Msk (0x1UL << HRTIM_CPT2CR_TA1RST_Pos) /*!< 0x00002000 */
22521#define HRTIM_CPT2CR_TA1RST HRTIM_CPT2CR_TA1RST_Msk /*!< Timer A output 1 reset */
22522#define HRTIM_CPT2CR_TIMACMP1_Pos (14U)
22523#define HRTIM_CPT2CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos) /*!< 0x00004000 */
22524#define HRTIM_CPT2CR_TIMACMP1 HRTIM_CPT2CR_TIMACMP1_Msk /*!< Timer A compare 1 */
22525#define HRTIM_CPT2CR_TIMACMP2_Pos (15U)
22526#define HRTIM_CPT2CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos) /*!< 0x00008000 */
22527#define HRTIM_CPT2CR_TIMACMP2 HRTIM_CPT2CR_TIMACMP2_Msk /*!< Timer A compare 2 */
22528
22529#define HRTIM_CPT2CR_TB1SET_Pos (16U)
22530#define HRTIM_CPT2CR_TB1SET_Msk (0x1UL << HRTIM_CPT2CR_TB1SET_Pos) /*!< 0x00010000 */
22531#define HRTIM_CPT2CR_TB1SET HRTIM_CPT2CR_TB1SET_Msk /*!< Timer B output 1 set */
22532#define HRTIM_CPT2CR_TB1RST_Pos (17U)
22533#define HRTIM_CPT2CR_TB1RST_Msk (0x1UL << HRTIM_CPT2CR_TB1RST_Pos) /*!< 0x00020000 */
22534#define HRTIM_CPT2CR_TB1RST HRTIM_CPT2CR_TB1RST_Msk /*!< Timer B output 1 reset */
22535#define HRTIM_CPT2CR_TIMBCMP1_Pos (18U)
22536#define HRTIM_CPT2CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos) /*!< 0x00040000 */
22537#define HRTIM_CPT2CR_TIMBCMP1 HRTIM_CPT2CR_TIMBCMP1_Msk /*!< Timer B compare 1 */
22538#define HRTIM_CPT2CR_TIMBCMP2_Pos (19U)
22539#define HRTIM_CPT2CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos) /*!< 0x00080000 */
22540#define HRTIM_CPT2CR_TIMBCMP2 HRTIM_CPT2CR_TIMBCMP2_Msk /*!< Timer B compare 2 */
22541
22542#define HRTIM_CPT2CR_TC1SET_Pos (20U)
22543#define HRTIM_CPT2CR_TC1SET_Msk (0x1UL << HRTIM_CPT2CR_TC1SET_Pos) /*!< 0x00100000 */
22544#define HRTIM_CPT2CR_TC1SET HRTIM_CPT2CR_TC1SET_Msk /*!< Timer C output 1 set */
22545#define HRTIM_CPT2CR_TC1RST_Pos (21U)
22546#define HRTIM_CPT2CR_TC1RST_Msk (0x1UL << HRTIM_CPT2CR_TC1RST_Pos) /*!< 0x00200000 */
22547#define HRTIM_CPT2CR_TC1RST HRTIM_CPT2CR_TC1RST_Msk /*!< Timer C output 1 reset */
22548#define HRTIM_CPT2CR_TIMCCMP1_Pos (22U)
22549#define HRTIM_CPT2CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos) /*!< 0x00400000 */
22550#define HRTIM_CPT2CR_TIMCCMP1 HRTIM_CPT2CR_TIMCCMP1_Msk /*!< Timer C compare 1 */
22551#define HRTIM_CPT2CR_TIMCCMP2_Pos (23U)
22552#define HRTIM_CPT2CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos) /*!< 0x00800000 */
22553#define HRTIM_CPT2CR_TIMCCMP2 HRTIM_CPT2CR_TIMCCMP2_Msk /*!< Timer C compare 2 */
22554
22555#define HRTIM_CPT2CR_TD1SET_Pos (24U)
22556#define HRTIM_CPT2CR_TD1SET_Msk (0x1UL << HRTIM_CPT2CR_TD1SET_Pos) /*!< 0x01000000 */
22557#define HRTIM_CPT2CR_TD1SET HRTIM_CPT2CR_TD1SET_Msk /*!< Timer D output 1 set */
22558#define HRTIM_CPT2CR_TD1RST_Pos (25U)
22559#define HRTIM_CPT2CR_TD1RST_Msk (0x1UL << HRTIM_CPT2CR_TD1RST_Pos) /*!< 0x02000000 */
22560#define HRTIM_CPT2CR_TD1RST HRTIM_CPT2CR_TD1RST_Msk /*!< Timer D output 1 reset */
22561#define HRTIM_CPT2CR_TIMDCMP1_Pos (26U)
22562#define HRTIM_CPT2CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos) /*!< 0x04000000 */
22563#define HRTIM_CPT2CR_TIMDCMP1 HRTIM_CPT2CR_TIMDCMP1_Msk /*!< Timer D compare 1 */
22564#define HRTIM_CPT2CR_TIMDCMP2_Pos (27U)
22565#define HRTIM_CPT2CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos) /*!< 0x08000000 */
22566#define HRTIM_CPT2CR_TIMDCMP2 HRTIM_CPT2CR_TIMDCMP2_Msk /*!< Timer D compare 2 */
22567
22568#define HRTIM_CPT2CR_TE1SET_Pos (28U)
22569#define HRTIM_CPT2CR_TE1SET_Msk (0x1UL << HRTIM_CPT2CR_TE1SET_Pos) /*!< 0x10000000 */
22570#define HRTIM_CPT2CR_TE1SET HRTIM_CPT2CR_TE1SET_Msk /*!< Timer E output 1 set */
22571#define HRTIM_CPT2CR_TE1RST_Pos (29U)
22572#define HRTIM_CPT2CR_TE1RST_Msk (0x1UL << HRTIM_CPT2CR_TE1RST_Pos) /*!< 0x20000000 */
22573#define HRTIM_CPT2CR_TE1RST HRTIM_CPT2CR_TE1RST_Msk /*!< Timer E output 1 reset */
22574#define HRTIM_CPT2CR_TIMECMP1_Pos (30U)
22575#define HRTIM_CPT2CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos) /*!< 0x40000000 */
22576#define HRTIM_CPT2CR_TIMECMP1 HRTIM_CPT2CR_TIMECMP1_Msk /*!< Timer E compare 1 */
22577#define HRTIM_CPT2CR_TIMECMP2_Pos (31U)
22578#define HRTIM_CPT2CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos) /*!< 0x80000000 */
22579#define HRTIM_CPT2CR_TIMECMP2 HRTIM_CPT2CR_TIMECMP2_Msk /*!< Timer E compare 2 */
22580
22581/**** Bit definition for Slave Timer Output register **************************/
22582#define HRTIM_OUTR_POL1_Pos (1U)
22583#define HRTIM_OUTR_POL1_Msk (0x1UL << HRTIM_OUTR_POL1_Pos) /*!< 0x00000002 */
22584#define HRTIM_OUTR_POL1 HRTIM_OUTR_POL1_Msk /*!< Slave output 1 polarity */
22585#define HRTIM_OUTR_IDLM1_Pos (2U)
22586#define HRTIM_OUTR_IDLM1_Msk (0x1UL << HRTIM_OUTR_IDLM1_Pos) /*!< 0x00000004 */
22587#define HRTIM_OUTR_IDLM1 HRTIM_OUTR_IDLM1_Msk /*!< Slave output 1 idle mode */
22588#define HRTIM_OUTR_IDLES1_Pos (3U)
22589#define HRTIM_OUTR_IDLES1_Msk (0x1UL << HRTIM_OUTR_IDLES1_Pos) /*!< 0x00000008 */
22590#define HRTIM_OUTR_IDLES1 HRTIM_OUTR_IDLES1_Msk /*!< Slave output 1 idle state */
22591#define HRTIM_OUTR_FAULT1_Pos (4U)
22592#define HRTIM_OUTR_FAULT1_Msk (0x3UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000030 */
22593#define HRTIM_OUTR_FAULT1 HRTIM_OUTR_FAULT1_Msk /*!< Slave output 1 fault state */
22594#define HRTIM_OUTR_FAULT1_0 (0x1UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000010 */
22595#define HRTIM_OUTR_FAULT1_1 (0x2UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000020 */
22596#define HRTIM_OUTR_CHP1_Pos (6U)
22597#define HRTIM_OUTR_CHP1_Msk (0x1UL << HRTIM_OUTR_CHP1_Pos) /*!< 0x00000040 */
22598#define HRTIM_OUTR_CHP1 HRTIM_OUTR_CHP1_Msk /*!< Slave output 1 chopper enable */
22599#define HRTIM_OUTR_DIDL1_Pos (7U)
22600#define HRTIM_OUTR_DIDL1_Msk (0x1UL << HRTIM_OUTR_DIDL1_Pos) /*!< 0x00000080 */
22601#define HRTIM_OUTR_DIDL1 HRTIM_OUTR_DIDL1_Msk /*!< Slave output 1 dead time idle */
22602
22603#define HRTIM_OUTR_DTEN_Pos (8U)
22604#define HRTIM_OUTR_DTEN_Msk (0x1UL << HRTIM_OUTR_DTEN_Pos) /*!< 0x00000100 */
22605#define HRTIM_OUTR_DTEN HRTIM_OUTR_DTEN_Msk /*!< Slave output deadtime enable */
22606#define HRTIM_OUTR_DLYPRTEN_Pos (9U)
22607#define HRTIM_OUTR_DLYPRTEN_Msk (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos) /*!< 0x00000200 */
22608#define HRTIM_OUTR_DLYPRTEN HRTIM_OUTR_DLYPRTEN_Msk /*!< Slave output delay protection enable */
22609#define HRTIM_OUTR_DLYPRT_Pos (10U)
22610#define HRTIM_OUTR_DLYPRT_Msk (0x7UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001C00 */
22611#define HRTIM_OUTR_DLYPRT HRTIM_OUTR_DLYPRT_Msk /*!< Slave output delay protection */
22612#define HRTIM_OUTR_DLYPRT_0 (0x1UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000400 */
22613#define HRTIM_OUTR_DLYPRT_1 (0x2UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000800 */
22614#define HRTIM_OUTR_DLYPRT_2 (0x4UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001000 */
22615
22616#define HRTIM_OUTR_POL2_Pos (17U)
22617#define HRTIM_OUTR_POL2_Msk (0x1UL << HRTIM_OUTR_POL2_Pos) /*!< 0x00020000 */
22618#define HRTIM_OUTR_POL2 HRTIM_OUTR_POL2_Msk /*!< Slave output 2 polarity */
22619#define HRTIM_OUTR_IDLM2_Pos (18U)
22620#define HRTIM_OUTR_IDLM2_Msk (0x1UL << HRTIM_OUTR_IDLM2_Pos) /*!< 0x00040000 */
22621#define HRTIM_OUTR_IDLM2 HRTIM_OUTR_IDLM2_Msk /*!< Slave output 2 idle mode */
22622#define HRTIM_OUTR_IDLES2_Pos (19U)
22623#define HRTIM_OUTR_IDLES2_Msk (0x1UL << HRTIM_OUTR_IDLES2_Pos) /*!< 0x00080000 */
22624#define HRTIM_OUTR_IDLES2 HRTIM_OUTR_IDLES2_Msk /*!< Slave output 2 idle state */
22625#define HRTIM_OUTR_FAULT2_Pos (20U)
22626#define HRTIM_OUTR_FAULT2_Msk (0x3UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00300000 */
22627#define HRTIM_OUTR_FAULT2 HRTIM_OUTR_FAULT2_Msk /*!< Slave output 2 fault state */
22628#define HRTIM_OUTR_FAULT2_0 (0x1UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00100000 */
22629#define HRTIM_OUTR_FAULT2_1 (0x2UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00200000 */
22630#define HRTIM_OUTR_CHP2_Pos (22U)
22631#define HRTIM_OUTR_CHP2_Msk (0x1UL << HRTIM_OUTR_CHP2_Pos) /*!< 0x00400000 */
22632#define HRTIM_OUTR_CHP2 HRTIM_OUTR_CHP2_Msk /*!< Slave output 2 chopper enable */
22633#define HRTIM_OUTR_DIDL2_Pos (23U)
22634#define HRTIM_OUTR_DIDL2_Msk (0x1UL << HRTIM_OUTR_DIDL2_Pos) /*!< 0x00800000 */
22635#define HRTIM_OUTR_DIDL2 HRTIM_OUTR_DIDL2_Msk /*!< Slave output 2 dead time idle */
22636
22637/**** Bit definition for Slave Timer Fault register ***************************/
22638#define HRTIM_FLTR_FLT1EN_Pos (0U)
22639#define HRTIM_FLTR_FLT1EN_Msk (0x1UL << HRTIM_FLTR_FLT1EN_Pos) /*!< 0x00000001 */
22640#define HRTIM_FLTR_FLT1EN HRTIM_FLTR_FLT1EN_Msk /*!< Fault 1 enable */
22641#define HRTIM_FLTR_FLT2EN_Pos (1U)
22642#define HRTIM_FLTR_FLT2EN_Msk (0x1UL << HRTIM_FLTR_FLT2EN_Pos) /*!< 0x00000002 */
22643#define HRTIM_FLTR_FLT2EN HRTIM_FLTR_FLT2EN_Msk /*!< Fault 2 enable */
22644#define HRTIM_FLTR_FLT3EN_Pos (2U)
22645#define HRTIM_FLTR_FLT3EN_Msk (0x1UL << HRTIM_FLTR_FLT3EN_Pos) /*!< 0x00000004 */
22646#define HRTIM_FLTR_FLT3EN HRTIM_FLTR_FLT3EN_Msk /*!< Fault 3 enable */
22647#define HRTIM_FLTR_FLT4EN_Pos (3U)
22648#define HRTIM_FLTR_FLT4EN_Msk (0x1UL << HRTIM_FLTR_FLT4EN_Pos) /*!< 0x00000008 */
22649#define HRTIM_FLTR_FLT4EN HRTIM_FLTR_FLT4EN_Msk /*!< Fault 4 enable */
22650#define HRTIM_FLTR_FLT5EN_Pos (4U)
22651#define HRTIM_FLTR_FLT5EN_Msk (0x1UL << HRTIM_FLTR_FLT5EN_Pos) /*!< 0x00000010 */
22652#define HRTIM_FLTR_FLT5EN HRTIM_FLTR_FLT5EN_Msk /*!< Fault 5 enable */
22653#define HRTIM_FLTR_FLTLCK_Pos (31U)
22654#define HRTIM_FLTR_FLTLCK_Msk (0x1UL << HRTIM_FLTR_FLTLCK_Pos) /*!< 0x80000000 */
22655#define HRTIM_FLTR_FLTLCK HRTIM_FLTR_FLTLCK_Msk /*!< Fault sources lock */
22656
22657/**** Bit definition for Common HRTIM Timer control register 1 ****************/
22658#define HRTIM_CR1_MUDIS_Pos (0U)
22659#define HRTIM_CR1_MUDIS_Msk (0x1UL << HRTIM_CR1_MUDIS_Pos) /*!< 0x00000001 */
22660#define HRTIM_CR1_MUDIS HRTIM_CR1_MUDIS_Msk /*!< Master update disable*/
22661#define HRTIM_CR1_TAUDIS_Pos (1U)
22662#define HRTIM_CR1_TAUDIS_Msk (0x1UL << HRTIM_CR1_TAUDIS_Pos) /*!< 0x00000002 */
22663#define HRTIM_CR1_TAUDIS HRTIM_CR1_TAUDIS_Msk /*!< Timer A update disable*/
22664#define HRTIM_CR1_TBUDIS_Pos (2U)
22665#define HRTIM_CR1_TBUDIS_Msk (0x1UL << HRTIM_CR1_TBUDIS_Pos) /*!< 0x00000004 */
22666#define HRTIM_CR1_TBUDIS HRTIM_CR1_TBUDIS_Msk /*!< Timer B update disable*/
22667#define HRTIM_CR1_TCUDIS_Pos (3U)
22668#define HRTIM_CR1_TCUDIS_Msk (0x1UL << HRTIM_CR1_TCUDIS_Pos) /*!< 0x00000008 */
22669#define HRTIM_CR1_TCUDIS HRTIM_CR1_TCUDIS_Msk /*!< Timer C update disable*/
22670#define HRTIM_CR1_TDUDIS_Pos (4U)
22671#define HRTIM_CR1_TDUDIS_Msk (0x1UL << HRTIM_CR1_TDUDIS_Pos) /*!< 0x00000010 */
22672#define HRTIM_CR1_TDUDIS HRTIM_CR1_TDUDIS_Msk /*!< Timer D update disable*/
22673#define HRTIM_CR1_TEUDIS_Pos (5U)
22674#define HRTIM_CR1_TEUDIS_Msk (0x1UL << HRTIM_CR1_TEUDIS_Pos) /*!< 0x00000020 */
22675#define HRTIM_CR1_TEUDIS HRTIM_CR1_TEUDIS_Msk /*!< Timer E update disable*/
22676#define HRTIM_CR1_ADC1USRC_Pos (16U)
22677#define HRTIM_CR1_ADC1USRC_Msk (0x7UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00070000 */
22678#define HRTIM_CR1_ADC1USRC HRTIM_CR1_ADC1USRC_Msk /*!< ADC Trigger 1 update source */
22679#define HRTIM_CR1_ADC1USRC_0 (0x1UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00010000 */
22680#define HRTIM_CR1_ADC1USRC_1 (0x2UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00020000 */
22681#define HRTIM_CR1_ADC1USRC_2 (0x4UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00040000 */
22682#define HRTIM_CR1_ADC2USRC_Pos (19U)
22683#define HRTIM_CR1_ADC2USRC_Msk (0x7UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00380000 */
22684#define HRTIM_CR1_ADC2USRC HRTIM_CR1_ADC2USRC_Msk /*!< ADC Trigger 2 update source */
22685#define HRTIM_CR1_ADC2USRC_0 (0x1UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00080000 */
22686#define HRTIM_CR1_ADC2USRC_1 (0x2UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00100000 */
22687#define HRTIM_CR1_ADC2USRC_2 (0x4UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00200000 */
22688#define HRTIM_CR1_ADC3USRC_Pos (22U)
22689#define HRTIM_CR1_ADC3USRC_Msk (0x7UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01C00000 */
22690#define HRTIM_CR1_ADC3USRC HRTIM_CR1_ADC3USRC_Msk /*!< ADC Trigger 3 update source */
22691#define HRTIM_CR1_ADC3USRC_0 (0x1UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00400000 */
22692#define HRTIM_CR1_ADC3USRC_1 (0x2UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00800000 */
22693#define HRTIM_CR1_ADC3USRC_2 (0x4UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01000000 */
22694#define HRTIM_CR1_ADC4USRC_Pos (25U)
22695#define HRTIM_CR1_ADC4USRC_Msk (0x7UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0E000000 */
22696#define HRTIM_CR1_ADC4USRC HRTIM_CR1_ADC4USRC_Msk /*!< ADC Trigger 4 update source */
22697#define HRTIM_CR1_ADC4USRC_0 (0x1UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x02000000 */
22698#define HRTIM_CR1_ADC4USRC_1 (0x2UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x04000000 */
22699#define HRTIM_CR1_ADC4USRC_2 (0x0UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0800000 */
22700
22701/**** Bit definition for Common HRTIM Timer control register 2 ****************/
22702#define HRTIM_CR2_MSWU_Pos (0U)
22703#define HRTIM_CR2_MSWU_Msk (0x1UL << HRTIM_CR2_MSWU_Pos) /*!< 0x00000001 */
22704#define HRTIM_CR2_MSWU HRTIM_CR2_MSWU_Msk /*!< Master software update */
22705#define HRTIM_CR2_TASWU_Pos (1U)
22706#define HRTIM_CR2_TASWU_Msk (0x1UL << HRTIM_CR2_TASWU_Pos) /*!< 0x00000002 */
22707#define HRTIM_CR2_TASWU HRTIM_CR2_TASWU_Msk /*!< Timer A software update */
22708#define HRTIM_CR2_TBSWU_Pos (2U)
22709#define HRTIM_CR2_TBSWU_Msk (0x1UL << HRTIM_CR2_TBSWU_Pos) /*!< 0x00000004 */
22710#define HRTIM_CR2_TBSWU HRTIM_CR2_TBSWU_Msk /*!< Timer B software update */
22711#define HRTIM_CR2_TCSWU_Pos (3U)
22712#define HRTIM_CR2_TCSWU_Msk (0x1UL << HRTIM_CR2_TCSWU_Pos) /*!< 0x00000008 */
22713#define HRTIM_CR2_TCSWU HRTIM_CR2_TCSWU_Msk /*!< Timer C software update */
22714#define HRTIM_CR2_TDSWU_Pos (4U)
22715#define HRTIM_CR2_TDSWU_Msk (0x1UL << HRTIM_CR2_TDSWU_Pos) /*!< 0x00000010 */
22716#define HRTIM_CR2_TDSWU HRTIM_CR2_TDSWU_Msk /*!< Timer D software update */
22717#define HRTIM_CR2_TESWU_Pos (5U)
22718#define HRTIM_CR2_TESWU_Msk (0x1UL << HRTIM_CR2_TESWU_Pos) /*!< 0x00000020 */
22719#define HRTIM_CR2_TESWU HRTIM_CR2_TESWU_Msk /*!< Timer E software update */
22720#define HRTIM_CR2_MRST_Pos (8U)
22721#define HRTIM_CR2_MRST_Msk (0x1UL << HRTIM_CR2_MRST_Pos) /*!< 0x00000100 */
22722#define HRTIM_CR2_MRST HRTIM_CR2_MRST_Msk /*!< Master count software reset */
22723#define HRTIM_CR2_TARST_Pos (9U)
22724#define HRTIM_CR2_TARST_Msk (0x1UL << HRTIM_CR2_TARST_Pos) /*!< 0x00000200 */
22725#define HRTIM_CR2_TARST HRTIM_CR2_TARST_Msk /*!< Timer A count software reset */
22726#define HRTIM_CR2_TBRST_Pos (10U)
22727#define HRTIM_CR2_TBRST_Msk (0x1UL << HRTIM_CR2_TBRST_Pos) /*!< 0x00000400 */
22728#define HRTIM_CR2_TBRST HRTIM_CR2_TBRST_Msk /*!< Timer B count software reset */
22729#define HRTIM_CR2_TCRST_Pos (11U)
22730#define HRTIM_CR2_TCRST_Msk (0x1UL << HRTIM_CR2_TCRST_Pos) /*!< 0x00000800 */
22731#define HRTIM_CR2_TCRST HRTIM_CR2_TCRST_Msk /*!< Timer C count software reset */
22732#define HRTIM_CR2_TDRST_Pos (12U)
22733#define HRTIM_CR2_TDRST_Msk (0x1UL << HRTIM_CR2_TDRST_Pos) /*!< 0x00001000 */
22734#define HRTIM_CR2_TDRST HRTIM_CR2_TDRST_Msk /*!< Timer D count software reset */
22735#define HRTIM_CR2_TERST_Pos (13U)
22736#define HRTIM_CR2_TERST_Msk (0x1UL << HRTIM_CR2_TERST_Pos) /*!< 0x00002000 */
22737#define HRTIM_CR2_TERST HRTIM_CR2_TERST_Msk /*!< Timer E count software reset */
22738
22739/**** Bit definition for Common HRTIM Timer interrupt status register *********/
22740#define HRTIM_ISR_FLT1_Pos (0U)
22741#define HRTIM_ISR_FLT1_Msk (0x1UL << HRTIM_ISR_FLT1_Pos) /*!< 0x00000001 */
22742#define HRTIM_ISR_FLT1 HRTIM_ISR_FLT1_Msk /*!< Fault 1 interrupt flag */
22743#define HRTIM_ISR_FLT2_Pos (1U)
22744#define HRTIM_ISR_FLT2_Msk (0x1UL << HRTIM_ISR_FLT2_Pos) /*!< 0x00000002 */
22745#define HRTIM_ISR_FLT2 HRTIM_ISR_FLT2_Msk /*!< Fault 2 interrupt flag */
22746#define HRTIM_ISR_FLT3_Pos (2U)
22747#define HRTIM_ISR_FLT3_Msk (0x1UL << HRTIM_ISR_FLT3_Pos) /*!< 0x00000004 */
22748#define HRTIM_ISR_FLT3 HRTIM_ISR_FLT3_Msk /*!< Fault 3 interrupt flag */
22749#define HRTIM_ISR_FLT4_Pos (3U)
22750#define HRTIM_ISR_FLT4_Msk (0x1UL << HRTIM_ISR_FLT4_Pos) /*!< 0x00000008 */
22751#define HRTIM_ISR_FLT4 HRTIM_ISR_FLT4_Msk /*!< Fault 4 interrupt flag */
22752#define HRTIM_ISR_FLT5_Pos (4U)
22753#define HRTIM_ISR_FLT5_Msk (0x1UL << HRTIM_ISR_FLT5_Pos) /*!< 0x00000010 */
22754#define HRTIM_ISR_FLT5 HRTIM_ISR_FLT5_Msk /*!< Fault 5 interrupt flag */
22755#define HRTIM_ISR_SYSFLT_Pos (5U)
22756#define HRTIM_ISR_SYSFLT_Msk (0x1UL << HRTIM_ISR_SYSFLT_Pos) /*!< 0x00000020 */
22757#define HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT_Msk /*!< System Fault interrupt flag */
22758#define HRTIM_ISR_BMPER_Pos (17U)
22759#define HRTIM_ISR_BMPER_Msk (0x1UL << HRTIM_ISR_BMPER_Pos) /*!< 0x00020000 */
22760#define HRTIM_ISR_BMPER HRTIM_ISR_BMPER_Msk /*!< Burst mode period interrupt flag */
22761
22762/**** Bit definition for Common HRTIM Timer interrupt clear register **********/
22763#define HRTIM_ICR_FLT1C_Pos (0U)
22764#define HRTIM_ICR_FLT1C_Msk (0x1UL << HRTIM_ICR_FLT1C_Pos) /*!< 0x00000001 */
22765#define HRTIM_ICR_FLT1C HRTIM_ICR_FLT1C_Msk /*!< Fault 1 interrupt flag clear */
22766#define HRTIM_ICR_FLT2C_Pos (1U)
22767#define HRTIM_ICR_FLT2C_Msk (0x1UL << HRTIM_ICR_FLT2C_Pos) /*!< 0x00000002 */
22768#define HRTIM_ICR_FLT2C HRTIM_ICR_FLT2C_Msk /*!< Fault 2 interrupt flag clear */
22769#define HRTIM_ICR_FLT3C_Pos (2U)
22770#define HRTIM_ICR_FLT3C_Msk (0x1UL << HRTIM_ICR_FLT3C_Pos) /*!< 0x00000004 */
22771#define HRTIM_ICR_FLT3C HRTIM_ICR_FLT3C_Msk /*!< Fault 3 interrupt flag clear */
22772#define HRTIM_ICR_FLT4C_Pos (3U)
22773#define HRTIM_ICR_FLT4C_Msk (0x1UL << HRTIM_ICR_FLT4C_Pos) /*!< 0x00000008 */
22774#define HRTIM_ICR_FLT4C HRTIM_ICR_FLT4C_Msk /*!< Fault 4 interrupt flag clear */
22775#define HRTIM_ICR_FLT5C_Pos (4U)
22776#define HRTIM_ICR_FLT5C_Msk (0x1UL << HRTIM_ICR_FLT5C_Pos) /*!< 0x00000010 */
22777#define HRTIM_ICR_FLT5C HRTIM_ICR_FLT5C_Msk /*!< Fault 5 interrupt flag clear */
22778#define HRTIM_ICR_SYSFLTC_Pos (5U)
22779#define HRTIM_ICR_SYSFLTC_Msk (0x1UL << HRTIM_ICR_SYSFLTC_Pos) /*!< 0x00000020 */
22780#define HRTIM_ICR_SYSFLTC HRTIM_ICR_SYSFLTC_Msk /*!< System Fault interrupt flag clear */
22781#define HRTIM_ICR_BMPERC_Pos (17U)
22782#define HRTIM_ICR_BMPERC_Msk (0x1UL << HRTIM_ICR_BMPERC_Pos) /*!< 0x00020000 */
22783#define HRTIM_ICR_BMPERC HRTIM_ICR_BMPERC_Msk /*!< Burst mode period interrupt flag clear */
22784
22785/**** Bit definition for Common HRTIM Timer interrupt enable register *********/
22786#define HRTIM_IER_FLT1_Pos (0U)
22787#define HRTIM_IER_FLT1_Msk (0x1UL << HRTIM_IER_FLT1_Pos) /*!< 0x00000001 */
22788#define HRTIM_IER_FLT1 HRTIM_IER_FLT1_Msk /*!< Fault 1 interrupt enable */
22789#define HRTIM_IER_FLT2_Pos (1U)
22790#define HRTIM_IER_FLT2_Msk (0x1UL << HRTIM_IER_FLT2_Pos) /*!< 0x00000002 */
22791#define HRTIM_IER_FLT2 HRTIM_IER_FLT2_Msk /*!< Fault 2 interrupt enable */
22792#define HRTIM_IER_FLT3_Pos (2U)
22793#define HRTIM_IER_FLT3_Msk (0x1UL << HRTIM_IER_FLT3_Pos) /*!< 0x00000004 */
22794#define HRTIM_IER_FLT3 HRTIM_IER_FLT3_Msk /*!< Fault 3 interrupt enable */
22795#define HRTIM_IER_FLT4_Pos (3U)
22796#define HRTIM_IER_FLT4_Msk (0x1UL << HRTIM_IER_FLT4_Pos) /*!< 0x00000008 */
22797#define HRTIM_IER_FLT4 HRTIM_IER_FLT4_Msk /*!< Fault 4 interrupt enable */
22798#define HRTIM_IER_FLT5_Pos (4U)
22799#define HRTIM_IER_FLT5_Msk (0x1UL << HRTIM_IER_FLT5_Pos) /*!< 0x00000010 */
22800#define HRTIM_IER_FLT5 HRTIM_IER_FLT5_Msk /*!< Fault 5 interrupt enable */
22801#define HRTIM_IER_SYSFLT_Pos (5U)
22802#define HRTIM_IER_SYSFLT_Msk (0x1UL << HRTIM_IER_SYSFLT_Pos) /*!< 0x00000020 */
22803#define HRTIM_IER_SYSFLT HRTIM_IER_SYSFLT_Msk /*!< System Fault interrupt enable */
22804#define HRTIM_IER_BMPER_Pos (17U)
22805#define HRTIM_IER_BMPER_Msk (0x1UL << HRTIM_IER_BMPER_Pos) /*!< 0x00020000 */
22806#define HRTIM_IER_BMPER HRTIM_IER_BMPER_Msk /*!< Burst mode period interrupt enable */
22807
22808/**** Bit definition for Common HRTIM Timer output enable register ************/
22809#define HRTIM_OENR_TA1OEN_Pos (0U)
22810#define HRTIM_OENR_TA1OEN_Msk (0x1UL << HRTIM_OENR_TA1OEN_Pos) /*!< 0x00000001 */
22811#define HRTIM_OENR_TA1OEN HRTIM_OENR_TA1OEN_Msk /*!< Timer A Output 1 enable */
22812#define HRTIM_OENR_TA2OEN_Pos (1U)
22813#define HRTIM_OENR_TA2OEN_Msk (0x1UL << HRTIM_OENR_TA2OEN_Pos) /*!< 0x00000002 */
22814#define HRTIM_OENR_TA2OEN HRTIM_OENR_TA2OEN_Msk /*!< Timer A Output 2 enable */
22815#define HRTIM_OENR_TB1OEN_Pos (2U)
22816#define HRTIM_OENR_TB1OEN_Msk (0x1UL << HRTIM_OENR_TB1OEN_Pos) /*!< 0x00000004 */
22817#define HRTIM_OENR_TB1OEN HRTIM_OENR_TB1OEN_Msk /*!< Timer B Output 1 enable */
22818#define HRTIM_OENR_TB2OEN_Pos (3U)
22819#define HRTIM_OENR_TB2OEN_Msk (0x1UL << HRTIM_OENR_TB2OEN_Pos) /*!< 0x00000008 */
22820#define HRTIM_OENR_TB2OEN HRTIM_OENR_TB2OEN_Msk /*!< Timer B Output 2 enable */
22821#define HRTIM_OENR_TC1OEN_Pos (4U)
22822#define HRTIM_OENR_TC1OEN_Msk (0x1UL << HRTIM_OENR_TC1OEN_Pos) /*!< 0x00000010 */
22823#define HRTIM_OENR_TC1OEN HRTIM_OENR_TC1OEN_Msk /*!< Timer C Output 1 enable */
22824#define HRTIM_OENR_TC2OEN_Pos (5U)
22825#define HRTIM_OENR_TC2OEN_Msk (0x1UL << HRTIM_OENR_TC2OEN_Pos) /*!< 0x00000020 */
22826#define HRTIM_OENR_TC2OEN HRTIM_OENR_TC2OEN_Msk /*!< Timer C Output 2 enable */
22827#define HRTIM_OENR_TD1OEN_Pos (6U)
22828#define HRTIM_OENR_TD1OEN_Msk (0x1UL << HRTIM_OENR_TD1OEN_Pos) /*!< 0x00000040 */
22829#define HRTIM_OENR_TD1OEN HRTIM_OENR_TD1OEN_Msk /*!< Timer D Output 1 enable */
22830#define HRTIM_OENR_TD2OEN_Pos (7U)
22831#define HRTIM_OENR_TD2OEN_Msk (0x1UL << HRTIM_OENR_TD2OEN_Pos) /*!< 0x00000080 */
22832#define HRTIM_OENR_TD2OEN HRTIM_OENR_TD2OEN_Msk /*!< Timer D Output 2 enable */
22833#define HRTIM_OENR_TE1OEN_Pos (8U)
22834#define HRTIM_OENR_TE1OEN_Msk (0x1UL << HRTIM_OENR_TE1OEN_Pos) /*!< 0x00000100 */
22835#define HRTIM_OENR_TE1OEN HRTIM_OENR_TE1OEN_Msk /*!< Timer E Output 1 enable */
22836#define HRTIM_OENR_TE2OEN_Pos (9U)
22837#define HRTIM_OENR_TE2OEN_Msk (0x1UL << HRTIM_OENR_TE2OEN_Pos) /*!< 0x00000200 */
22838#define HRTIM_OENR_TE2OEN HRTIM_OENR_TE2OEN_Msk /*!< Timer E Output 2 enable */
22839
22840/**** Bit definition for Common HRTIM Timer output disable register ***********/
22841#define HRTIM_ODISR_TA1ODIS_Pos (0U)
22842#define HRTIM_ODISR_TA1ODIS_Msk (0x1UL << HRTIM_ODISR_TA1ODIS_Pos) /*!< 0x00000001 */
22843#define HRTIM_ODISR_TA1ODIS HRTIM_ODISR_TA1ODIS_Msk /*!< Timer A Output 1 disable */
22844#define HRTIM_ODISR_TA2ODIS_Pos (1U)
22845#define HRTIM_ODISR_TA2ODIS_Msk (0x1UL << HRTIM_ODISR_TA2ODIS_Pos) /*!< 0x00000002 */
22846#define HRTIM_ODISR_TA2ODIS HRTIM_ODISR_TA2ODIS_Msk /*!< Timer A Output 2 disable */
22847#define HRTIM_ODISR_TB1ODIS_Pos (2U)
22848#define HRTIM_ODISR_TB1ODIS_Msk (0x1UL << HRTIM_ODISR_TB1ODIS_Pos) /*!< 0x00000004 */
22849#define HRTIM_ODISR_TB1ODIS HRTIM_ODISR_TB1ODIS_Msk /*!< Timer B Output 1 disable */
22850#define HRTIM_ODISR_TB2ODIS_Pos (3U)
22851#define HRTIM_ODISR_TB2ODIS_Msk (0x1UL << HRTIM_ODISR_TB2ODIS_Pos) /*!< 0x00000008 */
22852#define HRTIM_ODISR_TB2ODIS HRTIM_ODISR_TB2ODIS_Msk /*!< Timer B Output 2 disable */
22853#define HRTIM_ODISR_TC1ODIS_Pos (4U)
22854#define HRTIM_ODISR_TC1ODIS_Msk (0x1UL << HRTIM_ODISR_TC1ODIS_Pos) /*!< 0x00000010 */
22855#define HRTIM_ODISR_TC1ODIS HRTIM_ODISR_TC1ODIS_Msk /*!< Timer C Output 1 disable */
22856#define HRTIM_ODISR_TC2ODIS_Pos (5U)
22857#define HRTIM_ODISR_TC2ODIS_Msk (0x1UL << HRTIM_ODISR_TC2ODIS_Pos) /*!< 0x00000020 */
22858#define HRTIM_ODISR_TC2ODIS HRTIM_ODISR_TC2ODIS_Msk /*!< Timer C Output 2 disable */
22859#define HRTIM_ODISR_TD1ODIS_Pos (6U)
22860#define HRTIM_ODISR_TD1ODIS_Msk (0x1UL << HRTIM_ODISR_TD1ODIS_Pos) /*!< 0x00000040 */
22861#define HRTIM_ODISR_TD1ODIS HRTIM_ODISR_TD1ODIS_Msk /*!< Timer D Output 1 disable */
22862#define HRTIM_ODISR_TD2ODIS_Pos (7U)
22863#define HRTIM_ODISR_TD2ODIS_Msk (0x1UL << HRTIM_ODISR_TD2ODIS_Pos) /*!< 0x00000080 */
22864#define HRTIM_ODISR_TD2ODIS HRTIM_ODISR_TD2ODIS_Msk /*!< Timer D Output 2 disable */
22865#define HRTIM_ODISR_TE1ODIS_Pos (8U)
22866#define HRTIM_ODISR_TE1ODIS_Msk (0x1UL << HRTIM_ODISR_TE1ODIS_Pos) /*!< 0x00000100 */
22867#define HRTIM_ODISR_TE1ODIS HRTIM_ODISR_TE1ODIS_Msk /*!< Timer E Output 1 disable */
22868#define HRTIM_ODISR_TE2ODIS_Pos (9U)
22869#define HRTIM_ODISR_TE2ODIS_Msk (0x1UL << HRTIM_ODISR_TE2ODIS_Pos) /*!< 0x00000200 */
22870#define HRTIM_ODISR_TE2ODIS HRTIM_ODISR_TE2ODIS_Msk /*!< Timer E Output 2 disable */
22871
22872/**** Bit definition for Common HRTIM Timer output disable status register *****/
22873#define HRTIM_ODSR_TA1ODS_Pos (0U)
22874#define HRTIM_ODSR_TA1ODS_Msk (0x1UL << HRTIM_ODSR_TA1ODS_Pos) /*!< 0x00000001 */
22875#define HRTIM_ODSR_TA1ODS HRTIM_ODSR_TA1ODS_Msk /*!< Timer A Output 1 disable status */
22876#define HRTIM_ODSR_TA2ODS_Pos (1U)
22877#define HRTIM_ODSR_TA2ODS_Msk (0x1UL << HRTIM_ODSR_TA2ODS_Pos) /*!< 0x00000002 */
22878#define HRTIM_ODSR_TA2ODS HRTIM_ODSR_TA2ODS_Msk /*!< Timer A Output 2 disable status */
22879#define HRTIM_ODSR_TB1ODS_Pos (2U)
22880#define HRTIM_ODSR_TB1ODS_Msk (0x1UL << HRTIM_ODSR_TB1ODS_Pos) /*!< 0x00000004 */
22881#define HRTIM_ODSR_TB1ODS HRTIM_ODSR_TB1ODS_Msk /*!< Timer B Output 1 disable status */
22882#define HRTIM_ODSR_TB2ODS_Pos (3U)
22883#define HRTIM_ODSR_TB2ODS_Msk (0x1UL << HRTIM_ODSR_TB2ODS_Pos) /*!< 0x00000008 */
22884#define HRTIM_ODSR_TB2ODS HRTIM_ODSR_TB2ODS_Msk /*!< Timer B Output 2 disable status */
22885#define HRTIM_ODSR_TC1ODS_Pos (4U)
22886#define HRTIM_ODSR_TC1ODS_Msk (0x1UL << HRTIM_ODSR_TC1ODS_Pos) /*!< 0x00000010 */
22887#define HRTIM_ODSR_TC1ODS HRTIM_ODSR_TC1ODS_Msk /*!< Timer C Output 1 disable status */
22888#define HRTIM_ODSR_TC2ODS_Pos (5U)
22889#define HRTIM_ODSR_TC2ODS_Msk (0x1UL << HRTIM_ODSR_TC2ODS_Pos) /*!< 0x00000020 */
22890#define HRTIM_ODSR_TC2ODS HRTIM_ODSR_TC2ODS_Msk /*!< Timer C Output 2 disable status */
22891#define HRTIM_ODSR_TD1ODS_Pos (6U)
22892#define HRTIM_ODSR_TD1ODS_Msk (0x1UL << HRTIM_ODSR_TD1ODS_Pos) /*!< 0x00000040 */
22893#define HRTIM_ODSR_TD1ODS HRTIM_ODSR_TD1ODS_Msk /*!< Timer D Output 1 disable status */
22894#define HRTIM_ODSR_TD2ODS_Pos (7U)
22895#define HRTIM_ODSR_TD2ODS_Msk (0x1UL << HRTIM_ODSR_TD2ODS_Pos) /*!< 0x00000080 */
22896#define HRTIM_ODSR_TD2ODS HRTIM_ODSR_TD2ODS_Msk /*!< Timer D Output 2 disable status */
22897#define HRTIM_ODSR_TE1ODS_Pos (8U)
22898#define HRTIM_ODSR_TE1ODS_Msk (0x1UL << HRTIM_ODSR_TE1ODS_Pos) /*!< 0x00000100 */
22899#define HRTIM_ODSR_TE1ODS HRTIM_ODSR_TE1ODS_Msk /*!< Timer E Output 1 disable status */
22900#define HRTIM_ODSR_TE2ODS_Pos (9U)
22901#define HRTIM_ODSR_TE2ODS_Msk (0x1UL << HRTIM_ODSR_TE2ODS_Pos) /*!< 0x00000200 */
22902#define HRTIM_ODSR_TE2ODS HRTIM_ODSR_TE2ODS_Msk /*!< Timer E Output 2 disable status */
22903
22904/**** Bit definition for Common HRTIM Timer Burst mode control register ********/
22905#define HRTIM_BMCR_BME_Pos (0U)
22906#define HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos) /*!< 0x00000001 */
22907#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enbale */
22908#define HRTIM_BMCR_BMOM_Pos (1U)
22909#define HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos) /*!< 0x00000002 */
22910#define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk /*!< Burst mode operating mode */
22911#define HRTIM_BMCR_BMCLK_Pos (2U)
22912#define HRTIM_BMCR_BMCLK_Msk (0xFUL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x0000003C */
22913#define HRTIM_BMCR_BMCLK HRTIM_BMCR_BMCLK_Msk /*!< Burst mode clock source */
22914#define HRTIM_BMCR_BMCLK_0 (0x1UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000004 */
22915#define HRTIM_BMCR_BMCLK_1 (0x2UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000008 */
22916#define HRTIM_BMCR_BMCLK_2 (0x4UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000010 */
22917#define HRTIM_BMCR_BMCLK_3 (0x8UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000020 */
22918#define HRTIM_BMCR_BMPRSC_Pos (6U)
22919#define HRTIM_BMCR_BMPRSC_Msk (0xFUL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x000003C0 */
22920#define HRTIM_BMCR_BMPRSC HRTIM_BMCR_BMPRSC_Msk /*!< Burst mode prescaler */
22921#define HRTIM_BMCR_BMPRSC_0 (0x1UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000040 */
22922#define HRTIM_BMCR_BMPRSC_1 (0x2UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000080 */
22923#define HRTIM_BMCR_BMPRSC_2 (0x4UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000100 */
22924#define HRTIM_BMCR_BMPRSC_3 (0x8UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000200 */
22925#define HRTIM_BMCR_BMPREN_Pos (10U)
22926#define HRTIM_BMCR_BMPREN_Msk (0x1UL << HRTIM_BMCR_BMPREN_Pos) /*!< 0x00000400 */
22927#define HRTIM_BMCR_BMPREN HRTIM_BMCR_BMPREN_Msk /*!< Burst mode Preload bit */
22928#define HRTIM_BMCR_MTBM_Pos (16U)
22929#define HRTIM_BMCR_MTBM_Msk (0x1UL << HRTIM_BMCR_MTBM_Pos) /*!< 0x00010000 */
22930#define HRTIM_BMCR_MTBM HRTIM_BMCR_MTBM_Msk /*!< Master Timer Burst mode */
22931#define HRTIM_BMCR_TABM_Pos (17U)
22932#define HRTIM_BMCR_TABM_Msk (0x1UL << HRTIM_BMCR_TABM_Pos) /*!< 0x00020000 */
22933#define HRTIM_BMCR_TABM HRTIM_BMCR_TABM_Msk /*!< Timer A Burst mode */
22934#define HRTIM_BMCR_TBBM_Pos (18U)
22935#define HRTIM_BMCR_TBBM_Msk (0x1UL << HRTIM_BMCR_TBBM_Pos) /*!< 0x00040000 */
22936#define HRTIM_BMCR_TBBM HRTIM_BMCR_TBBM_Msk /*!< Timer B Burst mode */
22937#define HRTIM_BMCR_TCBM_Pos (19U)
22938#define HRTIM_BMCR_TCBM_Msk (0x1UL << HRTIM_BMCR_TCBM_Pos) /*!< 0x00080000 */
22939#define HRTIM_BMCR_TCBM HRTIM_BMCR_TCBM_Msk /*!< Timer C Burst mode */
22940#define HRTIM_BMCR_TDBM_Pos (20U)
22941#define HRTIM_BMCR_TDBM_Msk (0x1UL << HRTIM_BMCR_TDBM_Pos) /*!< 0x00100000 */
22942#define HRTIM_BMCR_TDBM HRTIM_BMCR_TDBM_Msk /*!< Timer D Burst mode */
22943#define HRTIM_BMCR_TEBM_Pos (21U)
22944#define HRTIM_BMCR_TEBM_Msk (0x1UL << HRTIM_BMCR_TEBM_Pos) /*!< 0x00200000 */
22945#define HRTIM_BMCR_TEBM HRTIM_BMCR_TEBM_Msk /*!< Timer E Burst mode */
22946#define HRTIM_BMCR_BMSTAT_Pos (31U)
22947#define HRTIM_BMCR_BMSTAT_Msk (0x1UL << HRTIM_BMCR_BMSTAT_Pos) /*!< 0x80000000 */
22948#define HRTIM_BMCR_BMSTAT HRTIM_BMCR_BMSTAT_Msk /*!< Burst mode status */
22949
22950/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
22951#define HRTIM_BMTRGR_SW_Pos (0U)
22952#define HRTIM_BMTRGR_SW_Msk (0x1UL << HRTIM_BMTRGR_SW_Pos) /*!< 0x00000001 */
22953#define HRTIM_BMTRGR_SW HRTIM_BMTRGR_SW_Msk /*!< Software start */
22954#define HRTIM_BMTRGR_MSTRST_Pos (1U)
22955#define HRTIM_BMTRGR_MSTRST_Msk (0x1UL << HRTIM_BMTRGR_MSTRST_Pos) /*!< 0x00000002 */
22956#define HRTIM_BMTRGR_MSTRST HRTIM_BMTRGR_MSTRST_Msk /*!< Master reset */
22957#define HRTIM_BMTRGR_MSTREP_Pos (2U)
22958#define HRTIM_BMTRGR_MSTREP_Msk (0x1UL << HRTIM_BMTRGR_MSTREP_Pos) /*!< 0x00000004 */
22959#define HRTIM_BMTRGR_MSTREP HRTIM_BMTRGR_MSTREP_Msk /*!< Master repetition */
22960#define HRTIM_BMTRGR_MSTCMP1_Pos (3U)
22961#define HRTIM_BMTRGR_MSTCMP1_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos) /*!< 0x00000008 */
22962#define HRTIM_BMTRGR_MSTCMP1 HRTIM_BMTRGR_MSTCMP1_Msk /*!< Master compare 1 */
22963#define HRTIM_BMTRGR_MSTCMP2_Pos (4U)
22964#define HRTIM_BMTRGR_MSTCMP2_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos) /*!< 0x00000010 */
22965#define HRTIM_BMTRGR_MSTCMP2 HRTIM_BMTRGR_MSTCMP2_Msk /*!< Master compare 2 */
22966#define HRTIM_BMTRGR_MSTCMP3_Pos (5U)
22967#define HRTIM_BMTRGR_MSTCMP3_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos) /*!< 0x00000020 */
22968#define HRTIM_BMTRGR_MSTCMP3 HRTIM_BMTRGR_MSTCMP3_Msk /*!< Master compare 3 */
22969#define HRTIM_BMTRGR_MSTCMP4_Pos (6U)
22970#define HRTIM_BMTRGR_MSTCMP4_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos) /*!< 0x00000040 */
22971#define HRTIM_BMTRGR_MSTCMP4 HRTIM_BMTRGR_MSTCMP4_Msk /*!< Master compare 4 */
22972#define HRTIM_BMTRGR_TARST_Pos (7U)
22973#define HRTIM_BMTRGR_TARST_Msk (0x1UL << HRTIM_BMTRGR_TARST_Pos) /*!< 0x00000080 */
22974#define HRTIM_BMTRGR_TARST HRTIM_BMTRGR_TARST_Msk /*!< Timer A reset */
22975#define HRTIM_BMTRGR_TAREP_Pos (8U)
22976#define HRTIM_BMTRGR_TAREP_Msk (0x1UL << HRTIM_BMTRGR_TAREP_Pos) /*!< 0x00000100 */
22977#define HRTIM_BMTRGR_TAREP HRTIM_BMTRGR_TAREP_Msk /*!< Timer A repetition */
22978#define HRTIM_BMTRGR_TACMP1_Pos (9U)
22979#define HRTIM_BMTRGR_TACMP1_Msk (0x1UL << HRTIM_BMTRGR_TACMP1_Pos) /*!< 0x00000200 */
22980#define HRTIM_BMTRGR_TACMP1 HRTIM_BMTRGR_TACMP1_Msk /*!< Timer A compare 1 */
22981#define HRTIM_BMTRGR_TACMP2_Pos (10U)
22982#define HRTIM_BMTRGR_TACMP2_Msk (0x1UL << HRTIM_BMTRGR_TACMP2_Pos) /*!< 0x00000400 */
22983#define HRTIM_BMTRGR_TACMP2 HRTIM_BMTRGR_TACMP2_Msk /*!< Timer A compare 2 */
22984#define HRTIM_BMTRGR_TBRST_Pos (11U)
22985#define HRTIM_BMTRGR_TBRST_Msk (0x1UL << HRTIM_BMTRGR_TBRST_Pos) /*!< 0x00000800 */
22986#define HRTIM_BMTRGR_TBRST HRTIM_BMTRGR_TBRST_Msk /*!< Timer B reset */
22987#define HRTIM_BMTRGR_TBREP_Pos (12U)
22988#define HRTIM_BMTRGR_TBREP_Msk (0x1UL << HRTIM_BMTRGR_TBREP_Pos) /*!< 0x00001000 */
22989#define HRTIM_BMTRGR_TBREP HRTIM_BMTRGR_TBREP_Msk /*!< Timer B repetition */
22990#define HRTIM_BMTRGR_TBCMP1_Pos (13U)
22991#define HRTIM_BMTRGR_TBCMP1_Msk (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos) /*!< 0x00002000 */
22992#define HRTIM_BMTRGR_TBCMP1 HRTIM_BMTRGR_TBCMP1_Msk /*!< Timer B compare 1 */
22993#define HRTIM_BMTRGR_TBCMP2_Pos (14U)
22994#define HRTIM_BMTRGR_TBCMP2_Msk (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos) /*!< 0x00004000 */
22995#define HRTIM_BMTRGR_TBCMP2 HRTIM_BMTRGR_TBCMP2_Msk /*!< Timer B compare 2 */
22996#define HRTIM_BMTRGR_TCRST_Pos (15U)
22997#define HRTIM_BMTRGR_TCRST_Msk (0x1UL << HRTIM_BMTRGR_TCRST_Pos) /*!< 0x00008000 */
22998#define HRTIM_BMTRGR_TCRST HRTIM_BMTRGR_TCRST_Msk /*!< Timer C reset */
22999#define HRTIM_BMTRGR_TCREP_Pos (16U)
23000#define HRTIM_BMTRGR_TCREP_Msk (0x1UL << HRTIM_BMTRGR_TCREP_Pos) /*!< 0x00010000 */
23001#define HRTIM_BMTRGR_TCREP HRTIM_BMTRGR_TCREP_Msk /*!< Timer C repetition */
23002#define HRTIM_BMTRGR_TCCMP1_Pos (17U)
23003#define HRTIM_BMTRGR_TCCMP1_Msk (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos) /*!< 0x00020000 */
23004#define HRTIM_BMTRGR_TCCMP1 HRTIM_BMTRGR_TCCMP1_Msk /*!< Timer C compare 1 */
23005#define HRTIM_BMTRGR_TCCMP2_Pos (18U)
23006#define HRTIM_BMTRGR_TCCMP2_Msk (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos) /*!< 0x00040000 */
23007#define HRTIM_BMTRGR_TCCMP2 HRTIM_BMTRGR_TCCMP2_Msk /*!< Timer C compare 2 */
23008#define HRTIM_BMTRGR_TDRST_Pos (19U)
23009#define HRTIM_BMTRGR_TDRST_Msk (0x1UL << HRTIM_BMTRGR_TDRST_Pos) /*!< 0x00080000 */
23010#define HRTIM_BMTRGR_TDRST HRTIM_BMTRGR_TDRST_Msk /*!< Timer D reset */
23011#define HRTIM_BMTRGR_TDREP_Pos (20U)
23012#define HRTIM_BMTRGR_TDREP_Msk (0x1UL << HRTIM_BMTRGR_TDREP_Pos) /*!< 0x00100000 */
23013#define HRTIM_BMTRGR_TDREP HRTIM_BMTRGR_TDREP_Msk /*!< Timer D repetition */
23014#define HRTIM_BMTRGR_TDCMP1_Pos (21U)
23015#define HRTIM_BMTRGR_TDCMP1_Msk (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos) /*!< 0x00200000 */
23016#define HRTIM_BMTRGR_TDCMP1 HRTIM_BMTRGR_TDCMP1_Msk /*!< Timer D compare 1 */
23017#define HRTIM_BMTRGR_TDCMP2_Pos (22U)
23018#define HRTIM_BMTRGR_TDCMP2_Msk (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos) /*!< 0x00400000 */
23019#define HRTIM_BMTRGR_TDCMP2 HRTIM_BMTRGR_TDCMP2_Msk /*!< Timer D compare 2 */
23020#define HRTIM_BMTRGR_TERST_Pos (23U)
23021#define HRTIM_BMTRGR_TERST_Msk (0x1UL << HRTIM_BMTRGR_TERST_Pos) /*!< 0x00800000 */
23022#define HRTIM_BMTRGR_TERST HRTIM_BMTRGR_TERST_Msk /*!< Timer E reset */
23023#define HRTIM_BMTRGR_TEREP_Pos (24U)
23024#define HRTIM_BMTRGR_TEREP_Msk (0x1UL << HRTIM_BMTRGR_TEREP_Pos) /*!< 0x01000000 */
23025#define HRTIM_BMTRGR_TEREP HRTIM_BMTRGR_TEREP_Msk /*!< Timer E repetition */
23026#define HRTIM_BMTRGR_TECMP1_Pos (25U)
23027#define HRTIM_BMTRGR_TECMP1_Msk (0x1UL << HRTIM_BMTRGR_TECMP1_Pos) /*!< 0x02000000 */
23028#define HRTIM_BMTRGR_TECMP1 HRTIM_BMTRGR_TECMP1_Msk /*!< Timer E compare 1 */
23029#define HRTIM_BMTRGR_TECMP2_Pos (26U)
23030#define HRTIM_BMTRGR_TECMP2_Msk (0x1UL << HRTIM_BMTRGR_TECMP2_Pos) /*!< 0x04000000 */
23031#define HRTIM_BMTRGR_TECMP2 HRTIM_BMTRGR_TECMP2_Msk /*!< Timer E compare 2 */
23032#define HRTIM_BMTRGR_TAEEV7_Pos (27U)
23033#define HRTIM_BMTRGR_TAEEV7_Msk (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos) /*!< 0x08000000 */
23034#define HRTIM_BMTRGR_TAEEV7 HRTIM_BMTRGR_TAEEV7_Msk /*!< Timer A period following External Event7 */
23035#define HRTIM_BMTRGR_TDEEV8_Pos (28U)
23036#define HRTIM_BMTRGR_TDEEV8_Msk (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos) /*!< 0x10000000 */
23037#define HRTIM_BMTRGR_TDEEV8 HRTIM_BMTRGR_TDEEV8_Msk /*!< Timer D period following External Event8 */
23038#define HRTIM_BMTRGR_EEV7_Pos (29U)
23039#define HRTIM_BMTRGR_EEV7_Msk (0x1UL << HRTIM_BMTRGR_EEV7_Pos) /*!< 0x20000000 */
23040#define HRTIM_BMTRGR_EEV7 HRTIM_BMTRGR_EEV7_Msk /*!< External Event 7 */
23041#define HRTIM_BMTRGR_EEV8_Pos (30U)
23042#define HRTIM_BMTRGR_EEV8_Msk (0x1UL << HRTIM_BMTRGR_EEV8_Pos) /*!< 0x40000000 */
23043#define HRTIM_BMTRGR_EEV8 HRTIM_BMTRGR_EEV8_Msk /*!< External Event 8 */
23044#define HRTIM_BMTRGR_OCHPEV_Pos (31U)
23045#define HRTIM_BMTRGR_OCHPEV_Msk (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos) /*!< 0x80000000 */
23046#define HRTIM_BMTRGR_OCHPEV HRTIM_BMTRGR_OCHPEV_Msk /*!< on-chip Event */
23047
23048/******************* Bit definition for HRTIM_BMCMPR register ***************/
23049#define HRTIM_BMCMPR_BMCMPR_Pos (0U)
23050#define HRTIM_BMCMPR_BMCMPR_Msk (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos) /*!< 0x0000FFFF */
23051#define HRTIM_BMCMPR_BMCMPR HRTIM_BMCMPR_BMCMPR_Msk /*!<!<Burst Compare Value */
23052
23053/******************* Bit definition for HRTIM_BMPER register ****************/
23054#define HRTIM_BMPER_BMPER_Pos (0U)
23055#define HRTIM_BMPER_BMPER_Msk (0xFFFFUL << HRTIM_BMPER_BMPER_Pos) /*!< 0x0000FFFF */
23056#define HRTIM_BMPER_BMPER HRTIM_BMPER_BMPER_Msk /*!<!<Burst period Value */
23057
23058/******************* Bit definition for HRTIM_EECR1 register ****************/
23059#define HRTIM_EECR1_EE1SRC_Pos (0U)
23060#define HRTIM_EECR1_EE1SRC_Msk (0x3UL << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000003 */
23061#define HRTIM_EECR1_EE1SRC HRTIM_EECR1_EE1SRC_Msk /*!< External event 1 source */
23062#define HRTIM_EECR1_EE1SRC_0 (0x1UL << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000001 */
23063#define HRTIM_EECR1_EE1SRC_1 (0x2UL << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000002 */
23064#define HRTIM_EECR1_EE1POL_Pos (2U)
23065#define HRTIM_EECR1_EE1POL_Msk (0x1UL << HRTIM_EECR1_EE1POL_Pos) /*!< 0x00000004 */
23066#define HRTIM_EECR1_EE1POL HRTIM_EECR1_EE1POL_Msk /*!< External event 1 Polarity */
23067#define HRTIM_EECR1_EE1SNS_Pos (3U)
23068#define HRTIM_EECR1_EE1SNS_Msk (0x3UL << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000018 */
23069#define HRTIM_EECR1_EE1SNS HRTIM_EECR1_EE1SNS_Msk /*!< External event 1 sensitivity */
23070#define HRTIM_EECR1_EE1SNS_0 (0x1UL << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000008 */
23071#define HRTIM_EECR1_EE1SNS_1 (0x2UL << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000010 */
23072#define HRTIM_EECR1_EE1FAST_Pos (5U)
23073#define HRTIM_EECR1_EE1FAST_Msk (0x1UL << HRTIM_EECR1_EE1FAST_Pos) /*!< 0x00000020 */
23074#define HRTIM_EECR1_EE1FAST HRTIM_EECR1_EE1FAST_Msk /*!< External event 1 Fast mode */
23075
23076#define HRTIM_EECR1_EE2SRC_Pos (6U)
23077#define HRTIM_EECR1_EE2SRC_Msk (0x3UL << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x000000C0 */
23078#define HRTIM_EECR1_EE2SRC HRTIM_EECR1_EE2SRC_Msk /*!< External event 2 source */
23079#define HRTIM_EECR1_EE2SRC_0 (0x1UL << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x00000040 */
23080#define HRTIM_EECR1_EE2SRC_1 (0x2UL << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x00000080 */
23081#define HRTIM_EECR1_EE2POL_Pos (8U)
23082#define HRTIM_EECR1_EE2POL_Msk (0x1UL << HRTIM_EECR1_EE2POL_Pos) /*!< 0x00000100 */
23083#define HRTIM_EECR1_EE2POL HRTIM_EECR1_EE2POL_Msk /*!< External event 2 Polarity */
23084#define HRTIM_EECR1_EE2SNS_Pos (9U)
23085#define HRTIM_EECR1_EE2SNS_Msk (0x3UL << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000600 */
23086#define HRTIM_EECR1_EE2SNS HRTIM_EECR1_EE2SNS_Msk /*!< External event 2 sensitivity */
23087#define HRTIM_EECR1_EE2SNS_0 (0x1UL << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000200 */
23088#define HRTIM_EECR1_EE2SNS_1 (0x2UL << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000400 */
23089#define HRTIM_EECR1_EE2FAST_Pos (11U)
23090#define HRTIM_EECR1_EE2FAST_Msk (0x1UL << HRTIM_EECR1_EE2FAST_Pos) /*!< 0x00000800 */
23091#define HRTIM_EECR1_EE2FAST HRTIM_EECR1_EE2FAST_Msk /*!< External event 2 Fast mode */
23092
23093#define HRTIM_EECR1_EE3SRC_Pos (12U)
23094#define HRTIM_EECR1_EE3SRC_Msk (0x3UL << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00003000 */
23095#define HRTIM_EECR1_EE3SRC HRTIM_EECR1_EE3SRC_Msk /*!< External event 3 source */
23096#define HRTIM_EECR1_EE3SRC_0 (0x1UL << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00001000 */
23097#define HRTIM_EECR1_EE3SRC_1 (0x2UL << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00002000 */
23098#define HRTIM_EECR1_EE3POL_Pos (14U)
23099#define HRTIM_EECR1_EE3POL_Msk (0x1UL << HRTIM_EECR1_EE3POL_Pos) /*!< 0x00004000 */
23100#define HRTIM_EECR1_EE3POL HRTIM_EECR1_EE3POL_Msk /*!< External event 3 Polarity */
23101#define HRTIM_EECR1_EE3SNS_Pos (15U)
23102#define HRTIM_EECR1_EE3SNS_Msk (0x3UL << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00018000 */
23103#define HRTIM_EECR1_EE3SNS HRTIM_EECR1_EE3SNS_Msk /*!< External event 3 sensitivity */
23104#define HRTIM_EECR1_EE3SNS_0 (0x1UL << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00008000 */
23105#define HRTIM_EECR1_EE3SNS_1 (0x2UL << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00010000 */
23106#define HRTIM_EECR1_EE3FAST_Pos (17U)
23107#define HRTIM_EECR1_EE3FAST_Msk (0x1UL << HRTIM_EECR1_EE3FAST_Pos) /*!< 0x00020000 */
23108#define HRTIM_EECR1_EE3FAST HRTIM_EECR1_EE3FAST_Msk /*!< External event 3 Fast mode */
23109
23110#define HRTIM_EECR1_EE4SRC_Pos (18U)
23111#define HRTIM_EECR1_EE4SRC_Msk (0x3UL << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x000C0000 */
23112#define HRTIM_EECR1_EE4SRC HRTIM_EECR1_EE4SRC_Msk /*!< External event 4 source */
23113#define HRTIM_EECR1_EE4SRC_0 (0x1UL << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x00040000 */
23114#define HRTIM_EECR1_EE4SRC_1 (0x2UL << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x00080000 */
23115#define HRTIM_EECR1_EE4POL_Pos (20U)
23116#define HRTIM_EECR1_EE4POL_Msk (0x1UL << HRTIM_EECR1_EE4POL_Pos) /*!< 0x00100000 */
23117#define HRTIM_EECR1_EE4POL HRTIM_EECR1_EE4POL_Msk /*!< External event 4 Polarity */
23118#define HRTIM_EECR1_EE4SNS_Pos (21U)
23119#define HRTIM_EECR1_EE4SNS_Msk (0x3UL << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00600000 */
23120#define HRTIM_EECR1_EE4SNS HRTIM_EECR1_EE4SNS_Msk /*!< External event 4 sensitivity */
23121#define HRTIM_EECR1_EE4SNS_0 (0x1UL << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00200000 */
23122#define HRTIM_EECR1_EE4SNS_1 (0x2UL << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00400000 */
23123#define HRTIM_EECR1_EE4FAST_Pos (23U)
23124#define HRTIM_EECR1_EE4FAST_Msk (0x1UL << HRTIM_EECR1_EE4FAST_Pos) /*!< 0x00800000 */
23125#define HRTIM_EECR1_EE4FAST HRTIM_EECR1_EE4FAST_Msk /*!< External event 4 Fast mode */
23126
23127#define HRTIM_EECR1_EE5SRC_Pos (24U)
23128#define HRTIM_EECR1_EE5SRC_Msk (0x3UL << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x03000000 */
23129#define HRTIM_EECR1_EE5SRC HRTIM_EECR1_EE5SRC_Msk /*!< External event 5 source */
23130#define HRTIM_EECR1_EE5SRC_0 (0x1UL << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x01000000 */
23131#define HRTIM_EECR1_EE5SRC_1 (0x2UL << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x02000000 */
23132#define HRTIM_EECR1_EE5POL_Pos (26U)
23133#define HRTIM_EECR1_EE5POL_Msk (0x1UL << HRTIM_EECR1_EE5POL_Pos) /*!< 0x04000000 */
23134#define HRTIM_EECR1_EE5POL HRTIM_EECR1_EE5POL_Msk /*!< External event 5 Polarity */
23135#define HRTIM_EECR1_EE5SNS_Pos (27U)
23136#define HRTIM_EECR1_EE5SNS_Msk (0x3UL << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x18000000 */
23137#define HRTIM_EECR1_EE5SNS HRTIM_EECR1_EE5SNS_Msk /*!< External event 5 sensitivity */
23138#define HRTIM_EECR1_EE5SNS_0 (0x1UL << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x08000000 */
23139#define HRTIM_EECR1_EE5SNS_1 (0x2UL << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x10000000 */
23140#define HRTIM_EECR1_EE5FAST_Pos (29U)
23141#define HRTIM_EECR1_EE5FAST_Msk (0x1UL << HRTIM_EECR1_EE5FAST_Pos) /*!< 0x20000000 */
23142#define HRTIM_EECR1_EE5FAST HRTIM_EECR1_EE5FAST_Msk /*!< External event 5 Fast mode */
23143
23144/******************* Bit definition for HRTIM_EECR2 register ****************/
23145#define HRTIM_EECR2_EE6SRC_Pos (0U)
23146#define HRTIM_EECR2_EE6SRC_Msk (0x3UL << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000003 */
23147#define HRTIM_EECR2_EE6SRC HRTIM_EECR2_EE6SRC_Msk /*!< External event 6 source */
23148#define HRTIM_EECR2_EE6SRC_0 (0x1UL << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000001 */
23149#define HRTIM_EECR2_EE6SRC_1 (0x2UL << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000002 */
23150#define HRTIM_EECR2_EE6POL_Pos (2U)
23151#define HRTIM_EECR2_EE6POL_Msk (0x1UL << HRTIM_EECR2_EE6POL_Pos) /*!< 0x00000004 */
23152#define HRTIM_EECR2_EE6POL HRTIM_EECR2_EE6POL_Msk /*!< External event 6 Polarity */
23153#define HRTIM_EECR2_EE6SNS_Pos (3U)
23154#define HRTIM_EECR2_EE6SNS_Msk (0x3UL << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000018 */
23155#define HRTIM_EECR2_EE6SNS HRTIM_EECR2_EE6SNS_Msk /*!< External event 6 sensitivity */
23156#define HRTIM_EECR2_EE6SNS_0 (0x1UL << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000008 */
23157#define HRTIM_EECR2_EE6SNS_1 (0x2UL << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000010 */
23158
23159#define HRTIM_EECR2_EE7SRC_Pos (6U)
23160#define HRTIM_EECR2_EE7SRC_Msk (0x3UL << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x000000C0 */
23161#define HRTIM_EECR2_EE7SRC HRTIM_EECR2_EE7SRC_Msk /*!< External event 7 source */
23162#define HRTIM_EECR2_EE7SRC_0 (0x1UL << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x00000040 */
23163#define HRTIM_EECR2_EE7SRC_1 (0x2UL << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x00000080 */
23164#define HRTIM_EECR2_EE7POL_Pos (8U)
23165#define HRTIM_EECR2_EE7POL_Msk (0x1UL << HRTIM_EECR2_EE7POL_Pos) /*!< 0x00000100 */
23166#define HRTIM_EECR2_EE7POL HRTIM_EECR2_EE7POL_Msk /*!< External event 7 Polarity */
23167#define HRTIM_EECR2_EE7SNS_Pos (9U)
23168#define HRTIM_EECR2_EE7SNS_Msk (0x3UL << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000600 */
23169#define HRTIM_EECR2_EE7SNS HRTIM_EECR2_EE7SNS_Msk /*!< External event 7 sensitivity */
23170#define HRTIM_EECR2_EE7SNS_0 (0x1UL << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000200 */
23171#define HRTIM_EECR2_EE7SNS_1 (0x2UL << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000400 */
23172
23173#define HRTIM_EECR2_EE8SRC_Pos (12U)
23174#define HRTIM_EECR2_EE8SRC_Msk (0x3UL << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00003000 */
23175#define HRTIM_EECR2_EE8SRC HRTIM_EECR2_EE8SRC_Msk /*!< External event 8 source */
23176#define HRTIM_EECR2_EE8SRC_0 (0x1UL << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00001000 */
23177#define HRTIM_EECR2_EE8SRC_1 (0x2UL << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00002000 */
23178#define HRTIM_EECR2_EE8POL_Pos (14U)
23179#define HRTIM_EECR2_EE8POL_Msk (0x1UL << HRTIM_EECR2_EE8POL_Pos) /*!< 0x00004000 */
23180#define HRTIM_EECR2_EE8POL HRTIM_EECR2_EE8POL_Msk /*!< External event 8 Polarity */
23181#define HRTIM_EECR2_EE8SNS_Pos (15U)
23182#define HRTIM_EECR2_EE8SNS_Msk (0x3UL << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00018000 */
23183#define HRTIM_EECR2_EE8SNS HRTIM_EECR2_EE8SNS_Msk /*!< External event 8 sensitivity */
23184#define HRTIM_EECR2_EE8SNS_0 (0x1UL << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00008000 */
23185#define HRTIM_EECR2_EE8SNS_1 (0x2UL << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00010000 */
23186
23187#define HRTIM_EECR2_EE9SRC_Pos (18U)
23188#define HRTIM_EECR2_EE9SRC_Msk (0x3UL << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x000C0000 */
23189#define HRTIM_EECR2_EE9SRC HRTIM_EECR2_EE9SRC_Msk /*!< External event 9 source */
23190#define HRTIM_EECR2_EE9SRC_0 (0x1UL << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x00040000 */
23191#define HRTIM_EECR2_EE9SRC_1 (0x2UL << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x00080000 */
23192#define HRTIM_EECR2_EE9POL_Pos (20U)
23193#define HRTIM_EECR2_EE9POL_Msk (0x1UL << HRTIM_EECR2_EE9POL_Pos) /*!< 0x00100000 */
23194#define HRTIM_EECR2_EE9POL HRTIM_EECR2_EE9POL_Msk /*!< External event 9 Polarity */
23195#define HRTIM_EECR2_EE9SNS_Pos (21U)
23196#define HRTIM_EECR2_EE9SNS_Msk (0x3UL << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00600000 */
23197#define HRTIM_EECR2_EE9SNS HRTIM_EECR2_EE9SNS_Msk /*!< External event 9 sensitivity */
23198#define HRTIM_EECR2_EE9SNS_0 (0x1UL << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00200000 */
23199#define HRTIM_EECR2_EE9SNS_1 (0x2UL << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00400000 */
23200
23201#define HRTIM_EECR2_EE10SRC_Pos (24U)
23202#define HRTIM_EECR2_EE10SRC_Msk (0x3UL << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x03000000 */
23203#define HRTIM_EECR2_EE10SRC HRTIM_EECR2_EE10SRC_Msk /*!< External event 10 source */
23204#define HRTIM_EECR2_EE10SRC_0 (0x1UL << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x01000000 */
23205#define HRTIM_EECR2_EE10SRC_1 (0x2UL << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x02000000 */
23206#define HRTIM_EECR2_EE10POL_Pos (26U)
23207#define HRTIM_EECR2_EE10POL_Msk (0x1UL << HRTIM_EECR2_EE10POL_Pos) /*!< 0x04000000 */
23208#define HRTIM_EECR2_EE10POL HRTIM_EECR2_EE10POL_Msk /*!< External event 10 Polarity */
23209#define HRTIM_EECR2_EE10SNS_Pos (27U)
23210#define HRTIM_EECR2_EE10SNS_Msk (0x3UL << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x18000000 */
23211#define HRTIM_EECR2_EE10SNS HRTIM_EECR2_EE10SNS_Msk /*!< External event 10 sensitivity */
23212#define HRTIM_EECR2_EE10SNS_0 (0x1UL << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x08000000 */
23213#define HRTIM_EECR2_EE10SNS_1 (0x2UL << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x10000000 */
23214
23215/******************* Bit definition for HRTIM_EECR3 register ****************/
23216#define HRTIM_EECR3_EE6F_Pos (0U)
23217#define HRTIM_EECR3_EE6F_Msk (0xFUL << HRTIM_EECR3_EE6F_Pos) /*!< 0x0000000F */
23218#define HRTIM_EECR3_EE6F HRTIM_EECR3_EE6F_Msk /*!< External event 6 filter */
23219#define HRTIM_EECR3_EE6F_0 (0x1UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000001 */
23220#define HRTIM_EECR3_EE6F_1 (0x2UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000002 */
23221#define HRTIM_EECR3_EE6F_2 (0x4UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000004 */
23222#define HRTIM_EECR3_EE6F_3 (0x8UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000008 */
23223#define HRTIM_EECR3_EE7F_Pos (6U)
23224#define HRTIM_EECR3_EE7F_Msk (0xFUL << HRTIM_EECR3_EE7F_Pos) /*!< 0x000003C0 */
23225#define HRTIM_EECR3_EE7F HRTIM_EECR3_EE7F_Msk /*!< External event 7 filter */
23226#define HRTIM_EECR3_EE7F_0 (0x1UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000040 */
23227#define HRTIM_EECR3_EE7F_1 (0x2UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000080 */
23228#define HRTIM_EECR3_EE7F_2 (0x4UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000100 */
23229#define HRTIM_EECR3_EE7F_3 (0x8UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000200 */
23230#define HRTIM_EECR3_EE8F_Pos (12U)
23231#define HRTIM_EECR3_EE8F_Msk (0xFUL << HRTIM_EECR3_EE8F_Pos) /*!< 0x0000F000 */
23232#define HRTIM_EECR3_EE8F HRTIM_EECR3_EE8F_Msk /*!< External event 8 filter */
23233#define HRTIM_EECR3_EE8F_0 (0x1UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00001000 */
23234#define HRTIM_EECR3_EE8F_1 (0x2UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00002000 */
23235#define HRTIM_EECR3_EE8F_2 (0x4UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00004000 */
23236#define HRTIM_EECR3_EE8F_3 (0x8UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00008000 */
23237#define HRTIM_EECR3_EE9F_Pos (18U)
23238#define HRTIM_EECR3_EE9F_Msk (0xFUL << HRTIM_EECR3_EE9F_Pos) /*!< 0x003C0000 */
23239#define HRTIM_EECR3_EE9F HRTIM_EECR3_EE9F_Msk /*!< External event 9 filter */
23240#define HRTIM_EECR3_EE9F_0 (0x1UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00040000 */
23241#define HRTIM_EECR3_EE9F_1 (0x2UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00080000 */
23242#define HRTIM_EECR3_EE9F_2 (0x4UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00100000 */
23243#define HRTIM_EECR3_EE9F_3 (0x8UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00200000 */
23244#define HRTIM_EECR3_EE10F_Pos (24U)
23245#define HRTIM_EECR3_EE10F_Msk (0xFUL << HRTIM_EECR3_EE10F_Pos) /*!< 0x0F000000 */
23246#define HRTIM_EECR3_EE10F HRTIM_EECR3_EE10F_Msk /*!< External event 10 filter */
23247#define HRTIM_EECR3_EE10F_0 (0x1UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x01000000 */
23248#define HRTIM_EECR3_EE10F_1 (0x2UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x02000000 */
23249#define HRTIM_EECR3_EE10F_2 (0x4UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x04000000 */
23250#define HRTIM_EECR3_EE10F_3 (0x8UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x08000000 */
23251#define HRTIM_EECR3_EEVSD_Pos (30U)
23252#define HRTIM_EECR3_EEVSD_Msk (0x3UL << HRTIM_EECR3_EEVSD_Pos) /*!< 0xC0000000 */
23253#define HRTIM_EECR3_EEVSD HRTIM_EECR3_EEVSD_Msk /*!< External event sampling clock division */
23254#define HRTIM_EECR3_EEVSD_0 (0x1UL << HRTIM_EECR3_EEVSD_Pos) /*!< 0x40000000 */
23255#define HRTIM_EECR3_EEVSD_1 (0x2UL << HRTIM_EECR3_EEVSD_Pos) /*!< 0x80000000 */
23256
23257/******************* Bit definition for HRTIM_ADC1R register ****************/
23258#define HRTIM_ADC1R_AD1MC1_Pos (0U)
23259#define HRTIM_ADC1R_AD1MC1_Msk (0x1UL << HRTIM_ADC1R_AD1MC1_Pos) /*!< 0x00000001 */
23260#define HRTIM_ADC1R_AD1MC1 HRTIM_ADC1R_AD1MC1_Msk /*!< ADC Trigger 1 on master compare 1 */
23261#define HRTIM_ADC1R_AD1MC2_Pos (1U)
23262#define HRTIM_ADC1R_AD1MC2_Msk (0x1UL << HRTIM_ADC1R_AD1MC2_Pos) /*!< 0x00000002 */
23263#define HRTIM_ADC1R_AD1MC2 HRTIM_ADC1R_AD1MC2_Msk /*!< ADC Trigger 1 on master compare 2 */
23264#define HRTIM_ADC1R_AD1MC3_Pos (2U)
23265#define HRTIM_ADC1R_AD1MC3_Msk (0x1UL << HRTIM_ADC1R_AD1MC3_Pos) /*!< 0x00000004 */
23266#define HRTIM_ADC1R_AD1MC3 HRTIM_ADC1R_AD1MC3_Msk /*!< ADC Trigger 1 on master compare 3 */
23267#define HRTIM_ADC1R_AD1MC4_Pos (3U)
23268#define HRTIM_ADC1R_AD1MC4_Msk (0x1UL << HRTIM_ADC1R_AD1MC4_Pos) /*!< 0x00000008 */
23269#define HRTIM_ADC1R_AD1MC4 HRTIM_ADC1R_AD1MC4_Msk /*!< ADC Trigger 1 on master compare 4 */
23270#define HRTIM_ADC1R_AD1MPER_Pos (4U)
23271#define HRTIM_ADC1R_AD1MPER_Msk (0x1UL << HRTIM_ADC1R_AD1MPER_Pos) /*!< 0x00000010 */
23272#define HRTIM_ADC1R_AD1MPER HRTIM_ADC1R_AD1MPER_Msk /*!< ADC Trigger 1 on master period */
23273#define HRTIM_ADC1R_AD1EEV1_Pos (5U)
23274#define HRTIM_ADC1R_AD1EEV1_Msk (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos) /*!< 0x00000020 */
23275#define HRTIM_ADC1R_AD1EEV1 HRTIM_ADC1R_AD1EEV1_Msk /*!< ADC Trigger 1 on external event 1 */
23276#define HRTIM_ADC1R_AD1EEV2_Pos (6U)
23277#define HRTIM_ADC1R_AD1EEV2_Msk (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos) /*!< 0x00000040 */
23278#define HRTIM_ADC1R_AD1EEV2 HRTIM_ADC1R_AD1EEV2_Msk /*!< ADC Trigger 1 on external event 2 */
23279#define HRTIM_ADC1R_AD1EEV3_Pos (7U)
23280#define HRTIM_ADC1R_AD1EEV3_Msk (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos) /*!< 0x00000080 */
23281#define HRTIM_ADC1R_AD1EEV3 HRTIM_ADC1R_AD1EEV3_Msk /*!< ADC Trigger 1 on external event 3 */
23282#define HRTIM_ADC1R_AD1EEV4_Pos (8U)
23283#define HRTIM_ADC1R_AD1EEV4_Msk (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos) /*!< 0x00000100 */
23284#define HRTIM_ADC1R_AD1EEV4 HRTIM_ADC1R_AD1EEV4_Msk /*!< ADC Trigger 1 on external event 4 */
23285#define HRTIM_ADC1R_AD1EEV5_Pos (9U)
23286#define HRTIM_ADC1R_AD1EEV5_Msk (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos) /*!< 0x00000200 */
23287#define HRTIM_ADC1R_AD1EEV5 HRTIM_ADC1R_AD1EEV5_Msk /*!< ADC Trigger 1 on external event 5 */
23288#define HRTIM_ADC1R_AD1TAC2_Pos (10U)
23289#define HRTIM_ADC1R_AD1TAC2_Msk (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos) /*!< 0x00000400 */
23290#define HRTIM_ADC1R_AD1TAC2 HRTIM_ADC1R_AD1TAC2_Msk /*!< ADC Trigger 1 on Timer A compare 2 */
23291#define HRTIM_ADC1R_AD1TAC3_Pos (11U)
23292#define HRTIM_ADC1R_AD1TAC3_Msk (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos) /*!< 0x00000800 */
23293#define HRTIM_ADC1R_AD1TAC3 HRTIM_ADC1R_AD1TAC3_Msk /*!< ADC Trigger 1 on Timer A compare 3 */
23294#define HRTIM_ADC1R_AD1TAC4_Pos (12U)
23295#define HRTIM_ADC1R_AD1TAC4_Msk (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos) /*!< 0x00001000 */
23296#define HRTIM_ADC1R_AD1TAC4 HRTIM_ADC1R_AD1TAC4_Msk /*!< ADC Trigger 1 on Timer A compare 4 */
23297#define HRTIM_ADC1R_AD1TAPER_Pos (13U)
23298#define HRTIM_ADC1R_AD1TAPER_Msk (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos) /*!< 0x00002000 */
23299#define HRTIM_ADC1R_AD1TAPER HRTIM_ADC1R_AD1TAPER_Msk /*!< ADC Trigger 1 on Timer A period */
23300#define HRTIM_ADC1R_AD1TARST_Pos (14U)
23301#define HRTIM_ADC1R_AD1TARST_Msk (0x1UL << HRTIM_ADC1R_AD1TARST_Pos) /*!< 0x00004000 */
23302#define HRTIM_ADC1R_AD1TARST HRTIM_ADC1R_AD1TARST_Msk /*!< ADC Trigger 1 on Timer A reset */
23303#define HRTIM_ADC1R_AD1TBC2_Pos (15U)
23304#define HRTIM_ADC1R_AD1TBC2_Msk (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos) /*!< 0x00008000 */
23305#define HRTIM_ADC1R_AD1TBC2 HRTIM_ADC1R_AD1TBC2_Msk /*!< ADC Trigger 1 on Timer B compare 2 */
23306#define HRTIM_ADC1R_AD1TBC3_Pos (16U)
23307#define HRTIM_ADC1R_AD1TBC3_Msk (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos) /*!< 0x00010000 */
23308#define HRTIM_ADC1R_AD1TBC3 HRTIM_ADC1R_AD1TBC3_Msk /*!< ADC Trigger 1 on Timer B compare 3 */
23309#define HRTIM_ADC1R_AD1TBC4_Pos (17U)
23310#define HRTIM_ADC1R_AD1TBC4_Msk (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos) /*!< 0x00020000 */
23311#define HRTIM_ADC1R_AD1TBC4 HRTIM_ADC1R_AD1TBC4_Msk /*!< ADC Trigger 1 on Timer B compare 4 */
23312#define HRTIM_ADC1R_AD1TBPER_Pos (18U)
23313#define HRTIM_ADC1R_AD1TBPER_Msk (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos) /*!< 0x00040000 */
23314#define HRTIM_ADC1R_AD1TBPER HRTIM_ADC1R_AD1TBPER_Msk /*!< ADC Trigger 1 on Timer B period */
23315#define HRTIM_ADC1R_AD1TBRST_Pos (19U)
23316#define HRTIM_ADC1R_AD1TBRST_Msk (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos) /*!< 0x00080000 */
23317#define HRTIM_ADC1R_AD1TBRST HRTIM_ADC1R_AD1TBRST_Msk /*!< ADC Trigger 1 on Timer B reset */
23318#define HRTIM_ADC1R_AD1TCC2_Pos (20U)
23319#define HRTIM_ADC1R_AD1TCC2_Msk (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos) /*!< 0x00100000 */
23320#define HRTIM_ADC1R_AD1TCC2 HRTIM_ADC1R_AD1TCC2_Msk /*!< ADC Trigger 1 on Timer C compare 2 */
23321#define HRTIM_ADC1R_AD1TCC3_Pos (21U)
23322#define HRTIM_ADC1R_AD1TCC3_Msk (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos) /*!< 0x00200000 */
23323#define HRTIM_ADC1R_AD1TCC3 HRTIM_ADC1R_AD1TCC3_Msk /*!< ADC Trigger 1 on Timer C compare 3 */
23324#define HRTIM_ADC1R_AD1TCC4_Pos (22U)
23325#define HRTIM_ADC1R_AD1TCC4_Msk (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos) /*!< 0x00400000 */
23326#define HRTIM_ADC1R_AD1TCC4 HRTIM_ADC1R_AD1TCC4_Msk /*!< ADC Trigger 1 on Timer C compare 4 */
23327#define HRTIM_ADC1R_AD1TCPER_Pos (23U)
23328#define HRTIM_ADC1R_AD1TCPER_Msk (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos) /*!< 0x00800000 */
23329#define HRTIM_ADC1R_AD1TCPER HRTIM_ADC1R_AD1TCPER_Msk /*!< ADC Trigger 1 on Timer C period */
23330#define HRTIM_ADC1R_AD1TDC2_Pos (24U)
23331#define HRTIM_ADC1R_AD1TDC2_Msk (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos) /*!< 0x01000000 */
23332#define HRTIM_ADC1R_AD1TDC2 HRTIM_ADC1R_AD1TDC2_Msk /*!< ADC Trigger 1 on Timer D compare 2 */
23333#define HRTIM_ADC1R_AD1TDC3_Pos (25U)
23334#define HRTIM_ADC1R_AD1TDC3_Msk (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos) /*!< 0x02000000 */
23335#define HRTIM_ADC1R_AD1TDC3 HRTIM_ADC1R_AD1TDC3_Msk /*!< ADC Trigger 1 on Timer D compare 3 */
23336#define HRTIM_ADC1R_AD1TDC4_Pos (26U)
23337#define HRTIM_ADC1R_AD1TDC4_Msk (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos) /*!< 0x04000000 */
23338#define HRTIM_ADC1R_AD1TDC4 HRTIM_ADC1R_AD1TDC4_Msk /*!< ADC Trigger 1 on Timer D compare 4 */
23339#define HRTIM_ADC1R_AD1TDPER_Pos (27U)
23340#define HRTIM_ADC1R_AD1TDPER_Msk (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos) /*!< 0x08000000 */
23341#define HRTIM_ADC1R_AD1TDPER HRTIM_ADC1R_AD1TDPER_Msk /*!< ADC Trigger 1 on Timer D period */
23342#define HRTIM_ADC1R_AD1TEC2_Pos (28U)
23343#define HRTIM_ADC1R_AD1TEC2_Msk (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos) /*!< 0x10000000 */
23344#define HRTIM_ADC1R_AD1TEC2 HRTIM_ADC1R_AD1TEC2_Msk /*!< ADC Trigger 1 on Timer E compare 2 */
23345#define HRTIM_ADC1R_AD1TEC3_Pos (29U)
23346#define HRTIM_ADC1R_AD1TEC3_Msk (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos) /*!< 0x20000000 */
23347#define HRTIM_ADC1R_AD1TEC3 HRTIM_ADC1R_AD1TEC3_Msk /*!< ADC Trigger 1 on Timer E compare 3 */
23348#define HRTIM_ADC1R_AD1TEC4_Pos (30U)
23349#define HRTIM_ADC1R_AD1TEC4_Msk (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos) /*!< 0x40000000 */
23350#define HRTIM_ADC1R_AD1TEC4 HRTIM_ADC1R_AD1TEC4_Msk /*!< ADC Trigger 1 on Timer E compare 4 */
23351#define HRTIM_ADC1R_AD1TEPER_Pos (31U)
23352#define HRTIM_ADC1R_AD1TEPER_Msk (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos) /*!< 0x80000000 */
23353#define HRTIM_ADC1R_AD1TEPER HRTIM_ADC1R_AD1TEPER_Msk /*!< ADC Trigger 1 on Timer E period */
23354
23355/******************* Bit definition for HRTIM_ADC2R register ****************/
23356#define HRTIM_ADC2R_AD2MC1_Pos (0U)
23357#define HRTIM_ADC2R_AD2MC1_Msk (0x1UL << HRTIM_ADC2R_AD2MC1_Pos) /*!< 0x00000001 */
23358#define HRTIM_ADC2R_AD2MC1 HRTIM_ADC2R_AD2MC1_Msk /*!< ADC Trigger 2 on master compare 1 */
23359#define HRTIM_ADC2R_AD2MC2_Pos (1U)
23360#define HRTIM_ADC2R_AD2MC2_Msk (0x1UL << HRTIM_ADC2R_AD2MC2_Pos) /*!< 0x00000002 */
23361#define HRTIM_ADC2R_AD2MC2 HRTIM_ADC2R_AD2MC2_Msk /*!< ADC Trigger 2 on master compare 2 */
23362#define HRTIM_ADC2R_AD2MC3_Pos (2U)
23363#define HRTIM_ADC2R_AD2MC3_Msk (0x1UL << HRTIM_ADC2R_AD2MC3_Pos) /*!< 0x00000004 */
23364#define HRTIM_ADC2R_AD2MC3 HRTIM_ADC2R_AD2MC3_Msk /*!< ADC Trigger 2 on master compare 3 */
23365#define HRTIM_ADC2R_AD2MC4_Pos (3U)
23366#define HRTIM_ADC2R_AD2MC4_Msk (0x1UL << HRTIM_ADC2R_AD2MC4_Pos) /*!< 0x00000008 */
23367#define HRTIM_ADC2R_AD2MC4 HRTIM_ADC2R_AD2MC4_Msk /*!< ADC Trigger 2 on master compare 4 */
23368#define HRTIM_ADC2R_AD2MPER_Pos (4U)
23369#define HRTIM_ADC2R_AD2MPER_Msk (0x1UL << HRTIM_ADC2R_AD2MPER_Pos) /*!< 0x00000010 */
23370#define HRTIM_ADC2R_AD2MPER HRTIM_ADC2R_AD2MPER_Msk /*!< ADC Trigger 2 on master period */
23371#define HRTIM_ADC2R_AD2EEV6_Pos (5U)
23372#define HRTIM_ADC2R_AD2EEV6_Msk (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos) /*!< 0x00000020 */
23373#define HRTIM_ADC2R_AD2EEV6 HRTIM_ADC2R_AD2EEV6_Msk /*!< ADC Trigger 2 on external event 6 */
23374#define HRTIM_ADC2R_AD2EEV7_Pos (6U)
23375#define HRTIM_ADC2R_AD2EEV7_Msk (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos) /*!< 0x00000040 */
23376#define HRTIM_ADC2R_AD2EEV7 HRTIM_ADC2R_AD2EEV7_Msk /*!< ADC Trigger 2 on external event 7 */
23377#define HRTIM_ADC2R_AD2EEV8_Pos (7U)
23378#define HRTIM_ADC2R_AD2EEV8_Msk (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos) /*!< 0x00000080 */
23379#define HRTIM_ADC2R_AD2EEV8 HRTIM_ADC2R_AD2EEV8_Msk /*!< ADC Trigger 2 on external event 8 */
23380#define HRTIM_ADC2R_AD2EEV9_Pos (8U)
23381#define HRTIM_ADC2R_AD2EEV9_Msk (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos) /*!< 0x00000100 */
23382#define HRTIM_ADC2R_AD2EEV9 HRTIM_ADC2R_AD2EEV9_Msk /*!< ADC Trigger 2 on external event 9 */
23383#define HRTIM_ADC2R_AD2EEV10_Pos (9U)
23384#define HRTIM_ADC2R_AD2EEV10_Msk (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos) /*!< 0x00000200 */
23385#define HRTIM_ADC2R_AD2EEV10 HRTIM_ADC2R_AD2EEV10_Msk /*!< ADC Trigger 2 on external event 10 */
23386#define HRTIM_ADC2R_AD2TAC2_Pos (10U)
23387#define HRTIM_ADC2R_AD2TAC2_Msk (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos) /*!< 0x00000400 */
23388#define HRTIM_ADC2R_AD2TAC2 HRTIM_ADC2R_AD2TAC2_Msk /*!< ADC Trigger 2 on Timer A compare 2 */
23389#define HRTIM_ADC2R_AD2TAC3_Pos (11U)
23390#define HRTIM_ADC2R_AD2TAC3_Msk (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos) /*!< 0x00000800 */
23391#define HRTIM_ADC2R_AD2TAC3 HRTIM_ADC2R_AD2TAC3_Msk /*!< ADC Trigger 2 on Timer A compare 3 */
23392#define HRTIM_ADC2R_AD2TAC4_Pos (12U)
23393#define HRTIM_ADC2R_AD2TAC4_Msk (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos) /*!< 0x00001000 */
23394#define HRTIM_ADC2R_AD2TAC4 HRTIM_ADC2R_AD2TAC4_Msk /*!< ADC Trigger 2 on Timer A compare 4*/
23395#define HRTIM_ADC2R_AD2TAPER_Pos (13U)
23396#define HRTIM_ADC2R_AD2TAPER_Msk (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos) /*!< 0x00002000 */
23397#define HRTIM_ADC2R_AD2TAPER HRTIM_ADC2R_AD2TAPER_Msk /*!< ADC Trigger 2 on Timer A period */
23398#define HRTIM_ADC2R_AD2TBC2_Pos (14U)
23399#define HRTIM_ADC2R_AD2TBC2_Msk (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos) /*!< 0x00004000 */
23400#define HRTIM_ADC2R_AD2TBC2 HRTIM_ADC2R_AD2TBC2_Msk /*!< ADC Trigger 2 on Timer B compare 2 */
23401#define HRTIM_ADC2R_AD2TBC3_Pos (15U)
23402#define HRTIM_ADC2R_AD2TBC3_Msk (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos) /*!< 0x00008000 */
23403#define HRTIM_ADC2R_AD2TBC3 HRTIM_ADC2R_AD2TBC3_Msk /*!< ADC Trigger 2 on Timer B compare 3 */
23404#define HRTIM_ADC2R_AD2TBC4_Pos (16U)
23405#define HRTIM_ADC2R_AD2TBC4_Msk (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos) /*!< 0x00010000 */
23406#define HRTIM_ADC2R_AD2TBC4 HRTIM_ADC2R_AD2TBC4_Msk /*!< ADC Trigger 2 on Timer B compare 4 */
23407#define HRTIM_ADC2R_AD2TBPER_Pos (17U)
23408#define HRTIM_ADC2R_AD2TBPER_Msk (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos) /*!< 0x00020000 */
23409#define HRTIM_ADC2R_AD2TBPER HRTIM_ADC2R_AD2TBPER_Msk /*!< ADC Trigger 2 on Timer B period */
23410#define HRTIM_ADC2R_AD2TCC2_Pos (18U)
23411#define HRTIM_ADC2R_AD2TCC2_Msk (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos) /*!< 0x00040000 */
23412#define HRTIM_ADC2R_AD2TCC2 HRTIM_ADC2R_AD2TCC2_Msk /*!< ADC Trigger 2 on Timer C compare 2 */
23413#define HRTIM_ADC2R_AD2TCC3_Pos (19U)
23414#define HRTIM_ADC2R_AD2TCC3_Msk (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos) /*!< 0x00080000 */
23415#define HRTIM_ADC2R_AD2TCC3 HRTIM_ADC2R_AD2TCC3_Msk /*!< ADC Trigger 2 on Timer C compare 3 */
23416#define HRTIM_ADC2R_AD2TCC4_Pos (20U)
23417#define HRTIM_ADC2R_AD2TCC4_Msk (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos) /*!< 0x00100000 */
23418#define HRTIM_ADC2R_AD2TCC4 HRTIM_ADC2R_AD2TCC4_Msk /*!< ADC Trigger 2 on Timer C compare 4 */
23419#define HRTIM_ADC2R_AD2TCPER_Pos (21U)
23420#define HRTIM_ADC2R_AD2TCPER_Msk (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos) /*!< 0x00200000 */
23421#define HRTIM_ADC2R_AD2TCPER HRTIM_ADC2R_AD2TCPER_Msk /*!< ADC Trigger 2 on Timer C period */
23422#define HRTIM_ADC2R_AD2TCRST_Pos (22U)
23423#define HRTIM_ADC2R_AD2TCRST_Msk (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos) /*!< 0x00400000 */
23424#define HRTIM_ADC2R_AD2TCRST HRTIM_ADC2R_AD2TCRST_Msk /*!< ADC Trigger 2 on Timer C reset */
23425#define HRTIM_ADC2R_AD2TDC2_Pos (23U)
23426#define HRTIM_ADC2R_AD2TDC2_Msk (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos) /*!< 0x00800000 */
23427#define HRTIM_ADC2R_AD2TDC2 HRTIM_ADC2R_AD2TDC2_Msk /*!< ADC Trigger 2 on Timer D compare 2 */
23428#define HRTIM_ADC2R_AD2TDC3_Pos (24U)
23429#define HRTIM_ADC2R_AD2TDC3_Msk (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos) /*!< 0x01000000 */
23430#define HRTIM_ADC2R_AD2TDC3 HRTIM_ADC2R_AD2TDC3_Msk /*!< ADC Trigger 2 on Timer D compare 3 */
23431#define HRTIM_ADC2R_AD2TDC4_Pos (25U)
23432#define HRTIM_ADC2R_AD2TDC4_Msk (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos) /*!< 0x02000000 */
23433#define HRTIM_ADC2R_AD2TDC4 HRTIM_ADC2R_AD2TDC4_Msk /*!< ADC Trigger 2 on Timer D compare 4*/
23434#define HRTIM_ADC2R_AD2TDPER_Pos (26U)
23435#define HRTIM_ADC2R_AD2TDPER_Msk (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos) /*!< 0x04000000 */
23436#define HRTIM_ADC2R_AD2TDPER HRTIM_ADC2R_AD2TDPER_Msk /*!< ADC Trigger 2 on Timer D period */
23437#define HRTIM_ADC2R_AD2TDRST_Pos (27U)
23438#define HRTIM_ADC2R_AD2TDRST_Msk (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos) /*!< 0x08000000 */
23439#define HRTIM_ADC2R_AD2TDRST HRTIM_ADC2R_AD2TDRST_Msk /*!< ADC Trigger 2 on Timer D reset */
23440#define HRTIM_ADC2R_AD2TEC2_Pos (28U)
23441#define HRTIM_ADC2R_AD2TEC2_Msk (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos) /*!< 0x10000000 */
23442#define HRTIM_ADC2R_AD2TEC2 HRTIM_ADC2R_AD2TEC2_Msk /*!< ADC Trigger 2 on Timer E compare 2 */
23443#define HRTIM_ADC2R_AD2TEC3_Pos (29U)
23444#define HRTIM_ADC2R_AD2TEC3_Msk (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos) /*!< 0x20000000 */
23445#define HRTIM_ADC2R_AD2TEC3 HRTIM_ADC2R_AD2TEC3_Msk /*!< ADC Trigger 2 on Timer E compare 3 */
23446#define HRTIM_ADC2R_AD2TEC4_Pos (30U)
23447#define HRTIM_ADC2R_AD2TEC4_Msk (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos) /*!< 0x40000000 */
23448#define HRTIM_ADC2R_AD2TEC4 HRTIM_ADC2R_AD2TEC4_Msk /*!< ADC Trigger 2 on Timer E compare 4 */
23449#define HRTIM_ADC2R_AD2TERST_Pos (31U)
23450#define HRTIM_ADC2R_AD2TERST_Msk (0x1UL << HRTIM_ADC2R_AD2TERST_Pos) /*!< 0x80000000 */
23451#define HRTIM_ADC2R_AD2TERST HRTIM_ADC2R_AD2TERST_Msk /*!< ADC Trigger 2 on Timer E reset */
23452
23453/******************* Bit definition for HRTIM_ADC3R register ****************/
23454#define HRTIM_ADC3R_AD3MC1_Pos (0U)
23455#define HRTIM_ADC3R_AD3MC1_Msk (0x1UL << HRTIM_ADC3R_AD3MC1_Pos) /*!< 0x00000001 */
23456#define HRTIM_ADC3R_AD3MC1 HRTIM_ADC3R_AD3MC1_Msk /*!< ADC Trigger 3 on master compare 1 */
23457#define HRTIM_ADC3R_AD3MC2_Pos (1U)
23458#define HRTIM_ADC3R_AD3MC2_Msk (0x1UL << HRTIM_ADC3R_AD3MC2_Pos) /*!< 0x00000002 */
23459#define HRTIM_ADC3R_AD3MC2 HRTIM_ADC3R_AD3MC2_Msk /*!< ADC Trigger 3 on master compare 2 */
23460#define HRTIM_ADC3R_AD3MC3_Pos (2U)
23461#define HRTIM_ADC3R_AD3MC3_Msk (0x1UL << HRTIM_ADC3R_AD3MC3_Pos) /*!< 0x00000004 */
23462#define HRTIM_ADC3R_AD3MC3 HRTIM_ADC3R_AD3MC3_Msk /*!< ADC Trigger 3 on master compare 3 */
23463#define HRTIM_ADC3R_AD3MC4_Pos (3U)
23464#define HRTIM_ADC3R_AD3MC4_Msk (0x1UL << HRTIM_ADC3R_AD3MC4_Pos) /*!< 0x00000008 */
23465#define HRTIM_ADC3R_AD3MC4 HRTIM_ADC3R_AD3MC4_Msk /*!< ADC Trigger 3 on master compare 4 */
23466#define HRTIM_ADC3R_AD3MPER_Pos (4U)
23467#define HRTIM_ADC3R_AD3MPER_Msk (0x1UL << HRTIM_ADC3R_AD3MPER_Pos) /*!< 0x00000010 */
23468#define HRTIM_ADC3R_AD3MPER HRTIM_ADC3R_AD3MPER_Msk /*!< ADC Trigger 3 on master period */
23469#define HRTIM_ADC3R_AD3EEV1_Pos (5U)
23470#define HRTIM_ADC3R_AD3EEV1_Msk (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos) /*!< 0x00000020 */
23471#define HRTIM_ADC3R_AD3EEV1 HRTIM_ADC3R_AD3EEV1_Msk /*!< ADC Trigger 3 on external event 1 */
23472#define HRTIM_ADC3R_AD3EEV2_Pos (6U)
23473#define HRTIM_ADC3R_AD3EEV2_Msk (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos) /*!< 0x00000040 */
23474#define HRTIM_ADC3R_AD3EEV2 HRTIM_ADC3R_AD3EEV2_Msk /*!< ADC Trigger 3 on external event 2 */
23475#define HRTIM_ADC3R_AD3EEV3_Pos (7U)
23476#define HRTIM_ADC3R_AD3EEV3_Msk (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos) /*!< 0x00000080 */
23477#define HRTIM_ADC3R_AD3EEV3 HRTIM_ADC3R_AD3EEV3_Msk /*!< ADC Trigger 3 on external event 3 */
23478#define HRTIM_ADC3R_AD3EEV4_Pos (8U)
23479#define HRTIM_ADC3R_AD3EEV4_Msk (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos) /*!< 0x00000100 */
23480#define HRTIM_ADC3R_AD3EEV4 HRTIM_ADC3R_AD3EEV4_Msk /*!< ADC Trigger 3 on external event 4 */
23481#define HRTIM_ADC3R_AD3EEV5_Pos (9U)
23482#define HRTIM_ADC3R_AD3EEV5_Msk (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos) /*!< 0x00000200 */
23483#define HRTIM_ADC3R_AD3EEV5 HRTIM_ADC3R_AD3EEV5_Msk /*!< ADC Trigger 3 on external event 5 */
23484#define HRTIM_ADC3R_AD3TAC2_Pos (10U)
23485#define HRTIM_ADC3R_AD3TAC2_Msk (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos) /*!< 0x00000400 */
23486#define HRTIM_ADC3R_AD3TAC2 HRTIM_ADC3R_AD3TAC2_Msk /*!< ADC Trigger 3 on Timer A compare 2 */
23487#define HRTIM_ADC3R_AD3TAC3_Pos (11U)
23488#define HRTIM_ADC3R_AD3TAC3_Msk (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos) /*!< 0x00000800 */
23489#define HRTIM_ADC3R_AD3TAC3 HRTIM_ADC3R_AD3TAC3_Msk /*!< ADC Trigger 3 on Timer A compare 3 */
23490#define HRTIM_ADC3R_AD3TAC4_Pos (12U)
23491#define HRTIM_ADC3R_AD3TAC4_Msk (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos) /*!< 0x00001000 */
23492#define HRTIM_ADC3R_AD3TAC4 HRTIM_ADC3R_AD3TAC4_Msk /*!< ADC Trigger 3 on Timer A compare 4 */
23493#define HRTIM_ADC3R_AD3TAPER_Pos (13U)
23494#define HRTIM_ADC3R_AD3TAPER_Msk (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos) /*!< 0x00002000 */
23495#define HRTIM_ADC3R_AD3TAPER HRTIM_ADC3R_AD3TAPER_Msk /*!< ADC Trigger 3 on Timer A period */
23496#define HRTIM_ADC3R_AD3TARST_Pos (14U)
23497#define HRTIM_ADC3R_AD3TARST_Msk (0x1UL << HRTIM_ADC3R_AD3TARST_Pos) /*!< 0x00004000 */
23498#define HRTIM_ADC3R_AD3TARST HRTIM_ADC3R_AD3TARST_Msk /*!< ADC Trigger 3 on Timer A reset */
23499#define HRTIM_ADC3R_AD3TBC2_Pos (15U)
23500#define HRTIM_ADC3R_AD3TBC2_Msk (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos) /*!< 0x00008000 */
23501#define HRTIM_ADC3R_AD3TBC2 HRTIM_ADC3R_AD3TBC2_Msk /*!< ADC Trigger 3 on Timer B compare 2 */
23502#define HRTIM_ADC3R_AD3TBC3_Pos (16U)
23503#define HRTIM_ADC3R_AD3TBC3_Msk (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos) /*!< 0x00010000 */
23504#define HRTIM_ADC3R_AD3TBC3 HRTIM_ADC3R_AD3TBC3_Msk /*!< ADC Trigger 3 on Timer B compare 3 */
23505#define HRTIM_ADC3R_AD3TBC4_Pos (17U)
23506#define HRTIM_ADC3R_AD3TBC4_Msk (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos) /*!< 0x00020000 */
23507#define HRTIM_ADC3R_AD3TBC4 HRTIM_ADC3R_AD3TBC4_Msk /*!< ADC Trigger 3 on Timer B compare 4 */
23508#define HRTIM_ADC3R_AD3TBPER_Pos (18U)
23509#define HRTIM_ADC3R_AD3TBPER_Msk (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos) /*!< 0x00040000 */
23510#define HRTIM_ADC3R_AD3TBPER HRTIM_ADC3R_AD3TBPER_Msk /*!< ADC Trigger 3 on Timer B period */
23511#define HRTIM_ADC3R_AD3TBRST_Pos (19U)
23512#define HRTIM_ADC3R_AD3TBRST_Msk (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos) /*!< 0x00080000 */
23513#define HRTIM_ADC3R_AD3TBRST HRTIM_ADC3R_AD3TBRST_Msk /*!< ADC Trigger 3 on Timer B reset */
23514#define HRTIM_ADC3R_AD3TCC2_Pos (20U)
23515#define HRTIM_ADC3R_AD3TCC2_Msk (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos) /*!< 0x00100000 */
23516#define HRTIM_ADC3R_AD3TCC2 HRTIM_ADC3R_AD3TCC2_Msk /*!< ADC Trigger 3 on Timer C compare 2 */
23517#define HRTIM_ADC3R_AD3TCC3_Pos (21U)
23518#define HRTIM_ADC3R_AD3TCC3_Msk (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos) /*!< 0x00200000 */
23519#define HRTIM_ADC3R_AD3TCC3 HRTIM_ADC3R_AD3TCC3_Msk /*!< ADC Trigger 3 on Timer C compare 3 */
23520#define HRTIM_ADC3R_AD3TCC4_Pos (22U)
23521#define HRTIM_ADC3R_AD3TCC4_Msk (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos) /*!< 0x00400000 */
23522#define HRTIM_ADC3R_AD3TCC4 HRTIM_ADC3R_AD3TCC4_Msk /*!< ADC Trigger 3 on Timer C compare 4 */
23523#define HRTIM_ADC3R_AD3TCPER_Pos (23U)
23524#define HRTIM_ADC3R_AD3TCPER_Msk (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos) /*!< 0x00800000 */
23525#define HRTIM_ADC3R_AD3TCPER HRTIM_ADC3R_AD3TCPER_Msk /*!< ADC Trigger 3 on Timer C period */
23526#define HRTIM_ADC3R_AD3TDC2_Pos (24U)
23527#define HRTIM_ADC3R_AD3TDC2_Msk (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos) /*!< 0x01000000 */
23528#define HRTIM_ADC3R_AD3TDC2 HRTIM_ADC3R_AD3TDC2_Msk /*!< ADC Trigger 3 on Timer D compare 2 */
23529#define HRTIM_ADC3R_AD3TDC3_Pos (25U)
23530#define HRTIM_ADC3R_AD3TDC3_Msk (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos) /*!< 0x02000000 */
23531#define HRTIM_ADC3R_AD3TDC3 HRTIM_ADC3R_AD3TDC3_Msk /*!< ADC Trigger 3 on Timer D compare 3 */
23532#define HRTIM_ADC3R_AD3TDC4_Pos (26U)
23533#define HRTIM_ADC3R_AD3TDC4_Msk (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos) /*!< 0x04000000 */
23534#define HRTIM_ADC3R_AD3TDC4 HRTIM_ADC3R_AD3TDC4_Msk /*!< ADC Trigger 3 on Timer D compare 4 */
23535#define HRTIM_ADC3R_AD3TDPER_Pos (27U)
23536#define HRTIM_ADC3R_AD3TDPER_Msk (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos) /*!< 0x08000000 */
23537#define HRTIM_ADC3R_AD3TDPER HRTIM_ADC3R_AD3TDPER_Msk /*!< ADC Trigger 3 on Timer D period */
23538#define HRTIM_ADC3R_AD3TEC2_Pos (28U)
23539#define HRTIM_ADC3R_AD3TEC2_Msk (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos) /*!< 0x10000000 */
23540#define HRTIM_ADC3R_AD3TEC2 HRTIM_ADC3R_AD3TEC2_Msk /*!< ADC Trigger 3 on Timer E compare 2 */
23541#define HRTIM_ADC3R_AD3TEC3_Pos (29U)
23542#define HRTIM_ADC3R_AD3TEC3_Msk (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos) /*!< 0x20000000 */
23543#define HRTIM_ADC3R_AD3TEC3 HRTIM_ADC3R_AD3TEC3_Msk /*!< ADC Trigger 3 on Timer E compare 3 */
23544#define HRTIM_ADC3R_AD3TEC4_Pos (30U)
23545#define HRTIM_ADC3R_AD3TEC4_Msk (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos) /*!< 0x40000000 */
23546#define HRTIM_ADC3R_AD3TEC4 HRTIM_ADC3R_AD3TEC4_Msk /*!< ADC Trigger 3 on Timer E compare 4 */
23547#define HRTIM_ADC3R_AD3TEPER_Pos (31U)
23548#define HRTIM_ADC3R_AD3TEPER_Msk (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos) /*!< 0x80000000 */
23549#define HRTIM_ADC3R_AD3TEPER HRTIM_ADC3R_AD3TEPER_Msk /*!< ADC Trigger 3 on Timer E period */
23550
23551/******************* Bit definition for HRTIM_ADC4R register ****************/
23552#define HRTIM_ADC4R_AD4MC1_Pos (0U)
23553#define HRTIM_ADC4R_AD4MC1_Msk (0x1UL << HRTIM_ADC4R_AD4MC1_Pos) /*!< 0x00000001 */
23554#define HRTIM_ADC4R_AD4MC1 HRTIM_ADC4R_AD4MC1_Msk /*!< ADC Trigger 4 on master compare 1 */
23555#define HRTIM_ADC4R_AD4MC2_Pos (1U)
23556#define HRTIM_ADC4R_AD4MC2_Msk (0x1UL << HRTIM_ADC4R_AD4MC2_Pos) /*!< 0x00000002 */
23557#define HRTIM_ADC4R_AD4MC2 HRTIM_ADC4R_AD4MC2_Msk /*!< ADC Trigger 4 on master compare 2 */
23558#define HRTIM_ADC4R_AD4MC3_Pos (2U)
23559#define HRTIM_ADC4R_AD4MC3_Msk (0x1UL << HRTIM_ADC4R_AD4MC3_Pos) /*!< 0x00000004 */
23560#define HRTIM_ADC4R_AD4MC3 HRTIM_ADC4R_AD4MC3_Msk /*!< ADC Trigger 4 on master compare 3 */
23561#define HRTIM_ADC4R_AD4MC4_Pos (3U)
23562#define HRTIM_ADC4R_AD4MC4_Msk (0x1UL << HRTIM_ADC4R_AD4MC4_Pos) /*!< 0x00000008 */
23563#define HRTIM_ADC4R_AD4MC4 HRTIM_ADC4R_AD4MC4_Msk /*!< ADC Trigger 4 on master compare 4 */
23564#define HRTIM_ADC4R_AD4MPER_Pos (4U)
23565#define HRTIM_ADC4R_AD4MPER_Msk (0x1UL << HRTIM_ADC4R_AD4MPER_Pos) /*!< 0x00000010 */
23566#define HRTIM_ADC4R_AD4MPER HRTIM_ADC4R_AD4MPER_Msk /*!< ADC Trigger 4 on master period */
23567#define HRTIM_ADC4R_AD4EEV6_Pos (5U)
23568#define HRTIM_ADC4R_AD4EEV6_Msk (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos) /*!< 0x00000020 */
23569#define HRTIM_ADC4R_AD4EEV6 HRTIM_ADC4R_AD4EEV6_Msk /*!< ADC Trigger 4 on external event 6 */
23570#define HRTIM_ADC4R_AD4EEV7_Pos (6U)
23571#define HRTIM_ADC4R_AD4EEV7_Msk (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos) /*!< 0x00000040 */
23572#define HRTIM_ADC4R_AD4EEV7 HRTIM_ADC4R_AD4EEV7_Msk /*!< ADC Trigger 4 on external event 7 */
23573#define HRTIM_ADC4R_AD4EEV8_Pos (7U)
23574#define HRTIM_ADC4R_AD4EEV8_Msk (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos) /*!< 0x00000080 */
23575#define HRTIM_ADC4R_AD4EEV8 HRTIM_ADC4R_AD4EEV8_Msk /*!< ADC Trigger 4 on external event 8 */
23576#define HRTIM_ADC4R_AD4EEV9_Pos (8U)
23577#define HRTIM_ADC4R_AD4EEV9_Msk (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos) /*!< 0x00000100 */
23578#define HRTIM_ADC4R_AD4EEV9 HRTIM_ADC4R_AD4EEV9_Msk /*!< ADC Trigger 4 on external event 9 */
23579#define HRTIM_ADC4R_AD4EEV10_Pos (9U)
23580#define HRTIM_ADC4R_AD4EEV10_Msk (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos) /*!< 0x00000200 */
23581#define HRTIM_ADC4R_AD4EEV10 HRTIM_ADC4R_AD4EEV10_Msk /*!< ADC Trigger 4 on external event 10 */
23582#define HRTIM_ADC4R_AD4TAC2_Pos (10U)
23583#define HRTIM_ADC4R_AD4TAC2_Msk (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos) /*!< 0x00000400 */
23584#define HRTIM_ADC4R_AD4TAC2 HRTIM_ADC4R_AD4TAC2_Msk /*!< ADC Trigger 4 on Timer A compare 2 */
23585#define HRTIM_ADC4R_AD4TAC3_Pos (11U)
23586#define HRTIM_ADC4R_AD4TAC3_Msk (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos) /*!< 0x00000800 */
23587#define HRTIM_ADC4R_AD4TAC3 HRTIM_ADC4R_AD4TAC3_Msk /*!< ADC Trigger 4 on Timer A compare 3 */
23588#define HRTIM_ADC4R_AD4TAC4_Pos (12U)
23589#define HRTIM_ADC4R_AD4TAC4_Msk (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos) /*!< 0x00001000 */
23590#define HRTIM_ADC4R_AD4TAC4 HRTIM_ADC4R_AD4TAC4_Msk /*!< ADC Trigger 4 on Timer A compare 4*/
23591#define HRTIM_ADC4R_AD4TAPER_Pos (13U)
23592#define HRTIM_ADC4R_AD4TAPER_Msk (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos) /*!< 0x00002000 */
23593#define HRTIM_ADC4R_AD4TAPER HRTIM_ADC4R_AD4TAPER_Msk /*!< ADC Trigger 4 on Timer A period */
23594#define HRTIM_ADC4R_AD4TBC2_Pos (14U)
23595#define HRTIM_ADC4R_AD4TBC2_Msk (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos) /*!< 0x00004000 */
23596#define HRTIM_ADC4R_AD4TBC2 HRTIM_ADC4R_AD4TBC2_Msk /*!< ADC Trigger 4 on Timer B compare 2 */
23597#define HRTIM_ADC4R_AD4TBC3_Pos (15U)
23598#define HRTIM_ADC4R_AD4TBC3_Msk (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos) /*!< 0x00008000 */
23599#define HRTIM_ADC4R_AD4TBC3 HRTIM_ADC4R_AD4TBC3_Msk /*!< ADC Trigger 4 on Timer B compare 3 */
23600#define HRTIM_ADC4R_AD4TBC4_Pos (16U)
23601#define HRTIM_ADC4R_AD4TBC4_Msk (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos) /*!< 0x00010000 */
23602#define HRTIM_ADC4R_AD4TBC4 HRTIM_ADC4R_AD4TBC4_Msk /*!< ADC Trigger 4 on Timer B compare 4 */
23603#define HRTIM_ADC4R_AD4TBPER_Pos (17U)
23604#define HRTIM_ADC4R_AD4TBPER_Msk (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos) /*!< 0x00020000 */
23605#define HRTIM_ADC4R_AD4TBPER HRTIM_ADC4R_AD4TBPER_Msk /*!< ADC Trigger 4 on Timer B period */
23606#define HRTIM_ADC4R_AD4TCC2_Pos (18U)
23607#define HRTIM_ADC4R_AD4TCC2_Msk (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos) /*!< 0x00040000 */
23608#define HRTIM_ADC4R_AD4TCC2 HRTIM_ADC4R_AD4TCC2_Msk /*!< ADC Trigger 4 on Timer C compare 2 */
23609#define HRTIM_ADC4R_AD4TCC3_Pos (19U)
23610#define HRTIM_ADC4R_AD4TCC3_Msk (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos) /*!< 0x00080000 */
23611#define HRTIM_ADC4R_AD4TCC3 HRTIM_ADC4R_AD4TCC3_Msk /*!< ADC Trigger 4 on Timer C compare 3 */
23612#define HRTIM_ADC4R_AD4TCC4_Pos (20U)
23613#define HRTIM_ADC4R_AD4TCC4_Msk (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos) /*!< 0x00100000 */
23614#define HRTIM_ADC4R_AD4TCC4 HRTIM_ADC4R_AD4TCC4_Msk /*!< ADC Trigger 4 on Timer C compare 4 */
23615#define HRTIM_ADC4R_AD4TCPER_Pos (21U)
23616#define HRTIM_ADC4R_AD4TCPER_Msk (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos) /*!< 0x00200000 */
23617#define HRTIM_ADC4R_AD4TCPER HRTIM_ADC4R_AD4TCPER_Msk /*!< ADC Trigger 4 on Timer C period */
23618#define HRTIM_ADC4R_AD4TCRST_Pos (22U)
23619#define HRTIM_ADC4R_AD4TCRST_Msk (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos) /*!< 0x00400000 */
23620#define HRTIM_ADC4R_AD4TCRST HRTIM_ADC4R_AD4TCRST_Msk /*!< ADC Trigger 4 on Timer C reset */
23621#define HRTIM_ADC4R_AD4TDC2_Pos (23U)
23622#define HRTIM_ADC4R_AD4TDC2_Msk (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos) /*!< 0x00800000 */
23623#define HRTIM_ADC4R_AD4TDC2 HRTIM_ADC4R_AD4TDC2_Msk /*!< ADC Trigger 4 on Timer D compare 2 */
23624#define HRTIM_ADC4R_AD4TDC3_Pos (24U)
23625#define HRTIM_ADC4R_AD4TDC3_Msk (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos) /*!< 0x01000000 */
23626#define HRTIM_ADC4R_AD4TDC3 HRTIM_ADC4R_AD4TDC3_Msk /*!< ADC Trigger 4 on Timer D compare 3 */
23627#define HRTIM_ADC4R_AD4TDC4_Pos (25U)
23628#define HRTIM_ADC4R_AD4TDC4_Msk (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos) /*!< 0x02000000 */
23629#define HRTIM_ADC4R_AD4TDC4 HRTIM_ADC4R_AD4TDC4_Msk /*!< ADC Trigger 4 on Timer D compare 4*/
23630#define HRTIM_ADC4R_AD4TDPER_Pos (26U)
23631#define HRTIM_ADC4R_AD4TDPER_Msk (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos) /*!< 0x04000000 */
23632#define HRTIM_ADC4R_AD4TDPER HRTIM_ADC4R_AD4TDPER_Msk /*!< ADC Trigger 4 on Timer D period */
23633#define HRTIM_ADC4R_AD4TDRST_Pos (27U)
23634#define HRTIM_ADC4R_AD4TDRST_Msk (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos) /*!< 0x08000000 */
23635#define HRTIM_ADC4R_AD4TDRST HRTIM_ADC4R_AD4TDRST_Msk /*!< ADC Trigger 4 on Timer D reset */
23636#define HRTIM_ADC4R_AD4TEC2_Pos (28U)
23637#define HRTIM_ADC4R_AD4TEC2_Msk (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos) /*!< 0x10000000 */
23638#define HRTIM_ADC4R_AD4TEC2 HRTIM_ADC4R_AD4TEC2_Msk /*!< ADC Trigger 4 on Timer E compare 2 */
23639#define HRTIM_ADC4R_AD4TEC3_Pos (29U)
23640#define HRTIM_ADC4R_AD4TEC3_Msk (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos) /*!< 0x20000000 */
23641#define HRTIM_ADC4R_AD4TEC3 HRTIM_ADC4R_AD4TEC3_Msk /*!< ADC Trigger 4 on Timer E compare 3 */
23642#define HRTIM_ADC4R_AD4TEC4_Pos (30U)
23643#define HRTIM_ADC4R_AD4TEC4_Msk (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos) /*!< 0x40000000 */
23644#define HRTIM_ADC4R_AD4TEC4 HRTIM_ADC4R_AD4TEC4_Msk /*!< ADC Trigger 4 on Timer E compare 4 */
23645#define HRTIM_ADC4R_AD4TERST_Pos (31U)
23646#define HRTIM_ADC4R_AD4TERST_Msk (0x1UL << HRTIM_ADC4R_AD4TERST_Pos) /*!< 0x80000000 */
23647#define HRTIM_ADC4R_AD4TERST HRTIM_ADC4R_AD4TERST_Msk /*!< ADC Trigger 4 on Timer E reset */
23648
23649/******************* Bit definition for HRTIM_FLTINR1 register ***************/
23650#define HRTIM_FLTINR1_FLT1E_Pos (0U)
23651#define HRTIM_FLTINR1_FLT1E_Msk (0x1UL << HRTIM_FLTINR1_FLT1E_Pos) /*!< 0x00000001 */
23652#define HRTIM_FLTINR1_FLT1E HRTIM_FLTINR1_FLT1E_Msk /*!< Fault 1 enable */
23653#define HRTIM_FLTINR1_FLT1P_Pos (1U)
23654#define HRTIM_FLTINR1_FLT1P_Msk (0x1UL << HRTIM_FLTINR1_FLT1P_Pos) /*!< 0x00000002 */
23655#define HRTIM_FLTINR1_FLT1P HRTIM_FLTINR1_FLT1P_Msk /*!< Fault 1 polarity */
23656#define HRTIM_FLTINR1_FLT1SRC_Pos (2U)
23657#define HRTIM_FLTINR1_FLT1SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos) /*!< 0x00000004 */
23658#define HRTIM_FLTINR1_FLT1SRC HRTIM_FLTINR1_FLT1SRC_Msk /*!< Fault 1 source */
23659#define HRTIM_FLTINR1_FLT1F_Pos (3U)
23660#define HRTIM_FLTINR1_FLT1F_Msk (0xFUL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000078 */
23661#define HRTIM_FLTINR1_FLT1F HRTIM_FLTINR1_FLT1F_Msk /*!< Fault 1 filter */
23662#define HRTIM_FLTINR1_FLT1F_0 (0x1UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000008 */
23663#define HRTIM_FLTINR1_FLT1F_1 (0x2UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000010 */
23664#define HRTIM_FLTINR1_FLT1F_2 (0x4UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000020 */
23665#define HRTIM_FLTINR1_FLT1F_3 (0x8UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000040 */
23666#define HRTIM_FLTINR1_FLT1LCK_Pos (7U)
23667#define HRTIM_FLTINR1_FLT1LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos) /*!< 0x00000080 */
23668#define HRTIM_FLTINR1_FLT1LCK HRTIM_FLTINR1_FLT1LCK_Msk /*!< Fault 1 lock */
23669
23670#define HRTIM_FLTINR1_FLT2E_Pos (8U)
23671#define HRTIM_FLTINR1_FLT2E_Msk (0x1UL << HRTIM_FLTINR1_FLT2E_Pos) /*!< 0x00000100 */
23672#define HRTIM_FLTINR1_FLT2E HRTIM_FLTINR1_FLT2E_Msk /*!< Fault 2 enable */
23673#define HRTIM_FLTINR1_FLT2P_Pos (9U)
23674#define HRTIM_FLTINR1_FLT2P_Msk (0x1UL << HRTIM_FLTINR1_FLT2P_Pos) /*!< 0x00000200 */
23675#define HRTIM_FLTINR1_FLT2P HRTIM_FLTINR1_FLT2P_Msk /*!< Fault 2 polarity */
23676#define HRTIM_FLTINR1_FLT2SRC_Pos (10U)
23677#define HRTIM_FLTINR1_FLT2SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos) /*!< 0x00000400 */
23678#define HRTIM_FLTINR1_FLT2SRC HRTIM_FLTINR1_FLT2SRC_Msk /*!< Fault 2 source */
23679#define HRTIM_FLTINR1_FLT2F_Pos (11U)
23680#define HRTIM_FLTINR1_FLT2F_Msk (0xFUL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00007800 */
23681#define HRTIM_FLTINR1_FLT2F HRTIM_FLTINR1_FLT2F_Msk /*!< Fault 2 filter */
23682#define HRTIM_FLTINR1_FLT2F_0 (0x1UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00000800 */
23683#define HRTIM_FLTINR1_FLT2F_1 (0x2UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00001000 */
23684#define HRTIM_FLTINR1_FLT2F_2 (0x4UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00002000 */
23685#define HRTIM_FLTINR1_FLT2F_3 (0x8UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00004000 */
23686#define HRTIM_FLTINR1_FLT2LCK_Pos (15U)
23687#define HRTIM_FLTINR1_FLT2LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos) /*!< 0x00008000 */
23688#define HRTIM_FLTINR1_FLT2LCK HRTIM_FLTINR1_FLT2LCK_Msk /*!< Fault 2 lock */
23689
23690#define HRTIM_FLTINR1_FLT3E_Pos (16U)
23691#define HRTIM_FLTINR1_FLT3E_Msk (0x1UL << HRTIM_FLTINR1_FLT3E_Pos) /*!< 0x00010000 */
23692#define HRTIM_FLTINR1_FLT3E HRTIM_FLTINR1_FLT3E_Msk /*!< Fault 3 enable */
23693#define HRTIM_FLTINR1_FLT3P_Pos (17U)
23694#define HRTIM_FLTINR1_FLT3P_Msk (0x1UL << HRTIM_FLTINR1_FLT3P_Pos) /*!< 0x00020000 */
23695#define HRTIM_FLTINR1_FLT3P HRTIM_FLTINR1_FLT3P_Msk /*!< Fault 3 polarity */
23696#define HRTIM_FLTINR1_FLT3SRC_Pos (18U)
23697#define HRTIM_FLTINR1_FLT3SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos) /*!< 0x00040000 */
23698#define HRTIM_FLTINR1_FLT3SRC HRTIM_FLTINR1_FLT3SRC_Msk /*!< Fault 3 source */
23699#define HRTIM_FLTINR1_FLT3F_Pos (19U)
23700#define HRTIM_FLTINR1_FLT3F_Msk (0xFUL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00780000 */
23701#define HRTIM_FLTINR1_FLT3F HRTIM_FLTINR1_FLT3F_Msk /*!< Fault 3 filter */
23702#define HRTIM_FLTINR1_FLT3F_0 (0x1UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00080000 */
23703#define HRTIM_FLTINR1_FLT3F_1 (0x2UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00100000 */
23704#define HRTIM_FLTINR1_FLT3F_2 (0x4UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00200000 */
23705#define HRTIM_FLTINR1_FLT3F_3 (0x8UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00400000 */
23706#define HRTIM_FLTINR1_FLT3LCK_Pos (23U)
23707#define HRTIM_FLTINR1_FLT3LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos) /*!< 0x00800000 */
23708#define HRTIM_FLTINR1_FLT3LCK HRTIM_FLTINR1_FLT3LCK_Msk /*!< Fault 3 lock */
23709
23710#define HRTIM_FLTINR1_FLT4E_Pos (24U)
23711#define HRTIM_FLTINR1_FLT4E_Msk (0x1UL << HRTIM_FLTINR1_FLT4E_Pos) /*!< 0x01000000 */
23712#define HRTIM_FLTINR1_FLT4E HRTIM_FLTINR1_FLT4E_Msk /*!< Fault 4 enable */
23713#define HRTIM_FLTINR1_FLT4P_Pos (25U)
23714#define HRTIM_FLTINR1_FLT4P_Msk (0x1UL << HRTIM_FLTINR1_FLT4P_Pos) /*!< 0x02000000 */
23715#define HRTIM_FLTINR1_FLT4P HRTIM_FLTINR1_FLT4P_Msk /*!< Fault 4 polarity */
23716#define HRTIM_FLTINR1_FLT4SRC_Pos (26U)
23717#define HRTIM_FLTINR1_FLT4SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos) /*!< 0x04000000 */
23718#define HRTIM_FLTINR1_FLT4SRC HRTIM_FLTINR1_FLT4SRC_Msk /*!< Fault 4 source */
23719#define HRTIM_FLTINR1_FLT4F_Pos (27U)
23720#define HRTIM_FLTINR1_FLT4F_Msk (0xFUL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x78000000 */
23721#define HRTIM_FLTINR1_FLT4F HRTIM_FLTINR1_FLT4F_Msk /*!< Fault 4 filter */
23722#define HRTIM_FLTINR1_FLT4F_0 (0x1UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x08000000 */
23723#define HRTIM_FLTINR1_FLT4F_1 (0x2UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x10000000 */
23724#define HRTIM_FLTINR1_FLT4F_2 (0x4UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x20000000 */
23725#define HRTIM_FLTINR1_FLT4F_3 (0x8UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x40000000 */
23726#define HRTIM_FLTINR1_FLT4LCK_Pos (31U)
23727#define HRTIM_FLTINR1_FLT4LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos) /*!< 0x80000000 */
23728#define HRTIM_FLTINR1_FLT4LCK HRTIM_FLTINR1_FLT4LCK_Msk /*!< Fault 4 lock */
23729
23730/******************* Bit definition for HRTIM_FLTINR2 register ***************/
23731#define HRTIM_FLTINR2_FLT5E_Pos (0U)
23732#define HRTIM_FLTINR2_FLT5E_Msk (0x1UL << HRTIM_FLTINR2_FLT5E_Pos) /*!< 0x00000001 */
23733#define HRTIM_FLTINR2_FLT5E HRTIM_FLTINR2_FLT5E_Msk /*!< Fault 5 enable */
23734#define HRTIM_FLTINR2_FLT5P_Pos (1U)
23735#define HRTIM_FLTINR2_FLT5P_Msk (0x1UL << HRTIM_FLTINR2_FLT5P_Pos) /*!< 0x00000002 */
23736#define HRTIM_FLTINR2_FLT5P HRTIM_FLTINR2_FLT5P_Msk /*!< Fault 5 polarity */
23737#define HRTIM_FLTINR2_FLT5SRC_Pos (2U)
23738#define HRTIM_FLTINR2_FLT5SRC_Msk (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos) /*!< 0x00000004 */
23739#define HRTIM_FLTINR2_FLT5SRC HRTIM_FLTINR2_FLT5SRC_Msk /*!< Fault 5 source */
23740#define HRTIM_FLTINR2_FLT5F_Pos (3U)
23741#define HRTIM_FLTINR2_FLT5F_Msk (0xFUL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000078 */
23742#define HRTIM_FLTINR2_FLT5F HRTIM_FLTINR2_FLT5F_Msk /*!< Fault 5 filter */
23743#define HRTIM_FLTINR2_FLT5F_0 (0x1UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000008 */
23744#define HRTIM_FLTINR2_FLT5F_1 (0x2UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000010 */
23745#define HRTIM_FLTINR2_FLT5F_2 (0x4UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000020 */
23746#define HRTIM_FLTINR2_FLT5F_3 (0x8UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000040 */
23747#define HRTIM_FLTINR2_FLT5LCK_Pos (7U)
23748#define HRTIM_FLTINR2_FLT5LCK_Msk (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos) /*!< 0x00000080 */
23749#define HRTIM_FLTINR2_FLT5LCK HRTIM_FLTINR2_FLT5LCK_Msk /*!< Fault 5 lock */
23750#define HRTIM_FLTINR2_FLTSD_Pos (24U)
23751#define HRTIM_FLTINR2_FLTSD_Msk (0x3UL << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x03000000 */
23752#define HRTIM_FLTINR2_FLTSD HRTIM_FLTINR2_FLTSD_Msk /*!< Fault sampling clock division */
23753#define HRTIM_FLTINR2_FLTSD_0 (0x1UL << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x01000000 */
23754#define HRTIM_FLTINR2_FLTSD_1 (0x2UL << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x02000000 */
23755
23756/******************* Bit definition for HRTIM_BDMUPR register ***************/
23757#define HRTIM_BDMUPR_MCR_Pos (0U)
23758#define HRTIM_BDMUPR_MCR_Msk (0x1UL << HRTIM_BDMUPR_MCR_Pos) /*!< 0x00000001 */
23759#define HRTIM_BDMUPR_MCR HRTIM_BDMUPR_MCR_Msk /*!< MCR register update enable */
23760#define HRTIM_BDMUPR_MICR_Pos (1U)
23761#define HRTIM_BDMUPR_MICR_Msk (0x1UL << HRTIM_BDMUPR_MICR_Pos) /*!< 0x00000002 */
23762#define HRTIM_BDMUPR_MICR HRTIM_BDMUPR_MICR_Msk /*!< MICR register update enable */
23763#define HRTIM_BDMUPR_MDIER_Pos (2U)
23764#define HRTIM_BDMUPR_MDIER_Msk (0x1UL << HRTIM_BDMUPR_MDIER_Pos) /*!< 0x00000004 */
23765#define HRTIM_BDMUPR_MDIER HRTIM_BDMUPR_MDIER_Msk /*!< MDIER register update enable */
23766#define HRTIM_BDMUPR_MCNT_Pos (3U)
23767#define HRTIM_BDMUPR_MCNT_Msk (0x1UL << HRTIM_BDMUPR_MCNT_Pos) /*!< 0x00000008 */
23768#define HRTIM_BDMUPR_MCNT HRTIM_BDMUPR_MCNT_Msk /*!< MCNT register update enable */
23769#define HRTIM_BDMUPR_MPER_Pos (4U)
23770#define HRTIM_BDMUPR_MPER_Msk (0x1UL << HRTIM_BDMUPR_MPER_Pos) /*!< 0x00000010 */
23771#define HRTIM_BDMUPR_MPER HRTIM_BDMUPR_MPER_Msk /*!< MPER register update enable */
23772#define HRTIM_BDMUPR_MREP_Pos (5U)
23773#define HRTIM_BDMUPR_MREP_Msk (0x1UL << HRTIM_BDMUPR_MREP_Pos) /*!< 0x00000020 */
23774#define HRTIM_BDMUPR_MREP HRTIM_BDMUPR_MREP_Msk /*!< MREP register update enable */
23775#define HRTIM_BDMUPR_MCMP1_Pos (6U)
23776#define HRTIM_BDMUPR_MCMP1_Msk (0x1UL << HRTIM_BDMUPR_MCMP1_Pos) /*!< 0x00000040 */
23777#define HRTIM_BDMUPR_MCMP1 HRTIM_BDMUPR_MCMP1_Msk /*!< MCMP1 register update enable */
23778#define HRTIM_BDMUPR_MCMP2_Pos (7U)
23779#define HRTIM_BDMUPR_MCMP2_Msk (0x1UL << HRTIM_BDMUPR_MCMP2_Pos) /*!< 0x00000080 */
23780#define HRTIM_BDMUPR_MCMP2 HRTIM_BDMUPR_MCMP2_Msk /*!< MCMP2 register update enable */
23781#define HRTIM_BDMUPR_MCMP3_Pos (8U)
23782#define HRTIM_BDMUPR_MCMP3_Msk (0x1UL << HRTIM_BDMUPR_MCMP3_Pos) /*!< 0x00000100 */
23783#define HRTIM_BDMUPR_MCMP3 HRTIM_BDMUPR_MCMP3_Msk /*!< MCMP3 register update enable */
23784#define HRTIM_BDMUPR_MCMP4_Pos (9U)
23785#define HRTIM_BDMUPR_MCMP4_Msk (0x1UL << HRTIM_BDMUPR_MCMP4_Pos) /*!< 0x00000200 */
23786#define HRTIM_BDMUPR_MCMP4 HRTIM_BDMUPR_MCMP4_Msk /*!< MPCMP4 register update enable */
23787
23788/******************* Bit definition for HRTIM_BDTUPR register ***************/
23789#define HRTIM_BDTUPR_TIMCR_Pos (0U)
23790#define HRTIM_BDTUPR_TIMCR_Msk (0x1UL << HRTIM_BDTUPR_TIMCR_Pos) /*!< 0x00000001 */
23791#define HRTIM_BDTUPR_TIMCR HRTIM_BDTUPR_TIMCR_Msk /*!< TIMCR register update enable */
23792#define HRTIM_BDTUPR_TIMICR_Pos (1U)
23793#define HRTIM_BDTUPR_TIMICR_Msk (0x1UL << HRTIM_BDTUPR_TIMICR_Pos) /*!< 0x00000002 */
23794#define HRTIM_BDTUPR_TIMICR HRTIM_BDTUPR_TIMICR_Msk /*!< TIMICR register update enable */
23795#define HRTIM_BDTUPR_TIMDIER_Pos (2U)
23796#define HRTIM_BDTUPR_TIMDIER_Msk (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos) /*!< 0x00000004 */
23797#define HRTIM_BDTUPR_TIMDIER HRTIM_BDTUPR_TIMDIER_Msk /*!< TIMDIER register update enable */
23798#define HRTIM_BDTUPR_TIMCNT_Pos (3U)
23799#define HRTIM_BDTUPR_TIMCNT_Msk (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos) /*!< 0x00000008 */
23800#define HRTIM_BDTUPR_TIMCNT HRTIM_BDTUPR_TIMCNT_Msk /*!< TIMCNT register update enable */
23801#define HRTIM_BDTUPR_TIMPER_Pos (4U)
23802#define HRTIM_BDTUPR_TIMPER_Msk (0x1UL << HRTIM_BDTUPR_TIMPER_Pos) /*!< 0x00000010 */
23803#define HRTIM_BDTUPR_TIMPER HRTIM_BDTUPR_TIMPER_Msk /*!< TIMPER register update enable */
23804#define HRTIM_BDTUPR_TIMREP_Pos (5U)
23805#define HRTIM_BDTUPR_TIMREP_Msk (0x1UL << HRTIM_BDTUPR_TIMREP_Pos) /*!< 0x00000020 */
23806#define HRTIM_BDTUPR_TIMREP HRTIM_BDTUPR_TIMREP_Msk /*!< TIMREP register update enable */
23807#define HRTIM_BDTUPR_TIMCMP1_Pos (6U)
23808#define HRTIM_BDTUPR_TIMCMP1_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos) /*!< 0x00000040 */
23809#define HRTIM_BDTUPR_TIMCMP1 HRTIM_BDTUPR_TIMCMP1_Msk /*!< TIMCMP1 register update enable */
23810#define HRTIM_BDTUPR_TIMCMP2_Pos (7U)
23811#define HRTIM_BDTUPR_TIMCMP2_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos) /*!< 0x00000080 */
23812#define HRTIM_BDTUPR_TIMCMP2 HRTIM_BDTUPR_TIMCMP2_Msk /*!< TIMCMP2 register update enable */
23813#define HRTIM_BDTUPR_TIMCMP3_Pos (8U)
23814#define HRTIM_BDTUPR_TIMCMP3_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos) /*!< 0x00000100 */
23815#define HRTIM_BDTUPR_TIMCMP3 HRTIM_BDTUPR_TIMCMP3_Msk /*!< TIMCMP3 register update enable */
23816#define HRTIM_BDTUPR_TIMCMP4_Pos (9U)
23817#define HRTIM_BDTUPR_TIMCMP4_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos) /*!< 0x00000200 */
23818#define HRTIM_BDTUPR_TIMCMP4 HRTIM_BDTUPR_TIMCMP4_Msk /*!< TIMCMP4 register update enable */
23819#define HRTIM_BDTUPR_TIMDTR_Pos (10U)
23820#define HRTIM_BDTUPR_TIMDTR_Msk (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos) /*!< 0x00000400 */
23821#define HRTIM_BDTUPR_TIMDTR HRTIM_BDTUPR_TIMDTR_Msk /*!< TIMDTR register update enable */
23822#define HRTIM_BDTUPR_TIMSET1R_Pos (11U)
23823#define HRTIM_BDTUPR_TIMSET1R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos) /*!< 0x00000800 */
23824#define HRTIM_BDTUPR_TIMSET1R HRTIM_BDTUPR_TIMSET1R_Msk /*!< TIMSET1R register update enable */
23825#define HRTIM_BDTUPR_TIMRST1R_Pos (12U)
23826#define HRTIM_BDTUPR_TIMRST1R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos) /*!< 0x00001000 */
23827#define HRTIM_BDTUPR_TIMRST1R HRTIM_BDTUPR_TIMRST1R_Msk /*!< TIMRST1R register update enable */
23828#define HRTIM_BDTUPR_TIMSET2R_Pos (13U)
23829#define HRTIM_BDTUPR_TIMSET2R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos) /*!< 0x00002000 */
23830#define HRTIM_BDTUPR_TIMSET2R HRTIM_BDTUPR_TIMSET2R_Msk /*!< TIMSET2R register update enable */
23831#define HRTIM_BDTUPR_TIMRST2R_Pos (14U)
23832#define HRTIM_BDTUPR_TIMRST2R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos) /*!< 0x00004000 */
23833#define HRTIM_BDTUPR_TIMRST2R HRTIM_BDTUPR_TIMRST2R_Msk /*!< TIMRST2R register update enable */
23834#define HRTIM_BDTUPR_TIMEEFR1_Pos (15U)
23835#define HRTIM_BDTUPR_TIMEEFR1_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos) /*!< 0x00008000 */
23836#define HRTIM_BDTUPR_TIMEEFR1 HRTIM_BDTUPR_TIMEEFR1_Msk /*!< TIMEEFR1 register update enable */
23837#define HRTIM_BDTUPR_TIMEEFR2_Pos (16U)
23838#define HRTIM_BDTUPR_TIMEEFR2_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos) /*!< 0x00010000 */
23839#define HRTIM_BDTUPR_TIMEEFR2 HRTIM_BDTUPR_TIMEEFR2_Msk /*!< TIMEEFR2 register update enable */
23840#define HRTIM_BDTUPR_TIMRSTR_Pos (17U)
23841#define HRTIM_BDTUPR_TIMRSTR_Msk (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos) /*!< 0x00020000 */
23842#define HRTIM_BDTUPR_TIMRSTR HRTIM_BDTUPR_TIMRSTR_Msk /*!< TIMRSTR register update enable */
23843#define HRTIM_BDTUPR_TIMCHPR_Pos (18U)
23844#define HRTIM_BDTUPR_TIMCHPR_Msk (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos) /*!< 0x00040000 */
23845#define HRTIM_BDTUPR_TIMCHPR HRTIM_BDTUPR_TIMCHPR_Msk /*!< TIMCHPR register update enable */
23846#define HRTIM_BDTUPR_TIMOUTR_Pos (19U)
23847#define HRTIM_BDTUPR_TIMOUTR_Msk (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos) /*!< 0x00080000 */
23848#define HRTIM_BDTUPR_TIMOUTR HRTIM_BDTUPR_TIMOUTR_Msk /*!< TIMOUTR register update enable */
23849#define HRTIM_BDTUPR_TIMFLTR_Pos (20U)
23850#define HRTIM_BDTUPR_TIMFLTR_Msk (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos) /*!< 0x00100000 */
23851#define HRTIM_BDTUPR_TIMFLTR HRTIM_BDTUPR_TIMFLTR_Msk /*!< TIMFLTR register update enable */
23852
23853/******************* Bit definition for HRTIM_BDMADR register ***************/
23854#define HRTIM_BDMADR_BDMADR_Pos (0U)
23855#define HRTIM_BDMADR_BDMADR_Msk (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos) /*!< 0xFFFFFFFF */
23856#define HRTIM_BDMADR_BDMADR HRTIM_BDMADR_BDMADR_Msk /*!< Burst DMA Data register */
23857
23858/******************************************************************************/
23859/* */
23860/* RAM ECC monitoring */
23861/* */
23862/******************************************************************************/
23863/****************** Bit definition for RAMECC_IER register ******************/
23864#define RAMECC_IER_GECCDEBWIE_Pos (3U)
23865#define RAMECC_IER_GECCDEBWIE_Msk (0x1UL << RAMECC_IER_GECCDEBWIE_Pos) /*!< 0x00000008 */
23866#define RAMECC_IER_GECCDEBWIE RAMECC_IER_GECCDEBWIE_Msk /*!< Global ECC double error on byte write (BW) interrupt enable */
23867#define RAMECC_IER_GECCDEIE_Pos (2U)
23868#define RAMECC_IER_GECCDEIE_Msk (0x1UL << RAMECC_IER_GECCDEIE_Pos) /*!< 0x00000004 */
23869#define RAMECC_IER_GECCDEIE RAMECC_IER_GECCDEIE_Msk /*!< Global ECC double error interrupt enable */
23870#define RAMECC_IER_GECCSEIE_Pos (1U)
23871#define RAMECC_IER_GECCSEIE_Msk (0x1UL << RAMECC_IER_GECCSEIE_Pos) /*!< 0x00000002 */
23872#define RAMECC_IER_GECCSEIE RAMECC_IER_GECCSEIE_Msk /*!< Global ECC single error interrupt enable */
23873#define RAMECC_IER_GIE_Pos (0U)
23874#define RAMECC_IER_GIE_Msk (0x1UL << RAMECC_IER_GIE_Pos) /*!< 0x00000001 */
23875#define RAMECC_IER_GIE RAMECC_IER_GIE_Msk /*!< Global interrupt enable */
23876
23877/******************* Bit definition for RAMECC_CR register ******************/
23878#define RAMECC_CR_ECCELEN_Pos (5U)
23879#define RAMECC_CR_ECCELEN_Msk (0x1UL << RAMECC_CR_ECCELEN_Pos) /*!< 0x00000020 */
23880#define RAMECC_CR_ECCELEN RAMECC_CR_ECCELEN_Msk /*!< ECC error latching enable */
23881#define RAMECC_CR_ECCDEBWIE_Pos (4U)
23882#define RAMECC_CR_ECCDEBWIE_Msk (0x1UL << RAMECC_CR_ECCDEBWIE_Pos) /*!< 0x00000010 */
23883#define RAMECC_CR_ECCDEBWIE RAMECC_CR_ECCDEBWIE_Msk /*!< ECC double error on byte write (BW) interrupt enable */
23884#define RAMECC_CR_ECCDEIE_Pos (3U)
23885#define RAMECC_CR_ECCDEIE_Msk (0x1UL << RAMECC_CR_ECCDEIE_Pos) /*!< 0x00000008 */
23886#define RAMECC_CR_ECCDEIE RAMECC_CR_ECCDEIE_Msk /*!< ECC double error interrupt enable */
23887#define RAMECC_CR_ECCSEIE_Pos (2U)
23888#define RAMECC_CR_ECCSEIE_Msk (0x1UL << RAMECC_CR_ECCSEIE_Pos) /*!< 0x00000004 */
23889#define RAMECC_CR_ECCSEIE RAMECC_CR_ECCSEIE_Msk /*!< ECC single error interrupt enable */
23890
23891/******************* Bit definition for RAMECC_SR register ******************/
23892#define RAMECC_SR_DEBWDF_Pos (2U)
23893#define RAMECC_SR_DEBWDF_Msk (0x1UL << RAMECC_SR_DEBWDF_Pos) /*!< 0x00000004 */
23894#define RAMECC_SR_DEBWDF RAMECC_SR_DEBWDF_Msk /*!< ECC double error on byte write (BW) detected flag */
23895#define RAMECC_SR_DEDF_Pos (1U)
23896#define RAMECC_SR_DEDF_Msk (0x1UL << RAMECC_SR_DEDF_Pos) /*!< 0x00000002 */
23897#define RAMECC_SR_DEDF RAMECC_SR_DEDF_Msk /*!< ECC double error detected flag */
23898#define RAMECC_SR_SEDCF_Pos (0U)
23899#define RAMECC_SR_SEDCF_Msk (0x1UL << RAMECC_SR_SEDCF_Pos) /*!< 0x00000001 */
23900#define RAMECC_SR_SEDCF RAMECC_SR_SEDCF_Msk /*!< ECC single error detected and corrected flag */
23901
23902/****************** Bit definition for RAMECC_FAR register ******************/
23903#define RAMECC_FAR_FADD_Pos (0U)
23904#define RAMECC_FAR_FADD_Msk (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos) /*!< 0xFFFFFFFF */
23905#define RAMECC_FAR_FADD RAMECC_FAR_FADD_Msk /*!< ECC error failing address */
23906
23907/****************** Bit definition for RAMECC_FDRL register *****************/
23908#define RAMECC_FAR_FDATAL_Pos (0U)
23909#define RAMECC_FAR_FDATAL_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */
23910#define RAMECC_FAR_FDATAL RAMECC_FAR_FDATAL_Msk /*!< ECC error failing address */
23911
23912/****************** Bit definition for RAMECC_FDRH register *****************/
23913#define RAMECC_FAR_FDATAH_Pos (0U)
23914#define RAMECC_FAR_FDATAH_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */
23915#define RAMECC_FAR_FDATAH RAMECC_FAR_FDATAH_Msk /* Failing data high (64-bit memory) */
23916
23917/***************** Bit definition for RAMECC_FECR register ******************/
23918#define RAMECC_FECR_FEC_Pos (0U)
23919#define RAMECC_FECR_FEC_Msk (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos) /*!< 0xFFFFFFFF */
23920#define RAMECC_FECR_FEC RAMECC_FECR_FEC_Msk /*!< Failing error code */
23921
23922/******************************************************************************/
23923/* */
23924/* MDIOS */
23925/* */
23926/******************************************************************************/
23927/******************** Bit definition for MDIOS_CR register *******************/
23928#define MDIOS_CR_EN_Pos (0U)
23929#define MDIOS_CR_EN_Msk (0x1UL << MDIOS_CR_EN_Pos) /*!< 0x00000001 */
23930#define MDIOS_CR_EN MDIOS_CR_EN_Msk /*!< MDIOS slave peripheral enable */
23931#define MDIOS_CR_WRIE_Pos (1U)
23932#define MDIOS_CR_WRIE_Msk (0x1UL << MDIOS_CR_WRIE_Pos) /*!< 0x00000002 */
23933#define MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk /*!< MDIOS slave register write interrupt enable. */
23934#define MDIOS_CR_RDIE_Pos (2U)
23935#define MDIOS_CR_RDIE_Msk (0x1UL << MDIOS_CR_RDIE_Pos) /*!< 0x00000004 */
23936#define MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk /*!< MDIOS slave register read interrupt enable. */
23937#define MDIOS_CR_EIE_Pos (3U)
23938#define MDIOS_CR_EIE_Msk (0x1UL << MDIOS_CR_EIE_Pos) /*!< 0x00000008 */
23939#define MDIOS_CR_EIE MDIOS_CR_EIE_Msk /*!< MDIOS slave register error interrupt enable. */
23940#define MDIOS_CR_DPC_Pos (7U)
23941#define MDIOS_CR_DPC_Msk (0x1UL << MDIOS_CR_DPC_Pos) /*!< 0x00000080 */
23942#define MDIOS_CR_DPC MDIOS_CR_DPC_Msk /*!< MDIOS slave disable preamble check. */
23943#define MDIOS_CR_PORT_ADDRESS_Pos (8U)
23944#define MDIOS_CR_PORT_ADDRESS_Msk (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001F00 */
23945#define MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk /*!< MDIOS slave port address mask. */
23946#define MDIOS_CR_PORT_ADDRESS_0 (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000100 */
23947#define MDIOS_CR_PORT_ADDRESS_1 (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000200 */
23948#define MDIOS_CR_PORT_ADDRESS_2 (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000400 */
23949#define MDIOS_CR_PORT_ADDRESS_3 (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000800 */
23950#define MDIOS_CR_PORT_ADDRESS_4 (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001000 */
23951
23952/******************** Bit definition for MDIOS_SR register *******************/
23953#define MDIOS_SR_PERF_Pos (0U)
23954#define MDIOS_SR_PERF_Msk (0x1UL << MDIOS_SR_PERF_Pos) /*!< 0x00000001 */
23955#define MDIOS_SR_PERF MDIOS_SR_PERF_Msk /*!< MDIOS slave turnaround error flag*/
23956#define MDIOS_SR_SERF_Pos (1U)
23957#define MDIOS_SR_SERF_Msk (0x1UL << MDIOS_SR_SERF_Pos) /*!< 0x00000002 */
23958#define MDIOS_SR_SERF MDIOS_SR_SERF_Msk /*!< MDIOS slave start error flag */
23959#define MDIOS_SR_TERF_Pos (2U)
23960#define MDIOS_SR_TERF_Msk (0x1UL << MDIOS_SR_TERF_Pos) /*!< 0x00000004 */
23961#define MDIOS_SR_TERF MDIOS_SR_TERF_Msk /*!< MDIOS slave preamble error flag */
23962
23963/******************** Bit definition for MDIOS_CLRFR register *******************/
23964#define MDIOS_SR_CPERF_Pos (0U)
23965#define MDIOS_SR_CPERF_Msk (0x1UL << MDIOS_SR_CPERF_Pos) /*!< 0x00000001 */
23966#define MDIOS_SR_CPERF MDIOS_SR_CPERF_Msk /*!< MDIOS slave Clear the turnaround error flag */
23967#define MDIOS_SR_CSERF_Pos (1U)
23968#define MDIOS_SR_CSERF_Msk (0x1UL << MDIOS_SR_CSERF_Pos) /*!< 0x00000002 */
23969#define MDIOS_SR_CSERF MDIOS_SR_CSERF_Msk /*!< MDIOS slave Clear the start error flag */
23970#define MDIOS_SR_CTERF_Pos (2U)
23971#define MDIOS_SR_CTERF_Msk (0x1UL << MDIOS_SR_CTERF_Pos) /*!< 0x00000004 */
23972#define MDIOS_SR_CTERF MDIOS_SR_CTERF_Msk /*!< MDIOS slave Clear the preamble error flag */
23973
23974/******************************************************************************/
23975/* */
23976/* USB_OTG */
23977/* */
23978/******************************************************************************/
23979/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
23980#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
23981#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
23982#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
23983#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
23984#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
23985#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
23986#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
23987#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
23988#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
23989#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
23990#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
23991#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
23992#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
23993#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
23994#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
23995#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
23996#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
23997#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
23998#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
23999#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
24000#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
24001#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
24002#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
24003#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
24004#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
24005#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
24006#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
24007#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
24008#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
24009#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
24010#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
24011#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
24012#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
24013#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
24014#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
24015#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
24016#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
24017#define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
24018#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
24019#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
24020#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
24021#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
24022#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
24023#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
24024#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
24025#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
24026#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
24027#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
24028#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
24029#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
24030#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
24031#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
24032#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
24033#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
24034
24035/******************** Bit definition forUSB_OTG_HCFG register ********************/
24036
24037#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
24038#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
24039#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
24040#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
24041#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
24042#define USB_OTG_HCFG_FSLSS_Pos (2U)
24043#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
24044#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
24045
24046/******************** Bit definition forUSB_OTG_DCFG register ********************/
24047
24048#define USB_OTG_DCFG_DSPD_Pos (0U)
24049#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
24050#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
24051#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
24052#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
24053#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
24054#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
24055#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
24056
24057#define USB_OTG_DCFG_DAD_Pos (4U)
24058#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
24059#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
24060#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
24061#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
24062#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
24063#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
24064#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
24065#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
24066#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
24067
24068#define USB_OTG_DCFG_PFIVL_Pos (11U)
24069#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
24070#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
24071#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
24072#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
24073
24074#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
24075#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
24076#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
24077#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
24078#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
24079
24080/******************** Bit definition forUSB_OTG_PCGCR register ********************/
24081#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
24082#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
24083#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
24084#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
24085#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
24086#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
24087#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
24088#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
24089#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
24090
24091/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
24092#define USB_OTG_GOTGINT_SEDET_Pos (2U)
24093#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
24094#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
24095#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
24096#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
24097#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
24098#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
24099#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
24100#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
24101#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
24102#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
24103#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
24104#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
24105#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
24106#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
24107#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
24108#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
24109#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
24110
24111/******************** Bit definition forUSB_OTG_DCTL register ********************/
24112#define USB_OTG_DCTL_RWUSIG_Pos (0U)
24113#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
24114#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
24115#define USB_OTG_DCTL_SDIS_Pos (1U)
24116#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
24117#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
24118#define USB_OTG_DCTL_GINSTS_Pos (2U)
24119#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
24120#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
24121#define USB_OTG_DCTL_GONSTS_Pos (3U)
24122#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
24123#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
24124
24125#define USB_OTG_DCTL_TCTL_Pos (4U)
24126#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
24127#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
24128#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
24129#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
24130#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
24131#define USB_OTG_DCTL_SGINAK_Pos (7U)
24132#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
24133#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
24134#define USB_OTG_DCTL_CGINAK_Pos (8U)
24135#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
24136#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
24137#define USB_OTG_DCTL_SGONAK_Pos (9U)
24138#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
24139#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
24140#define USB_OTG_DCTL_CGONAK_Pos (10U)
24141#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
24142#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
24143#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
24144#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
24145#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
24146
24147/******************** Bit definition forUSB_OTG_HFIR register ********************/
24148#define USB_OTG_HFIR_FRIVL_Pos (0U)
24149#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
24150#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
24151
24152/******************** Bit definition forUSB_OTG_HFNUM register ********************/
24153#define USB_OTG_HFNUM_FRNUM_Pos (0U)
24154#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
24155#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
24156#define USB_OTG_HFNUM_FTREM_Pos (16U)
24157#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
24158#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
24159
24160/******************** Bit definition forUSB_OTG_DSTS register ********************/
24161#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
24162#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
24163#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
24164
24165#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
24166#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
24167#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
24168#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
24169#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
24170#define USB_OTG_DSTS_EERR_Pos (3U)
24171#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
24172#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
24173#define USB_OTG_DSTS_FNSOF_Pos (8U)
24174#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
24175#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
24176
24177/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
24178#define USB_OTG_GAHBCFG_GINT_Pos (0U)
24179#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
24180#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
24181
24182#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
24183#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
24184#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
24185#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
24186#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
24187#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
24188#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
24189#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
24190#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
24191#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
24192#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
24193#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
24194#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
24195#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
24196#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
24197#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
24198#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
24199
24200/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
24201
24202#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
24203#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
24204#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
24205#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
24206#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
24207#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
24208#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
24209#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
24210#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
24211#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
24212#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
24213#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
24214#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
24215#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
24216#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
24217
24218#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
24219#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
24220#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
24221#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
24222#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
24223#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
24224#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
24225#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
24226#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
24227#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
24228#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
24229#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
24230#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
24231#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
24232#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
24233#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
24234#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
24235#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
24236#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
24237#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
24238#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
24239#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
24240#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
24241#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
24242#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
24243#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
24244#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
24245#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
24246#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
24247#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
24248#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
24249#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
24250#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
24251#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
24252#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
24253#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
24254#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
24255#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
24256#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
24257#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
24258#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
24259#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
24260#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
24261#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
24262#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
24263#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
24264
24265/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
24266#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
24267#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
24268#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
24269#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
24270#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
24271#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
24272#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
24273#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
24274#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
24275#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
24276#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
24277#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
24278#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
24279#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
24280#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
24281
24282#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
24283#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
24284#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
24285#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
24286#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
24287#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
24288#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
24289#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
24290#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
24291#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
24292#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
24293#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
24294#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
24295#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
24296
24297/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
24298#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
24299#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
24300#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
24301#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
24302#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
24303#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
24304#define USB_OTG_DIEPMSK_TOM_Pos (3U)
24305#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
24306#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
24307#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
24308#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
24309#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
24310#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
24311#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
24312#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
24313#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
24314#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
24315#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
24316#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
24317#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
24318#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
24319#define USB_OTG_DIEPMSK_BIM_Pos (9U)
24320#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
24321#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
24322
24323/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
24324#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
24325#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
24326#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
24327
24328#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
24329#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
24330#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
24331#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
24332#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
24333#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
24334#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
24335#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
24336#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
24337#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
24338#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
24339
24340#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
24341#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
24342#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
24343#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
24344#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
24345#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
24346#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
24347#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
24348#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
24349#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
24350#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
24351
24352/******************** Bit definition forUSB_OTG_HAINT register ********************/
24353#define USB_OTG_HAINT_HAINT_Pos (0U)
24354#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
24355#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
24356
24357/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
24358#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
24359#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
24360#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
24361#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
24362#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
24363#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
24364#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
24365#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
24366#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */
24367#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
24368#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
24369#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
24370#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
24371#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
24372#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
24373#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
24374#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
24375#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
24376#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
24377#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
24378#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
24379#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
24380#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
24381#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
24382#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
24383#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
24384#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
24385#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
24386#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
24387#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */
24388#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
24389#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
24390#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */
24391#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
24392#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
24393#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */
24394
24395/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
24396#define USB_OTG_GINTSTS_CMOD_Pos (0U)
24397#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
24398#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
24399#define USB_OTG_GINTSTS_MMIS_Pos (1U)
24400#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
24401#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
24402#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
24403#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
24404#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
24405#define USB_OTG_GINTSTS_SOF_Pos (3U)
24406#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
24407#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
24408#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
24409#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
24410#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
24411#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
24412#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
24413#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
24414#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
24415#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
24416#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
24417#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
24418#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
24419#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
24420#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
24421#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
24422#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
24423#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
24424#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
24425#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
24426#define USB_OTG_GINTSTS_USBRST_Pos (12U)
24427#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
24428#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
24429#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
24430#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
24431#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
24432#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
24433#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
24434#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
24435#define USB_OTG_GINTSTS_EOPF_Pos (15U)
24436#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
24437#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
24438#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
24439#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
24440#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
24441#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
24442#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
24443#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
24444#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
24445#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
24446#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
24447#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
24448#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
24449#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
24450#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
24451#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
24452#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
24453#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
24454#define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
24455#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
24456#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
24457#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
24458#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
24459#define USB_OTG_GINTSTS_HCINT_Pos (25U)
24460#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
24461#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
24462#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
24463#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
24464#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
24465#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
24466#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
24467#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
24468#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
24469#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
24470#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
24471#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
24472#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
24473#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
24474#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
24475#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
24476#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
24477#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
24478#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
24479#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
24480
24481/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
24482#define USB_OTG_GINTMSK_MMISM_Pos (1U)
24483#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
24484#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
24485#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
24486#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
24487#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
24488#define USB_OTG_GINTMSK_SOFM_Pos (3U)
24489#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
24490#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
24491#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
24492#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
24493#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
24494#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
24495#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
24496#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
24497#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
24498#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
24499#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
24500#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
24501#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
24502#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
24503#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
24504#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
24505#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
24506#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
24507#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
24508#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
24509#define USB_OTG_GINTMSK_USBRST_Pos (12U)
24510#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
24511#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
24512#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
24513#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
24514#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
24515#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
24516#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
24517#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
24518#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
24519#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
24520#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
24521#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
24522#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
24523#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
24524#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
24525#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
24526#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
24527#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
24528#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
24529#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
24530#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
24531#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
24532#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
24533#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
24534#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
24535#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
24536#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
24537#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
24538#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
24539#define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
24540#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
24541#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */
24542#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
24543#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
24544#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
24545#define USB_OTG_GINTMSK_HCIM_Pos (25U)
24546#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
24547#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
24548#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
24549#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
24550#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
24551#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
24552#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
24553#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
24554#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
24555#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
24556#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
24557#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
24558#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
24559#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
24560#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
24561#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
24562#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
24563#define USB_OTG_GINTMSK_WUIM_Pos (31U)
24564#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
24565#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
24566
24567/******************** Bit definition forUSB_OTG_DAINT register ********************/
24568#define USB_OTG_DAINT_IEPINT_Pos (0U)
24569#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
24570#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
24571#define USB_OTG_DAINT_OEPINT_Pos (16U)
24572#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
24573#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
24574
24575/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
24576#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
24577#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
24578#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
24579
24580/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
24581#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
24582#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
24583#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
24584#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
24585#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
24586#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
24587#define USB_OTG_GRXSTSP_DPID_Pos (15U)
24588#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
24589#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
24590#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
24591#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
24592#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
24593
24594/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
24595#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
24596#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
24597#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
24598#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
24599#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
24600#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
24601
24602/******************** Bit definition for OTG register ********************/
24603
24604#define USB_OTG_CHNUM_Pos (0U)
24605#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
24606#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
24607#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
24608#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
24609#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
24610#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
24611#define USB_OTG_BCNT_Pos (4U)
24612#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
24613#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
24614
24615#define USB_OTG_DPID_Pos (15U)
24616#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
24617#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
24618#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
24619#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
24620
24621#define USB_OTG_PKTSTS_Pos (17U)
24622#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
24623#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
24624#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
24625#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
24626#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
24627#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
24628
24629#define USB_OTG_EPNUM_Pos (0U)
24630#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
24631#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
24632#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
24633#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
24634#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
24635#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
24636
24637#define USB_OTG_FRMNUM_Pos (21U)
24638#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
24639#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
24640#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
24641#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
24642#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
24643#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
24644
24645/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
24646#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
24647#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
24648#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
24649
24650/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
24651#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
24652#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
24653#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
24654
24655/******************** Bit definition for OTG register ********************/
24656#define USB_OTG_NPTXFSA_Pos (0U)
24657#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
24658#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
24659#define USB_OTG_NPTXFD_Pos (16U)
24660#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
24661#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
24662#define USB_OTG_TX0FSA_Pos (0U)
24663#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
24664#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
24665#define USB_OTG_TX0FD_Pos (16U)
24666#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
24667#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
24668
24669/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
24670#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
24671#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
24672#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
24673
24674/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
24675#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
24676#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
24677#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
24678
24679#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
24680#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
24681#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
24682#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
24683#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
24684#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
24685#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
24686#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
24687#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
24688#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
24689#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
24690
24691#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
24692#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
24693#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
24694#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
24695#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
24696#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
24697#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
24698#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
24699#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
24700#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
24701
24702/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
24703#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
24704#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
24705#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
24706#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
24707#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
24708#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
24709
24710#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
24711#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
24712#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
24713#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
24714#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
24715#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
24716#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
24717#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
24718#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
24719#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
24720#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
24721#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
24722#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
24723#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
24724#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
24725
24726#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
24727#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
24728#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
24729#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
24730#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
24731#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
24732#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
24733#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
24734#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
24735#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
24736#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
24737#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
24738#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
24739#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
24740#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
24741
24742/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
24743#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
24744#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
24745#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
24746
24747/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
24748#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
24749#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
24750#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
24751#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
24752#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
24753#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
24754
24755/******************** Bit definition forUSB_OTG_GCCFG register ********************/
24756#define USB_OTG_GCCFG_DCDET_Pos (0U)
24757#define USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
24758#define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */
24759#define USB_OTG_GCCFG_PDET_Pos (1U)
24760#define USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
24761#define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */
24762#define USB_OTG_GCCFG_SDET_Pos (2U)
24763#define USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
24764#define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */
24765#define USB_OTG_GCCFG_PS2DET_Pos (3U)
24766#define USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
24767#define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
24768#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
24769#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
24770#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
24771#define USB_OTG_GCCFG_BCDEN_Pos (17U)
24772#define USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
24773#define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */
24774#define USB_OTG_GCCFG_DCDEN_Pos (18U)
24775#define USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
24776#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/
24777#define USB_OTG_GCCFG_PDEN_Pos (19U)
24778#define USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
24779#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/
24780#define USB_OTG_GCCFG_SDEN_Pos (20U)
24781#define USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
24782#define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */
24783#define USB_OTG_GCCFG_VBDEN_Pos (21U)
24784#define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
24785#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Secondary detection (SD) mode enable */
24786
24787/******************** Bit definition forUSB_OTG_GPWRDN) register ********************/
24788#define USB_OTG_GPWRDN_ADPMEN_Pos (0U)
24789#define USB_OTG_GPWRDN_ADPMEN_Msk (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
24790#define USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk /*!< ADP module enable */
24791#define USB_OTG_GPWRDN_ADPIF_Pos (23U)
24792#define USB_OTG_GPWRDN_ADPIF_Msk (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
24793#define USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk /*!< ADP Interrupt flag */
24794
24795/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
24796#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
24797#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
24798#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
24799#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
24800#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
24801#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
24802
24803/******************** Bit definition forUSB_OTG_CID register ********************/
24804#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
24805#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
24806#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
24807
24808/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
24809#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
24810#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
24811#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
24812#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
24813#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
24814#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
24815#define USB_OTG_GLPMCFG_BESL_Pos (2U)
24816#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
24817#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
24818#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
24819#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
24820#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
24821#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
24822#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
24823#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
24824#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
24825#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
24826#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
24827#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
24828#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
24829#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
24830#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
24831#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
24832#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
24833#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
24834#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
24835#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
24836#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
24837#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
24838#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
24839#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
24840#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
24841#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
24842#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
24843#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
24844#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
24845#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
24846#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
24847#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
24848#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
24849#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
24850#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
24851#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
24852#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
24853#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
24854
24855/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
24856#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
24857#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
24858#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
24859#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
24860#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
24861#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
24862#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
24863#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
24864#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
24865#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
24866#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
24867#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
24868#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
24869#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
24870#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
24871#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
24872#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
24873#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
24874#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
24875#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
24876#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
24877#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
24878#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
24879#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
24880#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
24881#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
24882#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
24883
24884/******************** Bit definition forUSB_OTG_HPRT register ********************/
24885#define USB_OTG_HPRT_PCSTS_Pos (0U)
24886#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
24887#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
24888#define USB_OTG_HPRT_PCDET_Pos (1U)
24889#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
24890#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
24891#define USB_OTG_HPRT_PENA_Pos (2U)
24892#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
24893#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
24894#define USB_OTG_HPRT_PENCHNG_Pos (3U)
24895#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
24896#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
24897#define USB_OTG_HPRT_POCA_Pos (4U)
24898#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
24899#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
24900#define USB_OTG_HPRT_POCCHNG_Pos (5U)
24901#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
24902#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
24903#define USB_OTG_HPRT_PRES_Pos (6U)
24904#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
24905#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
24906#define USB_OTG_HPRT_PSUSP_Pos (7U)
24907#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
24908#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
24909#define USB_OTG_HPRT_PRST_Pos (8U)
24910#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
24911#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
24912
24913#define USB_OTG_HPRT_PLSTS_Pos (10U)
24914#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
24915#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
24916#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
24917#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
24918#define USB_OTG_HPRT_PPWR_Pos (12U)
24919#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
24920#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
24921
24922#define USB_OTG_HPRT_PTCTL_Pos (13U)
24923#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
24924#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
24925#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
24926#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
24927#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
24928#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
24929
24930#define USB_OTG_HPRT_PSPD_Pos (17U)
24931#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
24932#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
24933#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
24934#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
24935
24936/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
24937#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
24938#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
24939#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
24940#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
24941#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
24942#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
24943#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
24944#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
24945#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
24946#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
24947#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
24948#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
24949#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
24950#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
24951#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
24952#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
24953#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
24954#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
24955#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
24956#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
24957#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
24958#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
24959#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
24960#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
24961#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
24962#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
24963#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
24964#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
24965#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
24966#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
24967#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
24968#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
24969#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
24970
24971/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
24972#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
24973#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
24974#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
24975#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
24976#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
24977#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
24978
24979/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
24980#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
24981#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
24982#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
24983#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
24984#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
24985#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
24986#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
24987#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
24988#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
24989#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
24990#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
24991#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
24992
24993#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
24994#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
24995#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
24996#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
24997#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
24998#define USB_OTG_DIEPCTL_STALL_Pos (21U)
24999#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
25000#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
25001
25002#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
25003#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
25004#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
25005#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
25006#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
25007#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
25008#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
25009#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
25010#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
25011#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
25012#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
25013#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
25014#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
25015#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
25016#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
25017#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
25018#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
25019#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
25020#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
25021#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
25022#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
25023#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
25024#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
25025#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
25026#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
25027
25028/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
25029#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
25030#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
25031#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
25032
25033#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
25034#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
25035#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
25036#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
25037#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
25038#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
25039#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
25040#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
25041#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
25042#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
25043#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
25044#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
25045#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
25046
25047#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
25048#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
25049#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
25050#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
25051#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
25052
25053#define USB_OTG_HCCHAR_MC_Pos (20U)
25054#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
25055#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
25056#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
25057#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
25058
25059#define USB_OTG_HCCHAR_DAD_Pos (22U)
25060#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
25061#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
25062#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
25063#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
25064#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
25065#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
25066#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
25067#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
25068#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
25069#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
25070#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
25071#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
25072#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
25073#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
25074#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
25075#define USB_OTG_HCCHAR_CHENA_Pos (31U)
25076#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
25077#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
25078
25079/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
25080
25081#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
25082#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
25083#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
25084#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
25085#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
25086#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
25087#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
25088#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
25089#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
25090#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
25091
25092#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
25093#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
25094#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
25095#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
25096#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
25097#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
25098#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
25099#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
25100#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
25101#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
25102
25103#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
25104#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
25105#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
25106#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
25107#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
25108#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
25109#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
25110#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
25111#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
25112#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
25113#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
25114
25115/******************** Bit definition forUSB_OTG_HCINT register ********************/
25116#define USB_OTG_HCINT_XFRC_Pos (0U)
25117#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
25118#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
25119#define USB_OTG_HCINT_CHH_Pos (1U)
25120#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
25121#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
25122#define USB_OTG_HCINT_AHBERR_Pos (2U)
25123#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
25124#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
25125#define USB_OTG_HCINT_STALL_Pos (3U)
25126#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
25127#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
25128#define USB_OTG_HCINT_NAK_Pos (4U)
25129#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
25130#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
25131#define USB_OTG_HCINT_ACK_Pos (5U)
25132#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
25133#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
25134#define USB_OTG_HCINT_NYET_Pos (6U)
25135#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
25136#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
25137#define USB_OTG_HCINT_TXERR_Pos (7U)
25138#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
25139#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
25140#define USB_OTG_HCINT_BBERR_Pos (8U)
25141#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
25142#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
25143#define USB_OTG_HCINT_FRMOR_Pos (9U)
25144#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
25145#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
25146#define USB_OTG_HCINT_DTERR_Pos (10U)
25147#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
25148#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
25149
25150/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
25151#define USB_OTG_DIEPINT_XFRC_Pos (0U)
25152#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
25153#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
25154#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
25155#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
25156#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
25157#define USB_OTG_DIEPINT_AHBERR_Pos (2U)
25158#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
25159#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */
25160#define USB_OTG_DIEPINT_TOC_Pos (3U)
25161#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
25162#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
25163#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
25164#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
25165#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
25166#define USB_OTG_DIEPINT_INEPNM_Pos (5U)
25167#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */
25168#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */
25169#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
25170#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
25171#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
25172#define USB_OTG_DIEPINT_TXFE_Pos (7U)
25173#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
25174#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
25175#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
25176#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
25177#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
25178#define USB_OTG_DIEPINT_BNA_Pos (9U)
25179#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
25180#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
25181#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
25182#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
25183#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
25184#define USB_OTG_DIEPINT_BERR_Pos (12U)
25185#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
25186#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
25187#define USB_OTG_DIEPINT_NAK_Pos (13U)
25188#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
25189#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
25190
25191/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
25192#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
25193#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
25194#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
25195#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
25196#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
25197#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
25198#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
25199#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
25200#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
25201#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
25202#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
25203#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
25204#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
25205#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
25206#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
25207#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
25208#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
25209#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
25210#define USB_OTG_HCINTMSK_NYET_Pos (6U)
25211#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
25212#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
25213#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
25214#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
25215#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
25216#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
25217#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
25218#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
25219#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
25220#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
25221#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
25222#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
25223#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
25224#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
25225
25226/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
25227
25228#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
25229#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
25230#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
25231#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
25232#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
25233#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
25234#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
25235#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
25236#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
25237/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
25238#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
25239#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
25240#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
25241#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
25242#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
25243#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
25244#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
25245#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
25246#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
25247#define USB_OTG_HCTSIZ_DPID_Pos (29U)
25248#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
25249#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
25250#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
25251#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
25252
25253/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
25254#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
25255#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
25256#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
25257
25258/******************** Bit definition forUSB_OTG_HCDMA register ********************/
25259#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
25260#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
25261#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
25262
25263/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
25264#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
25265#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
25266#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
25267
25268/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
25269#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
25270#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
25271#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
25272#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
25273#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
25274#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
25275
25276/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
25277
25278#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
25279#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
25280#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
25281#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
25282#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
25283#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
25284#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
25285#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
25286#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
25287#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
25288#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
25289#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
25290#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
25291#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
25292#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
25293#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
25294#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
25295#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
25296#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
25297#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
25298#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
25299#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
25300#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
25301#define USB_OTG_DOEPCTL_STALL_Pos (21U)
25302#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
25303#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
25304#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
25305#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
25306#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
25307#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
25308#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
25309#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
25310#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
25311#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
25312#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
25313#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
25314#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
25315#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
25316
25317/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
25318#define USB_OTG_DOEPINT_XFRC_Pos (0U)
25319#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
25320#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
25321#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
25322#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
25323#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
25324#define USB_OTG_DOEPINT_AHBERR_Pos (2U)
25325#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
25326#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an OUT transaction */
25327#define USB_OTG_DOEPINT_STUP_Pos (3U)
25328#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
25329#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
25330#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
25331#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
25332#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
25333#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
25334#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
25335#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< OUT Status Phase Received interrupt */
25336#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
25337#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
25338#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
25339#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
25340#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
25341#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */
25342#define USB_OTG_DOEPINT_BERR_Pos (12U)
25343#define USB_OTG_DOEPINT_BERR_Msk (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */
25344#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */
25345#define USB_OTG_DOEPINT_NAK_Pos (13U)
25346#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
25347#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK Packet is transmitted by the device */
25348#define USB_OTG_DOEPINT_NYET_Pos (14U)
25349#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
25350#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
25351#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
25352#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
25353#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup Packet Received */
25354
25355/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
25356
25357#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
25358#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
25359#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
25360#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
25361#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
25362#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
25363
25364#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
25365#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
25366#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
25367#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
25368#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
25369
25370/******************** Bit definition for PCGCCTL register ********************/
25371#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
25372#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
25373#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
25374#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
25375#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
25376#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
25377#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
25378#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
25379#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
25380
25381/**
25382 * @}
25383 */
25384
25385/**
25386 * @}
25387 */
25388
25389/** @addtogroup Exported_macros
25390 * @{
25391 */
25392
25393/******************************* ADC Instances ********************************/
25394#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
25395 ((INSTANCE) == ADC2) || \
25396 ((INSTANCE) == ADC3))
25397
25398#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
25399
25400#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\
25401 ((INSTANCE) == ADC3_COMMON))
25402
25403/******************************** COMP Instances ******************************/
25404#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
25405 ((INSTANCE) == COMP2))
25406
25407#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
25408/******************** COMP Instances with window mode capability **************/
25409#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
25410
25411
25412/******************************* CRC Instances ********************************/
25413#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
25414
25415/******************************* DAC Instances ********************************/
25416#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
25417/******************************* DCMI Instances *******************************/
25418#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
25419
25420/******************************* DELAYBLOCK Instances *******************************/
25421#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1) || \
25422 ((INSTANCE) == DLYB_SDMMC2) || \
25423 ((INSTANCE) == DLYB_QUADSPI))
25424/****************************** DFSDM Instances *******************************/
25425#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
25426 ((INSTANCE) == DFSDM1_Filter1) || \
25427 ((INSTANCE) == DFSDM1_Filter2) || \
25428 ((INSTANCE) == DFSDM1_Filter3))
25429
25430#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
25431 ((INSTANCE) == DFSDM1_Channel1) || \
25432 ((INSTANCE) == DFSDM1_Channel2) || \
25433 ((INSTANCE) == DFSDM1_Channel3) || \
25434 ((INSTANCE) == DFSDM1_Channel4) || \
25435 ((INSTANCE) == DFSDM1_Channel5) || \
25436 ((INSTANCE) == DFSDM1_Channel6) || \
25437 ((INSTANCE) == DFSDM1_Channel7))
25438/****************************** RAMECC Instances ******************************/
25439#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1) || \
25440 ((INSTANCE) == RAMECC1_Monitor2) || \
25441 ((INSTANCE) == RAMECC1_Monitor3) || \
25442 ((INSTANCE) == RAMECC1_Monitor4) || \
25443 ((INSTANCE) == RAMECC1_Monitor5) || \
25444 ((INSTANCE) == RAMECC2_Monitor1) || \
25445 ((INSTANCE) == RAMECC2_Monitor2) || \
25446 ((INSTANCE) == RAMECC2_Monitor3) || \
25447 ((INSTANCE) == RAMECC2_Monitor4) || \
25448 ((INSTANCE) == RAMECC2_Monitor5) || \
25449 ((INSTANCE) == RAMECC3_Monitor1) || \
25450 ((INSTANCE) == RAMECC3_Monitor2))
25451
25452/******************************** DMA Instances *******************************/
25453#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
25454 ((INSTANCE) == DMA1_Stream1) || \
25455 ((INSTANCE) == DMA1_Stream2) || \
25456 ((INSTANCE) == DMA1_Stream3) || \
25457 ((INSTANCE) == DMA1_Stream4) || \
25458 ((INSTANCE) == DMA1_Stream5) || \
25459 ((INSTANCE) == DMA1_Stream6) || \
25460 ((INSTANCE) == DMA1_Stream7) || \
25461 ((INSTANCE) == DMA2_Stream0) || \
25462 ((INSTANCE) == DMA2_Stream1) || \
25463 ((INSTANCE) == DMA2_Stream2) || \
25464 ((INSTANCE) == DMA2_Stream3) || \
25465 ((INSTANCE) == DMA2_Stream4) || \
25466 ((INSTANCE) == DMA2_Stream5) || \
25467 ((INSTANCE) == DMA2_Stream6) || \
25468 ((INSTANCE) == DMA2_Stream7) || \
25469 ((INSTANCE) == BDMA_Channel0) || \
25470 ((INSTANCE) == BDMA_Channel1) || \
25471 ((INSTANCE) == BDMA_Channel2) || \
25472 ((INSTANCE) == BDMA_Channel3) || \
25473 ((INSTANCE) == BDMA_Channel4) || \
25474 ((INSTANCE) == BDMA_Channel5) || \
25475 ((INSTANCE) == BDMA_Channel6) || \
25476 ((INSTANCE) == BDMA_Channel7))
25477
25478/****************************** BDMA CHANNEL Instances ***************************/
25479#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
25480 ((INSTANCE) == BDMA_Channel1) || \
25481 ((INSTANCE) == BDMA_Channel2) || \
25482 ((INSTANCE) == BDMA_Channel3) || \
25483 ((INSTANCE) == BDMA_Channel4) || \
25484 ((INSTANCE) == BDMA_Channel5) || \
25485 ((INSTANCE) == BDMA_Channel6) || \
25486 ((INSTANCE) == BDMA_Channel7))
25487
25488/****************************** DMA DMAMUX ALL Instances ***************************/
25489#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
25490 ((INSTANCE) == DMA1_Stream1) || \
25491 ((INSTANCE) == DMA1_Stream2) || \
25492 ((INSTANCE) == DMA1_Stream3) || \
25493 ((INSTANCE) == DMA1_Stream4) || \
25494 ((INSTANCE) == DMA1_Stream5) || \
25495 ((INSTANCE) == DMA1_Stream6) || \
25496 ((INSTANCE) == DMA1_Stream7) || \
25497 ((INSTANCE) == DMA2_Stream0) || \
25498 ((INSTANCE) == DMA2_Stream1) || \
25499 ((INSTANCE) == DMA2_Stream2) || \
25500 ((INSTANCE) == DMA2_Stream3) || \
25501 ((INSTANCE) == DMA2_Stream4) || \
25502 ((INSTANCE) == DMA2_Stream5) || \
25503 ((INSTANCE) == DMA2_Stream6) || \
25504 ((INSTANCE) == DMA2_Stream7) || \
25505 ((INSTANCE) == BDMA_Channel0) || \
25506 ((INSTANCE) == BDMA_Channel1) || \
25507 ((INSTANCE) == BDMA_Channel2) || \
25508 ((INSTANCE) == BDMA_Channel3) || \
25509 ((INSTANCE) == BDMA_Channel4) || \
25510 ((INSTANCE) == BDMA_Channel5) || \
25511 ((INSTANCE) == BDMA_Channel6) || \
25512 ((INSTANCE) == BDMA_Channel7))
25513
25514/****************************** BDMA DMAMUX Instances ***************************/
25515#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
25516 ((INSTANCE) == BDMA_Channel1) || \
25517 ((INSTANCE) == BDMA_Channel2) || \
25518 ((INSTANCE) == BDMA_Channel3) || \
25519 ((INSTANCE) == BDMA_Channel4) || \
25520 ((INSTANCE) == BDMA_Channel5) || \
25521 ((INSTANCE) == BDMA_Channel6) || \
25522 ((INSTANCE) == BDMA_Channel7))
25523
25524/****************************** DMA STREAM Instances ***************************/
25525#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
25526 ((INSTANCE) == DMA1_Stream1) || \
25527 ((INSTANCE) == DMA1_Stream2) || \
25528 ((INSTANCE) == DMA1_Stream3) || \
25529 ((INSTANCE) == DMA1_Stream4) || \
25530 ((INSTANCE) == DMA1_Stream5) || \
25531 ((INSTANCE) == DMA1_Stream6) || \
25532 ((INSTANCE) == DMA1_Stream7) || \
25533 ((INSTANCE) == DMA2_Stream0) || \
25534 ((INSTANCE) == DMA2_Stream1) || \
25535 ((INSTANCE) == DMA2_Stream2) || \
25536 ((INSTANCE) == DMA2_Stream3) || \
25537 ((INSTANCE) == DMA2_Stream4) || \
25538 ((INSTANCE) == DMA2_Stream5) || \
25539 ((INSTANCE) == DMA2_Stream6) || \
25540 ((INSTANCE) == DMA2_Stream7))
25541
25542/****************************** DMA DMAMUX Instances ***************************/
25543#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
25544 ((INSTANCE) == DMA1_Stream1) || \
25545 ((INSTANCE) == DMA1_Stream2) || \
25546 ((INSTANCE) == DMA1_Stream3) || \
25547 ((INSTANCE) == DMA1_Stream4) || \
25548 ((INSTANCE) == DMA1_Stream5) || \
25549 ((INSTANCE) == DMA1_Stream6) || \
25550 ((INSTANCE) == DMA1_Stream7) || \
25551 ((INSTANCE) == DMA2_Stream0) || \
25552 ((INSTANCE) == DMA2_Stream1) || \
25553 ((INSTANCE) == DMA2_Stream2) || \
25554 ((INSTANCE) == DMA2_Stream3) || \
25555 ((INSTANCE) == DMA2_Stream4) || \
25556 ((INSTANCE) == DMA2_Stream5) || \
25557 ((INSTANCE) == DMA2_Stream6) || \
25558 ((INSTANCE) == DMA2_Stream7))
25559
25560/******************************** DMA Request Generator Instances **************/
25561#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
25562 ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
25563 ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
25564 ((INSTANCE) == DMAMUX1_RequestGenerator3) || \
25565 ((INSTANCE) == DMAMUX1_RequestGenerator4) || \
25566 ((INSTANCE) == DMAMUX1_RequestGenerator5) || \
25567 ((INSTANCE) == DMAMUX1_RequestGenerator6) || \
25568 ((INSTANCE) == DMAMUX1_RequestGenerator7) || \
25569 ((INSTANCE) == DMAMUX2_RequestGenerator0) || \
25570 ((INSTANCE) == DMAMUX2_RequestGenerator1) || \
25571 ((INSTANCE) == DMAMUX2_RequestGenerator2) || \
25572 ((INSTANCE) == DMAMUX2_RequestGenerator3) || \
25573 ((INSTANCE) == DMAMUX2_RequestGenerator4) || \
25574 ((INSTANCE) == DMAMUX2_RequestGenerator5) || \
25575 ((INSTANCE) == DMAMUX2_RequestGenerator6) || \
25576 ((INSTANCE) == DMAMUX2_RequestGenerator7))
25577
25578/******************************* DMA2D Instances *******************************/
25579#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
25580
25581/******************************** MDMA Request Generator Instances **************/
25582#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0) || \
25583 ((INSTANCE) == MDMA_Channel1) || \
25584 ((INSTANCE) == MDMA_Channel2) || \
25585 ((INSTANCE) == MDMA_Channel3) || \
25586 ((INSTANCE) == MDMA_Channel4) || \
25587 ((INSTANCE) == MDMA_Channel5) || \
25588 ((INSTANCE) == MDMA_Channel6) || \
25589 ((INSTANCE) == MDMA_Channel7) || \
25590 ((INSTANCE) == MDMA_Channel8) || \
25591 ((INSTANCE) == MDMA_Channel9) || \
25592 ((INSTANCE) == MDMA_Channel10) || \
25593 ((INSTANCE) == MDMA_Channel11) || \
25594 ((INSTANCE) == MDMA_Channel12) || \
25595 ((INSTANCE) == MDMA_Channel13) || \
25596 ((INSTANCE) == MDMA_Channel14) || \
25597 ((INSTANCE) == MDMA_Channel15))
25598
25599/******************************* QUADSPI Instances *******************************/
25600#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
25601
25602/******************************* FDCAN Instances ******************************/
25603#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \
25604 ((__INSTANCE__) == FDCAN2))
25605
25606#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)
25607
25608/******************************* GPIO Instances *******************************/
25609#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
25610 ((INSTANCE) == GPIOB) || \
25611 ((INSTANCE) == GPIOC) || \
25612 ((INSTANCE) == GPIOD) || \
25613 ((INSTANCE) == GPIOE) || \
25614 ((INSTANCE) == GPIOF) || \
25615 ((INSTANCE) == GPIOG) || \
25616 ((INSTANCE) == GPIOH) || \
25617 ((INSTANCE) == GPIOI) || \
25618 ((INSTANCE) == GPIOJ) || \
25619 ((INSTANCE) == GPIOK))
25620
25621/******************************* GPIO AF Instances ****************************/
25622#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
25623
25624/**************************** GPIO Lock Instances *****************************/
25625/* On H7, all GPIO Bank support the Lock mechanism */
25626#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
25627
25628/******************************** HSEM Instances *******************************/
25629#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
25630#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */
25631#define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
25632#define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
25633
25634#define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/
25635#define HSEM_SEMID_MAX (31U) /* HSEM ID Max */
25636
25637#define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */
25638#define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */
25639
25640#define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */
25641#define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */
25642
25643/******************************** I2C Instances *******************************/
25644#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
25645 ((INSTANCE) == I2C2) || \
25646 ((INSTANCE) == I2C3) || \
25647 ((INSTANCE) == I2C4))
25648/************** I2C Instances : wakeup capability from stop modes *************/
25649#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
25650
25651/****************************** SMBUS Instances *******************************/
25652#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
25653 ((INSTANCE) == I2C2) || \
25654 ((INSTANCE) == I2C3) || \
25655 ((INSTANCE) == I2C4))
25656/******************************** I2S Instances *******************************/
25657#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
25658 ((INSTANCE) == SPI2) || \
25659 ((INSTANCE) == SPI3))
25660
25661/****************************** LTDC Instances ********************************/
25662#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
25663
25664/******************************* RNG Instances ********************************/
25665#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
25666
25667/****************************** RTC Instances *********************************/
25668#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
25669
25670/****************************** SDMMC Instances *********************************/
25671#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \
25672 ((_INSTANCE_) == SDMMC2))
25673
25674/******************************** SMBUS Instances *****************************/
25675#define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
25676
25677/******************************** SPI Instances *******************************/
25678#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
25679 ((INSTANCE) == SPI2) || \
25680 ((INSTANCE) == SPI3) || \
25681 ((INSTANCE) == SPI4) || \
25682 ((INSTANCE) == SPI5) || \
25683 ((INSTANCE) == SPI6))
25684
25685#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
25686 ((INSTANCE) == SPI2) || \
25687 ((INSTANCE) == SPI3))
25688
25689/******************************** SWPMI Instances *****************************/
25690#define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
25691
25692/****************** LPTIM Instances : All supported instances *****************/
25693#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
25694 ((INSTANCE) == LPTIM2) || \
25695 ((INSTANCE) == LPTIM3) || \
25696 ((INSTANCE) == LPTIM4) || \
25697 ((INSTANCE) == LPTIM5))
25698
25699/****************** LPTIM Instances : supporting encoder interface **************/
25700#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
25701 ((INSTANCE) == LPTIM2))
25702
25703/****************** TIM Instances : All supported instances *******************/
25704#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25705 ((INSTANCE) == TIM2) || \
25706 ((INSTANCE) == TIM3) || \
25707 ((INSTANCE) == TIM4) || \
25708 ((INSTANCE) == TIM5) || \
25709 ((INSTANCE) == TIM6) || \
25710 ((INSTANCE) == TIM7) || \
25711 ((INSTANCE) == TIM8) || \
25712 ((INSTANCE) == TIM12) || \
25713 ((INSTANCE) == TIM13) || \
25714 ((INSTANCE) == TIM14) || \
25715 ((INSTANCE) == TIM15) || \
25716 ((INSTANCE) == TIM16) || \
25717 ((INSTANCE) == TIM17))
25718
25719/************* TIM Instances : at least 1 capture/compare channel *************/
25720#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25721 ((INSTANCE) == TIM2) || \
25722 ((INSTANCE) == TIM3) || \
25723 ((INSTANCE) == TIM4) || \
25724 ((INSTANCE) == TIM5) || \
25725 ((INSTANCE) == TIM8) || \
25726 ((INSTANCE) == TIM12) || \
25727 ((INSTANCE) == TIM13) || \
25728 ((INSTANCE) == TIM14) || \
25729 ((INSTANCE) == TIM15) || \
25730 ((INSTANCE) == TIM16) || \
25731 ((INSTANCE) == TIM17))
25732
25733/************ TIM Instances : at least 2 capture/compare channels *************/
25734#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25735 ((INSTANCE) == TIM2) || \
25736 ((INSTANCE) == TIM3) || \
25737 ((INSTANCE) == TIM4) || \
25738 ((INSTANCE) == TIM5) || \
25739 ((INSTANCE) == TIM8) || \
25740 ((INSTANCE) == TIM12) || \
25741 ((INSTANCE) == TIM15))
25742
25743/************ TIM Instances : at least 3 capture/compare channels *************/
25744#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25745 ((INSTANCE) == TIM2) || \
25746 ((INSTANCE) == TIM3) || \
25747 ((INSTANCE) == TIM4) || \
25748 ((INSTANCE) == TIM5) || \
25749 ((INSTANCE) == TIM8))
25750
25751/************ TIM Instances : at least 4 capture/compare channels *************/
25752#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25753 ((INSTANCE) == TIM2) || \
25754 ((INSTANCE) == TIM3) || \
25755 ((INSTANCE) == TIM4) || \
25756 ((INSTANCE) == TIM5) || \
25757 ((INSTANCE) == TIM8))
25758
25759/************ TIM Instances : at least 5 capture/compare channels *************/
25760#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25761 ((INSTANCE) == TIM8))
25762/************ TIM Instances : at least 6 capture/compare channels *************/
25763#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25764 ((INSTANCE) == TIM8))
25765
25766/******************** TIM Instances : Advanced-control timers *****************/
25767#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
25768 ((__INSTANCE__) == TIM8))
25769
25770/******************** TIM Instances : Advanced-control timers *****************/
25771
25772/******************* TIM Instances : Timer input XOR function *****************/
25773#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25774 ((INSTANCE) == TIM2) || \
25775 ((INSTANCE) == TIM3) || \
25776 ((INSTANCE) == TIM4) || \
25777 ((INSTANCE) == TIM5) || \
25778 ((INSTANCE) == TIM8) || \
25779 ((INSTANCE) == TIM15))
25780
25781/****************** TIM Instances : DMA requests generation (UDE) *************/
25782#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25783 ((INSTANCE) == TIM2) || \
25784 ((INSTANCE) == TIM3) || \
25785 ((INSTANCE) == TIM4) || \
25786 ((INSTANCE) == TIM5) || \
25787 ((INSTANCE) == TIM6) || \
25788 ((INSTANCE) == TIM7) || \
25789 ((INSTANCE) == TIM8) || \
25790 ((INSTANCE) == TIM15) || \
25791 ((INSTANCE) == TIM16) || \
25792 ((INSTANCE) == TIM17))
25793
25794/************ TIM Instances : DMA requests generation (CCxDE) *****************/
25795#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25796 ((INSTANCE) == TIM2) || \
25797 ((INSTANCE) == TIM3) || \
25798 ((INSTANCE) == TIM4) || \
25799 ((INSTANCE) == TIM5) || \
25800 ((INSTANCE) == TIM8) || \
25801 ((INSTANCE) == TIM15) || \
25802 ((INSTANCE) == TIM16) || \
25803 ((INSTANCE) == TIM17))
25804
25805/************ TIM Instances : DMA requests generation (COMDE) *****************/
25806#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25807 ((INSTANCE) == TIM2) || \
25808 ((INSTANCE) == TIM3) || \
25809 ((INSTANCE) == TIM4) || \
25810 ((INSTANCE) == TIM5) || \
25811 ((INSTANCE) == TIM8) || \
25812 ((INSTANCE) == TIM15))
25813
25814/******************** TIM Instances : DMA burst feature ***********************/
25815#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25816 ((INSTANCE) == TIM2) || \
25817 ((INSTANCE) == TIM3) || \
25818 ((INSTANCE) == TIM4) || \
25819 ((INSTANCE) == TIM5) || \
25820 ((INSTANCE) == TIM8))
25821
25822/*************** TIM Instances : external trigger reamp input available *******/
25823#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25824 ((INSTANCE) == TIM2) || \
25825 ((INSTANCE) == TIM3) || \
25826 ((INSTANCE) == TIM4) || \
25827 ((INSTANCE) == TIM5) || \
25828 ((INSTANCE) == TIM8))
25829
25830/****************** TIM Instances : remapping capability **********************/
25831#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25832 ((INSTANCE) == TIM2) || \
25833 ((INSTANCE) == TIM3) || \
25834 ((INSTANCE) == TIM5) || \
25835 ((INSTANCE) == TIM8) || \
25836 ((INSTANCE) == TIM16) || \
25837 ((INSTANCE) == TIM17))
25838
25839/*************** TIM Instances : external trigger reamp input available *******/
25840#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25841 ((INSTANCE) == TIM2) || \
25842 ((INSTANCE) == TIM3) || \
25843 ((INSTANCE) == TIM5) || \
25844 ((INSTANCE) == TIM8))
25845
25846/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
25847#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25848 ((INSTANCE) == TIM2) || \
25849 ((INSTANCE) == TIM3) || \
25850 ((INSTANCE) == TIM4) || \
25851 ((INSTANCE) == TIM5) || \
25852 ((INSTANCE) == TIM6) || \
25853 ((INSTANCE) == TIM7) || \
25854 ((INSTANCE) == TIM8) || \
25855 ((INSTANCE) == TIM15))
25856
25857/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
25858#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25859 ((INSTANCE) == TIM2) || \
25860 ((INSTANCE) == TIM3) || \
25861 ((INSTANCE) == TIM4) || \
25862 ((INSTANCE) == TIM5) || \
25863 ((INSTANCE) == TIM8) || \
25864 ((INSTANCE) == TIM12))
25865
25866/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
25867#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25868 ((INSTANCE) == TIM8))
25869
25870/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/
25871#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25872 ((INSTANCE) == TIM2) || \
25873 ((INSTANCE) == TIM3) || \
25874 ((INSTANCE) == TIM4) || \
25875 ((INSTANCE) == TIM5) || \
25876 ((INSTANCE) == TIM8) || \
25877 ((INSTANCE) == TIM15) || \
25878 ((INSTANCE) == TIM16) || \
25879 ((INSTANCE) == TIM17))
25880
25881/****************** TIM Instances : supporting commutation event *************/
25882#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25883 ((INSTANCE) == TIM8) || \
25884 ((INSTANCE) == TIM15) || \
25885 ((INSTANCE) == TIM16) || \
25886 ((INSTANCE) == TIM17))
25887
25888/****************** TIM Instances : supporting encoder interface **************/
25889#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
25890 ((__INSTANCE__) == TIM2) || \
25891 ((__INSTANCE__) == TIM3) || \
25892 ((__INSTANCE__) == TIM4) || \
25893 ((__INSTANCE__) == TIM5) || \
25894 ((__INSTANCE__) == TIM8))
25895
25896/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/
25897#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25898 ((INSTANCE) == TIM8))
25899/******************* TIM Instances : output(s) available **********************/
25900#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
25901 ((((INSTANCE) == TIM1) && \
25902 (((CHANNEL) == TIM_CHANNEL_1) || \
25903 ((CHANNEL) == TIM_CHANNEL_2) || \
25904 ((CHANNEL) == TIM_CHANNEL_3) || \
25905 ((CHANNEL) == TIM_CHANNEL_4) || \
25906 ((CHANNEL) == TIM_CHANNEL_5) || \
25907 ((CHANNEL) == TIM_CHANNEL_6))) \
25908 || \
25909 (((INSTANCE) == TIM2) && \
25910 (((CHANNEL) == TIM_CHANNEL_1) || \
25911 ((CHANNEL) == TIM_CHANNEL_2) || \
25912 ((CHANNEL) == TIM_CHANNEL_3) || \
25913 ((CHANNEL) == TIM_CHANNEL_4))) \
25914 || \
25915 (((INSTANCE) == TIM3) && \
25916 (((CHANNEL) == TIM_CHANNEL_1)|| \
25917 ((CHANNEL) == TIM_CHANNEL_2) || \
25918 ((CHANNEL) == TIM_CHANNEL_3) || \
25919 ((CHANNEL) == TIM_CHANNEL_4))) \
25920 || \
25921 (((INSTANCE) == TIM4) && \
25922 (((CHANNEL) == TIM_CHANNEL_1) || \
25923 ((CHANNEL) == TIM_CHANNEL_2) || \
25924 ((CHANNEL) == TIM_CHANNEL_3) || \
25925 ((CHANNEL) == TIM_CHANNEL_4))) \
25926 || \
25927 (((INSTANCE) == TIM5) && \
25928 (((CHANNEL) == TIM_CHANNEL_1) || \
25929 ((CHANNEL) == TIM_CHANNEL_2) || \
25930 ((CHANNEL) == TIM_CHANNEL_3) || \
25931 ((CHANNEL) == TIM_CHANNEL_4))) \
25932 || \
25933 (((INSTANCE) == TIM8) && \
25934 (((CHANNEL) == TIM_CHANNEL_1) || \
25935 ((CHANNEL) == TIM_CHANNEL_2) || \
25936 ((CHANNEL) == TIM_CHANNEL_3) || \
25937 ((CHANNEL) == TIM_CHANNEL_4) || \
25938 ((CHANNEL) == TIM_CHANNEL_5) || \
25939 ((CHANNEL) == TIM_CHANNEL_6))) \
25940 || \
25941 (((INSTANCE) == TIM12) && \
25942 (((CHANNEL) == TIM_CHANNEL_1) || \
25943 ((CHANNEL) == TIM_CHANNEL_2))) \
25944 || \
25945 (((INSTANCE) == TIM13) && \
25946 (((CHANNEL) == TIM_CHANNEL_1))) \
25947 || \
25948 (((INSTANCE) == TIM14) && \
25949 (((CHANNEL) == TIM_CHANNEL_1))) \
25950 || \
25951 (((INSTANCE) == TIM15) && \
25952 (((CHANNEL) == TIM_CHANNEL_1) || \
25953 ((CHANNEL) == TIM_CHANNEL_2))) \
25954 || \
25955 (((INSTANCE) == TIM16) && \
25956 (((CHANNEL) == TIM_CHANNEL_1))) \
25957 || \
25958 (((INSTANCE) == TIM17) && \
25959 (((CHANNEL) == TIM_CHANNEL_1))))
25960
25961/****************** TIM Instances : supporting the break function *************/
25962#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
25963 (((INSTANCE) == TIM1) || \
25964 ((INSTANCE) == TIM8) || \
25965 ((INSTANCE) == TIM15) || \
25966 ((INSTANCE) == TIM16) || \
25967 ((INSTANCE) == TIM17))
25968
25969/************** TIM Instances : supporting Break source selection *************/
25970#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25971 ((INSTANCE) == TIM8))
25972
25973/****************** TIM Instances : supporting complementary output(s) ********/
25974#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
25975 ((((INSTANCE) == TIM1) && \
25976 (((CHANNEL) == TIM_CHANNEL_1) || \
25977 ((CHANNEL) == TIM_CHANNEL_2) || \
25978 ((CHANNEL) == TIM_CHANNEL_3))) \
25979 || \
25980 (((INSTANCE) == TIM8) && \
25981 (((CHANNEL) == TIM_CHANNEL_1) || \
25982 ((CHANNEL) == TIM_CHANNEL_2) || \
25983 ((CHANNEL) == TIM_CHANNEL_3))) \
25984 || \
25985 (((INSTANCE) == TIM15) && \
25986 ((CHANNEL) == TIM_CHANNEL_1)) \
25987 || \
25988 (((INSTANCE) == TIM16) && \
25989 ((CHANNEL) == TIM_CHANNEL_1)) \
25990 || \
25991 (((INSTANCE) == TIM17) && \
25992 ((CHANNEL) == TIM_CHANNEL_1)))
25993
25994/****************** TIM Instances : supporting counting mode selection ********/
25995#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
25996 (((INSTANCE) == TIM1) || \
25997 ((INSTANCE) == TIM2) || \
25998 ((INSTANCE) == TIM3) || \
25999 ((INSTANCE) == TIM4) || \
26000 ((INSTANCE) == TIM5) || \
26001 ((INSTANCE) == TIM8))
26002
26003/****************** TIM Instances : supporting repetition counter *************/
26004#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
26005 (((INSTANCE) == TIM1) || \
26006 ((INSTANCE) == TIM8) || \
26007 ((INSTANCE) == TIM15) || \
26008 ((INSTANCE) == TIM16) || \
26009 ((INSTANCE) == TIM17))
26010
26011/****************** TIM Instances : supporting synchronization ****************/
26012#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
26013 (((__INSTANCE__) == TIM1) || \
26014 ((__INSTANCE__) == TIM2) || \
26015 ((__INSTANCE__) == TIM3) || \
26016 ((__INSTANCE__) == TIM4) || \
26017 ((__INSTANCE__) == TIM5) || \
26018 ((__INSTANCE__) == TIM6) || \
26019 ((__INSTANCE__) == TIM8) || \
26020 ((__INSTANCE__) == TIM12) || \
26021 ((__INSTANCE__) == TIM15))
26022
26023/****************** TIM Instances : supporting clock division *****************/
26024#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
26025 (((INSTANCE) == TIM1) || \
26026 ((INSTANCE) == TIM2) || \
26027 ((INSTANCE) == TIM3) || \
26028 ((INSTANCE) == TIM4) || \
26029 ((INSTANCE) == TIM5) || \
26030 ((INSTANCE) == TIM8) || \
26031 ((INSTANCE) == TIM15) || \
26032 ((INSTANCE) == TIM16) || \
26033 ((INSTANCE) == TIM17))
26034
26035/****************** TIM Instances : supporting external clock mode 1 for ETRF input */
26036#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
26037 (((INSTANCE) == TIM1) || \
26038 ((INSTANCE) == TIM2) || \
26039 ((INSTANCE) == TIM3) || \
26040 ((INSTANCE) == TIM4) || \
26041 ((INSTANCE) == TIM5) || \
26042 ((INSTANCE) == TIM8))
26043
26044/****************** TIM Instances : supporting external clock mode 2 **********/
26045#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
26046 (((INSTANCE) == TIM1) || \
26047 ((INSTANCE) == TIM2) || \
26048 ((INSTANCE) == TIM3) || \
26049 ((INSTANCE) == TIM4) || \
26050 ((INSTANCE) == TIM5) || \
26051 ((INSTANCE) == TIM8))
26052
26053/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
26054#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
26055 (((INSTANCE) == TIM1) || \
26056 ((INSTANCE) == TIM2) || \
26057 ((INSTANCE) == TIM3) || \
26058 ((INSTANCE) == TIM4) || \
26059 ((INSTANCE) == TIM5) || \
26060 ((INSTANCE) == TIM8) || \
26061 ((INSTANCE) == TIM15))
26062
26063/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
26064#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
26065 (((INSTANCE) == TIM1) || \
26066 ((INSTANCE) == TIM2) || \
26067 ((INSTANCE) == TIM3) || \
26068 ((INSTANCE) == TIM4) || \
26069 ((INSTANCE) == TIM5) || \
26070 ((INSTANCE) == TIM8) || \
26071 ((INSTANCE) == TIM15))
26072
26073/****************** TIM Instances : supporting OCxREF clear *******************/
26074#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
26075 (((INSTANCE) == TIM1) || \
26076 ((INSTANCE) == TIM2) || \
26077 ((INSTANCE) == TIM3))
26078
26079/****************** TIM Instances : TIM_32B_COUNTER ***************************/
26080#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
26081 (((INSTANCE) == TIM2) || \
26082 ((INSTANCE) == TIM5))
26083
26084/****************** TIM Instances : TIM_BKIN2 ***************************/
26085#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
26086 (((INSTANCE) == TIM1) || \
26087 ((INSTANCE) == TIM8))
26088
26089/****************** TIM Instances : supporting Hall sensor interface **********/
26090#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
26091 ((__INSTANCE__) == TIM2) || \
26092 ((__INSTANCE__) == TIM3) || \
26093 ((__INSTANCE__) == TIM4) || \
26094 ((__INSTANCE__) == TIM5) || \
26095 ((__INSTANCE__) == TIM15) || \
26096 ((__INSTANCE__) == TIM8))
26097
26098/****************************** HRTIM Instances *******************************/
26099#define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
26100
26101/******************** USART Instances : Synchronous mode **********************/
26102#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
26103 ((INSTANCE) == USART2) || \
26104 ((INSTANCE) == USART3) || \
26105 ((INSTANCE) == USART6))
26106
26107/******************** USART Instances : SPI slave mode ************************/
26108#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
26109 ((INSTANCE) == USART2) || \
26110 ((INSTANCE) == USART3) || \
26111 ((INSTANCE) == USART6))
26112
26113/******************** UART Instances : Asynchronous mode **********************/
26114#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
26115 ((INSTANCE) == USART2) || \
26116 ((INSTANCE) == USART3) || \
26117 ((INSTANCE) == UART4) || \
26118 ((INSTANCE) == UART5) || \
26119 ((INSTANCE) == USART6) || \
26120 ((INSTANCE) == UART7) || \
26121 ((INSTANCE) == UART8))
26122
26123/******************** UART Instances : FIFO mode.******************************/
26124#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
26125 ((INSTANCE) == USART2) || \
26126 ((INSTANCE) == USART3) || \
26127 ((INSTANCE) == UART4) || \
26128 ((INSTANCE) == UART5) || \
26129 ((INSTANCE) == USART6) || \
26130 ((INSTANCE) == UART7) || \
26131 ((INSTANCE) == UART8))
26132
26133/****************** UART Instances : Auto Baud Rate detection *****************/
26134#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
26135 ((INSTANCE) == USART2) || \
26136 ((INSTANCE) == USART3) || \
26137 ((INSTANCE) == UART4) || \
26138 ((INSTANCE) == UART5) || \
26139 ((INSTANCE) == USART6) || \
26140 ((INSTANCE) == UART7) || \
26141 ((INSTANCE) == UART8))
26142
26143/*********************** UART Instances : Driver Enable ***********************/
26144#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
26145 ((INSTANCE) == USART2) || \
26146 ((INSTANCE) == USART3) || \
26147 ((INSTANCE) == UART4) || \
26148 ((INSTANCE) == UART5) || \
26149 ((INSTANCE) == USART6) || \
26150 ((INSTANCE) == UART7) || \
26151 ((INSTANCE) == UART8) || \
26152 ((INSTANCE) == LPUART1))
26153
26154/********************* UART Instances : Half-Duplex mode **********************/
26155#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
26156 ((INSTANCE) == USART2) || \
26157 ((INSTANCE) == USART3) || \
26158 ((INSTANCE) == UART4) || \
26159 ((INSTANCE) == UART5) || \
26160 ((INSTANCE) == USART6) || \
26161 ((INSTANCE) == UART7) || \
26162 ((INSTANCE) == UART8) || \
26163 ((INSTANCE) == LPUART1))
26164
26165/******************* UART Instances : Hardware Flow control *******************/
26166#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
26167 ((INSTANCE) == USART2) || \
26168 ((INSTANCE) == USART3) || \
26169 ((INSTANCE) == UART4) || \
26170 ((INSTANCE) == UART5) || \
26171 ((INSTANCE) == USART6) || \
26172 ((INSTANCE) == UART7) || \
26173 ((INSTANCE) == UART8) || \
26174 ((INSTANCE) == LPUART1))
26175
26176/************************* UART Instances : LIN mode **************************/
26177#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
26178 ((INSTANCE) == USART2) || \
26179 ((INSTANCE) == USART3) || \
26180 ((INSTANCE) == UART4) || \
26181 ((INSTANCE) == UART5) || \
26182 ((INSTANCE) == USART6) || \
26183 ((INSTANCE) == UART7) || \
26184 ((INSTANCE) == UART8))
26185
26186/****************** UART Instances : Wake-up from Stop mode *******************/
26187#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
26188 ((INSTANCE) == USART2) || \
26189 ((INSTANCE) == USART3) || \
26190 ((INSTANCE) == UART4) || \
26191 ((INSTANCE) == UART5) || \
26192 ((INSTANCE) == USART6) || \
26193 ((INSTANCE) == UART7) || \
26194 ((INSTANCE) == UART8) || \
26195 ((INSTANCE) == LPUART1))
26196
26197/************************* UART Instances : IRDA mode *************************/
26198#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
26199 ((INSTANCE) == USART2) || \
26200 ((INSTANCE) == USART3) || \
26201 ((INSTANCE) == UART4) || \
26202 ((INSTANCE) == UART5) || \
26203 ((INSTANCE) == USART6) || \
26204 ((INSTANCE) == UART7) || \
26205 ((INSTANCE) == UART8))
26206
26207/********************* USART Instances : Smard card mode **********************/
26208#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
26209 ((INSTANCE) == USART2) || \
26210 ((INSTANCE) == USART3) || \
26211 ((INSTANCE) == USART6))
26212
26213/****************************** LPUART Instance *******************************/
26214#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
26215
26216/****************************** IWDG Instances ********************************/
26217#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1)
26218/****************************** USB Instances ********************************/
26219#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
26220
26221/****************************** WWDG Instances ********************************/
26222#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1)
26223/****************************** MDIOS Instances ********************************/
26224#define IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS)
26225
26226/****************************** CEC Instances *********************************/
26227#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
26228
26229/****************************** SAI Instances ********************************/
26230#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
26231 ((INSTANCE) == SAI1_Block_B) || \
26232 ((INSTANCE) == SAI2_Block_A) || \
26233 ((INSTANCE) == SAI2_Block_B) || \
26234 ((INSTANCE) == SAI3_Block_A) || \
26235 ((INSTANCE) == SAI3_Block_B) || \
26236 ((INSTANCE) == SAI4_Block_A) || \
26237 ((INSTANCE) == SAI4_Block_B))
26238
26239/****************************** SPDIFRX Instances ********************************/
26240#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
26241
26242/****************************** OPAMP Instances *******************************/
26243#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
26244 ((INSTANCE) == OPAMP2))
26245
26246#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
26247
26248/*********************** USB OTG PCD Instances ********************************/
26249#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
26250 ((INSTANCE) == USB_OTG_HS))
26251
26252/*********************** USB OTG HCD Instances ********************************/
26253#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
26254 ((INSTANCE) == USB_OTG_HS))
26255
26256/******************************************************************************/
26257/* For a painless codes migration between the STM32H7xx device product */
26258/* lines, or with STM32F7xx devices the aliases defined below are put */
26259/* in place to overcome the differences in the interrupt handlers and IRQn */
26260/* definitions. No need to update developed interrupt code when moving */
26261/* across product lines within the same STM32H7 Family */
26262/******************************************************************************/
26263
26264/* Aliases for __IRQn */
26265#define HASH_RNG_IRQn RNG_IRQn
26266#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
26267#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
26268#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
26269#define PVD_IRQn PVD_AVD_IRQn
26270
26271
26272
26273/* Aliases for __IRQHandler */
26274#define HASH_RNG_IRQHandler RNG_IRQHandler
26275#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
26276#define TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler
26277#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
26278#define PVD_IRQHandler PVD_AVD_IRQHandler
26279
26280/* Aliases for COMP __IRQHandler */
26281#define COMP_IRQHandler COMP1_IRQHandler
26282
26283/**
26284 * @}
26285 */
26286
26287/**
26288 * @}
26289 */
26290
26291/**
26292 * @}
26293 */
26294
26295#ifdef __cplusplus
26296}
26297#endif /* __cplusplus */
26298
26299#endif /* STM32H743xx_H */
26300
26301/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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