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authorAkshay <[email protected]>2022-04-10 12:13:40 +0100
committerAkshay <[email protected]>2022-04-10 12:13:40 +0100
commitdc90387ce7d8ba7b607d9c48540bf6d8b560f14d (patch)
tree4ccb8fa5886b66fa9d480edef74236c27f035e16 /lib/chibios/os/common/ext/ST/STM32L0xx/stm32l073xx.h
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1/**
2 ******************************************************************************
3 * @file stm32l073xx.h
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
6 * This file contains all the peripheral register's definitions, bits
7 * definitions and memory mapping for stm32l073xx devices.
8 *
9 * This file contains:
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral's registers hardware
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
18 *
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ******************************************************************************
42 */
43
44/** @addtogroup CMSIS
45 * @{
46 */
47
48/** @addtogroup stm32l073xx
49 * @{
50 */
51
52#ifndef __STM32L073xx_H
53#define __STM32L073xx_H
54
55#ifdef __cplusplus
56 extern "C" {
57#endif
58
59
60/** @addtogroup Configuration_section_for_CMSIS
61 * @{
62 */
63/**
64 * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
65 */
66#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */
67#define __MPU_PRESENT 1 /*!< STM32L0xx provides an MPU */
68#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */
69#define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */
70#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
71
72/**
73 * @}
74 */
75
76/** @addtogroup Peripheral_interrupt_number_definition
77 * @{
78 */
79
80/**
81 * @brief stm32l073xx Interrupt Number Definition, according to the selected device
82 * in @ref Library_configuration_section
83 */
84
85/*!< Interrupt Number Definition */
86typedef enum
87{
88/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
89 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
90 HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
91 SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
92 PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
93 SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
94
95/****** STM32L-0 specific Interrupt Numbers *********************************************************/
96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
97 PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
98 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
99 FLASH_IRQn = 3, /*!< FLASH Interrupt */
100 RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */
101 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
102 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
103 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
104 TSC_IRQn = 8, /*!< TSC Interrupt */
105 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
106 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
107 DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
108 ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
109 LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
110 USART4_5_IRQn = 14, /*!< USART4 and USART5 Interrupt */
111 TIM2_IRQn = 15, /*!< TIM2 Interrupt */
112 TIM3_IRQn = 16, /*!< TIM3 Interrupt */
113 TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
114 TIM7_IRQn = 18, /*!< TIM7 Interrupt */
115 TIM21_IRQn = 20, /*!< TIM21 Interrupt */
116 I2C3_IRQn = 21, /*!< I2C3 Interrupt */
117 TIM22_IRQn = 22, /*!< TIM22 Interrupt */
118 I2C1_IRQn = 23, /*!< I2C1 Interrupt */
119 I2C2_IRQn = 24, /*!< I2C2 Interrupt */
120 SPI1_IRQn = 25, /*!< SPI1 Interrupt */
121 SPI2_IRQn = 26, /*!< SPI2 Interrupt */
122 USART1_IRQn = 27, /*!< USART1 Interrupt */
123 USART2_IRQn = 28, /*!< USART2 Interrupt */
124 RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */
125 LCD_IRQn = 30, /*!< LCD Interrupt */
126 USB_IRQn = 31, /*!< USB global Interrupt */
127} IRQn_Type;
128
129/**
130 * @}
131 */
132
133#include "core_cm0plus.h"
134#include "system_stm32l0xx.h"
135#include <stdint.h>
136
137/** @addtogroup Peripheral_registers_structures
138 * @{
139 */
140
141/**
142 * @brief Analog to Digital Converter
143 */
144
145typedef struct
146{
147 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
148 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
149 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
150 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
151 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
152 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
153 uint32_t RESERVED1; /*!< Reserved, 0x18 */
154 uint32_t RESERVED2; /*!< Reserved, 0x1C */
155 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
156 uint32_t RESERVED3; /*!< Reserved, 0x24 */
157 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
158 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
159 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
160 uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
161 __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
162} ADC_TypeDef;
163
164typedef struct
165{
166 __IO uint32_t CCR;
167} ADC_Common_TypeDef;
168
169
170/**
171 * @brief Comparator
172 */
173
174typedef struct
175{
176 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
177} COMP_TypeDef;
178
179typedef struct
180{
181 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
182} COMP_Common_TypeDef;
183
184
185/**
186* @brief CRC calculation unit
187*/
188
189typedef struct
190{
191__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
192__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
193uint8_t RESERVED0; /*!< Reserved, 0x05 */
194uint16_t RESERVED1; /*!< Reserved, 0x06 */
195__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
196uint32_t RESERVED2; /*!< Reserved, 0x0C */
197__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
198__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
199} CRC_TypeDef;
200
201/**
202 * @brief Clock Recovery System
203 */
204
205typedef struct
206{
207__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
208__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
209__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
210__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
211} CRS_TypeDef;
212
213/**
214 * @brief Digital to Analog Converter
215 */
216
217typedef struct
218{
219 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
220 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
221 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
222 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
223 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
224 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
225 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
226 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
227 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
228 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
229 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
230 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
231 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
232 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
233} DAC_TypeDef;
234
235/**
236 * @brief Debug MCU
237 */
238
239typedef struct
240{
241 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
242 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
243 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
244 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
245}DBGMCU_TypeDef;
246
247/**
248 * @brief DMA Controller
249 */
250
251typedef struct
252{
253 __IO uint32_t CCR; /*!< DMA channel x configuration register */
254 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
255 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
256 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
257} DMA_Channel_TypeDef;
258
259typedef struct
260{
261 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
262 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
263} DMA_TypeDef;
264
265typedef struct
266{
267 __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
268} DMA_Request_TypeDef;
269
270/**
271 * @brief External Interrupt/Event Controller
272 */
273
274typedef struct
275{
276 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
277 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
278 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
279 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
280 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
281 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
282}EXTI_TypeDef;
283
284/**
285 * @brief FLASH Registers
286 */
287typedef struct
288{
289 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
290 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
291 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
292 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
293 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
294 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
295 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
296 __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
297 __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
298 __IO uint32_t RESERVED1[23]; /*!< Reserved1, Address offset: 0x24 */
299 __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */
300} FLASH_TypeDef;
301
302
303/**
304 * @brief Option Bytes Registers
305 */
306typedef struct
307{
308 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
309 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
310 __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
311 __IO uint32_t WRP23; /*!< write protection Bytes 2 and 3 Address offset: 0x0C */
312 __IO uint32_t WRP45; /*!< write protection Bytes 4 and 5 Address offset: 0x10 */
313} OB_TypeDef;
314
315
316/**
317 * @brief General Purpose IO
318 */
319
320typedef struct
321{
322 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
323 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
324 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
325 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
326 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
327 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
328 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
329 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
330 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
331 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
332}GPIO_TypeDef;
333
334/**
335 * @brief LPTIMIMER
336 */
337typedef struct
338{
339 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
340 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
341 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
342 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
343 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
344 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
345 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
346 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
347} LPTIM_TypeDef;
348
349/**
350 * @brief SysTem Configuration
351 */
352
353typedef struct
354{
355 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
356 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
357 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
358 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
359 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
360} SYSCFG_TypeDef;
361
362
363
364/**
365 * @brief Inter-integrated Circuit Interface
366 */
367
368typedef struct
369{
370 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
371 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
372 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
373 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
374 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
375 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
376 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
377 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
378 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
379 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
380 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
381}I2C_TypeDef;
382
383
384/**
385 * @brief Independent WATCHDOG
386 */
387typedef struct
388{
389 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
390 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
391 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
392 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
393 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
394} IWDG_TypeDef;
395
396/**
397 * @brief LCD
398 */
399typedef struct
400{
401 __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
402 __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
403 __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
404 __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
405 uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
406 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
407} LCD_TypeDef;
408
409/**
410 * @brief MIFARE Firewall
411 */
412typedef struct
413{
414 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
415 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
416 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
417 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
418 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
419 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
420 __IO uint32_t LSSA ; /*!< Library Segment Start Address register, Address offset: 0x18 */
421 __IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */
422 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
423
424} FIREWALL_TypeDef;
425
426/**
427 * @brief Power Control
428 */
429typedef struct
430{
431 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
432 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
433} PWR_TypeDef;
434
435/**
436 * @brief Reset and Clock Control
437 */
438typedef struct
439{
440 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
441 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
442 __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
443 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
444 __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
445 __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
446 __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
447 __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
448 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
449 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
450 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
451 __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
452 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
453 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
454 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
455 __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
456 __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
457 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
458 __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
459 __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
460 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
461} RCC_TypeDef;
462
463/**
464 * @brief Random numbers generator
465 */
466typedef struct
467{
468 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
469 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
470 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
471} RNG_TypeDef;
472
473/**
474 * @brief Real-Time Clock
475 */
476typedef struct
477{
478 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
479 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
480 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
481 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
482 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
483 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
484 uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
485 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
486 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
487 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
488 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
489 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
490 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
491 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
492 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
493 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
494 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
495 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
496 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
497 __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
498 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
499 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
500 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
501 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
502 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
503} RTC_TypeDef;
504
505
506/**
507 * @brief Serial Peripheral Interface
508 */
509typedef struct
510{
511 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
512 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
513 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
514 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
515 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
516 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
517 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
518 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
519 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
520} SPI_TypeDef;
521
522/**
523 * @brief TIM
524 */
525typedef struct
526{
527 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
528 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
529 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
530 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
531 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
532 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
533 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
534 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
535 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
536 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
537 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
538 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
539 uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
540 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
541 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
542 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
543 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
544 uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
545 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
546 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
547 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
548} TIM_TypeDef;
549
550/**
551 * @brief Touch Sensing Controller (TSC)
552 */
553typedef struct
554{
555 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
556 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
557 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
558 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
559 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
560 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
561 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
562 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
563 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
564 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
565 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
566 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
567 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
568 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
569} TSC_TypeDef;
570
571/**
572 * @brief Universal Synchronous Asynchronous Receiver Transmitter
573 */
574typedef struct
575{
576 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
577 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
578 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
579 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
580 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
581 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
582 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
583 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
584 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
585 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
586 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
587} USART_TypeDef;
588
589/**
590 * @brief Window WATCHDOG
591 */
592typedef struct
593{
594 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
595 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
596 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
597} WWDG_TypeDef;
598
599/**
600 * @brief Universal Serial Bus Full Speed Device
601 */
602typedef struct
603{
604 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
605 __IO uint16_t RESERVED0; /*!< Reserved */
606 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
607 __IO uint16_t RESERVED1; /*!< Reserved */
608 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
609 __IO uint16_t RESERVED2; /*!< Reserved */
610 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
611 __IO uint16_t RESERVED3; /*!< Reserved */
612 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
613 __IO uint16_t RESERVED4; /*!< Reserved */
614 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
615 __IO uint16_t RESERVED5; /*!< Reserved */
616 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
617 __IO uint16_t RESERVED6; /*!< Reserved */
618 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
619 __IO uint16_t RESERVED7[17]; /*!< Reserved */
620 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
621 __IO uint16_t RESERVED8; /*!< Reserved */
622 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
623 __IO uint16_t RESERVED9; /*!< Reserved */
624 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
625 __IO uint16_t RESERVEDA; /*!< Reserved */
626 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
627 __IO uint16_t RESERVEDB; /*!< Reserved */
628 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
629 __IO uint16_t RESERVEDC; /*!< Reserved */
630 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
631 __IO uint16_t RESERVEDD; /*!< Reserved */
632 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
633 __IO uint16_t RESERVEDE; /*!< Reserved */
634} USB_TypeDef;
635
636/**
637 * @}
638 */
639
640/** @addtogroup Peripheral_memory_map
641 * @{
642 */
643#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
644#define FLASH_BANK2_BASE ((uint32_t)0x08018000U) /*!< FLASH BANK2 base address in the alias region */
645#define FLASH_BANK1_END ((uint32_t)0x08017FFFU) /*!< Program end FLASH BANK1 address */
646#define FLASH_BANK2_END ((uint32_t)0x0802FFFFU) /*!< Program end FLASH BANK2 address */
647#define DATA_EEPROM_BASE ((uint32_t)0x08080000U) /*!< DATA_EEPROM base address in the alias region */
648#define DATA_EEPROM_BANK2_BASE ((uint32_t)0x08080C00U) /*!< DATA EEPROM BANK2 base address in the alias region */
649#define DATA_EEPROM_BANK1_END ((uint32_t)0x08080BFFU) /*!< Program end DATA EEPROM BANK1 address */
650#define DATA_EEPROM_BANK2_END ((uint32_t)0x080817FFU) /*!< Program end DATA EEPROM BANK2 address */
651#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
652#define SRAM_SIZE_MAX ((uint32_t)0x00005000U) /*!< maximum SRAM size (up to 20KBytes) */
653
654#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
655
656/*!< Peripheral memory map */
657#define APBPERIPH_BASE PERIPH_BASE
658#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
659#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000U)
660
661#define TIM2_BASE (APBPERIPH_BASE + 0x00000000U)
662#define TIM3_BASE (APBPERIPH_BASE + 0x00000400U)
663#define TIM6_BASE (APBPERIPH_BASE + 0x00001000U)
664#define TIM7_BASE (APBPERIPH_BASE + 0x00001400U)
665#define LCD_BASE (APBPERIPH_BASE + 0x00002400U)
666#define RTC_BASE (APBPERIPH_BASE + 0x00002800U)
667#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00U)
668#define IWDG_BASE (APBPERIPH_BASE + 0x00003000U)
669#define SPI2_BASE (APBPERIPH_BASE + 0x00003800U)
670#define USART2_BASE (APBPERIPH_BASE + 0x00004400U)
671#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800U)
672#define USART4_BASE (APBPERIPH_BASE + 0x00004C00U)
673#define USART5_BASE (APBPERIPH_BASE + 0x00005000U)
674#define I2C1_BASE (APBPERIPH_BASE + 0x00005400U)
675#define I2C2_BASE (APBPERIPH_BASE + 0x00005800U)
676#define CRS_BASE (APBPERIPH_BASE + 0x00006C00U)
677#define PWR_BASE (APBPERIPH_BASE + 0x00007000U)
678#define DAC_BASE (APBPERIPH_BASE + 0x00007400U)
679#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00U)
680#define I2C3_BASE (APBPERIPH_BASE + 0x00007800U)
681
682#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000U)
683#define COMP1_BASE (APBPERIPH_BASE + 0x00010018U)
684#define COMP2_BASE (APBPERIPH_BASE + 0x0001001CU)
685#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
686#define EXTI_BASE (APBPERIPH_BASE + 0x00010400U)
687#define TIM21_BASE (APBPERIPH_BASE + 0x00010800U)
688#define TIM22_BASE (APBPERIPH_BASE + 0x00011400U)
689#define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00U)
690#define ADC1_BASE (APBPERIPH_BASE + 0x00012400U)
691#define ADC_BASE (APBPERIPH_BASE + 0x00012708U)
692#define SPI1_BASE (APBPERIPH_BASE + 0x00013000U)
693#define USART1_BASE (APBPERIPH_BASE + 0x00013800U)
694#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800U)
695
696#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
697#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U)
698#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU)
699#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U)
700#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U)
701#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U)
702#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU)
703#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U)
704#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8U)
705
706
707#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
708#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */
709#define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */
710#define FLASHSIZE_BASE ((uint32_t)0x1FF8007CU) /*!< FLASH Size register base address */
711#define UID_BASE ((uint32_t)0x1FF80050U) /*!< Unique device ID register base address */
712#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
713#define TSC_BASE (AHBPERIPH_BASE + 0x00004000U)
714#define RNG_BASE (AHBPERIPH_BASE + 0x00005000U)
715
716#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000U)
717#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400U)
718#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800U)
719#define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00U)
720#define GPIOE_BASE (IOPPERIPH_BASE + 0x00001000U)
721#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00U)
722
723/**
724 * @}
725 */
726
727/** @addtogroup Peripheral_declaration
728 * @{
729 */
730
731#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
732#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
733#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
734#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
735#define RTC ((RTC_TypeDef *) RTC_BASE)
736#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
737#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
738#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
739#define USART2 ((USART_TypeDef *) USART2_BASE)
740#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
741#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
742#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
743#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
744#define CRS ((CRS_TypeDef *) CRS_BASE)
745#define PWR ((PWR_TypeDef *) PWR_BASE)
746#define DAC ((DAC_TypeDef *) DAC_BASE)
747#define DAC1 ((DAC_TypeDef *) DAC_BASE)
748#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
749#define LCD ((LCD_TypeDef *) LCD_BASE)
750#define USART4 ((USART_TypeDef *) USART4_BASE)
751#define USART5 ((USART_TypeDef *) USART5_BASE)
752
753#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
754#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
755#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
756#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
757#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
758#define TIM22 ((TIM_TypeDef *) TIM22_BASE)
759#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
760#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
761#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
762/* Legacy defines */
763#define ADC ADC1_COMMON
764#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
765#define USART1 ((USART_TypeDef *) USART1_BASE)
766#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
767
768#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
769#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
770#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
771#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
772#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
773#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
774#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
775#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
776#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
777
778
779#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
780#define OB ((OB_TypeDef *) OB_BASE)
781#define RCC ((RCC_TypeDef *) RCC_BASE)
782#define CRC ((CRC_TypeDef *) CRC_BASE)
783#define TSC ((TSC_TypeDef *) TSC_BASE)
784#define RNG ((RNG_TypeDef *) RNG_BASE)
785
786#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
787#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
788#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
789#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
790#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
791#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
792
793#define USB ((USB_TypeDef *) USB_BASE)
794
795/**
796 * @}
797 */
798
799/** @addtogroup Exported_constants
800 * @{
801 */
802
803 /** @addtogroup Peripheral_Registers_Bits_Definition
804 * @{
805 */
806
807/******************************************************************************/
808/* Peripheral Registers Bits Definition */
809/******************************************************************************/
810/******************************************************************************/
811/* */
812/* Analog to Digital Converter (ADC) */
813/* */
814/******************************************************************************/
815/******************** Bits definition for ADC_ISR register ******************/
816#define ADC_ISR_EOCAL_Pos (11U)
817#define ADC_ISR_EOCAL_Msk (0x1U << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
818#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
819#define ADC_ISR_AWD_Pos (7U)
820#define ADC_ISR_AWD_Msk (0x1U << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
821#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
822#define ADC_ISR_OVR_Pos (4U)
823#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
824#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
825#define ADC_ISR_EOSEQ_Pos (3U)
826#define ADC_ISR_EOSEQ_Msk (0x1U << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
827#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
828#define ADC_ISR_EOC_Pos (2U)
829#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
830#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
831#define ADC_ISR_EOSMP_Pos (1U)
832#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
833#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
834#define ADC_ISR_ADRDY_Pos (0U)
835#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
836#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
837
838/* Old EOSEQ bit definition, maintained for legacy purpose */
839#define ADC_ISR_EOS ADC_ISR_EOSEQ
840
841/******************** Bits definition for ADC_IER register ******************/
842#define ADC_IER_EOCALIE_Pos (11U)
843#define ADC_IER_EOCALIE_Msk (0x1U << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
844#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
845#define ADC_IER_AWDIE_Pos (7U)
846#define ADC_IER_AWDIE_Msk (0x1U << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
847#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
848#define ADC_IER_OVRIE_Pos (4U)
849#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
850#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
851#define ADC_IER_EOSEQIE_Pos (3U)
852#define ADC_IER_EOSEQIE_Msk (0x1U << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
853#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
854#define ADC_IER_EOCIE_Pos (2U)
855#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
856#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
857#define ADC_IER_EOSMPIE_Pos (1U)
858#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
859#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
860#define ADC_IER_ADRDYIE_Pos (0U)
861#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
862#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
863
864/* Old EOSEQIE bit definition, maintained for legacy purpose */
865#define ADC_IER_EOSIE ADC_IER_EOSEQIE
866
867/******************** Bits definition for ADC_CR register *******************/
868#define ADC_CR_ADCAL_Pos (31U)
869#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
870#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
871#define ADC_CR_ADVREGEN_Pos (28U)
872#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
873#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
874#define ADC_CR_ADSTP_Pos (4U)
875#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
876#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
877#define ADC_CR_ADSTART_Pos (2U)
878#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
879#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
880#define ADC_CR_ADDIS_Pos (1U)
881#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
882#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
883#define ADC_CR_ADEN_Pos (0U)
884#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
885#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
886
887/******************* Bits definition for ADC_CFGR1 register *****************/
888#define ADC_CFGR1_AWDCH_Pos (26U)
889#define ADC_CFGR1_AWDCH_Msk (0x1FU << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
890#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
891#define ADC_CFGR1_AWDCH_0 (0x01U << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
892#define ADC_CFGR1_AWDCH_1 (0x02U << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
893#define ADC_CFGR1_AWDCH_2 (0x04U << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
894#define ADC_CFGR1_AWDCH_3 (0x08U << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
895#define ADC_CFGR1_AWDCH_4 (0x10U << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
896#define ADC_CFGR1_AWDEN_Pos (23U)
897#define ADC_CFGR1_AWDEN_Msk (0x1U << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
898#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
899#define ADC_CFGR1_AWDSGL_Pos (22U)
900#define ADC_CFGR1_AWDSGL_Msk (0x1U << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
901#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
902#define ADC_CFGR1_DISCEN_Pos (16U)
903#define ADC_CFGR1_DISCEN_Msk (0x1U << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
904#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
905#define ADC_CFGR1_AUTOFF_Pos (15U)
906#define ADC_CFGR1_AUTOFF_Msk (0x1U << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
907#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
908#define ADC_CFGR1_WAIT_Pos (14U)
909#define ADC_CFGR1_WAIT_Msk (0x1U << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
910#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
911#define ADC_CFGR1_CONT_Pos (13U)
912#define ADC_CFGR1_CONT_Msk (0x1U << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
913#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
914#define ADC_CFGR1_OVRMOD_Pos (12U)
915#define ADC_CFGR1_OVRMOD_Msk (0x1U << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
916#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
917#define ADC_CFGR1_EXTEN_Pos (10U)
918#define ADC_CFGR1_EXTEN_Msk (0x3U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
919#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
920#define ADC_CFGR1_EXTEN_0 (0x1U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
921#define ADC_CFGR1_EXTEN_1 (0x2U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
922#define ADC_CFGR1_EXTSEL_Pos (6U)
923#define ADC_CFGR1_EXTSEL_Msk (0x7U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
924#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
925#define ADC_CFGR1_EXTSEL_0 (0x1U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
926#define ADC_CFGR1_EXTSEL_1 (0x2U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
927#define ADC_CFGR1_EXTSEL_2 (0x4U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
928#define ADC_CFGR1_ALIGN_Pos (5U)
929#define ADC_CFGR1_ALIGN_Msk (0x1U << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
930#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
931#define ADC_CFGR1_RES_Pos (3U)
932#define ADC_CFGR1_RES_Msk (0x3U << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
933#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
934#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
935#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
936#define ADC_CFGR1_SCANDIR_Pos (2U)
937#define ADC_CFGR1_SCANDIR_Msk (0x1U << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
938#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
939#define ADC_CFGR1_DMACFG_Pos (1U)
940#define ADC_CFGR1_DMACFG_Msk (0x1U << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
941#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
942#define ADC_CFGR1_DMAEN_Pos (0U)
943#define ADC_CFGR1_DMAEN_Msk (0x1U << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
944#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
945
946/* Old WAIT bit definition, maintained for legacy purpose */
947#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
948
949/******************* Bits definition for ADC_CFGR2 register *****************/
950#define ADC_CFGR2_TOVS_Pos (9U)
951#define ADC_CFGR2_TOVS_Msk (0x1U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
952#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
953#define ADC_CFGR2_OVSS_Pos (5U)
954#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
955#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
956#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
957#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
958#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
959#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
960#define ADC_CFGR2_OVSR_Pos (2U)
961#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
962#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
963#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
964#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
965#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
966#define ADC_CFGR2_OVSE_Pos (0U)
967#define ADC_CFGR2_OVSE_Msk (0x1U << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
968#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
969#define ADC_CFGR2_CKMODE_Pos (30U)
970#define ADC_CFGR2_CKMODE_Msk (0x3U << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
971#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
972#define ADC_CFGR2_CKMODE_0 (0x1U << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
973#define ADC_CFGR2_CKMODE_1 (0x2U << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
974
975
976/****************** Bit definition for ADC_SMPR register ********************/
977#define ADC_SMPR_SMP_Pos (0U)
978#define ADC_SMPR_SMP_Msk (0x7U << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
979#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
980#define ADC_SMPR_SMP_0 (0x1U << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
981#define ADC_SMPR_SMP_1 (0x2U << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
982#define ADC_SMPR_SMP_2 (0x4U << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
983
984/* Legacy defines */
985#define ADC_SMPR_SMPR ADC_SMPR_SMP
986#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
987#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
988#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
989
990/******************* Bit definition for ADC_TR register ********************/
991#define ADC_TR_HT_Pos (16U)
992#define ADC_TR_HT_Msk (0xFFFU << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
993#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
994#define ADC_TR_LT_Pos (0U)
995#define ADC_TR_LT_Msk (0xFFFU << ADC_TR_LT_Pos) /*!< 0x00000FFF */
996#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
997
998/****************** Bit definition for ADC_CHSELR register ******************/
999#define ADC_CHSELR_CHSEL_Pos (0U)
1000#define ADC_CHSELR_CHSEL_Msk (0x7FFFFU << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
1001#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
1002#define ADC_CHSELR_CHSEL18_Pos (18U)
1003#define ADC_CHSELR_CHSEL18_Msk (0x1U << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
1004#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
1005#define ADC_CHSELR_CHSEL17_Pos (17U)
1006#define ADC_CHSELR_CHSEL17_Msk (0x1U << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
1007#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
1008#define ADC_CHSELR_CHSEL16_Pos (16U)
1009#define ADC_CHSELR_CHSEL16_Msk (0x1U << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */
1010#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< Channel 16 selection */
1011#define ADC_CHSELR_CHSEL15_Pos (15U)
1012#define ADC_CHSELR_CHSEL15_Msk (0x1U << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
1013#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
1014#define ADC_CHSELR_CHSEL14_Pos (14U)
1015#define ADC_CHSELR_CHSEL14_Msk (0x1U << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
1016#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
1017#define ADC_CHSELR_CHSEL13_Pos (13U)
1018#define ADC_CHSELR_CHSEL13_Msk (0x1U << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
1019#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
1020#define ADC_CHSELR_CHSEL12_Pos (12U)
1021#define ADC_CHSELR_CHSEL12_Msk (0x1U << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
1022#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
1023#define ADC_CHSELR_CHSEL11_Pos (11U)
1024#define ADC_CHSELR_CHSEL11_Msk (0x1U << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
1025#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
1026#define ADC_CHSELR_CHSEL10_Pos (10U)
1027#define ADC_CHSELR_CHSEL10_Msk (0x1U << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
1028#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
1029#define ADC_CHSELR_CHSEL9_Pos (9U)
1030#define ADC_CHSELR_CHSEL9_Msk (0x1U << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
1031#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
1032#define ADC_CHSELR_CHSEL8_Pos (8U)
1033#define ADC_CHSELR_CHSEL8_Msk (0x1U << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
1034#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
1035#define ADC_CHSELR_CHSEL7_Pos (7U)
1036#define ADC_CHSELR_CHSEL7_Msk (0x1U << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
1037#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
1038#define ADC_CHSELR_CHSEL6_Pos (6U)
1039#define ADC_CHSELR_CHSEL6_Msk (0x1U << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
1040#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
1041#define ADC_CHSELR_CHSEL5_Pos (5U)
1042#define ADC_CHSELR_CHSEL5_Msk (0x1U << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
1043#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
1044#define ADC_CHSELR_CHSEL4_Pos (4U)
1045#define ADC_CHSELR_CHSEL4_Msk (0x1U << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
1046#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
1047#define ADC_CHSELR_CHSEL3_Pos (3U)
1048#define ADC_CHSELR_CHSEL3_Msk (0x1U << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
1049#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
1050#define ADC_CHSELR_CHSEL2_Pos (2U)
1051#define ADC_CHSELR_CHSEL2_Msk (0x1U << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
1052#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
1053#define ADC_CHSELR_CHSEL1_Pos (1U)
1054#define ADC_CHSELR_CHSEL1_Msk (0x1U << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
1055#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
1056#define ADC_CHSELR_CHSEL0_Pos (0U)
1057#define ADC_CHSELR_CHSEL0_Msk (0x1U << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
1058#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
1059
1060/******************** Bit definition for ADC_DR register ********************/
1061#define ADC_DR_DATA_Pos (0U)
1062#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
1063#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
1064
1065/******************** Bit definition for ADC_CALFACT register ********************/
1066#define ADC_CALFACT_CALFACT_Pos (0U)
1067#define ADC_CALFACT_CALFACT_Msk (0x7FU << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
1068#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
1069
1070/******************* Bit definition for ADC_CCR register ********************/
1071#define ADC_CCR_LFMEN_Pos (25U)
1072#define ADC_CCR_LFMEN_Msk (0x1U << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
1073#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
1074#define ADC_CCR_VLCDEN_Pos (24U)
1075#define ADC_CCR_VLCDEN_Msk (0x1U << ADC_CCR_VLCDEN_Pos) /*!< 0x01000000 */
1076#define ADC_CCR_VLCDEN ADC_CCR_VLCDEN_Msk /*!< Voltage LCD enable */
1077#define ADC_CCR_TSEN_Pos (23U)
1078#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
1079#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */
1080#define ADC_CCR_VREFEN_Pos (22U)
1081#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
1082#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
1083#define ADC_CCR_PRESC_Pos (18U)
1084#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
1085#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
1086#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
1087#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
1088#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
1089#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
1090
1091/******************************************************************************/
1092/* */
1093/* Analog Comparators (COMP) */
1094/* */
1095/******************************************************************************/
1096/************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
1097/* COMP1 bits definition */
1098#define COMP_CSR_COMP1EN_Pos (0U)
1099#define COMP_CSR_COMP1EN_Msk (0x1U << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */
1100#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */
1101#define COMP_CSR_COMP1INNSEL_Pos (4U)
1102#define COMP_CSR_COMP1INNSEL_Msk (0x3U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
1103#define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */
1104#define COMP_CSR_COMP1INNSEL_0 (0x1U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
1105#define COMP_CSR_COMP1INNSEL_1 (0x2U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
1106#define COMP_CSR_COMP1WM_Pos (8U)
1107#define COMP_CSR_COMP1WM_Msk (0x1U << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */
1108#define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */
1109#define COMP_CSR_COMP1LPTIM1IN1_Pos (12U)
1110#define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */
1111#define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */
1112#define COMP_CSR_COMP1POLARITY_Pos (15U)
1113#define COMP_CSR_COMP1POLARITY_Msk (0x1U << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */
1114#define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */
1115#define COMP_CSR_COMP1VALUE_Pos (30U)
1116#define COMP_CSR_COMP1VALUE_Msk (0x1U << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */
1117#define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */
1118#define COMP_CSR_COMP1LOCK_Pos (31U)
1119#define COMP_CSR_COMP1LOCK_Msk (0x1U << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */
1120#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
1121/* COMP2 bits definition */
1122#define COMP_CSR_COMP2EN_Pos (0U)
1123#define COMP_CSR_COMP2EN_Msk (0x1U << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */
1124#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */
1125#define COMP_CSR_COMP2SPEED_Pos (3U)
1126#define COMP_CSR_COMP2SPEED_Msk (0x1U << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */
1127#define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */
1128#define COMP_CSR_COMP2INNSEL_Pos (4U)
1129#define COMP_CSR_COMP2INNSEL_Msk (0x7U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */
1130#define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */
1131#define COMP_CSR_COMP2INNSEL_0 (0x1U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */
1132#define COMP_CSR_COMP2INNSEL_1 (0x2U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */
1133#define COMP_CSR_COMP2INNSEL_2 (0x4U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
1134#define COMP_CSR_COMP2INPSEL_Pos (8U)
1135#define COMP_CSR_COMP2INPSEL_Msk (0x7U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */
1136#define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */
1137#define COMP_CSR_COMP2INPSEL_0 (0x1U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */
1138#define COMP_CSR_COMP2INPSEL_1 (0x2U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */
1139#define COMP_CSR_COMP2INPSEL_2 (0x4U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */
1140#define COMP_CSR_COMP2LPTIM1IN2_Pos (12U)
1141#define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */
1142#define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */
1143#define COMP_CSR_COMP2LPTIM1IN1_Pos (13U)
1144#define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */
1145#define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */
1146#define COMP_CSR_COMP2POLARITY_Pos (15U)
1147#define COMP_CSR_COMP2POLARITY_Msk (0x1U << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */
1148#define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */
1149#define COMP_CSR_COMP2VALUE_Pos (30U)
1150#define COMP_CSR_COMP2VALUE_Msk (0x1U << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */
1151#define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */
1152#define COMP_CSR_COMP2LOCK_Pos (31U)
1153#define COMP_CSR_COMP2LOCK_Msk (0x1U << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
1154#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
1155
1156/********************** Bit definition for COMP_CSR register common ****************/
1157#define COMP_CSR_COMPxEN_Pos (0U)
1158#define COMP_CSR_COMPxEN_Msk (0x1U << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
1159#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
1160#define COMP_CSR_COMPxPOLARITY_Pos (15U)
1161#define COMP_CSR_COMPxPOLARITY_Msk (0x1U << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */
1162#define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */
1163#define COMP_CSR_COMPxOUTVALUE_Pos (30U)
1164#define COMP_CSR_COMPxOUTVALUE_Msk (0x1U << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */
1165#define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */
1166#define COMP_CSR_COMPxLOCK_Pos (31U)
1167#define COMP_CSR_COMPxLOCK_Msk (0x1U << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
1168#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
1169
1170/* Reference defines */
1171#define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
1172
1173/******************************************************************************/
1174/* */
1175/* CRC calculation unit (CRC) */
1176/* */
1177/******************************************************************************/
1178/******************* Bit definition for CRC_DR register *********************/
1179#define CRC_DR_DR_Pos (0U)
1180#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
1181#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
1182
1183/******************* Bit definition for CRC_IDR register ********************/
1184#define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
1185
1186/******************** Bit definition for CRC_CR register ********************/
1187#define CRC_CR_RESET_Pos (0U)
1188#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
1189#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
1190#define CRC_CR_POLYSIZE_Pos (3U)
1191#define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
1192#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
1193#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
1194#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
1195#define CRC_CR_REV_IN_Pos (5U)
1196#define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
1197#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
1198#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
1199#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
1200#define CRC_CR_REV_OUT_Pos (7U)
1201#define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
1202#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
1203
1204/******************* Bit definition for CRC_INIT register *******************/
1205#define CRC_INIT_INIT_Pos (0U)
1206#define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
1207#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
1208
1209/******************* Bit definition for CRC_POL register ********************/
1210#define CRC_POL_POL_Pos (0U)
1211#define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
1212#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
1213
1214/******************************************************************************/
1215/* */
1216/* CRS Clock Recovery System */
1217/* */
1218/******************************************************************************/
1219
1220/******************* Bit definition for CRS_CR register *********************/
1221#define CRS_CR_SYNCOKIE_Pos (0U)
1222#define CRS_CR_SYNCOKIE_Msk (0x1U << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
1223#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /* SYNC event OK interrupt enable */
1224#define CRS_CR_SYNCWARNIE_Pos (1U)
1225#define CRS_CR_SYNCWARNIE_Msk (0x1U << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
1226#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /* SYNC warning interrupt enable */
1227#define CRS_CR_ERRIE_Pos (2U)
1228#define CRS_CR_ERRIE_Msk (0x1U << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
1229#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /* SYNC error interrupt enable */
1230#define CRS_CR_ESYNCIE_Pos (3U)
1231#define CRS_CR_ESYNCIE_Msk (0x1U << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
1232#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /* Expected SYNC(ESYNCF) interrupt Enable*/
1233#define CRS_CR_CEN_Pos (5U)
1234#define CRS_CR_CEN_Msk (0x1U << CRS_CR_CEN_Pos) /*!< 0x00000020 */
1235#define CRS_CR_CEN CRS_CR_CEN_Msk /* Frequency error counter enable */
1236#define CRS_CR_AUTOTRIMEN_Pos (6U)
1237#define CRS_CR_AUTOTRIMEN_Msk (0x1U << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
1238#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /* Automatic trimming enable */
1239#define CRS_CR_SWSYNC_Pos (7U)
1240#define CRS_CR_SWSYNC_Msk (0x1U << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
1241#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /* A Software SYNC event is generated */
1242#define CRS_CR_TRIM_Pos (8U)
1243#define CRS_CR_TRIM_Msk (0x3FU << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
1244#define CRS_CR_TRIM CRS_CR_TRIM_Msk /* HSI48 oscillator smooth trimming */
1245
1246/******************* Bit definition for CRS_CFGR register *********************/
1247#define CRS_CFGR_RELOAD_Pos (0U)
1248#define CRS_CFGR_RELOAD_Msk (0xFFFFU << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
1249#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /* Counter reload value */
1250#define CRS_CFGR_FELIM_Pos (16U)
1251#define CRS_CFGR_FELIM_Msk (0xFFU << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
1252#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /* Frequency error limit */
1253
1254#define CRS_CFGR_SYNCDIV_Pos (24U)
1255#define CRS_CFGR_SYNCDIV_Msk (0x7U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
1256#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /* SYNC divider */
1257#define CRS_CFGR_SYNCDIV_0 (0x1U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
1258#define CRS_CFGR_SYNCDIV_1 (0x2U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
1259#define CRS_CFGR_SYNCDIV_2 (0x4U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
1260
1261#define CRS_CFGR_SYNCSRC_Pos (28U)
1262#define CRS_CFGR_SYNCSRC_Msk (0x3U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
1263#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /* SYNC signal source selection */
1264#define CRS_CFGR_SYNCSRC_0 (0x1U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
1265#define CRS_CFGR_SYNCSRC_1 (0x2U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
1266
1267#define CRS_CFGR_SYNCPOL_Pos (31U)
1268#define CRS_CFGR_SYNCPOL_Msk (0x1U << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
1269#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /* SYNC polarity selection */
1270
1271/******************* Bit definition for CRS_ISR register *********************/
1272#define CRS_ISR_SYNCOKF_Pos (0U)
1273#define CRS_ISR_SYNCOKF_Msk (0x1U << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
1274#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /* SYNC event OK flag */
1275#define CRS_ISR_SYNCWARNF_Pos (1U)
1276#define CRS_ISR_SYNCWARNF_Msk (0x1U << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
1277#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /* SYNC warning */
1278#define CRS_ISR_ERRF_Pos (2U)
1279#define CRS_ISR_ERRF_Msk (0x1U << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
1280#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /* SYNC error flag */
1281#define CRS_ISR_ESYNCF_Pos (3U)
1282#define CRS_ISR_ESYNCF_Msk (0x1U << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
1283#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /* Expected SYNC flag */
1284#define CRS_ISR_SYNCERR_Pos (8U)
1285#define CRS_ISR_SYNCERR_Msk (0x1U << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
1286#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /* SYNC error */
1287#define CRS_ISR_SYNCMISS_Pos (9U)
1288#define CRS_ISR_SYNCMISS_Msk (0x1U << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
1289#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /* SYNC missed */
1290#define CRS_ISR_TRIMOVF_Pos (10U)
1291#define CRS_ISR_TRIMOVF_Msk (0x1U << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
1292#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /* Trimming overflow or underflow */
1293#define CRS_ISR_FEDIR_Pos (15U)
1294#define CRS_ISR_FEDIR_Msk (0x1U << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
1295#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /* Frequency error direction */
1296#define CRS_ISR_FECAP_Pos (16U)
1297#define CRS_ISR_FECAP_Msk (0xFFFFU << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
1298#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /* Frequency error capture */
1299
1300/******************* Bit definition for CRS_ICR register *********************/
1301#define CRS_ICR_SYNCOKC_Pos (0U)
1302#define CRS_ICR_SYNCOKC_Msk (0x1U << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
1303#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /* SYNC event OK clear flag */
1304#define CRS_ICR_SYNCWARNC_Pos (1U)
1305#define CRS_ICR_SYNCWARNC_Msk (0x1U << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
1306#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /* SYNC warning clear flag */
1307#define CRS_ICR_ERRC_Pos (2U)
1308#define CRS_ICR_ERRC_Msk (0x1U << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
1309#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /* Error clear flag */
1310#define CRS_ICR_ESYNCC_Pos (3U)
1311#define CRS_ICR_ESYNCC_Msk (0x1U << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
1312#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /* Expected SYNC clear flag */
1313
1314/******************************************************************************/
1315/* */
1316/* Digital to Analog Converter (DAC) */
1317/* */
1318/******************************************************************************/
1319
1320/*
1321 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
1322 */
1323#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
1324
1325/******************** Bit definition for DAC_CR register ********************/
1326#define DAC_CR_EN1_Pos (0U)
1327#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
1328#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
1329#define DAC_CR_BOFF1_Pos (1U)
1330#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
1331#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
1332#define DAC_CR_TEN1_Pos (2U)
1333#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
1334#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
1335
1336#define DAC_CR_TSEL1_Pos (3U)
1337#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
1338#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
1339#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
1340#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
1341#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
1342
1343#define DAC_CR_WAVE1_Pos (6U)
1344#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
1345#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
1346#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
1347#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
1348
1349#define DAC_CR_MAMP1_Pos (8U)
1350#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
1351#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
1352#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
1353#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
1354#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
1355#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
1356
1357#define DAC_CR_DMAEN1_Pos (12U)
1358#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
1359#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
1360#define DAC_CR_DMAUDRIE1_Pos (13U)
1361#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
1362#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun interrupt enable */
1363
1364#define DAC_CR_EN2_Pos (16U)
1365#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
1366#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */
1367#define DAC_CR_BOFF2_Pos (17U)
1368#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
1369#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */
1370#define DAC_CR_TEN2_Pos (18U)
1371#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
1372#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */
1373
1374#define DAC_CR_TSEL2_Pos (19U)
1375#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
1376#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
1377#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
1378#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
1379#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
1380
1381#define DAC_CR_WAVE2_Pos (22U)
1382#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
1383#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
1384#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
1385#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
1386
1387#define DAC_CR_MAMP2_Pos (24U)
1388#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
1389#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
1390#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
1391#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
1392#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
1393#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
1394
1395#define DAC_CR_DMAEN2_Pos (28U)
1396#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
1397#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */
1398#define DAC_CR_DMAUDRIE2_Pos (29U)
1399#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
1400#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< DAC channel12DMA Underrun interrupt enable */
1401
1402/***************** Bit definition for DAC_SWTRIGR register ******************/
1403#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
1404#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
1405#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
1406#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
1407#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
1408#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */
1409
1410/***************** Bit definition for DAC_DHR12R1 register ******************/
1411#define DAC_DHR12R1_DACC1DHR_Pos (0U)
1412#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
1413#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
1414
1415/***************** Bit definition for DAC_DHR12L1 register ******************/
1416#define DAC_DHR12L1_DACC1DHR_Pos (4U)
1417#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
1418#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
1419
1420/****************** Bit definition for DAC_DHR8R1 register ******************/
1421#define DAC_DHR8R1_DACC1DHR_Pos (0U)
1422#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
1423#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
1424
1425/***************** Bit definition for DAC_DHR12R2 register ******************/
1426#define DAC_DHR12R2_DACC2DHR_Pos (0U)
1427#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
1428#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
1429
1430/***************** Bit definition for DAC_DHR12L2 register ******************/
1431#define DAC_DHR12L2_DACC2DHR_Pos (4U)
1432#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
1433#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
1434
1435/****************** Bit definition for DAC_DHR8R2 register ******************/
1436#define DAC_DHR8R2_DACC2DHR_Pos (0U)
1437#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
1438#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
1439
1440/***************** Bit definition for DAC_DHR12RD register ******************/
1441#define DAC_DHR12RD_DACC1DHR_Pos (0U)
1442#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
1443#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
1444#define DAC_DHR12RD_DACC2DHR_Pos (16U)
1445#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
1446#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
1447
1448/***************** Bit definition for DAC_DHR12LD register ******************/
1449#define DAC_DHR12LD_DACC1DHR_Pos (4U)
1450#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
1451#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
1452#define DAC_DHR12LD_DACC2DHR_Pos (20U)
1453#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
1454#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
1455
1456/****************** Bit definition for DAC_DHR8RD register ******************/
1457#define DAC_DHR8RD_DACC1DHR_Pos (0U)
1458#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
1459#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
1460#define DAC_DHR8RD_DACC2DHR_Pos (8U)
1461#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
1462#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
1463
1464/******************* Bit definition for DAC_DOR1 register *******************/
1465#define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFFU) /*!< DAC channel1 data output */
1466
1467/******************* Bit definition for DAC_DOR2 register *******************/
1468#define DAC_DOR2_DACC2DOR_Pos (0U)
1469#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
1470#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */
1471
1472/******************** Bit definition for DAC_SR register ********************/
1473#define DAC_SR_DMAUDR1_Pos (13U)
1474#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
1475#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */
1476#define DAC_SR_DMAUDR2_Pos (29U)
1477#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
1478#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */
1479
1480/******************************************************************************/
1481/* */
1482/* Debug MCU (DBGMCU) */
1483/* */
1484/******************************************************************************/
1485
1486/**************** Bit definition for DBGMCU_IDCODE register *****************/
1487#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
1488#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
1489#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
1490
1491#define DBGMCU_IDCODE_DIV_ID_Pos (12U)
1492#define DBGMCU_IDCODE_DIV_ID_Msk (0xFU << DBGMCU_IDCODE_DIV_ID_Pos) /*!< 0x0000F000 */
1493#define DBGMCU_IDCODE_DIV_ID DBGMCU_IDCODE_DIV_ID_Msk /*!< Division Identifier */
1494#define DBGMCU_IDCODE_MCD_DIV_ID_Pos (13U)
1495#define DBGMCU_IDCODE_MCD_DIV_ID_Msk (0x3U << DBGMCU_IDCODE_MCD_DIV_ID_Pos) /*!< 0x00006000 */
1496#define DBGMCU_IDCODE_MCD_DIV_ID DBGMCU_IDCODE_MCD_DIV_ID_Msk /*!< MCD divsion ID is 6 */
1497#define DBGMCU_IDCODE_REV_ID_Pos (16U)
1498#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
1499#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
1500#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
1501#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
1502#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
1503#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
1504#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
1505#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
1506#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
1507#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
1508#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
1509#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
1510#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
1511#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
1512#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
1513#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
1514#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
1515#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
1516
1517/****************** Bit definition for DBGMCU_CR register *******************/
1518#define DBGMCU_CR_DBG_Pos (0U)
1519#define DBGMCU_CR_DBG_Msk (0x7U << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
1520#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
1521#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
1522#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
1523#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
1524#define DBGMCU_CR_DBG_STOP_Pos (1U)
1525#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
1526#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
1527#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
1528#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
1529#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
1530
1531/****************** Bit definition for DBGMCU_APB1_FZ register **************/
1532#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
1533#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
1534#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
1535#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
1536#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
1537#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
1538#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
1539#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
1540#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
1541#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
1542#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
1543#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
1544#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
1545#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
1546#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
1547#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
1548#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
1549#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
1550#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
1551#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
1552#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
1553#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
1554#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
1555#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
1556#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos (22U)
1557#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
1558#define DBGMCU_APB1_FZ_DBG_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
1559#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos (23U)
1560#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
1561#define DBGMCU_APB1_FZ_DBG_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
1562#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
1563#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
1564#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
1565/****************** Bit definition for DBGMCU_APB2_FZ register **************/
1566#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U)
1567#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
1568#define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
1569#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
1570#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
1571#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
1572
1573/******************************************************************************/
1574/* */
1575/* DMA Controller (DMA) */
1576/* */
1577/******************************************************************************/
1578
1579/******************* Bit definition for DMA_ISR register ********************/
1580#define DMA_ISR_GIF1_Pos (0U)
1581#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
1582#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
1583#define DMA_ISR_TCIF1_Pos (1U)
1584#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
1585#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
1586#define DMA_ISR_HTIF1_Pos (2U)
1587#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
1588#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
1589#define DMA_ISR_TEIF1_Pos (3U)
1590#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
1591#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
1592#define DMA_ISR_GIF2_Pos (4U)
1593#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
1594#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
1595#define DMA_ISR_TCIF2_Pos (5U)
1596#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
1597#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
1598#define DMA_ISR_HTIF2_Pos (6U)
1599#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
1600#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
1601#define DMA_ISR_TEIF2_Pos (7U)
1602#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
1603#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
1604#define DMA_ISR_GIF3_Pos (8U)
1605#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
1606#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
1607#define DMA_ISR_TCIF3_Pos (9U)
1608#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
1609#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
1610#define DMA_ISR_HTIF3_Pos (10U)
1611#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
1612#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
1613#define DMA_ISR_TEIF3_Pos (11U)
1614#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
1615#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
1616#define DMA_ISR_GIF4_Pos (12U)
1617#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
1618#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
1619#define DMA_ISR_TCIF4_Pos (13U)
1620#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
1621#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
1622#define DMA_ISR_HTIF4_Pos (14U)
1623#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
1624#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
1625#define DMA_ISR_TEIF4_Pos (15U)
1626#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
1627#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
1628#define DMA_ISR_GIF5_Pos (16U)
1629#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
1630#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
1631#define DMA_ISR_TCIF5_Pos (17U)
1632#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
1633#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
1634#define DMA_ISR_HTIF5_Pos (18U)
1635#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
1636#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
1637#define DMA_ISR_TEIF5_Pos (19U)
1638#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
1639#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
1640#define DMA_ISR_GIF6_Pos (20U)
1641#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
1642#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
1643#define DMA_ISR_TCIF6_Pos (21U)
1644#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
1645#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
1646#define DMA_ISR_HTIF6_Pos (22U)
1647#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
1648#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
1649#define DMA_ISR_TEIF6_Pos (23U)
1650#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
1651#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
1652#define DMA_ISR_GIF7_Pos (24U)
1653#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
1654#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
1655#define DMA_ISR_TCIF7_Pos (25U)
1656#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
1657#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
1658#define DMA_ISR_HTIF7_Pos (26U)
1659#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
1660#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
1661#define DMA_ISR_TEIF7_Pos (27U)
1662#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
1663#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
1664
1665/******************* Bit definition for DMA_IFCR register *******************/
1666#define DMA_IFCR_CGIF1_Pos (0U)
1667#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
1668#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
1669#define DMA_IFCR_CTCIF1_Pos (1U)
1670#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
1671#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
1672#define DMA_IFCR_CHTIF1_Pos (2U)
1673#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1674#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
1675#define DMA_IFCR_CTEIF1_Pos (3U)
1676#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
1677#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
1678#define DMA_IFCR_CGIF2_Pos (4U)
1679#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
1680#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
1681#define DMA_IFCR_CTCIF2_Pos (5U)
1682#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
1683#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
1684#define DMA_IFCR_CHTIF2_Pos (6U)
1685#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
1686#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
1687#define DMA_IFCR_CTEIF2_Pos (7U)
1688#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
1689#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
1690#define DMA_IFCR_CGIF3_Pos (8U)
1691#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
1692#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
1693#define DMA_IFCR_CTCIF3_Pos (9U)
1694#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
1695#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
1696#define DMA_IFCR_CHTIF3_Pos (10U)
1697#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
1698#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
1699#define DMA_IFCR_CTEIF3_Pos (11U)
1700#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
1701#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
1702#define DMA_IFCR_CGIF4_Pos (12U)
1703#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
1704#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
1705#define DMA_IFCR_CTCIF4_Pos (13U)
1706#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
1707#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
1708#define DMA_IFCR_CHTIF4_Pos (14U)
1709#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
1710#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
1711#define DMA_IFCR_CTEIF4_Pos (15U)
1712#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
1713#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
1714#define DMA_IFCR_CGIF5_Pos (16U)
1715#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
1716#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
1717#define DMA_IFCR_CTCIF5_Pos (17U)
1718#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
1719#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
1720#define DMA_IFCR_CHTIF5_Pos (18U)
1721#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
1722#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
1723#define DMA_IFCR_CTEIF5_Pos (19U)
1724#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
1725#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
1726#define DMA_IFCR_CGIF6_Pos (20U)
1727#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
1728#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
1729#define DMA_IFCR_CTCIF6_Pos (21U)
1730#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
1731#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
1732#define DMA_IFCR_CHTIF6_Pos (22U)
1733#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
1734#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
1735#define DMA_IFCR_CTEIF6_Pos (23U)
1736#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
1737#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
1738#define DMA_IFCR_CGIF7_Pos (24U)
1739#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
1740#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
1741#define DMA_IFCR_CTCIF7_Pos (25U)
1742#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
1743#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
1744#define DMA_IFCR_CHTIF7_Pos (26U)
1745#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
1746#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
1747#define DMA_IFCR_CTEIF7_Pos (27U)
1748#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
1749#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
1750
1751/******************* Bit definition for DMA_CCR register ********************/
1752#define DMA_CCR_EN_Pos (0U)
1753#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
1754#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
1755#define DMA_CCR_TCIE_Pos (1U)
1756#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
1757#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
1758#define DMA_CCR_HTIE_Pos (2U)
1759#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
1760#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
1761#define DMA_CCR_TEIE_Pos (3U)
1762#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
1763#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
1764#define DMA_CCR_DIR_Pos (4U)
1765#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
1766#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
1767#define DMA_CCR_CIRC_Pos (5U)
1768#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
1769#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
1770#define DMA_CCR_PINC_Pos (6U)
1771#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
1772#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
1773#define DMA_CCR_MINC_Pos (7U)
1774#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
1775#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
1776
1777#define DMA_CCR_PSIZE_Pos (8U)
1778#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
1779#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
1780#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
1781#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
1782
1783#define DMA_CCR_MSIZE_Pos (10U)
1784#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
1785#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
1786#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
1787#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
1788
1789#define DMA_CCR_PL_Pos (12U)
1790#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
1791#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
1792#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
1793#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
1794
1795#define DMA_CCR_MEM2MEM_Pos (14U)
1796#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
1797#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
1798
1799/****************** Bit definition for DMA_CNDTR register *******************/
1800#define DMA_CNDTR_NDT_Pos (0U)
1801#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
1802#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
1803
1804/****************** Bit definition for DMA_CPAR register ********************/
1805#define DMA_CPAR_PA_Pos (0U)
1806#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
1807#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
1808
1809/****************** Bit definition for DMA_CMAR register ********************/
1810#define DMA_CMAR_MA_Pos (0U)
1811#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
1812#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
1813
1814
1815/******************* Bit definition for DMA_CSELR register *******************/
1816#define DMA_CSELR_C1S_Pos (0U)
1817#define DMA_CSELR_C1S_Msk (0xFU << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
1818#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
1819#define DMA_CSELR_C2S_Pos (4U)
1820#define DMA_CSELR_C2S_Msk (0xFU << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
1821#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
1822#define DMA_CSELR_C3S_Pos (8U)
1823#define DMA_CSELR_C3S_Msk (0xFU << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
1824#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
1825#define DMA_CSELR_C4S_Pos (12U)
1826#define DMA_CSELR_C4S_Msk (0xFU << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
1827#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
1828#define DMA_CSELR_C5S_Pos (16U)
1829#define DMA_CSELR_C5S_Msk (0xFU << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
1830#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
1831#define DMA_CSELR_C6S_Pos (20U)
1832#define DMA_CSELR_C6S_Msk (0xFU << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
1833#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
1834#define DMA_CSELR_C7S_Pos (24U)
1835#define DMA_CSELR_C7S_Msk (0xFU << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
1836#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
1837
1838/******************************************************************************/
1839/* */
1840/* External Interrupt/Event Controller (EXTI) */
1841/* */
1842/******************************************************************************/
1843
1844/******************* Bit definition for EXTI_IMR register *******************/
1845#define EXTI_IMR_IM0_Pos (0U)
1846#define EXTI_IMR_IM0_Msk (0x1U << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
1847#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
1848#define EXTI_IMR_IM1_Pos (1U)
1849#define EXTI_IMR_IM1_Msk (0x1U << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
1850#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
1851#define EXTI_IMR_IM2_Pos (2U)
1852#define EXTI_IMR_IM2_Msk (0x1U << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
1853#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
1854#define EXTI_IMR_IM3_Pos (3U)
1855#define EXTI_IMR_IM3_Msk (0x1U << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
1856#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
1857#define EXTI_IMR_IM4_Pos (4U)
1858#define EXTI_IMR_IM4_Msk (0x1U << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
1859#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
1860#define EXTI_IMR_IM5_Pos (5U)
1861#define EXTI_IMR_IM5_Msk (0x1U << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
1862#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
1863#define EXTI_IMR_IM6_Pos (6U)
1864#define EXTI_IMR_IM6_Msk (0x1U << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
1865#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
1866#define EXTI_IMR_IM7_Pos (7U)
1867#define EXTI_IMR_IM7_Msk (0x1U << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
1868#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
1869#define EXTI_IMR_IM8_Pos (8U)
1870#define EXTI_IMR_IM8_Msk (0x1U << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
1871#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
1872#define EXTI_IMR_IM9_Pos (9U)
1873#define EXTI_IMR_IM9_Msk (0x1U << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
1874#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
1875#define EXTI_IMR_IM10_Pos (10U)
1876#define EXTI_IMR_IM10_Msk (0x1U << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
1877#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
1878#define EXTI_IMR_IM11_Pos (11U)
1879#define EXTI_IMR_IM11_Msk (0x1U << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
1880#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
1881#define EXTI_IMR_IM12_Pos (12U)
1882#define EXTI_IMR_IM12_Msk (0x1U << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
1883#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
1884#define EXTI_IMR_IM13_Pos (13U)
1885#define EXTI_IMR_IM13_Msk (0x1U << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
1886#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
1887#define EXTI_IMR_IM14_Pos (14U)
1888#define EXTI_IMR_IM14_Msk (0x1U << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
1889#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
1890#define EXTI_IMR_IM15_Pos (15U)
1891#define EXTI_IMR_IM15_Msk (0x1U << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
1892#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
1893#define EXTI_IMR_IM16_Pos (16U)
1894#define EXTI_IMR_IM16_Msk (0x1U << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */
1895#define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */
1896#define EXTI_IMR_IM17_Pos (17U)
1897#define EXTI_IMR_IM17_Msk (0x1U << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
1898#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
1899#define EXTI_IMR_IM18_Pos (18U)
1900#define EXTI_IMR_IM18_Msk (0x1U << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */
1901#define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */
1902#define EXTI_IMR_IM19_Pos (19U)
1903#define EXTI_IMR_IM19_Msk (0x1U << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
1904#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
1905#define EXTI_IMR_IM20_Pos (20U)
1906#define EXTI_IMR_IM20_Msk (0x1U << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
1907#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
1908#define EXTI_IMR_IM21_Pos (21U)
1909#define EXTI_IMR_IM21_Msk (0x1U << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */
1910#define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */
1911#define EXTI_IMR_IM22_Pos (22U)
1912#define EXTI_IMR_IM22_Msk (0x1U << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */
1913#define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */
1914#define EXTI_IMR_IM23_Pos (23U)
1915#define EXTI_IMR_IM23_Msk (0x1U << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
1916#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
1917#define EXTI_IMR_IM24_Pos (24U)
1918#define EXTI_IMR_IM24_Msk (0x1U << EXTI_IMR_IM24_Pos) /*!< 0x01000000 */
1919#define EXTI_IMR_IM24 EXTI_IMR_IM24_Msk /*!< Interrupt Mask on line 24 */
1920#define EXTI_IMR_IM25_Pos (25U)
1921#define EXTI_IMR_IM25_Msk (0x1U << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */
1922#define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */
1923#define EXTI_IMR_IM26_Pos (26U)
1924#define EXTI_IMR_IM26_Msk (0x1U << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
1925#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
1926#define EXTI_IMR_IM28_Pos (28U)
1927#define EXTI_IMR_IM28_Msk (0x1U << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
1928#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
1929#define EXTI_IMR_IM29_Pos (29U)
1930#define EXTI_IMR_IM29_Msk (0x1U << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
1931#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
1932
1933#define EXTI_IMR_IM_Pos (0U)
1934#define EXTI_IMR_IM_Msk (0x37FFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x37FFFFFF */
1935#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
1936
1937/****************** Bit definition for EXTI_EMR register ********************/
1938#define EXTI_EMR_EM0_Pos (0U)
1939#define EXTI_EMR_EM0_Msk (0x1U << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
1940#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
1941#define EXTI_EMR_EM1_Pos (1U)
1942#define EXTI_EMR_EM1_Msk (0x1U << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
1943#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
1944#define EXTI_EMR_EM2_Pos (2U)
1945#define EXTI_EMR_EM2_Msk (0x1U << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
1946#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
1947#define EXTI_EMR_EM3_Pos (3U)
1948#define EXTI_EMR_EM3_Msk (0x1U << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
1949#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
1950#define EXTI_EMR_EM4_Pos (4U)
1951#define EXTI_EMR_EM4_Msk (0x1U << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
1952#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
1953#define EXTI_EMR_EM5_Pos (5U)
1954#define EXTI_EMR_EM5_Msk (0x1U << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
1955#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
1956#define EXTI_EMR_EM6_Pos (6U)
1957#define EXTI_EMR_EM6_Msk (0x1U << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
1958#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
1959#define EXTI_EMR_EM7_Pos (7U)
1960#define EXTI_EMR_EM7_Msk (0x1U << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
1961#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
1962#define EXTI_EMR_EM8_Pos (8U)
1963#define EXTI_EMR_EM8_Msk (0x1U << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
1964#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
1965#define EXTI_EMR_EM9_Pos (9U)
1966#define EXTI_EMR_EM9_Msk (0x1U << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
1967#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
1968#define EXTI_EMR_EM10_Pos (10U)
1969#define EXTI_EMR_EM10_Msk (0x1U << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
1970#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
1971#define EXTI_EMR_EM11_Pos (11U)
1972#define EXTI_EMR_EM11_Msk (0x1U << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
1973#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
1974#define EXTI_EMR_EM12_Pos (12U)
1975#define EXTI_EMR_EM12_Msk (0x1U << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
1976#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
1977#define EXTI_EMR_EM13_Pos (13U)
1978#define EXTI_EMR_EM13_Msk (0x1U << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
1979#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
1980#define EXTI_EMR_EM14_Pos (14U)
1981#define EXTI_EMR_EM14_Msk (0x1U << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
1982#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
1983#define EXTI_EMR_EM15_Pos (15U)
1984#define EXTI_EMR_EM15_Msk (0x1U << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
1985#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
1986#define EXTI_EMR_EM16_Pos (16U)
1987#define EXTI_EMR_EM16_Msk (0x1U << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */
1988#define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */
1989#define EXTI_EMR_EM17_Pos (17U)
1990#define EXTI_EMR_EM17_Msk (0x1U << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
1991#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
1992#define EXTI_EMR_EM18_Pos (18U)
1993#define EXTI_EMR_EM18_Msk (0x1U << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */
1994#define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */
1995#define EXTI_EMR_EM19_Pos (19U)
1996#define EXTI_EMR_EM19_Msk (0x1U << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
1997#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
1998#define EXTI_EMR_EM20_Pos (20U)
1999#define EXTI_EMR_EM20_Msk (0x1U << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
2000#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
2001#define EXTI_EMR_EM21_Pos (21U)
2002#define EXTI_EMR_EM21_Msk (0x1U << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */
2003#define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */
2004#define EXTI_EMR_EM22_Pos (22U)
2005#define EXTI_EMR_EM22_Msk (0x1U << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */
2006#define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */
2007#define EXTI_EMR_EM23_Pos (23U)
2008#define EXTI_EMR_EM23_Msk (0x1U << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
2009#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
2010#define EXTI_EMR_EM24_Pos (24U)
2011#define EXTI_EMR_EM24_Msk (0x1U << EXTI_EMR_EM24_Pos) /*!< 0x01000000 */
2012#define EXTI_EMR_EM24 EXTI_EMR_EM24_Msk /*!< Event Mask on line 24 */
2013#define EXTI_EMR_EM25_Pos (25U)
2014#define EXTI_EMR_EM25_Msk (0x1U << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */
2015#define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */
2016#define EXTI_EMR_EM26_Pos (26U)
2017#define EXTI_EMR_EM26_Msk (0x1U << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
2018#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
2019#define EXTI_EMR_EM28_Pos (28U)
2020#define EXTI_EMR_EM28_Msk (0x1U << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
2021#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
2022#define EXTI_EMR_EM29_Pos (29U)
2023#define EXTI_EMR_EM29_Msk (0x1U << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
2024#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
2025
2026/******************* Bit definition for EXTI_RTSR register ******************/
2027#define EXTI_RTSR_RT0_Pos (0U)
2028#define EXTI_RTSR_RT0_Msk (0x1U << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
2029#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
2030#define EXTI_RTSR_RT1_Pos (1U)
2031#define EXTI_RTSR_RT1_Msk (0x1U << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
2032#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
2033#define EXTI_RTSR_RT2_Pos (2U)
2034#define EXTI_RTSR_RT2_Msk (0x1U << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
2035#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
2036#define EXTI_RTSR_RT3_Pos (3U)
2037#define EXTI_RTSR_RT3_Msk (0x1U << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
2038#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
2039#define EXTI_RTSR_RT4_Pos (4U)
2040#define EXTI_RTSR_RT4_Msk (0x1U << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
2041#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
2042#define EXTI_RTSR_RT5_Pos (5U)
2043#define EXTI_RTSR_RT5_Msk (0x1U << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
2044#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
2045#define EXTI_RTSR_RT6_Pos (6U)
2046#define EXTI_RTSR_RT6_Msk (0x1U << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
2047#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
2048#define EXTI_RTSR_RT7_Pos (7U)
2049#define EXTI_RTSR_RT7_Msk (0x1U << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
2050#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
2051#define EXTI_RTSR_RT8_Pos (8U)
2052#define EXTI_RTSR_RT8_Msk (0x1U << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
2053#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
2054#define EXTI_RTSR_RT9_Pos (9U)
2055#define EXTI_RTSR_RT9_Msk (0x1U << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
2056#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
2057#define EXTI_RTSR_RT10_Pos (10U)
2058#define EXTI_RTSR_RT10_Msk (0x1U << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
2059#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
2060#define EXTI_RTSR_RT11_Pos (11U)
2061#define EXTI_RTSR_RT11_Msk (0x1U << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
2062#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
2063#define EXTI_RTSR_RT12_Pos (12U)
2064#define EXTI_RTSR_RT12_Msk (0x1U << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
2065#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
2066#define EXTI_RTSR_RT13_Pos (13U)
2067#define EXTI_RTSR_RT13_Msk (0x1U << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
2068#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
2069#define EXTI_RTSR_RT14_Pos (14U)
2070#define EXTI_RTSR_RT14_Msk (0x1U << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
2071#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
2072#define EXTI_RTSR_RT15_Pos (15U)
2073#define EXTI_RTSR_RT15_Msk (0x1U << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
2074#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
2075#define EXTI_RTSR_RT16_Pos (16U)
2076#define EXTI_RTSR_RT16_Msk (0x1U << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
2077#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
2078#define EXTI_RTSR_RT17_Pos (17U)
2079#define EXTI_RTSR_RT17_Msk (0x1U << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
2080#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
2081#define EXTI_RTSR_RT19_Pos (19U)
2082#define EXTI_RTSR_RT19_Msk (0x1U << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
2083#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
2084#define EXTI_RTSR_RT20_Pos (20U)
2085#define EXTI_RTSR_RT20_Msk (0x1U << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
2086#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
2087#define EXTI_RTSR_RT21_Pos (21U)
2088#define EXTI_RTSR_RT21_Msk (0x1U << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
2089#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
2090#define EXTI_RTSR_RT22_Pos (22U)
2091#define EXTI_RTSR_RT22_Msk (0x1U << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
2092#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
2093
2094/* Legacy defines */
2095#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
2096#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
2097#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
2098#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
2099#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
2100#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
2101#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
2102#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
2103#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
2104#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
2105#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
2106#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
2107#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
2108#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
2109#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
2110#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
2111#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
2112#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
2113#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
2114#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
2115#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
2116#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
2117
2118/******************* Bit definition for EXTI_FTSR register *******************/
2119#define EXTI_FTSR_FT0_Pos (0U)
2120#define EXTI_FTSR_FT0_Msk (0x1U << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
2121#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
2122#define EXTI_FTSR_FT1_Pos (1U)
2123#define EXTI_FTSR_FT1_Msk (0x1U << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
2124#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
2125#define EXTI_FTSR_FT2_Pos (2U)
2126#define EXTI_FTSR_FT2_Msk (0x1U << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
2127#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
2128#define EXTI_FTSR_FT3_Pos (3U)
2129#define EXTI_FTSR_FT3_Msk (0x1U << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
2130#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
2131#define EXTI_FTSR_FT4_Pos (4U)
2132#define EXTI_FTSR_FT4_Msk (0x1U << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
2133#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
2134#define EXTI_FTSR_FT5_Pos (5U)
2135#define EXTI_FTSR_FT5_Msk (0x1U << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
2136#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
2137#define EXTI_FTSR_FT6_Pos (6U)
2138#define EXTI_FTSR_FT6_Msk (0x1U << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
2139#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
2140#define EXTI_FTSR_FT7_Pos (7U)
2141#define EXTI_FTSR_FT7_Msk (0x1U << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
2142#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
2143#define EXTI_FTSR_FT8_Pos (8U)
2144#define EXTI_FTSR_FT8_Msk (0x1U << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
2145#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
2146#define EXTI_FTSR_FT9_Pos (9U)
2147#define EXTI_FTSR_FT9_Msk (0x1U << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
2148#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
2149#define EXTI_FTSR_FT10_Pos (10U)
2150#define EXTI_FTSR_FT10_Msk (0x1U << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
2151#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
2152#define EXTI_FTSR_FT11_Pos (11U)
2153#define EXTI_FTSR_FT11_Msk (0x1U << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
2154#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
2155#define EXTI_FTSR_FT12_Pos (12U)
2156#define EXTI_FTSR_FT12_Msk (0x1U << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
2157#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
2158#define EXTI_FTSR_FT13_Pos (13U)
2159#define EXTI_FTSR_FT13_Msk (0x1U << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
2160#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
2161#define EXTI_FTSR_FT14_Pos (14U)
2162#define EXTI_FTSR_FT14_Msk (0x1U << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
2163#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
2164#define EXTI_FTSR_FT15_Pos (15U)
2165#define EXTI_FTSR_FT15_Msk (0x1U << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
2166#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
2167#define EXTI_FTSR_FT16_Pos (16U)
2168#define EXTI_FTSR_FT16_Msk (0x1U << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
2169#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
2170#define EXTI_FTSR_FT17_Pos (17U)
2171#define EXTI_FTSR_FT17_Msk (0x1U << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
2172#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
2173#define EXTI_FTSR_FT19_Pos (19U)
2174#define EXTI_FTSR_FT19_Msk (0x1U << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
2175#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
2176#define EXTI_FTSR_FT20_Pos (20U)
2177#define EXTI_FTSR_FT20_Msk (0x1U << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
2178#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
2179#define EXTI_FTSR_FT21_Pos (21U)
2180#define EXTI_FTSR_FT21_Msk (0x1U << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
2181#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
2182#define EXTI_FTSR_FT22_Pos (22U)
2183#define EXTI_FTSR_FT22_Msk (0x1U << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
2184#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
2185
2186/* Legacy defines */
2187#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
2188#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
2189#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
2190#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
2191#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
2192#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
2193#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
2194#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
2195#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
2196#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
2197#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
2198#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
2199#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
2200#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
2201#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
2202#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
2203#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
2204#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
2205#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
2206#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
2207#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
2208#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
2209
2210/******************* Bit definition for EXTI_SWIER register *******************/
2211#define EXTI_SWIER_SWI0_Pos (0U)
2212#define EXTI_SWIER_SWI0_Msk (0x1U << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
2213#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
2214#define EXTI_SWIER_SWI1_Pos (1U)
2215#define EXTI_SWIER_SWI1_Msk (0x1U << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
2216#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
2217#define EXTI_SWIER_SWI2_Pos (2U)
2218#define EXTI_SWIER_SWI2_Msk (0x1U << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
2219#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
2220#define EXTI_SWIER_SWI3_Pos (3U)
2221#define EXTI_SWIER_SWI3_Msk (0x1U << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
2222#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
2223#define EXTI_SWIER_SWI4_Pos (4U)
2224#define EXTI_SWIER_SWI4_Msk (0x1U << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
2225#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
2226#define EXTI_SWIER_SWI5_Pos (5U)
2227#define EXTI_SWIER_SWI5_Msk (0x1U << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
2228#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
2229#define EXTI_SWIER_SWI6_Pos (6U)
2230#define EXTI_SWIER_SWI6_Msk (0x1U << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
2231#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
2232#define EXTI_SWIER_SWI7_Pos (7U)
2233#define EXTI_SWIER_SWI7_Msk (0x1U << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
2234#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
2235#define EXTI_SWIER_SWI8_Pos (8U)
2236#define EXTI_SWIER_SWI8_Msk (0x1U << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
2237#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
2238#define EXTI_SWIER_SWI9_Pos (9U)
2239#define EXTI_SWIER_SWI9_Msk (0x1U << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
2240#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
2241#define EXTI_SWIER_SWI10_Pos (10U)
2242#define EXTI_SWIER_SWI10_Msk (0x1U << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
2243#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
2244#define EXTI_SWIER_SWI11_Pos (11U)
2245#define EXTI_SWIER_SWI11_Msk (0x1U << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
2246#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
2247#define EXTI_SWIER_SWI12_Pos (12U)
2248#define EXTI_SWIER_SWI12_Msk (0x1U << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
2249#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
2250#define EXTI_SWIER_SWI13_Pos (13U)
2251#define EXTI_SWIER_SWI13_Msk (0x1U << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
2252#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
2253#define EXTI_SWIER_SWI14_Pos (14U)
2254#define EXTI_SWIER_SWI14_Msk (0x1U << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
2255#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
2256#define EXTI_SWIER_SWI15_Pos (15U)
2257#define EXTI_SWIER_SWI15_Msk (0x1U << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
2258#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
2259#define EXTI_SWIER_SWI16_Pos (16U)
2260#define EXTI_SWIER_SWI16_Msk (0x1U << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
2261#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
2262#define EXTI_SWIER_SWI17_Pos (17U)
2263#define EXTI_SWIER_SWI17_Msk (0x1U << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
2264#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
2265#define EXTI_SWIER_SWI19_Pos (19U)
2266#define EXTI_SWIER_SWI19_Msk (0x1U << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
2267#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
2268#define EXTI_SWIER_SWI20_Pos (20U)
2269#define EXTI_SWIER_SWI20_Msk (0x1U << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
2270#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
2271#define EXTI_SWIER_SWI21_Pos (21U)
2272#define EXTI_SWIER_SWI21_Msk (0x1U << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
2273#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
2274#define EXTI_SWIER_SWI22_Pos (22U)
2275#define EXTI_SWIER_SWI22_Msk (0x1U << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
2276#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
2277
2278/* Legacy defines */
2279#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
2280#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
2281#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
2282#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
2283#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
2284#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
2285#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
2286#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
2287#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
2288#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
2289#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
2290#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
2291#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
2292#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
2293#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
2294#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
2295#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
2296#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
2297#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
2298#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
2299#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
2300#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
2301
2302/****************** Bit definition for EXTI_PR register *********************/
2303#define EXTI_PR_PIF0_Pos (0U)
2304#define EXTI_PR_PIF0_Msk (0x1U << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
2305#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
2306#define EXTI_PR_PIF1_Pos (1U)
2307#define EXTI_PR_PIF1_Msk (0x1U << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
2308#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
2309#define EXTI_PR_PIF2_Pos (2U)
2310#define EXTI_PR_PIF2_Msk (0x1U << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
2311#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
2312#define EXTI_PR_PIF3_Pos (3U)
2313#define EXTI_PR_PIF3_Msk (0x1U << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
2314#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
2315#define EXTI_PR_PIF4_Pos (4U)
2316#define EXTI_PR_PIF4_Msk (0x1U << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
2317#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
2318#define EXTI_PR_PIF5_Pos (5U)
2319#define EXTI_PR_PIF5_Msk (0x1U << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
2320#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
2321#define EXTI_PR_PIF6_Pos (6U)
2322#define EXTI_PR_PIF6_Msk (0x1U << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
2323#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
2324#define EXTI_PR_PIF7_Pos (7U)
2325#define EXTI_PR_PIF7_Msk (0x1U << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
2326#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
2327#define EXTI_PR_PIF8_Pos (8U)
2328#define EXTI_PR_PIF8_Msk (0x1U << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
2329#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
2330#define EXTI_PR_PIF9_Pos (9U)
2331#define EXTI_PR_PIF9_Msk (0x1U << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
2332#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
2333#define EXTI_PR_PIF10_Pos (10U)
2334#define EXTI_PR_PIF10_Msk (0x1U << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
2335#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
2336#define EXTI_PR_PIF11_Pos (11U)
2337#define EXTI_PR_PIF11_Msk (0x1U << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
2338#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
2339#define EXTI_PR_PIF12_Pos (12U)
2340#define EXTI_PR_PIF12_Msk (0x1U << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
2341#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
2342#define EXTI_PR_PIF13_Pos (13U)
2343#define EXTI_PR_PIF13_Msk (0x1U << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
2344#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
2345#define EXTI_PR_PIF14_Pos (14U)
2346#define EXTI_PR_PIF14_Msk (0x1U << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
2347#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
2348#define EXTI_PR_PIF15_Pos (15U)
2349#define EXTI_PR_PIF15_Msk (0x1U << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
2350#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
2351#define EXTI_PR_PIF16_Pos (16U)
2352#define EXTI_PR_PIF16_Msk (0x1U << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
2353#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
2354#define EXTI_PR_PIF17_Pos (17U)
2355#define EXTI_PR_PIF17_Msk (0x1U << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
2356#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
2357#define EXTI_PR_PIF19_Pos (19U)
2358#define EXTI_PR_PIF19_Msk (0x1U << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
2359#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
2360#define EXTI_PR_PIF20_Pos (20U)
2361#define EXTI_PR_PIF20_Msk (0x1U << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
2362#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
2363#define EXTI_PR_PIF21_Pos (21U)
2364#define EXTI_PR_PIF21_Msk (0x1U << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
2365#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
2366#define EXTI_PR_PIF22_Pos (22U)
2367#define EXTI_PR_PIF22_Msk (0x1U << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
2368#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
2369
2370/* Legacy defines */
2371#define EXTI_PR_PR0 EXTI_PR_PIF0
2372#define EXTI_PR_PR1 EXTI_PR_PIF1
2373#define EXTI_PR_PR2 EXTI_PR_PIF2
2374#define EXTI_PR_PR3 EXTI_PR_PIF3
2375#define EXTI_PR_PR4 EXTI_PR_PIF4
2376#define EXTI_PR_PR5 EXTI_PR_PIF5
2377#define EXTI_PR_PR6 EXTI_PR_PIF6
2378#define EXTI_PR_PR7 EXTI_PR_PIF7
2379#define EXTI_PR_PR8 EXTI_PR_PIF8
2380#define EXTI_PR_PR9 EXTI_PR_PIF9
2381#define EXTI_PR_PR10 EXTI_PR_PIF10
2382#define EXTI_PR_PR11 EXTI_PR_PIF11
2383#define EXTI_PR_PR12 EXTI_PR_PIF12
2384#define EXTI_PR_PR13 EXTI_PR_PIF13
2385#define EXTI_PR_PR14 EXTI_PR_PIF14
2386#define EXTI_PR_PR15 EXTI_PR_PIF15
2387#define EXTI_PR_PR16 EXTI_PR_PIF16
2388#define EXTI_PR_PR17 EXTI_PR_PIF17
2389#define EXTI_PR_PR19 EXTI_PR_PIF19
2390#define EXTI_PR_PR20 EXTI_PR_PIF20
2391#define EXTI_PR_PR21 EXTI_PR_PIF21
2392#define EXTI_PR_PR22 EXTI_PR_PIF22
2393
2394/******************************************************************************/
2395/* */
2396/* FLASH and Option Bytes Registers */
2397/* */
2398/******************************************************************************/
2399
2400/******************* Bit definition for FLASH_ACR register ******************/
2401#define FLASH_ACR_LATENCY_Pos (0U)
2402#define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
2403#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
2404#define FLASH_ACR_PRFTEN_Pos (1U)
2405#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
2406#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
2407#define FLASH_ACR_SLEEP_PD_Pos (3U)
2408#define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
2409#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
2410#define FLASH_ACR_RUN_PD_Pos (4U)
2411#define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
2412#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
2413#define FLASH_ACR_DISAB_BUF_Pos (5U)
2414#define FLASH_ACR_DISAB_BUF_Msk (0x1U << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
2415#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
2416#define FLASH_ACR_PRE_READ_Pos (6U)
2417#define FLASH_ACR_PRE_READ_Msk (0x1U << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
2418#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
2419
2420/******************* Bit definition for FLASH_PECR register ******************/
2421#define FLASH_PECR_PELOCK_Pos (0U)
2422#define FLASH_PECR_PELOCK_Msk (0x1U << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
2423#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
2424#define FLASH_PECR_PRGLOCK_Pos (1U)
2425#define FLASH_PECR_PRGLOCK_Msk (0x1U << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
2426#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
2427#define FLASH_PECR_OPTLOCK_Pos (2U)
2428#define FLASH_PECR_OPTLOCK_Msk (0x1U << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
2429#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
2430#define FLASH_PECR_PROG_Pos (3U)
2431#define FLASH_PECR_PROG_Msk (0x1U << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
2432#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
2433#define FLASH_PECR_DATA_Pos (4U)
2434#define FLASH_PECR_DATA_Msk (0x1U << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
2435#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
2436#define FLASH_PECR_FIX_Pos (8U)
2437#define FLASH_PECR_FIX_Msk (0x1U << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
2438#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
2439#define FLASH_PECR_ERASE_Pos (9U)
2440#define FLASH_PECR_ERASE_Msk (0x1U << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
2441#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
2442#define FLASH_PECR_FPRG_Pos (10U)
2443#define FLASH_PECR_FPRG_Msk (0x1U << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
2444#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
2445#define FLASH_PECR_PARALLBANK_Pos (15U)
2446#define FLASH_PECR_PARALLBANK_Msk (0x1U << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */
2447#define FLASH_PECR_PARALLBANK FLASH_PECR_PARALLBANK_Msk /*!< Parallel Bank mode */
2448#define FLASH_PECR_EOPIE_Pos (16U)
2449#define FLASH_PECR_EOPIE_Msk (0x1U << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
2450#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
2451#define FLASH_PECR_ERRIE_Pos (17U)
2452#define FLASH_PECR_ERRIE_Msk (0x1U << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
2453#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
2454#define FLASH_PECR_OBL_LAUNCH_Pos (18U)
2455#define FLASH_PECR_OBL_LAUNCH_Msk (0x1U << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
2456#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
2457#define FLASH_PECR_HALF_ARRAY_Pos (19U)
2458#define FLASH_PECR_HALF_ARRAY_Msk (0x1U << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
2459#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
2460#define FLASH_PECR_NZDISABLE_Pos (22U)
2461#define FLASH_PECR_NZDISABLE_Msk (0x1U << FLASH_PECR_NZDISABLE_Pos) /*!< 0x00400000 */
2462#define FLASH_PECR_NZDISABLE FLASH_PECR_NZDISABLE_Msk /*!< Non-Zero check disable */
2463
2464/****************** Bit definition for FLASH_PDKEYR register ******************/
2465#define FLASH_PDKEYR_PDKEYR_Pos (0U)
2466#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
2467#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
2468
2469/****************** Bit definition for FLASH_PEKEYR register ******************/
2470#define FLASH_PEKEYR_PEKEYR_Pos (0U)
2471#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
2472#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
2473
2474/****************** Bit definition for FLASH_PRGKEYR register ******************/
2475#define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
2476#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
2477#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
2478
2479/****************** Bit definition for FLASH_OPTKEYR register ******************/
2480#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
2481#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
2482#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
2483
2484/****************** Bit definition for FLASH_SR register *******************/
2485#define FLASH_SR_BSY_Pos (0U)
2486#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
2487#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
2488#define FLASH_SR_EOP_Pos (1U)
2489#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
2490#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
2491#define FLASH_SR_HVOFF_Pos (2U)
2492#define FLASH_SR_HVOFF_Msk (0x1U << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
2493#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
2494#define FLASH_SR_READY_Pos (3U)
2495#define FLASH_SR_READY_Msk (0x1U << FLASH_SR_READY_Pos) /*!< 0x00000008 */
2496#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
2497
2498#define FLASH_SR_WRPERR_Pos (8U)
2499#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
2500#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
2501#define FLASH_SR_PGAERR_Pos (9U)
2502#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
2503#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
2504#define FLASH_SR_SIZERR_Pos (10U)
2505#define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
2506#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
2507#define FLASH_SR_OPTVERR_Pos (11U)
2508#define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
2509#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
2510#define FLASH_SR_RDERR_Pos (13U)
2511#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
2512#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
2513#define FLASH_SR_NOTZEROERR_Pos (16U)
2514#define FLASH_SR_NOTZEROERR_Msk (0x1U << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
2515#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
2516#define FLASH_SR_FWWERR_Pos (17U)
2517#define FLASH_SR_FWWERR_Msk (0x1U << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
2518#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
2519
2520/* Legacy defines */
2521#define FLASH_SR_FWWER FLASH_SR_FWWERR
2522#define FLASH_SR_ENHV FLASH_SR_HVOFF
2523#define FLASH_SR_ENDHV FLASH_SR_HVOFF
2524
2525/****************** Bit definition for FLASH_OPTR register *******************/
2526#define FLASH_OPTR_RDPROT_Pos (0U)
2527#define FLASH_OPTR_RDPROT_Msk (0xFFU << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
2528#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
2529#define FLASH_OPTR_WPRMOD_Pos (8U)
2530#define FLASH_OPTR_WPRMOD_Msk (0x1U << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
2531#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
2532#define FLASH_OPTR_BOR_LEV_Pos (16U)
2533#define FLASH_OPTR_BOR_LEV_Msk (0xFU << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
2534#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
2535#define FLASH_OPTR_IWDG_SW_Pos (20U)
2536#define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
2537#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
2538#define FLASH_OPTR_nRST_STOP_Pos (21U)
2539#define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
2540#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
2541#define FLASH_OPTR_nRST_STDBY_Pos (22U)
2542#define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
2543#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
2544#define FLASH_OPTR_BFB2_Pos (23U)
2545#define FLASH_OPTR_BFB2_Msk (0x1U << FLASH_OPTR_BFB2_Pos) /*!< 0x00800000 */
2546#define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk /*!< BFB2 */
2547#define FLASH_OPTR_USER_Pos (20U)
2548#define FLASH_OPTR_USER_Msk (0x7U << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
2549#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
2550#define FLASH_OPTR_BOOT1_Pos (31U)
2551#define FLASH_OPTR_BOOT1_Msk (0x1U << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
2552#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
2553
2554/****************** Bit definition for FLASH_WRPR register ******************/
2555#define FLASH_WRPR_WRP_Pos (0U)
2556#define FLASH_WRPR_WRP_Msk (0xFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
2557#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
2558
2559/******************************************************************************/
2560/* */
2561/* General Purpose IOs (GPIO) */
2562/* */
2563/******************************************************************************/
2564/******************* Bit definition for GPIO_MODER register *****************/
2565#define GPIO_MODER_MODE0_Pos (0U)
2566#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
2567#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
2568#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
2569#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
2570#define GPIO_MODER_MODE1_Pos (2U)
2571#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
2572#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
2573#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
2574#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
2575#define GPIO_MODER_MODE2_Pos (4U)
2576#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
2577#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
2578#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
2579#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
2580#define GPIO_MODER_MODE3_Pos (6U)
2581#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
2582#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
2583#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
2584#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
2585#define GPIO_MODER_MODE4_Pos (8U)
2586#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
2587#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
2588#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
2589#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
2590#define GPIO_MODER_MODE5_Pos (10U)
2591#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
2592#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
2593#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
2594#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
2595#define GPIO_MODER_MODE6_Pos (12U)
2596#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
2597#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
2598#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
2599#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
2600#define GPIO_MODER_MODE7_Pos (14U)
2601#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
2602#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
2603#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
2604#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
2605#define GPIO_MODER_MODE8_Pos (16U)
2606#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
2607#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
2608#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
2609#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
2610#define GPIO_MODER_MODE9_Pos (18U)
2611#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
2612#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
2613#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
2614#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
2615#define GPIO_MODER_MODE10_Pos (20U)
2616#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
2617#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
2618#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
2619#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
2620#define GPIO_MODER_MODE11_Pos (22U)
2621#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
2622#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
2623#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
2624#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
2625#define GPIO_MODER_MODE12_Pos (24U)
2626#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
2627#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
2628#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
2629#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
2630#define GPIO_MODER_MODE13_Pos (26U)
2631#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
2632#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
2633#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
2634#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
2635#define GPIO_MODER_MODE14_Pos (28U)
2636#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
2637#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
2638#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
2639#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
2640#define GPIO_MODER_MODE15_Pos (30U)
2641#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
2642#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
2643#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
2644#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
2645
2646/****************** Bit definition for GPIO_OTYPER register *****************/
2647#define GPIO_OTYPER_OT_0 (0x00000001U)
2648#define GPIO_OTYPER_OT_1 (0x00000002U)
2649#define GPIO_OTYPER_OT_2 (0x00000004U)
2650#define GPIO_OTYPER_OT_3 (0x00000008U)
2651#define GPIO_OTYPER_OT_4 (0x00000010U)
2652#define GPIO_OTYPER_OT_5 (0x00000020U)
2653#define GPIO_OTYPER_OT_6 (0x00000040U)
2654#define GPIO_OTYPER_OT_7 (0x00000080U)
2655#define GPIO_OTYPER_OT_8 (0x00000100U)
2656#define GPIO_OTYPER_OT_9 (0x00000200U)
2657#define GPIO_OTYPER_OT_10 (0x00000400U)
2658#define GPIO_OTYPER_OT_11 (0x00000800U)
2659#define GPIO_OTYPER_OT_12 (0x00001000U)
2660#define GPIO_OTYPER_OT_13 (0x00002000U)
2661#define GPIO_OTYPER_OT_14 (0x00004000U)
2662#define GPIO_OTYPER_OT_15 (0x00008000U)
2663
2664/**************** Bit definition for GPIO_OSPEEDR register ******************/
2665#define GPIO_OSPEEDER_OSPEED0_Pos (0U)
2666#define GPIO_OSPEEDER_OSPEED0_Msk (0x3U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
2667#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
2668#define GPIO_OSPEEDER_OSPEED0_0 (0x1U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
2669#define GPIO_OSPEEDER_OSPEED0_1 (0x2U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
2670#define GPIO_OSPEEDER_OSPEED1_Pos (2U)
2671#define GPIO_OSPEEDER_OSPEED1_Msk (0x3U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
2672#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
2673#define GPIO_OSPEEDER_OSPEED1_0 (0x1U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
2674#define GPIO_OSPEEDER_OSPEED1_1 (0x2U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
2675#define GPIO_OSPEEDER_OSPEED2_Pos (4U)
2676#define GPIO_OSPEEDER_OSPEED2_Msk (0x3U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
2677#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
2678#define GPIO_OSPEEDER_OSPEED2_0 (0x1U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
2679#define GPIO_OSPEEDER_OSPEED2_1 (0x2U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
2680#define GPIO_OSPEEDER_OSPEED3_Pos (6U)
2681#define GPIO_OSPEEDER_OSPEED3_Msk (0x3U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
2682#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
2683#define GPIO_OSPEEDER_OSPEED3_0 (0x1U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
2684#define GPIO_OSPEEDER_OSPEED3_1 (0x2U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
2685#define GPIO_OSPEEDER_OSPEED4_Pos (8U)
2686#define GPIO_OSPEEDER_OSPEED4_Msk (0x3U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
2687#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
2688#define GPIO_OSPEEDER_OSPEED4_0 (0x1U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
2689#define GPIO_OSPEEDER_OSPEED4_1 (0x2U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
2690#define GPIO_OSPEEDER_OSPEED5_Pos (10U)
2691#define GPIO_OSPEEDER_OSPEED5_Msk (0x3U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
2692#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
2693#define GPIO_OSPEEDER_OSPEED5_0 (0x1U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
2694#define GPIO_OSPEEDER_OSPEED5_1 (0x2U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
2695#define GPIO_OSPEEDER_OSPEED6_Pos (12U)
2696#define GPIO_OSPEEDER_OSPEED6_Msk (0x3U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
2697#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
2698#define GPIO_OSPEEDER_OSPEED6_0 (0x1U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
2699#define GPIO_OSPEEDER_OSPEED6_1 (0x2U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
2700#define GPIO_OSPEEDER_OSPEED7_Pos (14U)
2701#define GPIO_OSPEEDER_OSPEED7_Msk (0x3U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
2702#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
2703#define GPIO_OSPEEDER_OSPEED7_0 (0x1U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
2704#define GPIO_OSPEEDER_OSPEED7_1 (0x2U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
2705#define GPIO_OSPEEDER_OSPEED8_Pos (16U)
2706#define GPIO_OSPEEDER_OSPEED8_Msk (0x3U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
2707#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
2708#define GPIO_OSPEEDER_OSPEED8_0 (0x1U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
2709#define GPIO_OSPEEDER_OSPEED8_1 (0x2U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
2710#define GPIO_OSPEEDER_OSPEED9_Pos (18U)
2711#define GPIO_OSPEEDER_OSPEED9_Msk (0x3U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
2712#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
2713#define GPIO_OSPEEDER_OSPEED9_0 (0x1U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
2714#define GPIO_OSPEEDER_OSPEED9_1 (0x2U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
2715#define GPIO_OSPEEDER_OSPEED10_Pos (20U)
2716#define GPIO_OSPEEDER_OSPEED10_Msk (0x3U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
2717#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
2718#define GPIO_OSPEEDER_OSPEED10_0 (0x1U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
2719#define GPIO_OSPEEDER_OSPEED10_1 (0x2U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
2720#define GPIO_OSPEEDER_OSPEED11_Pos (22U)
2721#define GPIO_OSPEEDER_OSPEED11_Msk (0x3U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
2722#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
2723#define GPIO_OSPEEDER_OSPEED11_0 (0x1U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
2724#define GPIO_OSPEEDER_OSPEED11_1 (0x2U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
2725#define GPIO_OSPEEDER_OSPEED12_Pos (24U)
2726#define GPIO_OSPEEDER_OSPEED12_Msk (0x3U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
2727#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
2728#define GPIO_OSPEEDER_OSPEED12_0 (0x1U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
2729#define GPIO_OSPEEDER_OSPEED12_1 (0x2U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
2730#define GPIO_OSPEEDER_OSPEED13_Pos (26U)
2731#define GPIO_OSPEEDER_OSPEED13_Msk (0x3U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
2732#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
2733#define GPIO_OSPEEDER_OSPEED13_0 (0x1U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
2734#define GPIO_OSPEEDER_OSPEED13_1 (0x2U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
2735#define GPIO_OSPEEDER_OSPEED14_Pos (28U)
2736#define GPIO_OSPEEDER_OSPEED14_Msk (0x3U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
2737#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
2738#define GPIO_OSPEEDER_OSPEED14_0 (0x1U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
2739#define GPIO_OSPEEDER_OSPEED14_1 (0x2U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
2740#define GPIO_OSPEEDER_OSPEED15_Pos (30U)
2741#define GPIO_OSPEEDER_OSPEED15_Msk (0x3U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
2742#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
2743#define GPIO_OSPEEDER_OSPEED15_0 (0x1U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
2744#define GPIO_OSPEEDER_OSPEED15_1 (0x2U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
2745
2746/******************* Bit definition for GPIO_PUPDR register ******************/
2747#define GPIO_PUPDR_PUPD0_Pos (0U)
2748#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
2749#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
2750#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
2751#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
2752#define GPIO_PUPDR_PUPD1_Pos (2U)
2753#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
2754#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
2755#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
2756#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
2757#define GPIO_PUPDR_PUPD2_Pos (4U)
2758#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
2759#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
2760#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
2761#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
2762#define GPIO_PUPDR_PUPD3_Pos (6U)
2763#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
2764#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
2765#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
2766#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
2767#define GPIO_PUPDR_PUPD4_Pos (8U)
2768#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
2769#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
2770#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
2771#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
2772#define GPIO_PUPDR_PUPD5_Pos (10U)
2773#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
2774#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
2775#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
2776#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
2777#define GPIO_PUPDR_PUPD6_Pos (12U)
2778#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
2779#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
2780#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
2781#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
2782#define GPIO_PUPDR_PUPD7_Pos (14U)
2783#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
2784#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
2785#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
2786#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
2787#define GPIO_PUPDR_PUPD8_Pos (16U)
2788#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
2789#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
2790#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
2791#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
2792#define GPIO_PUPDR_PUPD9_Pos (18U)
2793#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
2794#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
2795#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
2796#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
2797#define GPIO_PUPDR_PUPD10_Pos (20U)
2798#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
2799#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
2800#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
2801#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
2802#define GPIO_PUPDR_PUPD11_Pos (22U)
2803#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
2804#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
2805#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
2806#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
2807#define GPIO_PUPDR_PUPD12_Pos (24U)
2808#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
2809#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
2810#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
2811#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
2812#define GPIO_PUPDR_PUPD13_Pos (26U)
2813#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
2814#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
2815#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
2816#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
2817#define GPIO_PUPDR_PUPD14_Pos (28U)
2818#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
2819#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
2820#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
2821#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
2822#define GPIO_PUPDR_PUPD15_Pos (30U)
2823#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
2824#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
2825#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
2826#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
2827
2828/******************* Bit definition for GPIO_IDR register *******************/
2829#define GPIO_IDR_ID0_Pos (0U)
2830#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
2831#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
2832#define GPIO_IDR_ID1_Pos (1U)
2833#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
2834#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
2835#define GPIO_IDR_ID2_Pos (2U)
2836#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
2837#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
2838#define GPIO_IDR_ID3_Pos (3U)
2839#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
2840#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
2841#define GPIO_IDR_ID4_Pos (4U)
2842#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
2843#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
2844#define GPIO_IDR_ID5_Pos (5U)
2845#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
2846#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
2847#define GPIO_IDR_ID6_Pos (6U)
2848#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
2849#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
2850#define GPIO_IDR_ID7_Pos (7U)
2851#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
2852#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
2853#define GPIO_IDR_ID8_Pos (8U)
2854#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
2855#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
2856#define GPIO_IDR_ID9_Pos (9U)
2857#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
2858#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
2859#define GPIO_IDR_ID10_Pos (10U)
2860#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
2861#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
2862#define GPIO_IDR_ID11_Pos (11U)
2863#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
2864#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
2865#define GPIO_IDR_ID12_Pos (12U)
2866#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
2867#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
2868#define GPIO_IDR_ID13_Pos (13U)
2869#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
2870#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
2871#define GPIO_IDR_ID14_Pos (14U)
2872#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
2873#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
2874#define GPIO_IDR_ID15_Pos (15U)
2875#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
2876#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
2877
2878/****************** Bit definition for GPIO_ODR register ********************/
2879#define GPIO_ODR_OD0_Pos (0U)
2880#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
2881#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
2882#define GPIO_ODR_OD1_Pos (1U)
2883#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
2884#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
2885#define GPIO_ODR_OD2_Pos (2U)
2886#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
2887#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
2888#define GPIO_ODR_OD3_Pos (3U)
2889#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
2890#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
2891#define GPIO_ODR_OD4_Pos (4U)
2892#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
2893#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
2894#define GPIO_ODR_OD5_Pos (5U)
2895#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
2896#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
2897#define GPIO_ODR_OD6_Pos (6U)
2898#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
2899#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
2900#define GPIO_ODR_OD7_Pos (7U)
2901#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
2902#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
2903#define GPIO_ODR_OD8_Pos (8U)
2904#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
2905#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
2906#define GPIO_ODR_OD9_Pos (9U)
2907#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
2908#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
2909#define GPIO_ODR_OD10_Pos (10U)
2910#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
2911#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
2912#define GPIO_ODR_OD11_Pos (11U)
2913#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
2914#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
2915#define GPIO_ODR_OD12_Pos (12U)
2916#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
2917#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
2918#define GPIO_ODR_OD13_Pos (13U)
2919#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
2920#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
2921#define GPIO_ODR_OD14_Pos (14U)
2922#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
2923#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
2924#define GPIO_ODR_OD15_Pos (15U)
2925#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
2926#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
2927
2928/****************** Bit definition for GPIO_BSRR register ********************/
2929#define GPIO_BSRR_BS_0 (0x00000001U)
2930#define GPIO_BSRR_BS_1 (0x00000002U)
2931#define GPIO_BSRR_BS_2 (0x00000004U)
2932#define GPIO_BSRR_BS_3 (0x00000008U)
2933#define GPIO_BSRR_BS_4 (0x00000010U)
2934#define GPIO_BSRR_BS_5 (0x00000020U)
2935#define GPIO_BSRR_BS_6 (0x00000040U)
2936#define GPIO_BSRR_BS_7 (0x00000080U)
2937#define GPIO_BSRR_BS_8 (0x00000100U)
2938#define GPIO_BSRR_BS_9 (0x00000200U)
2939#define GPIO_BSRR_BS_10 (0x00000400U)
2940#define GPIO_BSRR_BS_11 (0x00000800U)
2941#define GPIO_BSRR_BS_12 (0x00001000U)
2942#define GPIO_BSRR_BS_13 (0x00002000U)
2943#define GPIO_BSRR_BS_14 (0x00004000U)
2944#define GPIO_BSRR_BS_15 (0x00008000U)
2945#define GPIO_BSRR_BR_0 (0x00010000U)
2946#define GPIO_BSRR_BR_1 (0x00020000U)
2947#define GPIO_BSRR_BR_2 (0x00040000U)
2948#define GPIO_BSRR_BR_3 (0x00080000U)
2949#define GPIO_BSRR_BR_4 (0x00100000U)
2950#define GPIO_BSRR_BR_5 (0x00200000U)
2951#define GPIO_BSRR_BR_6 (0x00400000U)
2952#define GPIO_BSRR_BR_7 (0x00800000U)
2953#define GPIO_BSRR_BR_8 (0x01000000U)
2954#define GPIO_BSRR_BR_9 (0x02000000U)
2955#define GPIO_BSRR_BR_10 (0x04000000U)
2956#define GPIO_BSRR_BR_11 (0x08000000U)
2957#define GPIO_BSRR_BR_12 (0x10000000U)
2958#define GPIO_BSRR_BR_13 (0x20000000U)
2959#define GPIO_BSRR_BR_14 (0x40000000U)
2960#define GPIO_BSRR_BR_15 (0x80000000U)
2961
2962/****************** Bit definition for GPIO_LCKR register ********************/
2963#define GPIO_LCKR_LCK0_Pos (0U)
2964#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
2965#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
2966#define GPIO_LCKR_LCK1_Pos (1U)
2967#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
2968#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
2969#define GPIO_LCKR_LCK2_Pos (2U)
2970#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
2971#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
2972#define GPIO_LCKR_LCK3_Pos (3U)
2973#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
2974#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
2975#define GPIO_LCKR_LCK4_Pos (4U)
2976#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
2977#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
2978#define GPIO_LCKR_LCK5_Pos (5U)
2979#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
2980#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
2981#define GPIO_LCKR_LCK6_Pos (6U)
2982#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
2983#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
2984#define GPIO_LCKR_LCK7_Pos (7U)
2985#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
2986#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
2987#define GPIO_LCKR_LCK8_Pos (8U)
2988#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
2989#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
2990#define GPIO_LCKR_LCK9_Pos (9U)
2991#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
2992#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
2993#define GPIO_LCKR_LCK10_Pos (10U)
2994#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
2995#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
2996#define GPIO_LCKR_LCK11_Pos (11U)
2997#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
2998#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
2999#define GPIO_LCKR_LCK12_Pos (12U)
3000#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
3001#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
3002#define GPIO_LCKR_LCK13_Pos (13U)
3003#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
3004#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
3005#define GPIO_LCKR_LCK14_Pos (14U)
3006#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
3007#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
3008#define GPIO_LCKR_LCK15_Pos (15U)
3009#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
3010#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
3011#define GPIO_LCKR_LCKK_Pos (16U)
3012#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
3013#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
3014
3015/****************** Bit definition for GPIO_AFRL register ********************/
3016#define GPIO_AFRL_AFRL0_Pos (0U)
3017#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
3018#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
3019#define GPIO_AFRL_AFRL1_Pos (4U)
3020#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
3021#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
3022#define GPIO_AFRL_AFRL2_Pos (8U)
3023#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
3024#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
3025#define GPIO_AFRL_AFRL3_Pos (12U)
3026#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
3027#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
3028#define GPIO_AFRL_AFRL4_Pos (16U)
3029#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
3030#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
3031#define GPIO_AFRL_AFRL5_Pos (20U)
3032#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
3033#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
3034#define GPIO_AFRL_AFRL6_Pos (24U)
3035#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
3036#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
3037#define GPIO_AFRL_AFRL7_Pos (28U)
3038#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
3039#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
3040
3041/****************** Bit definition for GPIO_AFRH register ********************/
3042#define GPIO_AFRH_AFRH0_Pos (0U)
3043#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
3044#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
3045#define GPIO_AFRH_AFRH1_Pos (4U)
3046#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
3047#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
3048#define GPIO_AFRH_AFRH2_Pos (8U)
3049#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
3050#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
3051#define GPIO_AFRH_AFRH3_Pos (12U)
3052#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
3053#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
3054#define GPIO_AFRH_AFRH4_Pos (16U)
3055#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
3056#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
3057#define GPIO_AFRH_AFRH5_Pos (20U)
3058#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
3059#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
3060#define GPIO_AFRH_AFRH6_Pos (24U)
3061#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
3062#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
3063#define GPIO_AFRH_AFRH7_Pos (28U)
3064#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
3065#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
3066
3067/****************** Bit definition for GPIO_BRR register *********************/
3068#define GPIO_BRR_BR_0 (0x00000001U)
3069#define GPIO_BRR_BR_1 (0x00000002U)
3070#define GPIO_BRR_BR_2 (0x00000004U)
3071#define GPIO_BRR_BR_3 (0x00000008U)
3072#define GPIO_BRR_BR_4 (0x00000010U)
3073#define GPIO_BRR_BR_5 (0x00000020U)
3074#define GPIO_BRR_BR_6 (0x00000040U)
3075#define GPIO_BRR_BR_7 (0x00000080U)
3076#define GPIO_BRR_BR_8 (0x00000100U)
3077#define GPIO_BRR_BR_9 (0x00000200U)
3078#define GPIO_BRR_BR_10 (0x00000400U)
3079#define GPIO_BRR_BR_11 (0x00000800U)
3080#define GPIO_BRR_BR_12 (0x00001000U)
3081#define GPIO_BRR_BR_13 (0x00002000U)
3082#define GPIO_BRR_BR_14 (0x00004000U)
3083#define GPIO_BRR_BR_15 (0x00008000U)
3084
3085/******************************************************************************/
3086/* */
3087/* Inter-integrated Circuit Interface (I2C) */
3088/* */
3089/******************************************************************************/
3090
3091/******************* Bit definition for I2C_CR1 register *******************/
3092#define I2C_CR1_PE_Pos (0U)
3093#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
3094#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
3095#define I2C_CR1_TXIE_Pos (1U)
3096#define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
3097#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
3098#define I2C_CR1_RXIE_Pos (2U)
3099#define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
3100#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
3101#define I2C_CR1_ADDRIE_Pos (3U)
3102#define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
3103#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
3104#define I2C_CR1_NACKIE_Pos (4U)
3105#define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
3106#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
3107#define I2C_CR1_STOPIE_Pos (5U)
3108#define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
3109#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
3110#define I2C_CR1_TCIE_Pos (6U)
3111#define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
3112#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
3113#define I2C_CR1_ERRIE_Pos (7U)
3114#define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
3115#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
3116#define I2C_CR1_DNF_Pos (8U)
3117#define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
3118#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
3119#define I2C_CR1_ANFOFF_Pos (12U)
3120#define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
3121#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
3122#define I2C_CR1_TXDMAEN_Pos (14U)
3123#define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
3124#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
3125#define I2C_CR1_RXDMAEN_Pos (15U)
3126#define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
3127#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
3128#define I2C_CR1_SBC_Pos (16U)
3129#define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
3130#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
3131#define I2C_CR1_NOSTRETCH_Pos (17U)
3132#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
3133#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
3134#define I2C_CR1_WUPEN_Pos (18U)
3135#define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
3136#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
3137#define I2C_CR1_GCEN_Pos (19U)
3138#define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
3139#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
3140#define I2C_CR1_SMBHEN_Pos (20U)
3141#define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
3142#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
3143#define I2C_CR1_SMBDEN_Pos (21U)
3144#define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
3145#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
3146#define I2C_CR1_ALERTEN_Pos (22U)
3147#define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
3148#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
3149#define I2C_CR1_PECEN_Pos (23U)
3150#define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
3151#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
3152
3153/****************** Bit definition for I2C_CR2 register ********************/
3154#define I2C_CR2_SADD_Pos (0U)
3155#define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
3156#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
3157#define I2C_CR2_RD_WRN_Pos (10U)
3158#define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
3159#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
3160#define I2C_CR2_ADD10_Pos (11U)
3161#define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
3162#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
3163#define I2C_CR2_HEAD10R_Pos (12U)
3164#define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
3165#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
3166#define I2C_CR2_START_Pos (13U)
3167#define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
3168#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
3169#define I2C_CR2_STOP_Pos (14U)
3170#define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
3171#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
3172#define I2C_CR2_NACK_Pos (15U)
3173#define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
3174#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
3175#define I2C_CR2_NBYTES_Pos (16U)
3176#define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
3177#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
3178#define I2C_CR2_RELOAD_Pos (24U)
3179#define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
3180#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
3181#define I2C_CR2_AUTOEND_Pos (25U)
3182#define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
3183#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
3184#define I2C_CR2_PECBYTE_Pos (26U)
3185#define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
3186#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
3187
3188/******************* Bit definition for I2C_OAR1 register ******************/
3189#define I2C_OAR1_OA1_Pos (0U)
3190#define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
3191#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
3192#define I2C_OAR1_OA1MODE_Pos (10U)
3193#define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
3194#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
3195#define I2C_OAR1_OA1EN_Pos (15U)
3196#define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
3197#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
3198
3199/******************* Bit definition for I2C_OAR2 register ******************/
3200#define I2C_OAR2_OA2_Pos (1U)
3201#define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
3202#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
3203#define I2C_OAR2_OA2MSK_Pos (8U)
3204#define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
3205#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
3206#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
3207#define I2C_OAR2_OA2MASK01_Pos (8U)
3208#define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
3209#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
3210#define I2C_OAR2_OA2MASK02_Pos (9U)
3211#define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
3212#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
3213#define I2C_OAR2_OA2MASK03_Pos (8U)
3214#define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
3215#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
3216#define I2C_OAR2_OA2MASK04_Pos (10U)
3217#define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
3218#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
3219#define I2C_OAR2_OA2MASK05_Pos (8U)
3220#define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
3221#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
3222#define I2C_OAR2_OA2MASK06_Pos (9U)
3223#define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
3224#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
3225#define I2C_OAR2_OA2MASK07_Pos (8U)
3226#define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
3227#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
3228#define I2C_OAR2_OA2EN_Pos (15U)
3229#define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
3230#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
3231
3232/******************* Bit definition for I2C_TIMINGR register *******************/
3233#define I2C_TIMINGR_SCLL_Pos (0U)
3234#define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
3235#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
3236#define I2C_TIMINGR_SCLH_Pos (8U)
3237#define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
3238#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
3239#define I2C_TIMINGR_SDADEL_Pos (16U)
3240#define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
3241#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
3242#define I2C_TIMINGR_SCLDEL_Pos (20U)
3243#define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
3244#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
3245#define I2C_TIMINGR_PRESC_Pos (28U)
3246#define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
3247#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
3248
3249/******************* Bit definition for I2C_TIMEOUTR register *******************/
3250#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
3251#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
3252#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
3253#define I2C_TIMEOUTR_TIDLE_Pos (12U)
3254#define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
3255#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
3256#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
3257#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
3258#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
3259#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
3260#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
3261#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
3262#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
3263#define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
3264#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
3265
3266/****************** Bit definition for I2C_ISR register *********************/
3267#define I2C_ISR_TXE_Pos (0U)
3268#define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
3269#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
3270#define I2C_ISR_TXIS_Pos (1U)
3271#define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
3272#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
3273#define I2C_ISR_RXNE_Pos (2U)
3274#define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
3275#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
3276#define I2C_ISR_ADDR_Pos (3U)
3277#define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
3278#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
3279#define I2C_ISR_NACKF_Pos (4U)
3280#define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
3281#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
3282#define I2C_ISR_STOPF_Pos (5U)
3283#define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
3284#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
3285#define I2C_ISR_TC_Pos (6U)
3286#define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
3287#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
3288#define I2C_ISR_TCR_Pos (7U)
3289#define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
3290#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
3291#define I2C_ISR_BERR_Pos (8U)
3292#define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
3293#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
3294#define I2C_ISR_ARLO_Pos (9U)
3295#define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
3296#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
3297#define I2C_ISR_OVR_Pos (10U)
3298#define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
3299#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
3300#define I2C_ISR_PECERR_Pos (11U)
3301#define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
3302#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
3303#define I2C_ISR_TIMEOUT_Pos (12U)
3304#define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
3305#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
3306#define I2C_ISR_ALERT_Pos (13U)
3307#define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
3308#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
3309#define I2C_ISR_BUSY_Pos (15U)
3310#define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
3311#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
3312#define I2C_ISR_DIR_Pos (16U)
3313#define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
3314#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
3315#define I2C_ISR_ADDCODE_Pos (17U)
3316#define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
3317#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
3318
3319/****************** Bit definition for I2C_ICR register *********************/
3320#define I2C_ICR_ADDRCF_Pos (3U)
3321#define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
3322#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
3323#define I2C_ICR_NACKCF_Pos (4U)
3324#define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
3325#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
3326#define I2C_ICR_STOPCF_Pos (5U)
3327#define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
3328#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
3329#define I2C_ICR_BERRCF_Pos (8U)
3330#define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
3331#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
3332#define I2C_ICR_ARLOCF_Pos (9U)
3333#define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
3334#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
3335#define I2C_ICR_OVRCF_Pos (10U)
3336#define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
3337#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
3338#define I2C_ICR_PECCF_Pos (11U)
3339#define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
3340#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
3341#define I2C_ICR_TIMOUTCF_Pos (12U)
3342#define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
3343#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
3344#define I2C_ICR_ALERTCF_Pos (13U)
3345#define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
3346#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
3347
3348/****************** Bit definition for I2C_PECR register *********************/
3349#define I2C_PECR_PEC_Pos (0U)
3350#define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
3351#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
3352
3353/****************** Bit definition for I2C_RXDR register *********************/
3354#define I2C_RXDR_RXDATA_Pos (0U)
3355#define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
3356#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
3357
3358/****************** Bit definition for I2C_TXDR register *********************/
3359#define I2C_TXDR_TXDATA_Pos (0U)
3360#define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
3361#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
3362
3363/******************************************************************************/
3364/* */
3365/* Independent WATCHDOG (IWDG) */
3366/* */
3367/******************************************************************************/
3368/******************* Bit definition for IWDG_KR register ********************/
3369#define IWDG_KR_KEY_Pos (0U)
3370#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
3371#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
3372
3373/******************* Bit definition for IWDG_PR register ********************/
3374#define IWDG_PR_PR_Pos (0U)
3375#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
3376#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
3377#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
3378#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
3379#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
3380
3381/******************* Bit definition for IWDG_RLR register *******************/
3382#define IWDG_RLR_RL_Pos (0U)
3383#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
3384#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
3385
3386/******************* Bit definition for IWDG_SR register ********************/
3387#define IWDG_SR_PVU_Pos (0U)
3388#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
3389#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
3390#define IWDG_SR_RVU_Pos (1U)
3391#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
3392#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
3393#define IWDG_SR_WVU_Pos (2U)
3394#define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
3395#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
3396
3397/******************* Bit definition for IWDG_KR register ********************/
3398#define IWDG_WINR_WIN_Pos (0U)
3399#define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
3400#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
3401
3402/******************************************************************************/
3403/* */
3404/* LCD Controller (LCD) */
3405/* */
3406/******************************************************************************/
3407
3408/******************* Bit definition for LCD_CR register *********************/
3409#define LCD_CR_LCDEN_Pos (0U)
3410#define LCD_CR_LCDEN_Msk (0x1U << LCD_CR_LCDEN_Pos) /*!< 0x00000001 */
3411#define LCD_CR_LCDEN LCD_CR_LCDEN_Msk /*!< LCD Enable Bit */
3412#define LCD_CR_VSEL_Pos (1U)
3413#define LCD_CR_VSEL_Msk (0x1U << LCD_CR_VSEL_Pos) /*!< 0x00000002 */
3414#define LCD_CR_VSEL LCD_CR_VSEL_Msk /*!< Voltage source selector Bit */
3415
3416#define LCD_CR_DUTY_Pos (2U)
3417#define LCD_CR_DUTY_Msk (0x7U << LCD_CR_DUTY_Pos) /*!< 0x0000001C */
3418#define LCD_CR_DUTY LCD_CR_DUTY_Msk /*!< DUTY[2:0] bits (Duty selector) */
3419#define LCD_CR_DUTY_0 (0x1U << LCD_CR_DUTY_Pos) /*!< 0x00000004 */
3420#define LCD_CR_DUTY_1 (0x2U << LCD_CR_DUTY_Pos) /*!< 0x00000008 */
3421#define LCD_CR_DUTY_2 (0x4U << LCD_CR_DUTY_Pos) /*!< 0x00000010 */
3422
3423#define LCD_CR_BIAS_Pos (5U)
3424#define LCD_CR_BIAS_Msk (0x3U << LCD_CR_BIAS_Pos) /*!< 0x00000060 */
3425#define LCD_CR_BIAS LCD_CR_BIAS_Msk /*!< BIAS[1:0] bits (Bias selector) */
3426#define LCD_CR_BIAS_0 (0x1U << LCD_CR_BIAS_Pos) /*!< 0x00000020 */
3427#define LCD_CR_BIAS_1 (0x2U << LCD_CR_BIAS_Pos) /*!< 0x00000040 */
3428
3429#define LCD_CR_MUX_SEG_Pos (7U)
3430#define LCD_CR_MUX_SEG_Msk (0x1U << LCD_CR_MUX_SEG_Pos) /*!< 0x00000080 */
3431#define LCD_CR_MUX_SEG LCD_CR_MUX_SEG_Msk /*!< Mux Segment Enable Bit */
3432
3433#define LCD_CR_BUFEN_Pos (8U)
3434#define LCD_CR_BUFEN_Msk (0x1U << LCD_CR_BUFEN_Pos) /*!< 0x00000100 */
3435#define LCD_CR_BUFEN LCD_CR_BUFEN_Msk /*!< Voltage output buffer enable Bit */
3436
3437/******************* Bit definition for LCD_FCR register ********************/
3438#define LCD_FCR_HD_Pos (0U)
3439#define LCD_FCR_HD_Msk (0x1U << LCD_FCR_HD_Pos) /*!< 0x00000001 */
3440#define LCD_FCR_HD LCD_FCR_HD_Msk /*!< High Drive Enable Bit */
3441#define LCD_FCR_SOFIE_Pos (1U)
3442#define LCD_FCR_SOFIE_Msk (0x1U << LCD_FCR_SOFIE_Pos) /*!< 0x00000002 */
3443#define LCD_FCR_SOFIE LCD_FCR_SOFIE_Msk /*!< Start of Frame Interrupt Enable Bit */
3444#define LCD_FCR_UDDIE_Pos (3U)
3445#define LCD_FCR_UDDIE_Msk (0x1U << LCD_FCR_UDDIE_Pos) /*!< 0x00000008 */
3446#define LCD_FCR_UDDIE LCD_FCR_UDDIE_Msk /*!< Update Display Done Interrupt Enable Bit */
3447
3448#define LCD_FCR_PON_Pos (4U)
3449#define LCD_FCR_PON_Msk (0x7U << LCD_FCR_PON_Pos) /*!< 0x00000070 */
3450#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
3451#define LCD_FCR_PON_0 (0x1U << LCD_FCR_PON_Pos) /*!< 0x00000010 */
3452#define LCD_FCR_PON_1 (0x2U << LCD_FCR_PON_Pos) /*!< 0x00000020 */
3453#define LCD_FCR_PON_2 (0x4U << LCD_FCR_PON_Pos) /*!< 0x00000040 */
3454
3455#define LCD_FCR_DEAD_Pos (7U)
3456#define LCD_FCR_DEAD_Msk (0x7U << LCD_FCR_DEAD_Pos) /*!< 0x00000380 */
3457#define LCD_FCR_DEAD LCD_FCR_DEAD_Msk /*!< DEAD[2:0] bits (DEAD Time) */
3458#define LCD_FCR_DEAD_0 (0x1U << LCD_FCR_DEAD_Pos) /*!< 0x00000080 */
3459#define LCD_FCR_DEAD_1 (0x2U << LCD_FCR_DEAD_Pos) /*!< 0x00000100 */
3460#define LCD_FCR_DEAD_2 (0x4U << LCD_FCR_DEAD_Pos) /*!< 0x00000200 */
3461
3462#define LCD_FCR_CC_Pos (10U)
3463#define LCD_FCR_CC_Msk (0x7U << LCD_FCR_CC_Pos) /*!< 0x00001C00 */
3464#define LCD_FCR_CC LCD_FCR_CC_Msk /*!< CC[2:0] bits (Contrast Control) */
3465#define LCD_FCR_CC_0 (0x1U << LCD_FCR_CC_Pos) /*!< 0x00000400 */
3466#define LCD_FCR_CC_1 (0x2U << LCD_FCR_CC_Pos) /*!< 0x00000800 */
3467#define LCD_FCR_CC_2 (0x4U << LCD_FCR_CC_Pos) /*!< 0x00001000 */
3468
3469#define LCD_FCR_BLINKF_Pos (13U)
3470#define LCD_FCR_BLINKF_Msk (0x7U << LCD_FCR_BLINKF_Pos) /*!< 0x0000E000 */
3471#define LCD_FCR_BLINKF LCD_FCR_BLINKF_Msk /*!< BLINKF[2:0] bits (Blink Frequency) */
3472#define LCD_FCR_BLINKF_0 (0x1U << LCD_FCR_BLINKF_Pos) /*!< 0x00002000 */
3473#define LCD_FCR_BLINKF_1 (0x2U << LCD_FCR_BLINKF_Pos) /*!< 0x00004000 */
3474#define LCD_FCR_BLINKF_2 (0x4U << LCD_FCR_BLINKF_Pos) /*!< 0x00008000 */
3475
3476#define LCD_FCR_BLINK_Pos (16U)
3477#define LCD_FCR_BLINK_Msk (0x3U << LCD_FCR_BLINK_Pos) /*!< 0x00030000 */
3478#define LCD_FCR_BLINK LCD_FCR_BLINK_Msk /*!< BLINK[1:0] bits (Blink Enable) */
3479#define LCD_FCR_BLINK_0 (0x1U << LCD_FCR_BLINK_Pos) /*!< 0x00010000 */
3480#define LCD_FCR_BLINK_1 (0x2U << LCD_FCR_BLINK_Pos) /*!< 0x00020000 */
3481
3482#define LCD_FCR_DIV_Pos (18U)
3483#define LCD_FCR_DIV_Msk (0xFU << LCD_FCR_DIV_Pos) /*!< 0x003C0000 */
3484#define LCD_FCR_DIV LCD_FCR_DIV_Msk /*!< DIV[3:0] bits (Divider) */
3485#define LCD_FCR_PS_Pos (22U)
3486#define LCD_FCR_PS_Msk (0xFU << LCD_FCR_PS_Pos) /*!< 0x03C00000 */
3487#define LCD_FCR_PS LCD_FCR_PS_Msk /*!< PS[3:0] bits (Prescaler) */
3488
3489/******************* Bit definition for LCD_SR register *********************/
3490#define LCD_SR_ENS_Pos (0U)
3491#define LCD_SR_ENS_Msk (0x1U << LCD_SR_ENS_Pos) /*!< 0x00000001 */
3492#define LCD_SR_ENS LCD_SR_ENS_Msk /*!< LCD Enabled Bit */
3493#define LCD_SR_SOF_Pos (1U)
3494#define LCD_SR_SOF_Msk (0x1U << LCD_SR_SOF_Pos) /*!< 0x00000002 */
3495#define LCD_SR_SOF LCD_SR_SOF_Msk /*!< Start Of Frame Flag Bit */
3496#define LCD_SR_UDR_Pos (2U)
3497#define LCD_SR_UDR_Msk (0x1U << LCD_SR_UDR_Pos) /*!< 0x00000004 */
3498#define LCD_SR_UDR LCD_SR_UDR_Msk /*!< Update Display Request Bit */
3499#define LCD_SR_UDD_Pos (3U)
3500#define LCD_SR_UDD_Msk (0x1U << LCD_SR_UDD_Pos) /*!< 0x00000008 */
3501#define LCD_SR_UDD LCD_SR_UDD_Msk /*!< Update Display Done Flag Bit */
3502#define LCD_SR_RDY_Pos (4U)
3503#define LCD_SR_RDY_Msk (0x1U << LCD_SR_RDY_Pos) /*!< 0x00000010 */
3504#define LCD_SR_RDY LCD_SR_RDY_Msk /*!< Ready Flag Bit */
3505#define LCD_SR_FCRSR_Pos (5U)
3506#define LCD_SR_FCRSR_Msk (0x1U << LCD_SR_FCRSR_Pos) /*!< 0x00000020 */
3507#define LCD_SR_FCRSR LCD_SR_FCRSR_Msk /*!< LCD FCR Register Synchronization Flag Bit */
3508
3509/******************* Bit definition for LCD_CLR register ********************/
3510#define LCD_CLR_SOFC_Pos (1U)
3511#define LCD_CLR_SOFC_Msk (0x1U << LCD_CLR_SOFC_Pos) /*!< 0x00000002 */
3512#define LCD_CLR_SOFC LCD_CLR_SOFC_Msk /*!< Start Of Frame Flag Clear Bit */
3513#define LCD_CLR_UDDC_Pos (3U)
3514#define LCD_CLR_UDDC_Msk (0x1U << LCD_CLR_UDDC_Pos) /*!< 0x00000008 */
3515#define LCD_CLR_UDDC LCD_CLR_UDDC_Msk /*!< Update Display Done Flag Clear Bit */
3516
3517/******************* Bit definition for LCD_RAM register ********************/
3518#define LCD_RAM_SEGMENT_DATA_Pos (0U)
3519#define LCD_RAM_SEGMENT_DATA_Msk (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos) /*!< 0xFFFFFFFF */
3520#define LCD_RAM_SEGMENT_DATA LCD_RAM_SEGMENT_DATA_Msk /*!< Segment Data Bits */
3521
3522/******************************************************************************/
3523/* */
3524/* Low Power Timer (LPTTIM) */
3525/* */
3526/******************************************************************************/
3527/****************** Bit definition for LPTIM_ISR register *******************/
3528#define LPTIM_ISR_CMPM_Pos (0U)
3529#define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
3530#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
3531#define LPTIM_ISR_ARRM_Pos (1U)
3532#define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
3533#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
3534#define LPTIM_ISR_EXTTRIG_Pos (2U)
3535#define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
3536#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
3537#define LPTIM_ISR_CMPOK_Pos (3U)
3538#define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
3539#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
3540#define LPTIM_ISR_ARROK_Pos (4U)
3541#define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
3542#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
3543#define LPTIM_ISR_UP_Pos (5U)
3544#define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
3545#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
3546#define LPTIM_ISR_DOWN_Pos (6U)
3547#define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
3548#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
3549
3550/****************** Bit definition for LPTIM_ICR register *******************/
3551#define LPTIM_ICR_CMPMCF_Pos (0U)
3552#define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
3553#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
3554#define LPTIM_ICR_ARRMCF_Pos (1U)
3555#define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
3556#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
3557#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
3558#define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
3559#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
3560#define LPTIM_ICR_CMPOKCF_Pos (3U)
3561#define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
3562#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
3563#define LPTIM_ICR_ARROKCF_Pos (4U)
3564#define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
3565#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
3566#define LPTIM_ICR_UPCF_Pos (5U)
3567#define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
3568#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
3569#define LPTIM_ICR_DOWNCF_Pos (6U)
3570#define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
3571#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
3572
3573/****************** Bit definition for LPTIM_IER register ********************/
3574#define LPTIM_IER_CMPMIE_Pos (0U)
3575#define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
3576#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
3577#define LPTIM_IER_ARRMIE_Pos (1U)
3578#define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
3579#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
3580#define LPTIM_IER_EXTTRIGIE_Pos (2U)
3581#define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
3582#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
3583#define LPTIM_IER_CMPOKIE_Pos (3U)
3584#define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
3585#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
3586#define LPTIM_IER_ARROKIE_Pos (4U)
3587#define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
3588#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
3589#define LPTIM_IER_UPIE_Pos (5U)
3590#define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
3591#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
3592#define LPTIM_IER_DOWNIE_Pos (6U)
3593#define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
3594#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
3595
3596/****************** Bit definition for LPTIM_CFGR register *******************/
3597#define LPTIM_CFGR_CKSEL_Pos (0U)
3598#define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
3599#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
3600
3601#define LPTIM_CFGR_CKPOL_Pos (1U)
3602#define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
3603#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
3604#define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
3605#define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
3606
3607#define LPTIM_CFGR_CKFLT_Pos (3U)
3608#define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
3609#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
3610#define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
3611#define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
3612
3613#define LPTIM_CFGR_TRGFLT_Pos (6U)
3614#define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
3615#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
3616#define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
3617#define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
3618
3619#define LPTIM_CFGR_PRESC_Pos (9U)
3620#define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
3621#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
3622#define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
3623#define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
3624#define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
3625
3626#define LPTIM_CFGR_TRIGSEL_Pos (13U)
3627#define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
3628#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
3629#define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
3630#define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
3631#define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
3632
3633#define LPTIM_CFGR_TRIGEN_Pos (17U)
3634#define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
3635#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
3636#define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
3637#define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
3638
3639#define LPTIM_CFGR_TIMOUT_Pos (19U)
3640#define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
3641#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
3642#define LPTIM_CFGR_WAVE_Pos (20U)
3643#define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
3644#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
3645#define LPTIM_CFGR_WAVPOL_Pos (21U)
3646#define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
3647#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
3648#define LPTIM_CFGR_PRELOAD_Pos (22U)
3649#define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
3650#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
3651#define LPTIM_CFGR_COUNTMODE_Pos (23U)
3652#define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
3653#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
3654#define LPTIM_CFGR_ENC_Pos (24U)
3655#define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
3656#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
3657
3658/****************** Bit definition for LPTIM_CR register ********************/
3659#define LPTIM_CR_ENABLE_Pos (0U)
3660#define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
3661#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
3662#define LPTIM_CR_SNGSTRT_Pos (1U)
3663#define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
3664#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
3665#define LPTIM_CR_CNTSTRT_Pos (2U)
3666#define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
3667#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
3668
3669/****************** Bit definition for LPTIM_CMP register *******************/
3670#define LPTIM_CMP_CMP_Pos (0U)
3671#define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
3672#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
3673
3674/****************** Bit definition for LPTIM_ARR register *******************/
3675#define LPTIM_ARR_ARR_Pos (0U)
3676#define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
3677#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
3678
3679/****************** Bit definition for LPTIM_CNT register *******************/
3680#define LPTIM_CNT_CNT_Pos (0U)
3681#define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
3682#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
3683
3684/******************************************************************************/
3685/* */
3686/* MIFARE Firewall */
3687/* */
3688/******************************************************************************/
3689
3690/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
3691#define FW_CSSA_ADD_Pos (8U)
3692#define FW_CSSA_ADD_Msk (0xFFFFU << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
3693#define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
3694#define FW_CSL_LENG_Pos (8U)
3695#define FW_CSL_LENG_Msk (0x3FFFU << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
3696#define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
3697#define FW_NVDSSA_ADD_Pos (8U)
3698#define FW_NVDSSA_ADD_Msk (0xFFFFU << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
3699#define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
3700#define FW_NVDSL_LENG_Pos (8U)
3701#define FW_NVDSL_LENG_Msk (0x3FFFU << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
3702#define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
3703#define FW_VDSSA_ADD_Pos (6U)
3704#define FW_VDSSA_ADD_Msk (0x3FFU << FW_VDSSA_ADD_Pos) /*!< 0x0000FFC0 */
3705#define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
3706#define FW_VDSL_LENG_Pos (6U)
3707#define FW_VDSL_LENG_Msk (0x3FFU << FW_VDSL_LENG_Pos) /*!< 0x0000FFC0 */
3708#define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
3709
3710/**************************Bit definition for CR register *********************/
3711#define FW_CR_FPA_Pos (0U)
3712#define FW_CR_FPA_Msk (0x1U << FW_CR_FPA_Pos) /*!< 0x00000001 */
3713#define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
3714#define FW_CR_VDS_Pos (1U)
3715#define FW_CR_VDS_Msk (0x1U << FW_CR_VDS_Pos) /*!< 0x00000002 */
3716#define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
3717#define FW_CR_VDE_Pos (2U)
3718#define FW_CR_VDE_Msk (0x1U << FW_CR_VDE_Pos) /*!< 0x00000004 */
3719#define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
3720
3721/******************************************************************************/
3722/* */
3723/* Power Control (PWR) */
3724/* */
3725/******************************************************************************/
3726
3727#define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */
3728
3729/******************** Bit definition for PWR_CR register ********************/
3730#define PWR_CR_LPSDSR_Pos (0U)
3731#define PWR_CR_LPSDSR_Msk (0x1U << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
3732#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
3733#define PWR_CR_PDDS_Pos (1U)
3734#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
3735#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
3736#define PWR_CR_CWUF_Pos (2U)
3737#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
3738#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
3739#define PWR_CR_CSBF_Pos (3U)
3740#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
3741#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
3742#define PWR_CR_PVDE_Pos (4U)
3743#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
3744#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
3745
3746#define PWR_CR_PLS_Pos (5U)
3747#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
3748#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
3749#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
3750#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
3751#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
3752
3753/*!< PVD level configuration */
3754#define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
3755#define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
3756#define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
3757#define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
3758#define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
3759#define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
3760#define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
3761#define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
3762
3763#define PWR_CR_DBP_Pos (8U)
3764#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
3765#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
3766#define PWR_CR_ULP_Pos (9U)
3767#define PWR_CR_ULP_Msk (0x1U << PWR_CR_ULP_Pos) /*!< 0x00000200 */
3768#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
3769#define PWR_CR_FWU_Pos (10U)
3770#define PWR_CR_FWU_Msk (0x1U << PWR_CR_FWU_Pos) /*!< 0x00000400 */
3771#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
3772
3773#define PWR_CR_VOS_Pos (11U)
3774#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x00001800 */
3775#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
3776#define PWR_CR_VOS_0 (0x1U << PWR_CR_VOS_Pos) /*!< 0x00000800 */
3777#define PWR_CR_VOS_1 (0x2U << PWR_CR_VOS_Pos) /*!< 0x00001000 */
3778#define PWR_CR_DSEEKOFF_Pos (13U)
3779#define PWR_CR_DSEEKOFF_Msk (0x1U << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */
3780#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */
3781#define PWR_CR_LPRUN_Pos (14U)
3782#define PWR_CR_LPRUN_Msk (0x1U << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
3783#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
3784
3785/******************* Bit definition for PWR_CSR register ********************/
3786#define PWR_CSR_WUF_Pos (0U)
3787#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
3788#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
3789#define PWR_CSR_SBF_Pos (1U)
3790#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
3791#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
3792#define PWR_CSR_PVDO_Pos (2U)
3793#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
3794#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
3795#define PWR_CSR_VREFINTRDYF_Pos (3U)
3796#define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
3797#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
3798#define PWR_CSR_VOSF_Pos (4U)
3799#define PWR_CSR_VOSF_Msk (0x1U << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
3800#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
3801#define PWR_CSR_REGLPF_Pos (5U)
3802#define PWR_CSR_REGLPF_Msk (0x1U << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
3803#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
3804
3805#define PWR_CSR_EWUP1_Pos (8U)
3806#define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
3807#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
3808#define PWR_CSR_EWUP2_Pos (9U)
3809#define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
3810#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
3811#define PWR_CSR_EWUP3_Pos (10U)
3812#define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
3813#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
3814
3815/******************************************************************************/
3816/* */
3817/* Reset and Clock Control */
3818/* */
3819/******************************************************************************/
3820
3821#define RCC_HSI48_SUPPORT /*!< HSI48 feature support */
3822#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
3823
3824/******************** Bit definition for RCC_CR register ********************/
3825#define RCC_CR_HSION_Pos (0U)
3826#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
3827#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
3828#define RCC_CR_HSIKERON_Pos (1U)
3829#define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
3830#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
3831#define RCC_CR_HSIRDY_Pos (2U)
3832#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
3833#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
3834#define RCC_CR_HSIDIVEN_Pos (3U)
3835#define RCC_CR_HSIDIVEN_Msk (0x1U << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */
3836#define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */
3837#define RCC_CR_HSIDIVF_Pos (4U)
3838#define RCC_CR_HSIDIVF_Msk (0x1U << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */
3839#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */
3840#define RCC_CR_HSIOUTEN_Pos (5U)
3841#define RCC_CR_HSIOUTEN_Msk (0x1U << RCC_CR_HSIOUTEN_Pos) /*!< 0x00000020 */
3842#define RCC_CR_HSIOUTEN RCC_CR_HSIOUTEN_Msk /*!< Internal High Speed clock out enable */
3843#define RCC_CR_MSION_Pos (8U)
3844#define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000100 */
3845#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
3846#define RCC_CR_MSIRDY_Pos (9U)
3847#define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
3848#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
3849#define RCC_CR_HSEON_Pos (16U)
3850#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
3851#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
3852#define RCC_CR_HSERDY_Pos (17U)
3853#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
3854#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
3855#define RCC_CR_HSEBYP_Pos (18U)
3856#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
3857#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
3858#define RCC_CR_CSSHSEON_Pos (19U)
3859#define RCC_CR_CSSHSEON_Msk (0x1U << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
3860#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */
3861#define RCC_CR_RTCPRE_Pos (20U)
3862#define RCC_CR_RTCPRE_Msk (0x3U << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */
3863#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC/LCD prescaler [1:0] bits */
3864#define RCC_CR_RTCPRE_0 (0x1U << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */
3865#define RCC_CR_RTCPRE_1 (0x2U << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */
3866#define RCC_CR_PLLON_Pos (24U)
3867#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
3868#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
3869#define RCC_CR_PLLRDY_Pos (25U)
3870#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
3871#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
3872
3873/* Reference defines */
3874#define RCC_CR_CSSON RCC_CR_CSSHSEON
3875
3876/******************** Bit definition for RCC_ICSCR register *****************/
3877#define RCC_ICSCR_HSICAL_Pos (0U)
3878#define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
3879#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
3880#define RCC_ICSCR_HSITRIM_Pos (8U)
3881#define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
3882#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
3883
3884#define RCC_ICSCR_MSIRANGE_Pos (13U)
3885#define RCC_ICSCR_MSIRANGE_Msk (0x7U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
3886#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
3887#define RCC_ICSCR_MSIRANGE_0 (0x0U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
3888#define RCC_ICSCR_MSIRANGE_1 (0x1U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
3889#define RCC_ICSCR_MSIRANGE_2 (0x2U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
3890#define RCC_ICSCR_MSIRANGE_3 (0x3U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
3891#define RCC_ICSCR_MSIRANGE_4 (0x4U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
3892#define RCC_ICSCR_MSIRANGE_5 (0x5U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
3893#define RCC_ICSCR_MSIRANGE_6 (0x6U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
3894#define RCC_ICSCR_MSICAL_Pos (16U)
3895#define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
3896#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
3897#define RCC_ICSCR_MSITRIM_Pos (24U)
3898#define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
3899#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
3900
3901/******************** Bit definition for RCC_CRRCR register *****************/
3902#define RCC_CRRCR_HSI48ON_Pos (0U)
3903#define RCC_CRRCR_HSI48ON_Msk (0x1U << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
3904#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk /*!< HSI 48MHz clock enable */
3905#define RCC_CRRCR_HSI48RDY_Pos (1U)
3906#define RCC_CRRCR_HSI48RDY_Msk (0x1U << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
3907#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk /*!< HSI 48MHz clock ready flag */
3908#define RCC_CRRCR_HSI48DIV6OUTEN_Pos (2U)
3909#define RCC_CRRCR_HSI48DIV6OUTEN_Msk (0x1U << RCC_CRRCR_HSI48DIV6OUTEN_Pos) /*!< 0x00000004 */
3910#define RCC_CRRCR_HSI48DIV6OUTEN RCC_CRRCR_HSI48DIV6OUTEN_Msk /*!< HSI 48MHz DIV6 out enable */
3911#define RCC_CRRCR_HSI48CAL_Pos (8U)
3912#define RCC_CRRCR_HSI48CAL_Msk (0xFFU << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF00 */
3913#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI 48MHz clock Calibration */
3914
3915/******************* Bit definition for RCC_CFGR register *******************/
3916/*!< SW configuration */
3917#define RCC_CFGR_SW_Pos (0U)
3918#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
3919#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
3920#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
3921#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
3922
3923#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
3924#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
3925#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
3926#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
3927
3928/*!< SWS configuration */
3929#define RCC_CFGR_SWS_Pos (2U)
3930#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
3931#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
3932#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
3933#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
3934
3935#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
3936#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
3937#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
3938#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
3939
3940/*!< HPRE configuration */
3941#define RCC_CFGR_HPRE_Pos (4U)
3942#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
3943#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
3944#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
3945#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
3946#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
3947#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
3948
3949#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
3950#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
3951#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
3952#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
3953#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
3954#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
3955#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
3956#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
3957#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
3958
3959/*!< PPRE1 configuration */
3960#define RCC_CFGR_PPRE1_Pos (8U)
3961#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
3962#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
3963#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
3964#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
3965#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
3966
3967#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
3968#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
3969#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
3970#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
3971#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
3972
3973/*!< PPRE2 configuration */
3974#define RCC_CFGR_PPRE2_Pos (11U)
3975#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
3976#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
3977#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
3978#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
3979#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
3980
3981#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
3982#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
3983#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
3984#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
3985#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
3986
3987#define RCC_CFGR_STOPWUCK_Pos (15U)
3988#define RCC_CFGR_STOPWUCK_Msk (0x1U << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
3989#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */
3990
3991/*!< PLL entry clock source*/
3992#define RCC_CFGR_PLLSRC_Pos (16U)
3993#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
3994#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
3995
3996#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
3997#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
3998
3999
4000/*!< PLLMUL configuration */
4001#define RCC_CFGR_PLLMUL_Pos (18U)
4002#define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
4003#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
4004#define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
4005#define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
4006#define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
4007#define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
4008
4009#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
4010#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
4011#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
4012#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
4013#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
4014#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
4015#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
4016#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
4017#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
4018
4019/*!< PLLDIV configuration */
4020#define RCC_CFGR_PLLDIV_Pos (22U)
4021#define RCC_CFGR_PLLDIV_Msk (0x3U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
4022#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
4023#define RCC_CFGR_PLLDIV_0 (0x1U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
4024#define RCC_CFGR_PLLDIV_1 (0x2U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
4025
4026#define RCC_CFGR_PLLDIV2_Pos (22U)
4027#define RCC_CFGR_PLLDIV2_Msk (0x1U << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
4028#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
4029#define RCC_CFGR_PLLDIV3_Pos (23U)
4030#define RCC_CFGR_PLLDIV3_Msk (0x1U << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
4031#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
4032#define RCC_CFGR_PLLDIV4_Pos (22U)
4033#define RCC_CFGR_PLLDIV4_Msk (0x3U << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
4034#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
4035
4036/*!< MCO configuration */
4037#define RCC_CFGR_MCOSEL_Pos (24U)
4038#define RCC_CFGR_MCOSEL_Msk (0xFU << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
4039#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
4040#define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
4041#define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
4042#define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
4043#define RCC_CFGR_MCOSEL_3 (0x8U << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
4044
4045#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
4046#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
4047#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1U << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
4048#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */
4049#define RCC_CFGR_MCOSEL_HSI_Pos (25U)
4050#define RCC_CFGR_MCOSEL_HSI_Msk (0x1U << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
4051#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
4052#define RCC_CFGR_MCOSEL_MSI_Pos (24U)
4053#define RCC_CFGR_MCOSEL_MSI_Msk (0x3U << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
4054#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
4055#define RCC_CFGR_MCOSEL_HSE_Pos (26U)
4056#define RCC_CFGR_MCOSEL_HSE_Msk (0x1U << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
4057#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
4058#define RCC_CFGR_MCOSEL_PLL_Pos (24U)
4059#define RCC_CFGR_MCOSEL_PLL_Msk (0x5U << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
4060#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
4061#define RCC_CFGR_MCOSEL_LSI_Pos (25U)
4062#define RCC_CFGR_MCOSEL_LSI_Msk (0x3U << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
4063#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
4064#define RCC_CFGR_MCOSEL_LSE_Pos (24U)
4065#define RCC_CFGR_MCOSEL_LSE_Msk (0x7U << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
4066#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
4067#define RCC_CFGR_MCOSEL_HSI48_Pos (27U)
4068#define RCC_CFGR_MCOSEL_HSI48_Msk (0x1U << RCC_CFGR_MCOSEL_HSI48_Pos) /*!< 0x08000000 */
4069#define RCC_CFGR_MCOSEL_HSI48 RCC_CFGR_MCOSEL_HSI48_Msk /*!< HSI48 clock selected as MCO source */
4070
4071#define RCC_CFGR_MCOPRE_Pos (28U)
4072#define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
4073#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
4074#define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
4075#define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
4076#define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
4077
4078#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
4079#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
4080#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
4081#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
4082#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
4083
4084/* Legacy defines */
4085#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
4086#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
4087#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
4088#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
4089#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
4090#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
4091#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
4092#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
4093#define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48
4094
4095#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
4096#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
4097#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
4098#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
4099#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
4100#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
4101
4102/*!<****************** Bit definition for RCC_CIER register ********************/
4103#define RCC_CIER_LSIRDYIE_Pos (0U)
4104#define RCC_CIER_LSIRDYIE_Msk (0x1U << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
4105#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
4106#define RCC_CIER_LSERDYIE_Pos (1U)
4107#define RCC_CIER_LSERDYIE_Msk (0x1U << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
4108#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
4109#define RCC_CIER_HSIRDYIE_Pos (2U)
4110#define RCC_CIER_HSIRDYIE_Msk (0x1U << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
4111#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
4112#define RCC_CIER_HSERDYIE_Pos (3U)
4113#define RCC_CIER_HSERDYIE_Msk (0x1U << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
4114#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
4115#define RCC_CIER_PLLRDYIE_Pos (4U)
4116#define RCC_CIER_PLLRDYIE_Msk (0x1U << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */
4117#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
4118#define RCC_CIER_MSIRDYIE_Pos (5U)
4119#define RCC_CIER_MSIRDYIE_Msk (0x1U << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */
4120#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */
4121#define RCC_CIER_HSI48RDYIE_Pos (6U)
4122#define RCC_CIER_HSI48RDYIE_Msk (0x1U << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000040 */
4123#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk /*!< HSI48 Ready Interrupt Enable */
4124#define RCC_CIER_CSSLSE_Pos (7U)
4125#define RCC_CIER_CSSLSE_Msk (0x1U << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */
4126#define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */
4127
4128/* Reference defines */
4129#define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
4130
4131/*!<****************** Bit definition for RCC_CIFR register ********************/
4132#define RCC_CIFR_LSIRDYF_Pos (0U)
4133#define RCC_CIFR_LSIRDYF_Msk (0x1U << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
4134#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
4135#define RCC_CIFR_LSERDYF_Pos (1U)
4136#define RCC_CIFR_LSERDYF_Msk (0x1U << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
4137#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
4138#define RCC_CIFR_HSIRDYF_Pos (2U)
4139#define RCC_CIFR_HSIRDYF_Msk (0x1U << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
4140#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
4141#define RCC_CIFR_HSERDYF_Pos (3U)
4142#define RCC_CIFR_HSERDYF_Msk (0x1U << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
4143#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
4144#define RCC_CIFR_PLLRDYF_Pos (4U)
4145#define RCC_CIFR_PLLRDYF_Msk (0x1U << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */
4146#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
4147#define RCC_CIFR_MSIRDYF_Pos (5U)
4148#define RCC_CIFR_MSIRDYF_Msk (0x1U << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */
4149#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */
4150#define RCC_CIFR_HSI48RDYF_Pos (6U)
4151#define RCC_CIFR_HSI48RDYF_Msk (0x1U << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000040 */
4152#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk /*!< HSI48 Ready Interrupt flag */
4153#define RCC_CIFR_CSSLSEF_Pos (7U)
4154#define RCC_CIFR_CSSLSEF_Msk (0x1U << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */
4155#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */
4156#define RCC_CIFR_CSSHSEF_Pos (8U)
4157#define RCC_CIFR_CSSHSEF_Msk (0x1U << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */
4158#define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */
4159
4160/* Reference defines */
4161#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
4162#define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
4163
4164/*!<****************** Bit definition for RCC_CICR register ********************/
4165#define RCC_CICR_LSIRDYC_Pos (0U)
4166#define RCC_CICR_LSIRDYC_Msk (0x1U << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
4167#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
4168#define RCC_CICR_LSERDYC_Pos (1U)
4169#define RCC_CICR_LSERDYC_Msk (0x1U << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
4170#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
4171#define RCC_CICR_HSIRDYC_Pos (2U)
4172#define RCC_CICR_HSIRDYC_Msk (0x1U << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
4173#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
4174#define RCC_CICR_HSERDYC_Pos (3U)
4175#define RCC_CICR_HSERDYC_Msk (0x1U << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
4176#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
4177#define RCC_CICR_PLLRDYC_Pos (4U)
4178#define RCC_CICR_PLLRDYC_Msk (0x1U << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */
4179#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
4180#define RCC_CICR_MSIRDYC_Pos (5U)
4181#define RCC_CICR_MSIRDYC_Msk (0x1U << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */
4182#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */
4183#define RCC_CICR_HSI48RDYC_Pos (6U)
4184#define RCC_CICR_HSI48RDYC_Msk (0x1U << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000040 */
4185#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk /*!< HSI48 Ready Interrupt Clear */
4186#define RCC_CICR_CSSLSEC_Pos (7U)
4187#define RCC_CICR_CSSLSEC_Msk (0x1U << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */
4188#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */
4189#define RCC_CICR_CSSHSEC_Pos (8U)
4190#define RCC_CICR_CSSHSEC_Msk (0x1U << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */
4191#define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */
4192
4193/* Reference defines */
4194#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
4195#define RCC_CICR_CSSC RCC_CICR_CSSHSEC
4196/***************** Bit definition for RCC_IOPRSTR register ******************/
4197#define RCC_IOPRSTR_IOPARST_Pos (0U)
4198#define RCC_IOPRSTR_IOPARST_Msk (0x1U << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */
4199#define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */
4200#define RCC_IOPRSTR_IOPBRST_Pos (1U)
4201#define RCC_IOPRSTR_IOPBRST_Msk (0x1U << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */
4202#define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */
4203#define RCC_IOPRSTR_IOPCRST_Pos (2U)
4204#define RCC_IOPRSTR_IOPCRST_Msk (0x1U << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */
4205#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */
4206#define RCC_IOPRSTR_IOPDRST_Pos (3U)
4207#define RCC_IOPRSTR_IOPDRST_Msk (0x1U << RCC_IOPRSTR_IOPDRST_Pos) /*!< 0x00000008 */
4208#define RCC_IOPRSTR_IOPDRST RCC_IOPRSTR_IOPDRST_Msk /*!< GPIO port D reset */
4209#define RCC_IOPRSTR_IOPERST_Pos (4U)
4210#define RCC_IOPRSTR_IOPERST_Msk (0x1U << RCC_IOPRSTR_IOPERST_Pos) /*!< 0x00000010 */
4211#define RCC_IOPRSTR_IOPERST RCC_IOPRSTR_IOPERST_Msk /*!< GPIO port E reset */
4212#define RCC_IOPRSTR_IOPHRST_Pos (7U)
4213#define RCC_IOPRSTR_IOPHRST_Msk (0x1U << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */
4214#define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */
4215
4216/* Reference defines */
4217#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
4218#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
4219#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
4220#define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_IOPDRST /*!< GPIO port D reset */
4221#define RCC_IOPRSTR_GPIOERST RCC_IOPRSTR_IOPERST /*!< GPIO port E reset */
4222#define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */
4223
4224
4225/****************** Bit definition for RCC_AHBRST register ******************/
4226#define RCC_AHBRSTR_DMARST_Pos (0U)
4227#define RCC_AHBRSTR_DMARST_Msk (0x1U << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */
4228#define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */
4229#define RCC_AHBRSTR_MIFRST_Pos (8U)
4230#define RCC_AHBRSTR_MIFRST_Msk (0x1U << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */
4231#define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset reset */
4232#define RCC_AHBRSTR_CRCRST_Pos (12U)
4233#define RCC_AHBRSTR_CRCRST_Msk (0x1U << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
4234#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */
4235#define RCC_AHBRSTR_TSCRST_Pos (16U)
4236#define RCC_AHBRSTR_TSCRST_Msk (0x1U << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x00010000 */
4237#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TSC reset */
4238#define RCC_AHBRSTR_RNGRST_Pos (20U)
4239#define RCC_AHBRSTR_RNGRST_Msk (0x1U << RCC_AHBRSTR_RNGRST_Pos) /*!< 0x00100000 */
4240#define RCC_AHBRSTR_RNGRST RCC_AHBRSTR_RNGRST_Msk /*!< RNG reset */
4241
4242/* Reference defines */
4243#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
4244
4245/***************** Bit definition for RCC_APB2RSTR register *****************/
4246#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
4247#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
4248#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */
4249#define RCC_APB2RSTR_TIM21RST_Pos (2U)
4250#define RCC_APB2RSTR_TIM21RST_Msk (0x1U << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */
4251#define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 clock reset */
4252#define RCC_APB2RSTR_TIM22RST_Pos (5U)
4253#define RCC_APB2RSTR_TIM22RST_Msk (0x1U << RCC_APB2RSTR_TIM22RST_Pos) /*!< 0x00000020 */
4254#define RCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_Msk /*!< TIM22 clock reset */
4255#define RCC_APB2RSTR_ADCRST_Pos (9U)
4256#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
4257#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 clock reset */
4258#define RCC_APB2RSTR_SPI1RST_Pos (12U)
4259#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
4260#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */
4261#define RCC_APB2RSTR_USART1RST_Pos (14U)
4262#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
4263#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */
4264#define RCC_APB2RSTR_DBGRST_Pos (22U)
4265#define RCC_APB2RSTR_DBGRST_Msk (0x1U << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */
4266#define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU clock reset */
4267
4268/* Reference defines */
4269#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 clock reset */
4270#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU clock reset */
4271
4272/***************** Bit definition for RCC_APB1RSTR register *****************/
4273#define RCC_APB1RSTR_TIM2RST_Pos (0U)
4274#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
4275#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */
4276#define RCC_APB1RSTR_TIM3RST_Pos (1U)
4277#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
4278#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */
4279#define RCC_APB1RSTR_TIM6RST_Pos (4U)
4280#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
4281#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */
4282#define RCC_APB1RSTR_TIM7RST_Pos (5U)
4283#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
4284#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 clock reset */
4285#define RCC_APB1RSTR_LCDRST_Pos (9U)
4286#define RCC_APB1RSTR_LCDRST_Msk (0x1U << RCC_APB1RSTR_LCDRST_Pos) /*!< 0x00000200 */
4287#define RCC_APB1RSTR_LCDRST RCC_APB1RSTR_LCDRST_Msk /*!< LCD clock reset */
4288#define RCC_APB1RSTR_WWDGRST_Pos (11U)
4289#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
4290#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */
4291#define RCC_APB1RSTR_SPI2RST_Pos (14U)
4292#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
4293#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */
4294#define RCC_APB1RSTR_USART2RST_Pos (17U)
4295#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
4296#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */
4297#define RCC_APB1RSTR_LPUART1RST_Pos (18U)
4298#define RCC_APB1RSTR_LPUART1RST_Msk (0x1U << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
4299#define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 clock reset */
4300#define RCC_APB1RSTR_USART4RST_Pos (19U)
4301#define RCC_APB1RSTR_USART4RST_Msk (0x1U << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */
4302#define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART4 clock reset */
4303#define RCC_APB1RSTR_USART5RST_Pos (20U)
4304#define RCC_APB1RSTR_USART5RST_Msk (0x1U << RCC_APB1RSTR_USART5RST_Pos) /*!< 0x00100000 */
4305#define RCC_APB1RSTR_USART5RST RCC_APB1RSTR_USART5RST_Msk /*!< USART5 clock reset */
4306#define RCC_APB1RSTR_I2C1RST_Pos (21U)
4307#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
4308#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */
4309#define RCC_APB1RSTR_I2C2RST_Pos (22U)
4310#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
4311#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */
4312#define RCC_APB1RSTR_USBRST_Pos (23U)
4313#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
4314#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB clock reset */
4315#define RCC_APB1RSTR_CRSRST_Pos (27U)
4316#define RCC_APB1RSTR_CRSRST_Msk (0x1U << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */
4317#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS clock reset */
4318#define RCC_APB1RSTR_PWRRST_Pos (28U)
4319#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
4320#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */
4321#define RCC_APB1RSTR_DACRST_Pos (29U)
4322#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
4323#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC clock reset */
4324#define RCC_APB1RSTR_I2C3RST_Pos (30U)
4325#define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x40000000 */
4326#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk /*!< I2C 3 clock reset */
4327#define RCC_APB1RSTR_LPTIM1RST_Pos (31U)
4328#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */
4329#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 clock reset */
4330
4331/***************** Bit definition for RCC_IOPENR register ******************/
4332#define RCC_IOPENR_IOPAEN_Pos (0U)
4333#define RCC_IOPENR_IOPAEN_Msk (0x1U << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */
4334#define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */
4335#define RCC_IOPENR_IOPBEN_Pos (1U)
4336#define RCC_IOPENR_IOPBEN_Msk (0x1U << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */
4337#define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */
4338#define RCC_IOPENR_IOPCEN_Pos (2U)
4339#define RCC_IOPENR_IOPCEN_Msk (0x1U << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */
4340#define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */
4341#define RCC_IOPENR_IOPDEN_Pos (3U)
4342#define RCC_IOPENR_IOPDEN_Msk (0x1U << RCC_IOPENR_IOPDEN_Pos) /*!< 0x00000008 */
4343#define RCC_IOPENR_IOPDEN RCC_IOPENR_IOPDEN_Msk /*!< GPIO port D clock enable */
4344#define RCC_IOPENR_IOPEEN_Pos (4U)
4345#define RCC_IOPENR_IOPEEN_Msk (0x1U << RCC_IOPENR_IOPEEN_Pos) /*!< 0x00000010 */
4346#define RCC_IOPENR_IOPEEN RCC_IOPENR_IOPEEN_Msk /*!< GPIO port E clock enable */
4347#define RCC_IOPENR_IOPHEN_Pos (7U)
4348#define RCC_IOPENR_IOPHEN_Msk (0x1U << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */
4349#define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */
4350
4351/* Reference defines */
4352#define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
4353#define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
4354#define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
4355#define RCC_IOPENR_GPIODEN RCC_IOPENR_IOPDEN /*!< GPIO port D clock enable */
4356#define RCC_IOPENR_GPIOEEN RCC_IOPENR_IOPEEN /*!< GPIO port E clock enable */
4357#define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */
4358
4359/***************** Bit definition for RCC_AHBENR register ******************/
4360#define RCC_AHBENR_DMAEN_Pos (0U)
4361#define RCC_AHBENR_DMAEN_Msk (0x1U << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
4362#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
4363#define RCC_AHBENR_MIFEN_Pos (8U)
4364#define RCC_AHBENR_MIFEN_Msk (0x1U << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */
4365#define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */
4366#define RCC_AHBENR_CRCEN_Pos (12U)
4367#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
4368#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
4369#define RCC_AHBENR_TSCEN_Pos (16U)
4370#define RCC_AHBENR_TSCEN_Msk (0x1U << RCC_AHBENR_TSCEN_Pos) /*!< 0x00010000 */
4371#define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TSC clock enable */
4372#define RCC_AHBENR_RNGEN_Pos (20U)
4373#define RCC_AHBENR_RNGEN_Msk (0x1U << RCC_AHBENR_RNGEN_Pos) /*!< 0x00100000 */
4374#define RCC_AHBENR_RNGEN RCC_AHBENR_RNGEN_Msk /*!< RNG clock enable */
4375
4376/* Reference defines */
4377#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
4378
4379/***************** Bit definition for RCC_APB2ENR register ******************/
4380#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
4381#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
4382#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */
4383#define RCC_APB2ENR_TIM21EN_Pos (2U)
4384#define RCC_APB2ENR_TIM21EN_Msk (0x1U << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */
4385#define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */
4386#define RCC_APB2ENR_TIM22EN_Pos (5U)
4387#define RCC_APB2ENR_TIM22EN_Msk (0x1U << RCC_APB2ENR_TIM22EN_Pos) /*!< 0x00000020 */
4388#define RCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_Msk /*!< TIM22 clock enable */
4389#define RCC_APB2ENR_FWEN_Pos (7U)
4390#define RCC_APB2ENR_FWEN_Msk (0x1U << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
4391#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */
4392#define RCC_APB2ENR_ADCEN_Pos (9U)
4393#define RCC_APB2ENR_ADCEN_Msk (0x1U << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
4394#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
4395#define RCC_APB2ENR_SPI1EN_Pos (12U)
4396#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
4397#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
4398#define RCC_APB2ENR_USART1EN_Pos (14U)
4399#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
4400#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
4401#define RCC_APB2ENR_DBGEN_Pos (22U)
4402#define RCC_APB2ENR_DBGEN_Msk (0x1U << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */
4403#define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */
4404
4405/* Reference defines */
4406
4407#define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
4408#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
4409#define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
4410
4411/***************** Bit definition for RCC_APB1ENR register ******************/
4412#define RCC_APB1ENR_TIM2EN_Pos (0U)
4413#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
4414#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
4415#define RCC_APB1ENR_TIM3EN_Pos (1U)
4416#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
4417#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
4418#define RCC_APB1ENR_TIM6EN_Pos (4U)
4419#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
4420#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
4421#define RCC_APB1ENR_TIM7EN_Pos (5U)
4422#define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
4423#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */
4424#define RCC_APB1ENR_LCDEN_Pos (9U)
4425#define RCC_APB1ENR_LCDEN_Msk (0x1U << RCC_APB1ENR_LCDEN_Pos) /*!< 0x00000200 */
4426#define RCC_APB1ENR_LCDEN RCC_APB1ENR_LCDEN_Msk /*!< LCD clock enable */
4427#define RCC_APB1ENR_WWDGEN_Pos (11U)
4428#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
4429#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
4430#define RCC_APB1ENR_SPI2EN_Pos (14U)
4431#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
4432#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */
4433#define RCC_APB1ENR_USART2EN_Pos (17U)
4434#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
4435#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
4436#define RCC_APB1ENR_LPUART1EN_Pos (18U)
4437#define RCC_APB1ENR_LPUART1EN_Msk (0x1U << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */
4438#define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */
4439#define RCC_APB1ENR_USART4EN_Pos (19U)
4440#define RCC_APB1ENR_USART4EN_Msk (0x1U << RCC_APB1ENR_USART4EN_Pos) /*!< 0x00080000 */
4441#define RCC_APB1ENR_USART4EN RCC_APB1ENR_USART4EN_Msk /*!< USART4 clock enable */
4442#define RCC_APB1ENR_USART5EN_Pos (20U)
4443#define RCC_APB1ENR_USART5EN_Msk (0x1U << RCC_APB1ENR_USART5EN_Pos) /*!< 0x00100000 */
4444#define RCC_APB1ENR_USART5EN RCC_APB1ENR_USART5EN_Msk /*!< USART5 clock enable */
4445#define RCC_APB1ENR_I2C1EN_Pos (21U)
4446#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
4447#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
4448#define RCC_APB1ENR_I2C2EN_Pos (22U)
4449#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
4450#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */
4451#define RCC_APB1ENR_USBEN_Pos (23U)
4452#define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
4453#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */
4454#define RCC_APB1ENR_CRSEN_Pos (27U)
4455#define RCC_APB1ENR_CRSEN_Msk (0x1U << RCC_APB1ENR_CRSEN_Pos) /*!< 0x08000000 */
4456#define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enable */
4457#define RCC_APB1ENR_PWREN_Pos (28U)
4458#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
4459#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
4460#define RCC_APB1ENR_DACEN_Pos (29U)
4461#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
4462#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC clock enable */
4463#define RCC_APB1ENR_I2C3EN_Pos (30U)
4464#define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x40000000 */
4465#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk /*!< I2C3 clock enable */
4466#define RCC_APB1ENR_LPTIM1EN_Pos (31U)
4467#define RCC_APB1ENR_LPTIM1EN_Msk (0x1U << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */
4468#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */
4469
4470/****************** Bit definition for RCC_IOPSMENR register ****************/
4471#define RCC_IOPSMENR_IOPASMEN_Pos (0U)
4472#define RCC_IOPSMENR_IOPASMEN_Msk (0x1U << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */
4473#define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */
4474#define RCC_IOPSMENR_IOPBSMEN_Pos (1U)
4475#define RCC_IOPSMENR_IOPBSMEN_Msk (0x1U << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */
4476#define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */
4477#define RCC_IOPSMENR_IOPCSMEN_Pos (2U)
4478#define RCC_IOPSMENR_IOPCSMEN_Msk (0x1U << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */
4479#define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */
4480#define RCC_IOPSMENR_IOPDSMEN_Pos (3U)
4481#define RCC_IOPSMENR_IOPDSMEN_Msk (0x1U << RCC_IOPSMENR_IOPDSMEN_Pos) /*!< 0x00000008 */
4482#define RCC_IOPSMENR_IOPDSMEN RCC_IOPSMENR_IOPDSMEN_Msk /*!< GPIO port D clock enabled in sleep mode */
4483#define RCC_IOPSMENR_IOPESMEN_Pos (4U)
4484#define RCC_IOPSMENR_IOPESMEN_Msk (0x1U << RCC_IOPSMENR_IOPESMEN_Pos) /*!< 0x00000010 */
4485#define RCC_IOPSMENR_IOPESMEN RCC_IOPSMENR_IOPESMEN_Msk /*!< GPIO port E clock enabled in sleep mode */
4486#define RCC_IOPSMENR_IOPHSMEN_Pos (7U)
4487#define RCC_IOPSMENR_IOPHSMEN_Msk (0x1U << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */
4488#define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */
4489
4490/* Reference defines */
4491#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
4492#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
4493#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
4494#define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_IOPDSMEN /*!< GPIO port D clock enabled in sleep mode */
4495#define RCC_IOPSMENR_GPIOESMEN RCC_IOPSMENR_IOPESMEN /*!< GPIO port E clock enabled in sleep mode */
4496#define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */
4497
4498/***************** Bit definition for RCC_AHBSMENR register ******************/
4499#define RCC_AHBSMENR_DMASMEN_Pos (0U)
4500#define RCC_AHBSMENR_DMASMEN_Msk (0x1U << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */
4501#define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */
4502#define RCC_AHBSMENR_MIFSMEN_Pos (8U)
4503#define RCC_AHBSMENR_MIFSMEN_Msk (0x1U << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */
4504#define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */
4505#define RCC_AHBSMENR_SRAMSMEN_Pos (9U)
4506#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1U << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */
4507#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */
4508#define RCC_AHBSMENR_CRCSMEN_Pos (12U)
4509#define RCC_AHBSMENR_CRCSMEN_Msk (0x1U << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */
4510#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */
4511#define RCC_AHBSMENR_TSCSMEN_Pos (16U)
4512#define RCC_AHBSMENR_TSCSMEN_Msk (0x1U << RCC_AHBSMENR_TSCSMEN_Pos) /*!< 0x00010000 */
4513#define RCC_AHBSMENR_TSCSMEN RCC_AHBSMENR_TSCSMEN_Msk /*!< TSC clock enabled in sleep mode */
4514#define RCC_AHBSMENR_RNGSMEN_Pos (20U)
4515#define RCC_AHBSMENR_RNGSMEN_Msk (0x1U << RCC_AHBSMENR_RNGSMEN_Pos) /*!< 0x00100000 */
4516#define RCC_AHBSMENR_RNGSMEN RCC_AHBSMENR_RNGSMEN_Msk /*!< RNG clock enabled in sleep mode */
4517
4518/* Reference defines */
4519#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
4520
4521/***************** Bit definition for RCC_APB2SMENR register ******************/
4522#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
4523#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
4524#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */
4525#define RCC_APB2SMENR_TIM21SMEN_Pos (2U)
4526#define RCC_APB2SMENR_TIM21SMEN_Msk (0x1U << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
4527#define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */
4528#define RCC_APB2SMENR_TIM22SMEN_Pos (5U)
4529#define RCC_APB2SMENR_TIM22SMEN_Msk (0x1U << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
4530#define RCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_Msk /*!< TIM22 clock enabled in sleep mode */
4531#define RCC_APB2SMENR_ADCSMEN_Pos (9U)
4532#define RCC_APB2SMENR_ADCSMEN_Msk (0x1U << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */
4533#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */
4534#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
4535#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
4536#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */
4537#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
4538#define RCC_APB2SMENR_USART1SMEN_Msk (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
4539#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk /*!< USART1 clock enabled in sleep mode */
4540#define RCC_APB2SMENR_DBGSMEN_Pos (22U)
4541#define RCC_APB2SMENR_DBGSMEN_Msk (0x1U << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */
4542#define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */
4543
4544/* Reference defines */
4545#define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
4546#define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
4547
4548/***************** Bit definition for RCC_APB1SMENR register ******************/
4549#define RCC_APB1SMENR_TIM2SMEN_Pos (0U)
4550#define RCC_APB1SMENR_TIM2SMEN_Msk (0x1U << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */
4551#define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */
4552#define RCC_APB1SMENR_TIM3SMEN_Pos (1U)
4553#define RCC_APB1SMENR_TIM3SMEN_Msk (0x1U << RCC_APB1SMENR_TIM3SMEN_Pos) /*!< 0x00000002 */
4554#define RCC_APB1SMENR_TIM3SMEN RCC_APB1SMENR_TIM3SMEN_Msk /*!< Timer 3 clock enabled in sleep mode */
4555#define RCC_APB1SMENR_TIM6SMEN_Pos (4U)
4556#define RCC_APB1SMENR_TIM6SMEN_Msk (0x1U << RCC_APB1SMENR_TIM6SMEN_Pos) /*!< 0x00000010 */
4557#define RCC_APB1SMENR_TIM6SMEN RCC_APB1SMENR_TIM6SMEN_Msk /*!< Timer 6 clock enabled in sleep mode */
4558#define RCC_APB1SMENR_TIM7SMEN_Pos (5U)
4559#define RCC_APB1SMENR_TIM7SMEN_Msk (0x1U << RCC_APB1SMENR_TIM7SMEN_Pos) /*!< 0x00000020 */
4560#define RCC_APB1SMENR_TIM7SMEN RCC_APB1SMENR_TIM7SMEN_Msk /*!< Timer 7 clock enabled in sleep mode */
4561#define RCC_APB1SMENR_LCDSMEN_Pos (9U)
4562#define RCC_APB1SMENR_LCDSMEN_Msk (0x1U << RCC_APB1SMENR_LCDSMEN_Pos) /*!< 0x00000200 */
4563#define RCC_APB1SMENR_LCDSMEN RCC_APB1SMENR_LCDSMEN_Msk /*!< LCD clock enabled in sleep mode */
4564#define RCC_APB1SMENR_WWDGSMEN_Pos (11U)
4565#define RCC_APB1SMENR_WWDGSMEN_Msk (0x1U << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */
4566#define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */
4567#define RCC_APB1SMENR_SPI2SMEN_Pos (14U)
4568#define RCC_APB1SMENR_SPI2SMEN_Msk (0x1U << RCC_APB1SMENR_SPI2SMEN_Pos) /*!< 0x00004000 */
4569#define RCC_APB1SMENR_SPI2SMEN RCC_APB1SMENR_SPI2SMEN_Msk /*!< SPI2 clock enabled in sleep mode */
4570#define RCC_APB1SMENR_USART2SMEN_Pos (17U)
4571#define RCC_APB1SMENR_USART2SMEN_Msk (0x1U << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
4572#define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */
4573#define RCC_APB1SMENR_LPUART1SMEN_Pos (18U)
4574#define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1U << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
4575#define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */
4576#define RCC_APB1SMENR_USART4SMEN_Pos (19U)
4577#define RCC_APB1SMENR_USART4SMEN_Msk (0x1U << RCC_APB1SMENR_USART4SMEN_Pos) /*!< 0x00080000 */
4578#define RCC_APB1SMENR_USART4SMEN RCC_APB1SMENR_USART4SMEN_Msk /*!< USART4 clock enabled in sleep mode */
4579#define RCC_APB1SMENR_USART5SMEN_Pos (20U)
4580#define RCC_APB1SMENR_USART5SMEN_Msk (0x1U << RCC_APB1SMENR_USART5SMEN_Pos) /*!< 0x00100000 */
4581#define RCC_APB1SMENR_USART5SMEN RCC_APB1SMENR_USART5SMEN_Msk /*!< USART5 clock enabled in sleep mode */
4582#define RCC_APB1SMENR_I2C1SMEN_Pos (21U)
4583#define RCC_APB1SMENR_I2C1SMEN_Msk (0x1U << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */
4584#define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */
4585#define RCC_APB1SMENR_I2C2SMEN_Pos (22U)
4586#define RCC_APB1SMENR_I2C2SMEN_Msk (0x1U << RCC_APB1SMENR_I2C2SMEN_Pos) /*!< 0x00400000 */
4587#define RCC_APB1SMENR_I2C2SMEN RCC_APB1SMENR_I2C2SMEN_Msk /*!< I2C2 clock enabled in sleep mode */
4588#define RCC_APB1SMENR_USBSMEN_Pos (23U)
4589#define RCC_APB1SMENR_USBSMEN_Msk (0x1U << RCC_APB1SMENR_USBSMEN_Pos) /*!< 0x00800000 */
4590#define RCC_APB1SMENR_USBSMEN RCC_APB1SMENR_USBSMEN_Msk /*!< USB clock enabled in sleep mode */
4591#define RCC_APB1SMENR_CRSSMEN_Pos (27U)
4592#define RCC_APB1SMENR_CRSSMEN_Msk (0x1U << RCC_APB1SMENR_CRSSMEN_Pos) /*!< 0x08000000 */
4593#define RCC_APB1SMENR_CRSSMEN RCC_APB1SMENR_CRSSMEN_Msk /*!< CRS clock enabled in sleep mode */
4594#define RCC_APB1SMENR_PWRSMEN_Pos (28U)
4595#define RCC_APB1SMENR_PWRSMEN_Msk (0x1U << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */
4596#define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */
4597#define RCC_APB1SMENR_DACSMEN_Pos (29U)
4598#define RCC_APB1SMENR_DACSMEN_Msk (0x1U << RCC_APB1SMENR_DACSMEN_Pos) /*!< 0x20000000 */
4599#define RCC_APB1SMENR_DACSMEN RCC_APB1SMENR_DACSMEN_Msk /*!< DAC clock enabled in sleep mode */
4600#define RCC_APB1SMENR_I2C3SMEN_Pos (30U)
4601#define RCC_APB1SMENR_I2C3SMEN_Msk (0x1U << RCC_APB1SMENR_I2C3SMEN_Pos) /*!< 0x40000000 */
4602#define RCC_APB1SMENR_I2C3SMEN RCC_APB1SMENR_I2C3SMEN_Msk /*!< I2C3 clock enabled in sleep mode */
4603#define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U)
4604#define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1U << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
4605#define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */
4606
4607/******************* Bit definition for RCC_CCIPR register *******************/
4608/*!< USART1 Clock source selection */
4609#define RCC_CCIPR_USART1SEL_Pos (0U)
4610#define RCC_CCIPR_USART1SEL_Msk (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
4611#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk /*!< USART1SEL[1:0] bits */
4612#define RCC_CCIPR_USART1SEL_0 (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
4613#define RCC_CCIPR_USART1SEL_1 (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
4614
4615/*!< USART2 Clock source selection */
4616#define RCC_CCIPR_USART2SEL_Pos (2U)
4617#define RCC_CCIPR_USART2SEL_Msk (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
4618#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */
4619#define RCC_CCIPR_USART2SEL_0 (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
4620#define RCC_CCIPR_USART2SEL_1 (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
4621
4622/*!< LPUART1 Clock source selection */
4623#define RCC_CCIPR_LPUART1SEL_Pos (10U)
4624#define RCC_CCIPR_LPUART1SEL_Msk (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
4625#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */
4626#define RCC_CCIPR_LPUART1SEL_0 (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */
4627#define RCC_CCIPR_LPUART1SEL_1 (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */
4628
4629/*!< I2C1 Clock source selection */
4630#define RCC_CCIPR_I2C1SEL_Pos (12U)
4631#define RCC_CCIPR_I2C1SEL_Msk (0x3U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
4632#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */
4633#define RCC_CCIPR_I2C1SEL_0 (0x1U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
4634#define RCC_CCIPR_I2C1SEL_1 (0x2U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
4635
4636/*!< I2C3 Clock source selection */
4637#define RCC_CCIPR_I2C3SEL_Pos (16U)
4638#define RCC_CCIPR_I2C3SEL_Msk (0x3U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
4639#define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk /*!< I2C3SEL [1:0] bits */
4640#define RCC_CCIPR_I2C3SEL_0 (0x1U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
4641#define RCC_CCIPR_I2C3SEL_1 (0x2U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
4642
4643/*!< LPTIM1 Clock source selection */
4644#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
4645#define RCC_CCIPR_LPTIM1SEL_Msk (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
4646#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */
4647#define RCC_CCIPR_LPTIM1SEL_0 (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
4648#define RCC_CCIPR_LPTIM1SEL_1 (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
4649
4650/*!< HSI48 Clock source selection */
4651#define RCC_CCIPR_HSI48SEL_Pos (26U)
4652#define RCC_CCIPR_HSI48SEL_Msk (0x1U << RCC_CCIPR_HSI48SEL_Pos) /*!< 0x04000000 */
4653#define RCC_CCIPR_HSI48SEL RCC_CCIPR_HSI48SEL_Msk /*!< HSI48 RC clock source selection bit for USB and RNG*/
4654
4655/* Legacy defines */
4656#define RCC_CCIPR_HSI48MSEL RCC_CCIPR_HSI48SEL
4657
4658/******************* Bit definition for RCC_CSR register *******************/
4659#define RCC_CSR_LSION_Pos (0U)
4660#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
4661#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
4662#define RCC_CSR_LSIRDY_Pos (1U)
4663#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
4664#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
4665
4666#define RCC_CSR_LSEON_Pos (8U)
4667#define RCC_CSR_LSEON_Msk (0x1U << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */
4668#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */
4669#define RCC_CSR_LSERDY_Pos (9U)
4670#define RCC_CSR_LSERDY_Msk (0x1U << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */
4671#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
4672#define RCC_CSR_LSEBYP_Pos (10U)
4673#define RCC_CSR_LSEBYP_Msk (0x1U << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */
4674#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
4675
4676#define RCC_CSR_LSEDRV_Pos (11U)
4677#define RCC_CSR_LSEDRV_Msk (0x3U << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */
4678#define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
4679#define RCC_CSR_LSEDRV_0 (0x1U << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */
4680#define RCC_CSR_LSEDRV_1 (0x2U << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */
4681
4682#define RCC_CSR_LSECSSON_Pos (13U)
4683#define RCC_CSR_LSECSSON_Msk (0x1U << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */
4684#define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */
4685#define RCC_CSR_LSECSSD_Pos (14U)
4686#define RCC_CSR_LSECSSD_Msk (0x1U << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
4687#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
4688
4689/*!< RTC congiguration */
4690#define RCC_CSR_RTCSEL_Pos (16U)
4691#define RCC_CSR_RTCSEL_Msk (0x3U << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
4692#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
4693#define RCC_CSR_RTCSEL_0 (0x1U << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
4694#define RCC_CSR_RTCSEL_1 (0x2U << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
4695
4696#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
4697#define RCC_CSR_RTCSEL_LSE_Pos (16U)
4698#define RCC_CSR_RTCSEL_LSE_Msk (0x1U << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
4699#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */
4700#define RCC_CSR_RTCSEL_LSI_Pos (17U)
4701#define RCC_CSR_RTCSEL_LSI_Msk (0x1U << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */
4702#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */
4703#define RCC_CSR_RTCSEL_HSE_Pos (16U)
4704#define RCC_CSR_RTCSEL_HSE_Msk (0x3U << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */
4705#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */
4706
4707#define RCC_CSR_RTCEN_Pos (18U)
4708#define RCC_CSR_RTCEN_Msk (0x1U << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */
4709#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */
4710#define RCC_CSR_RTCRST_Pos (19U)
4711#define RCC_CSR_RTCRST_Msk (0x1U << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */
4712#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */
4713
4714#define RCC_CSR_RMVF_Pos (23U)
4715#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
4716#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
4717#define RCC_CSR_FWRSTF_Pos (24U)
4718#define RCC_CSR_FWRSTF_Msk (0x1U << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
4719#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk /*!< Mifare Firewall reset flag */
4720#define RCC_CSR_OBLRSTF_Pos (25U)
4721#define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
4722#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
4723#define RCC_CSR_PINRSTF_Pos (26U)
4724#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
4725#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
4726#define RCC_CSR_PORRSTF_Pos (27U)
4727#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
4728#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
4729#define RCC_CSR_SFTRSTF_Pos (28U)
4730#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
4731#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
4732#define RCC_CSR_IWDGRSTF_Pos (29U)
4733#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
4734#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
4735#define RCC_CSR_WWDGRSTF_Pos (30U)
4736#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
4737#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
4738#define RCC_CSR_LPWRRSTF_Pos (31U)
4739#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
4740#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
4741
4742/* Reference defines */
4743#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
4744
4745
4746/******************************************************************************/
4747/* */
4748/* RNG */
4749/* */
4750/******************************************************************************/
4751/******************** Bits definition for RNG_CR register *******************/
4752#define RNG_CR_RNGEN_Pos (2U)
4753#define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
4754#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
4755#define RNG_CR_IE_Pos (3U)
4756#define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
4757#define RNG_CR_IE RNG_CR_IE_Msk
4758
4759/******************** Bits definition for RNG_SR register *******************/
4760#define RNG_SR_DRDY_Pos (0U)
4761#define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
4762#define RNG_SR_DRDY RNG_SR_DRDY_Msk
4763#define RNG_SR_CECS_Pos (1U)
4764#define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
4765#define RNG_SR_CECS RNG_SR_CECS_Msk
4766#define RNG_SR_SECS_Pos (2U)
4767#define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
4768#define RNG_SR_SECS RNG_SR_SECS_Msk
4769#define RNG_SR_CEIS_Pos (5U)
4770#define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
4771#define RNG_SR_CEIS RNG_SR_CEIS_Msk
4772#define RNG_SR_SEIS_Pos (6U)
4773#define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
4774#define RNG_SR_SEIS RNG_SR_SEIS_Msk
4775
4776/******************************************************************************/
4777/* */
4778/* Real-Time Clock (RTC) */
4779/* */
4780/******************************************************************************/
4781/*
4782* @brief Specific device feature definitions
4783*/
4784#define RTC_TAMPER1_SUPPORT
4785#define RTC_TAMPER2_SUPPORT
4786#define RTC_TAMPER3_SUPPORT
4787#define RTC_WAKEUP_SUPPORT
4788#define RTC_BACKUP_SUPPORT
4789
4790/******************** Bits definition for RTC_TR register *******************/
4791#define RTC_TR_PM_Pos (22U)
4792#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
4793#define RTC_TR_PM RTC_TR_PM_Msk /*!< */
4794#define RTC_TR_HT_Pos (20U)
4795#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
4796#define RTC_TR_HT RTC_TR_HT_Msk /*!< */
4797#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
4798#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
4799#define RTC_TR_HU_Pos (16U)
4800#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
4801#define RTC_TR_HU RTC_TR_HU_Msk /*!< */
4802#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
4803#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
4804#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
4805#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
4806#define RTC_TR_MNT_Pos (12U)
4807#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
4808#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */
4809#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
4810#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
4811#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
4812#define RTC_TR_MNU_Pos (8U)
4813#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
4814#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */
4815#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
4816#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
4817#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
4818#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
4819#define RTC_TR_ST_Pos (4U)
4820#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
4821#define RTC_TR_ST RTC_TR_ST_Msk /*!< */
4822#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
4823#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
4824#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
4825#define RTC_TR_SU_Pos (0U)
4826#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
4827#define RTC_TR_SU RTC_TR_SU_Msk /*!< */
4828#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
4829#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
4830#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
4831#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
4832
4833/******************** Bits definition for RTC_DR register *******************/
4834#define RTC_DR_YT_Pos (20U)
4835#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
4836#define RTC_DR_YT RTC_DR_YT_Msk /*!< */
4837#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
4838#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
4839#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
4840#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
4841#define RTC_DR_YU_Pos (16U)
4842#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
4843#define RTC_DR_YU RTC_DR_YU_Msk /*!< */
4844#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
4845#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
4846#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
4847#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
4848#define RTC_DR_WDU_Pos (13U)
4849#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
4850#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */
4851#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
4852#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
4853#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
4854#define RTC_DR_MT_Pos (12U)
4855#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
4856#define RTC_DR_MT RTC_DR_MT_Msk /*!< */
4857#define RTC_DR_MU_Pos (8U)
4858#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
4859#define RTC_DR_MU RTC_DR_MU_Msk /*!< */
4860#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
4861#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
4862#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
4863#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
4864#define RTC_DR_DT_Pos (4U)
4865#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
4866#define RTC_DR_DT RTC_DR_DT_Msk /*!< */
4867#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
4868#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
4869#define RTC_DR_DU_Pos (0U)
4870#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
4871#define RTC_DR_DU RTC_DR_DU_Msk /*!< */
4872#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
4873#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
4874#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
4875#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
4876
4877/******************** Bits definition for RTC_CR register *******************/
4878#define RTC_CR_COE_Pos (23U)
4879#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
4880#define RTC_CR_COE RTC_CR_COE_Msk /*!< */
4881#define RTC_CR_OSEL_Pos (21U)
4882#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
4883#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */
4884#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
4885#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
4886#define RTC_CR_POL_Pos (20U)
4887#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
4888#define RTC_CR_POL RTC_CR_POL_Msk /*!< */
4889#define RTC_CR_COSEL_Pos (19U)
4890#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
4891#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */
4892#define RTC_CR_BCK_Pos (18U)
4893#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
4894#define RTC_CR_BCK RTC_CR_BCK_Msk /*!< */
4895#define RTC_CR_SUB1H_Pos (17U)
4896#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
4897#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */
4898#define RTC_CR_ADD1H_Pos (16U)
4899#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
4900#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */
4901#define RTC_CR_TSIE_Pos (15U)
4902#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
4903#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */
4904#define RTC_CR_WUTIE_Pos (14U)
4905#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
4906#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */
4907#define RTC_CR_ALRBIE_Pos (13U)
4908#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
4909#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */
4910#define RTC_CR_ALRAIE_Pos (12U)
4911#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
4912#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */
4913#define RTC_CR_TSE_Pos (11U)
4914#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
4915#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */
4916#define RTC_CR_WUTE_Pos (10U)
4917#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
4918#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */
4919#define RTC_CR_ALRBE_Pos (9U)
4920#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
4921#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */
4922#define RTC_CR_ALRAE_Pos (8U)
4923#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
4924#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */
4925#define RTC_CR_FMT_Pos (6U)
4926#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
4927#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */
4928#define RTC_CR_BYPSHAD_Pos (5U)
4929#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
4930#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */
4931#define RTC_CR_REFCKON_Pos (4U)
4932#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
4933#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */
4934#define RTC_CR_TSEDGE_Pos (3U)
4935#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
4936#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */
4937#define RTC_CR_WUCKSEL_Pos (0U)
4938#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
4939#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */
4940#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
4941#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
4942#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
4943
4944/******************** Bits definition for RTC_ISR register ******************/
4945#define RTC_ISR_RECALPF_Pos (16U)
4946#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
4947#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */
4948#define RTC_ISR_TAMP3F_Pos (15U)
4949#define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
4950#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk /*!< */
4951#define RTC_ISR_TAMP2F_Pos (14U)
4952#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
4953#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */
4954#define RTC_ISR_TAMP1F_Pos (13U)
4955#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
4956#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */
4957#define RTC_ISR_TSOVF_Pos (12U)
4958#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
4959#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */
4960#define RTC_ISR_TSF_Pos (11U)
4961#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
4962#define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */
4963#define RTC_ISR_WUTF_Pos (10U)
4964#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
4965#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */
4966#define RTC_ISR_ALRBF_Pos (9U)
4967#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
4968#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */
4969#define RTC_ISR_ALRAF_Pos (8U)
4970#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
4971#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */
4972#define RTC_ISR_INIT_Pos (7U)
4973#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
4974#define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */
4975#define RTC_ISR_INITF_Pos (6U)
4976#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
4977#define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */
4978#define RTC_ISR_RSF_Pos (5U)
4979#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
4980#define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */
4981#define RTC_ISR_INITS_Pos (4U)
4982#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
4983#define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */
4984#define RTC_ISR_SHPF_Pos (3U)
4985#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
4986#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */
4987#define RTC_ISR_WUTWF_Pos (2U)
4988#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
4989#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */
4990#define RTC_ISR_ALRBWF_Pos (1U)
4991#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
4992#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */
4993#define RTC_ISR_ALRAWF_Pos (0U)
4994#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
4995#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */
4996
4997/******************** Bits definition for RTC_PRER register *****************/
4998#define RTC_PRER_PREDIV_A_Pos (16U)
4999#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
5000#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */
5001#define RTC_PRER_PREDIV_S_Pos (0U)
5002#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
5003#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */
5004
5005/******************** Bits definition for RTC_WUTR register *****************/
5006#define RTC_WUTR_WUT_Pos (0U)
5007#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
5008#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
5009
5010/******************** Bits definition for RTC_ALRMAR register ***************/
5011#define RTC_ALRMAR_MSK4_Pos (31U)
5012#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
5013#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */
5014#define RTC_ALRMAR_WDSEL_Pos (30U)
5015#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
5016#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */
5017#define RTC_ALRMAR_DT_Pos (28U)
5018#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
5019#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */
5020#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
5021#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
5022#define RTC_ALRMAR_DU_Pos (24U)
5023#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
5024#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */
5025#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
5026#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
5027#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
5028#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
5029#define RTC_ALRMAR_MSK3_Pos (23U)
5030#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
5031#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */
5032#define RTC_ALRMAR_PM_Pos (22U)
5033#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
5034#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */
5035#define RTC_ALRMAR_HT_Pos (20U)
5036#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
5037#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */
5038#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
5039#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
5040#define RTC_ALRMAR_HU_Pos (16U)
5041#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
5042#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */
5043#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
5044#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
5045#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
5046#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
5047#define RTC_ALRMAR_MSK2_Pos (15U)
5048#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
5049#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */
5050#define RTC_ALRMAR_MNT_Pos (12U)
5051#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
5052#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */
5053#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
5054#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
5055#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
5056#define RTC_ALRMAR_MNU_Pos (8U)
5057#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
5058#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */
5059#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
5060#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
5061#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
5062#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
5063#define RTC_ALRMAR_MSK1_Pos (7U)
5064#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
5065#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */
5066#define RTC_ALRMAR_ST_Pos (4U)
5067#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
5068#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */
5069#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
5070#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
5071#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
5072#define RTC_ALRMAR_SU_Pos (0U)
5073#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
5074#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */
5075#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
5076#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
5077#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
5078#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
5079
5080/******************** Bits definition for RTC_ALRMBR register ***************/
5081#define RTC_ALRMBR_MSK4_Pos (31U)
5082#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
5083#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */
5084#define RTC_ALRMBR_WDSEL_Pos (30U)
5085#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
5086#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */
5087#define RTC_ALRMBR_DT_Pos (28U)
5088#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
5089#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */
5090#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
5091#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
5092#define RTC_ALRMBR_DU_Pos (24U)
5093#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
5094#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */
5095#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
5096#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
5097#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
5098#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
5099#define RTC_ALRMBR_MSK3_Pos (23U)
5100#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
5101#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */
5102#define RTC_ALRMBR_PM_Pos (22U)
5103#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
5104#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */
5105#define RTC_ALRMBR_HT_Pos (20U)
5106#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
5107#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */
5108#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
5109#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
5110#define RTC_ALRMBR_HU_Pos (16U)
5111#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
5112#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */
5113#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
5114#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
5115#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
5116#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
5117#define RTC_ALRMBR_MSK2_Pos (15U)
5118#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
5119#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */
5120#define RTC_ALRMBR_MNT_Pos (12U)
5121#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
5122#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */
5123#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
5124#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
5125#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
5126#define RTC_ALRMBR_MNU_Pos (8U)
5127#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
5128#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */
5129#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
5130#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
5131#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
5132#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
5133#define RTC_ALRMBR_MSK1_Pos (7U)
5134#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
5135#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */
5136#define RTC_ALRMBR_ST_Pos (4U)
5137#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
5138#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */
5139#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
5140#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
5141#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
5142#define RTC_ALRMBR_SU_Pos (0U)
5143#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
5144#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */
5145#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
5146#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
5147#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
5148#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
5149
5150/******************** Bits definition for RTC_WPR register ******************/
5151#define RTC_WPR_KEY_Pos (0U)
5152#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
5153#define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */
5154
5155/******************** Bits definition for RTC_SSR register ******************/
5156#define RTC_SSR_SS_Pos (0U)
5157#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
5158#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */
5159
5160/******************** Bits definition for RTC_SHIFTR register ***************/
5161#define RTC_SHIFTR_SUBFS_Pos (0U)
5162#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
5163#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */
5164#define RTC_SHIFTR_ADD1S_Pos (31U)
5165#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
5166#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */
5167
5168/******************** Bits definition for RTC_TSTR register *****************/
5169#define RTC_TSTR_PM_Pos (22U)
5170#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
5171#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */
5172#define RTC_TSTR_HT_Pos (20U)
5173#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
5174#define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */
5175#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
5176#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
5177#define RTC_TSTR_HU_Pos (16U)
5178#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
5179#define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */
5180#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
5181#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
5182#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
5183#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
5184#define RTC_TSTR_MNT_Pos (12U)
5185#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
5186#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */
5187#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
5188#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
5189#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
5190#define RTC_TSTR_MNU_Pos (8U)
5191#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
5192#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */
5193#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
5194#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
5195#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
5196#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
5197#define RTC_TSTR_ST_Pos (4U)
5198#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
5199#define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */
5200#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
5201#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
5202#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
5203#define RTC_TSTR_SU_Pos (0U)
5204#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
5205#define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */
5206#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
5207#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
5208#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
5209#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
5210
5211/******************** Bits definition for RTC_TSDR register *****************/
5212#define RTC_TSDR_WDU_Pos (13U)
5213#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
5214#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */
5215#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
5216#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
5217#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
5218#define RTC_TSDR_MT_Pos (12U)
5219#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
5220#define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */
5221#define RTC_TSDR_MU_Pos (8U)
5222#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
5223#define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */
5224#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
5225#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
5226#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
5227#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
5228#define RTC_TSDR_DT_Pos (4U)
5229#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
5230#define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */
5231#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
5232#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
5233#define RTC_TSDR_DU_Pos (0U)
5234#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
5235#define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */
5236#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
5237#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
5238#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
5239#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
5240
5241/******************** Bits definition for RTC_TSSSR register ****************/
5242#define RTC_TSSSR_SS_Pos (0U)
5243#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
5244#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
5245
5246/******************** Bits definition for RTC_CALR register *****************/
5247#define RTC_CALR_CALP_Pos (15U)
5248#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
5249#define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */
5250#define RTC_CALR_CALW8_Pos (14U)
5251#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
5252#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */
5253#define RTC_CALR_CALW16_Pos (13U)
5254#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
5255#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */
5256#define RTC_CALR_CALM_Pos (0U)
5257#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
5258#define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */
5259#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
5260#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
5261#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
5262#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
5263#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
5264#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
5265#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
5266#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
5267#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
5268
5269/* Legacy defines */
5270#define RTC_CAL_CALP RTC_CALR_CALP
5271#define RTC_CAL_CALW8 RTC_CALR_CALW8
5272#define RTC_CAL_CALW16 RTC_CALR_CALW16
5273#define RTC_CAL_CALM RTC_CALR_CALM
5274#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
5275#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
5276#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
5277#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
5278#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
5279#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
5280#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
5281#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
5282#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
5283
5284/******************** Bits definition for RTC_TAMPCR register ****************/
5285#define RTC_TAMPCR_TAMP3MF_Pos (24U)
5286#define RTC_TAMPCR_TAMP3MF_Msk (0x1U << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
5287#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk /*!< */
5288#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
5289#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
5290#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk /*!< */
5291#define RTC_TAMPCR_TAMP3IE_Pos (22U)
5292#define RTC_TAMPCR_TAMP3IE_Msk (0x1U << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
5293#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk /*!< */
5294#define RTC_TAMPCR_TAMP2MF_Pos (21U)
5295#define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
5296#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */
5297#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
5298#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
5299#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */
5300#define RTC_TAMPCR_TAMP2IE_Pos (19U)
5301#define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
5302#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */
5303#define RTC_TAMPCR_TAMP1MF_Pos (18U)
5304#define RTC_TAMPCR_TAMP1MF_Msk (0x1U << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
5305#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */
5306#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
5307#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
5308#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */
5309#define RTC_TAMPCR_TAMP1IE_Pos (16U)
5310#define RTC_TAMPCR_TAMP1IE_Msk (0x1U << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
5311#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */
5312#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
5313#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
5314#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */
5315#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
5316#define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
5317#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */
5318#define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
5319#define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
5320#define RTC_TAMPCR_TAMPFLT_Pos (11U)
5321#define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
5322#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */
5323#define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
5324#define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
5325#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
5326#define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
5327#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */
5328#define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
5329#define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
5330#define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
5331#define RTC_TAMPCR_TAMPTS_Pos (7U)
5332#define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
5333#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */
5334#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
5335#define RTC_TAMPCR_TAMP3TRG_Msk (0x1U << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
5336#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk /*!< */
5337#define RTC_TAMPCR_TAMP3E_Pos (5U)
5338#define RTC_TAMPCR_TAMP3E_Msk (0x1U << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
5339#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk /*!< */
5340#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
5341#define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
5342#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */
5343#define RTC_TAMPCR_TAMP2E_Pos (3U)
5344#define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
5345#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */
5346#define RTC_TAMPCR_TAMPIE_Pos (2U)
5347#define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
5348#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */
5349#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
5350#define RTC_TAMPCR_TAMP1TRG_Msk (0x1U << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
5351#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */
5352#define RTC_TAMPCR_TAMP1E_Pos (0U)
5353#define RTC_TAMPCR_TAMP1E_Msk (0x1U << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
5354#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */
5355
5356/******************** Bits definition for RTC_ALRMASSR register *************/
5357#define RTC_ALRMASSR_MASKSS_Pos (24U)
5358#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
5359#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
5360#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
5361#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
5362#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
5363#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
5364#define RTC_ALRMASSR_SS_Pos (0U)
5365#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
5366#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
5367
5368/******************** Bits definition for RTC_ALRMBSSR register *************/
5369#define RTC_ALRMBSSR_MASKSS_Pos (24U)
5370#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
5371#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
5372#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
5373#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
5374#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
5375#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
5376#define RTC_ALRMBSSR_SS_Pos (0U)
5377#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
5378#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
5379
5380/******************** Bits definition for RTC_OR register ****************/
5381#define RTC_OR_OUT_RMP_Pos (1U)
5382#define RTC_OR_OUT_RMP_Msk (0x1U << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
5383#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */
5384#define RTC_OR_ALARMOUTTYPE_Pos (0U)
5385#define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
5386#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */
5387
5388/* Legacy defines */
5389#define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
5390
5391/******************** Bits definition for RTC_BKP0R register ****************/
5392#define RTC_BKP0R_Pos (0U)
5393#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
5394#define RTC_BKP0R RTC_BKP0R_Msk /*!< */
5395
5396/******************** Bits definition for RTC_BKP1R register ****************/
5397#define RTC_BKP1R_Pos (0U)
5398#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
5399#define RTC_BKP1R RTC_BKP1R_Msk /*!< */
5400
5401/******************** Bits definition for RTC_BKP2R register ****************/
5402#define RTC_BKP2R_Pos (0U)
5403#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
5404#define RTC_BKP2R RTC_BKP2R_Msk /*!< */
5405
5406/******************** Bits definition for RTC_BKP3R register ****************/
5407#define RTC_BKP3R_Pos (0U)
5408#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
5409#define RTC_BKP3R RTC_BKP3R_Msk /*!< */
5410
5411/******************** Bits definition for RTC_BKP4R register ****************/
5412#define RTC_BKP4R_Pos (0U)
5413#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
5414#define RTC_BKP4R RTC_BKP4R_Msk /*!< */
5415
5416/******************** Number of backup registers ******************************/
5417#define RTC_BKP_NUMBER (0x00000005U) /*!< */
5418
5419/******************************************************************************/
5420/* */
5421/* Serial Peripheral Interface (SPI) */
5422/* */
5423/******************************************************************************/
5424
5425/*
5426 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
5427 */
5428#define SPI_I2S_SUPPORT /*!< I2S support */
5429
5430/******************* Bit definition for SPI_CR1 register ********************/
5431#define SPI_CR1_CPHA_Pos (0U)
5432#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
5433#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
5434#define SPI_CR1_CPOL_Pos (1U)
5435#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
5436#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
5437#define SPI_CR1_MSTR_Pos (2U)
5438#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
5439#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
5440#define SPI_CR1_BR_Pos (3U)
5441#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
5442#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
5443#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
5444#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
5445#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
5446#define SPI_CR1_SPE_Pos (6U)
5447#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
5448#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
5449#define SPI_CR1_LSBFIRST_Pos (7U)
5450#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
5451#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
5452#define SPI_CR1_SSI_Pos (8U)
5453#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
5454#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
5455#define SPI_CR1_SSM_Pos (9U)
5456#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
5457#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
5458#define SPI_CR1_RXONLY_Pos (10U)
5459#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
5460#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
5461#define SPI_CR1_DFF_Pos (11U)
5462#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
5463#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
5464#define SPI_CR1_CRCNEXT_Pos (12U)
5465#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
5466#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
5467#define SPI_CR1_CRCEN_Pos (13U)
5468#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
5469#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
5470#define SPI_CR1_BIDIOE_Pos (14U)
5471#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
5472#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
5473#define SPI_CR1_BIDIMODE_Pos (15U)
5474#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
5475#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
5476
5477/******************* Bit definition for SPI_CR2 register ********************/
5478#define SPI_CR2_RXDMAEN_Pos (0U)
5479#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
5480#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
5481#define SPI_CR2_TXDMAEN_Pos (1U)
5482#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
5483#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
5484#define SPI_CR2_SSOE_Pos (2U)
5485#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
5486#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
5487#define SPI_CR2_FRF_Pos (4U)
5488#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
5489#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
5490#define SPI_CR2_ERRIE_Pos (5U)
5491#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
5492#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
5493#define SPI_CR2_RXNEIE_Pos (6U)
5494#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
5495#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
5496#define SPI_CR2_TXEIE_Pos (7U)
5497#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
5498#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
5499
5500/******************** Bit definition for SPI_SR register ********************/
5501#define SPI_SR_RXNE_Pos (0U)
5502#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
5503#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
5504#define SPI_SR_TXE_Pos (1U)
5505#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
5506#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
5507#define SPI_SR_CHSIDE_Pos (2U)
5508#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
5509#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
5510#define SPI_SR_UDR_Pos (3U)
5511#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
5512#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
5513#define SPI_SR_CRCERR_Pos (4U)
5514#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
5515#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
5516#define SPI_SR_MODF_Pos (5U)
5517#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
5518#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
5519#define SPI_SR_OVR_Pos (6U)
5520#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
5521#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
5522#define SPI_SR_BSY_Pos (7U)
5523#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
5524#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
5525#define SPI_SR_FRE_Pos (8U)
5526#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
5527#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
5528
5529/******************** Bit definition for SPI_DR register ********************/
5530#define SPI_DR_DR_Pos (0U)
5531#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
5532#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
5533
5534/******************* Bit definition for SPI_CRCPR register ******************/
5535#define SPI_CRCPR_CRCPOLY_Pos (0U)
5536#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
5537#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
5538
5539/****************** Bit definition for SPI_RXCRCR register ******************/
5540#define SPI_RXCRCR_RXCRC_Pos (0U)
5541#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
5542#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
5543
5544/****************** Bit definition for SPI_TXCRCR register ******************/
5545#define SPI_TXCRCR_TXCRC_Pos (0U)
5546#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
5547#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
5548
5549/****************** Bit definition for SPI_I2SCFGR register *****************/
5550#define SPI_I2SCFGR_CHLEN_Pos (0U)
5551#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
5552#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
5553#define SPI_I2SCFGR_DATLEN_Pos (1U)
5554#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
5555#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
5556#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
5557#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
5558#define SPI_I2SCFGR_CKPOL_Pos (3U)
5559#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
5560#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
5561#define SPI_I2SCFGR_I2SSTD_Pos (4U)
5562#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
5563#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
5564#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
5565#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
5566#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
5567#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
5568#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
5569#define SPI_I2SCFGR_I2SCFG_Pos (8U)
5570#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
5571#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
5572#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
5573#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
5574#define SPI_I2SCFGR_I2SE_Pos (10U)
5575#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
5576#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
5577#define SPI_I2SCFGR_I2SMOD_Pos (11U)
5578#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
5579#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
5580#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
5581#define SPI_I2SCFGR_ASTRTEN_Msk (0x1U << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
5582#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
5583/****************** Bit definition for SPI_I2SPR register *******************/
5584#define SPI_I2SPR_I2SDIV_Pos (0U)
5585#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
5586#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
5587#define SPI_I2SPR_ODD_Pos (8U)
5588#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
5589#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
5590#define SPI_I2SPR_MCKOE_Pos (9U)
5591#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
5592#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
5593
5594/******************************************************************************/
5595/* */
5596/* System Configuration (SYSCFG) */
5597/* */
5598/******************************************************************************/
5599/***************** Bit definition for SYSCFG_CFGR1 register ****************/
5600#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
5601#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
5602#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
5603#define SYSCFG_CFGR1_MEM_MODE_0 (0x1U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
5604#define SYSCFG_CFGR1_MEM_MODE_1 (0x2U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
5605#define SYSCFG_CFGR1_UFB_Pos (3U)
5606#define SYSCFG_CFGR1_UFB_Msk (0x1U << SYSCFG_CFGR1_UFB_Pos) /*!< 0x00000008 */
5607#define SYSCFG_CFGR1_UFB SYSCFG_CFGR1_UFB_Msk /*!< User bank swapping */
5608#define SYSCFG_CFGR1_BOOT_MODE_Pos (8U)
5609#define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
5610#define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */
5611#define SYSCFG_CFGR1_BOOT_MODE_0 (0x1U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
5612#define SYSCFG_CFGR1_BOOT_MODE_1 (0x2U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
5613
5614/***************** Bit definition for SYSCFG_CFGR2 register ****************/
5615#define SYSCFG_CFGR2_FWDISEN_Pos (0U)
5616#define SYSCFG_CFGR2_FWDISEN_Msk (0x1U << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
5617#define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */
5618#define SYSCFG_CFGR2_CAPA_Pos (1U)
5619#define SYSCFG_CFGR2_CAPA_Msk (0x1FU << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x0000003E */
5620#define SYSCFG_CFGR2_CAPA SYSCFG_CFGR2_CAPA_Msk /*!< Connection of internal Vlcd rail to external capacitors */
5621#define SYSCFG_CFGR2_CAPA_0 (0x01U << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000002 */
5622#define SYSCFG_CFGR2_CAPA_1 (0x02U << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000004 */
5623#define SYSCFG_CFGR2_CAPA_2 (0x04U << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000008 */
5624#define SYSCFG_CFGR2_CAPA_3 (0x08U << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000010 */
5625#define SYSCFG_CFGR2_CAPA_4 (0x10U << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000020 */
5626#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos (8U)
5627#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
5628#define SYSCFG_CFGR2_I2C_PB6_FMP SYSCFG_CFGR2_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
5629#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos (9U)
5630#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
5631#define SYSCFG_CFGR2_I2C_PB7_FMP SYSCFG_CFGR2_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
5632#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos (10U)
5633#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
5634#define SYSCFG_CFGR2_I2C_PB8_FMP SYSCFG_CFGR2_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
5635#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos (11U)
5636#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
5637#define SYSCFG_CFGR2_I2C_PB9_FMP SYSCFG_CFGR2_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
5638#define SYSCFG_CFGR2_I2C1_FMP_Pos (12U)
5639#define SYSCFG_CFGR2_I2C1_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
5640#define SYSCFG_CFGR2_I2C1_FMP SYSCFG_CFGR2_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
5641#define SYSCFG_CFGR2_I2C2_FMP_Pos (13U)
5642#define SYSCFG_CFGR2_I2C2_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
5643#define SYSCFG_CFGR2_I2C2_FMP SYSCFG_CFGR2_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
5644#define SYSCFG_CFGR2_I2C3_FMP_Pos (14U)
5645#define SYSCFG_CFGR2_I2C3_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C3_FMP_Pos) /*!< 0x00004000 */
5646#define SYSCFG_CFGR2_I2C3_FMP SYSCFG_CFGR2_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
5647
5648/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
5649#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
5650#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
5651#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
5652#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
5653#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
5654#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
5655#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
5656#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
5657#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
5658#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
5659#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
5660#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
5661
5662/**
5663 * @brief EXTI0 configuration
5664 */
5665#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
5666#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
5667#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
5668#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
5669#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */
5670#define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
5671
5672/**
5673 * @brief EXTI1 configuration
5674 */
5675#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
5676#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
5677#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
5678#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
5679#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */
5680#define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
5681
5682/**
5683 * @brief EXTI2 configuration
5684 */
5685#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
5686#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
5687#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
5688#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
5689#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */
5690
5691/**
5692 * @brief EXTI3 configuration
5693 */
5694#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
5695#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
5696#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
5697#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
5698#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
5699
5700/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
5701#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
5702#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
5703#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
5704#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
5705#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
5706#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
5707#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
5708#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
5709#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
5710#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
5711#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
5712#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
5713
5714/**
5715 * @brief EXTI4 configuration
5716 */
5717#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
5718#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
5719#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
5720#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
5721#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */
5722
5723/**
5724 * @brief EXTI5 configuration
5725 */
5726#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
5727#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
5728#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
5729#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
5730#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */
5731
5732/**
5733 * @brief EXTI6 configuration
5734 */
5735#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
5736#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
5737#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
5738#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
5739#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */
5740
5741/**
5742 * @brief EXTI7 configuration
5743 */
5744#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
5745#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
5746#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
5747#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
5748#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */
5749
5750/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
5751#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
5752#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
5753#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
5754#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
5755#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
5756#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
5757#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
5758#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
5759#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
5760#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
5761#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
5762#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
5763
5764/**
5765 * @brief EXTI8 configuration
5766 */
5767#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
5768#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
5769#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
5770#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
5771#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */
5772
5773/**
5774 * @brief EXTI9 configuration
5775 */
5776#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
5777#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
5778#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
5779#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
5780#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */
5781#define SYSCFG_EXTICR3_EXTI9_PH (0x00000050U) /*!< PH[9] pin */
5782
5783/**
5784 * @brief EXTI10 configuration
5785 */
5786#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
5787#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
5788#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
5789#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
5790#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */
5791#define SYSCFG_EXTICR3_EXTI10_PH (0x00000500U) /*!< PH[10] pin */
5792
5793/**
5794 * @brief EXTI11 configuration
5795 */
5796#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
5797#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
5798#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
5799#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
5800#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */
5801
5802/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
5803#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
5804#define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
5805#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
5806#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
5807#define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
5808#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
5809#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
5810#define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
5811#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
5812#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
5813#define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
5814#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
5815
5816/**
5817 * @brief EXTI12 configuration
5818 */
5819#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
5820#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
5821#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
5822#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
5823#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */
5824
5825/**
5826 * @brief EXTI13 configuration
5827 */
5828#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
5829#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
5830#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
5831#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
5832#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */
5833
5834/**
5835 * @brief EXTI14 configuration
5836 */
5837#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
5838#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
5839#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
5840#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
5841#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */
5842
5843/**
5844 * @brief EXTI15 configuration
5845 */
5846#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
5847#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
5848#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
5849#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
5850#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
5851
5852
5853/***************** Bit definition for SYSCFG_CFGR3 register ****************/
5854#define SYSCFG_CFGR3_VREF_OUT_Pos (4U)
5855#define SYSCFG_CFGR3_VREF_OUT_Msk (0x3U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
5856#define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */
5857#define SYSCFG_CFGR3_VREF_OUT_0 (0x1U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
5858#define SYSCFG_CFGR3_VREF_OUT_1 (0x2U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
5859#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U)
5860#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1U << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
5861#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
5862#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U)
5863#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1U << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
5864#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
5865#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U)
5866#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1U << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
5867#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
5868#define SYSCFG_CFGR3_ENREF_HSI48_Pos (13U)
5869#define SYSCFG_CFGR3_ENREF_HSI48_Msk (0x1U << SYSCFG_CFGR3_ENREF_HSI48_Pos) /*!< 0x00002000 */
5870#define SYSCFG_CFGR3_ENREF_HSI48 SYSCFG_CFGR3_ENREF_HSI48_Msk /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
5871#define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U)
5872#define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1U << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
5873#define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
5874#define SYSCFG_CFGR3_REF_LOCK_Pos (31U)
5875#define SYSCFG_CFGR3_REF_LOCK_Msk (0x1U << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
5876#define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */
5877
5878/* Legacy defines */
5879
5880#define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
5881#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
5882#define SYSCFG_CFGR3_ENREF_RC48MHz SYSCFG_CFGR3_ENREF_HSI48
5883#define SYSCFG_CFGR3_REF_RC48MHz_RDYF SYSCFG_CFGR3_VREFINT_RDYF
5884#define SYSCFG_CFGR3_REF_HSI48_RDYF SYSCFG_CFGR3_VREFINT_RDYF
5885#define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
5886#define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
5887#define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
5888#define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF
5889
5890/******************************************************************************/
5891/* */
5892/* Timers (TIM) */
5893/* */
5894/******************************************************************************/
5895/*
5896* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
5897*/
5898#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
5899 || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
5900#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
5901#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
5902#else
5903#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
5904#endif
5905
5906/******************* Bit definition for TIM_CR1 register ********************/
5907#define TIM_CR1_CEN_Pos (0U)
5908#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
5909#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
5910#define TIM_CR1_UDIS_Pos (1U)
5911#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
5912#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
5913#define TIM_CR1_URS_Pos (2U)
5914#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
5915#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
5916#define TIM_CR1_OPM_Pos (3U)
5917#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
5918#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
5919#define TIM_CR1_DIR_Pos (4U)
5920#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
5921#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
5922
5923#define TIM_CR1_CMS_Pos (5U)
5924#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
5925#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
5926#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
5927#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
5928
5929#define TIM_CR1_ARPE_Pos (7U)
5930#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
5931#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
5932
5933#define TIM_CR1_CKD_Pos (8U)
5934#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
5935#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
5936#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
5937#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
5938
5939/******************* Bit definition for TIM_CR2 register ********************/
5940#define TIM_CR2_CCDS_Pos (3U)
5941#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
5942#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
5943
5944#define TIM_CR2_MMS_Pos (4U)
5945#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
5946#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
5947#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
5948#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
5949#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
5950
5951#define TIM_CR2_TI1S_Pos (7U)
5952#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
5953#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
5954
5955/******************* Bit definition for TIM_SMCR register *******************/
5956#define TIM_SMCR_SMS_Pos (0U)
5957#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
5958#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
5959#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
5960#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
5961#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
5962
5963#define TIM_SMCR_OCCS_Pos (3U)
5964#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
5965#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
5966
5967#define TIM_SMCR_TS_Pos (4U)
5968#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
5969#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
5970#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
5971#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
5972#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
5973
5974#define TIM_SMCR_MSM_Pos (7U)
5975#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
5976#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
5977
5978#define TIM_SMCR_ETF_Pos (8U)
5979#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
5980#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
5981#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
5982#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
5983#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
5984#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
5985
5986#define TIM_SMCR_ETPS_Pos (12U)
5987#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
5988#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
5989#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
5990#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
5991
5992#define TIM_SMCR_ECE_Pos (14U)
5993#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
5994#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
5995#define TIM_SMCR_ETP_Pos (15U)
5996#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
5997#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
5998
5999/******************* Bit definition for TIM_DIER register *******************/
6000#define TIM_DIER_UIE_Pos (0U)
6001#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
6002#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
6003#define TIM_DIER_CC1IE_Pos (1U)
6004#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
6005#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
6006#define TIM_DIER_CC2IE_Pos (2U)
6007#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
6008#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
6009#define TIM_DIER_CC3IE_Pos (3U)
6010#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
6011#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
6012#define TIM_DIER_CC4IE_Pos (4U)
6013#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
6014#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
6015#define TIM_DIER_TIE_Pos (6U)
6016#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
6017#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
6018#define TIM_DIER_UDE_Pos (8U)
6019#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
6020#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
6021#define TIM_DIER_CC1DE_Pos (9U)
6022#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
6023#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
6024#define TIM_DIER_CC2DE_Pos (10U)
6025#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
6026#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
6027#define TIM_DIER_CC3DE_Pos (11U)
6028#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
6029#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
6030#define TIM_DIER_CC4DE_Pos (12U)
6031#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
6032#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
6033#define TIM_DIER_TDE_Pos (14U)
6034#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
6035#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
6036
6037/******************** Bit definition for TIM_SR register ********************/
6038#define TIM_SR_UIF_Pos (0U)
6039#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
6040#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
6041#define TIM_SR_CC1IF_Pos (1U)
6042#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
6043#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
6044#define TIM_SR_CC2IF_Pos (2U)
6045#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
6046#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
6047#define TIM_SR_CC3IF_Pos (3U)
6048#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
6049#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
6050#define TIM_SR_CC4IF_Pos (4U)
6051#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
6052#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
6053#define TIM_SR_TIF_Pos (6U)
6054#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
6055#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
6056#define TIM_SR_CC1OF_Pos (9U)
6057#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
6058#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
6059#define TIM_SR_CC2OF_Pos (10U)
6060#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
6061#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
6062#define TIM_SR_CC3OF_Pos (11U)
6063#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
6064#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
6065#define TIM_SR_CC4OF_Pos (12U)
6066#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
6067#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
6068
6069/******************* Bit definition for TIM_EGR register ********************/
6070#define TIM_EGR_UG_Pos (0U)
6071#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
6072#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
6073#define TIM_EGR_CC1G_Pos (1U)
6074#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
6075#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
6076#define TIM_EGR_CC2G_Pos (2U)
6077#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
6078#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
6079#define TIM_EGR_CC3G_Pos (3U)
6080#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
6081#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
6082#define TIM_EGR_CC4G_Pos (4U)
6083#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
6084#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
6085#define TIM_EGR_TG_Pos (6U)
6086#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
6087#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
6088
6089/****************** Bit definition for TIM_CCMR1 register *******************/
6090#define TIM_CCMR1_CC1S_Pos (0U)
6091#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
6092#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
6093#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
6094#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
6095
6096#define TIM_CCMR1_OC1FE_Pos (2U)
6097#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
6098#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
6099#define TIM_CCMR1_OC1PE_Pos (3U)
6100#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
6101#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
6102
6103#define TIM_CCMR1_OC1M_Pos (4U)
6104#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
6105#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
6106#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
6107#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
6108#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
6109
6110#define TIM_CCMR1_OC1CE_Pos (7U)
6111#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
6112#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
6113
6114#define TIM_CCMR1_CC2S_Pos (8U)
6115#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
6116#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
6117#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
6118#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
6119
6120#define TIM_CCMR1_OC2FE_Pos (10U)
6121#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
6122#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
6123#define TIM_CCMR1_OC2PE_Pos (11U)
6124#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
6125#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
6126
6127#define TIM_CCMR1_OC2M_Pos (12U)
6128#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
6129#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
6130#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
6131#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
6132#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
6133
6134#define TIM_CCMR1_OC2CE_Pos (15U)
6135#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
6136#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
6137
6138/*----------------------------------------------------------------------------*/
6139
6140#define TIM_CCMR1_IC1PSC_Pos (2U)
6141#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
6142#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
6143#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
6144#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
6145
6146#define TIM_CCMR1_IC1F_Pos (4U)
6147#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
6148#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
6149#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
6150#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
6151#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
6152#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
6153
6154#define TIM_CCMR1_IC2PSC_Pos (10U)
6155#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
6156#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
6157#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
6158#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
6159
6160#define TIM_CCMR1_IC2F_Pos (12U)
6161#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
6162#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
6163#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
6164#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
6165#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
6166#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
6167
6168/****************** Bit definition for TIM_CCMR2 register *******************/
6169#define TIM_CCMR2_CC3S_Pos (0U)
6170#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
6171#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
6172#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
6173#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
6174
6175#define TIM_CCMR2_OC3FE_Pos (2U)
6176#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
6177#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
6178#define TIM_CCMR2_OC3PE_Pos (3U)
6179#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
6180#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
6181
6182#define TIM_CCMR2_OC3M_Pos (4U)
6183#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
6184#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
6185#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
6186#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
6187#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
6188
6189#define TIM_CCMR2_OC3CE_Pos (7U)
6190#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
6191#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
6192
6193#define TIM_CCMR2_CC4S_Pos (8U)
6194#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
6195#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
6196#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
6197#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
6198
6199#define TIM_CCMR2_OC4FE_Pos (10U)
6200#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
6201#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
6202#define TIM_CCMR2_OC4PE_Pos (11U)
6203#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
6204#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
6205
6206#define TIM_CCMR2_OC4M_Pos (12U)
6207#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
6208#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
6209#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
6210#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
6211#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
6212
6213#define TIM_CCMR2_OC4CE_Pos (15U)
6214#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
6215#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
6216
6217/*----------------------------------------------------------------------------*/
6218
6219#define TIM_CCMR2_IC3PSC_Pos (2U)
6220#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
6221#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
6222#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
6223#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
6224
6225#define TIM_CCMR2_IC3F_Pos (4U)
6226#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
6227#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
6228#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
6229#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
6230#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
6231#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
6232
6233#define TIM_CCMR2_IC4PSC_Pos (10U)
6234#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
6235#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
6236#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
6237#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
6238
6239#define TIM_CCMR2_IC4F_Pos (12U)
6240#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
6241#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
6242#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
6243#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
6244#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
6245#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
6246
6247/******************* Bit definition for TIM_CCER register *******************/
6248#define TIM_CCER_CC1E_Pos (0U)
6249#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
6250#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
6251#define TIM_CCER_CC1P_Pos (1U)
6252#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
6253#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
6254#define TIM_CCER_CC1NP_Pos (3U)
6255#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
6256#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
6257#define TIM_CCER_CC2E_Pos (4U)
6258#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
6259#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
6260#define TIM_CCER_CC2P_Pos (5U)
6261#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
6262#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
6263#define TIM_CCER_CC2NP_Pos (7U)
6264#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
6265#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
6266#define TIM_CCER_CC3E_Pos (8U)
6267#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
6268#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
6269#define TIM_CCER_CC3P_Pos (9U)
6270#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
6271#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
6272#define TIM_CCER_CC3NP_Pos (11U)
6273#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
6274#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
6275#define TIM_CCER_CC4E_Pos (12U)
6276#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
6277#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
6278#define TIM_CCER_CC4P_Pos (13U)
6279#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
6280#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
6281#define TIM_CCER_CC4NP_Pos (15U)
6282#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
6283#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
6284
6285/******************* Bit definition for TIM_CNT register ********************/
6286#define TIM_CNT_CNT_Pos (0U)
6287#define TIM_CNT_CNT_Msk (0xFFFFU << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
6288#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
6289
6290/******************* Bit definition for TIM_PSC register ********************/
6291#define TIM_PSC_PSC_Pos (0U)
6292#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
6293#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
6294
6295/******************* Bit definition for TIM_ARR register ********************/
6296#define TIM_ARR_ARR_Pos (0U)
6297#define TIM_ARR_ARR_Msk (0xFFFFU << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
6298#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
6299
6300/******************* Bit definition for TIM_CCR1 register *******************/
6301#define TIM_CCR1_CCR1_Pos (0U)
6302#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
6303#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
6304
6305/******************* Bit definition for TIM_CCR2 register *******************/
6306#define TIM_CCR2_CCR2_Pos (0U)
6307#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
6308#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
6309
6310/******************* Bit definition for TIM_CCR3 register *******************/
6311#define TIM_CCR3_CCR3_Pos (0U)
6312#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
6313#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
6314
6315/******************* Bit definition for TIM_CCR4 register *******************/
6316#define TIM_CCR4_CCR4_Pos (0U)
6317#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
6318#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
6319
6320/******************* Bit definition for TIM_DCR register ********************/
6321#define TIM_DCR_DBA_Pos (0U)
6322#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
6323#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
6324#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
6325#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
6326#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
6327#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
6328#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
6329
6330#define TIM_DCR_DBL_Pos (8U)
6331#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
6332#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
6333#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
6334#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
6335#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
6336#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
6337#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
6338
6339/******************* Bit definition for TIM_DMAR register *******************/
6340#define TIM_DMAR_DMAB_Pos (0U)
6341#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
6342#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
6343
6344/******************* Bit definition for TIM_OR register *********************/
6345#define TIM2_OR_ETR_RMP_Pos (0U)
6346#define TIM2_OR_ETR_RMP_Msk (0x7U << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000007 */
6347#define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
6348#define TIM2_OR_ETR_RMP_0 (0x1U << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000001 */
6349#define TIM2_OR_ETR_RMP_1 (0x2U << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */
6350#define TIM2_OR_ETR_RMP_2 (0x4U << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000004 */
6351#define TIM2_OR_TI4_RMP_Pos (3U)
6352#define TIM2_OR_TI4_RMP_Msk (0x3U << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000018 */
6353#define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
6354#define TIM2_OR_TI4_RMP_0 (0x1U << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */
6355#define TIM2_OR_TI4_RMP_1 (0x2U << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000010 */
6356
6357#define TIM21_OR_ETR_RMP_Pos (0U)
6358#define TIM21_OR_ETR_RMP_Msk (0x3U << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000003 */
6359#define TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
6360#define TIM21_OR_ETR_RMP_0 (0x1U << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000001 */
6361#define TIM21_OR_ETR_RMP_1 (0x2U << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000002 */
6362#define TIM21_OR_TI1_RMP_Pos (2U)
6363#define TIM21_OR_TI1_RMP_Msk (0x7U << TIM21_OR_TI1_RMP_Pos) /*!< 0x0000001C */
6364#define TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
6365#define TIM21_OR_TI1_RMP_0 (0x1U << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000004 */
6366#define TIM21_OR_TI1_RMP_1 (0x2U << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000008 */
6367#define TIM21_OR_TI1_RMP_2 (0x4U << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000010 */
6368#define TIM21_OR_TI2_RMP_Pos (5U)
6369#define TIM21_OR_TI2_RMP_Msk (0x1U << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */
6370#define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */
6371
6372#define TIM22_OR_ETR_RMP_Pos (0U)
6373#define TIM22_OR_ETR_RMP_Msk (0x3U << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000003 */
6374#define TIM22_OR_ETR_RMP TIM22_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
6375#define TIM22_OR_ETR_RMP_0 (0x1U << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000001 */
6376#define TIM22_OR_ETR_RMP_1 (0x2U << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000002 */
6377#define TIM22_OR_TI1_RMP_Pos (2U)
6378#define TIM22_OR_TI1_RMP_Msk (0x3U << TIM22_OR_TI1_RMP_Pos) /*!< 0x0000000C */
6379#define TIM22_OR_TI1_RMP TIM22_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
6380#define TIM22_OR_TI1_RMP_0 (0x1U << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000004 */
6381#define TIM22_OR_TI1_RMP_1 (0x2U << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000008 */
6382
6383#define TIM3_OR_ETR_RMP_Pos (0U)
6384#define TIM3_OR_ETR_RMP_Msk (0x3U << TIM3_OR_ETR_RMP_Pos) /*!< 0x00000003 */
6385#define TIM3_OR_ETR_RMP TIM3_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM3 ETR remap) */
6386#define TIM3_OR_ETR_RMP_0 (0x1U << TIM3_OR_ETR_RMP_Pos) /*!< 0x00000001 */
6387#define TIM3_OR_ETR_RMP_1 (0x2U << TIM3_OR_ETR_RMP_Pos) /*!< 0x00000002 */
6388#define TIM3_OR_TI1_RMP_Pos (2U)
6389#define TIM3_OR_TI1_RMP_Msk (0x1U << TIM3_OR_TI1_RMP_Pos) /*!< 0x00000004 */
6390#define TIM3_OR_TI1_RMP TIM3_OR_TI1_RMP_Msk /*!<TI1_RMP[2] bit */
6391#define TIM3_OR_TI2_RMP_Pos (3U)
6392#define TIM3_OR_TI2_RMP_Msk (0x1U << TIM3_OR_TI2_RMP_Pos) /*!< 0x00000008 */
6393#define TIM3_OR_TI2_RMP TIM3_OR_TI2_RMP_Msk /*!<TI2_RMP[3] bit */
6394#define TIM3_OR_TI4_RMP_Pos (4U)
6395#define TIM3_OR_TI4_RMP_Msk (0x1U << TIM3_OR_TI4_RMP_Pos) /*!< 0x00000010 */
6396#define TIM3_OR_TI4_RMP TIM3_OR_TI4_RMP_Msk /*!<TI4_RMP[4] bit */
6397
6398
6399/******************************************************************************/
6400/* */
6401/* Touch Sensing Controller (TSC) */
6402/* */
6403/******************************************************************************/
6404/******************* Bit definition for TSC_CR register *********************/
6405#define TSC_CR_TSCE_Pos (0U)
6406#define TSC_CR_TSCE_Msk (0x1U << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
6407#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
6408#define TSC_CR_START_Pos (1U)
6409#define TSC_CR_START_Msk (0x1U << TSC_CR_START_Pos) /*!< 0x00000002 */
6410#define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
6411#define TSC_CR_AM_Pos (2U)
6412#define TSC_CR_AM_Msk (0x1U << TSC_CR_AM_Pos) /*!< 0x00000004 */
6413#define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
6414#define TSC_CR_SYNCPOL_Pos (3U)
6415#define TSC_CR_SYNCPOL_Msk (0x1U << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
6416#define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
6417#define TSC_CR_IODEF_Pos (4U)
6418#define TSC_CR_IODEF_Msk (0x1U << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
6419#define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
6420
6421#define TSC_CR_MCV_Pos (5U)
6422#define TSC_CR_MCV_Msk (0x7U << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
6423#define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
6424#define TSC_CR_MCV_0 (0x1U << TSC_CR_MCV_Pos) /*!< 0x00000020 */
6425#define TSC_CR_MCV_1 (0x2U << TSC_CR_MCV_Pos) /*!< 0x00000040 */
6426#define TSC_CR_MCV_2 (0x4U << TSC_CR_MCV_Pos) /*!< 0x00000080 */
6427
6428#define TSC_CR_PGPSC_Pos (12U)
6429#define TSC_CR_PGPSC_Msk (0x7U << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
6430#define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
6431#define TSC_CR_PGPSC_0 (0x1U << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
6432#define TSC_CR_PGPSC_1 (0x2U << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
6433#define TSC_CR_PGPSC_2 (0x4U << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
6434
6435#define TSC_CR_SSPSC_Pos (15U)
6436#define TSC_CR_SSPSC_Msk (0x1U << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
6437#define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
6438#define TSC_CR_SSE_Pos (16U)
6439#define TSC_CR_SSE_Msk (0x1U << TSC_CR_SSE_Pos) /*!< 0x00010000 */
6440#define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
6441
6442#define TSC_CR_SSD_Pos (17U)
6443#define TSC_CR_SSD_Msk (0x7FU << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
6444#define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
6445#define TSC_CR_SSD_0 (0x01U << TSC_CR_SSD_Pos) /*!< 0x00020000 */
6446#define TSC_CR_SSD_1 (0x02U << TSC_CR_SSD_Pos) /*!< 0x00040000 */
6447#define TSC_CR_SSD_2 (0x04U << TSC_CR_SSD_Pos) /*!< 0x00080000 */
6448#define TSC_CR_SSD_3 (0x08U << TSC_CR_SSD_Pos) /*!< 0x00100000 */
6449#define TSC_CR_SSD_4 (0x10U << TSC_CR_SSD_Pos) /*!< 0x00200000 */
6450#define TSC_CR_SSD_5 (0x20U << TSC_CR_SSD_Pos) /*!< 0x00400000 */
6451#define TSC_CR_SSD_6 (0x40U << TSC_CR_SSD_Pos) /*!< 0x00800000 */
6452
6453#define TSC_CR_CTPL_Pos (24U)
6454#define TSC_CR_CTPL_Msk (0xFU << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
6455#define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
6456#define TSC_CR_CTPL_0 (0x1U << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
6457#define TSC_CR_CTPL_1 (0x2U << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
6458#define TSC_CR_CTPL_2 (0x4U << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
6459#define TSC_CR_CTPL_3 (0x8U << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
6460
6461#define TSC_CR_CTPH_Pos (28U)
6462#define TSC_CR_CTPH_Msk (0xFU << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
6463#define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
6464#define TSC_CR_CTPH_0 (0x1U << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
6465#define TSC_CR_CTPH_1 (0x2U << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
6466#define TSC_CR_CTPH_2 (0x4U << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
6467#define TSC_CR_CTPH_3 (0x8U << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
6468
6469/******************* Bit definition for TSC_IER register ********************/
6470#define TSC_IER_EOAIE_Pos (0U)
6471#define TSC_IER_EOAIE_Msk (0x1U << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
6472#define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
6473#define TSC_IER_MCEIE_Pos (1U)
6474#define TSC_IER_MCEIE_Msk (0x1U << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
6475#define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
6476
6477/******************* Bit definition for TSC_ICR register ********************/
6478#define TSC_ICR_EOAIC_Pos (0U)
6479#define TSC_ICR_EOAIC_Msk (0x1U << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
6480#define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
6481#define TSC_ICR_MCEIC_Pos (1U)
6482#define TSC_ICR_MCEIC_Msk (0x1U << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
6483#define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
6484
6485/******************* Bit definition for TSC_ISR register ********************/
6486#define TSC_ISR_EOAF_Pos (0U)
6487#define TSC_ISR_EOAF_Msk (0x1U << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
6488#define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
6489#define TSC_ISR_MCEF_Pos (1U)
6490#define TSC_ISR_MCEF_Msk (0x1U << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
6491#define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
6492
6493/******************* Bit definition for TSC_IOHCR register ******************/
6494#define TSC_IOHCR_G1_IO1_Pos (0U)
6495#define TSC_IOHCR_G1_IO1_Msk (0x1U << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
6496#define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
6497#define TSC_IOHCR_G1_IO2_Pos (1U)
6498#define TSC_IOHCR_G1_IO2_Msk (0x1U << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
6499#define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
6500#define TSC_IOHCR_G1_IO3_Pos (2U)
6501#define TSC_IOHCR_G1_IO3_Msk (0x1U << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
6502#define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
6503#define TSC_IOHCR_G1_IO4_Pos (3U)
6504#define TSC_IOHCR_G1_IO4_Msk (0x1U << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
6505#define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
6506#define TSC_IOHCR_G2_IO1_Pos (4U)
6507#define TSC_IOHCR_G2_IO1_Msk (0x1U << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
6508#define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
6509#define TSC_IOHCR_G2_IO2_Pos (5U)
6510#define TSC_IOHCR_G2_IO2_Msk (0x1U << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
6511#define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
6512#define TSC_IOHCR_G2_IO3_Pos (6U)
6513#define TSC_IOHCR_G2_IO3_Msk (0x1U << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
6514#define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
6515#define TSC_IOHCR_G2_IO4_Pos (7U)
6516#define TSC_IOHCR_G2_IO4_Msk (0x1U << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
6517#define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
6518#define TSC_IOHCR_G3_IO1_Pos (8U)
6519#define TSC_IOHCR_G3_IO1_Msk (0x1U << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
6520#define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
6521#define TSC_IOHCR_G3_IO2_Pos (9U)
6522#define TSC_IOHCR_G3_IO2_Msk (0x1U << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
6523#define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
6524#define TSC_IOHCR_G3_IO3_Pos (10U)
6525#define TSC_IOHCR_G3_IO3_Msk (0x1U << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
6526#define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
6527#define TSC_IOHCR_G3_IO4_Pos (11U)
6528#define TSC_IOHCR_G3_IO4_Msk (0x1U << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
6529#define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
6530#define TSC_IOHCR_G4_IO1_Pos (12U)
6531#define TSC_IOHCR_G4_IO1_Msk (0x1U << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
6532#define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
6533#define TSC_IOHCR_G4_IO2_Pos (13U)
6534#define TSC_IOHCR_G4_IO2_Msk (0x1U << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
6535#define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
6536#define TSC_IOHCR_G4_IO3_Pos (14U)
6537#define TSC_IOHCR_G4_IO3_Msk (0x1U << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
6538#define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
6539#define TSC_IOHCR_G4_IO4_Pos (15U)
6540#define TSC_IOHCR_G4_IO4_Msk (0x1U << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
6541#define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
6542#define TSC_IOHCR_G5_IO1_Pos (16U)
6543#define TSC_IOHCR_G5_IO1_Msk (0x1U << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
6544#define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
6545#define TSC_IOHCR_G5_IO2_Pos (17U)
6546#define TSC_IOHCR_G5_IO2_Msk (0x1U << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
6547#define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
6548#define TSC_IOHCR_G5_IO3_Pos (18U)
6549#define TSC_IOHCR_G5_IO3_Msk (0x1U << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
6550#define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
6551#define TSC_IOHCR_G5_IO4_Pos (19U)
6552#define TSC_IOHCR_G5_IO4_Msk (0x1U << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
6553#define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
6554#define TSC_IOHCR_G6_IO1_Pos (20U)
6555#define TSC_IOHCR_G6_IO1_Msk (0x1U << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
6556#define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
6557#define TSC_IOHCR_G6_IO2_Pos (21U)
6558#define TSC_IOHCR_G6_IO2_Msk (0x1U << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
6559#define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
6560#define TSC_IOHCR_G6_IO3_Pos (22U)
6561#define TSC_IOHCR_G6_IO3_Msk (0x1U << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
6562#define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
6563#define TSC_IOHCR_G6_IO4_Pos (23U)
6564#define TSC_IOHCR_G6_IO4_Msk (0x1U << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
6565#define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
6566#define TSC_IOHCR_G7_IO1_Pos (24U)
6567#define TSC_IOHCR_G7_IO1_Msk (0x1U << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
6568#define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
6569#define TSC_IOHCR_G7_IO2_Pos (25U)
6570#define TSC_IOHCR_G7_IO2_Msk (0x1U << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
6571#define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
6572#define TSC_IOHCR_G7_IO3_Pos (26U)
6573#define TSC_IOHCR_G7_IO3_Msk (0x1U << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
6574#define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
6575#define TSC_IOHCR_G7_IO4_Pos (27U)
6576#define TSC_IOHCR_G7_IO4_Msk (0x1U << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
6577#define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
6578#define TSC_IOHCR_G8_IO1_Pos (28U)
6579#define TSC_IOHCR_G8_IO1_Msk (0x1U << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */
6580#define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
6581#define TSC_IOHCR_G8_IO2_Pos (29U)
6582#define TSC_IOHCR_G8_IO2_Msk (0x1U << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */
6583#define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
6584#define TSC_IOHCR_G8_IO3_Pos (30U)
6585#define TSC_IOHCR_G8_IO3_Msk (0x1U << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */
6586#define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
6587#define TSC_IOHCR_G8_IO4_Pos (31U)
6588#define TSC_IOHCR_G8_IO4_Msk (0x1U << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */
6589#define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
6590
6591/******************* Bit definition for TSC_IOASCR register *****************/
6592#define TSC_IOASCR_G1_IO1_Pos (0U)
6593#define TSC_IOASCR_G1_IO1_Msk (0x1U << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
6594#define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
6595#define TSC_IOASCR_G1_IO2_Pos (1U)
6596#define TSC_IOASCR_G1_IO2_Msk (0x1U << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
6597#define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
6598#define TSC_IOASCR_G1_IO3_Pos (2U)
6599#define TSC_IOASCR_G1_IO3_Msk (0x1U << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
6600#define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
6601#define TSC_IOASCR_G1_IO4_Pos (3U)
6602#define TSC_IOASCR_G1_IO4_Msk (0x1U << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
6603#define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
6604#define TSC_IOASCR_G2_IO1_Pos (4U)
6605#define TSC_IOASCR_G2_IO1_Msk (0x1U << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
6606#define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
6607#define TSC_IOASCR_G2_IO2_Pos (5U)
6608#define TSC_IOASCR_G2_IO2_Msk (0x1U << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
6609#define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
6610#define TSC_IOASCR_G2_IO3_Pos (6U)
6611#define TSC_IOASCR_G2_IO3_Msk (0x1U << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
6612#define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
6613#define TSC_IOASCR_G2_IO4_Pos (7U)
6614#define TSC_IOASCR_G2_IO4_Msk (0x1U << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
6615#define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
6616#define TSC_IOASCR_G3_IO1_Pos (8U)
6617#define TSC_IOASCR_G3_IO1_Msk (0x1U << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
6618#define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
6619#define TSC_IOASCR_G3_IO2_Pos (9U)
6620#define TSC_IOASCR_G3_IO2_Msk (0x1U << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
6621#define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
6622#define TSC_IOASCR_G3_IO3_Pos (10U)
6623#define TSC_IOASCR_G3_IO3_Msk (0x1U << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
6624#define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
6625#define TSC_IOASCR_G3_IO4_Pos (11U)
6626#define TSC_IOASCR_G3_IO4_Msk (0x1U << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
6627#define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
6628#define TSC_IOASCR_G4_IO1_Pos (12U)
6629#define TSC_IOASCR_G4_IO1_Msk (0x1U << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
6630#define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
6631#define TSC_IOASCR_G4_IO2_Pos (13U)
6632#define TSC_IOASCR_G4_IO2_Msk (0x1U << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
6633#define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
6634#define TSC_IOASCR_G4_IO3_Pos (14U)
6635#define TSC_IOASCR_G4_IO3_Msk (0x1U << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
6636#define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
6637#define TSC_IOASCR_G4_IO4_Pos (15U)
6638#define TSC_IOASCR_G4_IO4_Msk (0x1U << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
6639#define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
6640#define TSC_IOASCR_G5_IO1_Pos (16U)
6641#define TSC_IOASCR_G5_IO1_Msk (0x1U << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
6642#define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
6643#define TSC_IOASCR_G5_IO2_Pos (17U)
6644#define TSC_IOASCR_G5_IO2_Msk (0x1U << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
6645#define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
6646#define TSC_IOASCR_G5_IO3_Pos (18U)
6647#define TSC_IOASCR_G5_IO3_Msk (0x1U << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
6648#define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
6649#define TSC_IOASCR_G5_IO4_Pos (19U)
6650#define TSC_IOASCR_G5_IO4_Msk (0x1U << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
6651#define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
6652#define TSC_IOASCR_G6_IO1_Pos (20U)
6653#define TSC_IOASCR_G6_IO1_Msk (0x1U << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
6654#define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
6655#define TSC_IOASCR_G6_IO2_Pos (21U)
6656#define TSC_IOASCR_G6_IO2_Msk (0x1U << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
6657#define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
6658#define TSC_IOASCR_G6_IO3_Pos (22U)
6659#define TSC_IOASCR_G6_IO3_Msk (0x1U << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
6660#define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
6661#define TSC_IOASCR_G6_IO4_Pos (23U)
6662#define TSC_IOASCR_G6_IO4_Msk (0x1U << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
6663#define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
6664#define TSC_IOASCR_G7_IO1_Pos (24U)
6665#define TSC_IOASCR_G7_IO1_Msk (0x1U << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
6666#define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
6667#define TSC_IOASCR_G7_IO2_Pos (25U)
6668#define TSC_IOASCR_G7_IO2_Msk (0x1U << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
6669#define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
6670#define TSC_IOASCR_G7_IO3_Pos (26U)
6671#define TSC_IOASCR_G7_IO3_Msk (0x1U << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
6672#define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
6673#define TSC_IOASCR_G7_IO4_Pos (27U)
6674#define TSC_IOASCR_G7_IO4_Msk (0x1U << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
6675#define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
6676#define TSC_IOASCR_G8_IO1_Pos (28U)
6677#define TSC_IOASCR_G8_IO1_Msk (0x1U << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */
6678#define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */
6679#define TSC_IOASCR_G8_IO2_Pos (29U)
6680#define TSC_IOASCR_G8_IO2_Msk (0x1U << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */
6681#define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */
6682#define TSC_IOASCR_G8_IO3_Pos (30U)
6683#define TSC_IOASCR_G8_IO3_Msk (0x1U << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */
6684#define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */
6685#define TSC_IOASCR_G8_IO4_Pos (31U)
6686#define TSC_IOASCR_G8_IO4_Msk (0x1U << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */
6687#define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */
6688
6689/******************* Bit definition for TSC_IOSCR register ******************/
6690#define TSC_IOSCR_G1_IO1_Pos (0U)
6691#define TSC_IOSCR_G1_IO1_Msk (0x1U << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
6692#define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
6693#define TSC_IOSCR_G1_IO2_Pos (1U)
6694#define TSC_IOSCR_G1_IO2_Msk (0x1U << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
6695#define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
6696#define TSC_IOSCR_G1_IO3_Pos (2U)
6697#define TSC_IOSCR_G1_IO3_Msk (0x1U << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
6698#define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
6699#define TSC_IOSCR_G1_IO4_Pos (3U)
6700#define TSC_IOSCR_G1_IO4_Msk (0x1U << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
6701#define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
6702#define TSC_IOSCR_G2_IO1_Pos (4U)
6703#define TSC_IOSCR_G2_IO1_Msk (0x1U << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
6704#define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
6705#define TSC_IOSCR_G2_IO2_Pos (5U)
6706#define TSC_IOSCR_G2_IO2_Msk (0x1U << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
6707#define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
6708#define TSC_IOSCR_G2_IO3_Pos (6U)
6709#define TSC_IOSCR_G2_IO3_Msk (0x1U << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
6710#define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
6711#define TSC_IOSCR_G2_IO4_Pos (7U)
6712#define TSC_IOSCR_G2_IO4_Msk (0x1U << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
6713#define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
6714#define TSC_IOSCR_G3_IO1_Pos (8U)
6715#define TSC_IOSCR_G3_IO1_Msk (0x1U << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
6716#define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
6717#define TSC_IOSCR_G3_IO2_Pos (9U)
6718#define TSC_IOSCR_G3_IO2_Msk (0x1U << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
6719#define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
6720#define TSC_IOSCR_G3_IO3_Pos (10U)
6721#define TSC_IOSCR_G3_IO3_Msk (0x1U << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
6722#define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
6723#define TSC_IOSCR_G3_IO4_Pos (11U)
6724#define TSC_IOSCR_G3_IO4_Msk (0x1U << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
6725#define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
6726#define TSC_IOSCR_G4_IO1_Pos (12U)
6727#define TSC_IOSCR_G4_IO1_Msk (0x1U << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
6728#define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
6729#define TSC_IOSCR_G4_IO2_Pos (13U)
6730#define TSC_IOSCR_G4_IO2_Msk (0x1U << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
6731#define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
6732#define TSC_IOSCR_G4_IO3_Pos (14U)
6733#define TSC_IOSCR_G4_IO3_Msk (0x1U << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
6734#define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
6735#define TSC_IOSCR_G4_IO4_Pos (15U)
6736#define TSC_IOSCR_G4_IO4_Msk (0x1U << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
6737#define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
6738#define TSC_IOSCR_G5_IO1_Pos (16U)
6739#define TSC_IOSCR_G5_IO1_Msk (0x1U << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
6740#define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
6741#define TSC_IOSCR_G5_IO2_Pos (17U)
6742#define TSC_IOSCR_G5_IO2_Msk (0x1U << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
6743#define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
6744#define TSC_IOSCR_G5_IO3_Pos (18U)
6745#define TSC_IOSCR_G5_IO3_Msk (0x1U << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
6746#define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
6747#define TSC_IOSCR_G5_IO4_Pos (19U)
6748#define TSC_IOSCR_G5_IO4_Msk (0x1U << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
6749#define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
6750#define TSC_IOSCR_G6_IO1_Pos (20U)
6751#define TSC_IOSCR_G6_IO1_Msk (0x1U << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
6752#define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
6753#define TSC_IOSCR_G6_IO2_Pos (21U)
6754#define TSC_IOSCR_G6_IO2_Msk (0x1U << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
6755#define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
6756#define TSC_IOSCR_G6_IO3_Pos (22U)
6757#define TSC_IOSCR_G6_IO3_Msk (0x1U << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
6758#define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
6759#define TSC_IOSCR_G6_IO4_Pos (23U)
6760#define TSC_IOSCR_G6_IO4_Msk (0x1U << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
6761#define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
6762#define TSC_IOSCR_G7_IO1_Pos (24U)
6763#define TSC_IOSCR_G7_IO1_Msk (0x1U << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
6764#define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
6765#define TSC_IOSCR_G7_IO2_Pos (25U)
6766#define TSC_IOSCR_G7_IO2_Msk (0x1U << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
6767#define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
6768#define TSC_IOSCR_G7_IO3_Pos (26U)
6769#define TSC_IOSCR_G7_IO3_Msk (0x1U << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
6770#define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
6771#define TSC_IOSCR_G7_IO4_Pos (27U)
6772#define TSC_IOSCR_G7_IO4_Msk (0x1U << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
6773#define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
6774#define TSC_IOSCR_G8_IO1_Pos (28U)
6775#define TSC_IOSCR_G8_IO1_Msk (0x1U << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */
6776#define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */
6777#define TSC_IOSCR_G8_IO2_Pos (29U)
6778#define TSC_IOSCR_G8_IO2_Msk (0x1U << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */
6779#define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */
6780#define TSC_IOSCR_G8_IO3_Pos (30U)
6781#define TSC_IOSCR_G8_IO3_Msk (0x1U << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */
6782#define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */
6783#define TSC_IOSCR_G8_IO4_Pos (31U)
6784#define TSC_IOSCR_G8_IO4_Msk (0x1U << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */
6785#define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */
6786
6787/******************* Bit definition for TSC_IOCCR register ******************/
6788#define TSC_IOCCR_G1_IO1_Pos (0U)
6789#define TSC_IOCCR_G1_IO1_Msk (0x1U << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
6790#define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
6791#define TSC_IOCCR_G1_IO2_Pos (1U)
6792#define TSC_IOCCR_G1_IO2_Msk (0x1U << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
6793#define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
6794#define TSC_IOCCR_G1_IO3_Pos (2U)
6795#define TSC_IOCCR_G1_IO3_Msk (0x1U << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
6796#define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
6797#define TSC_IOCCR_G1_IO4_Pos (3U)
6798#define TSC_IOCCR_G1_IO4_Msk (0x1U << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
6799#define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
6800#define TSC_IOCCR_G2_IO1_Pos (4U)
6801#define TSC_IOCCR_G2_IO1_Msk (0x1U << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
6802#define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
6803#define TSC_IOCCR_G2_IO2_Pos (5U)
6804#define TSC_IOCCR_G2_IO2_Msk (0x1U << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
6805#define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
6806#define TSC_IOCCR_G2_IO3_Pos (6U)
6807#define TSC_IOCCR_G2_IO3_Msk (0x1U << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
6808#define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
6809#define TSC_IOCCR_G2_IO4_Pos (7U)
6810#define TSC_IOCCR_G2_IO4_Msk (0x1U << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
6811#define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
6812#define TSC_IOCCR_G3_IO1_Pos (8U)
6813#define TSC_IOCCR_G3_IO1_Msk (0x1U << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
6814#define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
6815#define TSC_IOCCR_G3_IO2_Pos (9U)
6816#define TSC_IOCCR_G3_IO2_Msk (0x1U << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
6817#define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
6818#define TSC_IOCCR_G3_IO3_Pos (10U)
6819#define TSC_IOCCR_G3_IO3_Msk (0x1U << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
6820#define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
6821#define TSC_IOCCR_G3_IO4_Pos (11U)
6822#define TSC_IOCCR_G3_IO4_Msk (0x1U << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
6823#define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
6824#define TSC_IOCCR_G4_IO1_Pos (12U)
6825#define TSC_IOCCR_G4_IO1_Msk (0x1U << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
6826#define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
6827#define TSC_IOCCR_G4_IO2_Pos (13U)
6828#define TSC_IOCCR_G4_IO2_Msk (0x1U << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
6829#define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
6830#define TSC_IOCCR_G4_IO3_Pos (14U)
6831#define TSC_IOCCR_G4_IO3_Msk (0x1U << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
6832#define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
6833#define TSC_IOCCR_G4_IO4_Pos (15U)
6834#define TSC_IOCCR_G4_IO4_Msk (0x1U << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
6835#define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
6836#define TSC_IOCCR_G5_IO1_Pos (16U)
6837#define TSC_IOCCR_G5_IO1_Msk (0x1U << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
6838#define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
6839#define TSC_IOCCR_G5_IO2_Pos (17U)
6840#define TSC_IOCCR_G5_IO2_Msk (0x1U << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
6841#define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
6842#define TSC_IOCCR_G5_IO3_Pos (18U)
6843#define TSC_IOCCR_G5_IO3_Msk (0x1U << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
6844#define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
6845#define TSC_IOCCR_G5_IO4_Pos (19U)
6846#define TSC_IOCCR_G5_IO4_Msk (0x1U << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
6847#define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
6848#define TSC_IOCCR_G6_IO1_Pos (20U)
6849#define TSC_IOCCR_G6_IO1_Msk (0x1U << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
6850#define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
6851#define TSC_IOCCR_G6_IO2_Pos (21U)
6852#define TSC_IOCCR_G6_IO2_Msk (0x1U << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
6853#define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
6854#define TSC_IOCCR_G6_IO3_Pos (22U)
6855#define TSC_IOCCR_G6_IO3_Msk (0x1U << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
6856#define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
6857#define TSC_IOCCR_G6_IO4_Pos (23U)
6858#define TSC_IOCCR_G6_IO4_Msk (0x1U << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
6859#define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
6860#define TSC_IOCCR_G7_IO1_Pos (24U)
6861#define TSC_IOCCR_G7_IO1_Msk (0x1U << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
6862#define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
6863#define TSC_IOCCR_G7_IO2_Pos (25U)
6864#define TSC_IOCCR_G7_IO2_Msk (0x1U << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
6865#define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
6866#define TSC_IOCCR_G7_IO3_Pos (26U)
6867#define TSC_IOCCR_G7_IO3_Msk (0x1U << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
6868#define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
6869#define TSC_IOCCR_G7_IO4_Pos (27U)
6870#define TSC_IOCCR_G7_IO4_Msk (0x1U << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
6871#define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
6872#define TSC_IOCCR_G8_IO1_Pos (28U)
6873#define TSC_IOCCR_G8_IO1_Msk (0x1U << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */
6874#define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */
6875#define TSC_IOCCR_G8_IO2_Pos (29U)
6876#define TSC_IOCCR_G8_IO2_Msk (0x1U << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */
6877#define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */
6878#define TSC_IOCCR_G8_IO3_Pos (30U)
6879#define TSC_IOCCR_G8_IO3_Msk (0x1U << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */
6880#define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */
6881#define TSC_IOCCR_G8_IO4_Pos (31U)
6882#define TSC_IOCCR_G8_IO4_Msk (0x1U << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */
6883#define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */
6884
6885/******************* Bit definition for TSC_IOGCSR register *****************/
6886#define TSC_IOGCSR_G1E_Pos (0U)
6887#define TSC_IOGCSR_G1E_Msk (0x1U << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
6888#define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
6889#define TSC_IOGCSR_G2E_Pos (1U)
6890#define TSC_IOGCSR_G2E_Msk (0x1U << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
6891#define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
6892#define TSC_IOGCSR_G3E_Pos (2U)
6893#define TSC_IOGCSR_G3E_Msk (0x1U << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
6894#define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
6895#define TSC_IOGCSR_G4E_Pos (3U)
6896#define TSC_IOGCSR_G4E_Msk (0x1U << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
6897#define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
6898#define TSC_IOGCSR_G5E_Pos (4U)
6899#define TSC_IOGCSR_G5E_Msk (0x1U << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
6900#define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
6901#define TSC_IOGCSR_G6E_Pos (5U)
6902#define TSC_IOGCSR_G6E_Msk (0x1U << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
6903#define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
6904#define TSC_IOGCSR_G7E_Pos (6U)
6905#define TSC_IOGCSR_G7E_Msk (0x1U << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
6906#define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
6907#define TSC_IOGCSR_G8E_Pos (7U)
6908#define TSC_IOGCSR_G8E_Msk (0x1U << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */
6909#define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */
6910#define TSC_IOGCSR_G1S_Pos (16U)
6911#define TSC_IOGCSR_G1S_Msk (0x1U << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
6912#define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
6913#define TSC_IOGCSR_G2S_Pos (17U)
6914#define TSC_IOGCSR_G2S_Msk (0x1U << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
6915#define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
6916#define TSC_IOGCSR_G3S_Pos (18U)
6917#define TSC_IOGCSR_G3S_Msk (0x1U << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
6918#define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
6919#define TSC_IOGCSR_G4S_Pos (19U)
6920#define TSC_IOGCSR_G4S_Msk (0x1U << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
6921#define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
6922#define TSC_IOGCSR_G5S_Pos (20U)
6923#define TSC_IOGCSR_G5S_Msk (0x1U << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
6924#define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
6925#define TSC_IOGCSR_G6S_Pos (21U)
6926#define TSC_IOGCSR_G6S_Msk (0x1U << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
6927#define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
6928#define TSC_IOGCSR_G7S_Pos (22U)
6929#define TSC_IOGCSR_G7S_Msk (0x1U << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
6930#define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
6931#define TSC_IOGCSR_G8S_Pos (23U)
6932#define TSC_IOGCSR_G8S_Msk (0x1U << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */
6933#define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */
6934
6935/******************* Bit definition for TSC_IOGXCR register *****************/
6936#define TSC_IOGXCR_CNT_Pos (0U)
6937#define TSC_IOGXCR_CNT_Msk (0x3FFFU << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
6938#define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
6939
6940/******************************************************************************/
6941/* */
6942/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
6943/* */
6944/******************************************************************************/
6945
6946/*
6947 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
6948 */
6949/* Note: No specific macro feature on this device */
6950
6951/****************** Bit definition for USART_CR1 register *******************/
6952#define USART_CR1_UE_Pos (0U)
6953#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
6954#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
6955#define USART_CR1_UESM_Pos (1U)
6956#define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
6957#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
6958#define USART_CR1_RE_Pos (2U)
6959#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
6960#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
6961#define USART_CR1_TE_Pos (3U)
6962#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
6963#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
6964#define USART_CR1_IDLEIE_Pos (4U)
6965#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
6966#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
6967#define USART_CR1_RXNEIE_Pos (5U)
6968#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
6969#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
6970#define USART_CR1_TCIE_Pos (6U)
6971#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
6972#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
6973#define USART_CR1_TXEIE_Pos (7U)
6974#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
6975#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
6976#define USART_CR1_PEIE_Pos (8U)
6977#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
6978#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
6979#define USART_CR1_PS_Pos (9U)
6980#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
6981#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
6982#define USART_CR1_PCE_Pos (10U)
6983#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
6984#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
6985#define USART_CR1_WAKE_Pos (11U)
6986#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
6987#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
6988#define USART_CR1_M_Pos (12U)
6989#define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
6990#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
6991#define USART_CR1_M0_Pos (12U)
6992#define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */
6993#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
6994#define USART_CR1_MME_Pos (13U)
6995#define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
6996#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
6997#define USART_CR1_CMIE_Pos (14U)
6998#define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
6999#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
7000#define USART_CR1_OVER8_Pos (15U)
7001#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
7002#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
7003#define USART_CR1_DEDT_Pos (16U)
7004#define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
7005#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
7006#define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
7007#define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
7008#define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
7009#define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
7010#define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
7011#define USART_CR1_DEAT_Pos (21U)
7012#define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
7013#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
7014#define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
7015#define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
7016#define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
7017#define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
7018#define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
7019#define USART_CR1_RTOIE_Pos (26U)
7020#define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
7021#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
7022#define USART_CR1_EOBIE_Pos (27U)
7023#define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
7024#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
7025#define USART_CR1_M1_Pos (28U)
7026#define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */
7027#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
7028/****************** Bit definition for USART_CR2 register *******************/
7029#define USART_CR2_ADDM7_Pos (4U)
7030#define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
7031#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
7032#define USART_CR2_LBDL_Pos (5U)
7033#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
7034#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
7035#define USART_CR2_LBDIE_Pos (6U)
7036#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
7037#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
7038#define USART_CR2_LBCL_Pos (8U)
7039#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
7040#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
7041#define USART_CR2_CPHA_Pos (9U)
7042#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
7043#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
7044#define USART_CR2_CPOL_Pos (10U)
7045#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
7046#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
7047#define USART_CR2_CLKEN_Pos (11U)
7048#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
7049#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
7050#define USART_CR2_STOP_Pos (12U)
7051#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
7052#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
7053#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
7054#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
7055#define USART_CR2_LINEN_Pos (14U)
7056#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
7057#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
7058#define USART_CR2_SWAP_Pos (15U)
7059#define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
7060#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
7061#define USART_CR2_RXINV_Pos (16U)
7062#define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
7063#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
7064#define USART_CR2_TXINV_Pos (17U)
7065#define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
7066#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
7067#define USART_CR2_DATAINV_Pos (18U)
7068#define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
7069#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
7070#define USART_CR2_MSBFIRST_Pos (19U)
7071#define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
7072#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
7073#define USART_CR2_ABREN_Pos (20U)
7074#define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
7075#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
7076#define USART_CR2_ABRMODE_Pos (21U)
7077#define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
7078#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
7079#define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
7080#define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
7081#define USART_CR2_RTOEN_Pos (23U)
7082#define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
7083#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
7084#define USART_CR2_ADD_Pos (24U)
7085#define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
7086#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
7087
7088/****************** Bit definition for USART_CR3 register *******************/
7089#define USART_CR3_EIE_Pos (0U)
7090#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
7091#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
7092#define USART_CR3_IREN_Pos (1U)
7093#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
7094#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
7095#define USART_CR3_IRLP_Pos (2U)
7096#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
7097#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
7098#define USART_CR3_HDSEL_Pos (3U)
7099#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
7100#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
7101#define USART_CR3_NACK_Pos (4U)
7102#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
7103#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
7104#define USART_CR3_SCEN_Pos (5U)
7105#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
7106#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
7107#define USART_CR3_DMAR_Pos (6U)
7108#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
7109#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
7110#define USART_CR3_DMAT_Pos (7U)
7111#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
7112#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
7113#define USART_CR3_RTSE_Pos (8U)
7114#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
7115#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
7116#define USART_CR3_CTSE_Pos (9U)
7117#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
7118#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
7119#define USART_CR3_CTSIE_Pos (10U)
7120#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
7121#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
7122#define USART_CR3_ONEBIT_Pos (11U)
7123#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
7124#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
7125#define USART_CR3_OVRDIS_Pos (12U)
7126#define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
7127#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
7128#define USART_CR3_DDRE_Pos (13U)
7129#define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
7130#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
7131#define USART_CR3_DEM_Pos (14U)
7132#define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
7133#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
7134#define USART_CR3_DEP_Pos (15U)
7135#define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
7136#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
7137#define USART_CR3_SCARCNT_Pos (17U)
7138#define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
7139#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
7140#define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
7141#define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
7142#define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
7143#define USART_CR3_WUS_Pos (20U)
7144#define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
7145#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
7146#define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
7147#define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
7148#define USART_CR3_WUFIE_Pos (22U)
7149#define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
7150#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
7151#define USART_CR3_UCESM_Pos (23U)
7152#define USART_CR3_UCESM_Msk (0x1U << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
7153#define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
7154
7155/****************** Bit definition for USART_BRR register *******************/
7156#define USART_BRR_DIV_FRACTION_Pos (0U)
7157#define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
7158#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
7159#define USART_BRR_DIV_MANTISSA_Pos (4U)
7160#define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
7161#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
7162
7163/****************** Bit definition for USART_GTPR register ******************/
7164#define USART_GTPR_PSC_Pos (0U)
7165#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
7166#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
7167#define USART_GTPR_GT_Pos (8U)
7168#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
7169#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
7170
7171
7172/******************* Bit definition for USART_RTOR register *****************/
7173#define USART_RTOR_RTO_Pos (0U)
7174#define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
7175#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
7176#define USART_RTOR_BLEN_Pos (24U)
7177#define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
7178#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
7179
7180/******************* Bit definition for USART_RQR register ******************/
7181#define USART_RQR_ABRRQ_Pos (0U)
7182#define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
7183#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
7184#define USART_RQR_SBKRQ_Pos (1U)
7185#define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
7186#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
7187#define USART_RQR_MMRQ_Pos (2U)
7188#define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
7189#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
7190#define USART_RQR_RXFRQ_Pos (3U)
7191#define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
7192#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
7193#define USART_RQR_TXFRQ_Pos (4U)
7194#define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
7195#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
7196
7197/******************* Bit definition for USART_ISR register ******************/
7198#define USART_ISR_PE_Pos (0U)
7199#define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
7200#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
7201#define USART_ISR_FE_Pos (1U)
7202#define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
7203#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
7204#define USART_ISR_NE_Pos (2U)
7205#define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
7206#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
7207#define USART_ISR_ORE_Pos (3U)
7208#define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
7209#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
7210#define USART_ISR_IDLE_Pos (4U)
7211#define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
7212#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
7213#define USART_ISR_RXNE_Pos (5U)
7214#define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
7215#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
7216#define USART_ISR_TC_Pos (6U)
7217#define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
7218#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
7219#define USART_ISR_TXE_Pos (7U)
7220#define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
7221#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
7222#define USART_ISR_LBDF_Pos (8U)
7223#define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
7224#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
7225#define USART_ISR_CTSIF_Pos (9U)
7226#define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
7227#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
7228#define USART_ISR_CTS_Pos (10U)
7229#define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
7230#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
7231#define USART_ISR_RTOF_Pos (11U)
7232#define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
7233#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
7234#define USART_ISR_EOBF_Pos (12U)
7235#define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
7236#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
7237#define USART_ISR_ABRE_Pos (14U)
7238#define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
7239#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
7240#define USART_ISR_ABRF_Pos (15U)
7241#define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
7242#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
7243#define USART_ISR_BUSY_Pos (16U)
7244#define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
7245#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
7246#define USART_ISR_CMF_Pos (17U)
7247#define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
7248#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
7249#define USART_ISR_SBKF_Pos (18U)
7250#define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
7251#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
7252#define USART_ISR_RWU_Pos (19U)
7253#define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
7254#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
7255#define USART_ISR_WUF_Pos (20U)
7256#define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
7257#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
7258#define USART_ISR_TEACK_Pos (21U)
7259#define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
7260#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
7261#define USART_ISR_REACK_Pos (22U)
7262#define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
7263#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
7264
7265/******************* Bit definition for USART_ICR register ******************/
7266#define USART_ICR_PECF_Pos (0U)
7267#define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
7268#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
7269#define USART_ICR_FECF_Pos (1U)
7270#define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
7271#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
7272#define USART_ICR_NCF_Pos (2U)
7273#define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
7274#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
7275#define USART_ICR_ORECF_Pos (3U)
7276#define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
7277#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
7278#define USART_ICR_IDLECF_Pos (4U)
7279#define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
7280#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
7281#define USART_ICR_TCCF_Pos (6U)
7282#define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
7283#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
7284#define USART_ICR_LBDCF_Pos (8U)
7285#define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
7286#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
7287#define USART_ICR_CTSCF_Pos (9U)
7288#define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
7289#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
7290#define USART_ICR_RTOCF_Pos (11U)
7291#define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
7292#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
7293#define USART_ICR_EOBCF_Pos (12U)
7294#define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
7295#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
7296#define USART_ICR_CMCF_Pos (17U)
7297#define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
7298#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
7299#define USART_ICR_WUCF_Pos (20U)
7300#define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
7301#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
7302
7303/******************* Bit definition for USART_RDR register ******************/
7304#define USART_RDR_RDR_Pos (0U)
7305#define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
7306#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
7307
7308/******************* Bit definition for USART_TDR register ******************/
7309#define USART_TDR_TDR_Pos (0U)
7310#define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */
7311#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
7312
7313/******************************************************************************/
7314/* */
7315/* USB Device General registers */
7316/* */
7317/******************************************************************************/
7318#define USB_BASE (0x40005C00U) /*!< USB_IP Peripheral Registers base address */
7319#define USB_PMAADDR_Pos (13U)
7320#define USB_PMAADDR_Msk (0x20003U << USB_PMAADDR_Pos) /*!< 0x40006000 */
7321#define USB_PMAADDR USB_PMAADDR_Msk /*!< USB_IP Packet Memory Area base address */
7322
7323#define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
7324#define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
7325#define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
7326#define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
7327#define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
7328#define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
7329#define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
7330
7331/**************************** ISTR interrupt events *************************/
7332#define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
7333#define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
7334#define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
7335#define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
7336#define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
7337#define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
7338#define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
7339#define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
7340#define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
7341#define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
7342#define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
7343
7344#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
7345#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
7346#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
7347#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
7348#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
7349#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
7350#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
7351#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
7352#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
7353/************************* CNTR control register bits definitions ***********/
7354#define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
7355#define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
7356#define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
7357#define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
7358#define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
7359#define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
7360#define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
7361#define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
7362#define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
7363#define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
7364#define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
7365#define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
7366#define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
7367#define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
7368#define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
7369/************************* BCDR control register bits definitions ***********/
7370#define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
7371#define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
7372#define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
7373#define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
7374#define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
7375#define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
7376#define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
7377#define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
7378#define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
7379/*************************** LPM register bits definitions ******************/
7380#define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
7381#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
7382#define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
7383#define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
7384/******************** FNR Frame Number Register bit definitions ************/
7385#define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
7386#define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
7387#define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
7388#define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
7389#define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
7390/******************** DADDR Device ADDRess bit definitions ****************/
7391#define USB_DADDR_EF ((uint8_t)0x80U) /*!< USB device address Enable Function */
7392#define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< USB device address */
7393/****************************** Endpoint register *************************/
7394#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
7395#define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
7396#define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
7397#define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
7398#define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
7399#define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
7400#define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
7401#define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
7402/* bit positions */
7403#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
7404#define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
7405#define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
7406#define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
7407#define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
7408#define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
7409#define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
7410#define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
7411#define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
7412#define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
7413
7414/* EndPoint REGister MASK (no toggle fields) */
7415#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
7416 /*!< EP_TYPE[1:0] EndPoint TYPE */
7417#define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
7418#define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
7419#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
7420#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
7421#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
7422#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
7423
7424#define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
7425 /*!< STAT_TX[1:0] STATus for TX transfer */
7426#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
7427#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
7428#define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
7429#define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
7430#define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
7431#define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
7432#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
7433 /*!< STAT_RX[1:0] STATus for RX transfer */
7434#define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
7435#define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
7436#define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
7437#define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
7438#define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
7439#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
7440#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
7441
7442/******************************************************************************/
7443/* */
7444/* Window WATCHDOG (WWDG) */
7445/* */
7446/******************************************************************************/
7447
7448/******************* Bit definition for WWDG_CR register ********************/
7449#define WWDG_CR_T_Pos (0U)
7450#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
7451#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
7452#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
7453#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
7454#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
7455#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
7456#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
7457#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
7458#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
7459
7460/* Legacy defines */
7461#define WWDG_CR_T0 WWDG_CR_T_0
7462#define WWDG_CR_T1 WWDG_CR_T_1
7463#define WWDG_CR_T2 WWDG_CR_T_2
7464#define WWDG_CR_T3 WWDG_CR_T_3
7465#define WWDG_CR_T4 WWDG_CR_T_4
7466#define WWDG_CR_T5 WWDG_CR_T_5
7467#define WWDG_CR_T6 WWDG_CR_T_6
7468
7469#define WWDG_CR_WDGA_Pos (7U)
7470#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
7471#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
7472
7473/******************* Bit definition for WWDG_CFR register *******************/
7474#define WWDG_CFR_W_Pos (0U)
7475#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
7476#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
7477#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
7478#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
7479#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
7480#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
7481#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
7482#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
7483#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
7484
7485/* Legacy defines */
7486#define WWDG_CFR_W0 WWDG_CFR_W_0
7487#define WWDG_CFR_W1 WWDG_CFR_W_1
7488#define WWDG_CFR_W2 WWDG_CFR_W_2
7489#define WWDG_CFR_W3 WWDG_CFR_W_3
7490#define WWDG_CFR_W4 WWDG_CFR_W_4
7491#define WWDG_CFR_W5 WWDG_CFR_W_5
7492#define WWDG_CFR_W6 WWDG_CFR_W_6
7493
7494#define WWDG_CFR_WDGTB_Pos (7U)
7495#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
7496#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
7497#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
7498#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
7499
7500/* Legacy defines */
7501#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
7502#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
7503
7504#define WWDG_CFR_EWI_Pos (9U)
7505#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
7506#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
7507
7508/******************* Bit definition for WWDG_SR register ********************/
7509#define WWDG_SR_EWIF_Pos (0U)
7510#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
7511#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
7512
7513/**
7514 * @}
7515 */
7516
7517/**
7518 * @}
7519 */
7520
7521/** @addtogroup Exported_macros
7522 * @{
7523 */
7524
7525/******************************* ADC Instances ********************************/
7526#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
7527#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
7528
7529/******************************* COMP Instances *******************************/
7530#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
7531 ((INSTANCE) == COMP2))
7532
7533#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
7534
7535/******************************* CRC Instances ********************************/
7536#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
7537
7538/******************************* DAC Instances *********************************/
7539#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
7540
7541/******************************* DMA Instances *********************************/
7542#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
7543 ((INSTANCE) == DMA1_Channel2) || \
7544 ((INSTANCE) == DMA1_Channel3) || \
7545 ((INSTANCE) == DMA1_Channel4) || \
7546 ((INSTANCE) == DMA1_Channel5) || \
7547 ((INSTANCE) == DMA1_Channel6) || \
7548 ((INSTANCE) == DMA1_Channel7))
7549
7550/******************************* GPIO Instances *******************************/
7551#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
7552 ((INSTANCE) == GPIOB) || \
7553 ((INSTANCE) == GPIOC) || \
7554 ((INSTANCE) == GPIOD) || \
7555 ((INSTANCE) == GPIOE) || \
7556 ((INSTANCE) == GPIOH))
7557
7558#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
7559 ((INSTANCE) == GPIOB) || \
7560 ((INSTANCE) == GPIOC) || \
7561 ((INSTANCE) == GPIOD) || \
7562 ((INSTANCE) == GPIOE) || \
7563 ((INSTANCE) == GPIOH))
7564
7565/******************************** I2C Instances *******************************/
7566#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
7567 ((INSTANCE) == I2C2) || \
7568 ((INSTANCE) == I2C3))
7569
7570/****************** I2C Instances : wakeup capability from stop modes *********/
7571#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
7572 ((INSTANCE) == I2C3))
7573
7574
7575/******************************** I2S Instances *******************************/
7576#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI2)
7577
7578/******************************* RNG Instances ********************************/
7579#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
7580
7581/****************************** RTC Instances *********************************/
7582#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
7583
7584/******************************** SMBUS Instances *****************************/
7585#define IS_SMBUS_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
7586 ((INSTANCE) == I2C3))
7587
7588/******************************** SPI Instances *******************************/
7589#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
7590 ((INSTANCE) == SPI2))
7591
7592/****************** LPTIM Instances : All supported instances *****************/
7593#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
7594
7595/****************** TIM Instances : All supported instances *******************/
7596#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7597 ((INSTANCE) == TIM3) || \
7598 ((INSTANCE) == TIM6) || \
7599 ((INSTANCE) == TIM7) || \
7600 ((INSTANCE) == TIM21) || \
7601 ((INSTANCE) == TIM22))
7602
7603/****************** TIM Instances : supporting counting mode selection ********/
7604#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7605 ((INSTANCE) == TIM3) || \
7606 ((INSTANCE) == TIM21) || \
7607 ((INSTANCE) == TIM22))
7608
7609/****************** TIM Instances : supporting clock division *****************/
7610#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7611 ((INSTANCE) == TIM3) || \
7612 ((INSTANCE) == TIM21) || \
7613 ((INSTANCE) == TIM22))
7614
7615/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
7616#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7617 ((INSTANCE) == TIM3) || \
7618 ((INSTANCE) == TIM21))
7619
7620/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
7621#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7622 ((INSTANCE) == TIM3) || \
7623 ((INSTANCE) == TIM21) || \
7624 ((INSTANCE) == TIM22))
7625
7626/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
7627#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7628 ((INSTANCE) == TIM3) || \
7629 ((INSTANCE) == TIM21))
7630
7631/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
7632#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7633 ((INSTANCE) == TIM3) || \
7634 ((INSTANCE) == TIM21) || \
7635 ((INSTANCE) == TIM22))
7636
7637/************* TIM Instances : at least 1 capture/compare channel *************/
7638#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7639 ((INSTANCE) == TIM3) || \
7640 ((INSTANCE) == TIM21) || \
7641 ((INSTANCE) == TIM22))
7642
7643/************ TIM Instances : at least 2 capture/compare channels *************/
7644#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7645 ((INSTANCE) == TIM3) || \
7646 ((INSTANCE) == TIM21) || \
7647 ((INSTANCE) == TIM22))
7648
7649/************ TIM Instances : at least 3 capture/compare channels *************/
7650#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7651 ((INSTANCE) == TIM3))
7652
7653/************ TIM Instances : at least 4 capture/compare channels *************/
7654#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7655 ((INSTANCE) == TIM3))
7656
7657/******************** TIM Instances : Advanced-control timers *****************/
7658
7659/******************* TIM Instances : Timer input XOR function *****************/
7660#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7661 ((INSTANCE) == TIM3))
7662
7663/****************** TIM Instances : DMA requests generation (UDE) *************/
7664#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7665 ((INSTANCE) == TIM3) || \
7666 ((INSTANCE) == TIM6) || \
7667 ((INSTANCE) == TIM7))
7668
7669/************ TIM Instances : DMA requests generation (CCxDE) *****************/
7670#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7671 ((INSTANCE) == TIM3))
7672
7673/************ TIM Instances : DMA requests generation (COMDE) *****************/
7674#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7675 (INSTANCE) == TIM3))
7676
7677/******************** TIM Instances : DMA burst feature ***********************/
7678#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7679 ((INSTANCE) == TIM3))
7680
7681/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
7682#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7683 ((INSTANCE) == TIM3) || \
7684 ((INSTANCE) == TIM6) || \
7685 ((INSTANCE) == TIM7) || \
7686 ((INSTANCE) == TIM21) || \
7687 ((INSTANCE) == TIM22))
7688
7689/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
7690#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7691 ((INSTANCE) == TIM3) || \
7692 ((INSTANCE) == TIM21) || \
7693 ((INSTANCE) == TIM22))
7694
7695/********************** TIM Instances : 32 bit Counter ************************/
7696
7697/***************** TIM Instances : external trigger input availabe ************/
7698#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7699 ((INSTANCE) == TIM3) || \
7700 ((INSTANCE) == TIM21) || \
7701 ((INSTANCE) == TIM22))
7702
7703/****************** TIM Instances : remapping capability **********************/
7704#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7705 ((INSTANCE) == TIM3) || \
7706 ((INSTANCE) == TIM21) || \
7707 ((INSTANCE) == TIM22))
7708
7709/****************** TIM Instances : supporting encoder interface **************/
7710#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7711 ((INSTANCE) == TIM3) || \
7712 ((INSTANCE) == TIM21) || \
7713 ((INSTANCE) == TIM22))
7714
7715/******************* TIM Instances : output(s) OCXEC register *****************/
7716#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
7717 ((INSTANCE) == TIM3))
7718
7719/******************* TIM Instances : output(s) available **********************/
7720#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
7721 (((((INSTANCE) == TIM2) || \
7722 ((INSTANCE) == TIM3)) \
7723 && \
7724 (((CHANNEL) == TIM_CHANNEL_1) || \
7725 ((CHANNEL) == TIM_CHANNEL_2) || \
7726 ((CHANNEL) == TIM_CHANNEL_3) || \
7727 ((CHANNEL) == TIM_CHANNEL_4))) \
7728 || \
7729 (((INSTANCE) == TIM21) && \
7730 (((CHANNEL) == TIM_CHANNEL_1) || \
7731 ((CHANNEL) == TIM_CHANNEL_2))) \
7732 || \
7733 (((INSTANCE) == TIM22) && \
7734 (((CHANNEL) == TIM_CHANNEL_1) || \
7735 ((CHANNEL) == TIM_CHANNEL_2))))
7736
7737/******************** UART Instances : Asynchronous mode **********************/
7738#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7739 ((INSTANCE) == USART2) || \
7740 ((INSTANCE) == USART4) || \
7741 ((INSTANCE) == USART5) || \
7742 ((INSTANCE) == LPUART1))
7743
7744/******************** USART Instances : Synchronous mode **********************/
7745#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7746 ((INSTANCE) == USART2) || \
7747 ((INSTANCE) == USART4) || \
7748 ((INSTANCE) == USART5))
7749
7750/****************** USART Instances : Auto Baud Rate detection ****************/
7751
7752#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7753 ((INSTANCE) == USART2))
7754
7755/******************** UART Instances : Half-Duplex mode **********************/
7756#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7757 ((INSTANCE) == USART2) || \
7758 ((INSTANCE) == USART4) || \
7759 ((INSTANCE) == USART5) || \
7760 ((INSTANCE) == LPUART1))
7761
7762/******************** UART Instances : LIN mode **********************/
7763#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7764 ((INSTANCE) == USART2))
7765
7766/******************** UART Instances : Wake-up from Stop mode **********************/
7767#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7768 ((INSTANCE) == USART2) || \
7769 ((INSTANCE) == LPUART1))
7770/****************** UART Instances : Hardware Flow control ********************/
7771#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7772 ((INSTANCE) == USART2) || \
7773 ((INSTANCE) == USART4) || \
7774 ((INSTANCE) == USART5) || \
7775 ((INSTANCE) == LPUART1))
7776
7777/********************* UART Instances : Smard card mode ***********************/
7778#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7779 ((INSTANCE) == USART2))
7780
7781/*********************** UART Instances : IRDA mode ***************************/
7782#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7783 ((INSTANCE) == USART2))
7784
7785/******************** LPUART Instance *****************************************/
7786#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
7787
7788/****************************** IWDG Instances ********************************/
7789#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
7790
7791/****************************** USB Instances ********************************/
7792#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
7793
7794/****************************** WWDG Instances ********************************/
7795#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
7796
7797/****************************** LCD Instances ********************************/
7798#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
7799
7800/**
7801 * @}
7802 */
7803
7804/******************************************************************************/
7805/* For a painless codes migration between the STM32L0xx device product */
7806/* lines, the aliases defined below are put in place to overcome the */
7807/* differences in the interrupt handlers and IRQn definitions. */
7808/* No need to update developed interrupt code when moving across */
7809/* product lines within the same STM32L0 Family */
7810/******************************************************************************/
7811
7812/* Aliases for __IRQn */
7813
7814#define LPUART1_IRQn RNG_LPUART1_IRQn
7815#define AES_LPUART1_IRQn RNG_LPUART1_IRQn
7816#define AES_RNG_LPUART1_IRQn RNG_LPUART1_IRQn
7817#define TIM6_IRQn TIM6_DAC_IRQn
7818#define RCC_IRQn RCC_CRS_IRQn
7819
7820/* Aliases for __IRQHandler */
7821#define LPUART1_IRQHandler RNG_LPUART1_IRQHandler
7822#define AES_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
7823#define AES_RNG_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
7824#define TIM6_IRQHandler TIM6_DAC_IRQHandler
7825#define RCC_IRQHandler RCC_CRS_IRQHandler
7826
7827/**
7828 * @}
7829 */
7830
7831/**
7832 * @}
7833 */
7834
7835#ifdef __cplusplus
7836}
7837#endif /* __cplusplus */
7838
7839#endif /* __STM32L073xx_H */
7840
7841
7842
7843/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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