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authorAkshay <[email protected]>2022-04-10 12:13:40 +0100
committerAkshay <[email protected]>2022-04-10 12:13:40 +0100
commitdc90387ce7d8ba7b607d9c48540bf6d8b560f14d (patch)
tree4ccb8fa5886b66fa9d480edef74236c27f035e16 /lib/chibios/os/common/ext/ST/STM32L4xx/stm32l4s5xx.h
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1/**
2 ******************************************************************************
3 * @file stm32l4s5xx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32L4S5xx Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral�s registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
16 *
17 * Redistribution and use in source and binary forms, with or without modification,
18 * are permitted provided that the following conditions are met:
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright notice,
22 * this list of conditions and the following disclaimer in the documentation
23 * and/or other materials provided with the distribution.
24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 ******************************************************************************
40 */
41
42/** @addtogroup CMSIS_Device
43 * @{
44 */
45
46/** @addtogroup stm32l4s5xx
47 * @{
48 */
49
50#ifndef __STM32L4S5xx_H
51#define __STM32L4S5xx_H
52
53#ifdef __cplusplus
54 extern "C" {
55#endif /* __cplusplus */
56
57/** @addtogroup Configuration_section_for_CMSIS
58 * @{
59 */
60
61/**
62 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
63 */
64#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
65#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
66#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
67#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
68#define __FPU_PRESENT 1 /*!< FPU present */
69
70/**
71 * @}
72 */
73
74/** @addtogroup Peripheral_interrupt_number_definition
75 * @{
76 */
77
78/**
79 * @brief STM32L4XX Interrupt Number Definition, according to the selected device
80 * in @ref Library_configuration_section
81 */
82typedef enum
83{
84/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
85 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
86 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
87 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
88 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
89 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
90 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
91 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
92 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
93 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
94/****** STM32 specific Interrupt Numbers **********************************************************************/
95 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
96 PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
97 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
98 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
99 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
100 RCC_IRQn = 5, /*!< RCC global Interrupt */
101 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
102 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
103 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
104 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
105 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
106 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
107 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
108 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
109 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
110 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
111 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
112 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
113 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
114 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
115 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
116 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
117 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
118 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
119 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */
120 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
121 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */
122 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
123 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
124 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
125 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
126 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
127 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
128 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
129 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
130 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
131 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
132 USART1_IRQn = 37, /*!< USART1 global Interrupt */
133 USART2_IRQn = 38, /*!< USART2 global Interrupt */
134 USART3_IRQn = 39, /*!< USART3 global Interrupt */
135 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
136 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
137 DFSDM1_FLT3_IRQn = 42, /*!< DFSDM1 Filter 3 global Interrupt */
138 TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
139 TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
140 TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
141 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
142 FMC_IRQn = 48, /*!< FMC global Interrupt */
143 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
144 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
145 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
146 UART4_IRQn = 52, /*!< UART4 global Interrupt */
147 UART5_IRQn = 53, /*!< UART5 global Interrupt */
148 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
149 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
150 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
151 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
152 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
153 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
154 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
155 DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
156 DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
157 DFSDM1_FLT2_IRQn = 63, /*!< DFSDM1 Filter 2 global Interrupt */
158 COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */
159 LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */
160 LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */
161 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
162 DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */
163 DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */
164 LPUART1_IRQn = 70, /*!< LP UART1 interrupt */
165 OCTOSPI1_IRQn = 71, /*!< OctoSPI1 global interrupt */
166 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
167 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
168 SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */
169 SAI2_IRQn = 75, /*!< Serial Audio Interface 2 global interrupt */
170 OCTOSPI2_IRQn = 76, /*!< OctoSPI2 global interrupt */
171 TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */
172 AES_IRQn = 79, /*!< AES global interrupt */
173 RNG_IRQn = 80, /*!< RNG global interrupt */
174 FPU_IRQn = 81, /*!< FPU global interrupt */
175 HASH_CRS_IRQn = 82, /*!< HASH and CRS interrupt */
176 I2C4_EV_IRQn = 83, /*!< I2C4 Event interrupt */
177 I2C4_ER_IRQn = 84, /*!< I2C4 Error interrupt */
178 DCMI_IRQn = 85, /*!< DCMI global interrupt */
179 DMA2D_IRQn = 90, /*!< DMA2D global interrupt */
180 DMAMUX1_OVR_IRQn = 94 /*!< DMAMUX1 overrun global interrupt */
181} IRQn_Type;
182
183/**
184 * @}
185 */
186
187#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
188#include "system_stm32l4xx.h"
189#include <stdint.h>
190
191/** @addtogroup Peripheral_registers_structures
192 * @{
193 */
194
195/**
196 * @brief Analog to Digital Converter
197 */
198
199typedef struct
200{
201 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
202 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
203 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
204 __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
205 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
206 __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
207 __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
208 uint32_t RESERVED1; /*!< Reserved, 0x1C */
209 __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
210 __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
211 __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
212 uint32_t RESERVED2; /*!< Reserved, 0x2C */
213 __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
214 __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
215 __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
216 __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
217 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
218 uint32_t RESERVED3; /*!< Reserved, 0x44 */
219 uint32_t RESERVED4; /*!< Reserved, 0x48 */
220 __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
221 uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
222 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
223 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
224 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
225 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
226 uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
227 __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
228 __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
229 __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
230 __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
231 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
232 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */
233 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
234 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
235 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
236 __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
237 __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
238
239} ADC_TypeDef;
240
241typedef struct
242{
243 uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */
244 uint32_t RESERVED2; /*!< Reserved, Address offset: ADC1 base address + 0x304 */
245 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
246 uint32_t RESERVED3; /*!< Reserved, Address offset: ADC1 base address + 0x30C */
247} ADC_Common_TypeDef;
248
249/**
250 * @brief DCMI
251 */
252
253typedef struct
254{
255 __IO uint32_t CR; /*!< DCMI control register, Address offset: 0x00 */
256 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
257 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
258 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
259 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
260 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
261 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
262 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
263 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
264 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
265 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
266} DCMI_TypeDef;
267
268/**
269 * @brief Controller Area Network TxMailBox
270 */
271
272typedef struct
273{
274 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
275 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
276 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
277 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
278} CAN_TxMailBox_TypeDef;
279
280/**
281 * @brief Controller Area Network FIFOMailBox
282 */
283
284typedef struct
285{
286 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
287 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
288 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
289 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
290} CAN_FIFOMailBox_TypeDef;
291
292/**
293 * @brief Controller Area Network FilterRegister
294 */
295
296typedef struct
297{
298 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
299 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
300} CAN_FilterRegister_TypeDef;
301
302/**
303 * @brief Controller Area Network
304 */
305
306typedef struct
307{
308 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
309 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
310 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
311 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
312 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
313 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
314 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
315 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
316 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
317 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
318 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
319 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
320 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
321 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
322 uint32_t RESERVED2; /*!< Reserved, 0x208 */
323 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
324 uint32_t RESERVED3; /*!< Reserved, 0x210 */
325 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
326 uint32_t RESERVED4; /*!< Reserved, 0x218 */
327 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
328 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
329 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
330} CAN_TypeDef;
331
332
333/**
334 * @brief Comparator
335 */
336
337typedef struct
338{
339 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
340} COMP_TypeDef;
341
342typedef struct
343{
344 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
345} COMP_Common_TypeDef;
346
347/**
348 * @brief CRC calculation unit
349 */
350
351typedef struct
352{
353 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
354 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
355 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
356 uint32_t RESERVED2; /*!< Reserved, 0x0C */
357 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
358 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
359} CRC_TypeDef;
360
361/**
362 * @brief Clock Recovery System
363 */
364typedef struct
365{
366__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
367__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
368__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
369__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
370} CRS_TypeDef;
371
372/**
373 * @brief Digital to Analog Converter
374 */
375
376typedef struct
377{
378 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
379 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
380 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
381 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
382 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
383 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
384 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
385 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
386 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
387 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
388 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
389 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
390 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
391 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
392 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
393 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
394 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
395 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
396 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
397 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
398} DAC_TypeDef;
399
400/**
401 * @brief DFSDM module registers
402 */
403typedef struct
404{
405 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
406 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
407 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
408 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
409 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
410 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
411 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
412 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
413 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
414 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
415 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
416 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
417 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
418 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
419 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
420} DFSDM_Filter_TypeDef;
421
422/**
423 * @brief DFSDM channel configuration registers
424 */
425typedef struct
426{
427 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
428 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
429 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
430 short circuit detector register, Address offset: 0x08 */
431 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
432 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
433 __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */
434} DFSDM_Channel_TypeDef;
435
436/**
437 * @brief Debug MCU
438 */
439
440typedef struct
441{
442 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
443 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
444 __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
445 __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
446 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
447} DBGMCU_TypeDef;
448
449
450/**
451 * @brief DMA Controller
452 */
453
454typedef struct
455{
456 __IO uint32_t CCR; /*!< DMA channel x configuration register */
457 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
458 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
459 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
460} DMA_Channel_TypeDef;
461
462typedef struct
463{
464 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
465 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
466} DMA_TypeDef;
467
468/**
469 * @brief DMA Multiplexer
470 */
471
472typedef struct
473{
474 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */
475}DMAMUX_Channel_TypeDef;
476
477typedef struct
478{
479 __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */
480 __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */
481}DMAMUX_ChannelStatus_TypeDef;
482
483typedef struct
484{
485 __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */
486}DMAMUX_RequestGen_TypeDef;
487
488typedef struct
489{
490 __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */
491 __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */
492}DMAMUX_RequestGenStatus_TypeDef;
493
494
495/**
496 * @brief DMA2D Controller
497 */
498
499typedef struct
500{
501 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
502 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
503 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
504 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
505 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
506 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
507 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
508 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
509 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
510 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
511 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
512 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
513 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
514 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
515 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
516 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
517 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
518 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
519 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
520 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
521 uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */
522 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */
523 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */
524} DMA2D_TypeDef;
525
526/**
527 * @brief External Interrupt/Event Controller
528 */
529
530typedef struct
531{
532 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
533 __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
534 __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
535 __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
536 __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
537 __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
538 uint32_t RESERVED1; /*!< Reserved, 0x18 */
539 uint32_t RESERVED2; /*!< Reserved, 0x1C */
540 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
541 __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
542 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
543 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
544 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
545 __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
546} EXTI_TypeDef;
547
548
549/**
550 * @brief Firewall
551 */
552
553typedef struct
554{
555 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
556 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
557 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
558 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
559 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
560 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
561 uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */
562 uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
563 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
564} FIREWALL_TypeDef;
565
566
567/**
568 * @brief FLASH Registers
569 */
570
571typedef struct
572{
573 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
574 __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
575 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
576 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
577 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
578 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
579 __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
580 __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
581 __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
582 __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
583 __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
584 __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
585 __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
586 uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34-0x40 */
587 __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
588 __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */
589 __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */
590 __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */
591 uint32_t RESERVED3[55]; /*!< Reserved3, Address offset: 0x54-0x12C */
592 __IO uint32_t CFGR; /*!< FLASH configuration register, Address offset: 0x130 */
593} FLASH_TypeDef;
594
595
596/**
597 * @brief Flexible Memory Controller
598 */
599
600typedef struct
601{
602 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
603} FMC_Bank1_TypeDef;
604
605/**
606 * @brief Flexible Memory Controller Bank1E
607 */
608
609typedef struct
610{
611 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
612} FMC_Bank1E_TypeDef;
613
614/**
615 * @brief Flexible Memory Controller Bank3
616 */
617
618typedef struct
619{
620 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
621 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
622 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
623 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
624 uint32_t RESERVED0; /*!< Reserved, 0x90 */
625 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
626} FMC_Bank3_TypeDef;
627
628/**
629 * @brief General Purpose I/O
630 */
631
632typedef struct
633{
634 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
635 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
636 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
637 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
638 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
639 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
640 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
641 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
642 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
643 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
644
645} GPIO_TypeDef;
646
647
648/**
649 * @brief Inter-integrated Circuit Interface
650 */
651
652typedef struct
653{
654 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
655 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
656 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
657 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
658 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
659 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
660 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
661 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
662 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
663 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
664 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
665} I2C_TypeDef;
666
667/**
668 * @brief Independent WATCHDOG
669 */
670
671typedef struct
672{
673 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
674 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
675 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
676 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
677 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
678} IWDG_TypeDef;
679
680/**
681 * @brief LPTIMER
682 */
683typedef struct
684{
685 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
686 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
687 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
688 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
689 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
690 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
691 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
692 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
693 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
694} LPTIM_TypeDef;
695
696/**
697 * @brief Operational Amplifier (OPAMP)
698 */
699
700typedef struct
701{
702 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
703 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
704 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
705} OPAMP_TypeDef;
706
707typedef struct
708{
709 __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
710} OPAMP_Common_TypeDef;
711
712/**
713 * @brief Power Control
714 */
715
716typedef struct
717{
718 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
719 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
720 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
721 __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
722 __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
723 __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
724 __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
725 uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
726 __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
727 __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
728 __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
729 __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
730 __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
731 __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
732 __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
733 __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
734 __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
735 __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
736 __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */
737 __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
738 __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */
739 __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
740 __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */
741 __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
742 __IO uint32_t PUCRI; /*!< Pull_up control register of portI, Address offset: 0x60 */
743 __IO uint32_t PDCRI; /*!< Pull_Down control register of portI, Address offset: 0x64 */
744 uint32_t RESERVED1[6]; /*!< Reserved, Address offset: 0x68-0x7C */
745 __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */
746} PWR_TypeDef;
747
748
749/**
750 * @brief OCTO Serial Peripheral Interface
751 */
752
753typedef struct
754{
755 __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */
756 uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */
757 __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */
758 __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */
759 __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */
760 uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x014-0x01C */
761 __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */
762 __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */
763 uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */
764 __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */
765 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */
766 __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */
767 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */
768 __IO uint32_t DR; /*!< OCTOPSI Data register, Address offset: 0x050 */
769 uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */
770 __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */
771 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */
772 __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */
773 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */
774 __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */
775 uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */
776 __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */
777 uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */
778 __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */
779 uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */
780 __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */
781 uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */
782 __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */
783 uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */
784 __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */
785 uint32_t RESERVED13[19]; /*!< Reserved, Address offset: 0x134-0x17C */
786 __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */
787 uint32_t RESERVED14; /*!< Reserved, Address offset: 0x184 */
788 __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */
789 uint32_t RESERVED15; /*!< Reserved, Address offset: 0x18C */
790 __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */
791 uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x194-0x19C */
792 __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */
793 uint32_t RESERVED17[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
794 __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */
795} OCTOSPI_TypeDef;
796
797/**
798 * @brief OCTO Serial Peripheral Interface IO Manager
799 */
800
801typedef struct
802{
803 uint32_t RESERVED; /*!< Reserved, Address offset: 0x00 */
804 __IO uint32_t PCR[2]; /*!< OCTOSPI IO Manager Port[1:2] Configuration register, Address offset: 0x04-0x08 */
805} OCTOSPIM_TypeDef;
806
807/**
808 * @brief Reset and Clock Control
809 */
810
811typedef struct
812{
813 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
814 __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
815 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
816 __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
817 __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */
818 __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register, Address offset: 0x14 */
819 __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
820 __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
821 __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
822 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */
823 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
824 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
825 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
826 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
827 __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
828 __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
829 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
830 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */
831 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
832 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
833 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
834 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */
835 __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
836 __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
837 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
838 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */
839 __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
840 __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
841 __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
842 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */
843 __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
844 __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
845 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
846 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */
847 __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
848 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */
849 __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
850 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
851 __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */
852 __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */
853} RCC_TypeDef;
854
855/**
856 * @brief Real-Time Clock
857 */
858
859typedef struct
860{
861 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
862 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
863 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
864 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
865 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
866 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
867 uint32_t reserved; /*!< Reserved */
868 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
869 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
870 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
871 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
872 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
873 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
874 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
875 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
876 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
877 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
878 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
879 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
880 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
881 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
882 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
883 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
884 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
885 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
886 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
887 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
888 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
889 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
890 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
891 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
892 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
893 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
894 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
895 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
896 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
897 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
898 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
899 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
900 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
901 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
902 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
903 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
904 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
905 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
906 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
907 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
908 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
909 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
910 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
911 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
912 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
913} RTC_TypeDef;
914
915
916/**
917 * @brief Serial Audio Interface
918 */
919
920typedef struct
921{
922 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
923 uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */
924 __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
925 __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
926} SAI_TypeDef;
927
928typedef struct
929{
930 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
931 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
932 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
933 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
934 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
935 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
936 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
937 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
938} SAI_Block_TypeDef;
939
940
941/**
942 * @brief Secure digital input/output Interface
943 */
944
945typedef struct
946{
947 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
948 __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
949 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
950 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
951 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
952 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
953 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
954 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
955 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
956 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
957 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
958 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
959 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
960 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
961 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
962 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
963 __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
964 uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
965 __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
966 __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
967 __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
968 __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
969 uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
970 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
971} SDMMC_TypeDef;
972/**
973 * @brief Serial Peripheral Interface
974 */
975
976typedef struct
977{
978 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
979 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
980 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
981 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
982 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
983 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
984 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
985} SPI_TypeDef;
986
987
988/**
989 * @brief System configuration controller
990 */
991
992typedef struct
993{
994 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
995 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
996 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
997 __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */
998 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
999 __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */
1000 __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */
1001 __IO uint32_t SWPR2; /*!< SYSCFG SRAM2 write protection register 2, Address offset: 0x28 */
1002} SYSCFG_TypeDef;
1003
1004
1005/**
1006 * @brief TIM
1007 */
1008
1009typedef struct
1010{
1011 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
1012 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
1013 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
1014 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
1015 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
1016 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
1017 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
1018 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
1019 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
1020 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
1021 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
1022 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
1023 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
1024 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
1025 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
1026 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
1027 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
1028 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
1029 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
1030 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
1031 __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */
1032 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
1033 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
1034 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
1035 __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */
1036 __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */
1037} TIM_TypeDef;
1038
1039
1040/**
1041 * @brief Touch Sensing Controller (TSC)
1042 */
1043
1044typedef struct
1045{
1046 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
1047 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
1048 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
1049 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
1050 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
1051 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
1052 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
1053 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
1054 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
1055 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
1056 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
1057 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
1058 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
1059 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
1060} TSC_TypeDef;
1061
1062/**
1063 * @brief Universal Synchronous Asynchronous Receiver Transmitter
1064 */
1065
1066typedef struct
1067{
1068 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
1069 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
1070 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
1071 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
1072 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
1073 uint16_t RESERVED2; /*!< Reserved, 0x12 */
1074 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
1075 __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
1076 uint16_t RESERVED3; /*!< Reserved, 0x1A */
1077 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
1078 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
1079 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
1080 uint16_t RESERVED4; /*!< Reserved, 0x26 */
1081 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
1082 uint16_t RESERVED5; /*!< Reserved, 0x2A */
1083 __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
1084} USART_TypeDef;
1085
1086/**
1087 * @brief VREFBUF
1088 */
1089
1090typedef struct
1091{
1092 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
1093 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
1094} VREFBUF_TypeDef;
1095
1096/**
1097 * @brief Window WATCHDOG
1098 */
1099
1100typedef struct
1101{
1102 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
1103 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
1104 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
1105} WWDG_TypeDef;
1106
1107/**
1108 * @brief AES hardware accelerator
1109 */
1110
1111typedef struct
1112{
1113 __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
1114 __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
1115 __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
1116 __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
1117 __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
1118 __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
1119 __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
1120 __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
1121 __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
1122 __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
1123 __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
1124 __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
1125 __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */
1126 __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */
1127 __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */
1128 __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */
1129 __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */
1130 __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */
1131 __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */
1132 __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */
1133 __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */
1134 __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */
1135 __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */
1136 __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */
1137} AES_TypeDef;
1138
1139/**
1140 * @brief HASH
1141 */
1142
1143typedef struct
1144{
1145 __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
1146 __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
1147 __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
1148 __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
1149 __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
1150 __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
1151 uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
1152 __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
1153} HASH_TypeDef;
1154
1155/**
1156 * @brief HASH_DIGEST
1157 */
1158
1159typedef struct
1160{
1161 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
1162} HASH_DIGEST_TypeDef;
1163
1164/**
1165 * @brief RNG
1166 */
1167
1168typedef struct
1169{
1170 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
1171 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
1172 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
1173} RNG_TypeDef;
1174
1175/**
1176 * @brief USB_OTG_Core_register
1177 */
1178typedef struct
1179{
1180 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/
1181 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/
1182 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/
1183 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/
1184 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/
1185 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/
1186 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/
1187 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/
1188 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/
1189 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
1190 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
1191 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
1192 uint32_t Reserved30[2]; /* Reserved 030h*/
1193 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
1194 __IO uint32_t CID; /* User ID Register 03Ch*/
1195 __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
1196 __IO uint32_t GHWCFG1; /* User HW config1 044h*/
1197 __IO uint32_t GHWCFG2; /* User HW config2 048h*/
1198 __IO uint32_t GHWCFG3; /* User HW config3 04Ch*/
1199 uint32_t Reserved6; /* Reserved 050h*/
1200 __IO uint32_t GLPMCFG; /* LPM Register 054h*/
1201 __IO uint32_t GPWRDN; /* Power Down Register 058h*/
1202 __IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/
1203 __IO uint32_t GADPCTL; /* ADP Timer, Control and Status Register 60Ch*/
1204 uint32_t Reserved43[39]; /* Reserved 058h-0FFh*/
1205 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
1206 __IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */
1207} USB_OTG_GlobalTypeDef;
1208
1209/**
1210 * @brief USB_OTG_device_Registers
1211 */
1212typedef struct
1213{
1214 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
1215 __IO uint32_t DCTL; /* dev Control Register 804h*/
1216 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
1217 uint32_t Reserved0C; /* Reserved 80Ch*/
1218 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
1219 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
1220 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
1221 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
1222 uint32_t Reserved20; /* Reserved 820h*/
1223 uint32_t Reserved9; /* Reserved 824h*/
1224 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
1225 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
1226 __IO uint32_t DTHRCTL; /* dev thr 830h*/
1227 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
1228 __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
1229 __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
1230 uint32_t Reserved40; /* dedicated EP mask 840h*/
1231 __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
1232 uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
1233 __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
1234} USB_OTG_DeviceTypeDef;
1235
1236/**
1237 * @brief USB_OTG_IN_Endpoint-Specific_Register
1238 */
1239typedef struct
1240{
1241 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
1242 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
1243 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
1244 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
1245 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
1246 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
1247 __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
1248 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
1249} USB_OTG_INEndpointTypeDef;
1250
1251/**
1252 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1253 */
1254typedef struct
1255{
1256 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
1257 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
1258 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
1259 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
1260 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
1261 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
1262 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
1263} USB_OTG_OUTEndpointTypeDef;
1264
1265/**
1266 * @brief USB_OTG_Host_Mode_Register_Structures
1267 */
1268typedef struct
1269{
1270 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
1271 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
1272 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
1273 uint32_t Reserved40C; /* Reserved 40Ch*/
1274 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
1275 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
1276 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
1277} USB_OTG_HostTypeDef;
1278
1279/**
1280 * @brief USB_OTG_Host_Channel_Specific_Registers
1281 */
1282typedef struct
1283{
1284 __IO uint32_t HCCHAR;
1285 __IO uint32_t HCSPLT;
1286 __IO uint32_t HCINT;
1287 __IO uint32_t HCINTMSK;
1288 __IO uint32_t HCTSIZ;
1289 __IO uint32_t HCDMA;
1290 uint32_t Reserved[2];
1291} USB_OTG_HostChannelTypeDef;
1292
1293/**
1294 * @}
1295 */
1296
1297/** @addtogroup Peripheral_memory_map
1298 * @{
1299 */
1300#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 2 MB) base address */
1301#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 192 KB) base address */
1302#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(64 KB) base address */
1303#define SRAM3_BASE ((uint32_t)0x20040000U) /*!< SRAM3(384 KB) base address */
1304#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */
1305#define FMC_BASE ((uint32_t)0x60000000U) /*!< FMC base address */
1306#define OCTOSPI1_BASE ((uint32_t)0x90000000U) /*!< OCTOSPI1 memories accessible over AHB base address */
1307#define OCTOSPI2_BASE ((uint32_t)0x70000000U) /*!< OCTOSPI2 memories accessible over AHB base address */
1308
1309#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */
1310#define OCTOSPI1_R_BASE ((uint32_t)0xA0001000U) /*!< OCTOSPI1 control registers base address */
1311#define OCTOSPI2_R_BASE ((uint32_t)0xA0001400U) /*!< OCTOSPI2 control registers base address */
1312#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
1313#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
1314
1315/* Legacy defines */
1316#define SRAM_BASE SRAM1_BASE
1317#define SRAM_BB_BASE SRAM1_BB_BASE
1318
1319#define SRAM1_SIZE_MAX ((uint32_t)0x00030000U) /*!< maximum SRAM1 size (up to 192 KBytes) */
1320#define SRAM2_SIZE ((uint32_t)0x00010000U) /*!< SRAM2 size (64 KBytes) */
1321#define SRAM3_SIZE ((uint32_t)0x00060000U) /*!< SRAM3 size (384 KBytes) */
1322
1323/*!< Peripheral memory map */
1324#define APB1PERIPH_BASE PERIPH_BASE
1325#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1326#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1327#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U)
1328
1329#define FMC_BANK1 FMC_BASE
1330#define FMC_BANK1_1 FMC_BANK1
1331#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000U)
1332#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000U)
1333#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000U)
1334#define FMC_BANK3 (FMC_BASE + 0x20000000U)
1335
1336/*!< APB1 peripherals */
1337#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1338#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1339#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1340#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1341#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1342#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1343#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1344#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1345#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1346#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1347#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1348#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1349#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1350#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1351#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1352#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1353#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1354#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1355#define CRS_BASE (APB1PERIPH_BASE + 0x6000U)
1356#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1357#define I2C4_BASE (APB1PERIPH_BASE + 0x8400U)
1358#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1359#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1360#define DAC1_BASE (APB1PERIPH_BASE + 0x7400U)
1361#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U)
1362#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U)
1363#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810U)
1364#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U)
1365#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U)
1366#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U)
1367
1368
1369/*!< APB2 peripherals */
1370#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U)
1371#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U)
1372#define COMP1_BASE (APB2PERIPH_BASE + 0x0200U)
1373#define COMP2_BASE (APB2PERIPH_BASE + 0x0204U)
1374#define EXTI_BASE (APB2PERIPH_BASE + 0x0400U)
1375#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U)
1376#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U)
1377#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1378#define TIM8_BASE (APB2PERIPH_BASE + 0x3400U)
1379#define USART1_BASE (APB2PERIPH_BASE + 0x3800U)
1380#define TIM15_BASE (APB2PERIPH_BASE + 0x4000U)
1381#define TIM16_BASE (APB2PERIPH_BASE + 0x4400U)
1382#define TIM17_BASE (APB2PERIPH_BASE + 0x4800U)
1383#define SAI1_BASE (APB2PERIPH_BASE + 0x5400U)
1384#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
1385#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
1386#define SAI2_BASE (APB2PERIPH_BASE + 0x5800U)
1387#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
1388#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
1389#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U)
1390#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00)
1391#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20)
1392#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40)
1393#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60)
1394#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80)
1395#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0)
1396#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0)
1397#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0)
1398#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100)
1399#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180)
1400#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200)
1401#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280)
1402
1403/*!< AHB1 peripherals */
1404#define DMA1_BASE (AHB1PERIPH_BASE)
1405#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U)
1406#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800U)
1407#define RCC_BASE (AHB1PERIPH_BASE + 0x1000U)
1408#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U)
1409#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1410#define TSC_BASE (AHB1PERIPH_BASE + 0x4000U)
1411#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
1412
1413
1414#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U)
1415#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU)
1416#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U)
1417#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U)
1418#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U)
1419#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU)
1420#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U)
1421
1422
1423#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U)
1424#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU)
1425#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U)
1426#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U)
1427#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U)
1428#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU)
1429#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U)
1430
1431#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
1432#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004)
1433#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008)
1434#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000C)
1435#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010)
1436#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014)
1437#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018)
1438#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0000001C)
1439#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x00000020)
1440#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x00000024)
1441#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x00000028)
1442#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0000002C)
1443#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x00000030)
1444#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x00000034)
1445
1446#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100)
1447#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104)
1448#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108)
1449#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010C)
1450
1451#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080)
1452#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140)
1453
1454/*!< AHB2 peripherals */
1455#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U)
1456#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U)
1457#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U)
1458#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U)
1459#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U)
1460#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400U)
1461#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800U)
1462#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U)
1463#define GPIOI_BASE (AHB2PERIPH_BASE + 0x2000U)
1464
1465#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000U)
1466
1467#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U)
1468#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U)
1469
1470#define DCMI_BASE (AHB2PERIPH_BASE + 0x08050000U)
1471
1472#define AES_BASE (AHB2PERIPH_BASE + 0x08060000U)
1473#define HASH_BASE (AHB2PERIPH_BASE + 0x08060400U)
1474#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x08060710U)
1475#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U)
1476
1477#define OCTOSPIM_BASE (AHB2PERIPH_BASE + 0x08061C00U)
1478#define SDMMC1_BASE (AHB2PERIPH_BASE + 0x08062400U)
1479
1480/*!< FMC Banks registers base address */
1481#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1482#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1483#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
1484
1485/* Debug MCU registers base address */
1486#define DBGMCU_BASE ((uint32_t)0xE0042000U)
1487
1488/*!< USB registers base address */
1489#define USB_OTG_FS_PERIPH_BASE ((uint32_t)0x50000000U)
1490
1491#define USB_OTG_GLOBAL_BASE ((uint32_t)0x00000000U)
1492#define USB_OTG_DEVICE_BASE ((uint32_t)0x00000800U)
1493#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t)0x00000900U)
1494#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t)0x00000B00U)
1495#define USB_OTG_EP_REG_SIZE ((uint32_t)0x00000020U)
1496#define USB_OTG_HOST_BASE ((uint32_t)0x00000400U)
1497#define USB_OTG_HOST_PORT_BASE ((uint32_t)0x00000440U)
1498#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t)0x00000500U)
1499#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t)0x00000020U)
1500#define USB_OTG_PCGCCTL_BASE ((uint32_t)0x00000E00U)
1501#define USB_OTG_FIFO_BASE ((uint32_t)0x00001000U)
1502#define USB_OTG_FIFO_SIZE ((uint32_t)0x00001000U)
1503
1504
1505#define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */
1506#define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */
1507#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */
1508/**
1509 * @}
1510 */
1511
1512/** @addtogroup Peripheral_declaration
1513 * @{
1514 */
1515#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1516#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1517#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1518#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1519#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1520#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1521#define RTC ((RTC_TypeDef *) RTC_BASE)
1522#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1523#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1524#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1525#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1526#define USART2 ((USART_TypeDef *) USART2_BASE)
1527#define USART3 ((USART_TypeDef *) USART3_BASE)
1528#define UART4 ((USART_TypeDef *) UART4_BASE)
1529#define UART5 ((USART_TypeDef *) UART5_BASE)
1530#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1531#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1532#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1533#define CRS ((CRS_TypeDef *) CRS_BASE)
1534#define CAN ((CAN_TypeDef *) CAN1_BASE)
1535#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1536#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
1537#define PWR ((PWR_TypeDef *) PWR_BASE)
1538#define DAC ((DAC_TypeDef *) DAC1_BASE)
1539#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
1540#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
1541#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
1542#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
1543#define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
1544#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1545#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
1546#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
1547
1548#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1549#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
1550#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
1551#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
1552#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
1553#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1554#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
1555#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1556#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1557#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1558#define USART1 ((USART_TypeDef *) USART1_BASE)
1559#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
1560#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
1561#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
1562#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1563#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1564#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1565#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1566#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1567#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1568#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
1569#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
1570#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
1571#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
1572#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
1573#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
1574#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
1575#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
1576#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
1577#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
1578#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
1579#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
1580/* Aliases to keep compatibility after DFSDM renaming */
1581#define DFSDM_Channel0 DFSDM1_Channel0
1582#define DFSDM_Channel1 DFSDM1_Channel1
1583#define DFSDM_Channel2 DFSDM1_Channel2
1584#define DFSDM_Channel3 DFSDM1_Channel3
1585#define DFSDM_Channel4 DFSDM1_Channel4
1586#define DFSDM_Channel5 DFSDM1_Channel5
1587#define DFSDM_Channel6 DFSDM1_Channel6
1588#define DFSDM_Channel7 DFSDM1_Channel7
1589#define DFSDM_Filter0 DFSDM1_Filter0
1590#define DFSDM_Filter1 DFSDM1_Filter1
1591#define DFSDM_Filter2 DFSDM1_Filter2
1592#define DFSDM_Filter3 DFSDM1_Filter3
1593#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1594#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1595#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
1596#define RCC ((RCC_TypeDef *) RCC_BASE)
1597#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1598#define CRC ((CRC_TypeDef *) CRC_BASE)
1599#define TSC ((TSC_TypeDef *) TSC_BASE)
1600
1601#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1602#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1603#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1604#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1605#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1606#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1607#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1608#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1609#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1610#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1611#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
1612#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1613#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1614#define HASH ((HASH_TypeDef *) HASH_BASE)
1615#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
1616#define AES ((AES_TypeDef *) AES_BASE)
1617#define RNG ((RNG_TypeDef *) RNG_BASE)
1618#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1619
1620
1621#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1622#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1623#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1624#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1625#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1626#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1627#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1628
1629
1630#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1631#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1632#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1633#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1634#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1635#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
1636#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
1637
1638#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
1639#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
1640#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
1641#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
1642#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
1643#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
1644#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
1645#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
1646#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
1647#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
1648#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
1649#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
1650#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
1651#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
1652
1653#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
1654#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
1655#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
1656#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
1657
1658#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
1659#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
1660
1661
1662#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1663#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1664#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1665
1666#define OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)
1667#define OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)
1668#define OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)
1669
1670#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1671
1672#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1673/**
1674 * @}
1675 */
1676
1677/** @addtogroup Exported_constants
1678 * @{
1679 */
1680
1681/** @addtogroup Peripheral_Registers_Bits_Definition
1682 * @{
1683 */
1684
1685/******************************************************************************/
1686/* Peripheral Registers_Bits_Definition */
1687/******************************************************************************/
1688
1689/******************************************************************************/
1690/* */
1691/* Analog to Digital Converter */
1692/* */
1693/******************************************************************************/
1694
1695/*
1696 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
1697 */
1698
1699/******************** Bit definition for ADC_ISR register *******************/
1700#define ADC_ISR_ADRDY_Pos (0U)
1701#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
1702#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
1703#define ADC_ISR_EOSMP_Pos (1U)
1704#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
1705#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
1706#define ADC_ISR_EOC_Pos (2U)
1707#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
1708#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
1709#define ADC_ISR_EOS_Pos (3U)
1710#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
1711#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
1712#define ADC_ISR_OVR_Pos (4U)
1713#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
1714#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
1715#define ADC_ISR_JEOC_Pos (5U)
1716#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
1717#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
1718#define ADC_ISR_JEOS_Pos (6U)
1719#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
1720#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
1721#define ADC_ISR_AWD1_Pos (7U)
1722#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
1723#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
1724#define ADC_ISR_AWD2_Pos (8U)
1725#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
1726#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
1727#define ADC_ISR_AWD3_Pos (9U)
1728#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
1729#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
1730#define ADC_ISR_JQOVF_Pos (10U)
1731#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
1732#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
1733
1734/******************** Bit definition for ADC_IER register *******************/
1735#define ADC_IER_ADRDYIE_Pos (0U)
1736#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
1737#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
1738#define ADC_IER_EOSMPIE_Pos (1U)
1739#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
1740#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
1741#define ADC_IER_EOCIE_Pos (2U)
1742#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
1743#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
1744#define ADC_IER_EOSIE_Pos (3U)
1745#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
1746#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
1747#define ADC_IER_OVRIE_Pos (4U)
1748#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
1749#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
1750#define ADC_IER_JEOCIE_Pos (5U)
1751#define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
1752#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
1753#define ADC_IER_JEOSIE_Pos (6U)
1754#define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
1755#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
1756#define ADC_IER_AWD1IE_Pos (7U)
1757#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
1758#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
1759#define ADC_IER_AWD2IE_Pos (8U)
1760#define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
1761#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
1762#define ADC_IER_AWD3IE_Pos (9U)
1763#define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
1764#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
1765#define ADC_IER_JQOVFIE_Pos (10U)
1766#define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
1767#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
1768
1769/* Legacy defines */
1770#define ADC_IER_ADRDY (ADC_IER_ADRDYIE)
1771#define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
1772#define ADC_IER_EOC (ADC_IER_EOCIE)
1773#define ADC_IER_EOS (ADC_IER_EOSIE)
1774#define ADC_IER_OVR (ADC_IER_OVRIE)
1775#define ADC_IER_JEOC (ADC_IER_JEOCIE)
1776#define ADC_IER_JEOS (ADC_IER_JEOSIE)
1777#define ADC_IER_AWD1 (ADC_IER_AWD1IE)
1778#define ADC_IER_AWD2 (ADC_IER_AWD2IE)
1779#define ADC_IER_AWD3 (ADC_IER_AWD3IE)
1780#define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
1781
1782/******************** Bit definition for ADC_CR register ********************/
1783#define ADC_CR_ADEN_Pos (0U)
1784#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
1785#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
1786#define ADC_CR_ADDIS_Pos (1U)
1787#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
1788#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
1789#define ADC_CR_ADSTART_Pos (2U)
1790#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
1791#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
1792#define ADC_CR_JADSTART_Pos (3U)
1793#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
1794#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
1795#define ADC_CR_ADSTP_Pos (4U)
1796#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
1797#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
1798#define ADC_CR_JADSTP_Pos (5U)
1799#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
1800#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
1801#define ADC_CR_ADVREGEN_Pos (28U)
1802#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
1803#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
1804#define ADC_CR_DEEPPWD_Pos (29U)
1805#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
1806#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
1807#define ADC_CR_ADCALDIF_Pos (30U)
1808#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
1809#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
1810#define ADC_CR_ADCAL_Pos (31U)
1811#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
1812#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
1813
1814/******************** Bit definition for ADC_CFGR register ******************/
1815#define ADC_CFGR_DMAEN_Pos (0U)
1816#define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
1817#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
1818#define ADC_CFGR_DMACFG_Pos (1U)
1819#define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
1820#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
1821
1822#define ADC_CFGR_DFSDMCFG_Pos (2U)
1823#define ADC_CFGR_DFSDMCFG_Msk (0x1U << ADC_CFGR_DFSDMCFG_Pos) /*!< 0x00000004 */
1824#define ADC_CFGR_DFSDMCFG ADC_CFGR_DFSDMCFG_Msk /*!< ADC DFSDM mode configuration */
1825
1826#define ADC_CFGR_RES_Pos (3U)
1827#define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
1828#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
1829#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
1830#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
1831
1832#define ADC_CFGR_ALIGN_Pos (5U)
1833#define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
1834#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
1835
1836#define ADC_CFGR_EXTSEL_Pos (6U)
1837#define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
1838#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
1839#define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
1840#define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
1841#define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
1842#define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
1843
1844#define ADC_CFGR_EXTEN_Pos (10U)
1845#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
1846#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
1847#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
1848#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
1849
1850#define ADC_CFGR_OVRMOD_Pos (12U)
1851#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
1852#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
1853#define ADC_CFGR_CONT_Pos (13U)
1854#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
1855#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
1856#define ADC_CFGR_AUTDLY_Pos (14U)
1857#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
1858#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
1859
1860#define ADC_CFGR_DISCEN_Pos (16U)
1861#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
1862#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
1863
1864#define ADC_CFGR_DISCNUM_Pos (17U)
1865#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
1866#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
1867#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
1868#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
1869#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
1870
1871#define ADC_CFGR_JDISCEN_Pos (20U)
1872#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
1873#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
1874#define ADC_CFGR_JQM_Pos (21U)
1875#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
1876#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
1877#define ADC_CFGR_AWD1SGL_Pos (22U)
1878#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
1879#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1880#define ADC_CFGR_AWD1EN_Pos (23U)
1881#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
1882#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1883#define ADC_CFGR_JAWD1EN_Pos (24U)
1884#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
1885#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1886#define ADC_CFGR_JAUTO_Pos (25U)
1887#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
1888#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
1889
1890#define ADC_CFGR_AWD1CH_Pos (26U)
1891#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
1892#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
1893#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
1894#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
1895#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
1896#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
1897#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
1898
1899#define ADC_CFGR_JQDIS_Pos (31U)
1900#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
1901#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
1902
1903/******************** Bit definition for ADC_CFGR2 register *****************/
1904#define ADC_CFGR2_ROVSE_Pos (0U)
1905#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
1906#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
1907#define ADC_CFGR2_JOVSE_Pos (1U)
1908#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
1909#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
1910
1911#define ADC_CFGR2_OVSR_Pos (2U)
1912#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
1913#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
1914#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
1915#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
1916#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
1917
1918#define ADC_CFGR2_OVSS_Pos (5U)
1919#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
1920#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
1921#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
1922#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
1923#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
1924#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
1925
1926#define ADC_CFGR2_TROVS_Pos (9U)
1927#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
1928#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1929#define ADC_CFGR2_ROVSM_Pos (10U)
1930#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
1931#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
1932
1933/******************** Bit definition for ADC_SMPR1 register *****************/
1934#define ADC_SMPR1_SMP0_Pos (0U)
1935#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
1936#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
1937#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
1938#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
1939#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
1940
1941#define ADC_SMPR1_SMP1_Pos (3U)
1942#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
1943#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
1944#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
1945#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
1946#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
1947
1948#define ADC_SMPR1_SMP2_Pos (6U)
1949#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
1950#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
1951#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
1952#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
1953#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
1954
1955#define ADC_SMPR1_SMP3_Pos (9U)
1956#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
1957#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
1958#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
1959#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
1960#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
1961
1962#define ADC_SMPR1_SMP4_Pos (12U)
1963#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
1964#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
1965#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
1966#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
1967#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
1968
1969#define ADC_SMPR1_SMP5_Pos (15U)
1970#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
1971#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
1972#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
1973#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
1974#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
1975
1976#define ADC_SMPR1_SMP6_Pos (18U)
1977#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
1978#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
1979#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
1980#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
1981#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
1982
1983#define ADC_SMPR1_SMP7_Pos (21U)
1984#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
1985#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
1986#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
1987#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
1988#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
1989
1990#define ADC_SMPR1_SMP8_Pos (24U)
1991#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
1992#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
1993#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
1994#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
1995#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
1996
1997#define ADC_SMPR1_SMP9_Pos (27U)
1998#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
1999#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
2000#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
2001#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
2002#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
2003
2004#define ADC_SMPR1_SMPPLUS_Pos (31U)
2005#define ADC_SMPR1_SMPPLUS_Msk (0x1U << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */
2006#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */
2007
2008/******************** Bit definition for ADC_SMPR2 register *****************/
2009#define ADC_SMPR2_SMP10_Pos (0U)
2010#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
2011#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
2012#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
2013#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
2014#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
2015
2016#define ADC_SMPR2_SMP11_Pos (3U)
2017#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
2018#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
2019#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
2020#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
2021#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
2022
2023#define ADC_SMPR2_SMP12_Pos (6U)
2024#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
2025#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
2026#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
2027#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
2028#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
2029
2030#define ADC_SMPR2_SMP13_Pos (9U)
2031#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
2032#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
2033#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
2034#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
2035#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
2036
2037#define ADC_SMPR2_SMP14_Pos (12U)
2038#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
2039#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
2040#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
2041#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
2042#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
2043
2044#define ADC_SMPR2_SMP15_Pos (15U)
2045#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
2046#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
2047#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
2048#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
2049#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
2050
2051#define ADC_SMPR2_SMP16_Pos (18U)
2052#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
2053#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
2054#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
2055#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
2056#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
2057
2058#define ADC_SMPR2_SMP17_Pos (21U)
2059#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
2060#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
2061#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
2062#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
2063#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
2064
2065#define ADC_SMPR2_SMP18_Pos (24U)
2066#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
2067#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
2068#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
2069#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
2070#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
2071
2072/******************** Bit definition for ADC_TR1 register *******************/
2073#define ADC_TR1_LT1_Pos (0U)
2074#define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
2075#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
2076#define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
2077#define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
2078#define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
2079#define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
2080#define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
2081#define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
2082#define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
2083#define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
2084#define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
2085#define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
2086#define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
2087#define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
2088
2089#define ADC_TR1_HT1_Pos (16U)
2090#define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
2091#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
2092#define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
2093#define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
2094#define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
2095#define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
2096#define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
2097#define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
2098#define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
2099#define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
2100#define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
2101#define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
2102#define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
2103#define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
2104
2105/******************** Bit definition for ADC_TR2 register *******************/
2106#define ADC_TR2_LT2_Pos (0U)
2107#define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
2108#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
2109#define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
2110#define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
2111#define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
2112#define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
2113#define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
2114#define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
2115#define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
2116#define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
2117
2118#define ADC_TR2_HT2_Pos (16U)
2119#define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
2120#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
2121#define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
2122#define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
2123#define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
2124#define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
2125#define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
2126#define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
2127#define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
2128#define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
2129
2130/******************** Bit definition for ADC_TR3 register *******************/
2131#define ADC_TR3_LT3_Pos (0U)
2132#define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
2133#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
2134#define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
2135#define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
2136#define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
2137#define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
2138#define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
2139#define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
2140#define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
2141#define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
2142
2143#define ADC_TR3_HT3_Pos (16U)
2144#define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
2145#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
2146#define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
2147#define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
2148#define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
2149#define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
2150#define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
2151#define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
2152#define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
2153#define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
2154
2155/******************** Bit definition for ADC_SQR1 register ******************/
2156#define ADC_SQR1_L_Pos (0U)
2157#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */
2158#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
2159#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */
2160#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */
2161#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */
2162#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */
2163
2164#define ADC_SQR1_SQ1_Pos (6U)
2165#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
2166#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
2167#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
2168#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
2169#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
2170#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
2171#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
2172
2173#define ADC_SQR1_SQ2_Pos (12U)
2174#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
2175#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
2176#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
2177#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
2178#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
2179#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
2180#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
2181
2182#define ADC_SQR1_SQ3_Pos (18U)
2183#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
2184#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
2185#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
2186#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
2187#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
2188#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
2189#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
2190
2191#define ADC_SQR1_SQ4_Pos (24U)
2192#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
2193#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
2194#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
2195#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
2196#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
2197#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
2198#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
2199
2200/******************** Bit definition for ADC_SQR2 register ******************/
2201#define ADC_SQR2_SQ5_Pos (0U)
2202#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
2203#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
2204#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
2205#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
2206#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
2207#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
2208#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
2209
2210#define ADC_SQR2_SQ6_Pos (6U)
2211#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
2212#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
2213#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
2214#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
2215#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
2216#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
2217#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
2218
2219#define ADC_SQR2_SQ7_Pos (12U)
2220#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
2221#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
2222#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
2223#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
2224#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
2225#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
2226#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
2227
2228#define ADC_SQR2_SQ8_Pos (18U)
2229#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
2230#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
2231#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
2232#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
2233#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
2234#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
2235#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
2236
2237#define ADC_SQR2_SQ9_Pos (24U)
2238#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
2239#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
2240#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
2241#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
2242#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
2243#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
2244#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
2245
2246/******************** Bit definition for ADC_SQR3 register ******************/
2247#define ADC_SQR3_SQ10_Pos (0U)
2248#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
2249#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
2250#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
2251#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
2252#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
2253#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
2254#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
2255
2256#define ADC_SQR3_SQ11_Pos (6U)
2257#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
2258#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
2259#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
2260#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
2261#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
2262#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
2263#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
2264
2265#define ADC_SQR3_SQ12_Pos (12U)
2266#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
2267#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
2268#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
2269#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
2270#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
2271#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
2272#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
2273
2274#define ADC_SQR3_SQ13_Pos (18U)
2275#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
2276#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
2277#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
2278#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
2279#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
2280#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
2281#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
2282
2283#define ADC_SQR3_SQ14_Pos (24U)
2284#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
2285#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
2286#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
2287#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
2288#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
2289#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
2290#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
2291
2292/******************** Bit definition for ADC_SQR4 register ******************/
2293#define ADC_SQR4_SQ15_Pos (0U)
2294#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
2295#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
2296#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
2297#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
2298#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
2299#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
2300#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
2301
2302#define ADC_SQR4_SQ16_Pos (6U)
2303#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
2304#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
2305#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
2306#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
2307#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
2308#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
2309#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
2310
2311/******************** Bit definition for ADC_DR register ********************/
2312#define ADC_DR_RDATA_Pos (0U)
2313#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
2314#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
2315#define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
2316#define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
2317#define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
2318#define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
2319#define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
2320#define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
2321#define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
2322#define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
2323#define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
2324#define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
2325#define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
2326#define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
2327#define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
2328#define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
2329#define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
2330#define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
2331
2332/******************** Bit definition for ADC_JSQR register ******************/
2333#define ADC_JSQR_JL_Pos (0U)
2334#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
2335#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
2336#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
2337#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
2338
2339#define ADC_JSQR_JEXTSEL_Pos (2U)
2340#define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */
2341#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
2342#define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
2343#define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
2344#define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
2345#define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
2346
2347#define ADC_JSQR_JEXTEN_Pos (6U)
2348#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */
2349#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
2350#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */
2351#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
2352
2353#define ADC_JSQR_JSQ1_Pos (8U)
2354#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */
2355#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
2356#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */
2357#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
2358#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
2359#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
2360#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
2361
2362#define ADC_JSQR_JSQ2_Pos (14U)
2363#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
2364#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
2365#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
2366#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
2367#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
2368#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
2369#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
2370
2371#define ADC_JSQR_JSQ3_Pos (20U)
2372#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */
2373#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
2374#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */
2375#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
2376#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
2377#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
2378#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
2379
2380#define ADC_JSQR_JSQ4_Pos (26U)
2381#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */
2382#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
2383#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */
2384#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
2385#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
2386#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
2387#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
2388
2389/******************** Bit definition for ADC_OFR1 register ******************/
2390#define ADC_OFR1_OFFSET1_Pos (0U)
2391#define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
2392#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
2393#define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
2394#define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
2395#define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
2396#define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
2397#define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
2398#define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
2399#define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
2400#define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
2401#define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
2402#define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
2403#define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
2404#define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
2405
2406#define ADC_OFR1_OFFSET1_CH_Pos (26U)
2407#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
2408#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
2409#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
2410#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
2411#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
2412#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
2413#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
2414
2415#define ADC_OFR1_OFFSET1_EN_Pos (31U)
2416#define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
2417#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
2418
2419/******************** Bit definition for ADC_OFR2 register ******************/
2420#define ADC_OFR2_OFFSET2_Pos (0U)
2421#define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
2422#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
2423#define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
2424#define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
2425#define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
2426#define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
2427#define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
2428#define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
2429#define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
2430#define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
2431#define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
2432#define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
2433#define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
2434#define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
2435
2436#define ADC_OFR2_OFFSET2_CH_Pos (26U)
2437#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
2438#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
2439#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
2440#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
2441#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
2442#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
2443#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
2444
2445#define ADC_OFR2_OFFSET2_EN_Pos (31U)
2446#define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
2447#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
2448
2449/******************** Bit definition for ADC_OFR3 register ******************/
2450#define ADC_OFR3_OFFSET3_Pos (0U)
2451#define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
2452#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
2453#define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
2454#define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
2455#define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
2456#define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
2457#define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
2458#define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
2459#define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
2460#define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
2461#define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
2462#define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
2463#define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
2464#define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
2465
2466#define ADC_OFR3_OFFSET3_CH_Pos (26U)
2467#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
2468#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
2469#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
2470#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
2471#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
2472#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
2473#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
2474
2475#define ADC_OFR3_OFFSET3_EN_Pos (31U)
2476#define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
2477#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
2478
2479/******************** Bit definition for ADC_OFR4 register ******************/
2480#define ADC_OFR4_OFFSET4_Pos (0U)
2481#define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
2482#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
2483#define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
2484#define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
2485#define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
2486#define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
2487#define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
2488#define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
2489#define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
2490#define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
2491#define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
2492#define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
2493#define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
2494#define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
2495
2496#define ADC_OFR4_OFFSET4_CH_Pos (26U)
2497#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
2498#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
2499#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
2500#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
2501#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
2502#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
2503#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
2504
2505#define ADC_OFR4_OFFSET4_EN_Pos (31U)
2506#define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
2507#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
2508
2509/******************** Bit definition for ADC_JDR1 register ******************/
2510#define ADC_JDR1_JDATA_Pos (0U)
2511#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
2512#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
2513#define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
2514#define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
2515#define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
2516#define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
2517#define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
2518#define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
2519#define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
2520#define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
2521#define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
2522#define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
2523#define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
2524#define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
2525#define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
2526#define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
2527#define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
2528#define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
2529
2530/******************** Bit definition for ADC_JDR2 register ******************/
2531#define ADC_JDR2_JDATA_Pos (0U)
2532#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
2533#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
2534#define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
2535#define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
2536#define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
2537#define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
2538#define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
2539#define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
2540#define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
2541#define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
2542#define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
2543#define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
2544#define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
2545#define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
2546#define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
2547#define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
2548#define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
2549#define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
2550
2551/******************** Bit definition for ADC_JDR3 register ******************/
2552#define ADC_JDR3_JDATA_Pos (0U)
2553#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
2554#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
2555#define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
2556#define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
2557#define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
2558#define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
2559#define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
2560#define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
2561#define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
2562#define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
2563#define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
2564#define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
2565#define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
2566#define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
2567#define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
2568#define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
2569#define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
2570#define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
2571
2572/******************** Bit definition for ADC_JDR4 register ******************/
2573#define ADC_JDR4_JDATA_Pos (0U)
2574#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
2575#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
2576#define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
2577#define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
2578#define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
2579#define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
2580#define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
2581#define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
2582#define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
2583#define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
2584#define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
2585#define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
2586#define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
2587#define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
2588#define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
2589#define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
2590#define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
2591#define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
2592
2593/******************** Bit definition for ADC_AWD2CR register ****************/
2594#define ADC_AWD2CR_AWD2CH_Pos (0U)
2595#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
2596#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
2597#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
2598#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
2599#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
2600#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
2601#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
2602#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
2603#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
2604#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
2605#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
2606#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
2607#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
2608#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
2609#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
2610#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
2611#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
2612#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
2613#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
2614#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
2615#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
2616
2617/******************** Bit definition for ADC_AWD3CR register ****************/
2618#define ADC_AWD3CR_AWD3CH_Pos (0U)
2619#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
2620#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
2621#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
2622#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
2623#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
2624#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
2625#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
2626#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
2627#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
2628#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
2629#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
2630#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
2631#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
2632#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
2633#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
2634#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
2635#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
2636#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
2637#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
2638#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
2639#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
2640
2641/******************** Bit definition for ADC_DIFSEL register ****************/
2642#define ADC_DIFSEL_DIFSEL_Pos (0U)
2643#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
2644#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
2645#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
2646#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
2647#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
2648#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
2649#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
2650#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
2651#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
2652#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
2653#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
2654#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
2655#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
2656#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
2657#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
2658#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
2659#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
2660#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
2661#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
2662#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
2663#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
2664
2665/******************** Bit definition for ADC_CALFACT register ***************/
2666#define ADC_CALFACT_CALFACT_S_Pos (0U)
2667#define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
2668#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
2669#define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
2670#define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
2671#define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
2672#define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
2673#define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
2674#define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
2675#define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
2676
2677#define ADC_CALFACT_CALFACT_D_Pos (16U)
2678#define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
2679#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
2680#define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
2681#define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
2682#define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
2683#define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
2684#define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
2685#define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
2686#define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
2687
2688/************************* ADC Common registers *****************************/
2689/******************** Bit definition for ADC_CCR register *******************/
2690#define ADC_CCR_CKMODE_Pos (16U)
2691#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
2692#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
2693#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
2694#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
2695
2696#define ADC_CCR_PRESC_Pos (18U)
2697#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
2698#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
2699#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
2700#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
2701#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
2702#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
2703
2704#define ADC_CCR_VREFEN_Pos (22U)
2705#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
2706#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
2707#define ADC_CCR_TSEN_Pos (23U)
2708#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
2709#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
2710#define ADC_CCR_VBATEN_Pos (24U)
2711#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
2712#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
2713
2714/******************************************************************************/
2715/* */
2716/* Controller Area Network */
2717/* */
2718/******************************************************************************/
2719/*!<CAN control and status registers */
2720/******************* Bit definition for CAN_MCR register ********************/
2721#define CAN_MCR_INRQ_Pos (0U)
2722#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
2723#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
2724#define CAN_MCR_SLEEP_Pos (1U)
2725#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
2726#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
2727#define CAN_MCR_TXFP_Pos (2U)
2728#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
2729#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
2730#define CAN_MCR_RFLM_Pos (3U)
2731#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
2732#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
2733#define CAN_MCR_NART_Pos (4U)
2734#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
2735#define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
2736#define CAN_MCR_AWUM_Pos (5U)
2737#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
2738#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
2739#define CAN_MCR_ABOM_Pos (6U)
2740#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
2741#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
2742#define CAN_MCR_TTCM_Pos (7U)
2743#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
2744#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
2745#define CAN_MCR_RESET_Pos (15U)
2746#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
2747#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
2748
2749/******************* Bit definition for CAN_MSR register ********************/
2750#define CAN_MSR_INAK_Pos (0U)
2751#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
2752#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
2753#define CAN_MSR_SLAK_Pos (1U)
2754#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
2755#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
2756#define CAN_MSR_ERRI_Pos (2U)
2757#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
2758#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
2759#define CAN_MSR_WKUI_Pos (3U)
2760#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
2761#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
2762#define CAN_MSR_SLAKI_Pos (4U)
2763#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
2764#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
2765#define CAN_MSR_TXM_Pos (8U)
2766#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
2767#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
2768#define CAN_MSR_RXM_Pos (9U)
2769#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
2770#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
2771#define CAN_MSR_SAMP_Pos (10U)
2772#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
2773#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
2774#define CAN_MSR_RX_Pos (11U)
2775#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
2776#define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
2777
2778/******************* Bit definition for CAN_TSR register ********************/
2779#define CAN_TSR_RQCP0_Pos (0U)
2780#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
2781#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
2782#define CAN_TSR_TXOK0_Pos (1U)
2783#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
2784#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
2785#define CAN_TSR_ALST0_Pos (2U)
2786#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
2787#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
2788#define CAN_TSR_TERR0_Pos (3U)
2789#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
2790#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
2791#define CAN_TSR_ABRQ0_Pos (7U)
2792#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
2793#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
2794#define CAN_TSR_RQCP1_Pos (8U)
2795#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
2796#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
2797#define CAN_TSR_TXOK1_Pos (9U)
2798#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
2799#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
2800#define CAN_TSR_ALST1_Pos (10U)
2801#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
2802#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
2803#define CAN_TSR_TERR1_Pos (11U)
2804#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
2805#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
2806#define CAN_TSR_ABRQ1_Pos (15U)
2807#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
2808#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
2809#define CAN_TSR_RQCP2_Pos (16U)
2810#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
2811#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
2812#define CAN_TSR_TXOK2_Pos (17U)
2813#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
2814#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
2815#define CAN_TSR_ALST2_Pos (18U)
2816#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
2817#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
2818#define CAN_TSR_TERR2_Pos (19U)
2819#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
2820#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
2821#define CAN_TSR_ABRQ2_Pos (23U)
2822#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
2823#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
2824#define CAN_TSR_CODE_Pos (24U)
2825#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
2826#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
2827
2828#define CAN_TSR_TME_Pos (26U)
2829#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
2830#define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
2831#define CAN_TSR_TME0_Pos (26U)
2832#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
2833#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
2834#define CAN_TSR_TME1_Pos (27U)
2835#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
2836#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
2837#define CAN_TSR_TME2_Pos (28U)
2838#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
2839#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
2840
2841#define CAN_TSR_LOW_Pos (29U)
2842#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
2843#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
2844#define CAN_TSR_LOW0_Pos (29U)
2845#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
2846#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
2847#define CAN_TSR_LOW1_Pos (30U)
2848#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
2849#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
2850#define CAN_TSR_LOW2_Pos (31U)
2851#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
2852#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
2853
2854/******************* Bit definition for CAN_RF0R register *******************/
2855#define CAN_RF0R_FMP0_Pos (0U)
2856#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
2857#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
2858#define CAN_RF0R_FULL0_Pos (3U)
2859#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
2860#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
2861#define CAN_RF0R_FOVR0_Pos (4U)
2862#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
2863#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
2864#define CAN_RF0R_RFOM0_Pos (5U)
2865#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
2866#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
2867
2868/******************* Bit definition for CAN_RF1R register *******************/
2869#define CAN_RF1R_FMP1_Pos (0U)
2870#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
2871#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
2872#define CAN_RF1R_FULL1_Pos (3U)
2873#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
2874#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
2875#define CAN_RF1R_FOVR1_Pos (4U)
2876#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
2877#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
2878#define CAN_RF1R_RFOM1_Pos (5U)
2879#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
2880#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
2881
2882/******************** Bit definition for CAN_IER register *******************/
2883#define CAN_IER_TMEIE_Pos (0U)
2884#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
2885#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
2886#define CAN_IER_FMPIE0_Pos (1U)
2887#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
2888#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
2889#define CAN_IER_FFIE0_Pos (2U)
2890#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
2891#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
2892#define CAN_IER_FOVIE0_Pos (3U)
2893#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
2894#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
2895#define CAN_IER_FMPIE1_Pos (4U)
2896#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
2897#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
2898#define CAN_IER_FFIE1_Pos (5U)
2899#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
2900#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
2901#define CAN_IER_FOVIE1_Pos (6U)
2902#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
2903#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
2904#define CAN_IER_EWGIE_Pos (8U)
2905#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
2906#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
2907#define CAN_IER_EPVIE_Pos (9U)
2908#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
2909#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
2910#define CAN_IER_BOFIE_Pos (10U)
2911#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
2912#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
2913#define CAN_IER_LECIE_Pos (11U)
2914#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
2915#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
2916#define CAN_IER_ERRIE_Pos (15U)
2917#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
2918#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
2919#define CAN_IER_WKUIE_Pos (16U)
2920#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
2921#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
2922#define CAN_IER_SLKIE_Pos (17U)
2923#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
2924#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
2925
2926/******************** Bit definition for CAN_ESR register *******************/
2927#define CAN_ESR_EWGF_Pos (0U)
2928#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
2929#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
2930#define CAN_ESR_EPVF_Pos (1U)
2931#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
2932#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
2933#define CAN_ESR_BOFF_Pos (2U)
2934#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
2935#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
2936
2937#define CAN_ESR_LEC_Pos (4U)
2938#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
2939#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
2940#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
2941#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
2942#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
2943
2944#define CAN_ESR_TEC_Pos (16U)
2945#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
2946#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
2947#define CAN_ESR_REC_Pos (24U)
2948#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
2949#define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
2950
2951/******************* Bit definition for CAN_BTR register ********************/
2952#define CAN_BTR_BRP_Pos (0U)
2953#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
2954#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
2955#define CAN_BTR_TS1_Pos (16U)
2956#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
2957#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
2958#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
2959#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
2960#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
2961#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
2962#define CAN_BTR_TS2_Pos (20U)
2963#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
2964#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
2965#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
2966#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
2967#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
2968#define CAN_BTR_SJW_Pos (24U)
2969#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
2970#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
2971#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
2972#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
2973#define CAN_BTR_LBKM_Pos (30U)
2974#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
2975#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
2976#define CAN_BTR_SILM_Pos (31U)
2977#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
2978#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
2979
2980/*!<Mailbox registers */
2981/****************** Bit definition for CAN_TI0R register ********************/
2982#define CAN_TI0R_TXRQ_Pos (0U)
2983#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
2984#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
2985#define CAN_TI0R_RTR_Pos (1U)
2986#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
2987#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
2988#define CAN_TI0R_IDE_Pos (2U)
2989#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
2990#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
2991#define CAN_TI0R_EXID_Pos (3U)
2992#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
2993#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
2994#define CAN_TI0R_STID_Pos (21U)
2995#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
2996#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2997
2998/****************** Bit definition for CAN_TDT0R register *******************/
2999#define CAN_TDT0R_DLC_Pos (0U)
3000#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
3001#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
3002#define CAN_TDT0R_TGT_Pos (8U)
3003#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
3004#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
3005#define CAN_TDT0R_TIME_Pos (16U)
3006#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
3007#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
3008
3009/****************** Bit definition for CAN_TDL0R register *******************/
3010#define CAN_TDL0R_DATA0_Pos (0U)
3011#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
3012#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
3013#define CAN_TDL0R_DATA1_Pos (8U)
3014#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
3015#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
3016#define CAN_TDL0R_DATA2_Pos (16U)
3017#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
3018#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
3019#define CAN_TDL0R_DATA3_Pos (24U)
3020#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
3021#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
3022
3023/****************** Bit definition for CAN_TDH0R register *******************/
3024#define CAN_TDH0R_DATA4_Pos (0U)
3025#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
3026#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
3027#define CAN_TDH0R_DATA5_Pos (8U)
3028#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
3029#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
3030#define CAN_TDH0R_DATA6_Pos (16U)
3031#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
3032#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
3033#define CAN_TDH0R_DATA7_Pos (24U)
3034#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
3035#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
3036
3037/******************* Bit definition for CAN_TI1R register *******************/
3038#define CAN_TI1R_TXRQ_Pos (0U)
3039#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
3040#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
3041#define CAN_TI1R_RTR_Pos (1U)
3042#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
3043#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
3044#define CAN_TI1R_IDE_Pos (2U)
3045#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
3046#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
3047#define CAN_TI1R_EXID_Pos (3U)
3048#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
3049#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
3050#define CAN_TI1R_STID_Pos (21U)
3051#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
3052#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
3053
3054/******************* Bit definition for CAN_TDT1R register ******************/
3055#define CAN_TDT1R_DLC_Pos (0U)
3056#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
3057#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
3058#define CAN_TDT1R_TGT_Pos (8U)
3059#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
3060#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
3061#define CAN_TDT1R_TIME_Pos (16U)
3062#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
3063#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
3064
3065/******************* Bit definition for CAN_TDL1R register ******************/
3066#define CAN_TDL1R_DATA0_Pos (0U)
3067#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
3068#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
3069#define CAN_TDL1R_DATA1_Pos (8U)
3070#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
3071#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
3072#define CAN_TDL1R_DATA2_Pos (16U)
3073#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
3074#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
3075#define CAN_TDL1R_DATA3_Pos (24U)
3076#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
3077#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
3078
3079/******************* Bit definition for CAN_TDH1R register ******************/
3080#define CAN_TDH1R_DATA4_Pos (0U)
3081#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
3082#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
3083#define CAN_TDH1R_DATA5_Pos (8U)
3084#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
3085#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
3086#define CAN_TDH1R_DATA6_Pos (16U)
3087#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
3088#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
3089#define CAN_TDH1R_DATA7_Pos (24U)
3090#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
3091#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
3092
3093/******************* Bit definition for CAN_TI2R register *******************/
3094#define CAN_TI2R_TXRQ_Pos (0U)
3095#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
3096#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
3097#define CAN_TI2R_RTR_Pos (1U)
3098#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
3099#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
3100#define CAN_TI2R_IDE_Pos (2U)
3101#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
3102#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
3103#define CAN_TI2R_EXID_Pos (3U)
3104#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
3105#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
3106#define CAN_TI2R_STID_Pos (21U)
3107#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
3108#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
3109
3110/******************* Bit definition for CAN_TDT2R register ******************/
3111#define CAN_TDT2R_DLC_Pos (0U)
3112#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
3113#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
3114#define CAN_TDT2R_TGT_Pos (8U)
3115#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
3116#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
3117#define CAN_TDT2R_TIME_Pos (16U)
3118#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
3119#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
3120
3121/******************* Bit definition for CAN_TDL2R register ******************/
3122#define CAN_TDL2R_DATA0_Pos (0U)
3123#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
3124#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
3125#define CAN_TDL2R_DATA1_Pos (8U)
3126#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
3127#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
3128#define CAN_TDL2R_DATA2_Pos (16U)
3129#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
3130#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
3131#define CAN_TDL2R_DATA3_Pos (24U)
3132#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
3133#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
3134
3135/******************* Bit definition for CAN_TDH2R register ******************/
3136#define CAN_TDH2R_DATA4_Pos (0U)
3137#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
3138#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
3139#define CAN_TDH2R_DATA5_Pos (8U)
3140#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
3141#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
3142#define CAN_TDH2R_DATA6_Pos (16U)
3143#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
3144#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
3145#define CAN_TDH2R_DATA7_Pos (24U)
3146#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
3147#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
3148
3149/******************* Bit definition for CAN_RI0R register *******************/
3150#define CAN_RI0R_RTR_Pos (1U)
3151#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
3152#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
3153#define CAN_RI0R_IDE_Pos (2U)
3154#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
3155#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
3156#define CAN_RI0R_EXID_Pos (3U)
3157#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
3158#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
3159#define CAN_RI0R_STID_Pos (21U)
3160#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
3161#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
3162
3163/******************* Bit definition for CAN_RDT0R register ******************/
3164#define CAN_RDT0R_DLC_Pos (0U)
3165#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
3166#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
3167#define CAN_RDT0R_FMI_Pos (8U)
3168#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
3169#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
3170#define CAN_RDT0R_TIME_Pos (16U)
3171#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
3172#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
3173
3174/******************* Bit definition for CAN_RDL0R register ******************/
3175#define CAN_RDL0R_DATA0_Pos (0U)
3176#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
3177#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
3178#define CAN_RDL0R_DATA1_Pos (8U)
3179#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
3180#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
3181#define CAN_RDL0R_DATA2_Pos (16U)
3182#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
3183#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
3184#define CAN_RDL0R_DATA3_Pos (24U)
3185#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
3186#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
3187
3188/******************* Bit definition for CAN_RDH0R register ******************/
3189#define CAN_RDH0R_DATA4_Pos (0U)
3190#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
3191#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
3192#define CAN_RDH0R_DATA5_Pos (8U)
3193#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
3194#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
3195#define CAN_RDH0R_DATA6_Pos (16U)
3196#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
3197#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
3198#define CAN_RDH0R_DATA7_Pos (24U)
3199#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
3200#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
3201
3202/******************* Bit definition for CAN_RI1R register *******************/
3203#define CAN_RI1R_RTR_Pos (1U)
3204#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
3205#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
3206#define CAN_RI1R_IDE_Pos (2U)
3207#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
3208#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
3209#define CAN_RI1R_EXID_Pos (3U)
3210#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
3211#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
3212#define CAN_RI1R_STID_Pos (21U)
3213#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
3214#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
3215
3216/******************* Bit definition for CAN_RDT1R register ******************/
3217#define CAN_RDT1R_DLC_Pos (0U)
3218#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
3219#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
3220#define CAN_RDT1R_FMI_Pos (8U)
3221#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
3222#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
3223#define CAN_RDT1R_TIME_Pos (16U)
3224#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
3225#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
3226
3227/******************* Bit definition for CAN_RDL1R register ******************/
3228#define CAN_RDL1R_DATA0_Pos (0U)
3229#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
3230#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
3231#define CAN_RDL1R_DATA1_Pos (8U)
3232#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
3233#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
3234#define CAN_RDL1R_DATA2_Pos (16U)
3235#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
3236#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
3237#define CAN_RDL1R_DATA3_Pos (24U)
3238#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
3239#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
3240
3241/******************* Bit definition for CAN_RDH1R register ******************/
3242#define CAN_RDH1R_DATA4_Pos (0U)
3243#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
3244#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
3245#define CAN_RDH1R_DATA5_Pos (8U)
3246#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
3247#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
3248#define CAN_RDH1R_DATA6_Pos (16U)
3249#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
3250#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
3251#define CAN_RDH1R_DATA7_Pos (24U)
3252#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
3253#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
3254
3255/*!<CAN filter registers */
3256/******************* Bit definition for CAN_FMR register ********************/
3257#define CAN_FMR_FINIT_Pos (0U)
3258#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
3259#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
3260
3261/******************* Bit definition for CAN_FM1R register *******************/
3262#define CAN_FM1R_FBM_Pos (0U)
3263#define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
3264#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
3265#define CAN_FM1R_FBM0_Pos (0U)
3266#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
3267#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
3268#define CAN_FM1R_FBM1_Pos (1U)
3269#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
3270#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
3271#define CAN_FM1R_FBM2_Pos (2U)
3272#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
3273#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
3274#define CAN_FM1R_FBM3_Pos (3U)
3275#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
3276#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
3277#define CAN_FM1R_FBM4_Pos (4U)
3278#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
3279#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
3280#define CAN_FM1R_FBM5_Pos (5U)
3281#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
3282#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
3283#define CAN_FM1R_FBM6_Pos (6U)
3284#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
3285#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
3286#define CAN_FM1R_FBM7_Pos (7U)
3287#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
3288#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
3289#define CAN_FM1R_FBM8_Pos (8U)
3290#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
3291#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
3292#define CAN_FM1R_FBM9_Pos (9U)
3293#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
3294#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
3295#define CAN_FM1R_FBM10_Pos (10U)
3296#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
3297#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
3298#define CAN_FM1R_FBM11_Pos (11U)
3299#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
3300#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
3301#define CAN_FM1R_FBM12_Pos (12U)
3302#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
3303#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
3304#define CAN_FM1R_FBM13_Pos (13U)
3305#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
3306#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
3307
3308/******************* Bit definition for CAN_FS1R register *******************/
3309#define CAN_FS1R_FSC_Pos (0U)
3310#define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
3311#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
3312#define CAN_FS1R_FSC0_Pos (0U)
3313#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
3314#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
3315#define CAN_FS1R_FSC1_Pos (1U)
3316#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
3317#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
3318#define CAN_FS1R_FSC2_Pos (2U)
3319#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
3320#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
3321#define CAN_FS1R_FSC3_Pos (3U)
3322#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
3323#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
3324#define CAN_FS1R_FSC4_Pos (4U)
3325#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
3326#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
3327#define CAN_FS1R_FSC5_Pos (5U)
3328#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
3329#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
3330#define CAN_FS1R_FSC6_Pos (6U)
3331#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
3332#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
3333#define CAN_FS1R_FSC7_Pos (7U)
3334#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
3335#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
3336#define CAN_FS1R_FSC8_Pos (8U)
3337#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
3338#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
3339#define CAN_FS1R_FSC9_Pos (9U)
3340#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
3341#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
3342#define CAN_FS1R_FSC10_Pos (10U)
3343#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
3344#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
3345#define CAN_FS1R_FSC11_Pos (11U)
3346#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
3347#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
3348#define CAN_FS1R_FSC12_Pos (12U)
3349#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
3350#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
3351#define CAN_FS1R_FSC13_Pos (13U)
3352#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
3353#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
3354
3355/****************** Bit definition for CAN_FFA1R register *******************/
3356#define CAN_FFA1R_FFA_Pos (0U)
3357#define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
3358#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
3359#define CAN_FFA1R_FFA0_Pos (0U)
3360#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
3361#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
3362#define CAN_FFA1R_FFA1_Pos (1U)
3363#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
3364#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
3365#define CAN_FFA1R_FFA2_Pos (2U)
3366#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
3367#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
3368#define CAN_FFA1R_FFA3_Pos (3U)
3369#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
3370#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
3371#define CAN_FFA1R_FFA4_Pos (4U)
3372#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
3373#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
3374#define CAN_FFA1R_FFA5_Pos (5U)
3375#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
3376#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
3377#define CAN_FFA1R_FFA6_Pos (6U)
3378#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
3379#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
3380#define CAN_FFA1R_FFA7_Pos (7U)
3381#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
3382#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
3383#define CAN_FFA1R_FFA8_Pos (8U)
3384#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
3385#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
3386#define CAN_FFA1R_FFA9_Pos (9U)
3387#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
3388#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
3389#define CAN_FFA1R_FFA10_Pos (10U)
3390#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
3391#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
3392#define CAN_FFA1R_FFA11_Pos (11U)
3393#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
3394#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
3395#define CAN_FFA1R_FFA12_Pos (12U)
3396#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
3397#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
3398#define CAN_FFA1R_FFA13_Pos (13U)
3399#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
3400#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
3401
3402/******************* Bit definition for CAN_FA1R register *******************/
3403#define CAN_FA1R_FACT_Pos (0U)
3404#define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
3405#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
3406#define CAN_FA1R_FACT0_Pos (0U)
3407#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
3408#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
3409#define CAN_FA1R_FACT1_Pos (1U)
3410#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
3411#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
3412#define CAN_FA1R_FACT2_Pos (2U)
3413#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
3414#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
3415#define CAN_FA1R_FACT3_Pos (3U)
3416#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
3417#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
3418#define CAN_FA1R_FACT4_Pos (4U)
3419#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
3420#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
3421#define CAN_FA1R_FACT5_Pos (5U)
3422#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
3423#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
3424#define CAN_FA1R_FACT6_Pos (6U)
3425#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
3426#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
3427#define CAN_FA1R_FACT7_Pos (7U)
3428#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
3429#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
3430#define CAN_FA1R_FACT8_Pos (8U)
3431#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
3432#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
3433#define CAN_FA1R_FACT9_Pos (9U)
3434#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
3435#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
3436#define CAN_FA1R_FACT10_Pos (10U)
3437#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
3438#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
3439#define CAN_FA1R_FACT11_Pos (11U)
3440#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
3441#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
3442#define CAN_FA1R_FACT12_Pos (12U)
3443#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
3444#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
3445#define CAN_FA1R_FACT13_Pos (13U)
3446#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
3447#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
3448
3449/******************* Bit definition for CAN_F0R1 register *******************/
3450#define CAN_F0R1_FB0_Pos (0U)
3451#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
3452#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
3453#define CAN_F0R1_FB1_Pos (1U)
3454#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
3455#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
3456#define CAN_F0R1_FB2_Pos (2U)
3457#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
3458#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
3459#define CAN_F0R1_FB3_Pos (3U)
3460#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
3461#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
3462#define CAN_F0R1_FB4_Pos (4U)
3463#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
3464#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
3465#define CAN_F0R1_FB5_Pos (5U)
3466#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
3467#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
3468#define CAN_F0R1_FB6_Pos (6U)
3469#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
3470#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
3471#define CAN_F0R1_FB7_Pos (7U)
3472#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
3473#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
3474#define CAN_F0R1_FB8_Pos (8U)
3475#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
3476#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
3477#define CAN_F0R1_FB9_Pos (9U)
3478#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
3479#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
3480#define CAN_F0R1_FB10_Pos (10U)
3481#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
3482#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
3483#define CAN_F0R1_FB11_Pos (11U)
3484#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
3485#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
3486#define CAN_F0R1_FB12_Pos (12U)
3487#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
3488#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
3489#define CAN_F0R1_FB13_Pos (13U)
3490#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
3491#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
3492#define CAN_F0R1_FB14_Pos (14U)
3493#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
3494#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
3495#define CAN_F0R1_FB15_Pos (15U)
3496#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
3497#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
3498#define CAN_F0R1_FB16_Pos (16U)
3499#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
3500#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
3501#define CAN_F0R1_FB17_Pos (17U)
3502#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
3503#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
3504#define CAN_F0R1_FB18_Pos (18U)
3505#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
3506#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
3507#define CAN_F0R1_FB19_Pos (19U)
3508#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
3509#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
3510#define CAN_F0R1_FB20_Pos (20U)
3511#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
3512#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
3513#define CAN_F0R1_FB21_Pos (21U)
3514#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
3515#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
3516#define CAN_F0R1_FB22_Pos (22U)
3517#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
3518#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
3519#define CAN_F0R1_FB23_Pos (23U)
3520#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
3521#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
3522#define CAN_F0R1_FB24_Pos (24U)
3523#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
3524#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
3525#define CAN_F0R1_FB25_Pos (25U)
3526#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
3527#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
3528#define CAN_F0R1_FB26_Pos (26U)
3529#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
3530#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
3531#define CAN_F0R1_FB27_Pos (27U)
3532#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
3533#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
3534#define CAN_F0R1_FB28_Pos (28U)
3535#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
3536#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
3537#define CAN_F0R1_FB29_Pos (29U)
3538#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
3539#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
3540#define CAN_F0R1_FB30_Pos (30U)
3541#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
3542#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
3543#define CAN_F0R1_FB31_Pos (31U)
3544#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
3545#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
3546
3547/******************* Bit definition for CAN_F1R1 register *******************/
3548#define CAN_F1R1_FB0_Pos (0U)
3549#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
3550#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
3551#define CAN_F1R1_FB1_Pos (1U)
3552#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
3553#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
3554#define CAN_F1R1_FB2_Pos (2U)
3555#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
3556#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
3557#define CAN_F1R1_FB3_Pos (3U)
3558#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
3559#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
3560#define CAN_F1R1_FB4_Pos (4U)
3561#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
3562#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
3563#define CAN_F1R1_FB5_Pos (5U)
3564#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
3565#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
3566#define CAN_F1R1_FB6_Pos (6U)
3567#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
3568#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
3569#define CAN_F1R1_FB7_Pos (7U)
3570#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
3571#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
3572#define CAN_F1R1_FB8_Pos (8U)
3573#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
3574#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
3575#define CAN_F1R1_FB9_Pos (9U)
3576#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
3577#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
3578#define CAN_F1R1_FB10_Pos (10U)
3579#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
3580#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
3581#define CAN_F1R1_FB11_Pos (11U)
3582#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
3583#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
3584#define CAN_F1R1_FB12_Pos (12U)
3585#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
3586#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
3587#define CAN_F1R1_FB13_Pos (13U)
3588#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
3589#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
3590#define CAN_F1R1_FB14_Pos (14U)
3591#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
3592#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
3593#define CAN_F1R1_FB15_Pos (15U)
3594#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
3595#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
3596#define CAN_F1R1_FB16_Pos (16U)
3597#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
3598#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
3599#define CAN_F1R1_FB17_Pos (17U)
3600#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
3601#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
3602#define CAN_F1R1_FB18_Pos (18U)
3603#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
3604#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
3605#define CAN_F1R1_FB19_Pos (19U)
3606#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
3607#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
3608#define CAN_F1R1_FB20_Pos (20U)
3609#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
3610#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
3611#define CAN_F1R1_FB21_Pos (21U)
3612#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
3613#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
3614#define CAN_F1R1_FB22_Pos (22U)
3615#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
3616#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
3617#define CAN_F1R1_FB23_Pos (23U)
3618#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
3619#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
3620#define CAN_F1R1_FB24_Pos (24U)
3621#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
3622#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
3623#define CAN_F1R1_FB25_Pos (25U)
3624#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
3625#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
3626#define CAN_F1R1_FB26_Pos (26U)
3627#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
3628#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
3629#define CAN_F1R1_FB27_Pos (27U)
3630#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
3631#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
3632#define CAN_F1R1_FB28_Pos (28U)
3633#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
3634#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
3635#define CAN_F1R1_FB29_Pos (29U)
3636#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
3637#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
3638#define CAN_F1R1_FB30_Pos (30U)
3639#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
3640#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
3641#define CAN_F1R1_FB31_Pos (31U)
3642#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
3643#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
3644
3645/******************* Bit definition for CAN_F2R1 register *******************/
3646#define CAN_F2R1_FB0_Pos (0U)
3647#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
3648#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
3649#define CAN_F2R1_FB1_Pos (1U)
3650#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
3651#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
3652#define CAN_F2R1_FB2_Pos (2U)
3653#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
3654#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
3655#define CAN_F2R1_FB3_Pos (3U)
3656#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
3657#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
3658#define CAN_F2R1_FB4_Pos (4U)
3659#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
3660#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
3661#define CAN_F2R1_FB5_Pos (5U)
3662#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
3663#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
3664#define CAN_F2R1_FB6_Pos (6U)
3665#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
3666#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
3667#define CAN_F2R1_FB7_Pos (7U)
3668#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
3669#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
3670#define CAN_F2R1_FB8_Pos (8U)
3671#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
3672#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
3673#define CAN_F2R1_FB9_Pos (9U)
3674#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
3675#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
3676#define CAN_F2R1_FB10_Pos (10U)
3677#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
3678#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
3679#define CAN_F2R1_FB11_Pos (11U)
3680#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
3681#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
3682#define CAN_F2R1_FB12_Pos (12U)
3683#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
3684#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
3685#define CAN_F2R1_FB13_Pos (13U)
3686#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
3687#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
3688#define CAN_F2R1_FB14_Pos (14U)
3689#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
3690#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
3691#define CAN_F2R1_FB15_Pos (15U)
3692#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
3693#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
3694#define CAN_F2R1_FB16_Pos (16U)
3695#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
3696#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
3697#define CAN_F2R1_FB17_Pos (17U)
3698#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
3699#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
3700#define CAN_F2R1_FB18_Pos (18U)
3701#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
3702#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
3703#define CAN_F2R1_FB19_Pos (19U)
3704#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
3705#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
3706#define CAN_F2R1_FB20_Pos (20U)
3707#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
3708#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
3709#define CAN_F2R1_FB21_Pos (21U)
3710#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
3711#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
3712#define CAN_F2R1_FB22_Pos (22U)
3713#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
3714#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
3715#define CAN_F2R1_FB23_Pos (23U)
3716#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
3717#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
3718#define CAN_F2R1_FB24_Pos (24U)
3719#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
3720#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
3721#define CAN_F2R1_FB25_Pos (25U)
3722#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
3723#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
3724#define CAN_F2R1_FB26_Pos (26U)
3725#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
3726#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
3727#define CAN_F2R1_FB27_Pos (27U)
3728#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
3729#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
3730#define CAN_F2R1_FB28_Pos (28U)
3731#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
3732#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
3733#define CAN_F2R1_FB29_Pos (29U)
3734#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
3735#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
3736#define CAN_F2R1_FB30_Pos (30U)
3737#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
3738#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
3739#define CAN_F2R1_FB31_Pos (31U)
3740#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
3741#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
3742
3743/******************* Bit definition for CAN_F3R1 register *******************/
3744#define CAN_F3R1_FB0_Pos (0U)
3745#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
3746#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
3747#define CAN_F3R1_FB1_Pos (1U)
3748#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
3749#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
3750#define CAN_F3R1_FB2_Pos (2U)
3751#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
3752#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
3753#define CAN_F3R1_FB3_Pos (3U)
3754#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
3755#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
3756#define CAN_F3R1_FB4_Pos (4U)
3757#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
3758#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
3759#define CAN_F3R1_FB5_Pos (5U)
3760#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
3761#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
3762#define CAN_F3R1_FB6_Pos (6U)
3763#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
3764#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
3765#define CAN_F3R1_FB7_Pos (7U)
3766#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
3767#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
3768#define CAN_F3R1_FB8_Pos (8U)
3769#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
3770#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
3771#define CAN_F3R1_FB9_Pos (9U)
3772#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
3773#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
3774#define CAN_F3R1_FB10_Pos (10U)
3775#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
3776#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
3777#define CAN_F3R1_FB11_Pos (11U)
3778#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
3779#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
3780#define CAN_F3R1_FB12_Pos (12U)
3781#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
3782#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
3783#define CAN_F3R1_FB13_Pos (13U)
3784#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
3785#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
3786#define CAN_F3R1_FB14_Pos (14U)
3787#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
3788#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
3789#define CAN_F3R1_FB15_Pos (15U)
3790#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
3791#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
3792#define CAN_F3R1_FB16_Pos (16U)
3793#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
3794#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
3795#define CAN_F3R1_FB17_Pos (17U)
3796#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
3797#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
3798#define CAN_F3R1_FB18_Pos (18U)
3799#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
3800#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
3801#define CAN_F3R1_FB19_Pos (19U)
3802#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
3803#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
3804#define CAN_F3R1_FB20_Pos (20U)
3805#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
3806#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
3807#define CAN_F3R1_FB21_Pos (21U)
3808#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
3809#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
3810#define CAN_F3R1_FB22_Pos (22U)
3811#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
3812#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
3813#define CAN_F3R1_FB23_Pos (23U)
3814#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
3815#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
3816#define CAN_F3R1_FB24_Pos (24U)
3817#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
3818#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
3819#define CAN_F3R1_FB25_Pos (25U)
3820#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
3821#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
3822#define CAN_F3R1_FB26_Pos (26U)
3823#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
3824#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
3825#define CAN_F3R1_FB27_Pos (27U)
3826#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
3827#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
3828#define CAN_F3R1_FB28_Pos (28U)
3829#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
3830#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
3831#define CAN_F3R1_FB29_Pos (29U)
3832#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
3833#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
3834#define CAN_F3R1_FB30_Pos (30U)
3835#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
3836#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
3837#define CAN_F3R1_FB31_Pos (31U)
3838#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
3839#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
3840
3841/******************* Bit definition for CAN_F4R1 register *******************/
3842#define CAN_F4R1_FB0_Pos (0U)
3843#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
3844#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
3845#define CAN_F4R1_FB1_Pos (1U)
3846#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
3847#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
3848#define CAN_F4R1_FB2_Pos (2U)
3849#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
3850#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
3851#define CAN_F4R1_FB3_Pos (3U)
3852#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
3853#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
3854#define CAN_F4R1_FB4_Pos (4U)
3855#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
3856#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
3857#define CAN_F4R1_FB5_Pos (5U)
3858#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
3859#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
3860#define CAN_F4R1_FB6_Pos (6U)
3861#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
3862#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
3863#define CAN_F4R1_FB7_Pos (7U)
3864#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
3865#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
3866#define CAN_F4R1_FB8_Pos (8U)
3867#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
3868#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
3869#define CAN_F4R1_FB9_Pos (9U)
3870#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
3871#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
3872#define CAN_F4R1_FB10_Pos (10U)
3873#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
3874#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
3875#define CAN_F4R1_FB11_Pos (11U)
3876#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
3877#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
3878#define CAN_F4R1_FB12_Pos (12U)
3879#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
3880#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
3881#define CAN_F4R1_FB13_Pos (13U)
3882#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
3883#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
3884#define CAN_F4R1_FB14_Pos (14U)
3885#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
3886#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
3887#define CAN_F4R1_FB15_Pos (15U)
3888#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
3889#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
3890#define CAN_F4R1_FB16_Pos (16U)
3891#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
3892#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
3893#define CAN_F4R1_FB17_Pos (17U)
3894#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
3895#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
3896#define CAN_F4R1_FB18_Pos (18U)
3897#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
3898#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
3899#define CAN_F4R1_FB19_Pos (19U)
3900#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
3901#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
3902#define CAN_F4R1_FB20_Pos (20U)
3903#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
3904#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
3905#define CAN_F4R1_FB21_Pos (21U)
3906#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
3907#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
3908#define CAN_F4R1_FB22_Pos (22U)
3909#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
3910#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
3911#define CAN_F4R1_FB23_Pos (23U)
3912#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
3913#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
3914#define CAN_F4R1_FB24_Pos (24U)
3915#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
3916#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
3917#define CAN_F4R1_FB25_Pos (25U)
3918#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
3919#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
3920#define CAN_F4R1_FB26_Pos (26U)
3921#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
3922#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
3923#define CAN_F4R1_FB27_Pos (27U)
3924#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
3925#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
3926#define CAN_F4R1_FB28_Pos (28U)
3927#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
3928#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
3929#define CAN_F4R1_FB29_Pos (29U)
3930#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
3931#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
3932#define CAN_F4R1_FB30_Pos (30U)
3933#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
3934#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
3935#define CAN_F4R1_FB31_Pos (31U)
3936#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
3937#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
3938
3939/******************* Bit definition for CAN_F5R1 register *******************/
3940#define CAN_F5R1_FB0_Pos (0U)
3941#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
3942#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
3943#define CAN_F5R1_FB1_Pos (1U)
3944#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
3945#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
3946#define CAN_F5R1_FB2_Pos (2U)
3947#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
3948#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
3949#define CAN_F5R1_FB3_Pos (3U)
3950#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
3951#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
3952#define CAN_F5R1_FB4_Pos (4U)
3953#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
3954#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
3955#define CAN_F5R1_FB5_Pos (5U)
3956#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
3957#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
3958#define CAN_F5R1_FB6_Pos (6U)
3959#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
3960#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
3961#define CAN_F5R1_FB7_Pos (7U)
3962#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
3963#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
3964#define CAN_F5R1_FB8_Pos (8U)
3965#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
3966#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
3967#define CAN_F5R1_FB9_Pos (9U)
3968#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
3969#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
3970#define CAN_F5R1_FB10_Pos (10U)
3971#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
3972#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
3973#define CAN_F5R1_FB11_Pos (11U)
3974#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
3975#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
3976#define CAN_F5R1_FB12_Pos (12U)
3977#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
3978#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
3979#define CAN_F5R1_FB13_Pos (13U)
3980#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
3981#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
3982#define CAN_F5R1_FB14_Pos (14U)
3983#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
3984#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
3985#define CAN_F5R1_FB15_Pos (15U)
3986#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
3987#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
3988#define CAN_F5R1_FB16_Pos (16U)
3989#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
3990#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
3991#define CAN_F5R1_FB17_Pos (17U)
3992#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
3993#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
3994#define CAN_F5R1_FB18_Pos (18U)
3995#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
3996#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
3997#define CAN_F5R1_FB19_Pos (19U)
3998#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
3999#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
4000#define CAN_F5R1_FB20_Pos (20U)
4001#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
4002#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
4003#define CAN_F5R1_FB21_Pos (21U)
4004#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
4005#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
4006#define CAN_F5R1_FB22_Pos (22U)
4007#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
4008#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
4009#define CAN_F5R1_FB23_Pos (23U)
4010#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
4011#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
4012#define CAN_F5R1_FB24_Pos (24U)
4013#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
4014#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
4015#define CAN_F5R1_FB25_Pos (25U)
4016#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
4017#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
4018#define CAN_F5R1_FB26_Pos (26U)
4019#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
4020#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
4021#define CAN_F5R1_FB27_Pos (27U)
4022#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
4023#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
4024#define CAN_F5R1_FB28_Pos (28U)
4025#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
4026#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
4027#define CAN_F5R1_FB29_Pos (29U)
4028#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
4029#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
4030#define CAN_F5R1_FB30_Pos (30U)
4031#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
4032#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
4033#define CAN_F5R1_FB31_Pos (31U)
4034#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
4035#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
4036
4037/******************* Bit definition for CAN_F6R1 register *******************/
4038#define CAN_F6R1_FB0_Pos (0U)
4039#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
4040#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
4041#define CAN_F6R1_FB1_Pos (1U)
4042#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
4043#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
4044#define CAN_F6R1_FB2_Pos (2U)
4045#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
4046#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
4047#define CAN_F6R1_FB3_Pos (3U)
4048#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
4049#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
4050#define CAN_F6R1_FB4_Pos (4U)
4051#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
4052#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
4053#define CAN_F6R1_FB5_Pos (5U)
4054#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
4055#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
4056#define CAN_F6R1_FB6_Pos (6U)
4057#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
4058#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
4059#define CAN_F6R1_FB7_Pos (7U)
4060#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
4061#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
4062#define CAN_F6R1_FB8_Pos (8U)
4063#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
4064#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
4065#define CAN_F6R1_FB9_Pos (9U)
4066#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
4067#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
4068#define CAN_F6R1_FB10_Pos (10U)
4069#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
4070#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
4071#define CAN_F6R1_FB11_Pos (11U)
4072#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
4073#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
4074#define CAN_F6R1_FB12_Pos (12U)
4075#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
4076#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
4077#define CAN_F6R1_FB13_Pos (13U)
4078#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
4079#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
4080#define CAN_F6R1_FB14_Pos (14U)
4081#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
4082#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
4083#define CAN_F6R1_FB15_Pos (15U)
4084#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
4085#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
4086#define CAN_F6R1_FB16_Pos (16U)
4087#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
4088#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
4089#define CAN_F6R1_FB17_Pos (17U)
4090#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
4091#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
4092#define CAN_F6R1_FB18_Pos (18U)
4093#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
4094#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
4095#define CAN_F6R1_FB19_Pos (19U)
4096#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
4097#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
4098#define CAN_F6R1_FB20_Pos (20U)
4099#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
4100#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
4101#define CAN_F6R1_FB21_Pos (21U)
4102#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
4103#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
4104#define CAN_F6R1_FB22_Pos (22U)
4105#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
4106#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
4107#define CAN_F6R1_FB23_Pos (23U)
4108#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
4109#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
4110#define CAN_F6R1_FB24_Pos (24U)
4111#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
4112#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
4113#define CAN_F6R1_FB25_Pos (25U)
4114#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
4115#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
4116#define CAN_F6R1_FB26_Pos (26U)
4117#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
4118#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
4119#define CAN_F6R1_FB27_Pos (27U)
4120#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
4121#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
4122#define CAN_F6R1_FB28_Pos (28U)
4123#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
4124#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
4125#define CAN_F6R1_FB29_Pos (29U)
4126#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
4127#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
4128#define CAN_F6R1_FB30_Pos (30U)
4129#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
4130#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
4131#define CAN_F6R1_FB31_Pos (31U)
4132#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
4133#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
4134
4135/******************* Bit definition for CAN_F7R1 register *******************/
4136#define CAN_F7R1_FB0_Pos (0U)
4137#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
4138#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
4139#define CAN_F7R1_FB1_Pos (1U)
4140#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
4141#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
4142#define CAN_F7R1_FB2_Pos (2U)
4143#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
4144#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
4145#define CAN_F7R1_FB3_Pos (3U)
4146#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
4147#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
4148#define CAN_F7R1_FB4_Pos (4U)
4149#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
4150#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
4151#define CAN_F7R1_FB5_Pos (5U)
4152#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
4153#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
4154#define CAN_F7R1_FB6_Pos (6U)
4155#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
4156#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
4157#define CAN_F7R1_FB7_Pos (7U)
4158#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
4159#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
4160#define CAN_F7R1_FB8_Pos (8U)
4161#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
4162#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
4163#define CAN_F7R1_FB9_Pos (9U)
4164#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
4165#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
4166#define CAN_F7R1_FB10_Pos (10U)
4167#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
4168#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
4169#define CAN_F7R1_FB11_Pos (11U)
4170#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
4171#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
4172#define CAN_F7R1_FB12_Pos (12U)
4173#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
4174#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
4175#define CAN_F7R1_FB13_Pos (13U)
4176#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
4177#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
4178#define CAN_F7R1_FB14_Pos (14U)
4179#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
4180#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
4181#define CAN_F7R1_FB15_Pos (15U)
4182#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
4183#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
4184#define CAN_F7R1_FB16_Pos (16U)
4185#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
4186#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
4187#define CAN_F7R1_FB17_Pos (17U)
4188#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
4189#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
4190#define CAN_F7R1_FB18_Pos (18U)
4191#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
4192#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
4193#define CAN_F7R1_FB19_Pos (19U)
4194#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
4195#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
4196#define CAN_F7R1_FB20_Pos (20U)
4197#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
4198#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
4199#define CAN_F7R1_FB21_Pos (21U)
4200#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
4201#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
4202#define CAN_F7R1_FB22_Pos (22U)
4203#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
4204#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
4205#define CAN_F7R1_FB23_Pos (23U)
4206#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
4207#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
4208#define CAN_F7R1_FB24_Pos (24U)
4209#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
4210#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
4211#define CAN_F7R1_FB25_Pos (25U)
4212#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
4213#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
4214#define CAN_F7R1_FB26_Pos (26U)
4215#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
4216#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
4217#define CAN_F7R1_FB27_Pos (27U)
4218#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
4219#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
4220#define CAN_F7R1_FB28_Pos (28U)
4221#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
4222#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
4223#define CAN_F7R1_FB29_Pos (29U)
4224#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
4225#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
4226#define CAN_F7R1_FB30_Pos (30U)
4227#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
4228#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
4229#define CAN_F7R1_FB31_Pos (31U)
4230#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
4231#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
4232
4233/******************* Bit definition for CAN_F8R1 register *******************/
4234#define CAN_F8R1_FB0_Pos (0U)
4235#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
4236#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
4237#define CAN_F8R1_FB1_Pos (1U)
4238#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
4239#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
4240#define CAN_F8R1_FB2_Pos (2U)
4241#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
4242#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
4243#define CAN_F8R1_FB3_Pos (3U)
4244#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
4245#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
4246#define CAN_F8R1_FB4_Pos (4U)
4247#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
4248#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
4249#define CAN_F8R1_FB5_Pos (5U)
4250#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
4251#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
4252#define CAN_F8R1_FB6_Pos (6U)
4253#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
4254#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
4255#define CAN_F8R1_FB7_Pos (7U)
4256#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
4257#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
4258#define CAN_F8R1_FB8_Pos (8U)
4259#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
4260#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
4261#define CAN_F8R1_FB9_Pos (9U)
4262#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
4263#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
4264#define CAN_F8R1_FB10_Pos (10U)
4265#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
4266#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
4267#define CAN_F8R1_FB11_Pos (11U)
4268#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
4269#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
4270#define CAN_F8R1_FB12_Pos (12U)
4271#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
4272#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
4273#define CAN_F8R1_FB13_Pos (13U)
4274#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
4275#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
4276#define CAN_F8R1_FB14_Pos (14U)
4277#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
4278#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
4279#define CAN_F8R1_FB15_Pos (15U)
4280#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
4281#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
4282#define CAN_F8R1_FB16_Pos (16U)
4283#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
4284#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
4285#define CAN_F8R1_FB17_Pos (17U)
4286#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
4287#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
4288#define CAN_F8R1_FB18_Pos (18U)
4289#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
4290#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
4291#define CAN_F8R1_FB19_Pos (19U)
4292#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
4293#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
4294#define CAN_F8R1_FB20_Pos (20U)
4295#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
4296#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
4297#define CAN_F8R1_FB21_Pos (21U)
4298#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
4299#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
4300#define CAN_F8R1_FB22_Pos (22U)
4301#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
4302#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
4303#define CAN_F8R1_FB23_Pos (23U)
4304#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
4305#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
4306#define CAN_F8R1_FB24_Pos (24U)
4307#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
4308#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
4309#define CAN_F8R1_FB25_Pos (25U)
4310#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
4311#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
4312#define CAN_F8R1_FB26_Pos (26U)
4313#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
4314#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
4315#define CAN_F8R1_FB27_Pos (27U)
4316#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
4317#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
4318#define CAN_F8R1_FB28_Pos (28U)
4319#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
4320#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
4321#define CAN_F8R1_FB29_Pos (29U)
4322#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
4323#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
4324#define CAN_F8R1_FB30_Pos (30U)
4325#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
4326#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
4327#define CAN_F8R1_FB31_Pos (31U)
4328#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
4329#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
4330
4331/******************* Bit definition for CAN_F9R1 register *******************/
4332#define CAN_F9R1_FB0_Pos (0U)
4333#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
4334#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
4335#define CAN_F9R1_FB1_Pos (1U)
4336#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
4337#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
4338#define CAN_F9R1_FB2_Pos (2U)
4339#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
4340#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
4341#define CAN_F9R1_FB3_Pos (3U)
4342#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
4343#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
4344#define CAN_F9R1_FB4_Pos (4U)
4345#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
4346#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
4347#define CAN_F9R1_FB5_Pos (5U)
4348#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
4349#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
4350#define CAN_F9R1_FB6_Pos (6U)
4351#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
4352#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
4353#define CAN_F9R1_FB7_Pos (7U)
4354#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
4355#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
4356#define CAN_F9R1_FB8_Pos (8U)
4357#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
4358#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
4359#define CAN_F9R1_FB9_Pos (9U)
4360#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
4361#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
4362#define CAN_F9R1_FB10_Pos (10U)
4363#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
4364#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
4365#define CAN_F9R1_FB11_Pos (11U)
4366#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
4367#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
4368#define CAN_F9R1_FB12_Pos (12U)
4369#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
4370#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
4371#define CAN_F9R1_FB13_Pos (13U)
4372#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
4373#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
4374#define CAN_F9R1_FB14_Pos (14U)
4375#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
4376#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
4377#define CAN_F9R1_FB15_Pos (15U)
4378#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
4379#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
4380#define CAN_F9R1_FB16_Pos (16U)
4381#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
4382#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
4383#define CAN_F9R1_FB17_Pos (17U)
4384#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
4385#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
4386#define CAN_F9R1_FB18_Pos (18U)
4387#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
4388#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
4389#define CAN_F9R1_FB19_Pos (19U)
4390#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
4391#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
4392#define CAN_F9R1_FB20_Pos (20U)
4393#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
4394#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
4395#define CAN_F9R1_FB21_Pos (21U)
4396#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
4397#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
4398#define CAN_F9R1_FB22_Pos (22U)
4399#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
4400#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
4401#define CAN_F9R1_FB23_Pos (23U)
4402#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
4403#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
4404#define CAN_F9R1_FB24_Pos (24U)
4405#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
4406#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
4407#define CAN_F9R1_FB25_Pos (25U)
4408#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
4409#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
4410#define CAN_F9R1_FB26_Pos (26U)
4411#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
4412#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
4413#define CAN_F9R1_FB27_Pos (27U)
4414#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
4415#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
4416#define CAN_F9R1_FB28_Pos (28U)
4417#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
4418#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
4419#define CAN_F9R1_FB29_Pos (29U)
4420#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
4421#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
4422#define CAN_F9R1_FB30_Pos (30U)
4423#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
4424#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
4425#define CAN_F9R1_FB31_Pos (31U)
4426#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
4427#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
4428
4429/******************* Bit definition for CAN_F10R1 register ******************/
4430#define CAN_F10R1_FB0_Pos (0U)
4431#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
4432#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
4433#define CAN_F10R1_FB1_Pos (1U)
4434#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
4435#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
4436#define CAN_F10R1_FB2_Pos (2U)
4437#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
4438#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
4439#define CAN_F10R1_FB3_Pos (3U)
4440#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
4441#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
4442#define CAN_F10R1_FB4_Pos (4U)
4443#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
4444#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
4445#define CAN_F10R1_FB5_Pos (5U)
4446#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
4447#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
4448#define CAN_F10R1_FB6_Pos (6U)
4449#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
4450#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
4451#define CAN_F10R1_FB7_Pos (7U)
4452#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
4453#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
4454#define CAN_F10R1_FB8_Pos (8U)
4455#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
4456#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
4457#define CAN_F10R1_FB9_Pos (9U)
4458#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
4459#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
4460#define CAN_F10R1_FB10_Pos (10U)
4461#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
4462#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
4463#define CAN_F10R1_FB11_Pos (11U)
4464#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
4465#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
4466#define CAN_F10R1_FB12_Pos (12U)
4467#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
4468#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
4469#define CAN_F10R1_FB13_Pos (13U)
4470#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
4471#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
4472#define CAN_F10R1_FB14_Pos (14U)
4473#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
4474#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
4475#define CAN_F10R1_FB15_Pos (15U)
4476#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
4477#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
4478#define CAN_F10R1_FB16_Pos (16U)
4479#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
4480#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
4481#define CAN_F10R1_FB17_Pos (17U)
4482#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
4483#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
4484#define CAN_F10R1_FB18_Pos (18U)
4485#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
4486#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
4487#define CAN_F10R1_FB19_Pos (19U)
4488#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
4489#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
4490#define CAN_F10R1_FB20_Pos (20U)
4491#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
4492#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
4493#define CAN_F10R1_FB21_Pos (21U)
4494#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
4495#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
4496#define CAN_F10R1_FB22_Pos (22U)
4497#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
4498#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
4499#define CAN_F10R1_FB23_Pos (23U)
4500#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
4501#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
4502#define CAN_F10R1_FB24_Pos (24U)
4503#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
4504#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
4505#define CAN_F10R1_FB25_Pos (25U)
4506#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
4507#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
4508#define CAN_F10R1_FB26_Pos (26U)
4509#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
4510#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
4511#define CAN_F10R1_FB27_Pos (27U)
4512#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
4513#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
4514#define CAN_F10R1_FB28_Pos (28U)
4515#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
4516#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
4517#define CAN_F10R1_FB29_Pos (29U)
4518#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
4519#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
4520#define CAN_F10R1_FB30_Pos (30U)
4521#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
4522#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
4523#define CAN_F10R1_FB31_Pos (31U)
4524#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
4525#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
4526
4527/******************* Bit definition for CAN_F11R1 register ******************/
4528#define CAN_F11R1_FB0_Pos (0U)
4529#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
4530#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
4531#define CAN_F11R1_FB1_Pos (1U)
4532#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
4533#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
4534#define CAN_F11R1_FB2_Pos (2U)
4535#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
4536#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
4537#define CAN_F11R1_FB3_Pos (3U)
4538#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
4539#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
4540#define CAN_F11R1_FB4_Pos (4U)
4541#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
4542#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
4543#define CAN_F11R1_FB5_Pos (5U)
4544#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
4545#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
4546#define CAN_F11R1_FB6_Pos (6U)
4547#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
4548#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
4549#define CAN_F11R1_FB7_Pos (7U)
4550#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
4551#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
4552#define CAN_F11R1_FB8_Pos (8U)
4553#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
4554#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
4555#define CAN_F11R1_FB9_Pos (9U)
4556#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
4557#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
4558#define CAN_F11R1_FB10_Pos (10U)
4559#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
4560#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
4561#define CAN_F11R1_FB11_Pos (11U)
4562#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
4563#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
4564#define CAN_F11R1_FB12_Pos (12U)
4565#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
4566#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
4567#define CAN_F11R1_FB13_Pos (13U)
4568#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
4569#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
4570#define CAN_F11R1_FB14_Pos (14U)
4571#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
4572#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
4573#define CAN_F11R1_FB15_Pos (15U)
4574#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
4575#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
4576#define CAN_F11R1_FB16_Pos (16U)
4577#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
4578#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
4579#define CAN_F11R1_FB17_Pos (17U)
4580#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
4581#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
4582#define CAN_F11R1_FB18_Pos (18U)
4583#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
4584#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
4585#define CAN_F11R1_FB19_Pos (19U)
4586#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
4587#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
4588#define CAN_F11R1_FB20_Pos (20U)
4589#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
4590#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
4591#define CAN_F11R1_FB21_Pos (21U)
4592#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
4593#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
4594#define CAN_F11R1_FB22_Pos (22U)
4595#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
4596#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
4597#define CAN_F11R1_FB23_Pos (23U)
4598#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
4599#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
4600#define CAN_F11R1_FB24_Pos (24U)
4601#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
4602#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
4603#define CAN_F11R1_FB25_Pos (25U)
4604#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
4605#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
4606#define CAN_F11R1_FB26_Pos (26U)
4607#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
4608#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
4609#define CAN_F11R1_FB27_Pos (27U)
4610#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
4611#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
4612#define CAN_F11R1_FB28_Pos (28U)
4613#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
4614#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
4615#define CAN_F11R1_FB29_Pos (29U)
4616#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
4617#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
4618#define CAN_F11R1_FB30_Pos (30U)
4619#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
4620#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
4621#define CAN_F11R1_FB31_Pos (31U)
4622#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
4623#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
4624
4625/******************* Bit definition for CAN_F12R1 register ******************/
4626#define CAN_F12R1_FB0_Pos (0U)
4627#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
4628#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
4629#define CAN_F12R1_FB1_Pos (1U)
4630#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
4631#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
4632#define CAN_F12R1_FB2_Pos (2U)
4633#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
4634#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
4635#define CAN_F12R1_FB3_Pos (3U)
4636#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
4637#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
4638#define CAN_F12R1_FB4_Pos (4U)
4639#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
4640#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
4641#define CAN_F12R1_FB5_Pos (5U)
4642#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
4643#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
4644#define CAN_F12R1_FB6_Pos (6U)
4645#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
4646#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
4647#define CAN_F12R1_FB7_Pos (7U)
4648#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
4649#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
4650#define CAN_F12R1_FB8_Pos (8U)
4651#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
4652#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
4653#define CAN_F12R1_FB9_Pos (9U)
4654#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
4655#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
4656#define CAN_F12R1_FB10_Pos (10U)
4657#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
4658#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
4659#define CAN_F12R1_FB11_Pos (11U)
4660#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
4661#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
4662#define CAN_F12R1_FB12_Pos (12U)
4663#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
4664#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
4665#define CAN_F12R1_FB13_Pos (13U)
4666#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
4667#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
4668#define CAN_F12R1_FB14_Pos (14U)
4669#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
4670#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
4671#define CAN_F12R1_FB15_Pos (15U)
4672#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
4673#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
4674#define CAN_F12R1_FB16_Pos (16U)
4675#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
4676#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
4677#define CAN_F12R1_FB17_Pos (17U)
4678#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
4679#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
4680#define CAN_F12R1_FB18_Pos (18U)
4681#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
4682#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
4683#define CAN_F12R1_FB19_Pos (19U)
4684#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
4685#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
4686#define CAN_F12R1_FB20_Pos (20U)
4687#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
4688#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
4689#define CAN_F12R1_FB21_Pos (21U)
4690#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
4691#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
4692#define CAN_F12R1_FB22_Pos (22U)
4693#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
4694#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
4695#define CAN_F12R1_FB23_Pos (23U)
4696#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
4697#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
4698#define CAN_F12R1_FB24_Pos (24U)
4699#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
4700#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
4701#define CAN_F12R1_FB25_Pos (25U)
4702#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
4703#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
4704#define CAN_F12R1_FB26_Pos (26U)
4705#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
4706#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
4707#define CAN_F12R1_FB27_Pos (27U)
4708#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
4709#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
4710#define CAN_F12R1_FB28_Pos (28U)
4711#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
4712#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
4713#define CAN_F12R1_FB29_Pos (29U)
4714#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
4715#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
4716#define CAN_F12R1_FB30_Pos (30U)
4717#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
4718#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
4719#define CAN_F12R1_FB31_Pos (31U)
4720#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
4721#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
4722
4723/******************* Bit definition for CAN_F13R1 register ******************/
4724#define CAN_F13R1_FB0_Pos (0U)
4725#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
4726#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
4727#define CAN_F13R1_FB1_Pos (1U)
4728#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
4729#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
4730#define CAN_F13R1_FB2_Pos (2U)
4731#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
4732#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
4733#define CAN_F13R1_FB3_Pos (3U)
4734#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
4735#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
4736#define CAN_F13R1_FB4_Pos (4U)
4737#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
4738#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
4739#define CAN_F13R1_FB5_Pos (5U)
4740#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
4741#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
4742#define CAN_F13R1_FB6_Pos (6U)
4743#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
4744#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
4745#define CAN_F13R1_FB7_Pos (7U)
4746#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
4747#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
4748#define CAN_F13R1_FB8_Pos (8U)
4749#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
4750#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
4751#define CAN_F13R1_FB9_Pos (9U)
4752#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
4753#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
4754#define CAN_F13R1_FB10_Pos (10U)
4755#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
4756#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
4757#define CAN_F13R1_FB11_Pos (11U)
4758#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
4759#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
4760#define CAN_F13R1_FB12_Pos (12U)
4761#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
4762#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
4763#define CAN_F13R1_FB13_Pos (13U)
4764#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
4765#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
4766#define CAN_F13R1_FB14_Pos (14U)
4767#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
4768#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
4769#define CAN_F13R1_FB15_Pos (15U)
4770#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
4771#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
4772#define CAN_F13R1_FB16_Pos (16U)
4773#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
4774#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
4775#define CAN_F13R1_FB17_Pos (17U)
4776#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
4777#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
4778#define CAN_F13R1_FB18_Pos (18U)
4779#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
4780#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
4781#define CAN_F13R1_FB19_Pos (19U)
4782#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
4783#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
4784#define CAN_F13R1_FB20_Pos (20U)
4785#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
4786#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
4787#define CAN_F13R1_FB21_Pos (21U)
4788#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
4789#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
4790#define CAN_F13R1_FB22_Pos (22U)
4791#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
4792#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
4793#define CAN_F13R1_FB23_Pos (23U)
4794#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
4795#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
4796#define CAN_F13R1_FB24_Pos (24U)
4797#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
4798#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
4799#define CAN_F13R1_FB25_Pos (25U)
4800#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
4801#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
4802#define CAN_F13R1_FB26_Pos (26U)
4803#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
4804#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
4805#define CAN_F13R1_FB27_Pos (27U)
4806#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
4807#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
4808#define CAN_F13R1_FB28_Pos (28U)
4809#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
4810#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
4811#define CAN_F13R1_FB29_Pos (29U)
4812#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
4813#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
4814#define CAN_F13R1_FB30_Pos (30U)
4815#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
4816#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
4817#define CAN_F13R1_FB31_Pos (31U)
4818#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
4819#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
4820
4821/******************* Bit definition for CAN_F0R2 register *******************/
4822#define CAN_F0R2_FB0_Pos (0U)
4823#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
4824#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
4825#define CAN_F0R2_FB1_Pos (1U)
4826#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
4827#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
4828#define CAN_F0R2_FB2_Pos (2U)
4829#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
4830#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
4831#define CAN_F0R2_FB3_Pos (3U)
4832#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
4833#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
4834#define CAN_F0R2_FB4_Pos (4U)
4835#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
4836#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
4837#define CAN_F0R2_FB5_Pos (5U)
4838#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
4839#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
4840#define CAN_F0R2_FB6_Pos (6U)
4841#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
4842#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
4843#define CAN_F0R2_FB7_Pos (7U)
4844#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
4845#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
4846#define CAN_F0R2_FB8_Pos (8U)
4847#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
4848#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
4849#define CAN_F0R2_FB9_Pos (9U)
4850#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
4851#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
4852#define CAN_F0R2_FB10_Pos (10U)
4853#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
4854#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
4855#define CAN_F0R2_FB11_Pos (11U)
4856#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
4857#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
4858#define CAN_F0R2_FB12_Pos (12U)
4859#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
4860#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
4861#define CAN_F0R2_FB13_Pos (13U)
4862#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
4863#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
4864#define CAN_F0R2_FB14_Pos (14U)
4865#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
4866#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
4867#define CAN_F0R2_FB15_Pos (15U)
4868#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
4869#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
4870#define CAN_F0R2_FB16_Pos (16U)
4871#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
4872#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
4873#define CAN_F0R2_FB17_Pos (17U)
4874#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
4875#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
4876#define CAN_F0R2_FB18_Pos (18U)
4877#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
4878#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
4879#define CAN_F0R2_FB19_Pos (19U)
4880#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
4881#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
4882#define CAN_F0R2_FB20_Pos (20U)
4883#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
4884#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
4885#define CAN_F0R2_FB21_Pos (21U)
4886#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
4887#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
4888#define CAN_F0R2_FB22_Pos (22U)
4889#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
4890#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
4891#define CAN_F0R2_FB23_Pos (23U)
4892#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
4893#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
4894#define CAN_F0R2_FB24_Pos (24U)
4895#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
4896#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
4897#define CAN_F0R2_FB25_Pos (25U)
4898#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
4899#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
4900#define CAN_F0R2_FB26_Pos (26U)
4901#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
4902#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
4903#define CAN_F0R2_FB27_Pos (27U)
4904#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
4905#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
4906#define CAN_F0R2_FB28_Pos (28U)
4907#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
4908#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
4909#define CAN_F0R2_FB29_Pos (29U)
4910#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
4911#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
4912#define CAN_F0R2_FB30_Pos (30U)
4913#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
4914#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
4915#define CAN_F0R2_FB31_Pos (31U)
4916#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
4917#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
4918
4919/******************* Bit definition for CAN_F1R2 register *******************/
4920#define CAN_F1R2_FB0_Pos (0U)
4921#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
4922#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
4923#define CAN_F1R2_FB1_Pos (1U)
4924#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
4925#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
4926#define CAN_F1R2_FB2_Pos (2U)
4927#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
4928#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
4929#define CAN_F1R2_FB3_Pos (3U)
4930#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
4931#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
4932#define CAN_F1R2_FB4_Pos (4U)
4933#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
4934#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
4935#define CAN_F1R2_FB5_Pos (5U)
4936#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
4937#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
4938#define CAN_F1R2_FB6_Pos (6U)
4939#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
4940#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
4941#define CAN_F1R2_FB7_Pos (7U)
4942#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
4943#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
4944#define CAN_F1R2_FB8_Pos (8U)
4945#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
4946#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
4947#define CAN_F1R2_FB9_Pos (9U)
4948#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
4949#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
4950#define CAN_F1R2_FB10_Pos (10U)
4951#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
4952#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
4953#define CAN_F1R2_FB11_Pos (11U)
4954#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
4955#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
4956#define CAN_F1R2_FB12_Pos (12U)
4957#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
4958#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
4959#define CAN_F1R2_FB13_Pos (13U)
4960#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
4961#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
4962#define CAN_F1R2_FB14_Pos (14U)
4963#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
4964#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
4965#define CAN_F1R2_FB15_Pos (15U)
4966#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
4967#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
4968#define CAN_F1R2_FB16_Pos (16U)
4969#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
4970#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
4971#define CAN_F1R2_FB17_Pos (17U)
4972#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
4973#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
4974#define CAN_F1R2_FB18_Pos (18U)
4975#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
4976#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
4977#define CAN_F1R2_FB19_Pos (19U)
4978#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
4979#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
4980#define CAN_F1R2_FB20_Pos (20U)
4981#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
4982#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
4983#define CAN_F1R2_FB21_Pos (21U)
4984#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
4985#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
4986#define CAN_F1R2_FB22_Pos (22U)
4987#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
4988#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
4989#define CAN_F1R2_FB23_Pos (23U)
4990#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
4991#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
4992#define CAN_F1R2_FB24_Pos (24U)
4993#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
4994#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
4995#define CAN_F1R2_FB25_Pos (25U)
4996#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
4997#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
4998#define CAN_F1R2_FB26_Pos (26U)
4999#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
5000#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
5001#define CAN_F1R2_FB27_Pos (27U)
5002#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
5003#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
5004#define CAN_F1R2_FB28_Pos (28U)
5005#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
5006#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
5007#define CAN_F1R2_FB29_Pos (29U)
5008#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
5009#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
5010#define CAN_F1R2_FB30_Pos (30U)
5011#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
5012#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
5013#define CAN_F1R2_FB31_Pos (31U)
5014#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
5015#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
5016
5017/******************* Bit definition for CAN_F2R2 register *******************/
5018#define CAN_F2R2_FB0_Pos (0U)
5019#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
5020#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
5021#define CAN_F2R2_FB1_Pos (1U)
5022#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
5023#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
5024#define CAN_F2R2_FB2_Pos (2U)
5025#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
5026#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
5027#define CAN_F2R2_FB3_Pos (3U)
5028#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
5029#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
5030#define CAN_F2R2_FB4_Pos (4U)
5031#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
5032#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
5033#define CAN_F2R2_FB5_Pos (5U)
5034#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
5035#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
5036#define CAN_F2R2_FB6_Pos (6U)
5037#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
5038#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
5039#define CAN_F2R2_FB7_Pos (7U)
5040#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
5041#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
5042#define CAN_F2R2_FB8_Pos (8U)
5043#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
5044#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
5045#define CAN_F2R2_FB9_Pos (9U)
5046#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
5047#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
5048#define CAN_F2R2_FB10_Pos (10U)
5049#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
5050#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
5051#define CAN_F2R2_FB11_Pos (11U)
5052#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
5053#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
5054#define CAN_F2R2_FB12_Pos (12U)
5055#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
5056#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
5057#define CAN_F2R2_FB13_Pos (13U)
5058#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
5059#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
5060#define CAN_F2R2_FB14_Pos (14U)
5061#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
5062#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
5063#define CAN_F2R2_FB15_Pos (15U)
5064#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
5065#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
5066#define CAN_F2R2_FB16_Pos (16U)
5067#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
5068#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
5069#define CAN_F2R2_FB17_Pos (17U)
5070#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
5071#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
5072#define CAN_F2R2_FB18_Pos (18U)
5073#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
5074#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
5075#define CAN_F2R2_FB19_Pos (19U)
5076#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
5077#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
5078#define CAN_F2R2_FB20_Pos (20U)
5079#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
5080#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
5081#define CAN_F2R2_FB21_Pos (21U)
5082#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
5083#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
5084#define CAN_F2R2_FB22_Pos (22U)
5085#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
5086#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
5087#define CAN_F2R2_FB23_Pos (23U)
5088#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
5089#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
5090#define CAN_F2R2_FB24_Pos (24U)
5091#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
5092#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
5093#define CAN_F2R2_FB25_Pos (25U)
5094#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
5095#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
5096#define CAN_F2R2_FB26_Pos (26U)
5097#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
5098#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
5099#define CAN_F2R2_FB27_Pos (27U)
5100#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
5101#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
5102#define CAN_F2R2_FB28_Pos (28U)
5103#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
5104#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
5105#define CAN_F2R2_FB29_Pos (29U)
5106#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
5107#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
5108#define CAN_F2R2_FB30_Pos (30U)
5109#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
5110#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
5111#define CAN_F2R2_FB31_Pos (31U)
5112#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
5113#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
5114
5115/******************* Bit definition for CAN_F3R2 register *******************/
5116#define CAN_F3R2_FB0_Pos (0U)
5117#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
5118#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
5119#define CAN_F3R2_FB1_Pos (1U)
5120#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
5121#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
5122#define CAN_F3R2_FB2_Pos (2U)
5123#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
5124#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
5125#define CAN_F3R2_FB3_Pos (3U)
5126#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
5127#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
5128#define CAN_F3R2_FB4_Pos (4U)
5129#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
5130#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
5131#define CAN_F3R2_FB5_Pos (5U)
5132#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
5133#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
5134#define CAN_F3R2_FB6_Pos (6U)
5135#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
5136#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
5137#define CAN_F3R2_FB7_Pos (7U)
5138#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
5139#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
5140#define CAN_F3R2_FB8_Pos (8U)
5141#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
5142#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
5143#define CAN_F3R2_FB9_Pos (9U)
5144#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
5145#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
5146#define CAN_F3R2_FB10_Pos (10U)
5147#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
5148#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
5149#define CAN_F3R2_FB11_Pos (11U)
5150#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
5151#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
5152#define CAN_F3R2_FB12_Pos (12U)
5153#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
5154#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
5155#define CAN_F3R2_FB13_Pos (13U)
5156#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
5157#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
5158#define CAN_F3R2_FB14_Pos (14U)
5159#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
5160#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
5161#define CAN_F3R2_FB15_Pos (15U)
5162#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
5163#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
5164#define CAN_F3R2_FB16_Pos (16U)
5165#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
5166#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
5167#define CAN_F3R2_FB17_Pos (17U)
5168#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
5169#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
5170#define CAN_F3R2_FB18_Pos (18U)
5171#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
5172#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
5173#define CAN_F3R2_FB19_Pos (19U)
5174#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
5175#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
5176#define CAN_F3R2_FB20_Pos (20U)
5177#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
5178#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
5179#define CAN_F3R2_FB21_Pos (21U)
5180#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
5181#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
5182#define CAN_F3R2_FB22_Pos (22U)
5183#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
5184#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
5185#define CAN_F3R2_FB23_Pos (23U)
5186#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
5187#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
5188#define CAN_F3R2_FB24_Pos (24U)
5189#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
5190#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
5191#define CAN_F3R2_FB25_Pos (25U)
5192#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
5193#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
5194#define CAN_F3R2_FB26_Pos (26U)
5195#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
5196#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
5197#define CAN_F3R2_FB27_Pos (27U)
5198#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
5199#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
5200#define CAN_F3R2_FB28_Pos (28U)
5201#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
5202#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
5203#define CAN_F3R2_FB29_Pos (29U)
5204#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
5205#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
5206#define CAN_F3R2_FB30_Pos (30U)
5207#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
5208#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
5209#define CAN_F3R2_FB31_Pos (31U)
5210#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
5211#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
5212
5213/******************* Bit definition for CAN_F4R2 register *******************/
5214#define CAN_F4R2_FB0_Pos (0U)
5215#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
5216#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
5217#define CAN_F4R2_FB1_Pos (1U)
5218#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
5219#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
5220#define CAN_F4R2_FB2_Pos (2U)
5221#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
5222#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
5223#define CAN_F4R2_FB3_Pos (3U)
5224#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
5225#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
5226#define CAN_F4R2_FB4_Pos (4U)
5227#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
5228#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
5229#define CAN_F4R2_FB5_Pos (5U)
5230#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
5231#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
5232#define CAN_F4R2_FB6_Pos (6U)
5233#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
5234#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
5235#define CAN_F4R2_FB7_Pos (7U)
5236#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
5237#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
5238#define CAN_F4R2_FB8_Pos (8U)
5239#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
5240#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
5241#define CAN_F4R2_FB9_Pos (9U)
5242#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
5243#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
5244#define CAN_F4R2_FB10_Pos (10U)
5245#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
5246#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
5247#define CAN_F4R2_FB11_Pos (11U)
5248#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
5249#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
5250#define CAN_F4R2_FB12_Pos (12U)
5251#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
5252#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
5253#define CAN_F4R2_FB13_Pos (13U)
5254#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
5255#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
5256#define CAN_F4R2_FB14_Pos (14U)
5257#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
5258#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
5259#define CAN_F4R2_FB15_Pos (15U)
5260#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
5261#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
5262#define CAN_F4R2_FB16_Pos (16U)
5263#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
5264#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
5265#define CAN_F4R2_FB17_Pos (17U)
5266#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
5267#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
5268#define CAN_F4R2_FB18_Pos (18U)
5269#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
5270#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
5271#define CAN_F4R2_FB19_Pos (19U)
5272#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
5273#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
5274#define CAN_F4R2_FB20_Pos (20U)
5275#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
5276#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
5277#define CAN_F4R2_FB21_Pos (21U)
5278#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
5279#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
5280#define CAN_F4R2_FB22_Pos (22U)
5281#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
5282#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
5283#define CAN_F4R2_FB23_Pos (23U)
5284#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
5285#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
5286#define CAN_F4R2_FB24_Pos (24U)
5287#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
5288#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
5289#define CAN_F4R2_FB25_Pos (25U)
5290#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
5291#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
5292#define CAN_F4R2_FB26_Pos (26U)
5293#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
5294#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
5295#define CAN_F4R2_FB27_Pos (27U)
5296#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
5297#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
5298#define CAN_F4R2_FB28_Pos (28U)
5299#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
5300#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
5301#define CAN_F4R2_FB29_Pos (29U)
5302#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
5303#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
5304#define CAN_F4R2_FB30_Pos (30U)
5305#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
5306#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
5307#define CAN_F4R2_FB31_Pos (31U)
5308#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
5309#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
5310
5311/******************* Bit definition for CAN_F5R2 register *******************/
5312#define CAN_F5R2_FB0_Pos (0U)
5313#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
5314#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
5315#define CAN_F5R2_FB1_Pos (1U)
5316#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
5317#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
5318#define CAN_F5R2_FB2_Pos (2U)
5319#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
5320#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
5321#define CAN_F5R2_FB3_Pos (3U)
5322#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
5323#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
5324#define CAN_F5R2_FB4_Pos (4U)
5325#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
5326#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
5327#define CAN_F5R2_FB5_Pos (5U)
5328#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
5329#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
5330#define CAN_F5R2_FB6_Pos (6U)
5331#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
5332#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
5333#define CAN_F5R2_FB7_Pos (7U)
5334#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
5335#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
5336#define CAN_F5R2_FB8_Pos (8U)
5337#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
5338#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
5339#define CAN_F5R2_FB9_Pos (9U)
5340#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
5341#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
5342#define CAN_F5R2_FB10_Pos (10U)
5343#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
5344#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
5345#define CAN_F5R2_FB11_Pos (11U)
5346#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
5347#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
5348#define CAN_F5R2_FB12_Pos (12U)
5349#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
5350#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
5351#define CAN_F5R2_FB13_Pos (13U)
5352#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
5353#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
5354#define CAN_F5R2_FB14_Pos (14U)
5355#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
5356#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
5357#define CAN_F5R2_FB15_Pos (15U)
5358#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
5359#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
5360#define CAN_F5R2_FB16_Pos (16U)
5361#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
5362#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
5363#define CAN_F5R2_FB17_Pos (17U)
5364#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
5365#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
5366#define CAN_F5R2_FB18_Pos (18U)
5367#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
5368#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
5369#define CAN_F5R2_FB19_Pos (19U)
5370#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
5371#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
5372#define CAN_F5R2_FB20_Pos (20U)
5373#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
5374#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
5375#define CAN_F5R2_FB21_Pos (21U)
5376#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
5377#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
5378#define CAN_F5R2_FB22_Pos (22U)
5379#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
5380#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
5381#define CAN_F5R2_FB23_Pos (23U)
5382#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
5383#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
5384#define CAN_F5R2_FB24_Pos (24U)
5385#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
5386#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
5387#define CAN_F5R2_FB25_Pos (25U)
5388#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
5389#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
5390#define CAN_F5R2_FB26_Pos (26U)
5391#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
5392#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
5393#define CAN_F5R2_FB27_Pos (27U)
5394#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
5395#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
5396#define CAN_F5R2_FB28_Pos (28U)
5397#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
5398#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
5399#define CAN_F5R2_FB29_Pos (29U)
5400#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
5401#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
5402#define CAN_F5R2_FB30_Pos (30U)
5403#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
5404#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
5405#define CAN_F5R2_FB31_Pos (31U)
5406#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
5407#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
5408
5409/******************* Bit definition for CAN_F6R2 register *******************/
5410#define CAN_F6R2_FB0_Pos (0U)
5411#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
5412#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
5413#define CAN_F6R2_FB1_Pos (1U)
5414#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
5415#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
5416#define CAN_F6R2_FB2_Pos (2U)
5417#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
5418#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
5419#define CAN_F6R2_FB3_Pos (3U)
5420#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
5421#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
5422#define CAN_F6R2_FB4_Pos (4U)
5423#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
5424#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
5425#define CAN_F6R2_FB5_Pos (5U)
5426#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
5427#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
5428#define CAN_F6R2_FB6_Pos (6U)
5429#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
5430#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
5431#define CAN_F6R2_FB7_Pos (7U)
5432#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
5433#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
5434#define CAN_F6R2_FB8_Pos (8U)
5435#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
5436#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
5437#define CAN_F6R2_FB9_Pos (9U)
5438#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
5439#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
5440#define CAN_F6R2_FB10_Pos (10U)
5441#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
5442#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
5443#define CAN_F6R2_FB11_Pos (11U)
5444#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
5445#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
5446#define CAN_F6R2_FB12_Pos (12U)
5447#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
5448#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
5449#define CAN_F6R2_FB13_Pos (13U)
5450#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
5451#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
5452#define CAN_F6R2_FB14_Pos (14U)
5453#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
5454#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
5455#define CAN_F6R2_FB15_Pos (15U)
5456#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
5457#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
5458#define CAN_F6R2_FB16_Pos (16U)
5459#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
5460#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
5461#define CAN_F6R2_FB17_Pos (17U)
5462#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
5463#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
5464#define CAN_F6R2_FB18_Pos (18U)
5465#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
5466#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
5467#define CAN_F6R2_FB19_Pos (19U)
5468#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
5469#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
5470#define CAN_F6R2_FB20_Pos (20U)
5471#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
5472#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
5473#define CAN_F6R2_FB21_Pos (21U)
5474#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
5475#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
5476#define CAN_F6R2_FB22_Pos (22U)
5477#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
5478#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
5479#define CAN_F6R2_FB23_Pos (23U)
5480#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
5481#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
5482#define CAN_F6R2_FB24_Pos (24U)
5483#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
5484#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
5485#define CAN_F6R2_FB25_Pos (25U)
5486#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
5487#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
5488#define CAN_F6R2_FB26_Pos (26U)
5489#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
5490#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
5491#define CAN_F6R2_FB27_Pos (27U)
5492#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
5493#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
5494#define CAN_F6R2_FB28_Pos (28U)
5495#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
5496#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
5497#define CAN_F6R2_FB29_Pos (29U)
5498#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
5499#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
5500#define CAN_F6R2_FB30_Pos (30U)
5501#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
5502#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
5503#define CAN_F6R2_FB31_Pos (31U)
5504#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
5505#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
5506
5507/******************* Bit definition for CAN_F7R2 register *******************/
5508#define CAN_F7R2_FB0_Pos (0U)
5509#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
5510#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
5511#define CAN_F7R2_FB1_Pos (1U)
5512#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
5513#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
5514#define CAN_F7R2_FB2_Pos (2U)
5515#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
5516#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
5517#define CAN_F7R2_FB3_Pos (3U)
5518#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
5519#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
5520#define CAN_F7R2_FB4_Pos (4U)
5521#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
5522#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
5523#define CAN_F7R2_FB5_Pos (5U)
5524#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
5525#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
5526#define CAN_F7R2_FB6_Pos (6U)
5527#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
5528#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
5529#define CAN_F7R2_FB7_Pos (7U)
5530#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
5531#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
5532#define CAN_F7R2_FB8_Pos (8U)
5533#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
5534#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
5535#define CAN_F7R2_FB9_Pos (9U)
5536#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
5537#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
5538#define CAN_F7R2_FB10_Pos (10U)
5539#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
5540#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
5541#define CAN_F7R2_FB11_Pos (11U)
5542#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
5543#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
5544#define CAN_F7R2_FB12_Pos (12U)
5545#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
5546#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
5547#define CAN_F7R2_FB13_Pos (13U)
5548#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
5549#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
5550#define CAN_F7R2_FB14_Pos (14U)
5551#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
5552#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
5553#define CAN_F7R2_FB15_Pos (15U)
5554#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
5555#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
5556#define CAN_F7R2_FB16_Pos (16U)
5557#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
5558#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
5559#define CAN_F7R2_FB17_Pos (17U)
5560#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
5561#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
5562#define CAN_F7R2_FB18_Pos (18U)
5563#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
5564#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
5565#define CAN_F7R2_FB19_Pos (19U)
5566#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
5567#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
5568#define CAN_F7R2_FB20_Pos (20U)
5569#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
5570#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
5571#define CAN_F7R2_FB21_Pos (21U)
5572#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
5573#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
5574#define CAN_F7R2_FB22_Pos (22U)
5575#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
5576#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
5577#define CAN_F7R2_FB23_Pos (23U)
5578#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
5579#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
5580#define CAN_F7R2_FB24_Pos (24U)
5581#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
5582#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
5583#define CAN_F7R2_FB25_Pos (25U)
5584#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
5585#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
5586#define CAN_F7R2_FB26_Pos (26U)
5587#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
5588#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
5589#define CAN_F7R2_FB27_Pos (27U)
5590#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
5591#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
5592#define CAN_F7R2_FB28_Pos (28U)
5593#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
5594#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
5595#define CAN_F7R2_FB29_Pos (29U)
5596#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
5597#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
5598#define CAN_F7R2_FB30_Pos (30U)
5599#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
5600#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
5601#define CAN_F7R2_FB31_Pos (31U)
5602#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
5603#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
5604
5605/******************* Bit definition for CAN_F8R2 register *******************/
5606#define CAN_F8R2_FB0_Pos (0U)
5607#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
5608#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
5609#define CAN_F8R2_FB1_Pos (1U)
5610#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
5611#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
5612#define CAN_F8R2_FB2_Pos (2U)
5613#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
5614#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
5615#define CAN_F8R2_FB3_Pos (3U)
5616#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
5617#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
5618#define CAN_F8R2_FB4_Pos (4U)
5619#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
5620#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
5621#define CAN_F8R2_FB5_Pos (5U)
5622#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
5623#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
5624#define CAN_F8R2_FB6_Pos (6U)
5625#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
5626#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
5627#define CAN_F8R2_FB7_Pos (7U)
5628#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
5629#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
5630#define CAN_F8R2_FB8_Pos (8U)
5631#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
5632#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
5633#define CAN_F8R2_FB9_Pos (9U)
5634#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
5635#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
5636#define CAN_F8R2_FB10_Pos (10U)
5637#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
5638#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
5639#define CAN_F8R2_FB11_Pos (11U)
5640#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
5641#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
5642#define CAN_F8R2_FB12_Pos (12U)
5643#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
5644#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
5645#define CAN_F8R2_FB13_Pos (13U)
5646#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
5647#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
5648#define CAN_F8R2_FB14_Pos (14U)
5649#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
5650#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
5651#define CAN_F8R2_FB15_Pos (15U)
5652#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
5653#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
5654#define CAN_F8R2_FB16_Pos (16U)
5655#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
5656#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
5657#define CAN_F8R2_FB17_Pos (17U)
5658#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
5659#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
5660#define CAN_F8R2_FB18_Pos (18U)
5661#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
5662#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
5663#define CAN_F8R2_FB19_Pos (19U)
5664#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
5665#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
5666#define CAN_F8R2_FB20_Pos (20U)
5667#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
5668#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
5669#define CAN_F8R2_FB21_Pos (21U)
5670#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
5671#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
5672#define CAN_F8R2_FB22_Pos (22U)
5673#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
5674#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
5675#define CAN_F8R2_FB23_Pos (23U)
5676#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
5677#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
5678#define CAN_F8R2_FB24_Pos (24U)
5679#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
5680#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
5681#define CAN_F8R2_FB25_Pos (25U)
5682#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
5683#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
5684#define CAN_F8R2_FB26_Pos (26U)
5685#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
5686#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
5687#define CAN_F8R2_FB27_Pos (27U)
5688#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
5689#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
5690#define CAN_F8R2_FB28_Pos (28U)
5691#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
5692#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
5693#define CAN_F8R2_FB29_Pos (29U)
5694#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
5695#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
5696#define CAN_F8R2_FB30_Pos (30U)
5697#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
5698#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
5699#define CAN_F8R2_FB31_Pos (31U)
5700#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
5701#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
5702
5703/******************* Bit definition for CAN_F9R2 register *******************/
5704#define CAN_F9R2_FB0_Pos (0U)
5705#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
5706#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
5707#define CAN_F9R2_FB1_Pos (1U)
5708#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
5709#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
5710#define CAN_F9R2_FB2_Pos (2U)
5711#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
5712#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
5713#define CAN_F9R2_FB3_Pos (3U)
5714#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
5715#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
5716#define CAN_F9R2_FB4_Pos (4U)
5717#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
5718#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
5719#define CAN_F9R2_FB5_Pos (5U)
5720#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
5721#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
5722#define CAN_F9R2_FB6_Pos (6U)
5723#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
5724#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
5725#define CAN_F9R2_FB7_Pos (7U)
5726#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
5727#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
5728#define CAN_F9R2_FB8_Pos (8U)
5729#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
5730#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
5731#define CAN_F9R2_FB9_Pos (9U)
5732#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
5733#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
5734#define CAN_F9R2_FB10_Pos (10U)
5735#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
5736#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
5737#define CAN_F9R2_FB11_Pos (11U)
5738#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
5739#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
5740#define CAN_F9R2_FB12_Pos (12U)
5741#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
5742#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
5743#define CAN_F9R2_FB13_Pos (13U)
5744#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
5745#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
5746#define CAN_F9R2_FB14_Pos (14U)
5747#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
5748#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
5749#define CAN_F9R2_FB15_Pos (15U)
5750#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
5751#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
5752#define CAN_F9R2_FB16_Pos (16U)
5753#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
5754#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
5755#define CAN_F9R2_FB17_Pos (17U)
5756#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
5757#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
5758#define CAN_F9R2_FB18_Pos (18U)
5759#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
5760#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
5761#define CAN_F9R2_FB19_Pos (19U)
5762#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
5763#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
5764#define CAN_F9R2_FB20_Pos (20U)
5765#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
5766#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
5767#define CAN_F9R2_FB21_Pos (21U)
5768#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
5769#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
5770#define CAN_F9R2_FB22_Pos (22U)
5771#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
5772#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
5773#define CAN_F9R2_FB23_Pos (23U)
5774#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
5775#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
5776#define CAN_F9R2_FB24_Pos (24U)
5777#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
5778#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
5779#define CAN_F9R2_FB25_Pos (25U)
5780#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
5781#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
5782#define CAN_F9R2_FB26_Pos (26U)
5783#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
5784#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
5785#define CAN_F9R2_FB27_Pos (27U)
5786#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
5787#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
5788#define CAN_F9R2_FB28_Pos (28U)
5789#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
5790#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
5791#define CAN_F9R2_FB29_Pos (29U)
5792#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
5793#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
5794#define CAN_F9R2_FB30_Pos (30U)
5795#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
5796#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
5797#define CAN_F9R2_FB31_Pos (31U)
5798#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
5799#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
5800
5801/******************* Bit definition for CAN_F10R2 register ******************/
5802#define CAN_F10R2_FB0_Pos (0U)
5803#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
5804#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
5805#define CAN_F10R2_FB1_Pos (1U)
5806#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
5807#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
5808#define CAN_F10R2_FB2_Pos (2U)
5809#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
5810#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
5811#define CAN_F10R2_FB3_Pos (3U)
5812#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
5813#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
5814#define CAN_F10R2_FB4_Pos (4U)
5815#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
5816#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
5817#define CAN_F10R2_FB5_Pos (5U)
5818#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
5819#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
5820#define CAN_F10R2_FB6_Pos (6U)
5821#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
5822#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
5823#define CAN_F10R2_FB7_Pos (7U)
5824#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
5825#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
5826#define CAN_F10R2_FB8_Pos (8U)
5827#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
5828#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
5829#define CAN_F10R2_FB9_Pos (9U)
5830#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
5831#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
5832#define CAN_F10R2_FB10_Pos (10U)
5833#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
5834#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
5835#define CAN_F10R2_FB11_Pos (11U)
5836#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
5837#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
5838#define CAN_F10R2_FB12_Pos (12U)
5839#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
5840#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
5841#define CAN_F10R2_FB13_Pos (13U)
5842#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
5843#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
5844#define CAN_F10R2_FB14_Pos (14U)
5845#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
5846#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
5847#define CAN_F10R2_FB15_Pos (15U)
5848#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
5849#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
5850#define CAN_F10R2_FB16_Pos (16U)
5851#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
5852#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
5853#define CAN_F10R2_FB17_Pos (17U)
5854#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
5855#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
5856#define CAN_F10R2_FB18_Pos (18U)
5857#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
5858#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
5859#define CAN_F10R2_FB19_Pos (19U)
5860#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
5861#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
5862#define CAN_F10R2_FB20_Pos (20U)
5863#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
5864#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
5865#define CAN_F10R2_FB21_Pos (21U)
5866#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
5867#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
5868#define CAN_F10R2_FB22_Pos (22U)
5869#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
5870#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
5871#define CAN_F10R2_FB23_Pos (23U)
5872#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
5873#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
5874#define CAN_F10R2_FB24_Pos (24U)
5875#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
5876#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
5877#define CAN_F10R2_FB25_Pos (25U)
5878#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
5879#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
5880#define CAN_F10R2_FB26_Pos (26U)
5881#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
5882#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
5883#define CAN_F10R2_FB27_Pos (27U)
5884#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
5885#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
5886#define CAN_F10R2_FB28_Pos (28U)
5887#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
5888#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
5889#define CAN_F10R2_FB29_Pos (29U)
5890#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
5891#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
5892#define CAN_F10R2_FB30_Pos (30U)
5893#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
5894#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
5895#define CAN_F10R2_FB31_Pos (31U)
5896#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
5897#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
5898
5899/******************* Bit definition for CAN_F11R2 register ******************/
5900#define CAN_F11R2_FB0_Pos (0U)
5901#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
5902#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
5903#define CAN_F11R2_FB1_Pos (1U)
5904#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
5905#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
5906#define CAN_F11R2_FB2_Pos (2U)
5907#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
5908#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
5909#define CAN_F11R2_FB3_Pos (3U)
5910#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
5911#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
5912#define CAN_F11R2_FB4_Pos (4U)
5913#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
5914#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
5915#define CAN_F11R2_FB5_Pos (5U)
5916#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
5917#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
5918#define CAN_F11R2_FB6_Pos (6U)
5919#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
5920#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
5921#define CAN_F11R2_FB7_Pos (7U)
5922#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
5923#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
5924#define CAN_F11R2_FB8_Pos (8U)
5925#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
5926#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
5927#define CAN_F11R2_FB9_Pos (9U)
5928#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
5929#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
5930#define CAN_F11R2_FB10_Pos (10U)
5931#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
5932#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
5933#define CAN_F11R2_FB11_Pos (11U)
5934#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
5935#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
5936#define CAN_F11R2_FB12_Pos (12U)
5937#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
5938#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
5939#define CAN_F11R2_FB13_Pos (13U)
5940#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
5941#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
5942#define CAN_F11R2_FB14_Pos (14U)
5943#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
5944#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
5945#define CAN_F11R2_FB15_Pos (15U)
5946#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
5947#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
5948#define CAN_F11R2_FB16_Pos (16U)
5949#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
5950#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
5951#define CAN_F11R2_FB17_Pos (17U)
5952#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
5953#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
5954#define CAN_F11R2_FB18_Pos (18U)
5955#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
5956#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
5957#define CAN_F11R2_FB19_Pos (19U)
5958#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
5959#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
5960#define CAN_F11R2_FB20_Pos (20U)
5961#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
5962#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
5963#define CAN_F11R2_FB21_Pos (21U)
5964#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
5965#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
5966#define CAN_F11R2_FB22_Pos (22U)
5967#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
5968#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
5969#define CAN_F11R2_FB23_Pos (23U)
5970#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
5971#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
5972#define CAN_F11R2_FB24_Pos (24U)
5973#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
5974#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
5975#define CAN_F11R2_FB25_Pos (25U)
5976#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
5977#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
5978#define CAN_F11R2_FB26_Pos (26U)
5979#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
5980#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
5981#define CAN_F11R2_FB27_Pos (27U)
5982#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
5983#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
5984#define CAN_F11R2_FB28_Pos (28U)
5985#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
5986#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
5987#define CAN_F11R2_FB29_Pos (29U)
5988#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
5989#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
5990#define CAN_F11R2_FB30_Pos (30U)
5991#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
5992#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
5993#define CAN_F11R2_FB31_Pos (31U)
5994#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
5995#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
5996
5997/******************* Bit definition for CAN_F12R2 register ******************/
5998#define CAN_F12R2_FB0_Pos (0U)
5999#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
6000#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
6001#define CAN_F12R2_FB1_Pos (1U)
6002#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
6003#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
6004#define CAN_F12R2_FB2_Pos (2U)
6005#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
6006#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
6007#define CAN_F12R2_FB3_Pos (3U)
6008#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
6009#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
6010#define CAN_F12R2_FB4_Pos (4U)
6011#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
6012#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
6013#define CAN_F12R2_FB5_Pos (5U)
6014#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
6015#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
6016#define CAN_F12R2_FB6_Pos (6U)
6017#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
6018#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
6019#define CAN_F12R2_FB7_Pos (7U)
6020#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
6021#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
6022#define CAN_F12R2_FB8_Pos (8U)
6023#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
6024#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
6025#define CAN_F12R2_FB9_Pos (9U)
6026#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
6027#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
6028#define CAN_F12R2_FB10_Pos (10U)
6029#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
6030#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
6031#define CAN_F12R2_FB11_Pos (11U)
6032#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
6033#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
6034#define CAN_F12R2_FB12_Pos (12U)
6035#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
6036#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
6037#define CAN_F12R2_FB13_Pos (13U)
6038#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
6039#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
6040#define CAN_F12R2_FB14_Pos (14U)
6041#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
6042#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
6043#define CAN_F12R2_FB15_Pos (15U)
6044#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
6045#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
6046#define CAN_F12R2_FB16_Pos (16U)
6047#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
6048#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
6049#define CAN_F12R2_FB17_Pos (17U)
6050#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
6051#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
6052#define CAN_F12R2_FB18_Pos (18U)
6053#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
6054#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
6055#define CAN_F12R2_FB19_Pos (19U)
6056#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
6057#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
6058#define CAN_F12R2_FB20_Pos (20U)
6059#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
6060#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
6061#define CAN_F12R2_FB21_Pos (21U)
6062#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
6063#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
6064#define CAN_F12R2_FB22_Pos (22U)
6065#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
6066#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
6067#define CAN_F12R2_FB23_Pos (23U)
6068#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
6069#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
6070#define CAN_F12R2_FB24_Pos (24U)
6071#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
6072#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
6073#define CAN_F12R2_FB25_Pos (25U)
6074#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
6075#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
6076#define CAN_F12R2_FB26_Pos (26U)
6077#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
6078#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
6079#define CAN_F12R2_FB27_Pos (27U)
6080#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
6081#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
6082#define CAN_F12R2_FB28_Pos (28U)
6083#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
6084#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
6085#define CAN_F12R2_FB29_Pos (29U)
6086#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
6087#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
6088#define CAN_F12R2_FB30_Pos (30U)
6089#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
6090#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
6091#define CAN_F12R2_FB31_Pos (31U)
6092#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
6093#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
6094
6095/******************* Bit definition for CAN_F13R2 register ******************/
6096#define CAN_F13R2_FB0_Pos (0U)
6097#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
6098#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
6099#define CAN_F13R2_FB1_Pos (1U)
6100#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
6101#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
6102#define CAN_F13R2_FB2_Pos (2U)
6103#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
6104#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
6105#define CAN_F13R2_FB3_Pos (3U)
6106#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
6107#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
6108#define CAN_F13R2_FB4_Pos (4U)
6109#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
6110#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
6111#define CAN_F13R2_FB5_Pos (5U)
6112#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
6113#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
6114#define CAN_F13R2_FB6_Pos (6U)
6115#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
6116#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
6117#define CAN_F13R2_FB7_Pos (7U)
6118#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
6119#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
6120#define CAN_F13R2_FB8_Pos (8U)
6121#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
6122#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
6123#define CAN_F13R2_FB9_Pos (9U)
6124#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
6125#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
6126#define CAN_F13R2_FB10_Pos (10U)
6127#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
6128#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
6129#define CAN_F13R2_FB11_Pos (11U)
6130#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
6131#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
6132#define CAN_F13R2_FB12_Pos (12U)
6133#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
6134#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
6135#define CAN_F13R2_FB13_Pos (13U)
6136#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
6137#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
6138#define CAN_F13R2_FB14_Pos (14U)
6139#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
6140#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
6141#define CAN_F13R2_FB15_Pos (15U)
6142#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
6143#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
6144#define CAN_F13R2_FB16_Pos (16U)
6145#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
6146#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
6147#define CAN_F13R2_FB17_Pos (17U)
6148#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
6149#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
6150#define CAN_F13R2_FB18_Pos (18U)
6151#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
6152#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
6153#define CAN_F13R2_FB19_Pos (19U)
6154#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
6155#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
6156#define CAN_F13R2_FB20_Pos (20U)
6157#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
6158#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
6159#define CAN_F13R2_FB21_Pos (21U)
6160#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
6161#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
6162#define CAN_F13R2_FB22_Pos (22U)
6163#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
6164#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
6165#define CAN_F13R2_FB23_Pos (23U)
6166#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
6167#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
6168#define CAN_F13R2_FB24_Pos (24U)
6169#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
6170#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
6171#define CAN_F13R2_FB25_Pos (25U)
6172#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
6173#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
6174#define CAN_F13R2_FB26_Pos (26U)
6175#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
6176#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
6177#define CAN_F13R2_FB27_Pos (27U)
6178#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
6179#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
6180#define CAN_F13R2_FB28_Pos (28U)
6181#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
6182#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
6183#define CAN_F13R2_FB29_Pos (29U)
6184#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
6185#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
6186#define CAN_F13R2_FB30_Pos (30U)
6187#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
6188#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
6189#define CAN_F13R2_FB31_Pos (31U)
6190#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
6191#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
6192
6193/******************************************************************************/
6194/* */
6195/* CRC calculation unit */
6196/* */
6197/******************************************************************************/
6198/******************* Bit definition for CRC_DR register *********************/
6199#define CRC_DR_DR_Pos (0U)
6200#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
6201#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
6202
6203/******************* Bit definition for CRC_IDR register ********************/
6204#define CRC_IDR_IDR_Pos (0U)
6205#define CRC_IDR_IDR_Msk (0xFFFFFFFFU << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
6206#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
6207
6208/******************** Bit definition for CRC_CR register ********************/
6209#define CRC_CR_RESET_Pos (0U)
6210#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
6211#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
6212#define CRC_CR_POLYSIZE_Pos (3U)
6213#define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
6214#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
6215#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
6216#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
6217#define CRC_CR_REV_IN_Pos (5U)
6218#define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
6219#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
6220#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
6221#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
6222#define CRC_CR_REV_OUT_Pos (7U)
6223#define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
6224#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
6225
6226/******************* Bit definition for CRC_INIT register *******************/
6227#define CRC_INIT_INIT_Pos (0U)
6228#define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
6229#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
6230
6231/******************* Bit definition for CRC_POL register ********************/
6232#define CRC_POL_POL_Pos (0U)
6233#define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
6234#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
6235
6236/******************************************************************************/
6237/* */
6238/* CRS Clock Recovery System */
6239/******************************************************************************/
6240
6241/******************* Bit definition for CRS_CR register *********************/
6242#define CRS_CR_SYNCOKIE_Pos (0U)
6243#define CRS_CR_SYNCOKIE_Msk (0x1U << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
6244#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
6245#define CRS_CR_SYNCWARNIE_Pos (1U)
6246#define CRS_CR_SYNCWARNIE_Msk (0x1U << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
6247#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
6248#define CRS_CR_ERRIE_Pos (2U)
6249#define CRS_CR_ERRIE_Msk (0x1U << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
6250#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
6251#define CRS_CR_ESYNCIE_Pos (3U)
6252#define CRS_CR_ESYNCIE_Msk (0x1U << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
6253#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
6254#define CRS_CR_CEN_Pos (5U)
6255#define CRS_CR_CEN_Msk (0x1U << CRS_CR_CEN_Pos) /*!< 0x00000020 */
6256#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
6257#define CRS_CR_AUTOTRIMEN_Pos (6U)
6258#define CRS_CR_AUTOTRIMEN_Msk (0x1U << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
6259#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
6260#define CRS_CR_SWSYNC_Pos (7U)
6261#define CRS_CR_SWSYNC_Msk (0x1U << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
6262#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
6263#define CRS_CR_TRIM_Pos (8U)
6264#define CRS_CR_TRIM_Msk (0x3FU << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
6265#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
6266
6267/******************* Bit definition for CRS_CFGR register *********************/
6268#define CRS_CFGR_RELOAD_Pos (0U)
6269#define CRS_CFGR_RELOAD_Msk (0xFFFFU << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
6270#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
6271#define CRS_CFGR_FELIM_Pos (16U)
6272#define CRS_CFGR_FELIM_Msk (0xFFU << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
6273#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
6274
6275#define CRS_CFGR_SYNCDIV_Pos (24U)
6276#define CRS_CFGR_SYNCDIV_Msk (0x7U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
6277#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
6278#define CRS_CFGR_SYNCDIV_0 (0x1U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
6279#define CRS_CFGR_SYNCDIV_1 (0x2U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
6280#define CRS_CFGR_SYNCDIV_2 (0x4U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
6281
6282#define CRS_CFGR_SYNCSRC_Pos (28U)
6283#define CRS_CFGR_SYNCSRC_Msk (0x3U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
6284#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
6285#define CRS_CFGR_SYNCSRC_0 (0x1U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
6286#define CRS_CFGR_SYNCSRC_1 (0x2U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
6287
6288#define CRS_CFGR_SYNCPOL_Pos (31U)
6289#define CRS_CFGR_SYNCPOL_Msk (0x1U << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
6290#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
6291
6292/******************* Bit definition for CRS_ISR register *********************/
6293#define CRS_ISR_SYNCOKF_Pos (0U)
6294#define CRS_ISR_SYNCOKF_Msk (0x1U << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
6295#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
6296#define CRS_ISR_SYNCWARNF_Pos (1U)
6297#define CRS_ISR_SYNCWARNF_Msk (0x1U << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
6298#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
6299#define CRS_ISR_ERRF_Pos (2U)
6300#define CRS_ISR_ERRF_Msk (0x1U << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
6301#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
6302#define CRS_ISR_ESYNCF_Pos (3U)
6303#define CRS_ISR_ESYNCF_Msk (0x1U << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
6304#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
6305#define CRS_ISR_SYNCERR_Pos (8U)
6306#define CRS_ISR_SYNCERR_Msk (0x1U << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
6307#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
6308#define CRS_ISR_SYNCMISS_Pos (9U)
6309#define CRS_ISR_SYNCMISS_Msk (0x1U << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
6310#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
6311#define CRS_ISR_TRIMOVF_Pos (10U)
6312#define CRS_ISR_TRIMOVF_Msk (0x1U << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
6313#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
6314#define CRS_ISR_FEDIR_Pos (15U)
6315#define CRS_ISR_FEDIR_Msk (0x1U << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
6316#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
6317#define CRS_ISR_FECAP_Pos (16U)
6318#define CRS_ISR_FECAP_Msk (0xFFFFU << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
6319#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
6320
6321/******************* Bit definition for CRS_ICR register *********************/
6322#define CRS_ICR_SYNCOKC_Pos (0U)
6323#define CRS_ICR_SYNCOKC_Msk (0x1U << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
6324#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
6325#define CRS_ICR_SYNCWARNC_Pos (1U)
6326#define CRS_ICR_SYNCWARNC_Msk (0x1U << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
6327#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
6328#define CRS_ICR_ERRC_Pos (2U)
6329#define CRS_ICR_ERRC_Msk (0x1U << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
6330#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
6331#define CRS_ICR_ESYNCC_Pos (3U)
6332#define CRS_ICR_ESYNCC_Msk (0x1U << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
6333#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
6334
6335/******************************************************************************/
6336/* */
6337/* Advanced Encryption Standard (AES) */
6338/* */
6339/******************************************************************************/
6340/******************* Bit definition for AES_CR register *********************/
6341#define AES_CR_EN_Pos (0U)
6342#define AES_CR_EN_Msk (0x1U << AES_CR_EN_Pos) /*!< 0x00000001 */
6343#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */
6344#define AES_CR_DATATYPE_Pos (1U)
6345#define AES_CR_DATATYPE_Msk (0x3U << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */
6346#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */
6347#define AES_CR_DATATYPE_0 (0x1U << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */
6348#define AES_CR_DATATYPE_1 (0x2U << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */
6349
6350#define AES_CR_MODE_Pos (3U)
6351#define AES_CR_MODE_Msk (0x3U << AES_CR_MODE_Pos) /*!< 0x00000018 */
6352#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */
6353#define AES_CR_MODE_0 (0x1U << AES_CR_MODE_Pos) /*!< 0x00000008 */
6354#define AES_CR_MODE_1 (0x2U << AES_CR_MODE_Pos) /*!< 0x00000010 */
6355
6356#define AES_CR_CHMOD_Pos (5U)
6357#define AES_CR_CHMOD_Msk (0x803U << AES_CR_CHMOD_Pos) /*!< 0x00010060 */
6358#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */
6359#define AES_CR_CHMOD_0 (0x001U << AES_CR_CHMOD_Pos) /*!< 0x00000020 */
6360#define AES_CR_CHMOD_1 (0x002U << AES_CR_CHMOD_Pos) /*!< 0x00000040 */
6361#define AES_CR_CHMOD_2 (0x800U << AES_CR_CHMOD_Pos) /*!< 0x00010000 */
6362
6363#define AES_CR_CCFC_Pos (7U)
6364#define AES_CR_CCFC_Msk (0x1U << AES_CR_CCFC_Pos) /*!< 0x00000080 */
6365#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */
6366#define AES_CR_ERRC_Pos (8U)
6367#define AES_CR_ERRC_Msk (0x1U << AES_CR_ERRC_Pos) /*!< 0x00000100 */
6368#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */
6369#define AES_CR_CCFIE_Pos (9U)
6370#define AES_CR_CCFIE_Msk (0x1U << AES_CR_CCFIE_Pos) /*!< 0x00000200 */
6371#define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */
6372#define AES_CR_ERRIE_Pos (10U)
6373#define AES_CR_ERRIE_Msk (0x1U << AES_CR_ERRIE_Pos) /*!< 0x00000400 */
6374#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */
6375#define AES_CR_DMAINEN_Pos (11U)
6376#define AES_CR_DMAINEN_Msk (0x1U << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */
6377#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */
6378#define AES_CR_DMAOUTEN_Pos (12U)
6379#define AES_CR_DMAOUTEN_Msk (0x1U << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */
6380#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */
6381
6382#define AES_CR_GCMPH_Pos (13U)
6383#define AES_CR_GCMPH_Msk (0x3U << AES_CR_GCMPH_Pos) /*!< 0x00006000 */
6384#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */
6385#define AES_CR_GCMPH_0 (0x1U << AES_CR_GCMPH_Pos) /*!< 0x00002000 */
6386#define AES_CR_GCMPH_1 (0x2U << AES_CR_GCMPH_Pos) /*!< 0x00004000 */
6387
6388#define AES_CR_KEYSIZE_Pos (18U)
6389#define AES_CR_KEYSIZE_Msk (0x1U << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */
6390#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */
6391#define AES_CR_NPBLB_Pos (20U)
6392#define AES_CR_NPBLB_Msk (0xFU << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */
6393#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */
6394#define AES_CR_NPBLB_0 (0x1U << AES_CR_NPBLB_Pos) /*!< 0x00100000 */
6395#define AES_CR_NPBLB_1 (0x2U << AES_CR_NPBLB_Pos) /*!< 0x00200000 */
6396#define AES_CR_NPBLB_2 (0x4U << AES_CR_NPBLB_Pos) /*!< 0x00400000 */
6397#define AES_CR_NPBLB_3 (0x8U << AES_CR_NPBLB_Pos) /*!< 0x00800000 */
6398
6399/******************* Bit definition for AES_SR register *********************/
6400#define AES_SR_CCF_Pos (0U)
6401#define AES_SR_CCF_Msk (0x1U << AES_SR_CCF_Pos) /*!< 0x00000001 */
6402#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */
6403#define AES_SR_RDERR_Pos (1U)
6404#define AES_SR_RDERR_Msk (0x1U << AES_SR_RDERR_Pos) /*!< 0x00000002 */
6405#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */
6406#define AES_SR_WRERR_Pos (2U)
6407#define AES_SR_WRERR_Msk (0x1U << AES_SR_WRERR_Pos) /*!< 0x00000004 */
6408#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */
6409#define AES_SR_BUSY_Pos (3U)
6410#define AES_SR_BUSY_Msk (0x1U << AES_SR_BUSY_Pos) /*!< 0x00000008 */
6411#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */
6412
6413/******************* Bit definition for AES_DINR register *******************/
6414#define AES_DINR_Pos (0U)
6415#define AES_DINR_Msk (0xFFFFFFFFU << AES_DINR_Pos) /*!< 0xFFFFFFFF */
6416#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */
6417
6418/******************* Bit definition for AES_DOUTR register ******************/
6419#define AES_DOUTR_Pos (0U)
6420#define AES_DOUTR_Msk (0xFFFFFFFFU << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */
6421#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */
6422
6423/******************* Bit definition for AES_KEYR0 register ******************/
6424#define AES_KEYR0_Pos (0U)
6425#define AES_KEYR0_Msk (0xFFFFFFFFU << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */
6426#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */
6427
6428/******************* Bit definition for AES_KEYR1 register ******************/
6429#define AES_KEYR1_Pos (0U)
6430#define AES_KEYR1_Msk (0xFFFFFFFFU << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */
6431#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */
6432
6433/******************* Bit definition for AES_KEYR2 register ******************/
6434#define AES_KEYR2_Pos (0U)
6435#define AES_KEYR2_Msk (0xFFFFFFFFU << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */
6436#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */
6437
6438/******************* Bit definition for AES_KEYR3 register ******************/
6439#define AES_KEYR3_Pos (0U)
6440#define AES_KEYR3_Msk (0xFFFFFFFFU << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */
6441#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */
6442
6443/******************* Bit definition for AES_KEYR4 register ******************/
6444#define AES_KEYR4_Pos (0U)
6445#define AES_KEYR4_Msk (0xFFFFFFFFU << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */
6446#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */
6447
6448/******************* Bit definition for AES_KEYR5 register ******************/
6449#define AES_KEYR5_Pos (0U)
6450#define AES_KEYR5_Msk (0xFFFFFFFFU << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */
6451#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */
6452
6453/******************* Bit definition for AES_KEYR6 register ******************/
6454#define AES_KEYR6_Pos (0U)
6455#define AES_KEYR6_Msk (0xFFFFFFFFU << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */
6456#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */
6457
6458/******************* Bit definition for AES_KEYR7 register ******************/
6459#define AES_KEYR7_Pos (0U)
6460#define AES_KEYR7_Msk (0xFFFFFFFFU << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */
6461#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */
6462
6463/******************* Bit definition for AES_IVR0 register ******************/
6464#define AES_IVR0_Pos (0U)
6465#define AES_IVR0_Msk (0xFFFFFFFFU << AES_IVR0_Pos) /*!< 0xFFFFFFFF */
6466#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */
6467
6468/******************* Bit definition for AES_IVR1 register ******************/
6469#define AES_IVR1_Pos (0U)
6470#define AES_IVR1_Msk (0xFFFFFFFFU << AES_IVR1_Pos) /*!< 0xFFFFFFFF */
6471#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */
6472
6473/******************* Bit definition for AES_IVR2 register ******************/
6474#define AES_IVR2_Pos (0U)
6475#define AES_IVR2_Msk (0xFFFFFFFFU << AES_IVR2_Pos) /*!< 0xFFFFFFFF */
6476#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */
6477
6478/******************* Bit definition for AES_IVR3 register ******************/
6479#define AES_IVR3_Pos (0U)
6480#define AES_IVR3_Msk (0xFFFFFFFFU << AES_IVR3_Pos) /*!< 0xFFFFFFFF */
6481#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */
6482
6483/******************* Bit definition for AES_SUSP0R register ******************/
6484#define AES_SUSP0R_Pos (0U)
6485#define AES_SUSP0R_Msk (0xFFFFFFFFU << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */
6486#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */
6487
6488/******************* Bit definition for AES_SUSP1R register ******************/
6489#define AES_SUSP1R_Pos (0U)
6490#define AES_SUSP1R_Msk (0xFFFFFFFFU << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */
6491#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */
6492
6493/******************* Bit definition for AES_SUSP2R register ******************/
6494#define AES_SUSP2R_Pos (0U)
6495#define AES_SUSP2R_Msk (0xFFFFFFFFU << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */
6496#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */
6497
6498/******************* Bit definition for AES_SUSP3R register ******************/
6499#define AES_SUSP3R_Pos (0U)
6500#define AES_SUSP3R_Msk (0xFFFFFFFFU << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */
6501#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */
6502
6503/******************* Bit definition for AES_SUSP4R register ******************/
6504#define AES_SUSP4R_Pos (0U)
6505#define AES_SUSP4R_Msk (0xFFFFFFFFU << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */
6506#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */
6507
6508/******************* Bit definition for AES_SUSP5R register ******************/
6509#define AES_SUSP5R_Pos (0U)
6510#define AES_SUSP5R_Msk (0xFFFFFFFFU << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */
6511#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */
6512
6513/******************* Bit definition for AES_SUSP6R register ******************/
6514#define AES_SUSP6R_Pos (0U)
6515#define AES_SUSP6R_Msk (0xFFFFFFFFU << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */
6516#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */
6517
6518/******************* Bit definition for AES_SUSP7R register ******************/
6519#define AES_SUSP7R_Pos (0U)
6520#define AES_SUSP7R_Msk (0xFFFFFFFFU << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */
6521#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */
6522
6523/******************************************************************************/
6524/* */
6525/* Digital to Analog Converter */
6526/* */
6527/******************************************************************************/
6528/*
6529 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
6530 */
6531#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
6532
6533/******************** Bit definition for DAC_CR register ********************/
6534#define DAC_CR_EN1_Pos (0U)
6535#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
6536#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
6537#define DAC_CR_TEN1_Pos (1U)
6538#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
6539#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
6540
6541#define DAC_CR_TSEL1_Pos (2U)
6542#define DAC_CR_TSEL1_Msk (0xFU << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
6543#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
6544#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
6545#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
6546#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
6547#define DAC_CR_TSEL1_3 (0x8U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
6548
6549#define DAC_CR_WAVE1_Pos (6U)
6550#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
6551#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
6552#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
6553#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
6554
6555#define DAC_CR_MAMP1_Pos (8U)
6556#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
6557#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
6558#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
6559#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
6560#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
6561#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
6562
6563#define DAC_CR_DMAEN1_Pos (12U)
6564#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
6565#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
6566#define DAC_CR_DMAUDRIE1_Pos (13U)
6567#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
6568#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
6569#define DAC_CR_CEN1_Pos (14U)
6570#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
6571#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
6572
6573#define DAC_CR_HFSEL_Pos (15U)
6574#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */
6575#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!<DAC channel 1 and 2 high frequency mode enable >*/
6576
6577#define DAC_CR_EN2_Pos (16U)
6578#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
6579#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
6580#define DAC_CR_TEN2_Pos (17U)
6581#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
6582#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
6583
6584#define DAC_CR_TSEL2_Pos (18U)
6585#define DAC_CR_TSEL2_Msk (0xFU << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
6586#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */
6587#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
6588#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
6589#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
6590#define DAC_CR_TSEL2_3 (0x8U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
6591
6592#define DAC_CR_WAVE2_Pos (22U)
6593#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
6594#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
6595#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
6596#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
6597
6598#define DAC_CR_MAMP2_Pos (24U)
6599#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
6600#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
6601#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
6602#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
6603#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
6604#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
6605
6606#define DAC_CR_DMAEN2_Pos (28U)
6607#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
6608#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
6609#define DAC_CR_DMAUDRIE2_Pos (29U)
6610#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
6611#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
6612#define DAC_CR_CEN2_Pos (30U)
6613#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
6614#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
6615
6616/***************** Bit definition for DAC_SWTRIGR register ******************/
6617#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
6618#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
6619#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
6620#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
6621#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
6622#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
6623
6624/***************** Bit definition for DAC_DHR12R1 register ******************/
6625#define DAC_DHR12R1_DACC1DHR_Pos (0U)
6626#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
6627#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
6628
6629/***************** Bit definition for DAC_DHR12L1 register ******************/
6630#define DAC_DHR12L1_DACC1DHR_Pos (4U)
6631#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
6632#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
6633
6634/****************** Bit definition for DAC_DHR8R1 register ******************/
6635#define DAC_DHR8R1_DACC1DHR_Pos (0U)
6636#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
6637#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
6638
6639/***************** Bit definition for DAC_DHR12R2 register ******************/
6640#define DAC_DHR12R2_DACC2DHR_Pos (0U)
6641#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
6642#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
6643
6644/***************** Bit definition for DAC_DHR12L2 register ******************/
6645#define DAC_DHR12L2_DACC2DHR_Pos (4U)
6646#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
6647#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
6648
6649/****************** Bit definition for DAC_DHR8R2 register ******************/
6650#define DAC_DHR8R2_DACC2DHR_Pos (0U)
6651#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
6652#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
6653
6654/***************** Bit definition for DAC_DHR12RD register ******************/
6655#define DAC_DHR12RD_DACC1DHR_Pos (0U)
6656#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
6657#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
6658#define DAC_DHR12RD_DACC2DHR_Pos (16U)
6659#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
6660#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
6661
6662/***************** Bit definition for DAC_DHR12LD register ******************/
6663#define DAC_DHR12LD_DACC1DHR_Pos (4U)
6664#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
6665#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
6666#define DAC_DHR12LD_DACC2DHR_Pos (20U)
6667#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
6668#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
6669
6670/****************** Bit definition for DAC_DHR8RD register ******************/
6671#define DAC_DHR8RD_DACC1DHR_Pos (0U)
6672#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
6673#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
6674#define DAC_DHR8RD_DACC2DHR_Pos (8U)
6675#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
6676#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
6677
6678/******************* Bit definition for DAC_DOR1 register *******************/
6679#define DAC_DOR1_DACC1DOR_Pos (0U)
6680#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
6681#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
6682
6683/******************* Bit definition for DAC_DOR2 register *******************/
6684#define DAC_DOR2_DACC2DOR_Pos (0U)
6685#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
6686#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
6687
6688/******************** Bit definition for DAC_SR register ********************/
6689#define DAC_SR_DMAUDR1_Pos (13U)
6690#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
6691#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
6692#define DAC_SR_CAL_FLAG1_Pos (14U)
6693#define DAC_SR_CAL_FLAG1_Msk (0x1U << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
6694#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
6695#define DAC_SR_BWST1_Pos (15U)
6696#define DAC_SR_BWST1_Msk (0x1U << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
6697#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
6698
6699#define DAC_SR_DMAUDR2_Pos (29U)
6700#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
6701#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
6702#define DAC_SR_CAL_FLAG2_Pos (30U)
6703#define DAC_SR_CAL_FLAG2_Msk (0x1U << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
6704#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
6705#define DAC_SR_BWST2_Pos (31U)
6706#define DAC_SR_BWST2_Msk (0x1U << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
6707#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
6708
6709/******************* Bit definition for DAC_CCR register ********************/
6710#define DAC_CCR_OTRIM1_Pos (0U)
6711#define DAC_CCR_OTRIM1_Msk (0x1FU << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
6712#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
6713#define DAC_CCR_OTRIM2_Pos (16U)
6714#define DAC_CCR_OTRIM2_Msk (0x1FU << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
6715#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
6716
6717/******************* Bit definition for DAC_MCR register *******************/
6718#define DAC_MCR_MODE1_Pos (0U)
6719#define DAC_MCR_MODE1_Msk (0x7U << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
6720#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
6721#define DAC_MCR_MODE1_0 (0x1U << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
6722#define DAC_MCR_MODE1_1 (0x2U << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
6723#define DAC_MCR_MODE1_2 (0x4U << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
6724
6725#define DAC_MCR_MODE2_Pos (16U)
6726#define DAC_MCR_MODE2_Msk (0x7U << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
6727#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
6728#define DAC_MCR_MODE2_0 (0x1U << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
6729#define DAC_MCR_MODE2_1 (0x2U << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
6730#define DAC_MCR_MODE2_2 (0x4U << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
6731
6732/****************** Bit definition for DAC_SHSR1 register ******************/
6733#define DAC_SHSR1_TSAMPLE1_Pos (0U)
6734#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
6735#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
6736
6737/****************** Bit definition for DAC_SHSR2 register ******************/
6738#define DAC_SHSR2_TSAMPLE2_Pos (0U)
6739#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFU << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
6740#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
6741
6742/****************** Bit definition for DAC_SHHR register ******************/
6743#define DAC_SHHR_THOLD1_Pos (0U)
6744#define DAC_SHHR_THOLD1_Msk (0x3FFU << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
6745#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
6746#define DAC_SHHR_THOLD2_Pos (16U)
6747#define DAC_SHHR_THOLD2_Msk (0x3FFU << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
6748#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
6749
6750/****************** Bit definition for DAC_SHRR register ******************/
6751#define DAC_SHRR_TREFRESH1_Pos (0U)
6752#define DAC_SHRR_TREFRESH1_Msk (0xFFU << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
6753#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
6754#define DAC_SHRR_TREFRESH2_Pos (16U)
6755#define DAC_SHRR_TREFRESH2_Msk (0xFFU << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
6756#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
6757
6758/******************************************************************************/
6759/* */
6760/* DCMI */
6761/* */
6762/******************************************************************************/
6763/******************** Bits definition for DCMI_CR register ******************/
6764#define DCMI_CR_CAPTURE_Pos (0U)
6765#define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
6766#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk /*!< DCMI Capture enable */
6767#define DCMI_CR_CM_Pos (1U)
6768#define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
6769#define DCMI_CR_CM DCMI_CR_CM_Msk /*!< DCMI Capture mode */
6770#define DCMI_CR_CROP_Pos (2U)
6771#define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
6772#define DCMI_CR_CROP DCMI_CR_CROP_Msk /*!< DCMI Crop feature */
6773#define DCMI_CR_JPEG_Pos (3U)
6774#define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
6775#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk /*!< DCMI JPEG format */
6776#define DCMI_CR_ESS_Pos (4U)
6777#define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
6778#define DCMI_CR_ESS DCMI_CR_ESS_Msk /*!< DCMI Embedded synchronization select */
6779#define DCMI_CR_PCKPOL_Pos (5U)
6780#define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
6781#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk /*!< DCMI Pixel clock polarity */
6782#define DCMI_CR_HSPOL_Pos (6U)
6783#define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
6784#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk /*!< DCMI Horizontal synchronization polarity */
6785#define DCMI_CR_VSPOL_Pos (7U)
6786#define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
6787#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk /*!< DCMI Vertical synchronization polarity */
6788#define DCMI_CR_FCRC_Pos (8U)
6789#define DCMI_CR_FCRC_Msk (0x3U << DCMI_CR_FCRC_Pos) /*!< 0x00000300 */
6790#define DCMI_CR_FCRC DCMI_CR_FCRC_Msk /*!< DCMI Frame capture rate control FCRC[1:0] */
6791#define DCMI_CR_FCRC_0 (0x1U << DCMI_CR_FCRC_Pos) /*!< 0x00000100 */
6792#define DCMI_CR_FCRC_1 (0x2U << DCMI_CR_FCRC_Pos) /*!< 0x00000200 */
6793#define DCMI_CR_EDM_Pos (10U)
6794#define DCMI_CR_EDM_Msk (0x3U << DCMI_CR_EDM_Pos) /*!< 0x00000C00 */
6795#define DCMI_CR_EDM DCMI_CR_EDM_Msk /*!< DCMI Extended data mode EDM[1:0] */
6796#define DCMI_CR_EDM_0 (0x1U << DCMI_CR_EDM_Pos) /*!< 0x00000400 */
6797#define DCMI_CR_EDM_1 (0x2U << DCMI_CR_EDM_Pos) /*!< 0x00000800 */
6798#define DCMI_CR_ENABLE_Pos (14U)
6799#define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
6800#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk /*!< DCMI DCMI enable */
6801#define DCMI_CR_BSM_Pos (16U)
6802#define DCMI_CR_BSM_Msk (0x3U << DCMI_CR_BSM_Pos) /*!< 0x00030000 */
6803#define DCMI_CR_BSM DCMI_CR_BSM_Msk /*!< DCMI Byte Select mode BSM[1:0] */
6804#define DCMI_CR_BSM_0 (0x1U << DCMI_CR_BSM_Pos) /*!< 0x00010000 */
6805#define DCMI_CR_BSM_1 (0x2U << DCMI_CR_BSM_Pos) /*!< 0x00020000 */
6806#define DCMI_CR_OEBS_Pos (18U)
6807#define DCMI_CR_OEBS_Msk (0x1U << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
6808#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk /*!< DCMI Odd/Even Byte Select (Byte Select Start) */
6809#define DCMI_CR_LSM_Pos (19U)
6810#define DCMI_CR_LSM_Msk (0x1U << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
6811#define DCMI_CR_LSM DCMI_CR_LSM_Msk /*!< DCMI Line Select mode */
6812#define DCMI_CR_OELS_Pos (20U)
6813#define DCMI_CR_OELS_Msk (0x1U << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
6814#define DCMI_CR_OELS DCMI_CR_OELS_Msk /*!< DCMI Odd/Even Line Select (Line Select Start) */
6815
6816/******************** Bits definition for DCMI_SR register ******************/
6817#define DCMI_SR_HSYNC_Pos (0U)
6818#define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
6819#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
6820#define DCMI_SR_VSYNC_Pos (1U)
6821#define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
6822#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
6823#define DCMI_SR_FNE_Pos (2U)
6824#define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
6825#define DCMI_SR_FNE DCMI_SR_FNE_Msk /*!< DCMI FIFO not empty */
6826
6827/******************** Bits definition for DCMI_RISR register ****************/
6828#define DCMI_RIS_FRAME_RIS_Pos (0U)
6829#define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
6830#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk /*!< DCMI Capture complete raw interrupt status */
6831#define DCMI_RIS_OVR_RIS_Pos (1U)
6832#define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
6833#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk /*!< DCMI Overrun raw interrupt status */
6834#define DCMI_RIS_ERR_RIS_Pos (2U)
6835#define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
6836#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk /*!< DCMI Synchronization error raw interrupt status */
6837#define DCMI_RIS_VSYNC_RIS_Pos (3U)
6838#define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
6839#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk /*!< DCMI VSYNC raw interrupt status */
6840#define DCMI_RIS_LINE_RIS_Pos (4U)
6841#define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
6842#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk /*!< DCMI Line raw interrupt status */
6843
6844/******************** Bits definition for DCMI_IER register *****************/
6845#define DCMI_IER_FRAME_IE_Pos (0U)
6846#define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
6847#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk /*!< DCMI Capture complete interrupt enable */
6848#define DCMI_IER_OVR_IE_Pos (1U)
6849#define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
6850#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk /*!< DCMI Overrun interrupt enable */
6851#define DCMI_IER_ERR_IE_Pos (2U)
6852#define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
6853#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk /*!< DCMI Synchronization error interrupt enable */
6854#define DCMI_IER_VSYNC_IE_Pos (3U)
6855#define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
6856#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk /*!< DCMI VSYNC interrupt enable */
6857#define DCMI_IER_LINE_IE_Pos (4U)
6858#define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
6859#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk /*!< DCMI Line interrupt enable */
6860#define DCMI_IER_INT_IE_Pos (0U)
6861#define DCMI_IER_INT_IE_Msk (0x1FU << DCMI_IER_INT_IE_Pos) /*!< 0x0000001F */
6862#define DCMI_IER_INT_IE DCMI_IER_INT_IE_Msk
6863
6864/******************** Bits definition for DCMI_MIS register *****************/
6865#define DCMI_MIS_FRAME_MIS_Pos (0U)
6866#define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
6867#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk /*!< DCMI Capture complete masked interrupt status */
6868#define DCMI_MIS_OVR_MIS_Pos (1U)
6869#define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
6870#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk /*!< DCMI Overrun masked interrupt status */
6871#define DCMI_MIS_ERR_MIS_Pos (2U)
6872#define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
6873#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk /*!< DCMI Synchronization error masked interrupt status */
6874#define DCMI_MIS_VSYNC_MIS_Pos (3U)
6875#define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
6876#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk /*!< DCMI VSYNC masked interrupt status */
6877#define DCMI_MIS_LINE_MIS_Pos (4U)
6878#define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
6879#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk /*!< DCMI Line masked interrupt status */
6880
6881/******************** Bits definition for DCMI_ICR register *****************/
6882#define DCMI_ICR_FRAME_ISC_Pos (0U)
6883#define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
6884#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk /*!< DCMI Capture complete interrupt status clear */
6885#define DCMI_ICR_OVR_ISC_Pos (1U)
6886#define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
6887#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk /*!< DCMI Overrun interrupt status clear */
6888#define DCMI_ICR_ERR_ISC_Pos (2U)
6889#define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
6890#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk /*!< DCMI Synchronization error interrupt status clear */
6891#define DCMI_ICR_VSYNC_ISC_Pos (3U)
6892#define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
6893#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk /*!< DCMI Vertical synch interrupt status clear */
6894#define DCMI_ICR_LINE_ISC_Pos (4U)
6895#define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
6896#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk /*!< DCMI line interrupt status clear */
6897
6898/******************** Bits definition for DCMI_ESCR register ****************/
6899#define DCMI_ESCR_FSC_Pos (0U)
6900#define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
6901#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk /*!< DCMI Frame start delimiter code FSC[7:0] */
6902#define DCMI_ESCR_FSC_0 (0x01U << DCMI_ESCR_FSC_Pos) /*!< 0x00000001 */
6903#define DCMI_ESCR_FSC_1 (0x02U << DCMI_ESCR_FSC_Pos) /*!< 0x00000002 */
6904#define DCMI_ESCR_FSC_2 (0x04U << DCMI_ESCR_FSC_Pos) /*!< 0x00000004 */
6905#define DCMI_ESCR_FSC_3 (0x08U << DCMI_ESCR_FSC_Pos) /*!< 0x00000008 */
6906#define DCMI_ESCR_FSC_4 (0x10U << DCMI_ESCR_FSC_Pos) /*!< 0x00000010 */
6907#define DCMI_ESCR_FSC_5 (0x20U << DCMI_ESCR_FSC_Pos) /*!< 0x00000020 */
6908#define DCMI_ESCR_FSC_6 (0x40U << DCMI_ESCR_FSC_Pos) /*!< 0x00000040 */
6909#define DCMI_ESCR_FSC_7 (0x80U << DCMI_ESCR_FSC_Pos) /*!< 0x00000080 */
6910#define DCMI_ESCR_LSC_Pos (8U)
6911#define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
6912#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk /*!< DCMI Line start delimiter code LSC[7:0] */
6913#define DCMI_ESCR_LSC_0 (0x01U << DCMI_ESCR_LSC_Pos) /*!< 0x00000100 */
6914#define DCMI_ESCR_LSC_1 (0x02U << DCMI_ESCR_LSC_Pos) /*!< 0x00000200 */
6915#define DCMI_ESCR_LSC_2 (0x04U << DCMI_ESCR_LSC_Pos) /*!< 0x00000400 */
6916#define DCMI_ESCR_LSC_3 (0x08U << DCMI_ESCR_LSC_Pos) /*!< 0x00000800 */
6917#define DCMI_ESCR_LSC_4 (0x10U << DCMI_ESCR_LSC_Pos) /*!< 0x00001000 */
6918#define DCMI_ESCR_LSC_5 (0x20U << DCMI_ESCR_LSC_Pos) /*!< 0x00002000 */
6919#define DCMI_ESCR_LSC_6 (0x40U << DCMI_ESCR_LSC_Pos) /*!< 0x00004000 */
6920#define DCMI_ESCR_LSC_7 (0x80U << DCMI_ESCR_LSC_Pos) /*!< 0x00008000 */
6921#define DCMI_ESCR_LEC_Pos (16U)
6922#define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
6923#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk /*!< DCMI Line end delimiter code LEC[7:0] */
6924#define DCMI_ESCR_LEC_0 (0x01U << DCMI_ESCR_LEC_Pos) /*!< 0x00010000 */
6925#define DCMI_ESCR_LEC_1 (0x02U << DCMI_ESCR_LEC_Pos) /*!< 0x00020000 */
6926#define DCMI_ESCR_LEC_2 (0x04U << DCMI_ESCR_LEC_Pos) /*!< 0x00040000 */
6927#define DCMI_ESCR_LEC_3 (0x08U << DCMI_ESCR_LEC_Pos) /*!< 0x00080000 */
6928#define DCMI_ESCR_LEC_4 (0x10U << DCMI_ESCR_LEC_Pos) /*!< 0x00100000 */
6929#define DCMI_ESCR_LEC_5 (0x20U << DCMI_ESCR_LEC_Pos) /*!< 0x00200000 */
6930#define DCMI_ESCR_LEC_6 (0x40U << DCMI_ESCR_LEC_Pos) /*!< 0x00400000 */
6931#define DCMI_ESCR_LEC_7 (0x80U << DCMI_ESCR_LEC_Pos) /*!< 0x00800000 */
6932#define DCMI_ESCR_FEC_Pos (24U)
6933#define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
6934#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk /*!< DCMI Frame end delimiter code FEC[7:0] */
6935#define DCMI_ESCR_FEC_0 (0x01U << DCMI_ESCR_FEC_Pos) /*!< 0x01000000 */
6936#define DCMI_ESCR_FEC_1 (0x02U << DCMI_ESCR_FEC_Pos) /*!< 0x02000000 */
6937#define DCMI_ESCR_FEC_2 (0x04U << DCMI_ESCR_FEC_Pos) /*!< 0x04000000 */
6938#define DCMI_ESCR_FEC_3 (0x08U << DCMI_ESCR_FEC_Pos) /*!< 0x08000000 */
6939#define DCMI_ESCR_FEC_4 (0x10U << DCMI_ESCR_FEC_Pos) /*!< 0x10000000 */
6940#define DCMI_ESCR_FEC_5 (0x20U << DCMI_ESCR_FEC_Pos) /*!< 0x20000000 */
6941#define DCMI_ESCR_FEC_6 (0x40U << DCMI_ESCR_FEC_Pos) /*!< 0x40000000 */
6942#define DCMI_ESCR_FEC_7 (0x80U << DCMI_ESCR_FEC_Pos) /*!< 0x80000000 */
6943
6944/******************** Bits definition for DCMI_ESUR register ****************/
6945#define DCMI_ESUR_FSU_Pos (0U)
6946#define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
6947#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk /*!< DCMI Frame start delimiter unmask FSU[7:0] */
6948#define DCMI_ESUR_FSU_0 (0x01U << DCMI_ESUR_FSU_Pos) /*!< 0x00000001 */
6949#define DCMI_ESUR_FSU_1 (0x02U << DCMI_ESUR_FSU_Pos) /*!< 0x00000002 */
6950#define DCMI_ESUR_FSU_2 (0x04U << DCMI_ESUR_FSU_Pos) /*!< 0x00000004 */
6951#define DCMI_ESUR_FSU_3 (0x08U << DCMI_ESUR_FSU_Pos) /*!< 0x00000008 */
6952#define DCMI_ESUR_FSU_4 (0x10U << DCMI_ESUR_FSU_Pos) /*!< 0x00000010 */
6953#define DCMI_ESUR_FSU_5 (0x20U << DCMI_ESUR_FSU_Pos) /*!< 0x00000020 */
6954#define DCMI_ESUR_FSU_6 (0x40U << DCMI_ESUR_FSU_Pos) /*!< 0x00000040 */
6955#define DCMI_ESUR_FSU_7 (0x80U << DCMI_ESUR_FSU_Pos) /*!< 0x00000080 */
6956#define DCMI_ESUR_LSU_Pos (8U)
6957#define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
6958#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk /*!< DCMI Line start delimiter unmask LSU[7:0] */
6959#define DCMI_ESUR_LSU_0 (0x01U << DCMI_ESUR_LSU_Pos) /*!< 0x00000100 */
6960#define DCMI_ESUR_LSU_1 (0x02U << DCMI_ESUR_LSU_Pos) /*!< 0x00000200 */
6961#define DCMI_ESUR_LSU_2 (0x04U << DCMI_ESUR_LSU_Pos) /*!< 0x00000400 */
6962#define DCMI_ESUR_LSU_3 (0x08U << DCMI_ESUR_LSU_Pos) /*!< 0x00000800 */
6963#define DCMI_ESUR_LSU_4 (0x10U << DCMI_ESUR_LSU_Pos) /*!< 0x00001000 */
6964#define DCMI_ESUR_LSU_5 (0x20U << DCMI_ESUR_LSU_Pos) /*!< 0x00002000 */
6965#define DCMI_ESUR_LSU_6 (0x40U << DCMI_ESUR_LSU_Pos) /*!< 0x00004000 */
6966#define DCMI_ESUR_LSU_7 (0x80U << DCMI_ESUR_LSU_Pos) /*!< 0x00008000 */
6967#define DCMI_ESUR_LEU_Pos (16U)
6968#define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
6969#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk /*!< DCMI Line end delimiter unmask LEU[7:0] */
6970#define DCMI_ESUR_LEU_0 (0x01U << DCMI_ESUR_LEU_Pos) /*!< 0x00010000 */
6971#define DCMI_ESUR_LEU_1 (0x02U << DCMI_ESUR_LEU_Pos) /*!< 0x00020000 */
6972#define DCMI_ESUR_LEU_2 (0x04U << DCMI_ESUR_LEU_Pos) /*!< 0x00040000 */
6973#define DCMI_ESUR_LEU_3 (0x08U << DCMI_ESUR_LEU_Pos) /*!< 0x00080000 */
6974#define DCMI_ESUR_LEU_4 (0x10U << DCMI_ESUR_LEU_Pos) /*!< 0x00100000 */
6975#define DCMI_ESUR_LEU_5 (0x20U << DCMI_ESUR_LEU_Pos) /*!< 0x00200000 */
6976#define DCMI_ESUR_LEU_6 (0x40U << DCMI_ESUR_LEU_Pos) /*!< 0x00400000 */
6977#define DCMI_ESUR_LEU_7 (0x80U << DCMI_ESUR_LEU_Pos) /*!< 0x00800000 */
6978#define DCMI_ESUR_FEU_Pos (24U)
6979#define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
6980#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk /*!< DCMI Frame end delimiter unmask FEU[7:0] */
6981#define DCMI_ESUR_FEU_0 (0x01U << DCMI_ESUR_FEU_Pos) /*!< 0x01000000 */
6982#define DCMI_ESUR_FEU_1 (0x02U << DCMI_ESUR_FEU_Pos) /*!< 0x02000000 */
6983#define DCMI_ESUR_FEU_2 (0x04U << DCMI_ESUR_FEU_Pos) /*!< 0x04000000 */
6984#define DCMI_ESUR_FEU_3 (0x08U << DCMI_ESUR_FEU_Pos) /*!< 0x08000000 */
6985#define DCMI_ESUR_FEU_4 (0x10U << DCMI_ESUR_FEU_Pos) /*!< 0x10000000 */
6986#define DCMI_ESUR_FEU_5 (0x20U << DCMI_ESUR_FEU_Pos) /*!< 0x20000000 */
6987#define DCMI_ESUR_FEU_6 (0x40U << DCMI_ESUR_FEU_Pos) /*!< 0x40000000 */
6988#define DCMI_ESUR_FEU_7 (0x80U << DCMI_ESUR_FEU_Pos) /*!< 0x80000000 */
6989
6990/******************** Bits definition for DCMI_CWSTRT register **************/
6991#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
6992#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
6993#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk /*!< DCMI Horizontal offset count HOFFCNT[13:0] */
6994#define DCMI_CWSTRT_HOFFCNT_0 (0x0001U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000001 */
6995#define DCMI_CWSTRT_HOFFCNT_1 (0x0002U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000002 */
6996#define DCMI_CWSTRT_HOFFCNT_2 (0x0004U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000004 */
6997#define DCMI_CWSTRT_HOFFCNT_3 (0x0008U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000008 */
6998#define DCMI_CWSTRT_HOFFCNT_4 (0x0010U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000010 */
6999#define DCMI_CWSTRT_HOFFCNT_5 (0x0020U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000020 */
7000#define DCMI_CWSTRT_HOFFCNT_6 (0x0040U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000040 */
7001#define DCMI_CWSTRT_HOFFCNT_7 (0x0080U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000080 */
7002#define DCMI_CWSTRT_HOFFCNT_8 (0x0100U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000100 */
7003#define DCMI_CWSTRT_HOFFCNT_9 (0x0200U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000200 */
7004#define DCMI_CWSTRT_HOFFCNT_10 (0x0400U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000400 */
7005#define DCMI_CWSTRT_HOFFCNT_11 (0x0800U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000800 */
7006#define DCMI_CWSTRT_HOFFCNT_12 (0x1000U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00001000 */
7007#define DCMI_CWSTRT_HOFFCNT_13 (0x2000U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00002000 */
7008#define DCMI_CWSTRT_VST_Pos (16U)
7009#define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
7010#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk /*!< DCMI Vertical start line count VST[12:0] */
7011#define DCMI_CWSTRT_VST_0 (0x0001U << DCMI_CWSTRT_VST_Pos) /*!< 0x00010000 */
7012#define DCMI_CWSTRT_VST_1 (0x0002U << DCMI_CWSTRT_VST_Pos) /*!< 0x00020000 */
7013#define DCMI_CWSTRT_VST_2 (0x0004U << DCMI_CWSTRT_VST_Pos) /*!< 0x00040000 */
7014#define DCMI_CWSTRT_VST_3 (0x0008U << DCMI_CWSTRT_VST_Pos) /*!< 0x00080000 */
7015#define DCMI_CWSTRT_VST_4 (0x0010U << DCMI_CWSTRT_VST_Pos) /*!< 0x00100000 */
7016#define DCMI_CWSTRT_VST_5 (0x0020U << DCMI_CWSTRT_VST_Pos) /*!< 0x00200000 */
7017#define DCMI_CWSTRT_VST_6 (0x0040U << DCMI_CWSTRT_VST_Pos) /*!< 0x00400000 */
7018#define DCMI_CWSTRT_VST_7 (0x0080U << DCMI_CWSTRT_VST_Pos) /*!< 0x00800000 */
7019#define DCMI_CWSTRT_VST_8 (0x0100U << DCMI_CWSTRT_VST_Pos) /*!< 0x01000000 */
7020#define DCMI_CWSTRT_VST_9 (0x0200U << DCMI_CWSTRT_VST_Pos) /*!< 0x02000000 */
7021#define DCMI_CWSTRT_VST_10 (0x0400U << DCMI_CWSTRT_VST_Pos) /*!< 0x04000000 */
7022#define DCMI_CWSTRT_VST_11 (0x0800U << DCMI_CWSTRT_VST_Pos) /*!< 0x08000000 */
7023#define DCMI_CWSTRT_VST_12 (0x1000U << DCMI_CWSTRT_VST_Pos) /*!< 0x10000000 */
7024
7025/******************** Bits definition for DCMI_CWSIZE register **************/
7026#define DCMI_CWSIZE_CAPCNT_Pos (0U)
7027#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
7028#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk /*!< DCMI Capture count CAPCNT[13:0] */
7029#define DCMI_CWSIZE_CAPCNT_0 (0x0001U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000001 */
7030#define DCMI_CWSIZE_CAPCNT_1 (0x0002U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000002 */
7031#define DCMI_CWSIZE_CAPCNT_2 (0x0004U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000004 */
7032#define DCMI_CWSIZE_CAPCNT_3 (0x0008U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000008 */
7033#define DCMI_CWSIZE_CAPCNT_4 (0x0010U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000010 */
7034#define DCMI_CWSIZE_CAPCNT_5 (0x0020U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000020 */
7035#define DCMI_CWSIZE_CAPCNT_6 (0x0040U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000040 */
7036#define DCMI_CWSIZE_CAPCNT_7 (0x0080U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000080 */
7037#define DCMI_CWSIZE_CAPCNT_8 (0x0100U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000100 */
7038#define DCMI_CWSIZE_CAPCNT_9 (0x0200U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000200 */
7039#define DCMI_CWSIZE_CAPCNT_10 (0x0400U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000400 */
7040#define DCMI_CWSIZE_CAPCNT_11 (0x0800U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000800 */
7041#define DCMI_CWSIZE_CAPCNT_12 (0x1000U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00001000 */
7042#define DCMI_CWSIZE_CAPCNT_13 (0x2000U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00002000 */
7043#define DCMI_CWSIZE_VLINE_Pos (16U)
7044#define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
7045#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk /*!< DCMI Vertical line count VLINE[13:0] */
7046#define DCMI_CWSIZE_VLINE_0 (0x0001U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00010000 */
7047#define DCMI_CWSIZE_VLINE_1 (0x0002U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00020000 */
7048#define DCMI_CWSIZE_VLINE_2 (0x0004U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00040000 */
7049#define DCMI_CWSIZE_VLINE_3 (0x0008U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00080000 */
7050#define DCMI_CWSIZE_VLINE_4 (0x0010U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00100000 */
7051#define DCMI_CWSIZE_VLINE_5 (0x0020U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00200000 */
7052#define DCMI_CWSIZE_VLINE_6 (0x0040U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00400000 */
7053#define DCMI_CWSIZE_VLINE_7 (0x0080U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00800000 */
7054#define DCMI_CWSIZE_VLINE_8 (0x0100U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x01000000 */
7055#define DCMI_CWSIZE_VLINE_9 (0x0200U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x02000000 */
7056#define DCMI_CWSIZE_VLINE_10 (0x0400U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x04000000 */
7057#define DCMI_CWSIZE_VLINE_11 (0x0800U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x08000000 */
7058#define DCMI_CWSIZE_VLINE_12 (0x1000U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x10000000 */
7059#define DCMI_CWSIZE_VLINE_13 (0x2000U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x20000000 */
7060
7061/******************** Bits definition for DCMI_DR register **************/
7062#define DCMI_DR_BYTE0_Pos (0U)
7063#define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
7064#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk /*!< DCMI Data byte 0 Byte0[7:0] */
7065#define DCMI_DR_BYTE0_0 (0x01U << DCMI_DR_BYTE0_Pos) /*!< 0x00000001 */
7066#define DCMI_DR_BYTE0_1 (0x02U << DCMI_DR_BYTE0_Pos) /*!< 0x00000002 */
7067#define DCMI_DR_BYTE0_2 (0x04U << DCMI_DR_BYTE0_Pos) /*!< 0x00000004 */
7068#define DCMI_DR_BYTE0_3 (0x08U << DCMI_DR_BYTE0_Pos) /*!< 0x00000008 */
7069#define DCMI_DR_BYTE0_4 (0x10U << DCMI_DR_BYTE0_Pos) /*!< 0x00000010 */
7070#define DCMI_DR_BYTE0_5 (0x20U << DCMI_DR_BYTE0_Pos) /*!< 0x00000020 */
7071#define DCMI_DR_BYTE0_6 (0x40U << DCMI_DR_BYTE0_Pos) /*!< 0x00000040 */
7072#define DCMI_DR_BYTE0_7 (0x80U << DCMI_DR_BYTE0_Pos) /*!< 0x00000080 */
7073#define DCMI_DR_BYTE1_Pos (8U)
7074#define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
7075#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk /*!< DCMI Data byte 1 Byte1[7:0] */
7076#define DCMI_DR_BYTE1_0 (0x01U << DCMI_DR_BYTE1_Pos) /*!< 0x00000100 */
7077#define DCMI_DR_BYTE1_1 (0x02U << DCMI_DR_BYTE1_Pos) /*!< 0x00000200 */
7078#define DCMI_DR_BYTE1_2 (0x04U << DCMI_DR_BYTE1_Pos) /*!< 0x00000400 */
7079#define DCMI_DR_BYTE1_3 (0x08U << DCMI_DR_BYTE1_Pos) /*!< 0x00000800 */
7080#define DCMI_DR_BYTE1_4 (0x10U << DCMI_DR_BYTE1_Pos) /*!< 0x00001000 */
7081#define DCMI_DR_BYTE1_5 (0x20U << DCMI_DR_BYTE1_Pos) /*!< 0x00002000 */
7082#define DCMI_DR_BYTE1_6 (0x40U << DCMI_DR_BYTE1_Pos) /*!< 0x00004000 */
7083#define DCMI_DR_BYTE1_7 (0x80U << DCMI_DR_BYTE1_Pos) /*!< 0x00008000 */
7084#define DCMI_DR_BYTE2_Pos (16U)
7085#define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
7086#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk /*!< DCMI Data byte 2 Byte2[7:0] */
7087#define DCMI_DR_BYTE2_0 (0x01U << DCMI_DR_BYTE2_Pos) /*!< 0x00010000 */
7088#define DCMI_DR_BYTE2_1 (0x02U << DCMI_DR_BYTE2_Pos) /*!< 0x00020000 */
7089#define DCMI_DR_BYTE2_2 (0x04U << DCMI_DR_BYTE2_Pos) /*!< 0x00040000 */
7090#define DCMI_DR_BYTE2_3 (0x08U << DCMI_DR_BYTE2_Pos) /*!< 0x00080000 */
7091#define DCMI_DR_BYTE2_4 (0x10U << DCMI_DR_BYTE2_Pos) /*!< 0x00100000 */
7092#define DCMI_DR_BYTE2_5 (0x20U << DCMI_DR_BYTE2_Pos) /*!< 0x00200000 */
7093#define DCMI_DR_BYTE2_6 (0x40U << DCMI_DR_BYTE2_Pos) /*!< 0x00400000 */
7094#define DCMI_DR_BYTE2_7 (0x80U << DCMI_DR_BYTE2_Pos) /*!< 0x00800000 */
7095#define DCMI_DR_BYTE3_Pos (24U)
7096#define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
7097#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk /*!< DCMI Data byte 3 Byte3[7:0] */
7098#define DCMI_DR_BYTE3_0 (0x01U << DCMI_DR_BYTE3_Pos) /*!< 0x01000000 */
7099#define DCMI_DR_BYTE3_1 (0x02U << DCMI_DR_BYTE3_Pos) /*!< 0x02000000 */
7100#define DCMI_DR_BYTE3_2 (0x04U << DCMI_DR_BYTE3_Pos) /*!< 0x04000000 */
7101#define DCMI_DR_BYTE3_3 (0x08U << DCMI_DR_BYTE3_Pos) /*!< 0x08000000 */
7102#define DCMI_DR_BYTE3_4 (0x10U << DCMI_DR_BYTE3_Pos) /*!< 0x10000000 */
7103#define DCMI_DR_BYTE3_5 (0x20U << DCMI_DR_BYTE3_Pos) /*!< 0x20000000 */
7104#define DCMI_DR_BYTE3_6 (0x40U << DCMI_DR_BYTE3_Pos) /*!< 0x40000000 */
7105#define DCMI_DR_BYTE3_7 (0x80U << DCMI_DR_BYTE3_Pos) /*!< 0x80000000 */
7106
7107/******************************************************************************/
7108/* */
7109/* Digital Filter for Sigma Delta Modulators */
7110/* */
7111/******************************************************************************/
7112
7113/**************** DFSDM channel configuration registers ********************/
7114
7115/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
7116#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
7117#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
7118#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
7119#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
7120#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
7121#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
7122#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
7123#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
7124#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
7125#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
7126#define DFSDM_CHCFGR1_DATPACK_Msk (0x3U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
7127#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
7128#define DFSDM_CHCFGR1_DATPACK_1 (0x2U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
7129#define DFSDM_CHCFGR1_DATPACK_0 (0x1U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
7130#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
7131#define DFSDM_CHCFGR1_DATMPX_Msk (0x3U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
7132#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
7133#define DFSDM_CHCFGR1_DATMPX_1 (0x2U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
7134#define DFSDM_CHCFGR1_DATMPX_0 (0x1U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
7135#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
7136#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
7137#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
7138#define DFSDM_CHCFGR1_CHEN_Pos (7U)
7139#define DFSDM_CHCFGR1_CHEN_Msk (0x1U << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
7140#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
7141#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
7142#define DFSDM_CHCFGR1_CKABEN_Msk (0x1U << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
7143#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
7144#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
7145#define DFSDM_CHCFGR1_SCDEN_Msk (0x1U << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
7146#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
7147#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
7148#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
7149#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
7150#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
7151#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
7152#define DFSDM_CHCFGR1_SITP_Pos (0U)
7153#define DFSDM_CHCFGR1_SITP_Msk (0x3U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
7154#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
7155#define DFSDM_CHCFGR1_SITP_1 (0x2U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
7156#define DFSDM_CHCFGR1_SITP_0 (0x1U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
7157
7158/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
7159#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
7160#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
7161#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
7162#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
7163#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
7164#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
7165
7166/**************** Bit definition for DFSDM_CHAWSCDR register *****************/
7167#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
7168#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
7169#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
7170#define DFSDM_CHAWSCDR_AWFORD_1 (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
7171#define DFSDM_CHAWSCDR_AWFORD_0 (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
7172#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
7173#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
7174#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
7175#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
7176#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
7177#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
7178#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
7179#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
7180#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
7181
7182/**************** Bit definition for DFSDM_CHWDATR register *******************/
7183#define DFSDM_CHWDATR_WDATA_Pos (0U)
7184#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
7185#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
7186
7187/**************** Bit definition for DFSDM_CHDATINR register *****************/
7188#define DFSDM_CHDATINR_INDAT0_Pos (0U)
7189#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
7190#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
7191#define DFSDM_CHDATINR_INDAT1_Pos (16U)
7192#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
7193#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
7194
7195/**************** Bit definition for DFSDM_CHDLYR register *******************/
7196#define DFSDM_CHDLYR_PLSSKP_Pos (0U)
7197#define DFSDM_CHDLYR_PLSSKP_Msk (0x3FU << DFSDM_CHDLYR_PLSSKP_Pos) /*!< 0x0000003F */
7198#define DFSDM_CHDLYR_PLSSKP DFSDM_CHDLYR_PLSSKP_Msk /*!< PLSSKP[5:0] Number of input serial samples that will be skipped */
7199
7200/************************ DFSDM module registers ****************************/
7201
7202/***************** Bit definition for DFSDM_FLTCR1 register *******************/
7203#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
7204#define DFSDM_FLTCR1_AWFSEL_Msk (0x1U << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
7205#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
7206#define DFSDM_FLTCR1_FAST_Pos (29U)
7207#define DFSDM_FLTCR1_FAST_Msk (0x1U << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
7208#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
7209#define DFSDM_FLTCR1_RCH_Pos (24U)
7210#define DFSDM_FLTCR1_RCH_Msk (0x7U << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
7211#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
7212#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
7213#define DFSDM_FLTCR1_RDMAEN_Msk (0x1U << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
7214#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
7215#define DFSDM_FLTCR1_RSYNC_Pos (19U)
7216#define DFSDM_FLTCR1_RSYNC_Msk (0x1U << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
7217#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
7218#define DFSDM_FLTCR1_RCONT_Pos (18U)
7219#define DFSDM_FLTCR1_RCONT_Msk (0x1U << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
7220#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
7221#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
7222#define DFSDM_FLTCR1_RSWSTART_Msk (0x1U << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
7223#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
7224#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
7225#define DFSDM_FLTCR1_JEXTEN_Msk (0x3U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
7226#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
7227#define DFSDM_FLTCR1_JEXTEN_1 (0x2U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
7228#define DFSDM_FLTCR1_JEXTEN_0 (0x1U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
7229#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
7230#define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FU << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001F00 */
7231#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
7232#define DFSDM_FLTCR1_JEXTSEL_4 (0x10U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001000 */
7233#define DFSDM_FLTCR1_JEXTSEL_3 (0x08U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000800 */
7234#define DFSDM_FLTCR1_JEXTSEL_2 (0x04U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
7235#define DFSDM_FLTCR1_JEXTSEL_1 (0x02U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
7236#define DFSDM_FLTCR1_JEXTSEL_0 (0x01U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
7237#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
7238#define DFSDM_FLTCR1_JDMAEN_Msk (0x1U << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
7239#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
7240#define DFSDM_FLTCR1_JSCAN_Pos (4U)
7241#define DFSDM_FLTCR1_JSCAN_Msk (0x1U << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
7242#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
7243#define DFSDM_FLTCR1_JSYNC_Pos (3U)
7244#define DFSDM_FLTCR1_JSYNC_Msk (0x1U << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
7245#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
7246#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
7247#define DFSDM_FLTCR1_JSWSTART_Msk (0x1U << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
7248#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
7249#define DFSDM_FLTCR1_DFEN_Pos (0U)
7250#define DFSDM_FLTCR1_DFEN_Msk (0x1U << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
7251#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
7252
7253/***************** Bit definition for DFSDM_FLTCR2 register *******************/
7254#define DFSDM_FLTCR2_AWDCH_Pos (16U)
7255#define DFSDM_FLTCR2_AWDCH_Msk (0xFFU << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
7256#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
7257#define DFSDM_FLTCR2_EXCH_Pos (8U)
7258#define DFSDM_FLTCR2_EXCH_Msk (0xFFU << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
7259#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
7260#define DFSDM_FLTCR2_CKABIE_Pos (6U)
7261#define DFSDM_FLTCR2_CKABIE_Msk (0x1U << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
7262#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
7263#define DFSDM_FLTCR2_SCDIE_Pos (5U)
7264#define DFSDM_FLTCR2_SCDIE_Msk (0x1U << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
7265#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
7266#define DFSDM_FLTCR2_AWDIE_Pos (4U)
7267#define DFSDM_FLTCR2_AWDIE_Msk (0x1U << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
7268#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
7269#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
7270#define DFSDM_FLTCR2_ROVRIE_Msk (0x1U << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
7271#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
7272#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
7273#define DFSDM_FLTCR2_JOVRIE_Msk (0x1U << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
7274#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
7275#define DFSDM_FLTCR2_REOCIE_Pos (1U)
7276#define DFSDM_FLTCR2_REOCIE_Msk (0x1U << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
7277#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
7278#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
7279#define DFSDM_FLTCR2_JEOCIE_Msk (0x1U << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
7280#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
7281
7282/***************** Bit definition for DFSDM_FLTISR register *******************/
7283#define DFSDM_FLTISR_SCDF_Pos (24U)
7284#define DFSDM_FLTISR_SCDF_Msk (0xFFU << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
7285#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
7286#define DFSDM_FLTISR_CKABF_Pos (16U)
7287#define DFSDM_FLTISR_CKABF_Msk (0xFFU << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
7288#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
7289#define DFSDM_FLTISR_RCIP_Pos (14U)
7290#define DFSDM_FLTISR_RCIP_Msk (0x1U << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
7291#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
7292#define DFSDM_FLTISR_JCIP_Pos (13U)
7293#define DFSDM_FLTISR_JCIP_Msk (0x1U << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
7294#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
7295#define DFSDM_FLTISR_AWDF_Pos (4U)
7296#define DFSDM_FLTISR_AWDF_Msk (0x1U << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
7297#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
7298#define DFSDM_FLTISR_ROVRF_Pos (3U)
7299#define DFSDM_FLTISR_ROVRF_Msk (0x1U << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
7300#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
7301#define DFSDM_FLTISR_JOVRF_Pos (2U)
7302#define DFSDM_FLTISR_JOVRF_Msk (0x1U << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
7303#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
7304#define DFSDM_FLTISR_REOCF_Pos (1U)
7305#define DFSDM_FLTISR_REOCF_Msk (0x1U << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
7306#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
7307#define DFSDM_FLTISR_JEOCF_Pos (0U)
7308#define DFSDM_FLTISR_JEOCF_Msk (0x1U << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
7309#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
7310
7311/***************** Bit definition for DFSDM_FLTICR register *******************/
7312#define DFSDM_FLTICR_CLRSCSDF_Pos (24U)
7313#define DFSDM_FLTICR_CLRSCSDF_Msk (0xFFU << DFSDM_FLTICR_CLRSCSDF_Pos) /*!< 0xFF000000 */
7314#define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCSDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
7315#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
7316#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFU << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
7317#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
7318#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
7319#define DFSDM_FLTICR_CLRROVRF_Msk (0x1U << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
7320#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
7321#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
7322#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
7323#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
7324
7325/**************** Bit definition for DFSDM_FLTJCHGR register ******************/
7326#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
7327#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFU << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
7328#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
7329
7330/***************** Bit definition for DFSDM_FLTFCR register *******************/
7331#define DFSDM_FLTFCR_FORD_Pos (29U)
7332#define DFSDM_FLTFCR_FORD_Msk (0x7U << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
7333#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
7334#define DFSDM_FLTFCR_FORD_2 (0x4U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
7335#define DFSDM_FLTFCR_FORD_1 (0x2U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
7336#define DFSDM_FLTFCR_FORD_0 (0x1U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
7337#define DFSDM_FLTFCR_FOSR_Pos (16U)
7338#define DFSDM_FLTFCR_FOSR_Msk (0x3FFU << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
7339#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
7340#define DFSDM_FLTFCR_IOSR_Pos (0U)
7341#define DFSDM_FLTFCR_IOSR_Msk (0xFFU << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
7342#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
7343
7344/*************** Bit definition for DFSDM_FLTJDATAR register *****************/
7345#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
7346#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
7347#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
7348#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
7349#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
7350#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
7351
7352/*************** Bit definition for DFSDM_FLTRDATAR register *****************/
7353#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
7354#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
7355#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
7356#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
7357#define DFSDM_FLTRDATAR_RPEND_Msk (0x1U << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
7358#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
7359#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
7360#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
7361#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
7362
7363/*************** Bit definition for DFSDM_FLTAWHTR register ******************/
7364#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
7365#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
7366#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
7367#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
7368#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
7369#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
7370
7371/*************** Bit definition for DFSDM_FLTAWLTR register ******************/
7372#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
7373#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
7374#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWLT[23:0] Analog watchdog low threshold */
7375#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
7376#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
7377#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
7378
7379/*************** Bit definition for DFSDM_FLTAWSR register *******************/
7380#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
7381#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFU << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
7382#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
7383#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
7384#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFU << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
7385#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
7386
7387/*************** Bit definition for DFSDM_FLTAWCFR register ******************/
7388#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
7389#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
7390#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
7391#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
7392#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
7393#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
7394
7395/*************** Bit definition for DFSDM_FLTEXMAX register ******************/
7396#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
7397#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
7398#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
7399#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
7400#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
7401#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
7402
7403/*************** Bit definition for DFSDM_FLTEXMIN register ******************/
7404#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
7405#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
7406#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
7407#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
7408#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
7409#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
7410
7411/*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
7412#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
7413#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
7414#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
7415
7416/******************************************************************************/
7417/* */
7418/* DMA Controller (DMA) */
7419/* */
7420/******************************************************************************/
7421
7422/******************* Bit definition for DMA_ISR register ********************/
7423#define DMA_ISR_GIF1_Pos (0U)
7424#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
7425#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
7426#define DMA_ISR_TCIF1_Pos (1U)
7427#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
7428#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
7429#define DMA_ISR_HTIF1_Pos (2U)
7430#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
7431#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
7432#define DMA_ISR_TEIF1_Pos (3U)
7433#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
7434#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
7435#define DMA_ISR_GIF2_Pos (4U)
7436#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
7437#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
7438#define DMA_ISR_TCIF2_Pos (5U)
7439#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
7440#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
7441#define DMA_ISR_HTIF2_Pos (6U)
7442#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
7443#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
7444#define DMA_ISR_TEIF2_Pos (7U)
7445#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
7446#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
7447#define DMA_ISR_GIF3_Pos (8U)
7448#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
7449#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
7450#define DMA_ISR_TCIF3_Pos (9U)
7451#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
7452#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
7453#define DMA_ISR_HTIF3_Pos (10U)
7454#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
7455#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
7456#define DMA_ISR_TEIF3_Pos (11U)
7457#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
7458#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
7459#define DMA_ISR_GIF4_Pos (12U)
7460#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
7461#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
7462#define DMA_ISR_TCIF4_Pos (13U)
7463#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
7464#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
7465#define DMA_ISR_HTIF4_Pos (14U)
7466#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
7467#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
7468#define DMA_ISR_TEIF4_Pos (15U)
7469#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
7470#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
7471#define DMA_ISR_GIF5_Pos (16U)
7472#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
7473#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
7474#define DMA_ISR_TCIF5_Pos (17U)
7475#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
7476#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
7477#define DMA_ISR_HTIF5_Pos (18U)
7478#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
7479#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
7480#define DMA_ISR_TEIF5_Pos (19U)
7481#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
7482#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
7483#define DMA_ISR_GIF6_Pos (20U)
7484#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
7485#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
7486#define DMA_ISR_TCIF6_Pos (21U)
7487#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
7488#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
7489#define DMA_ISR_HTIF6_Pos (22U)
7490#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
7491#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
7492#define DMA_ISR_TEIF6_Pos (23U)
7493#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
7494#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
7495#define DMA_ISR_GIF7_Pos (24U)
7496#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
7497#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
7498#define DMA_ISR_TCIF7_Pos (25U)
7499#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
7500#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
7501#define DMA_ISR_HTIF7_Pos (26U)
7502#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
7503#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
7504#define DMA_ISR_TEIF7_Pos (27U)
7505#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
7506#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
7507
7508/******************* Bit definition for DMA_IFCR register *******************/
7509#define DMA_IFCR_CGIF1_Pos (0U)
7510#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
7511#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
7512#define DMA_IFCR_CTCIF1_Pos (1U)
7513#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
7514#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
7515#define DMA_IFCR_CHTIF1_Pos (2U)
7516#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
7517#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
7518#define DMA_IFCR_CTEIF1_Pos (3U)
7519#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
7520#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
7521#define DMA_IFCR_CGIF2_Pos (4U)
7522#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
7523#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
7524#define DMA_IFCR_CTCIF2_Pos (5U)
7525#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
7526#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
7527#define DMA_IFCR_CHTIF2_Pos (6U)
7528#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
7529#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
7530#define DMA_IFCR_CTEIF2_Pos (7U)
7531#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
7532#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
7533#define DMA_IFCR_CGIF3_Pos (8U)
7534#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
7535#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
7536#define DMA_IFCR_CTCIF3_Pos (9U)
7537#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
7538#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
7539#define DMA_IFCR_CHTIF3_Pos (10U)
7540#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
7541#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
7542#define DMA_IFCR_CTEIF3_Pos (11U)
7543#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
7544#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
7545#define DMA_IFCR_CGIF4_Pos (12U)
7546#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
7547#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
7548#define DMA_IFCR_CTCIF4_Pos (13U)
7549#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
7550#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
7551#define DMA_IFCR_CHTIF4_Pos (14U)
7552#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
7553#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
7554#define DMA_IFCR_CTEIF4_Pos (15U)
7555#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
7556#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
7557#define DMA_IFCR_CGIF5_Pos (16U)
7558#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
7559#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
7560#define DMA_IFCR_CTCIF5_Pos (17U)
7561#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
7562#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
7563#define DMA_IFCR_CHTIF5_Pos (18U)
7564#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
7565#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
7566#define DMA_IFCR_CTEIF5_Pos (19U)
7567#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
7568#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
7569#define DMA_IFCR_CGIF6_Pos (20U)
7570#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
7571#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
7572#define DMA_IFCR_CTCIF6_Pos (21U)
7573#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
7574#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
7575#define DMA_IFCR_CHTIF6_Pos (22U)
7576#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
7577#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
7578#define DMA_IFCR_CTEIF6_Pos (23U)
7579#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
7580#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
7581#define DMA_IFCR_CGIF7_Pos (24U)
7582#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
7583#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
7584#define DMA_IFCR_CTCIF7_Pos (25U)
7585#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
7586#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
7587#define DMA_IFCR_CHTIF7_Pos (26U)
7588#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
7589#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
7590#define DMA_IFCR_CTEIF7_Pos (27U)
7591#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
7592#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
7593
7594/******************* Bit definition for DMA_CCR register ********************/
7595#define DMA_CCR_EN_Pos (0U)
7596#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
7597#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
7598#define DMA_CCR_TCIE_Pos (1U)
7599#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
7600#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
7601#define DMA_CCR_HTIE_Pos (2U)
7602#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
7603#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
7604#define DMA_CCR_TEIE_Pos (3U)
7605#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
7606#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
7607#define DMA_CCR_DIR_Pos (4U)
7608#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
7609#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
7610#define DMA_CCR_CIRC_Pos (5U)
7611#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
7612#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
7613#define DMA_CCR_PINC_Pos (6U)
7614#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
7615#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
7616#define DMA_CCR_MINC_Pos (7U)
7617#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
7618#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
7619
7620#define DMA_CCR_PSIZE_Pos (8U)
7621#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
7622#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
7623#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
7624#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
7625
7626#define DMA_CCR_MSIZE_Pos (10U)
7627#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
7628#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
7629#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
7630#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
7631
7632#define DMA_CCR_PL_Pos (12U)
7633#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
7634#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
7635#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
7636#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
7637
7638#define DMA_CCR_MEM2MEM_Pos (14U)
7639#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
7640#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
7641
7642/****************** Bit definition for DMA_CNDTR register *******************/
7643#define DMA_CNDTR_NDT_Pos (0U)
7644#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
7645#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
7646
7647/****************** Bit definition for DMA_CPAR register ********************/
7648#define DMA_CPAR_PA_Pos (0U)
7649#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
7650#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
7651
7652/****************** Bit definition for DMA_CMAR register ********************/
7653#define DMA_CMAR_MA_Pos (0U)
7654#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
7655#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
7656
7657
7658
7659/******************************************************************************/
7660/* */
7661/* DMAMUX Controller */
7662/* */
7663/******************************************************************************/
7664
7665/******************** Bits definition for DMAMUX_CxCR register **************/
7666#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
7667#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFU << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */
7668#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
7669#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
7670#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
7671#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
7672#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
7673#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
7674#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
7675#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
7676#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
7677
7678#define DMAMUX_CxCR_SOIE_Pos (8U)
7679#define DMAMUX_CxCR_SOIE_Msk (0x1U << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
7680#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk
7681
7682#define DMAMUX_CxCR_EGE_Pos (9U)
7683#define DMAMUX_CxCR_EGE_Msk (0x1U << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */
7684#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk
7685
7686#define DMAMUX_CxCR_SE_Pos (16U)
7687#define DMAMUX_CxCR_SE_Msk (0x1U << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */
7688#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk
7689
7690#define DMAMUX_CxCR_SPOL_Pos (17U)
7691#define DMAMUX_CxCR_SPOL_Msk (0x3U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
7692#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk
7693#define DMAMUX_CxCR_SPOL_0 (0x1U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */
7694#define DMAMUX_CxCR_SPOL_1 (0x2U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */
7695
7696#define DMAMUX_CxCR_NBREQ_Pos (19U)
7697#define DMAMUX_CxCR_NBREQ_Msk (0x1FU << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
7698#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk
7699#define DMAMUX_CxCR_NBREQ_0 (0x01U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
7700#define DMAMUX_CxCR_NBREQ_1 (0x02U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
7701#define DMAMUX_CxCR_NBREQ_2 (0x04U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
7702#define DMAMUX_CxCR_NBREQ_3 (0x08U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
7703#define DMAMUX_CxCR_NBREQ_4 (0x10U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
7704
7705#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
7706#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FU << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
7707#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk
7708#define DMAMUX_CxCR_SYNC_ID_0 (0x01U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
7709#define DMAMUX_CxCR_SYNC_ID_1 (0x02U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
7710#define DMAMUX_CxCR_SYNC_ID_2 (0x04U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
7711#define DMAMUX_CxCR_SYNC_ID_3 (0x08U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
7712#define DMAMUX_CxCR_SYNC_ID_4 (0x10U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
7713
7714/******************** Bits definition for DMAMUX_CSR register ****************/
7715#define DMAMUX_CSR_SOF0_Pos (0U)
7716#define DMAMUX_CSR_SOF0_Msk (0x1U << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */
7717#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk
7718#define DMAMUX_CSR_SOF1_Pos (1U)
7719#define DMAMUX_CSR_SOF1_Msk (0x1U << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */
7720#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk
7721#define DMAMUX_CSR_SOF2_Pos (2U)
7722#define DMAMUX_CSR_SOF2_Msk (0x1U << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */
7723#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk
7724#define DMAMUX_CSR_SOF3_Pos (3U)
7725#define DMAMUX_CSR_SOF3_Msk (0x1U << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */
7726#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk
7727#define DMAMUX_CSR_SOF4_Pos (4U)
7728#define DMAMUX_CSR_SOF4_Msk (0x1U << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */
7729#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk
7730#define DMAMUX_CSR_SOF5_Pos (5U)
7731#define DMAMUX_CSR_SOF5_Msk (0x1U << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */
7732#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk
7733#define DMAMUX_CSR_SOF6_Pos (6U)
7734#define DMAMUX_CSR_SOF6_Msk (0x1U << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */
7735#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk
7736#define DMAMUX_CSR_SOF7_Pos (7U)
7737#define DMAMUX_CSR_SOF7_Msk (0x1U << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */
7738#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk
7739#define DMAMUX_CSR_SOF8_Pos (8U)
7740#define DMAMUX_CSR_SOF8_Msk (0x1U << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */
7741#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk
7742#define DMAMUX_CSR_SOF9_Pos (9U)
7743#define DMAMUX_CSR_SOF9_Msk (0x1U << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */
7744#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk
7745#define DMAMUX_CSR_SOF10_Pos (10U)
7746#define DMAMUX_CSR_SOF10_Msk (0x1U << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */
7747#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk
7748#define DMAMUX_CSR_SOF11_Pos (11U)
7749#define DMAMUX_CSR_SOF11_Msk (0x1U << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */
7750#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk
7751#define DMAMUX_CSR_SOF12_Pos (12U)
7752#define DMAMUX_CSR_SOF12_Msk (0x1U << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */
7753#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk
7754#define DMAMUX_CSR_SOF13_Pos (13U)
7755#define DMAMUX_CSR_SOF13_Msk (0x1U << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */
7756#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk
7757
7758/******************** Bits definition for DMAMUX_CFR register ****************/
7759
7760#define DMAMUX_CFR_CSOF0_Pos (0U)
7761#define DMAMUX_CFR_CSOF0_Msk (0x1U << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
7762#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk
7763#define DMAMUX_CFR_CSOF1_Pos (1U)
7764#define DMAMUX_CFR_CSOF1_Msk (0x1U << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
7765#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk
7766#define DMAMUX_CFR_CSOF2_Pos (2U)
7767#define DMAMUX_CFR_CSOF2_Msk (0x1U << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
7768#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk
7769#define DMAMUX_CFR_CSOF3_Pos (3U)
7770#define DMAMUX_CFR_CSOF3_Msk (0x1U << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
7771#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk
7772#define DMAMUX_CFR_CSOF4_Pos (4U)
7773#define DMAMUX_CFR_CSOF4_Msk (0x1U << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
7774#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk
7775#define DMAMUX_CFR_CSOF5_Pos (5U)
7776#define DMAMUX_CFR_CSOF5_Msk (0x1U << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
7777#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk
7778#define DMAMUX_CFR_CSOF6_Pos (6U)
7779#define DMAMUX_CFR_CSOF6_Msk (0x1U << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
7780#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk
7781#define DMAMUX_CFR_CSOF7_Pos (7U)
7782#define DMAMUX_CFR_CSOF7_Msk (0x1U << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */
7783#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk
7784#define DMAMUX_CFR_CSOF8_Pos (8U)
7785#define DMAMUX_CFR_CSOF8_Msk (0x1U << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */
7786#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk
7787#define DMAMUX_CFR_CSOF9_Pos (9U)
7788#define DMAMUX_CFR_CSOF9_Msk (0x1U << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */
7789#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk
7790#define DMAMUX_CFR_CSOF10_Pos (10U)
7791#define DMAMUX_CFR_CSOF10_Msk (0x1U << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */
7792#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk
7793#define DMAMUX_CFR_CSOF11_Pos (11U)
7794#define DMAMUX_CFR_CSOF11_Msk (0x1U << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */
7795#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk
7796#define DMAMUX_CFR_CSOF12_Pos (12U)
7797#define DMAMUX_CFR_CSOF12_Msk (0x1U << DMAMUX_CFR_CSOF12_Pos) /*!< 0x00001000 */
7798#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk
7799#define DMAMUX_CFR_CSOF13_Pos (13U)
7800#define DMAMUX_CFR_CSOF13_Msk (0x1U << DMAMUX_CFR_CSOF13_Pos) /*!< 0x00002000 */
7801#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk
7802
7803/******************** Bits definition for DMAMUX_RGxCR register ************/
7804#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
7805#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FU << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
7806#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk
7807#define DMAMUX_RGxCR_SIG_ID_0 (0x01U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
7808#define DMAMUX_RGxCR_SIG_ID_1 (0x02U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
7809#define DMAMUX_RGxCR_SIG_ID_2 (0x04U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
7810#define DMAMUX_RGxCR_SIG_ID_3 (0x08U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
7811#define DMAMUX_RGxCR_SIG_ID_4 (0x10U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
7812
7813#define DMAMUX_RGxCR_OIE_Pos (8U)
7814#define DMAMUX_RGxCR_OIE_Msk (0x1U << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
7815#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk
7816
7817#define DMAMUX_RGxCR_GE_Pos (16U)
7818#define DMAMUX_RGxCR_GE_Msk (0x1U << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */
7819#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk
7820
7821#define DMAMUX_RGxCR_GPOL_Pos (17U)
7822#define DMAMUX_RGxCR_GPOL_Msk (0x3U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
7823#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk
7824#define DMAMUX_RGxCR_GPOL_0 (0x1U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
7825#define DMAMUX_RGxCR_GPOL_1 (0x2U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
7826
7827#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
7828#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FU << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
7829#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk
7830#define DMAMUX_RGxCR_GNBREQ_0 (0x01U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
7831#define DMAMUX_RGxCR_GNBREQ_1 (0x02U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */
7832#define DMAMUX_RGxCR_GNBREQ_2 (0x04U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */
7833#define DMAMUX_RGxCR_GNBREQ_3 (0x08U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */
7834#define DMAMUX_RGxCR_GNBREQ_4 (0x10U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */
7835
7836/******************** Bits definition for DMAMUX_RGSR register **************/
7837#define DMAMUX_RGSR_OF0_Pos (0U)
7838#define DMAMUX_RGSR_OF0_Msk (0x1U << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */
7839#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk
7840#define DMAMUX_RGSR_OF1_Pos (1U)
7841#define DMAMUX_RGSR_OF1_Msk (0x1U << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */
7842#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk
7843#define DMAMUX_RGSR_OF2_Pos (2U)
7844#define DMAMUX_RGSR_OF2_Msk (0x1U << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */
7845#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk
7846#define DMAMUX_RGSR_OF3_Pos (3U)
7847#define DMAMUX_RGSR_OF3_Msk (0x1U << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */
7848#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk
7849
7850/******************** Bits definition for DMAMUX_RGCFR register ************/
7851#define DMAMUX_RGCFR_COF0_Pos (0U)
7852#define DMAMUX_RGCFR_COF0_Msk (0x1U << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
7853#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk
7854#define DMAMUX_RGCFR_COF1_Pos (1U)
7855#define DMAMUX_RGCFR_COF1_Msk (0x1U << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
7856#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk
7857#define DMAMUX_RGCFR_COF2_Pos (2U)
7858#define DMAMUX_RGCFR_COF2_Msk (0x1U << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
7859#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk
7860#define DMAMUX_RGCFR_COF3_Pos (3U)
7861#define DMAMUX_RGCFR_COF3_Msk (0x1U << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
7862#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk
7863
7864/******************************************************************************/
7865/* */
7866/* AHB Master DMA2D Controller (DMA2D) */
7867/* */
7868/******************************************************************************/
7869/*
7870* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
7871*/
7872#define DMA2D_LINE_OFFSET_MODE_SUPPORT
7873#define DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT
7874#define DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT
7875
7876/******************** Bit definition for DMA2D_CR register ******************/
7877
7878#define DMA2D_CR_START_Pos (0U)
7879#define DMA2D_CR_START_Msk (0x1U << DMA2D_CR_START_Pos) /*!< 0x00000001 */
7880#define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
7881#define DMA2D_CR_SUSP_Pos (1U)
7882#define DMA2D_CR_SUSP_Msk (0x1U << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
7883#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
7884#define DMA2D_CR_ABORT_Pos (2U)
7885#define DMA2D_CR_ABORT_Msk (0x1U << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
7886#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
7887#define DMA2D_CR_LOM_Pos (6U)
7888#define DMA2D_CR_LOM_Msk (0x1U << DMA2D_CR_LOM_Pos) /*!< 0x00000040 */
7889#define DMA2D_CR_LOM DMA2D_CR_LOM_Msk /*!< Line Offset Mode */
7890#define DMA2D_CR_TEIE_Pos (8U)
7891#define DMA2D_CR_TEIE_Msk (0x1U << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
7892#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
7893#define DMA2D_CR_TCIE_Pos (9U)
7894#define DMA2D_CR_TCIE_Msk (0x1U << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
7895#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
7896#define DMA2D_CR_TWIE_Pos (10U)
7897#define DMA2D_CR_TWIE_Msk (0x1U << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
7898#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
7899#define DMA2D_CR_CAEIE_Pos (11U)
7900#define DMA2D_CR_CAEIE_Msk (0x1U << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
7901#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
7902#define DMA2D_CR_CTCIE_Pos (12U)
7903#define DMA2D_CR_CTCIE_Msk (0x1U << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
7904#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
7905#define DMA2D_CR_CEIE_Pos (13U)
7906#define DMA2D_CR_CEIE_Msk (0x1U << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
7907#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
7908#define DMA2D_CR_MODE_Pos (16U)
7909#define DMA2D_CR_MODE_Msk (0x7U << DMA2D_CR_MODE_Pos) /*!< 0x00070000 */
7910#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[2:0] */
7911#define DMA2D_CR_MODE_0 (0x1U << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
7912#define DMA2D_CR_MODE_1 (0x2U << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
7913#define DMA2D_CR_MODE_2 (0x4U << DMA2D_CR_MODE_Pos) /*!< 0x00040000 */
7914
7915/******************** Bit definition for DMA2D_ISR register *****************/
7916
7917#define DMA2D_ISR_TEIF_Pos (0U)
7918#define DMA2D_ISR_TEIF_Msk (0x1U << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
7919#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
7920#define DMA2D_ISR_TCIF_Pos (1U)
7921#define DMA2D_ISR_TCIF_Msk (0x1U << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
7922#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
7923#define DMA2D_ISR_TWIF_Pos (2U)
7924#define DMA2D_ISR_TWIF_Msk (0x1U << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
7925#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
7926#define DMA2D_ISR_CAEIF_Pos (3U)
7927#define DMA2D_ISR_CAEIF_Msk (0x1U << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
7928#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
7929#define DMA2D_ISR_CTCIF_Pos (4U)
7930#define DMA2D_ISR_CTCIF_Msk (0x1U << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
7931#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
7932#define DMA2D_ISR_CEIF_Pos (5U)
7933#define DMA2D_ISR_CEIF_Msk (0x1U << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
7934#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
7935
7936/******************** Bit definition for DMA2D_IFCR register ****************/
7937
7938#define DMA2D_IFCR_CTEIF_Pos (0U)
7939#define DMA2D_IFCR_CTEIF_Msk (0x1U << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
7940#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
7941#define DMA2D_IFCR_CTCIF_Pos (1U)
7942#define DMA2D_IFCR_CTCIF_Msk (0x1U << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
7943#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
7944#define DMA2D_IFCR_CTWIF_Pos (2U)
7945#define DMA2D_IFCR_CTWIF_Msk (0x1U << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
7946#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
7947#define DMA2D_IFCR_CAECIF_Pos (3U)
7948#define DMA2D_IFCR_CAECIF_Msk (0x1U << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
7949#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
7950#define DMA2D_IFCR_CCTCIF_Pos (4U)
7951#define DMA2D_IFCR_CCTCIF_Msk (0x1U << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
7952#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
7953#define DMA2D_IFCR_CCEIF_Pos (5U)
7954#define DMA2D_IFCR_CCEIF_Msk (0x1U << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
7955#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
7956
7957/******************** Bit definition for DMA2D_FGMAR register ***************/
7958
7959#define DMA2D_FGMAR_MA_Pos (0U)
7960#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
7961#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */
7962
7963/******************** Bit definition for DMA2D_FGOR register ****************/
7964
7965#define DMA2D_FGOR_LO_Pos (0U)
7966#define DMA2D_FGOR_LO_Msk (0xFFFFU << DMA2D_FGOR_LO_Pos) /*!< 0x0000FFFF */
7967#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
7968
7969/******************** Bit definition for DMA2D_BGMAR register ***************/
7970
7971#define DMA2D_BGMAR_MA_Pos (0U)
7972#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
7973#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */
7974
7975/******************** Bit definition for DMA2D_BGOR register ****************/
7976
7977#define DMA2D_BGOR_LO_Pos (0U)
7978#define DMA2D_BGOR_LO_Msk (0xFFFFU << DMA2D_BGOR_LO_Pos) /*!< 0x0000FFFF */
7979#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
7980
7981/******************** Bit definition for DMA2D_FGPFCCR register *************/
7982
7983#define DMA2D_FGPFCCR_CM_Pos (0U)
7984#define DMA2D_FGPFCCR_CM_Msk (0xFU << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
7985#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
7986#define DMA2D_FGPFCCR_CM_0 (0x1U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
7987#define DMA2D_FGPFCCR_CM_1 (0x2U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
7988#define DMA2D_FGPFCCR_CM_2 (0x4U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
7989#define DMA2D_FGPFCCR_CM_3 (0x8U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
7990#define DMA2D_FGPFCCR_CCM_Pos (4U)
7991#define DMA2D_FGPFCCR_CCM_Msk (0x1U << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
7992#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
7993#define DMA2D_FGPFCCR_START_Pos (5U)
7994#define DMA2D_FGPFCCR_START_Msk (0x1U << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
7995#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
7996#define DMA2D_FGPFCCR_CS_Pos (8U)
7997#define DMA2D_FGPFCCR_CS_Msk (0xFFU << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
7998#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
7999#define DMA2D_FGPFCCR_AM_Pos (16U)
8000#define DMA2D_FGPFCCR_AM_Msk (0x3U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
8001#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
8002#define DMA2D_FGPFCCR_AM_0 (0x1U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
8003#define DMA2D_FGPFCCR_AM_1 (0x2U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
8004#define DMA2D_FGPFCCR_AI_Pos (20U)
8005#define DMA2D_FGPFCCR_AI_Msk (0x1U << DMA2D_FGPFCCR_AI_Pos) /*!< 0x00100000 */
8006#define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk /*!< Alpha Inverted */
8007#define DMA2D_FGPFCCR_RBS_Pos (21U)
8008#define DMA2D_FGPFCCR_RBS_Msk (0x1U << DMA2D_FGPFCCR_RBS_Pos) /*!< 0x00200000 */
8009#define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk /*!< Red Blue Swap */
8010#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
8011#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
8012#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
8013
8014/******************** Bit definition for DMA2D_FGCOLR register **************/
8015
8016#define DMA2D_FGCOLR_BLUE_Pos (0U)
8017#define DMA2D_FGCOLR_BLUE_Msk (0xFFU << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
8018#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */
8019#define DMA2D_FGCOLR_GREEN_Pos (8U)
8020#define DMA2D_FGCOLR_GREEN_Msk (0xFFU << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
8021#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */
8022#define DMA2D_FGCOLR_RED_Pos (16U)
8023#define DMA2D_FGCOLR_RED_Msk (0xFFU << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
8024#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */
8025
8026/******************** Bit definition for DMA2D_BGPFCCR register *************/
8027
8028#define DMA2D_BGPFCCR_CM_Pos (0U)
8029#define DMA2D_BGPFCCR_CM_Msk (0xFU << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
8030#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
8031#define DMA2D_BGPFCCR_CM_0 (0x1U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
8032#define DMA2D_BGPFCCR_CM_1 (0x2U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
8033#define DMA2D_BGPFCCR_CM_2 (0x4U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
8034#define DMA2D_BGPFCCR_CM_3 (0x8U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000008 */
8035#define DMA2D_BGPFCCR_CCM_Pos (4U)
8036#define DMA2D_BGPFCCR_CCM_Msk (0x1U << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
8037#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
8038#define DMA2D_BGPFCCR_START_Pos (5U)
8039#define DMA2D_BGPFCCR_START_Msk (0x1U << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
8040#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
8041#define DMA2D_BGPFCCR_CS_Pos (8U)
8042#define DMA2D_BGPFCCR_CS_Msk (0xFFU << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
8043#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
8044#define DMA2D_BGPFCCR_AM_Pos (16U)
8045#define DMA2D_BGPFCCR_AM_Msk (0x3U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
8046#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
8047#define DMA2D_BGPFCCR_AM_0 (0x1U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
8048#define DMA2D_BGPFCCR_AM_1 (0x2U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
8049#define DMA2D_BGPFCCR_AI_Pos (20U)
8050#define DMA2D_BGPFCCR_AI_Msk (0x1U << DMA2D_BGPFCCR_AI_Pos) /*!< 0x00100000 */
8051#define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk /*!< Alpha Inverted */
8052#define DMA2D_BGPFCCR_RBS_Pos (21U)
8053#define DMA2D_BGPFCCR_RBS_Msk (0x1U << DMA2D_BGPFCCR_RBS_Pos) /*!< 0x00200000 */
8054#define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk /*!< Red Blue Swap */
8055#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
8056#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
8057#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< Alpha value */
8058
8059/******************** Bit definition for DMA2D_BGCOLR register **************/
8060
8061#define DMA2D_BGCOLR_BLUE_Pos (0U)
8062#define DMA2D_BGCOLR_BLUE_Msk (0xFFU << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
8063#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */
8064#define DMA2D_BGCOLR_GREEN_Pos (8U)
8065#define DMA2D_BGCOLR_GREEN_Msk (0xFFU << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
8066#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */
8067#define DMA2D_BGCOLR_RED_Pos (16U)
8068#define DMA2D_BGCOLR_RED_Msk (0xFFU << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
8069#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */
8070
8071/******************** Bit definition for DMA2D_FGCMAR register **************/
8072
8073#define DMA2D_FGCMAR_MA_Pos (0U)
8074#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
8075#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */
8076
8077/******************** Bit definition for DMA2D_BGCMAR register **************/
8078
8079#define DMA2D_BGCMAR_MA_Pos (0U)
8080#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
8081#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */
8082
8083/******************** Bit definition for DMA2D_OPFCCR register **************/
8084
8085#define DMA2D_OPFCCR_CM_Pos (0U)
8086#define DMA2D_OPFCCR_CM_Msk (0x7U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
8087#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */
8088#define DMA2D_OPFCCR_CM_0 (0x1U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
8089#define DMA2D_OPFCCR_CM_1 (0x2U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
8090#define DMA2D_OPFCCR_CM_2 (0x4U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
8091#define DMA2D_OPFCCR_SB_Pos (8U)
8092#define DMA2D_OPFCCR_SB_Msk (0x1U << DMA2D_OPFCCR_SB_Pos) /*!< 0x00000100 */
8093#define DMA2D_OPFCCR_SB DMA2D_OPFCCR_SB_Msk /*!< Swap Bytes */
8094#define DMA2D_OPFCCR_AI_Pos (20U)
8095#define DMA2D_OPFCCR_AI_Msk (0x1U << DMA2D_OPFCCR_AI_Pos) /*!< 0x00100000 */
8096#define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk /*!< Alpha Inverted */
8097#define DMA2D_OPFCCR_RBS_Pos (21U)
8098#define DMA2D_OPFCCR_RBS_Msk (0x1U << DMA2D_OPFCCR_RBS_Pos) /*!< 0x00200000 */
8099#define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk /*!< Red Blue Swap */
8100
8101/******************** Bit definition for DMA2D_OCOLR register ***************/
8102
8103/*!<Mode_ARGB8888/RGB888 */
8104
8105#define DMA2D_OCOLR_BLUE_1 (0x000000FFU) /*!< Blue Value */
8106#define DMA2D_OCOLR_GREEN_1 (0x0000FF00U) /*!< Green Value */
8107#define DMA2D_OCOLR_RED_1 (0x00FF0000U) /*!< Red Value */
8108#define DMA2D_OCOLR_ALPHA_1 (0xFF000000U) /*!< Alpha Channel Value */
8109
8110/*!<Mode_RGB565 */
8111#define DMA2D_OCOLR_BLUE_2 (0x0000001FU) /*!< Blue Value */
8112#define DMA2D_OCOLR_GREEN_2 (0x000007E0U) /*!< Green Value */
8113#define DMA2D_OCOLR_RED_2 (0x0000F800U) /*!< Red Value */
8114
8115/*!<Mode_ARGB1555 */
8116#define DMA2D_OCOLR_BLUE_3 (0x0000001FU) /*!< Blue Value */
8117#define DMA2D_OCOLR_GREEN_3 (0x000003E0U) /*!< Green Value */
8118#define DMA2D_OCOLR_RED_3 (0x00007C00U) /*!< Red Value */
8119#define DMA2D_OCOLR_ALPHA_3 (0x00008000U) /*!< Alpha Channel Value */
8120
8121/*!<Mode_ARGB4444 */
8122#define DMA2D_OCOLR_BLUE_4 (0x0000000FU) /*!< Blue Value */
8123#define DMA2D_OCOLR_GREEN_4 (0x000000F0U) /*!< Green Value */
8124#define DMA2D_OCOLR_RED_4 (0x00000F00U) /*!< Red Value */
8125#define DMA2D_OCOLR_ALPHA_4 (0x0000F000U) /*!< Alpha Channel Value */
8126
8127/******************** Bit definition for DMA2D_OMAR register ****************/
8128
8129#define DMA2D_OMAR_MA_Pos (0U)
8130#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
8131#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */
8132
8133/******************** Bit definition for DMA2D_OOR register *****************/
8134
8135#define DMA2D_OOR_LO_Pos (0U)
8136#define DMA2D_OOR_LO_Msk (0xFFFFU << DMA2D_OOR_LO_Pos) /*!< 0x0000FFFF */
8137#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */
8138
8139/******************** Bit definition for DMA2D_NLR register *****************/
8140
8141#define DMA2D_NLR_NL_Pos (0U)
8142#define DMA2D_NLR_NL_Msk (0xFFFFU << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
8143#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
8144#define DMA2D_NLR_PL_Pos (16U)
8145#define DMA2D_NLR_PL_Msk (0x3FFFU << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
8146#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
8147
8148/******************** Bit definition for DMA2D_LWR register *****************/
8149
8150#define DMA2D_LWR_LW_Pos (0U)
8151#define DMA2D_LWR_LW_Msk (0xFFFFU << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
8152#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
8153
8154/******************** Bit definition for DMA2D_AMTCR register ***************/
8155
8156#define DMA2D_AMTCR_EN_Pos (0U)
8157#define DMA2D_AMTCR_EN_Msk (0x1U << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
8158#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
8159#define DMA2D_AMTCR_DT_Pos (8U)
8160#define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
8161#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
8162
8163/******************** Bit definition for DMA2D_FGCLUT register **************/
8164
8165/******************** Bit definition for DMA2D_BGCLUT register **************/
8166
8167/******************************************************************************/
8168/* */
8169/* External Interrupt/Event Controller */
8170/* */
8171/******************************************************************************/
8172/******************* Bit definition for EXTI_IMR1 register ******************/
8173#define EXTI_IMR1_IM0_Pos (0U)
8174#define EXTI_IMR1_IM0_Msk (0x1U << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
8175#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
8176#define EXTI_IMR1_IM1_Pos (1U)
8177#define EXTI_IMR1_IM1_Msk (0x1U << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
8178#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
8179#define EXTI_IMR1_IM2_Pos (2U)
8180#define EXTI_IMR1_IM2_Msk (0x1U << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
8181#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
8182#define EXTI_IMR1_IM3_Pos (3U)
8183#define EXTI_IMR1_IM3_Msk (0x1U << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
8184#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
8185#define EXTI_IMR1_IM4_Pos (4U)
8186#define EXTI_IMR1_IM4_Msk (0x1U << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
8187#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
8188#define EXTI_IMR1_IM5_Pos (5U)
8189#define EXTI_IMR1_IM5_Msk (0x1U << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
8190#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
8191#define EXTI_IMR1_IM6_Pos (6U)
8192#define EXTI_IMR1_IM6_Msk (0x1U << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
8193#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
8194#define EXTI_IMR1_IM7_Pos (7U)
8195#define EXTI_IMR1_IM7_Msk (0x1U << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
8196#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
8197#define EXTI_IMR1_IM8_Pos (8U)
8198#define EXTI_IMR1_IM8_Msk (0x1U << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
8199#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
8200#define EXTI_IMR1_IM9_Pos (9U)
8201#define EXTI_IMR1_IM9_Msk (0x1U << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
8202#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
8203#define EXTI_IMR1_IM10_Pos (10U)
8204#define EXTI_IMR1_IM10_Msk (0x1U << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
8205#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
8206#define EXTI_IMR1_IM11_Pos (11U)
8207#define EXTI_IMR1_IM11_Msk (0x1U << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
8208#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
8209#define EXTI_IMR1_IM12_Pos (12U)
8210#define EXTI_IMR1_IM12_Msk (0x1U << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
8211#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
8212#define EXTI_IMR1_IM13_Pos (13U)
8213#define EXTI_IMR1_IM13_Msk (0x1U << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
8214#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
8215#define EXTI_IMR1_IM14_Pos (14U)
8216#define EXTI_IMR1_IM14_Msk (0x1U << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
8217#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
8218#define EXTI_IMR1_IM15_Pos (15U)
8219#define EXTI_IMR1_IM15_Msk (0x1U << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
8220#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
8221#define EXTI_IMR1_IM16_Pos (16U)
8222#define EXTI_IMR1_IM16_Msk (0x1U << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
8223#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
8224#define EXTI_IMR1_IM17_Pos (17U)
8225#define EXTI_IMR1_IM17_Msk (0x1U << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
8226#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
8227#define EXTI_IMR1_IM18_Pos (18U)
8228#define EXTI_IMR1_IM18_Msk (0x1U << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
8229#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
8230#define EXTI_IMR1_IM19_Pos (19U)
8231#define EXTI_IMR1_IM19_Msk (0x1U << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
8232#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
8233#define EXTI_IMR1_IM20_Pos (20U)
8234#define EXTI_IMR1_IM20_Msk (0x1U << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
8235#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
8236#define EXTI_IMR1_IM21_Pos (21U)
8237#define EXTI_IMR1_IM21_Msk (0x1U << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
8238#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
8239#define EXTI_IMR1_IM22_Pos (22U)
8240#define EXTI_IMR1_IM22_Msk (0x1U << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
8241#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
8242#define EXTI_IMR1_IM23_Pos (23U)
8243#define EXTI_IMR1_IM23_Msk (0x1U << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
8244#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
8245#define EXTI_IMR1_IM24_Pos (24U)
8246#define EXTI_IMR1_IM24_Msk (0x1U << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
8247#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
8248#define EXTI_IMR1_IM25_Pos (25U)
8249#define EXTI_IMR1_IM25_Msk (0x1U << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
8250#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
8251#define EXTI_IMR1_IM26_Pos (26U)
8252#define EXTI_IMR1_IM26_Msk (0x1U << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
8253#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
8254#define EXTI_IMR1_IM27_Pos (27U)
8255#define EXTI_IMR1_IM27_Msk (0x1U << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
8256#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
8257#define EXTI_IMR1_IM28_Pos (28U)
8258#define EXTI_IMR1_IM28_Msk (0x1U << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
8259#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
8260#define EXTI_IMR1_IM29_Pos (29U)
8261#define EXTI_IMR1_IM29_Msk (0x1U << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
8262#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
8263#define EXTI_IMR1_IM30_Pos (30U)
8264#define EXTI_IMR1_IM30_Msk (0x1U << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
8265#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
8266#define EXTI_IMR1_IM31_Pos (31U)
8267#define EXTI_IMR1_IM31_Msk (0x1U << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
8268#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
8269#define EXTI_IMR1_IM_Pos (0U)
8270#define EXTI_IMR1_IM_Msk (0x9FFFFFFFU << EXTI_IMR1_IM_Pos) /*!< 0x9FFFFFFF */
8271#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
8272
8273/******************* Bit definition for EXTI_EMR1 register ******************/
8274#define EXTI_EMR1_EM0_Pos (0U)
8275#define EXTI_EMR1_EM0_Msk (0x1U << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
8276#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
8277#define EXTI_EMR1_EM1_Pos (1U)
8278#define EXTI_EMR1_EM1_Msk (0x1U << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
8279#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
8280#define EXTI_EMR1_EM2_Pos (2U)
8281#define EXTI_EMR1_EM2_Msk (0x1U << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
8282#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
8283#define EXTI_EMR1_EM3_Pos (3U)
8284#define EXTI_EMR1_EM3_Msk (0x1U << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
8285#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
8286#define EXTI_EMR1_EM4_Pos (4U)
8287#define EXTI_EMR1_EM4_Msk (0x1U << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
8288#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
8289#define EXTI_EMR1_EM5_Pos (5U)
8290#define EXTI_EMR1_EM5_Msk (0x1U << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
8291#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
8292#define EXTI_EMR1_EM6_Pos (6U)
8293#define EXTI_EMR1_EM6_Msk (0x1U << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
8294#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
8295#define EXTI_EMR1_EM7_Pos (7U)
8296#define EXTI_EMR1_EM7_Msk (0x1U << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
8297#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
8298#define EXTI_EMR1_EM8_Pos (8U)
8299#define EXTI_EMR1_EM8_Msk (0x1U << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
8300#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
8301#define EXTI_EMR1_EM9_Pos (9U)
8302#define EXTI_EMR1_EM9_Msk (0x1U << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
8303#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
8304#define EXTI_EMR1_EM10_Pos (10U)
8305#define EXTI_EMR1_EM10_Msk (0x1U << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
8306#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
8307#define EXTI_EMR1_EM11_Pos (11U)
8308#define EXTI_EMR1_EM11_Msk (0x1U << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
8309#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
8310#define EXTI_EMR1_EM12_Pos (12U)
8311#define EXTI_EMR1_EM12_Msk (0x1U << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
8312#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
8313#define EXTI_EMR1_EM13_Pos (13U)
8314#define EXTI_EMR1_EM13_Msk (0x1U << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
8315#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
8316#define EXTI_EMR1_EM14_Pos (14U)
8317#define EXTI_EMR1_EM14_Msk (0x1U << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
8318#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
8319#define EXTI_EMR1_EM15_Pos (15U)
8320#define EXTI_EMR1_EM15_Msk (0x1U << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
8321#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
8322#define EXTI_EMR1_EM16_Pos (16U)
8323#define EXTI_EMR1_EM16_Msk (0x1U << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
8324#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
8325#define EXTI_EMR1_EM17_Pos (17U)
8326#define EXTI_EMR1_EM17_Msk (0x1U << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
8327#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
8328#define EXTI_EMR1_EM18_Pos (18U)
8329#define EXTI_EMR1_EM18_Msk (0x1U << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
8330#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
8331#define EXTI_EMR1_EM19_Pos (19U)
8332#define EXTI_EMR1_EM19_Msk (0x1U << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
8333#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
8334#define EXTI_EMR1_EM20_Pos (20U)
8335#define EXTI_EMR1_EM20_Msk (0x1U << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
8336#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
8337#define EXTI_EMR1_EM21_Pos (21U)
8338#define EXTI_EMR1_EM21_Msk (0x1U << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
8339#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
8340#define EXTI_EMR1_EM22_Pos (22U)
8341#define EXTI_EMR1_EM22_Msk (0x1U << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
8342#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
8343#define EXTI_EMR1_EM23_Pos (23U)
8344#define EXTI_EMR1_EM23_Msk (0x1U << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
8345#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
8346#define EXTI_EMR1_EM24_Pos (24U)
8347#define EXTI_EMR1_EM24_Msk (0x1U << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
8348#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
8349#define EXTI_EMR1_EM25_Pos (25U)
8350#define EXTI_EMR1_EM25_Msk (0x1U << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
8351#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
8352#define EXTI_EMR1_EM26_Pos (26U)
8353#define EXTI_EMR1_EM26_Msk (0x1U << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
8354#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
8355#define EXTI_EMR1_EM27_Pos (27U)
8356#define EXTI_EMR1_EM27_Msk (0x1U << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
8357#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
8358#define EXTI_EMR1_EM28_Pos (28U)
8359#define EXTI_EMR1_EM28_Msk (0x1U << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
8360#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
8361#define EXTI_EMR1_EM29_Pos (29U)
8362#define EXTI_EMR1_EM29_Msk (0x1U << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
8363#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
8364#define EXTI_EMR1_EM30_Pos (30U)
8365#define EXTI_EMR1_EM30_Msk (0x1U << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
8366#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
8367#define EXTI_EMR1_EM31_Pos (31U)
8368#define EXTI_EMR1_EM31_Msk (0x1U << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
8369#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
8370
8371/****************** Bit definition for EXTI_RTSR1 register ******************/
8372#define EXTI_RTSR1_RT0_Pos (0U)
8373#define EXTI_RTSR1_RT0_Msk (0x1U << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
8374#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
8375#define EXTI_RTSR1_RT1_Pos (1U)
8376#define EXTI_RTSR1_RT1_Msk (0x1U << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
8377#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
8378#define EXTI_RTSR1_RT2_Pos (2U)
8379#define EXTI_RTSR1_RT2_Msk (0x1U << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
8380#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
8381#define EXTI_RTSR1_RT3_Pos (3U)
8382#define EXTI_RTSR1_RT3_Msk (0x1U << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
8383#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
8384#define EXTI_RTSR1_RT4_Pos (4U)
8385#define EXTI_RTSR1_RT4_Msk (0x1U << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
8386#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
8387#define EXTI_RTSR1_RT5_Pos (5U)
8388#define EXTI_RTSR1_RT5_Msk (0x1U << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
8389#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
8390#define EXTI_RTSR1_RT6_Pos (6U)
8391#define EXTI_RTSR1_RT6_Msk (0x1U << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
8392#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
8393#define EXTI_RTSR1_RT7_Pos (7U)
8394#define EXTI_RTSR1_RT7_Msk (0x1U << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
8395#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
8396#define EXTI_RTSR1_RT8_Pos (8U)
8397#define EXTI_RTSR1_RT8_Msk (0x1U << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
8398#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
8399#define EXTI_RTSR1_RT9_Pos (9U)
8400#define EXTI_RTSR1_RT9_Msk (0x1U << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
8401#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
8402#define EXTI_RTSR1_RT10_Pos (10U)
8403#define EXTI_RTSR1_RT10_Msk (0x1U << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
8404#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
8405#define EXTI_RTSR1_RT11_Pos (11U)
8406#define EXTI_RTSR1_RT11_Msk (0x1U << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
8407#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
8408#define EXTI_RTSR1_RT12_Pos (12U)
8409#define EXTI_RTSR1_RT12_Msk (0x1U << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
8410#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
8411#define EXTI_RTSR1_RT13_Pos (13U)
8412#define EXTI_RTSR1_RT13_Msk (0x1U << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
8413#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
8414#define EXTI_RTSR1_RT14_Pos (14U)
8415#define EXTI_RTSR1_RT14_Msk (0x1U << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
8416#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
8417#define EXTI_RTSR1_RT15_Pos (15U)
8418#define EXTI_RTSR1_RT15_Msk (0x1U << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
8419#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
8420#define EXTI_RTSR1_RT16_Pos (16U)
8421#define EXTI_RTSR1_RT16_Msk (0x1U << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
8422#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
8423#define EXTI_RTSR1_RT18_Pos (18U)
8424#define EXTI_RTSR1_RT18_Msk (0x1U << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */
8425#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */
8426#define EXTI_RTSR1_RT19_Pos (19U)
8427#define EXTI_RTSR1_RT19_Msk (0x1U << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */
8428#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
8429#define EXTI_RTSR1_RT20_Pos (20U)
8430#define EXTI_RTSR1_RT20_Msk (0x1U << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */
8431#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
8432#define EXTI_RTSR1_RT21_Pos (21U)
8433#define EXTI_RTSR1_RT21_Msk (0x1U << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
8434#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
8435#define EXTI_RTSR1_RT22_Pos (22U)
8436#define EXTI_RTSR1_RT22_Msk (0x1U << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */
8437#define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
8438
8439/****************** Bit definition for EXTI_FTSR1 register ******************/
8440#define EXTI_FTSR1_FT0_Pos (0U)
8441#define EXTI_FTSR1_FT0_Msk (0x1U << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
8442#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
8443#define EXTI_FTSR1_FT1_Pos (1U)
8444#define EXTI_FTSR1_FT1_Msk (0x1U << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
8445#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
8446#define EXTI_FTSR1_FT2_Pos (2U)
8447#define EXTI_FTSR1_FT2_Msk (0x1U << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
8448#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
8449#define EXTI_FTSR1_FT3_Pos (3U)
8450#define EXTI_FTSR1_FT3_Msk (0x1U << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
8451#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
8452#define EXTI_FTSR1_FT4_Pos (4U)
8453#define EXTI_FTSR1_FT4_Msk (0x1U << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
8454#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
8455#define EXTI_FTSR1_FT5_Pos (5U)
8456#define EXTI_FTSR1_FT5_Msk (0x1U << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
8457#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
8458#define EXTI_FTSR1_FT6_Pos (6U)
8459#define EXTI_FTSR1_FT6_Msk (0x1U << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
8460#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
8461#define EXTI_FTSR1_FT7_Pos (7U)
8462#define EXTI_FTSR1_FT7_Msk (0x1U << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
8463#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
8464#define EXTI_FTSR1_FT8_Pos (8U)
8465#define EXTI_FTSR1_FT8_Msk (0x1U << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
8466#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
8467#define EXTI_FTSR1_FT9_Pos (9U)
8468#define EXTI_FTSR1_FT9_Msk (0x1U << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
8469#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
8470#define EXTI_FTSR1_FT10_Pos (10U)
8471#define EXTI_FTSR1_FT10_Msk (0x1U << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
8472#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
8473#define EXTI_FTSR1_FT11_Pos (11U)
8474#define EXTI_FTSR1_FT11_Msk (0x1U << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
8475#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
8476#define EXTI_FTSR1_FT12_Pos (12U)
8477#define EXTI_FTSR1_FT12_Msk (0x1U << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
8478#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
8479#define EXTI_FTSR1_FT13_Pos (13U)
8480#define EXTI_FTSR1_FT13_Msk (0x1U << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
8481#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
8482#define EXTI_FTSR1_FT14_Pos (14U)
8483#define EXTI_FTSR1_FT14_Msk (0x1U << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
8484#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
8485#define EXTI_FTSR1_FT15_Pos (15U)
8486#define EXTI_FTSR1_FT15_Msk (0x1U << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
8487#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
8488#define EXTI_FTSR1_FT16_Pos (16U)
8489#define EXTI_FTSR1_FT16_Msk (0x1U << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
8490#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
8491#define EXTI_FTSR1_FT18_Pos (18U)
8492#define EXTI_FTSR1_FT18_Msk (0x1U << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */
8493#define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger event configuration bit of line 18 */
8494#define EXTI_FTSR1_FT19_Pos (19U)
8495#define EXTI_FTSR1_FT19_Msk (0x1U << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */
8496#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
8497#define EXTI_FTSR1_FT20_Pos (20U)
8498#define EXTI_FTSR1_FT20_Msk (0x1U << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */
8499#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
8500#define EXTI_FTSR1_FT21_Pos (21U)
8501#define EXTI_FTSR1_FT21_Msk (0x1U << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
8502#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
8503#define EXTI_FTSR1_FT22_Pos (22U)
8504#define EXTI_FTSR1_FT22_Msk (0x1U << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */
8505#define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
8506
8507/****************** Bit definition for EXTI_SWIER1 register *****************/
8508#define EXTI_SWIER1_SWI0_Pos (0U)
8509#define EXTI_SWIER1_SWI0_Msk (0x1U << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
8510#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
8511#define EXTI_SWIER1_SWI1_Pos (1U)
8512#define EXTI_SWIER1_SWI1_Msk (0x1U << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
8513#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
8514#define EXTI_SWIER1_SWI2_Pos (2U)
8515#define EXTI_SWIER1_SWI2_Msk (0x1U << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
8516#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
8517#define EXTI_SWIER1_SWI3_Pos (3U)
8518#define EXTI_SWIER1_SWI3_Msk (0x1U << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
8519#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
8520#define EXTI_SWIER1_SWI4_Pos (4U)
8521#define EXTI_SWIER1_SWI4_Msk (0x1U << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
8522#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
8523#define EXTI_SWIER1_SWI5_Pos (5U)
8524#define EXTI_SWIER1_SWI5_Msk (0x1U << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
8525#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
8526#define EXTI_SWIER1_SWI6_Pos (6U)
8527#define EXTI_SWIER1_SWI6_Msk (0x1U << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
8528#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
8529#define EXTI_SWIER1_SWI7_Pos (7U)
8530#define EXTI_SWIER1_SWI7_Msk (0x1U << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
8531#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
8532#define EXTI_SWIER1_SWI8_Pos (8U)
8533#define EXTI_SWIER1_SWI8_Msk (0x1U << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
8534#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
8535#define EXTI_SWIER1_SWI9_Pos (9U)
8536#define EXTI_SWIER1_SWI9_Msk (0x1U << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
8537#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
8538#define EXTI_SWIER1_SWI10_Pos (10U)
8539#define EXTI_SWIER1_SWI10_Msk (0x1U << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
8540#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
8541#define EXTI_SWIER1_SWI11_Pos (11U)
8542#define EXTI_SWIER1_SWI11_Msk (0x1U << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
8543#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
8544#define EXTI_SWIER1_SWI12_Pos (12U)
8545#define EXTI_SWIER1_SWI12_Msk (0x1U << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
8546#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
8547#define EXTI_SWIER1_SWI13_Pos (13U)
8548#define EXTI_SWIER1_SWI13_Msk (0x1U << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
8549#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
8550#define EXTI_SWIER1_SWI14_Pos (14U)
8551#define EXTI_SWIER1_SWI14_Msk (0x1U << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
8552#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
8553#define EXTI_SWIER1_SWI15_Pos (15U)
8554#define EXTI_SWIER1_SWI15_Msk (0x1U << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
8555#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
8556#define EXTI_SWIER1_SWI16_Pos (16U)
8557#define EXTI_SWIER1_SWI16_Msk (0x1U << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
8558#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
8559#define EXTI_SWIER1_SWI18_Pos (18U)
8560#define EXTI_SWIER1_SWI18_Msk (0x1U << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */
8561#define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */
8562#define EXTI_SWIER1_SWI19_Pos (19U)
8563#define EXTI_SWIER1_SWI19_Msk (0x1U << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */
8564#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */
8565#define EXTI_SWIER1_SWI20_Pos (20U)
8566#define EXTI_SWIER1_SWI20_Msk (0x1U << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */
8567#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */
8568#define EXTI_SWIER1_SWI21_Pos (21U)
8569#define EXTI_SWIER1_SWI21_Msk (0x1U << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
8570#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
8571#define EXTI_SWIER1_SWI22_Pos (22U)
8572#define EXTI_SWIER1_SWI22_Msk (0x1U << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */
8573#define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */
8574
8575/******************* Bit definition for EXTI_PR1 register *******************/
8576#define EXTI_PR1_PIF0_Pos (0U)
8577#define EXTI_PR1_PIF0_Msk (0x1U << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */
8578#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */
8579#define EXTI_PR1_PIF1_Pos (1U)
8580#define EXTI_PR1_PIF1_Msk (0x1U << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */
8581#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */
8582#define EXTI_PR1_PIF2_Pos (2U)
8583#define EXTI_PR1_PIF2_Msk (0x1U << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */
8584#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */
8585#define EXTI_PR1_PIF3_Pos (3U)
8586#define EXTI_PR1_PIF3_Msk (0x1U << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */
8587#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */
8588#define EXTI_PR1_PIF4_Pos (4U)
8589#define EXTI_PR1_PIF4_Msk (0x1U << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */
8590#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */
8591#define EXTI_PR1_PIF5_Pos (5U)
8592#define EXTI_PR1_PIF5_Msk (0x1U << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */
8593#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */
8594#define EXTI_PR1_PIF6_Pos (6U)
8595#define EXTI_PR1_PIF6_Msk (0x1U << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */
8596#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */
8597#define EXTI_PR1_PIF7_Pos (7U)
8598#define EXTI_PR1_PIF7_Msk (0x1U << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */
8599#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */
8600#define EXTI_PR1_PIF8_Pos (8U)
8601#define EXTI_PR1_PIF8_Msk (0x1U << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */
8602#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */
8603#define EXTI_PR1_PIF9_Pos (9U)
8604#define EXTI_PR1_PIF9_Msk (0x1U << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */
8605#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */
8606#define EXTI_PR1_PIF10_Pos (10U)
8607#define EXTI_PR1_PIF10_Msk (0x1U << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */
8608#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */
8609#define EXTI_PR1_PIF11_Pos (11U)
8610#define EXTI_PR1_PIF11_Msk (0x1U << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */
8611#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */
8612#define EXTI_PR1_PIF12_Pos (12U)
8613#define EXTI_PR1_PIF12_Msk (0x1U << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */
8614#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */
8615#define EXTI_PR1_PIF13_Pos (13U)
8616#define EXTI_PR1_PIF13_Msk (0x1U << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */
8617#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */
8618#define EXTI_PR1_PIF14_Pos (14U)
8619#define EXTI_PR1_PIF14_Msk (0x1U << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */
8620#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */
8621#define EXTI_PR1_PIF15_Pos (15U)
8622#define EXTI_PR1_PIF15_Msk (0x1U << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */
8623#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */
8624#define EXTI_PR1_PIF16_Pos (16U)
8625#define EXTI_PR1_PIF16_Msk (0x1U << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */
8626#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */
8627#define EXTI_PR1_PIF18_Pos (18U)
8628#define EXTI_PR1_PIF18_Msk (0x1U << EXTI_PR1_PIF18_Pos) /*!< 0x00040000 */
8629#define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk /*!< Pending bit for line 18 */
8630#define EXTI_PR1_PIF19_Pos (19U)
8631#define EXTI_PR1_PIF19_Msk (0x1U << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */
8632#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */
8633#define EXTI_PR1_PIF20_Pos (20U)
8634#define EXTI_PR1_PIF20_Msk (0x1U << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */
8635#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */
8636#define EXTI_PR1_PIF21_Pos (21U)
8637#define EXTI_PR1_PIF21_Msk (0x1U << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */
8638#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */
8639#define EXTI_PR1_PIF22_Pos (22U)
8640#define EXTI_PR1_PIF22_Msk (0x1U << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */
8641#define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */
8642
8643/******************* Bit definition for EXTI_IMR2 register ******************/
8644#define EXTI_IMR2_IM32_Pos (0U)
8645#define EXTI_IMR2_IM32_Msk (0x1U << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
8646#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
8647#define EXTI_IMR2_IM33_Pos (1U)
8648#define EXTI_IMR2_IM33_Msk (0x1U << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
8649#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
8650#define EXTI_IMR2_IM35_Pos (3U)
8651#define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
8652#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
8653#define EXTI_IMR2_IM36_Pos (4U)
8654#define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
8655#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
8656#define EXTI_IMR2_IM37_Pos (5U)
8657#define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
8658#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
8659#define EXTI_IMR2_IM38_Pos (6U)
8660#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
8661#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
8662#define EXTI_IMR2_IM40_Pos (8U)
8663#define EXTI_IMR2_IM40_Msk (0x1U << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
8664#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
8665#define EXTI_IMR2_IM_Pos (0U)
8666#define EXTI_IMR2_IM_Msk (0x17BU << EXTI_IMR2_IM_Pos) /*!< 0x0000017B */
8667#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
8668
8669/******************* Bit definition for EXTI_EMR2 register ******************/
8670#define EXTI_EMR2_EM32_Pos (0U)
8671#define EXTI_EMR2_EM32_Msk (0x1U << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
8672#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32 */
8673#define EXTI_EMR2_EM33_Pos (1U)
8674#define EXTI_EMR2_EM33_Msk (0x1U << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
8675#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
8676#define EXTI_EMR2_EM35_Pos (3U)
8677#define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
8678#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
8679#define EXTI_EMR2_EM36_Pos (4U)
8680#define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
8681#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
8682#define EXTI_EMR2_EM37_Pos (5U)
8683#define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
8684#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
8685#define EXTI_EMR2_EM38_Pos (6U)
8686#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
8687#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
8688#define EXTI_EMR2_EM40_Pos (8U)
8689#define EXTI_EMR2_EM40_Msk (0x1U << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
8690#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
8691#define EXTI_EMR2_EM_Pos (0U)
8692#define EXTI_EMR2_EM_Msk (0x17BU << EXTI_EMR2_EM_Pos) /*!< 0x0000017B */
8693#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
8694
8695/****************** Bit definition for EXTI_RTSR2 register ******************/
8696#define EXTI_RTSR2_RT35_Pos (3U)
8697#define EXTI_RTSR2_RT35_Msk (0x1U << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */
8698#define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */
8699#define EXTI_RTSR2_RT36_Pos (4U)
8700#define EXTI_RTSR2_RT36_Msk (0x1U << EXTI_RTSR2_RT36_Pos) /*!< 0x00000010 */
8701#define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk /*!< Rising trigger event configuration bit of line 36 */
8702#define EXTI_RTSR2_RT37_Pos (5U)
8703#define EXTI_RTSR2_RT37_Msk (0x1U << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */
8704#define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger event configuration bit of line 37 */
8705#define EXTI_RTSR2_RT38_Pos (6U)
8706#define EXTI_RTSR2_RT38_Msk (0x1U << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */
8707#define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
8708
8709/****************** Bit definition for EXTI_FTSR2 register ******************/
8710#define EXTI_FTSR2_FT35_Pos (3U)
8711#define EXTI_FTSR2_FT35_Msk (0x1U << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */
8712#define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */
8713#define EXTI_FTSR2_FT36_Pos (4U)
8714#define EXTI_FTSR2_FT36_Msk (0x1U << EXTI_FTSR2_FT36_Pos) /*!< 0x00000010 */
8715#define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk /*!< Falling trigger event configuration bit of line 36 */
8716#define EXTI_FTSR2_FT37_Pos (5U)
8717#define EXTI_FTSR2_FT37_Msk (0x1U << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */
8718#define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger event configuration bit of line 37 */
8719#define EXTI_FTSR2_FT38_Pos (6U)
8720#define EXTI_FTSR2_FT38_Msk (0x1U << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */
8721#define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 38 */
8722
8723/****************** Bit definition for EXTI_SWIER2 register *****************/
8724#define EXTI_SWIER2_SWI35_Pos (3U)
8725#define EXTI_SWIER2_SWI35_Msk (0x1U << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */
8726#define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */
8727#define EXTI_SWIER2_SWI36_Pos (4U)
8728#define EXTI_SWIER2_SWI36_Msk (0x1U << EXTI_SWIER2_SWI36_Pos) /*!< 0x00000010 */
8729#define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk /*!< Software Interrupt on line 36 */
8730#define EXTI_SWIER2_SWI37_Pos (5U)
8731#define EXTI_SWIER2_SWI37_Msk (0x1U << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */
8732#define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */
8733#define EXTI_SWIER2_SWI38_Pos (6U)
8734#define EXTI_SWIER2_SWI38_Msk (0x1U << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */
8735#define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
8736
8737/******************* Bit definition for EXTI_PR2 register *******************/
8738#define EXTI_PR2_PIF35_Pos (3U)
8739#define EXTI_PR2_PIF35_Msk (0x1U << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */
8740#define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */
8741#define EXTI_PR2_PIF36_Pos (4U)
8742#define EXTI_PR2_PIF36_Msk (0x1U << EXTI_PR2_PIF36_Pos) /*!< 0x00000010 */
8743#define EXTI_PR2_PIF36 EXTI_PR2_PIF36_Msk /*!< Pending bit for line 36 */
8744#define EXTI_PR2_PIF37_Pos (5U)
8745#define EXTI_PR2_PIF37_Msk (0x1U << EXTI_PR2_PIF37_Pos) /*!< 0x00000020 */
8746#define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk /*!< Pending bit for line 37 */
8747#define EXTI_PR2_PIF38_Pos (6U)
8748#define EXTI_PR2_PIF38_Msk (0x1U << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */
8749#define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */
8750
8751
8752/******************************************************************************/
8753/* */
8754/* FLASH */
8755/* */
8756/******************************************************************************/
8757/******************* Bits definition for FLASH_ACR register *****************/
8758#define FLASH_ACR_LATENCY_Pos (0U)
8759#define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
8760#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
8761#define FLASH_ACR_LATENCY_0WS (0x00000000U)
8762#define FLASH_ACR_LATENCY_1WS (0x00000001U)
8763#define FLASH_ACR_LATENCY_2WS (0x00000002U)
8764#define FLASH_ACR_LATENCY_3WS (0x00000003U)
8765#define FLASH_ACR_LATENCY_4WS (0x00000004U)
8766#define FLASH_ACR_LATENCY_5WS (0x00000005U)
8767#define FLASH_ACR_LATENCY_6WS (0x00000006U)
8768#define FLASH_ACR_LATENCY_7WS (0x00000007U)
8769#define FLASH_ACR_LATENCY_8WS (0x00000008U)
8770#define FLASH_ACR_LATENCY_9WS (0x00000009U)
8771#define FLASH_ACR_LATENCY_10WS (0x0000000AU)
8772#define FLASH_ACR_LATENCY_11WS (0x0000000BU)
8773#define FLASH_ACR_LATENCY_12WS (0x0000000CU)
8774#define FLASH_ACR_LATENCY_13WS (0x0000000DU)
8775#define FLASH_ACR_LATENCY_14WS (0x0000000EU)
8776#define FLASH_ACR_LATENCY_15WS (0x0000000FU)
8777#define FLASH_ACR_PRFTEN_Pos (8U)
8778#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
8779#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
8780#define FLASH_ACR_ICEN_Pos (9U)
8781#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
8782#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
8783#define FLASH_ACR_DCEN_Pos (10U)
8784#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
8785#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
8786#define FLASH_ACR_ICRST_Pos (11U)
8787#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
8788#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
8789#define FLASH_ACR_DCRST_Pos (12U)
8790#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
8791#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
8792#define FLASH_ACR_RUN_PD_Pos (13U)
8793#define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */
8794#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */
8795#define FLASH_ACR_SLEEP_PD_Pos (14U)
8796#define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
8797#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */
8798
8799/******************* Bits definition for FLASH_SR register ******************/
8800#define FLASH_SR_EOP_Pos (0U)
8801#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
8802#define FLASH_SR_EOP FLASH_SR_EOP_Msk
8803#define FLASH_SR_OPERR_Pos (1U)
8804#define FLASH_SR_OPERR_Msk (0x1U << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
8805#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
8806#define FLASH_SR_PROGERR_Pos (3U)
8807#define FLASH_SR_PROGERR_Msk (0x1U << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
8808#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
8809#define FLASH_SR_WRPERR_Pos (4U)
8810#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
8811#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
8812#define FLASH_SR_PGAERR_Pos (5U)
8813#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
8814#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
8815#define FLASH_SR_SIZERR_Pos (6U)
8816#define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
8817#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
8818#define FLASH_SR_PGSERR_Pos (7U)
8819#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
8820#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
8821#define FLASH_SR_MISERR_Pos (8U)
8822#define FLASH_SR_MISERR_Msk (0x1U << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
8823#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
8824#define FLASH_SR_FASTERR_Pos (9U)
8825#define FLASH_SR_FASTERR_Msk (0x1U << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
8826#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
8827#define FLASH_SR_RDERR_Pos (14U)
8828#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
8829#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
8830#define FLASH_SR_OPTVERR_Pos (15U)
8831#define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
8832#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
8833#define FLASH_SR_BSY_Pos (16U)
8834#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
8835#define FLASH_SR_BSY FLASH_SR_BSY_Msk
8836#define FLASH_SR_PEMPTY_Pos (17U)
8837#define FLASH_SR_PEMPTY_Msk (0x1U << FLASH_SR_PEMPTY_Pos) /*!< 0x00020000 */
8838#define FLASH_SR_PEMPTY FLASH_SR_PEMPTY_Msk
8839
8840/******************* Bits definition for FLASH_CR register ******************/
8841#define FLASH_CR_PG_Pos (0U)
8842#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
8843#define FLASH_CR_PG FLASH_CR_PG_Msk
8844#define FLASH_CR_PER_Pos (1U)
8845#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
8846#define FLASH_CR_PER FLASH_CR_PER_Msk
8847#define FLASH_CR_MER1_Pos (2U)
8848#define FLASH_CR_MER1_Msk (0x1U << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
8849#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
8850#define FLASH_CR_PNB_Pos (3U)
8851#define FLASH_CR_PNB_Msk (0xFFU << FLASH_CR_PNB_Pos) /*!< 0x000007F8 */
8852#define FLASH_CR_PNB FLASH_CR_PNB_Msk
8853#define FLASH_CR_BKER_Pos (11U)
8854#define FLASH_CR_BKER_Msk (0x1U << FLASH_CR_BKER_Pos) /*!< 0x00000800 */
8855#define FLASH_CR_BKER FLASH_CR_BKER_Msk
8856#define FLASH_CR_MER2_Pos (15U)
8857#define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
8858#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
8859#define FLASH_CR_STRT_Pos (16U)
8860#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
8861#define FLASH_CR_STRT FLASH_CR_STRT_Msk
8862#define FLASH_CR_OPTSTRT_Pos (17U)
8863#define FLASH_CR_OPTSTRT_Msk (0x1U << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
8864#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
8865#define FLASH_CR_FSTPG_Pos (18U)
8866#define FLASH_CR_FSTPG_Msk (0x1U << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
8867#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
8868#define FLASH_CR_EOPIE_Pos (24U)
8869#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
8870#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
8871#define FLASH_CR_ERRIE_Pos (25U)
8872#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
8873#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
8874#define FLASH_CR_RDERRIE_Pos (26U)
8875#define FLASH_CR_RDERRIE_Msk (0x1U << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
8876#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
8877#define FLASH_CR_OBL_LAUNCH_Pos (27U)
8878#define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
8879#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
8880#define FLASH_CR_OPTLOCK_Pos (30U)
8881#define FLASH_CR_OPTLOCK_Msk (0x1U << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
8882#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
8883#define FLASH_CR_LOCK_Pos (31U)
8884#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
8885#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
8886
8887/******************* Bits definition for FLASH_ECCR register ***************/
8888#define FLASH_ECCR_ADDR_ECC_Pos (0U)
8889#define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFFU << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x000FFFFF */
8890#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
8891#define FLASH_ECCR_BK_ECC_Pos (21U)
8892#define FLASH_ECCR_BK_ECC_Msk (0x1U << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */
8893#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk
8894#define FLASH_ECCR_SYSF_ECC_Pos (22U)
8895#define FLASH_ECCR_SYSF_ECC_Msk (0x1U << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */
8896#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
8897#define FLASH_ECCR_ECCIE_Pos (24U)
8898#define FLASH_ECCR_ECCIE_Msk (0x1U << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
8899#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
8900#define FLASH_ECCR_ECCC2_Pos (28U)
8901#define FLASH_ECCR_ECCC2_Msk (0x1U << FLASH_ECCR_ECCC2_Pos) /*!< 0x10000000 */
8902#define FLASH_ECCR_ECCC2 FLASH_ECCR_ECCC2_Msk
8903#define FLASH_ECCR_ECCD2_Pos (29U)
8904#define FLASH_ECCR_ECCD2_Msk (0x1U << FLASH_ECCR_ECCD2_Pos) /*!< 0x20000000 */
8905#define FLASH_ECCR_ECCD2 FLASH_ECCR_ECCD2_Msk
8906#define FLASH_ECCR_ECCC_Pos (30U)
8907#define FLASH_ECCR_ECCC_Msk (0x1U << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
8908#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
8909#define FLASH_ECCR_ECCD_Pos (31U)
8910#define FLASH_ECCR_ECCD_Msk (0x1U << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
8911#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
8912
8913/******************* Bits definition for FLASH_OPTR register ***************/
8914#define FLASH_OPTR_RDP_Pos (0U)
8915#define FLASH_OPTR_RDP_Msk (0xFFU << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
8916#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
8917#define FLASH_OPTR_BOR_LEV_Pos (8U)
8918#define FLASH_OPTR_BOR_LEV_Msk (0x7U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
8919#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
8920#define FLASH_OPTR_BOR_LEV_0 (0x0U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */
8921#define FLASH_OPTR_BOR_LEV_1 (0x1U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
8922#define FLASH_OPTR_BOR_LEV_2 (0x2U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
8923#define FLASH_OPTR_BOR_LEV_3 (0x3U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */
8924#define FLASH_OPTR_BOR_LEV_4 (0x4U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
8925#define FLASH_OPTR_nRST_STOP_Pos (12U)
8926#define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
8927#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
8928#define FLASH_OPTR_nRST_STDBY_Pos (13U)
8929#define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
8930#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
8931#define FLASH_OPTR_nRST_SHDW_Pos (14U)
8932#define FLASH_OPTR_nRST_SHDW_Msk (0x1U << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
8933#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
8934#define FLASH_OPTR_IWDG_SW_Pos (16U)
8935#define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
8936#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
8937#define FLASH_OPTR_IWDG_STOP_Pos (17U)
8938#define FLASH_OPTR_IWDG_STOP_Msk (0x1U << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
8939#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
8940#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
8941#define FLASH_OPTR_IWDG_STDBY_Msk (0x1U << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
8942#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
8943#define FLASH_OPTR_WWDG_SW_Pos (19U)
8944#define FLASH_OPTR_WWDG_SW_Msk (0x1U << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
8945#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
8946#define FLASH_OPTR_BFB2_Pos (20U)
8947#define FLASH_OPTR_BFB2_Msk (0x1U << FLASH_OPTR_BFB2_Pos) /*!< 0x00100000 */
8948#define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk
8949#define FLASH_OPTR_DB1M_Pos (21U)
8950#define FLASH_OPTR_DB1M_Msk (0x1U << FLASH_OPTR_DB1M_Pos) /*!< 0x00200000 */
8951#define FLASH_OPTR_DB1M FLASH_OPTR_DB1M_Msk
8952#define FLASH_OPTR_DBANK_Pos (22U)
8953#define FLASH_OPTR_DBANK_Msk (0x1U << FLASH_OPTR_DBANK_Pos) /*!< 0x00400000 */
8954#define FLASH_OPTR_DBANK FLASH_OPTR_DBANK_Msk
8955#define FLASH_OPTR_nBOOT1_Pos (23U)
8956#define FLASH_OPTR_nBOOT1_Msk (0x1U << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */
8957#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
8958#define FLASH_OPTR_SRAM2_PE_Pos (24U)
8959#define FLASH_OPTR_SRAM2_PE_Msk (0x1U << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */
8960#define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk
8961#define FLASH_OPTR_SRAM2_RST_Pos (25U)
8962#define FLASH_OPTR_SRAM2_RST_Msk (0x1U << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */
8963#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk
8964#define FLASH_OPTR_nSWBOOT0_Pos (26U)
8965#define FLASH_OPTR_nSWBOOT0_Msk (0x1U << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
8966#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk
8967#define FLASH_OPTR_nBOOT0_Pos (27U)
8968#define FLASH_OPTR_nBOOT0_Msk (0x1U << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */
8969#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
8970
8971/****************** Bits definition for FLASH_PCROP1SR register **********/
8972#define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
8973#define FLASH_PCROP1SR_PCROP1_STRT_Msk (0x1FFFFU << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x0001FFFF */
8974#define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
8975
8976/****************** Bits definition for FLASH_PCROP1ER register ***********/
8977#define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
8978#define FLASH_PCROP1ER_PCROP1_END_Msk (0x1FFFFU << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x0001FFFF */
8979#define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
8980#define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
8981#define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1U << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */
8982#define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
8983
8984/****************** Bits definition for FLASH_WRP1AR register ***************/
8985#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
8986#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFU << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
8987#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
8988#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
8989#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFU << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
8990#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
8991
8992/****************** Bits definition for FLASH_WRPB1R register ***************/
8993#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
8994#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFU << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
8995#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
8996#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
8997#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFU << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
8998#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
8999
9000/****************** Bits definition for FLASH_PCROP2SR register **********/
9001#define FLASH_PCROP2SR_PCROP2_STRT_Pos (0U)
9002#define FLASH_PCROP2SR_PCROP2_STRT_Msk (0x1FFFFU << FLASH_PCROP2SR_PCROP2_STRT_Pos) /*!< 0x0001FFFF */
9003#define FLASH_PCROP2SR_PCROP2_STRT FLASH_PCROP2SR_PCROP2_STRT_Msk
9004
9005/****************** Bits definition for FLASH_PCROP2ER register ***********/
9006#define FLASH_PCROP2ER_PCROP2_END_Pos (0U)
9007#define FLASH_PCROP2ER_PCROP2_END_Msk (0x1FFFFU << FLASH_PCROP2ER_PCROP2_END_Pos) /*!< 0x0001FFFF */
9008#define FLASH_PCROP2ER_PCROP2_END FLASH_PCROP2ER_PCROP2_END_Msk
9009
9010/****************** Bits definition for FLASH_WRP2AR register ***************/
9011#define FLASH_WRP2AR_WRP2A_STRT_Pos (0U)
9012#define FLASH_WRP2AR_WRP2A_STRT_Msk (0xFFU << FLASH_WRP2AR_WRP2A_STRT_Pos) /*!< 0x000000FF */
9013#define FLASH_WRP2AR_WRP2A_STRT FLASH_WRP2AR_WRP2A_STRT_Msk
9014#define FLASH_WRP2AR_WRP2A_END_Pos (16U)
9015#define FLASH_WRP2AR_WRP2A_END_Msk (0xFFU << FLASH_WRP2AR_WRP2A_END_Pos) /*!< 0x00FF0000 */
9016#define FLASH_WRP2AR_WRP2A_END FLASH_WRP2AR_WRP2A_END_Msk
9017
9018/****************** Bits definition for FLASH_WRP2BR register ***************/
9019#define FLASH_WRP2BR_WRP2B_STRT_Pos (0U)
9020#define FLASH_WRP2BR_WRP2B_STRT_Msk (0xFFU << FLASH_WRP2BR_WRP2B_STRT_Pos) /*!< 0x000000FF */
9021#define FLASH_WRP2BR_WRP2B_STRT FLASH_WRP2BR_WRP2B_STRT_Msk
9022#define FLASH_WRP2BR_WRP2B_END_Pos (16U)
9023#define FLASH_WRP2BR_WRP2B_END_Msk (0xFFU << FLASH_WRP2BR_WRP2B_END_Pos) /*!< 0x00FF0000 */
9024#define FLASH_WRP2BR_WRP2B_END FLASH_WRP2BR_WRP2B_END_Msk
9025
9026/****************** Bits definition for FLASH_CFGR register *****************/
9027#define FLASH_CFGR_LVEN_Pos (0U)
9028#define FLASH_CFGR_LVEN_Msk (0x1U << FLASH_CFGR_LVEN_Pos) /*!< 0x00000001 */
9029#define FLASH_CFGR_LVEN FLASH_CFGR_LVEN_Msk /*!< Flash low voltage enable */
9030
9031
9032/******************************************************************************/
9033/* */
9034/* Flexible Memory Controller */
9035/* */
9036/******************************************************************************/
9037/****************** Bit definition for FMC_BCR1 register *******************/
9038#define FMC_BCR1_CCLKEN_Pos (20U)
9039#define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
9040#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
9041#define FMC_BCR1_WFDIS_Pos (21U)
9042#define FMC_BCR1_WFDIS_Msk (0x1U << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
9043#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
9044
9045/****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
9046#define FMC_BCRx_MBKEN_Pos (0U)
9047#define FMC_BCRx_MBKEN_Msk (0x1U << FMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
9048#define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk /*!<Memory bank enable bit */
9049#define FMC_BCRx_MUXEN_Pos (1U)
9050#define FMC_BCRx_MUXEN_Msk (0x1U << FMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
9051#define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk /*!<Address/data multiplexing enable bit */
9052
9053#define FMC_BCRx_MTYP_Pos (2U)
9054#define FMC_BCRx_MTYP_Msk (0x3U << FMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
9055#define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
9056#define FMC_BCRx_MTYP_0 (0x1U << FMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
9057#define FMC_BCRx_MTYP_1 (0x2U << FMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
9058
9059#define FMC_BCRx_MWID_Pos (4U)
9060#define FMC_BCRx_MWID_Msk (0x3U << FMC_BCRx_MWID_Pos) /*!< 0x00000030 */
9061#define FMC_BCRx_MWID FMC_BCRx_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
9062#define FMC_BCRx_MWID_0 (0x1U << FMC_BCRx_MWID_Pos) /*!< 0x00000010 */
9063#define FMC_BCRx_MWID_1 (0x2U << FMC_BCRx_MWID_Pos) /*!< 0x00000020 */
9064
9065#define FMC_BCRx_FACCEN_Pos (6U)
9066#define FMC_BCRx_FACCEN_Msk (0x1U << FMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
9067#define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk /*!<Flash access enable */
9068#define FMC_BCRx_BURSTEN_Pos (8U)
9069#define FMC_BCRx_BURSTEN_Msk (0x1U << FMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
9070#define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk /*!<Burst enable bit */
9071#define FMC_BCRx_WAITPOL_Pos (9U)
9072#define FMC_BCRx_WAITPOL_Msk (0x1U << FMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
9073#define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk /*!<Wait signal polarity bit */
9074#define FMC_BCRx_WAITCFG_Pos (11U)
9075#define FMC_BCRx_WAITCFG_Msk (0x1U << FMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
9076#define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk /*!<Wait timing configuration */
9077#define FMC_BCRx_WREN_Pos (12U)
9078#define FMC_BCRx_WREN_Msk (0x1U << FMC_BCRx_WREN_Pos) /*!< 0x00001000 */
9079#define FMC_BCRx_WREN FMC_BCRx_WREN_Msk /*!<Write enable bit */
9080#define FMC_BCRx_WAITEN_Pos (13U)
9081#define FMC_BCRx_WAITEN_Msk (0x1U << FMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
9082#define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk /*!<Wait enable bit */
9083#define FMC_BCRx_EXTMOD_Pos (14U)
9084#define FMC_BCRx_EXTMOD_Msk (0x1U << FMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
9085#define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk /*!<Extended mode enable */
9086#define FMC_BCRx_ASYNCWAIT_Pos (15U)
9087#define FMC_BCRx_ASYNCWAIT_Msk (0x1U << FMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
9088#define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk /*!<Asynchronous wait */
9089
9090#define FMC_BCRx_CPSIZE_Pos (16U)
9091#define FMC_BCRx_CPSIZE_Msk (0x7U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */
9092#define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk /*!<CRAM page size */
9093#define FMC_BCRx_CPSIZE_0 (0x1U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */
9094#define FMC_BCRx_CPSIZE_1 (0x2U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */
9095#define FMC_BCRx_CPSIZE_2 (0x4U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */
9096
9097#define FMC_BCRx_CBURSTRW_Pos (19U)
9098#define FMC_BCRx_CBURSTRW_Msk (0x1U << FMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
9099#define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk /*!<Write burst enable */
9100
9101#define FMC_BCRx_NBLSET_Pos (22U)
9102#define FMC_BCRx_NBLSET_Msk (0x3U << FMC_BCRx_NBLSET_Pos) /*!< 0x00C00000 */
9103#define FMC_BCRx_NBLSET FMC_BCRx_NBLSET_Msk /*!<Byte lane (NBL) setup */
9104#define FMC_BCRx_NBLSET_0 (0x1U << FMC_BCRx_NBLSET_Pos) /*!< 0x00500000 */
9105#define FMC_BCRx_NBLSET_1 (0x2U << FMC_BCRx_NBLSET_Pos) /*!< 0x00800000 */
9106
9107/****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
9108#define FMC_BTRx_ADDSET_Pos (0U)
9109#define FMC_BTRx_ADDSET_Msk (0xFU << FMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
9110#define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
9111#define FMC_BTRx_ADDSET_0 (0x1U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
9112#define FMC_BTRx_ADDSET_1 (0x2U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
9113#define FMC_BTRx_ADDSET_2 (0x4U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
9114#define FMC_BTRx_ADDSET_3 (0x8U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
9115
9116#define FMC_BTRx_ADDHLD_Pos (4U)
9117#define FMC_BTRx_ADDHLD_Msk (0xFU << FMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
9118#define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
9119#define FMC_BTRx_ADDHLD_0 (0x1U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
9120#define FMC_BTRx_ADDHLD_1 (0x2U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
9121#define FMC_BTRx_ADDHLD_2 (0x4U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
9122#define FMC_BTRx_ADDHLD_3 (0x8U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
9123
9124#define FMC_BTRx_DATAST_Pos (8U)
9125#define FMC_BTRx_DATAST_Msk (0xFFU << FMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
9126#define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
9127#define FMC_BTRx_DATAST_0 (0x01U << FMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
9128#define FMC_BTRx_DATAST_1 (0x02U << FMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
9129#define FMC_BTRx_DATAST_2 (0x04U << FMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
9130#define FMC_BTRx_DATAST_3 (0x08U << FMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
9131#define FMC_BTRx_DATAST_4 (0x10U << FMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
9132#define FMC_BTRx_DATAST_5 (0x20U << FMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
9133#define FMC_BTRx_DATAST_6 (0x40U << FMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
9134#define FMC_BTRx_DATAST_7 (0x80U << FMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
9135
9136#define FMC_BTRx_BUSTURN_Pos (16U)
9137#define FMC_BTRx_BUSTURN_Msk (0xFU << FMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
9138#define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
9139#define FMC_BTRx_BUSTURN_0 (0x1U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
9140#define FMC_BTRx_BUSTURN_1 (0x2U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
9141#define FMC_BTRx_BUSTURN_2 (0x4U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
9142#define FMC_BTRx_BUSTURN_3 (0x8U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
9143
9144#define FMC_BTRx_CLKDIV_Pos (20U)
9145#define FMC_BTRx_CLKDIV_Msk (0xFU << FMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
9146#define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
9147#define FMC_BTRx_CLKDIV_0 (0x1U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
9148#define FMC_BTRx_CLKDIV_1 (0x2U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
9149#define FMC_BTRx_CLKDIV_2 (0x4U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
9150#define FMC_BTRx_CLKDIV_3 (0x8U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
9151
9152#define FMC_BTRx_DATLAT_Pos (24U)
9153#define FMC_BTRx_DATLAT_Msk (0xFU << FMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
9154#define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk /*!<DATLAT[3:0] bits (Data latency) */
9155#define FMC_BTRx_DATLAT_0 (0x1U << FMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
9156#define FMC_BTRx_DATLAT_1 (0x2U << FMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
9157#define FMC_BTRx_DATLAT_2 (0x4U << FMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
9158#define FMC_BTRx_DATLAT_3 (0x8U << FMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
9159
9160#define FMC_BTRx_ACCMOD_Pos (28U)
9161#define FMC_BTRx_ACCMOD_Msk (0x3U << FMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
9162#define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
9163#define FMC_BTRx_ACCMOD_0 (0x1U << FMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
9164#define FMC_BTRx_ACCMOD_1 (0x2U << FMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
9165
9166#define FMC_BTRx_DATAHLD_Pos (30U)
9167#define FMC_BTRx_DATAHLD_Msk (0x3U << FMC_BTRx_DATAHLD_Pos) /*!< 0xC0000000 */
9168#define FMC_BTRx_DATAHLD FMC_BTRx_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data hold phase duration) */
9169#define FMC_BTRx_DATAHLD_0 (0x1U << FMC_BTRx_DATAHLD_Pos) /*!< 0x40000000 */
9170#define FMC_BTRx_DATAHLD_1 (0x2U << FMC_BTRx_DATAHLD_Pos) /*!< 0x80000000 */
9171
9172/****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
9173#define FMC_BWTRx_ADDSET_Pos (0U)
9174#define FMC_BWTRx_ADDSET_Msk (0xFU << FMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
9175#define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
9176#define FMC_BWTRx_ADDSET_0 (0x1U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
9177#define FMC_BWTRx_ADDSET_1 (0x2U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
9178#define FMC_BWTRx_ADDSET_2 (0x4U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
9179#define FMC_BWTRx_ADDSET_3 (0x8U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
9180
9181#define FMC_BWTRx_ADDHLD_Pos (4U)
9182#define FMC_BWTRx_ADDHLD_Msk (0xFU << FMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
9183#define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
9184#define FMC_BWTRx_ADDHLD_0 (0x1U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
9185#define FMC_BWTRx_ADDHLD_1 (0x2U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
9186#define FMC_BWTRx_ADDHLD_2 (0x4U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
9187#define FMC_BWTRx_ADDHLD_3 (0x8U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
9188
9189#define FMC_BWTRx_DATAST_Pos (8U)
9190#define FMC_BWTRx_DATAST_Msk (0xFFU << FMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
9191#define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
9192#define FMC_BWTRx_DATAST_0 (0x01U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
9193#define FMC_BWTRx_DATAST_1 (0x02U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
9194#define FMC_BWTRx_DATAST_2 (0x04U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
9195#define FMC_BWTRx_DATAST_3 (0x08U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
9196#define FMC_BWTRx_DATAST_4 (0x10U << FMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
9197#define FMC_BWTRx_DATAST_5 (0x20U << FMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
9198#define FMC_BWTRx_DATAST_6 (0x40U << FMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
9199#define FMC_BWTRx_DATAST_7 (0x80U << FMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
9200
9201#define FMC_BWTRx_BUSTURN_Pos (16U)
9202#define FMC_BWTRx_BUSTURN_Msk (0xFU << FMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */
9203#define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
9204#define FMC_BWTRx_BUSTURN_0 (0x1U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */
9205#define FMC_BWTRx_BUSTURN_1 (0x2U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */
9206#define FMC_BWTRx_BUSTURN_2 (0x4U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */
9207#define FMC_BWTRx_BUSTURN_3 (0x8U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */
9208
9209#define FMC_BWTRx_ACCMOD_Pos (28U)
9210#define FMC_BWTRx_ACCMOD_Msk (0x3U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
9211#define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
9212#define FMC_BWTRx_ACCMOD_0 (0x1U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
9213#define FMC_BWTRx_ACCMOD_1 (0x2U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
9214
9215#define FMC_BWTRx_DATAHLD_Pos (30U)
9216#define FMC_BWTRx_DATAHLD_Msk (0x3U << FMC_BWTRx_DATAHLD_Pos) /*!< 0xC0000000 */
9217#define FMC_BWTRx_DATAHLD FMC_BWTRx_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data hold phase duration) */
9218#define FMC_BWTRx_DATAHLD_0 (0x1U << FMC_BWTRx_DATAHLD_Pos) /*!< 0x40000000 */
9219#define FMC_BWTRx_DATAHLD_1 (0x2U << FMC_BWTRx_DATAHLD_Pos) /*!< 0x80000000 */
9220
9221/****************** Bit definition for FMC_PCR register ********************/
9222#define FMC_PCR_PWAITEN_Pos (1U)
9223#define FMC_PCR_PWAITEN_Msk (0x1U << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
9224#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
9225#define FMC_PCR_PBKEN_Pos (2U)
9226#define FMC_PCR_PBKEN_Msk (0x1U << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
9227#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<NAND Flash memory bank enable bit */
9228#define FMC_PCR_PTYP_Pos (3U)
9229#define FMC_PCR_PTYP_Msk (0x1U << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
9230#define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
9231
9232#define FMC_PCR_PWID_Pos (4U)
9233#define FMC_PCR_PWID_Msk (0x3U << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
9234#define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
9235#define FMC_PCR_PWID_0 (0x1U << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
9236#define FMC_PCR_PWID_1 (0x2U << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
9237
9238#define FMC_PCR_ECCEN_Pos (6U)
9239#define FMC_PCR_ECCEN_Msk (0x1U << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
9240#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
9241
9242#define FMC_PCR_TCLR_Pos (9U)
9243#define FMC_PCR_TCLR_Msk (0xFU << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
9244#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
9245#define FMC_PCR_TCLR_0 (0x1U << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
9246#define FMC_PCR_TCLR_1 (0x2U << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
9247#define FMC_PCR_TCLR_2 (0x4U << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
9248#define FMC_PCR_TCLR_3 (0x8U << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
9249
9250#define FMC_PCR_TAR_Pos (13U)
9251#define FMC_PCR_TAR_Msk (0xFU << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
9252#define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
9253#define FMC_PCR_TAR_0 (0x1U << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
9254#define FMC_PCR_TAR_1 (0x2U << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
9255#define FMC_PCR_TAR_2 (0x4U << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
9256#define FMC_PCR_TAR_3 (0x8U << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
9257
9258#define FMC_PCR_ECCPS_Pos (17U)
9259#define FMC_PCR_ECCPS_Msk (0x7U << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
9260#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
9261#define FMC_PCR_ECCPS_0 (0x1U << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
9262#define FMC_PCR_ECCPS_1 (0x2U << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
9263#define FMC_PCR_ECCPS_2 (0x4U << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
9264
9265/******************* Bit definition for FMC_SR register ********************/
9266#define FMC_SR_IRS_Pos (0U)
9267#define FMC_SR_IRS_Msk (0x1U << FMC_SR_IRS_Pos) /*!< 0x00000001 */
9268#define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
9269#define FMC_SR_ILS_Pos (1U)
9270#define FMC_SR_ILS_Msk (0x1U << FMC_SR_ILS_Pos) /*!< 0x00000002 */
9271#define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
9272#define FMC_SR_IFS_Pos (2U)
9273#define FMC_SR_IFS_Msk (0x1U << FMC_SR_IFS_Pos) /*!< 0x00000004 */
9274#define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
9275#define FMC_SR_IREN_Pos (3U)
9276#define FMC_SR_IREN_Msk (0x1U << FMC_SR_IREN_Pos) /*!< 0x00000008 */
9277#define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
9278#define FMC_SR_ILEN_Pos (4U)
9279#define FMC_SR_ILEN_Msk (0x1U << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
9280#define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
9281#define FMC_SR_IFEN_Pos (5U)
9282#define FMC_SR_IFEN_Msk (0x1U << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
9283#define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
9284#define FMC_SR_FEMPT_Pos (6U)
9285#define FMC_SR_FEMPT_Msk (0x1U << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
9286#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
9287
9288/****************** Bit definition for FMC_PMEM register ******************/
9289#define FMC_PMEM_MEMSET_Pos (0U)
9290#define FMC_PMEM_MEMSET_Msk (0xFFU << FMC_PMEM_MEMSET_Pos) /*!< 0x000000FF */
9291#define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk /*!<MEMSET[7:0] bits (Common memory setup time) */
9292#define FMC_PMEM_MEMSET_0 (0x01U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000001 */
9293#define FMC_PMEM_MEMSET_1 (0x02U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000002 */
9294#define FMC_PMEM_MEMSET_2 (0x04U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000004 */
9295#define FMC_PMEM_MEMSET_3 (0x08U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000008 */
9296#define FMC_PMEM_MEMSET_4 (0x10U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000010 */
9297#define FMC_PMEM_MEMSET_5 (0x20U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000020 */
9298#define FMC_PMEM_MEMSET_6 (0x40U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000040 */
9299#define FMC_PMEM_MEMSET_7 (0x80U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000080 */
9300
9301#define FMC_PMEM_MEMWAIT_Pos (8U)
9302#define FMC_PMEM_MEMWAIT_Msk (0xFFU << FMC_PMEM_MEMWAIT_Pos) /*!< 0x0000FF00 */
9303#define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk /*!<MEMWAIT[7:0] bits (Common memory wait time) */
9304#define FMC_PMEM_MEMWAIT_0 (0x01U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000100 */
9305#define FMC_PMEM_MEMWAIT_1 (0x02U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000200 */
9306#define FMC_PMEM_MEMWAIT_2 (0x04U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000400 */
9307#define FMC_PMEM_MEMWAIT_3 (0x08U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000800 */
9308#define FMC_PMEM_MEMWAIT_4 (0x10U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00001000 */
9309#define FMC_PMEM_MEMWAIT_5 (0x20U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00002000 */
9310#define FMC_PMEM_MEMWAIT_6 (0x40U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00004000 */
9311#define FMC_PMEM_MEMWAIT_7 (0x80U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00008000 */
9312
9313#define FMC_PMEM_MEMHOLD_Pos (16U)
9314#define FMC_PMEM_MEMHOLD_Msk (0xFFU << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00FF0000 */
9315#define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk /*!<MEMHOLD[7:0] bits (Common memory hold time) */
9316#define FMC_PMEM_MEMHOLD_0 (0x01U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00010000 */
9317#define FMC_PMEM_MEMHOLD_1 (0x02U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00020000 */
9318#define FMC_PMEM_MEMHOLD_2 (0x04U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00040000 */
9319#define FMC_PMEM_MEMHOLD_3 (0x08U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00080000 */
9320#define FMC_PMEM_MEMHOLD_4 (0x10U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00100000 */
9321#define FMC_PMEM_MEMHOLD_5 (0x20U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00200000 */
9322#define FMC_PMEM_MEMHOLD_6 (0x40U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00400000 */
9323#define FMC_PMEM_MEMHOLD_7 (0x80U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00800000 */
9324
9325#define FMC_PMEM_MEMHIZ_Pos (24U)
9326#define FMC_PMEM_MEMHIZ_Msk (0xFFU << FMC_PMEM_MEMHIZ_Pos) /*!< 0xFF000000 */
9327#define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
9328#define FMC_PMEM_MEMHIZ_0 (0x01U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x01000000 */
9329#define FMC_PMEM_MEMHIZ_1 (0x02U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x02000000 */
9330#define FMC_PMEM_MEMHIZ_2 (0x04U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x04000000 */
9331#define FMC_PMEM_MEMHIZ_3 (0x08U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x08000000 */
9332#define FMC_PMEM_MEMHIZ_4 (0x10U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x10000000 */
9333#define FMC_PMEM_MEMHIZ_5 (0x20U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x20000000 */
9334#define FMC_PMEM_MEMHIZ_6 (0x40U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x40000000 */
9335#define FMC_PMEM_MEMHIZ_7 (0x80U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x80000000 */
9336
9337/****************** Bit definition for FMC_PATT register *******************/
9338#define FMC_PATT_ATTSET_Pos (0U)
9339#define FMC_PATT_ATTSET_Msk (0xFFU << FMC_PATT_ATTSET_Pos) /*!< 0x000000FF */
9340#define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk /*!<ATTSET[7:0] bits (Attribute memory setup time) */
9341#define FMC_PATT_ATTSET_0 (0x01U << FMC_PATT_ATTSET_Pos) /*!< 0x00000001 */
9342#define FMC_PATT_ATTSET_1 (0x02U << FMC_PATT_ATTSET_Pos) /*!< 0x00000002 */
9343#define FMC_PATT_ATTSET_2 (0x04U << FMC_PATT_ATTSET_Pos) /*!< 0x00000004 */
9344#define FMC_PATT_ATTSET_3 (0x08U << FMC_PATT_ATTSET_Pos) /*!< 0x00000008 */
9345#define FMC_PATT_ATTSET_4 (0x10U << FMC_PATT_ATTSET_Pos) /*!< 0x00000010 */
9346#define FMC_PATT_ATTSET_5 (0x20U << FMC_PATT_ATTSET_Pos) /*!< 0x00000020 */
9347#define FMC_PATT_ATTSET_6 (0x40U << FMC_PATT_ATTSET_Pos) /*!< 0x00000040 */
9348#define FMC_PATT_ATTSET_7 (0x80U << FMC_PATT_ATTSET_Pos) /*!< 0x00000080 */
9349
9350#define FMC_PATT_ATTWAIT_Pos (8U)
9351#define FMC_PATT_ATTWAIT_Msk (0xFFU << FMC_PATT_ATTWAIT_Pos) /*!< 0x0000FF00 */
9352#define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
9353#define FMC_PATT_ATTWAIT_0 (0x01U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000100 */
9354#define FMC_PATT_ATTWAIT_1 (0x02U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000200 */
9355#define FMC_PATT_ATTWAIT_2 (0x04U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000400 */
9356#define FMC_PATT_ATTWAIT_3 (0x08U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000800 */
9357#define FMC_PATT_ATTWAIT_4 (0x10U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00001000 */
9358#define FMC_PATT_ATTWAIT_5 (0x20U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00002000 */
9359#define FMC_PATT_ATTWAIT_6 (0x40U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00004000 */
9360#define FMC_PATT_ATTWAIT_7 (0x80U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00008000 */
9361
9362#define FMC_PATT_ATTHOLD_Pos (16U)
9363#define FMC_PATT_ATTHOLD_Msk (0xFFU << FMC_PATT_ATTHOLD_Pos) /*!< 0x00FF0000 */
9364#define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
9365#define FMC_PATT_ATTHOLD_0 (0x01U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00010000 */
9366#define FMC_PATT_ATTHOLD_1 (0x02U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00020000 */
9367#define FMC_PATT_ATTHOLD_2 (0x04U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00040000 */
9368#define FMC_PATT_ATTHOLD_3 (0x08U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00080000 */
9369#define FMC_PATT_ATTHOLD_4 (0x10U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00100000 */
9370#define FMC_PATT_ATTHOLD_5 (0x20U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00200000 */
9371#define FMC_PATT_ATTHOLD_6 (0x40U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00400000 */
9372#define FMC_PATT_ATTHOLD_7 (0x80U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00800000 */
9373
9374#define FMC_PATT_ATTHIZ_Pos (24U)
9375#define FMC_PATT_ATTHIZ_Msk (0xFFU << FMC_PATT_ATTHIZ_Pos) /*!< 0xFF000000 */
9376#define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
9377#define FMC_PATT_ATTHIZ_0 (0x01U << FMC_PATT_ATTHIZ_Pos) /*!< 0x01000000 */
9378#define FMC_PATT_ATTHIZ_1 (0x02U << FMC_PATT_ATTHIZ_Pos) /*!< 0x02000000 */
9379#define FMC_PATT_ATTHIZ_2 (0x04U << FMC_PATT_ATTHIZ_Pos) /*!< 0x04000000 */
9380#define FMC_PATT_ATTHIZ_3 (0x08U << FMC_PATT_ATTHIZ_Pos) /*!< 0x08000000 */
9381#define FMC_PATT_ATTHIZ_4 (0x10U << FMC_PATT_ATTHIZ_Pos) /*!< 0x10000000 */
9382#define FMC_PATT_ATTHIZ_5 (0x20U << FMC_PATT_ATTHIZ_Pos) /*!< 0x20000000 */
9383#define FMC_PATT_ATTHIZ_6 (0x40U << FMC_PATT_ATTHIZ_Pos) /*!< 0x40000000 */
9384#define FMC_PATT_ATTHIZ_7 (0x80U << FMC_PATT_ATTHIZ_Pos) /*!< 0x80000000 */
9385
9386/****************** Bit definition for FMC_ECCR register *******************/
9387#define FMC_ECCR_ECC_Pos (0U)
9388#define FMC_ECCR_ECC_Msk (0xFFFFFFFFU << FMC_ECCR_ECC_Pos) /*!< 0xFFFFFFFF */
9389#define FMC_ECCR_ECC FMC_ECCR_ECC_Msk /*!<ECC result */
9390
9391/******************************************************************************/
9392/* */
9393/* General Purpose IOs (GPIO) */
9394/* */
9395/******************************************************************************/
9396/****************** Bits definition for GPIO_MODER register *****************/
9397#define GPIO_MODER_MODE0_Pos (0U)
9398#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
9399#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
9400#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
9401#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
9402#define GPIO_MODER_MODE1_Pos (2U)
9403#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
9404#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
9405#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
9406#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
9407#define GPIO_MODER_MODE2_Pos (4U)
9408#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
9409#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
9410#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
9411#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
9412#define GPIO_MODER_MODE3_Pos (6U)
9413#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
9414#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
9415#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
9416#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
9417#define GPIO_MODER_MODE4_Pos (8U)
9418#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
9419#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
9420#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
9421#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
9422#define GPIO_MODER_MODE5_Pos (10U)
9423#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
9424#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
9425#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
9426#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
9427#define GPIO_MODER_MODE6_Pos (12U)
9428#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
9429#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
9430#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
9431#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
9432#define GPIO_MODER_MODE7_Pos (14U)
9433#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
9434#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
9435#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
9436#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
9437#define GPIO_MODER_MODE8_Pos (16U)
9438#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
9439#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
9440#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
9441#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
9442#define GPIO_MODER_MODE9_Pos (18U)
9443#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
9444#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
9445#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
9446#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
9447#define GPIO_MODER_MODE10_Pos (20U)
9448#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
9449#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
9450#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
9451#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
9452#define GPIO_MODER_MODE11_Pos (22U)
9453#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
9454#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
9455#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
9456#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
9457#define GPIO_MODER_MODE12_Pos (24U)
9458#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
9459#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
9460#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
9461#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
9462#define GPIO_MODER_MODE13_Pos (26U)
9463#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
9464#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
9465#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
9466#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
9467#define GPIO_MODER_MODE14_Pos (28U)
9468#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
9469#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
9470#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
9471#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
9472#define GPIO_MODER_MODE15_Pos (30U)
9473#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
9474#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
9475#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
9476#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
9477
9478/* Legacy defines */
9479#define GPIO_MODER_MODER0 GPIO_MODER_MODE0
9480#define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
9481#define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
9482#define GPIO_MODER_MODER1 GPIO_MODER_MODE1
9483#define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
9484#define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
9485#define GPIO_MODER_MODER2 GPIO_MODER_MODE2
9486#define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
9487#define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
9488#define GPIO_MODER_MODER3 GPIO_MODER_MODE3
9489#define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
9490#define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
9491#define GPIO_MODER_MODER4 GPIO_MODER_MODE4
9492#define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
9493#define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
9494#define GPIO_MODER_MODER5 GPIO_MODER_MODE5
9495#define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
9496#define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
9497#define GPIO_MODER_MODER6 GPIO_MODER_MODE6
9498#define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
9499#define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
9500#define GPIO_MODER_MODER7 GPIO_MODER_MODE7
9501#define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
9502#define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
9503#define GPIO_MODER_MODER8 GPIO_MODER_MODE8
9504#define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
9505#define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
9506#define GPIO_MODER_MODER9 GPIO_MODER_MODE9
9507#define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
9508#define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
9509#define GPIO_MODER_MODER10 GPIO_MODER_MODE10
9510#define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
9511#define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
9512#define GPIO_MODER_MODER11 GPIO_MODER_MODE11
9513#define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
9514#define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
9515#define GPIO_MODER_MODER12 GPIO_MODER_MODE12
9516#define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
9517#define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
9518#define GPIO_MODER_MODER13 GPIO_MODER_MODE13
9519#define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
9520#define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
9521#define GPIO_MODER_MODER14 GPIO_MODER_MODE14
9522#define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
9523#define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
9524#define GPIO_MODER_MODER15 GPIO_MODER_MODE15
9525#define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
9526#define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
9527
9528/****************** Bits definition for GPIO_OTYPER register ****************/
9529#define GPIO_OTYPER_OT0_Pos (0U)
9530#define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
9531#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
9532#define GPIO_OTYPER_OT1_Pos (1U)
9533#define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
9534#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
9535#define GPIO_OTYPER_OT2_Pos (2U)
9536#define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
9537#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
9538#define GPIO_OTYPER_OT3_Pos (3U)
9539#define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
9540#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
9541#define GPIO_OTYPER_OT4_Pos (4U)
9542#define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
9543#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
9544#define GPIO_OTYPER_OT5_Pos (5U)
9545#define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
9546#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
9547#define GPIO_OTYPER_OT6_Pos (6U)
9548#define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
9549#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
9550#define GPIO_OTYPER_OT7_Pos (7U)
9551#define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
9552#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
9553#define GPIO_OTYPER_OT8_Pos (8U)
9554#define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
9555#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
9556#define GPIO_OTYPER_OT9_Pos (9U)
9557#define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
9558#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
9559#define GPIO_OTYPER_OT10_Pos (10U)
9560#define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
9561#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
9562#define GPIO_OTYPER_OT11_Pos (11U)
9563#define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
9564#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
9565#define GPIO_OTYPER_OT12_Pos (12U)
9566#define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
9567#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
9568#define GPIO_OTYPER_OT13_Pos (13U)
9569#define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
9570#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
9571#define GPIO_OTYPER_OT14_Pos (14U)
9572#define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
9573#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
9574#define GPIO_OTYPER_OT15_Pos (15U)
9575#define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
9576#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
9577
9578/* Legacy defines */
9579#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
9580#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
9581#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
9582#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
9583#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
9584#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
9585#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
9586#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
9587#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
9588#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
9589#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
9590#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
9591#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
9592#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
9593#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
9594#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
9595
9596/****************** Bits definition for GPIO_OSPEEDR register ***************/
9597#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
9598#define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
9599#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
9600#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
9601#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
9602#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
9603#define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
9604#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
9605#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
9606#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
9607#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
9608#define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
9609#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
9610#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
9611#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
9612#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
9613#define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
9614#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
9615#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
9616#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
9617#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
9618#define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
9619#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
9620#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
9621#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
9622#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
9623#define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
9624#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
9625#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
9626#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
9627#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
9628#define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
9629#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
9630#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
9631#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
9632#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
9633#define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
9634#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
9635#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
9636#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
9637#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
9638#define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
9639#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
9640#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
9641#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
9642#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
9643#define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
9644#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
9645#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
9646#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
9647#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
9648#define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
9649#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
9650#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
9651#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
9652#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
9653#define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
9654#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
9655#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
9656#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
9657#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
9658#define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
9659#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
9660#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
9661#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
9662#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
9663#define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
9664#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
9665#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
9666#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
9667#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
9668#define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
9669#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
9670#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
9671#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
9672#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
9673#define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
9674#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
9675#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
9676#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
9677
9678/* Legacy defines */
9679#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
9680#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
9681#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
9682#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
9683#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
9684#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
9685#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
9686#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
9687#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
9688#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
9689#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
9690#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
9691#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
9692#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
9693#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
9694#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
9695#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
9696#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
9697#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
9698#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
9699#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
9700#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
9701#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
9702#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
9703#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
9704#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
9705#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
9706#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
9707#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
9708#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
9709#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
9710#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
9711#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
9712#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
9713#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
9714#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
9715#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
9716#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
9717#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
9718#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
9719#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
9720#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
9721#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
9722#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
9723#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
9724#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
9725#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
9726#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
9727
9728/****************** Bits definition for GPIO_PUPDR register *****************/
9729#define GPIO_PUPDR_PUPD0_Pos (0U)
9730#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
9731#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
9732#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
9733#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
9734#define GPIO_PUPDR_PUPD1_Pos (2U)
9735#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
9736#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
9737#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
9738#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
9739#define GPIO_PUPDR_PUPD2_Pos (4U)
9740#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
9741#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
9742#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
9743#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
9744#define GPIO_PUPDR_PUPD3_Pos (6U)
9745#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
9746#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
9747#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
9748#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
9749#define GPIO_PUPDR_PUPD4_Pos (8U)
9750#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
9751#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
9752#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
9753#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
9754#define GPIO_PUPDR_PUPD5_Pos (10U)
9755#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
9756#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
9757#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
9758#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
9759#define GPIO_PUPDR_PUPD6_Pos (12U)
9760#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
9761#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
9762#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
9763#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
9764#define GPIO_PUPDR_PUPD7_Pos (14U)
9765#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
9766#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
9767#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
9768#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
9769#define GPIO_PUPDR_PUPD8_Pos (16U)
9770#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
9771#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
9772#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
9773#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
9774#define GPIO_PUPDR_PUPD9_Pos (18U)
9775#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
9776#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
9777#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
9778#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
9779#define GPIO_PUPDR_PUPD10_Pos (20U)
9780#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
9781#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
9782#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
9783#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
9784#define GPIO_PUPDR_PUPD11_Pos (22U)
9785#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
9786#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
9787#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
9788#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
9789#define GPIO_PUPDR_PUPD12_Pos (24U)
9790#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
9791#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
9792#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
9793#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
9794#define GPIO_PUPDR_PUPD13_Pos (26U)
9795#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
9796#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
9797#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
9798#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
9799#define GPIO_PUPDR_PUPD14_Pos (28U)
9800#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
9801#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
9802#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
9803#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
9804#define GPIO_PUPDR_PUPD15_Pos (30U)
9805#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
9806#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
9807#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
9808#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
9809
9810/* Legacy defines */
9811#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
9812#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
9813#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
9814#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
9815#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
9816#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
9817#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
9818#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
9819#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
9820#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
9821#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
9822#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
9823#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
9824#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
9825#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
9826#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
9827#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
9828#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
9829#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
9830#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
9831#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
9832#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
9833#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
9834#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
9835#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
9836#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
9837#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
9838#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
9839#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
9840#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
9841#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
9842#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
9843#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
9844#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
9845#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
9846#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
9847#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
9848#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
9849#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
9850#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
9851#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
9852#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
9853#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
9854#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
9855#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
9856#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
9857#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
9858#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
9859
9860/****************** Bits definition for GPIO_IDR register *******************/
9861#define GPIO_IDR_ID0_Pos (0U)
9862#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
9863#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
9864#define GPIO_IDR_ID1_Pos (1U)
9865#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
9866#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
9867#define GPIO_IDR_ID2_Pos (2U)
9868#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
9869#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
9870#define GPIO_IDR_ID3_Pos (3U)
9871#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
9872#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
9873#define GPIO_IDR_ID4_Pos (4U)
9874#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
9875#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
9876#define GPIO_IDR_ID5_Pos (5U)
9877#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
9878#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
9879#define GPIO_IDR_ID6_Pos (6U)
9880#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
9881#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
9882#define GPIO_IDR_ID7_Pos (7U)
9883#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
9884#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
9885#define GPIO_IDR_ID8_Pos (8U)
9886#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
9887#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
9888#define GPIO_IDR_ID9_Pos (9U)
9889#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
9890#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
9891#define GPIO_IDR_ID10_Pos (10U)
9892#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
9893#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
9894#define GPIO_IDR_ID11_Pos (11U)
9895#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
9896#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
9897#define GPIO_IDR_ID12_Pos (12U)
9898#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
9899#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
9900#define GPIO_IDR_ID13_Pos (13U)
9901#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
9902#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
9903#define GPIO_IDR_ID14_Pos (14U)
9904#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
9905#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
9906#define GPIO_IDR_ID15_Pos (15U)
9907#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
9908#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
9909
9910/* Legacy defines */
9911#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
9912#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
9913#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
9914#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
9915#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
9916#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
9917#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
9918#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
9919#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
9920#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
9921#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
9922#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
9923#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
9924#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
9925#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
9926#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
9927
9928/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
9929#define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
9930#define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
9931#define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
9932#define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
9933#define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
9934#define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
9935#define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
9936#define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
9937#define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
9938#define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
9939#define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
9940#define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
9941#define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
9942#define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
9943#define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
9944#define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
9945
9946/****************** Bits definition for GPIO_ODR register *******************/
9947#define GPIO_ODR_OD0_Pos (0U)
9948#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
9949#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
9950#define GPIO_ODR_OD1_Pos (1U)
9951#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
9952#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
9953#define GPIO_ODR_OD2_Pos (2U)
9954#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
9955#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
9956#define GPIO_ODR_OD3_Pos (3U)
9957#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
9958#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
9959#define GPIO_ODR_OD4_Pos (4U)
9960#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
9961#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
9962#define GPIO_ODR_OD5_Pos (5U)
9963#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
9964#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
9965#define GPIO_ODR_OD6_Pos (6U)
9966#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
9967#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
9968#define GPIO_ODR_OD7_Pos (7U)
9969#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
9970#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
9971#define GPIO_ODR_OD8_Pos (8U)
9972#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
9973#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
9974#define GPIO_ODR_OD9_Pos (9U)
9975#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
9976#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
9977#define GPIO_ODR_OD10_Pos (10U)
9978#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
9979#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
9980#define GPIO_ODR_OD11_Pos (11U)
9981#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
9982#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
9983#define GPIO_ODR_OD12_Pos (12U)
9984#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
9985#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
9986#define GPIO_ODR_OD13_Pos (13U)
9987#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
9988#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
9989#define GPIO_ODR_OD14_Pos (14U)
9990#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
9991#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
9992#define GPIO_ODR_OD15_Pos (15U)
9993#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
9994#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
9995
9996/* Legacy defines */
9997#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
9998#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
9999#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
10000#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
10001#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
10002#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
10003#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
10004#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
10005#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
10006#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
10007#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
10008#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
10009#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
10010#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
10011#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
10012#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
10013
10014/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
10015#define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
10016#define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
10017#define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
10018#define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
10019#define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
10020#define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
10021#define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
10022#define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
10023#define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
10024#define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
10025#define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
10026#define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
10027#define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
10028#define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
10029#define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
10030#define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
10031
10032/****************** Bits definition for GPIO_BSRR register ******************/
10033#define GPIO_BSRR_BS0_Pos (0U)
10034#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
10035#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
10036#define GPIO_BSRR_BS1_Pos (1U)
10037#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
10038#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
10039#define GPIO_BSRR_BS2_Pos (2U)
10040#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
10041#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
10042#define GPIO_BSRR_BS3_Pos (3U)
10043#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
10044#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
10045#define GPIO_BSRR_BS4_Pos (4U)
10046#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
10047#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
10048#define GPIO_BSRR_BS5_Pos (5U)
10049#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
10050#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
10051#define GPIO_BSRR_BS6_Pos (6U)
10052#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
10053#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
10054#define GPIO_BSRR_BS7_Pos (7U)
10055#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
10056#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
10057#define GPIO_BSRR_BS8_Pos (8U)
10058#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
10059#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
10060#define GPIO_BSRR_BS9_Pos (9U)
10061#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
10062#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
10063#define GPIO_BSRR_BS10_Pos (10U)
10064#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
10065#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
10066#define GPIO_BSRR_BS11_Pos (11U)
10067#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
10068#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
10069#define GPIO_BSRR_BS12_Pos (12U)
10070#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
10071#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
10072#define GPIO_BSRR_BS13_Pos (13U)
10073#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
10074#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
10075#define GPIO_BSRR_BS14_Pos (14U)
10076#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
10077#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
10078#define GPIO_BSRR_BS15_Pos (15U)
10079#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
10080#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
10081#define GPIO_BSRR_BR0_Pos (16U)
10082#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
10083#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
10084#define GPIO_BSRR_BR1_Pos (17U)
10085#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
10086#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
10087#define GPIO_BSRR_BR2_Pos (18U)
10088#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
10089#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
10090#define GPIO_BSRR_BR3_Pos (19U)
10091#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
10092#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
10093#define GPIO_BSRR_BR4_Pos (20U)
10094#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
10095#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
10096#define GPIO_BSRR_BR5_Pos (21U)
10097#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
10098#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
10099#define GPIO_BSRR_BR6_Pos (22U)
10100#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
10101#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
10102#define GPIO_BSRR_BR7_Pos (23U)
10103#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
10104#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
10105#define GPIO_BSRR_BR8_Pos (24U)
10106#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
10107#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
10108#define GPIO_BSRR_BR9_Pos (25U)
10109#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
10110#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
10111#define GPIO_BSRR_BR10_Pos (26U)
10112#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
10113#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
10114#define GPIO_BSRR_BR11_Pos (27U)
10115#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
10116#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
10117#define GPIO_BSRR_BR12_Pos (28U)
10118#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
10119#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
10120#define GPIO_BSRR_BR13_Pos (29U)
10121#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
10122#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
10123#define GPIO_BSRR_BR14_Pos (30U)
10124#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
10125#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
10126#define GPIO_BSRR_BR15_Pos (31U)
10127#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
10128#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
10129
10130/* Legacy defines */
10131#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
10132#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
10133#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
10134#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
10135#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
10136#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
10137#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
10138#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
10139#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
10140#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
10141#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
10142#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
10143#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
10144#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
10145#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
10146#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
10147#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
10148#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
10149#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
10150#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
10151#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
10152#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
10153#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
10154#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
10155#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
10156#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
10157#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
10158#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
10159#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
10160#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
10161#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
10162#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
10163
10164/****************** Bit definition for GPIO_LCKR register *********************/
10165#define GPIO_LCKR_LCK0_Pos (0U)
10166#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
10167#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
10168#define GPIO_LCKR_LCK1_Pos (1U)
10169#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
10170#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
10171#define GPIO_LCKR_LCK2_Pos (2U)
10172#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
10173#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
10174#define GPIO_LCKR_LCK3_Pos (3U)
10175#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
10176#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
10177#define GPIO_LCKR_LCK4_Pos (4U)
10178#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
10179#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
10180#define GPIO_LCKR_LCK5_Pos (5U)
10181#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
10182#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
10183#define GPIO_LCKR_LCK6_Pos (6U)
10184#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
10185#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
10186#define GPIO_LCKR_LCK7_Pos (7U)
10187#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
10188#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
10189#define GPIO_LCKR_LCK8_Pos (8U)
10190#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
10191#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
10192#define GPIO_LCKR_LCK9_Pos (9U)
10193#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
10194#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
10195#define GPIO_LCKR_LCK10_Pos (10U)
10196#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
10197#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
10198#define GPIO_LCKR_LCK11_Pos (11U)
10199#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
10200#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
10201#define GPIO_LCKR_LCK12_Pos (12U)
10202#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
10203#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
10204#define GPIO_LCKR_LCK13_Pos (13U)
10205#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
10206#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
10207#define GPIO_LCKR_LCK14_Pos (14U)
10208#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
10209#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
10210#define GPIO_LCKR_LCK15_Pos (15U)
10211#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
10212#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
10213#define GPIO_LCKR_LCKK_Pos (16U)
10214#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
10215#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
10216
10217/****************** Bit definition for GPIO_AFRL register *********************/
10218#define GPIO_AFRL_AFSEL0_Pos (0U)
10219#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
10220#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
10221#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
10222#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
10223#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
10224#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
10225#define GPIO_AFRL_AFSEL1_Pos (4U)
10226#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
10227#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
10228#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
10229#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
10230#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
10231#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
10232#define GPIO_AFRL_AFSEL2_Pos (8U)
10233#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
10234#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
10235#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
10236#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
10237#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
10238#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
10239#define GPIO_AFRL_AFSEL3_Pos (12U)
10240#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
10241#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
10242#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
10243#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
10244#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
10245#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
10246#define GPIO_AFRL_AFSEL4_Pos (16U)
10247#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
10248#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
10249#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
10250#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
10251#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
10252#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
10253#define GPIO_AFRL_AFSEL5_Pos (20U)
10254#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
10255#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
10256#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
10257#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
10258#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
10259#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
10260#define GPIO_AFRL_AFSEL6_Pos (24U)
10261#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
10262#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
10263#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
10264#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
10265#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
10266#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
10267#define GPIO_AFRL_AFSEL7_Pos (28U)
10268#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
10269#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
10270#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
10271#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
10272#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
10273#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
10274
10275/* Legacy defines */
10276#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
10277#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
10278#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
10279#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
10280#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
10281#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
10282#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
10283#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
10284
10285/****************** Bit definition for GPIO_AFRH register *********************/
10286#define GPIO_AFRH_AFSEL8_Pos (0U)
10287#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
10288#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
10289#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
10290#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
10291#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
10292#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
10293#define GPIO_AFRH_AFSEL9_Pos (4U)
10294#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
10295#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
10296#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
10297#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
10298#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
10299#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
10300#define GPIO_AFRH_AFSEL10_Pos (8U)
10301#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
10302#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
10303#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
10304#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
10305#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
10306#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
10307#define GPIO_AFRH_AFSEL11_Pos (12U)
10308#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
10309#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
10310#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
10311#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
10312#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
10313#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
10314#define GPIO_AFRH_AFSEL12_Pos (16U)
10315#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
10316#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
10317#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
10318#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
10319#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
10320#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
10321#define GPIO_AFRH_AFSEL13_Pos (20U)
10322#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
10323#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
10324#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
10325#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
10326#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
10327#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
10328#define GPIO_AFRH_AFSEL14_Pos (24U)
10329#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
10330#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
10331#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
10332#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
10333#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
10334#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
10335#define GPIO_AFRH_AFSEL15_Pos (28U)
10336#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
10337#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
10338#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
10339#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
10340#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
10341#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
10342
10343/* Legacy defines */
10344#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
10345#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
10346#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
10347#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
10348#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
10349#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
10350#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
10351#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
10352
10353/****************** Bits definition for GPIO_BRR register ******************/
10354#define GPIO_BRR_BR0_Pos (0U)
10355#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
10356#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
10357#define GPIO_BRR_BR1_Pos (1U)
10358#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
10359#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
10360#define GPIO_BRR_BR2_Pos (2U)
10361#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
10362#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
10363#define GPIO_BRR_BR3_Pos (3U)
10364#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
10365#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
10366#define GPIO_BRR_BR4_Pos (4U)
10367#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
10368#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
10369#define GPIO_BRR_BR5_Pos (5U)
10370#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
10371#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
10372#define GPIO_BRR_BR6_Pos (6U)
10373#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
10374#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
10375#define GPIO_BRR_BR7_Pos (7U)
10376#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
10377#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
10378#define GPIO_BRR_BR8_Pos (8U)
10379#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
10380#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
10381#define GPIO_BRR_BR9_Pos (9U)
10382#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
10383#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
10384#define GPIO_BRR_BR10_Pos (10U)
10385#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
10386#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
10387#define GPIO_BRR_BR11_Pos (11U)
10388#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
10389#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
10390#define GPIO_BRR_BR12_Pos (12U)
10391#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
10392#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
10393#define GPIO_BRR_BR13_Pos (13U)
10394#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
10395#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
10396#define GPIO_BRR_BR14_Pos (14U)
10397#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
10398#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
10399#define GPIO_BRR_BR15_Pos (15U)
10400#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
10401#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
10402
10403/* Legacy defines */
10404#define GPIO_BRR_BR_0 GPIO_BRR_BR0
10405#define GPIO_BRR_BR_1 GPIO_BRR_BR1
10406#define GPIO_BRR_BR_2 GPIO_BRR_BR2
10407#define GPIO_BRR_BR_3 GPIO_BRR_BR3
10408#define GPIO_BRR_BR_4 GPIO_BRR_BR4
10409#define GPIO_BRR_BR_5 GPIO_BRR_BR5
10410#define GPIO_BRR_BR_6 GPIO_BRR_BR6
10411#define GPIO_BRR_BR_7 GPIO_BRR_BR7
10412#define GPIO_BRR_BR_8 GPIO_BRR_BR8
10413#define GPIO_BRR_BR_9 GPIO_BRR_BR9
10414#define GPIO_BRR_BR_10 GPIO_BRR_BR10
10415#define GPIO_BRR_BR_11 GPIO_BRR_BR11
10416#define GPIO_BRR_BR_12 GPIO_BRR_BR12
10417#define GPIO_BRR_BR_13 GPIO_BRR_BR13
10418#define GPIO_BRR_BR_14 GPIO_BRR_BR14
10419#define GPIO_BRR_BR_15 GPIO_BRR_BR15
10420
10421
10422
10423/******************************************************************************/
10424/* */
10425/* HASH */
10426/* */
10427/******************************************************************************/
10428/****************** Bits definition for HASH_CR register ********************/
10429#define HASH_CR_INIT_Pos (2U)
10430#define HASH_CR_INIT_Msk (0x1U << HASH_CR_INIT_Pos) /*!< 0x00000004 */
10431#define HASH_CR_INIT HASH_CR_INIT_Msk
10432#define HASH_CR_DMAE_Pos (3U)
10433#define HASH_CR_DMAE_Msk (0x1U << HASH_CR_DMAE_Pos) /*!< 0x00000008 */
10434#define HASH_CR_DMAE HASH_CR_DMAE_Msk
10435#define HASH_CR_DATATYPE_Pos (4U)
10436#define HASH_CR_DATATYPE_Msk (0x3U << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */
10437#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk
10438#define HASH_CR_DATATYPE_0 (0x1U << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */
10439#define HASH_CR_DATATYPE_1 (0x2U << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */
10440#define HASH_CR_MODE_Pos (6U)
10441#define HASH_CR_MODE_Msk (0x1U << HASH_CR_MODE_Pos) /*!< 0x00000040 */
10442#define HASH_CR_MODE HASH_CR_MODE_Msk
10443#define HASH_CR_ALGO_Pos (7U)
10444#define HASH_CR_ALGO_Msk (0x801U << HASH_CR_ALGO_Pos) /*!< 0x00040080 */
10445#define HASH_CR_ALGO HASH_CR_ALGO_Msk
10446#define HASH_CR_ALGO_0 (0x001U << HASH_CR_ALGO_Pos) /*!< 0x00000080 */
10447#define HASH_CR_ALGO_1 (0x800U << HASH_CR_ALGO_Pos) /*!< 0x00040000 */
10448#define HASH_CR_NBW_Pos (8U)
10449#define HASH_CR_NBW_Msk (0xFU << HASH_CR_NBW_Pos) /*!< 0x00000F00 */
10450#define HASH_CR_NBW HASH_CR_NBW_Msk
10451#define HASH_CR_NBW_0 (0x1U << HASH_CR_NBW_Pos) /*!< 0x00000100 */
10452#define HASH_CR_NBW_1 (0x2U << HASH_CR_NBW_Pos) /*!< 0x00000200 */
10453#define HASH_CR_NBW_2 (0x4U << HASH_CR_NBW_Pos) /*!< 0x00000400 */
10454#define HASH_CR_NBW_3 (0x8U << HASH_CR_NBW_Pos) /*!< 0x00000800 */
10455#define HASH_CR_DINNE_Pos (12U)
10456#define HASH_CR_DINNE_Msk (0x1U << HASH_CR_DINNE_Pos) /*!< 0x00001000 */
10457#define HASH_CR_DINNE HASH_CR_DINNE_Msk
10458#define HASH_CR_MDMAT_Pos (13U)
10459#define HASH_CR_MDMAT_Msk (0x1U << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */
10460#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk
10461#define HASH_CR_LKEY_Pos (16U)
10462#define HASH_CR_LKEY_Msk (0x1U << HASH_CR_LKEY_Pos) /*!< 0x00010000 */
10463#define HASH_CR_LKEY HASH_CR_LKEY_Msk
10464
10465/****************** Bits definition for HASH_STR register *******************/
10466#define HASH_STR_NBLW_Pos (0U)
10467#define HASH_STR_NBLW_Msk (0x1FU << HASH_STR_NBLW_Pos) /*!< 0x0000001F */
10468#define HASH_STR_NBLW HASH_STR_NBLW_Msk
10469#define HASH_STR_NBLW_0 (0x01U << HASH_STR_NBLW_Pos) /*!< 0x00000001 */
10470#define HASH_STR_NBLW_1 (0x02U << HASH_STR_NBLW_Pos) /*!< 0x00000002 */
10471#define HASH_STR_NBLW_2 (0x04U << HASH_STR_NBLW_Pos) /*!< 0x00000004 */
10472#define HASH_STR_NBLW_3 (0x08U << HASH_STR_NBLW_Pos) /*!< 0x00000008 */
10473#define HASH_STR_NBLW_4 (0x10U << HASH_STR_NBLW_Pos) /*!< 0x00000010 */
10474#define HASH_STR_DCAL_Pos (8U)
10475#define HASH_STR_DCAL_Msk (0x1U << HASH_STR_DCAL_Pos) /*!< 0x00000100 */
10476#define HASH_STR_DCAL HASH_STR_DCAL_Msk
10477
10478/****************** Bits definition for HASH_IMR register *******************/
10479#define HASH_IMR_DINIE_Pos (0U)
10480#define HASH_IMR_DINIE_Msk (0x1U << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */
10481#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk
10482#define HASH_IMR_DCIE_Pos (1U)
10483#define HASH_IMR_DCIE_Msk (0x1U << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */
10484#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk
10485
10486/****************** Bits definition for HASH_SR register ********************/
10487#define HASH_SR_DINIS_Pos (0U)
10488#define HASH_SR_DINIS_Msk (0x1U << HASH_SR_DINIS_Pos) /*!< 0x00000001 */
10489#define HASH_SR_DINIS HASH_SR_DINIS_Msk
10490#define HASH_SR_DCIS_Pos (1U)
10491#define HASH_SR_DCIS_Msk (0x1U << HASH_SR_DCIS_Pos) /*!< 0x00000002 */
10492#define HASH_SR_DCIS HASH_SR_DCIS_Msk
10493#define HASH_SR_DMAS_Pos (2U)
10494#define HASH_SR_DMAS_Msk (0x1U << HASH_SR_DMAS_Pos) /*!< 0x00000004 */
10495#define HASH_SR_DMAS HASH_SR_DMAS_Msk
10496#define HASH_SR_BUSY_Pos (3U)
10497#define HASH_SR_BUSY_Msk (0x1U << HASH_SR_BUSY_Pos) /*!< 0x00000008 */
10498#define HASH_SR_BUSY HASH_SR_BUSY_Msk
10499
10500/******************************************************************************/
10501/* */
10502/* Inter-integrated Circuit Interface (I2C) */
10503/* */
10504/******************************************************************************/
10505/******************* Bit definition for I2C_CR1 register *******************/
10506#define I2C_CR1_PE_Pos (0U)
10507#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
10508#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
10509#define I2C_CR1_TXIE_Pos (1U)
10510#define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
10511#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
10512#define I2C_CR1_RXIE_Pos (2U)
10513#define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
10514#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
10515#define I2C_CR1_ADDRIE_Pos (3U)
10516#define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
10517#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
10518#define I2C_CR1_NACKIE_Pos (4U)
10519#define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
10520#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
10521#define I2C_CR1_STOPIE_Pos (5U)
10522#define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
10523#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
10524#define I2C_CR1_TCIE_Pos (6U)
10525#define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
10526#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
10527#define I2C_CR1_ERRIE_Pos (7U)
10528#define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
10529#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
10530#define I2C_CR1_DNF_Pos (8U)
10531#define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
10532#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
10533#define I2C_CR1_ANFOFF_Pos (12U)
10534#define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
10535#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
10536#define I2C_CR1_SWRST_Pos (13U)
10537#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
10538#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
10539#define I2C_CR1_TXDMAEN_Pos (14U)
10540#define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
10541#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
10542#define I2C_CR1_RXDMAEN_Pos (15U)
10543#define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
10544#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
10545#define I2C_CR1_SBC_Pos (16U)
10546#define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
10547#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
10548#define I2C_CR1_NOSTRETCH_Pos (17U)
10549#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
10550#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
10551#define I2C_CR1_WUPEN_Pos (18U)
10552#define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
10553#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
10554#define I2C_CR1_GCEN_Pos (19U)
10555#define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
10556#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
10557#define I2C_CR1_SMBHEN_Pos (20U)
10558#define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
10559#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
10560#define I2C_CR1_SMBDEN_Pos (21U)
10561#define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
10562#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
10563#define I2C_CR1_ALERTEN_Pos (22U)
10564#define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
10565#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
10566#define I2C_CR1_PECEN_Pos (23U)
10567#define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
10568#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
10569
10570/****************** Bit definition for I2C_CR2 register ********************/
10571#define I2C_CR2_SADD_Pos (0U)
10572#define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
10573#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
10574#define I2C_CR2_RD_WRN_Pos (10U)
10575#define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
10576#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
10577#define I2C_CR2_ADD10_Pos (11U)
10578#define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
10579#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
10580#define I2C_CR2_HEAD10R_Pos (12U)
10581#define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
10582#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
10583#define I2C_CR2_START_Pos (13U)
10584#define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
10585#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
10586#define I2C_CR2_STOP_Pos (14U)
10587#define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
10588#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
10589#define I2C_CR2_NACK_Pos (15U)
10590#define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
10591#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
10592#define I2C_CR2_NBYTES_Pos (16U)
10593#define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
10594#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
10595#define I2C_CR2_RELOAD_Pos (24U)
10596#define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
10597#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
10598#define I2C_CR2_AUTOEND_Pos (25U)
10599#define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
10600#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
10601#define I2C_CR2_PECBYTE_Pos (26U)
10602#define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
10603#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
10604
10605/******************* Bit definition for I2C_OAR1 register ******************/
10606#define I2C_OAR1_OA1_Pos (0U)
10607#define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
10608#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
10609#define I2C_OAR1_OA1MODE_Pos (10U)
10610#define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
10611#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
10612#define I2C_OAR1_OA1EN_Pos (15U)
10613#define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
10614#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
10615
10616/******************* Bit definition for I2C_OAR2 register ******************/
10617#define I2C_OAR2_OA2_Pos (1U)
10618#define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
10619#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
10620#define I2C_OAR2_OA2MSK_Pos (8U)
10621#define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
10622#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
10623#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
10624#define I2C_OAR2_OA2MASK01_Pos (8U)
10625#define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
10626#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
10627#define I2C_OAR2_OA2MASK02_Pos (9U)
10628#define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
10629#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
10630#define I2C_OAR2_OA2MASK03_Pos (8U)
10631#define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
10632#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
10633#define I2C_OAR2_OA2MASK04_Pos (10U)
10634#define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
10635#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
10636#define I2C_OAR2_OA2MASK05_Pos (8U)
10637#define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
10638#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
10639#define I2C_OAR2_OA2MASK06_Pos (9U)
10640#define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
10641#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
10642#define I2C_OAR2_OA2MASK07_Pos (8U)
10643#define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
10644#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
10645#define I2C_OAR2_OA2EN_Pos (15U)
10646#define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
10647#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
10648
10649/******************* Bit definition for I2C_TIMINGR register *******************/
10650#define I2C_TIMINGR_SCLL_Pos (0U)
10651#define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
10652#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
10653#define I2C_TIMINGR_SCLH_Pos (8U)
10654#define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
10655#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
10656#define I2C_TIMINGR_SDADEL_Pos (16U)
10657#define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
10658#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
10659#define I2C_TIMINGR_SCLDEL_Pos (20U)
10660#define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
10661#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
10662#define I2C_TIMINGR_PRESC_Pos (28U)
10663#define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
10664#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
10665
10666/******************* Bit definition for I2C_TIMEOUTR register *******************/
10667#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
10668#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
10669#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
10670#define I2C_TIMEOUTR_TIDLE_Pos (12U)
10671#define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
10672#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
10673#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
10674#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
10675#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
10676#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
10677#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
10678#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
10679#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
10680#define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
10681#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
10682
10683/****************** Bit definition for I2C_ISR register *********************/
10684#define I2C_ISR_TXE_Pos (0U)
10685#define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
10686#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
10687#define I2C_ISR_TXIS_Pos (1U)
10688#define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
10689#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
10690#define I2C_ISR_RXNE_Pos (2U)
10691#define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
10692#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
10693#define I2C_ISR_ADDR_Pos (3U)
10694#define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
10695#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
10696#define I2C_ISR_NACKF_Pos (4U)
10697#define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
10698#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
10699#define I2C_ISR_STOPF_Pos (5U)
10700#define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
10701#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
10702#define I2C_ISR_TC_Pos (6U)
10703#define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
10704#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
10705#define I2C_ISR_TCR_Pos (7U)
10706#define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
10707#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
10708#define I2C_ISR_BERR_Pos (8U)
10709#define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
10710#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
10711#define I2C_ISR_ARLO_Pos (9U)
10712#define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
10713#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
10714#define I2C_ISR_OVR_Pos (10U)
10715#define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
10716#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
10717#define I2C_ISR_PECERR_Pos (11U)
10718#define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
10719#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
10720#define I2C_ISR_TIMEOUT_Pos (12U)
10721#define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
10722#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
10723#define I2C_ISR_ALERT_Pos (13U)
10724#define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
10725#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
10726#define I2C_ISR_BUSY_Pos (15U)
10727#define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
10728#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
10729#define I2C_ISR_DIR_Pos (16U)
10730#define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
10731#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
10732#define I2C_ISR_ADDCODE_Pos (17U)
10733#define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
10734#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
10735
10736/****************** Bit definition for I2C_ICR register *********************/
10737#define I2C_ICR_ADDRCF_Pos (3U)
10738#define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
10739#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
10740#define I2C_ICR_NACKCF_Pos (4U)
10741#define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
10742#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
10743#define I2C_ICR_STOPCF_Pos (5U)
10744#define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
10745#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
10746#define I2C_ICR_BERRCF_Pos (8U)
10747#define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
10748#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
10749#define I2C_ICR_ARLOCF_Pos (9U)
10750#define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
10751#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
10752#define I2C_ICR_OVRCF_Pos (10U)
10753#define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
10754#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
10755#define I2C_ICR_PECCF_Pos (11U)
10756#define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
10757#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
10758#define I2C_ICR_TIMOUTCF_Pos (12U)
10759#define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
10760#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
10761#define I2C_ICR_ALERTCF_Pos (13U)
10762#define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
10763#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
10764
10765/****************** Bit definition for I2C_PECR register *********************/
10766#define I2C_PECR_PEC_Pos (0U)
10767#define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
10768#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
10769
10770/****************** Bit definition for I2C_RXDR register *********************/
10771#define I2C_RXDR_RXDATA_Pos (0U)
10772#define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
10773#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
10774
10775/****************** Bit definition for I2C_TXDR register *********************/
10776#define I2C_TXDR_TXDATA_Pos (0U)
10777#define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
10778#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
10779
10780/******************************************************************************/
10781/* */
10782/* Independent WATCHDOG */
10783/* */
10784/******************************************************************************/
10785/******************* Bit definition for IWDG_KR register ********************/
10786#define IWDG_KR_KEY_Pos (0U)
10787#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
10788#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
10789
10790/******************* Bit definition for IWDG_PR register ********************/
10791#define IWDG_PR_PR_Pos (0U)
10792#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
10793#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
10794#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
10795#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
10796#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
10797
10798/******************* Bit definition for IWDG_RLR register *******************/
10799#define IWDG_RLR_RL_Pos (0U)
10800#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
10801#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
10802
10803/******************* Bit definition for IWDG_SR register ********************/
10804#define IWDG_SR_PVU_Pos (0U)
10805#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
10806#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
10807#define IWDG_SR_RVU_Pos (1U)
10808#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
10809#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
10810#define IWDG_SR_WVU_Pos (2U)
10811#define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
10812#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
10813
10814/******************* Bit definition for IWDG_KR register ********************/
10815#define IWDG_WINR_WIN_Pos (0U)
10816#define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
10817#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
10818
10819/******************************************************************************/
10820/* */
10821/* Firewall */
10822/* */
10823/******************************************************************************/
10824
10825/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
10826#define FW_CSSA_ADD_Pos (8U)
10827#define FW_CSSA_ADD_Msk (0xFFFFU << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
10828#define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
10829#define FW_CSL_LENG_Pos (8U)
10830#define FW_CSL_LENG_Msk (0x3FFFU << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
10831#define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
10832#define FW_NVDSSA_ADD_Pos (8U)
10833#define FW_NVDSSA_ADD_Msk (0xFFFFU << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
10834#define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
10835#define FW_NVDSL_LENG_Pos (8U)
10836#define FW_NVDSL_LENG_Msk (0x3FFFU << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
10837#define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
10838#define FW_VDSSA_ADD_Pos (6U)
10839#define FW_VDSSA_ADD_Msk (0xFFFU << FW_VDSSA_ADD_Pos) /*!< 0x0003FFC0 */
10840#define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
10841#define FW_VDSL_LENG_Pos (6U)
10842#define FW_VDSL_LENG_Msk (0xFFFU << FW_VDSL_LENG_Pos) /*!< 0x0003FFC0 */
10843#define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
10844
10845/**************************Bit definition for CR register *********************/
10846#define FW_CR_FPA_Pos (0U)
10847#define FW_CR_FPA_Msk (0x1U << FW_CR_FPA_Pos) /*!< 0x00000001 */
10848#define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
10849#define FW_CR_VDS_Pos (1U)
10850#define FW_CR_VDS_Msk (0x1U << FW_CR_VDS_Pos) /*!< 0x00000002 */
10851#define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
10852#define FW_CR_VDE_Pos (2U)
10853#define FW_CR_VDE_Msk (0x1U << FW_CR_VDE_Pos) /*!< 0x00000004 */
10854#define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
10855
10856/******************************************************************************/
10857/* */
10858/* Power Control */
10859/* */
10860/******************************************************************************/
10861
10862/******************** Bit definition for PWR_CR1 register ********************/
10863
10864#define PWR_CR1_LPR_Pos (14U)
10865#define PWR_CR1_LPR_Msk (0x1U << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
10866#define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator low-power mode */
10867#define PWR_CR1_VOS_Pos (9U)
10868#define PWR_CR1_VOS_Msk (0x3U << PWR_CR1_VOS_Pos) /*!< 0x00000600 */
10869#define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
10870#define PWR_CR1_VOS_0 (0x1U << PWR_CR1_VOS_Pos) /*!< 0x00000200 */
10871#define PWR_CR1_VOS_1 (0x2U << PWR_CR1_VOS_Pos) /*!< 0x00000400 */
10872#define PWR_CR1_DBP_Pos (8U)
10873#define PWR_CR1_DBP_Msk (0x1U << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
10874#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
10875#define PWR_CR1_RRSTP_Pos (4U)
10876#define PWR_CR1_RRSTP_Msk (0x1U << PWR_CR1_RRSTP_Pos) /*!< 0x00000010 */
10877#define PWR_CR1_RRSTP PWR_CR1_RRSTP_Msk /*!< SRAM3 Retention in Stop 2 mode */
10878#define PWR_CR1_LPMS_Pos (0U)
10879#define PWR_CR1_LPMS_Msk (0x7U << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
10880#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low-power mode selection field */
10881#define PWR_CR1_LPMS_STOP0 (0x00000000U) /*!< Stop 0 mode */
10882#define PWR_CR1_LPMS_STOP1_Pos (0U)
10883#define PWR_CR1_LPMS_STOP1_Msk (0x1U << PWR_CR1_LPMS_STOP1_Pos) /*!< 0x00000001 */
10884#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk /*!< Stop 1 mode */
10885#define PWR_CR1_LPMS_STOP2_Pos (1U)
10886#define PWR_CR1_LPMS_STOP2_Msk (0x1U << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */
10887#define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */
10888#define PWR_CR1_LPMS_STANDBY_Pos (0U)
10889#define PWR_CR1_LPMS_STANDBY_Msk (0x3U << PWR_CR1_LPMS_STANDBY_Pos) /*!< 0x00000003 */
10890#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk /*!< Stand-by mode */
10891#define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
10892#define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1U << PWR_CR1_LPMS_SHUTDOWN_Pos) /*!< 0x00000004 */
10893#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk /*!< Shut-down mode */
10894
10895
10896/******************** Bit definition for PWR_CR2 register ********************/
10897#define PWR_CR2_USV_Pos (10U)
10898#define PWR_CR2_USV_Msk (0x1U << PWR_CR2_USV_Pos) /*!< 0x00000400 */
10899#define PWR_CR2_USV PWR_CR2_USV_Msk /*!< VDD USB Supply Valid */
10900#define PWR_CR2_IOSV_Pos (9U)
10901#define PWR_CR2_IOSV_Msk (0x1U << PWR_CR2_IOSV_Pos) /*!< 0x00000200 */
10902#define PWR_CR2_IOSV PWR_CR2_IOSV_Msk /*!< VDD IO2 independent I/Os Supply Valid */
10903/*!< PVME Peripheral Voltage Monitor Enable */
10904#define PWR_CR2_PVME_Pos (4U)
10905#define PWR_CR2_PVME_Msk (0xFU << PWR_CR2_PVME_Pos) /*!< 0x000000F0 */
10906#define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< PVM bits field */
10907#define PWR_CR2_PVME4_Pos (7U)
10908#define PWR_CR2_PVME4_Msk (0x1U << PWR_CR2_PVME4_Pos) /*!< 0x00000080 */
10909#define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk /*!< PVM 4 Enable */
10910#define PWR_CR2_PVME3_Pos (6U)
10911#define PWR_CR2_PVME3_Msk (0x1U << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */
10912#define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< PVM 3 Enable */
10913#define PWR_CR2_PVME2_Pos (5U)
10914#define PWR_CR2_PVME2_Msk (0x1U << PWR_CR2_PVME2_Pos) /*!< 0x00000020 */
10915#define PWR_CR2_PVME2 PWR_CR2_PVME2_Msk /*!< PVM 2 Enable */
10916#define PWR_CR2_PVME1_Pos (4U)
10917#define PWR_CR2_PVME1_Msk (0x1U << PWR_CR2_PVME1_Pos) /*!< 0x00000010 */
10918#define PWR_CR2_PVME1 PWR_CR2_PVME1_Msk /*!< PVM 1 Enable */
10919/*!< PVD level configuration */
10920#define PWR_CR2_PLS_Pos (1U)
10921#define PWR_CR2_PLS_Msk (0x7U << PWR_CR2_PLS_Pos) /*!< 0x0000000E */
10922#define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< PVD level selection */
10923#define PWR_CR2_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
10924#define PWR_CR2_PLS_LEV1_Pos (1U)
10925#define PWR_CR2_PLS_LEV1_Msk (0x1U << PWR_CR2_PLS_LEV1_Pos) /*!< 0x00000002 */
10926#define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk /*!< PVD level 1 */
10927#define PWR_CR2_PLS_LEV2_Pos (2U)
10928#define PWR_CR2_PLS_LEV2_Msk (0x1U << PWR_CR2_PLS_LEV2_Pos) /*!< 0x00000004 */
10929#define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk /*!< PVD level 2 */
10930#define PWR_CR2_PLS_LEV3_Pos (1U)
10931#define PWR_CR2_PLS_LEV3_Msk (0x3U << PWR_CR2_PLS_LEV3_Pos) /*!< 0x00000006 */
10932#define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk /*!< PVD level 3 */
10933#define PWR_CR2_PLS_LEV4_Pos (3U)
10934#define PWR_CR2_PLS_LEV4_Msk (0x1U << PWR_CR2_PLS_LEV4_Pos) /*!< 0x00000008 */
10935#define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk /*!< PVD level 4 */
10936#define PWR_CR2_PLS_LEV5_Pos (1U)
10937#define PWR_CR2_PLS_LEV5_Msk (0x5U << PWR_CR2_PLS_LEV5_Pos) /*!< 0x0000000A */
10938#define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk /*!< PVD level 5 */
10939#define PWR_CR2_PLS_LEV6_Pos (2U)
10940#define PWR_CR2_PLS_LEV6_Msk (0x3U << PWR_CR2_PLS_LEV6_Pos) /*!< 0x0000000C */
10941#define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk /*!< PVD level 6 */
10942#define PWR_CR2_PLS_LEV7_Pos (1U)
10943#define PWR_CR2_PLS_LEV7_Msk (0x7U << PWR_CR2_PLS_LEV7_Pos) /*!< 0x0000000E */
10944#define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk /*!< PVD level 7 */
10945#define PWR_CR2_PVDE_Pos (0U)
10946#define PWR_CR2_PVDE_Msk (0x1U << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */
10947#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
10948
10949/******************** Bit definition for PWR_CR3 register ********************/
10950#define PWR_CR3_EIWUL_Pos (15U)
10951#define PWR_CR3_EIWUL_Msk (0x1U << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
10952#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
10953#define PWR_CR3_DSIPDEN_Pos (12U)
10954#define PWR_CR3_DSIPDEN_Msk (0x1U << PWR_CR3_DSIPDEN_Pos) /*!< 0x00001000 */
10955#define PWR_CR3_DSIPDEN PWR_CR3_DSIPDEN_Msk /*!< Disable DSI pads pull-down */
10956#define PWR_CR3_APC_Pos (10U)
10957#define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */
10958#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
10959#define PWR_CR3_RRS_Pos (8U)
10960#define PWR_CR3_RRS_Msk (0x1U << PWR_CR3_RRS_Pos) /*!< 0x00000100 */
10961#define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 Retention in Stand-by mode */
10962#define PWR_CR3_EWUP5_Pos (4U)
10963#define PWR_CR3_EWUP5_Msk (0x1U << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
10964#define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable Wake-Up Pin 5 */
10965#define PWR_CR3_EWUP4_Pos (3U)
10966#define PWR_CR3_EWUP4_Msk (0x1U << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
10967#define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable Wake-Up Pin 4 */
10968#define PWR_CR3_EWUP3_Pos (2U)
10969#define PWR_CR3_EWUP3_Msk (0x1U << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */
10970#define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable Wake-Up Pin 3 */
10971#define PWR_CR3_EWUP2_Pos (1U)
10972#define PWR_CR3_EWUP2_Msk (0x1U << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
10973#define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable Wake-Up Pin 2 */
10974#define PWR_CR3_EWUP1_Pos (0U)
10975#define PWR_CR3_EWUP1_Msk (0x1U << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
10976#define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable Wake-Up Pin 1 */
10977#define PWR_CR3_EWUP_Pos (0U)
10978#define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
10979#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
10980
10981/* Legacy defines */
10982#define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
10983#define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
10984#define PWR_CR3_EIWF PWR_CR3_EIWUL
10985
10986
10987/******************** Bit definition for PWR_CR4 register ********************/
10988#define PWR_CR4_VBRS_Pos (9U)
10989#define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
10990#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
10991#define PWR_CR4_VBE_Pos (8U)
10992#define PWR_CR4_VBE_Msk (0x1U << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
10993#define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
10994#define PWR_CR4_WP5_Pos (4U)
10995#define PWR_CR4_WP5_Msk (0x1U << PWR_CR4_WP5_Pos) /*!< 0x00000010 */
10996#define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */
10997#define PWR_CR4_WP4_Pos (3U)
10998#define PWR_CR4_WP4_Msk (0x1U << PWR_CR4_WP4_Pos) /*!< 0x00000008 */
10999#define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */
11000#define PWR_CR4_WP3_Pos (2U)
11001#define PWR_CR4_WP3_Msk (0x1U << PWR_CR4_WP3_Pos) /*!< 0x00000004 */
11002#define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 polarity */
11003#define PWR_CR4_WP2_Pos (1U)
11004#define PWR_CR4_WP2_Msk (0x1U << PWR_CR4_WP2_Pos) /*!< 0x00000002 */
11005#define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */
11006#define PWR_CR4_WP1_Pos (0U)
11007#define PWR_CR4_WP1_Msk (0x1U << PWR_CR4_WP1_Pos) /*!< 0x00000001 */
11008#define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */
11009
11010/******************** Bit definition for PWR_SR1 register ********************/
11011#define PWR_SR1_WUFI_Pos (15U)
11012#define PWR_SR1_WUFI_Msk (0x1U << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
11013#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wake-Up Flag Internal */
11014#define PWR_SR1_SBF_Pos (8U)
11015#define PWR_SR1_SBF_Msk (0x1U << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
11016#define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */
11017#define PWR_SR1_WUF_Pos (0U)
11018#define PWR_SR1_WUF_Msk (0x1FU << PWR_SR1_WUF_Pos) /*!< 0x0000001F */
11019#define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wake-up Flags */
11020#define PWR_SR1_WUF5_Pos (4U)
11021#define PWR_SR1_WUF5_Msk (0x1U << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */
11022#define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wake-up Flag 5 */
11023#define PWR_SR1_WUF4_Pos (3U)
11024#define PWR_SR1_WUF4_Msk (0x1U << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
11025#define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wake-up Flag 4 */
11026#define PWR_SR1_WUF3_Pos (2U)
11027#define PWR_SR1_WUF3_Msk (0x1U << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */
11028#define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wake-up Flag 3 */
11029#define PWR_SR1_WUF2_Pos (1U)
11030#define PWR_SR1_WUF2_Msk (0x1U << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
11031#define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wake-up Flag 2 */
11032#define PWR_SR1_WUF1_Pos (0U)
11033#define PWR_SR1_WUF1_Msk (0x1U << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
11034#define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wake-up Flag 1 */
11035
11036/******************** Bit definition for PWR_SR2 register ********************/
11037#define PWR_SR2_PVMO4_Pos (15U)
11038#define PWR_SR2_PVMO4_Msk (0x1U << PWR_SR2_PVMO4_Pos) /*!< 0x00008000 */
11039#define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk /*!< Peripheral Voltage Monitoring Output 4 */
11040#define PWR_SR2_PVMO3_Pos (14U)
11041#define PWR_SR2_PVMO3_Msk (0x1U << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */
11042#define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral Voltage Monitoring Output 3 */
11043#define PWR_SR2_PVMO2_Pos (13U)
11044#define PWR_SR2_PVMO2_Msk (0x1U << PWR_SR2_PVMO2_Pos) /*!< 0x00002000 */
11045#define PWR_SR2_PVMO2 PWR_SR2_PVMO2_Msk /*!< Peripheral Voltage Monitoring Output 2 */
11046#define PWR_SR2_PVMO1_Pos (12U)
11047#define PWR_SR2_PVMO1_Msk (0x1U << PWR_SR2_PVMO1_Pos) /*!< 0x00001000 */
11048#define PWR_SR2_PVMO1 PWR_SR2_PVMO1_Msk /*!< Peripheral Voltage Monitoring Output 1 */
11049#define PWR_SR2_PVDO_Pos (11U)
11050#define PWR_SR2_PVDO_Msk (0x1U << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
11051#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power Voltage Detector Output */
11052#define PWR_SR2_VOSF_Pos (10U)
11053#define PWR_SR2_VOSF_Msk (0x1U << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
11054#define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
11055#define PWR_SR2_REGLPF_Pos (9U)
11056#define PWR_SR2_REGLPF_Msk (0x1U << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
11057#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power Regulator Flag */
11058#define PWR_SR2_REGLPS_Pos (8U)
11059#define PWR_SR2_REGLPS_Msk (0x1U << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
11060#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power Regulator Started */
11061
11062/******************** Bit definition for PWR_SCR register ********************/
11063#define PWR_SCR_CSBF_Pos (8U)
11064#define PWR_SCR_CSBF_Msk (0x1U << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
11065#define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Stand-By Flag */
11066#define PWR_SCR_CWUF_Pos (0U)
11067#define PWR_SCR_CWUF_Msk (0x1FU << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */
11068#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
11069#define PWR_SCR_CWUF5_Pos (4U)
11070#define PWR_SCR_CWUF5_Msk (0x1U << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
11071#define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */
11072#define PWR_SCR_CWUF4_Pos (3U)
11073#define PWR_SCR_CWUF4_Msk (0x1U << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
11074#define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
11075#define PWR_SCR_CWUF3_Pos (2U)
11076#define PWR_SCR_CWUF3_Msk (0x1U << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */
11077#define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */
11078#define PWR_SCR_CWUF2_Pos (1U)
11079#define PWR_SCR_CWUF2_Msk (0x1U << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
11080#define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
11081#define PWR_SCR_CWUF1_Pos (0U)
11082#define PWR_SCR_CWUF1_Msk (0x1U << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
11083#define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
11084
11085/******************** Bit definition for PWR_PUCRA register ********************/
11086#define PWR_PUCRA_PA15_Pos (15U)
11087#define PWR_PUCRA_PA15_Msk (0x1U << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */
11088#define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Port PA15 Pull-Up set */
11089#define PWR_PUCRA_PA13_Pos (13U)
11090#define PWR_PUCRA_PA13_Msk (0x1U << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */
11091#define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Port PA13 Pull-Up set */
11092#define PWR_PUCRA_PA12_Pos (12U)
11093#define PWR_PUCRA_PA12_Msk (0x1U << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */
11094#define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Port PA12 Pull-Up set */
11095#define PWR_PUCRA_PA11_Pos (11U)
11096#define PWR_PUCRA_PA11_Msk (0x1U << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */
11097#define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Port PA11 Pull-Up set */
11098#define PWR_PUCRA_PA10_Pos (10U)
11099#define PWR_PUCRA_PA10_Msk (0x1U << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */
11100#define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Port PA10 Pull-Up set */
11101#define PWR_PUCRA_PA9_Pos (9U)
11102#define PWR_PUCRA_PA9_Msk (0x1U << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */
11103#define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Port PA9 Pull-Up set */
11104#define PWR_PUCRA_PA8_Pos (8U)
11105#define PWR_PUCRA_PA8_Msk (0x1U << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */
11106#define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Port PA8 Pull-Up set */
11107#define PWR_PUCRA_PA7_Pos (7U)
11108#define PWR_PUCRA_PA7_Msk (0x1U << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */
11109#define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Port PA7 Pull-Up set */
11110#define PWR_PUCRA_PA6_Pos (6U)
11111#define PWR_PUCRA_PA6_Msk (0x1U << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */
11112#define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Port PA6 Pull-Up set */
11113#define PWR_PUCRA_PA5_Pos (5U)
11114#define PWR_PUCRA_PA5_Msk (0x1U << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */
11115#define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Port PA5 Pull-Up set */
11116#define PWR_PUCRA_PA4_Pos (4U)
11117#define PWR_PUCRA_PA4_Msk (0x1U << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */
11118#define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Port PA4 Pull-Up set */
11119#define PWR_PUCRA_PA3_Pos (3U)
11120#define PWR_PUCRA_PA3_Msk (0x1U << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */
11121#define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Port PA3 Pull-Up set */
11122#define PWR_PUCRA_PA2_Pos (2U)
11123#define PWR_PUCRA_PA2_Msk (0x1U << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */
11124#define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Port PA2 Pull-Up set */
11125#define PWR_PUCRA_PA1_Pos (1U)
11126#define PWR_PUCRA_PA1_Msk (0x1U << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */
11127#define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Port PA1 Pull-Up set */
11128#define PWR_PUCRA_PA0_Pos (0U)
11129#define PWR_PUCRA_PA0_Msk (0x1U << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */
11130#define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Port PA0 Pull-Up set */
11131
11132/******************** Bit definition for PWR_PDCRA register ********************/
11133#define PWR_PDCRA_PA14_Pos (14U)
11134#define PWR_PDCRA_PA14_Msk (0x1U << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */
11135#define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Port PA14 Pull-Down set */
11136#define PWR_PDCRA_PA12_Pos (12U)
11137#define PWR_PDCRA_PA12_Msk (0x1U << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */
11138#define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Port PA12 Pull-Down set */
11139#define PWR_PDCRA_PA11_Pos (11U)
11140#define PWR_PDCRA_PA11_Msk (0x1U << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */
11141#define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Port PA11 Pull-Down set */
11142#define PWR_PDCRA_PA10_Pos (10U)
11143#define PWR_PDCRA_PA10_Msk (0x1U << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */
11144#define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Port PA10 Pull-Down set */
11145#define PWR_PDCRA_PA9_Pos (9U)
11146#define PWR_PDCRA_PA9_Msk (0x1U << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */
11147#define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Port PA9 Pull-Down set */
11148#define PWR_PDCRA_PA8_Pos (8U)
11149#define PWR_PDCRA_PA8_Msk (0x1U << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */
11150#define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Port PA8 Pull-Down set */
11151#define PWR_PDCRA_PA7_Pos (7U)
11152#define PWR_PDCRA_PA7_Msk (0x1U << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */
11153#define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Port PA7 Pull-Down set */
11154#define PWR_PDCRA_PA6_Pos (6U)
11155#define PWR_PDCRA_PA6_Msk (0x1U << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */
11156#define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Port PA6 Pull-Down set */
11157#define PWR_PDCRA_PA5_Pos (5U)
11158#define PWR_PDCRA_PA5_Msk (0x1U << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */
11159#define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Port PA5 Pull-Down set */
11160#define PWR_PDCRA_PA4_Pos (4U)
11161#define PWR_PDCRA_PA4_Msk (0x1U << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */
11162#define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Port PA4 Pull-Down set */
11163#define PWR_PDCRA_PA3_Pos (3U)
11164#define PWR_PDCRA_PA3_Msk (0x1U << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */
11165#define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Port PA3 Pull-Down set */
11166#define PWR_PDCRA_PA2_Pos (2U)
11167#define PWR_PDCRA_PA2_Msk (0x1U << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */
11168#define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Port PA2 Pull-Down set */
11169#define PWR_PDCRA_PA1_Pos (1U)
11170#define PWR_PDCRA_PA1_Msk (0x1U << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */
11171#define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Port PA1 Pull-Down set */
11172#define PWR_PDCRA_PA0_Pos (0U)
11173#define PWR_PDCRA_PA0_Msk (0x1U << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */
11174#define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Port PA0 Pull-Down set */
11175
11176/******************** Bit definition for PWR_PUCRB register ********************/
11177#define PWR_PUCRB_PB15_Pos (15U)
11178#define PWR_PUCRB_PB15_Msk (0x1U << PWR_PUCRB_PB15_Pos) /*!< 0x00008000 */
11179#define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk /*!< Port PB15 Pull-Up set */
11180#define PWR_PUCRB_PB14_Pos (14U)
11181#define PWR_PUCRB_PB14_Msk (0x1U << PWR_PUCRB_PB14_Pos) /*!< 0x00004000 */
11182#define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk /*!< Port PB14 Pull-Up set */
11183#define PWR_PUCRB_PB13_Pos (13U)
11184#define PWR_PUCRB_PB13_Msk (0x1U << PWR_PUCRB_PB13_Pos) /*!< 0x00002000 */
11185#define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk /*!< Port PB13 Pull-Up set */
11186#define PWR_PUCRB_PB12_Pos (12U)
11187#define PWR_PUCRB_PB12_Msk (0x1U << PWR_PUCRB_PB12_Pos) /*!< 0x00001000 */
11188#define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk /*!< Port PB12 Pull-Up set */
11189#define PWR_PUCRB_PB11_Pos (11U)
11190#define PWR_PUCRB_PB11_Msk (0x1U << PWR_PUCRB_PB11_Pos) /*!< 0x00000800 */
11191#define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk /*!< Port PB11 Pull-Up set */
11192#define PWR_PUCRB_PB10_Pos (10U)
11193#define PWR_PUCRB_PB10_Msk (0x1U << PWR_PUCRB_PB10_Pos) /*!< 0x00000400 */
11194#define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk /*!< Port PB10 Pull-Up set */
11195#define PWR_PUCRB_PB9_Pos (9U)
11196#define PWR_PUCRB_PB9_Msk (0x1U << PWR_PUCRB_PB9_Pos) /*!< 0x00000200 */
11197#define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Port PB9 Pull-Up set */
11198#define PWR_PUCRB_PB8_Pos (8U)
11199#define PWR_PUCRB_PB8_Msk (0x1U << PWR_PUCRB_PB8_Pos) /*!< 0x00000100 */
11200#define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Port PB8 Pull-Up set */
11201#define PWR_PUCRB_PB7_Pos (7U)
11202#define PWR_PUCRB_PB7_Msk (0x1U << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */
11203#define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Port PB7 Pull-Up set */
11204#define PWR_PUCRB_PB6_Pos (6U)
11205#define PWR_PUCRB_PB6_Msk (0x1U << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */
11206#define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Port PB6 Pull-Up set */
11207#define PWR_PUCRB_PB5_Pos (5U)
11208#define PWR_PUCRB_PB5_Msk (0x1U << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */
11209#define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Port PB5 Pull-Up set */
11210#define PWR_PUCRB_PB4_Pos (4U)
11211#define PWR_PUCRB_PB4_Msk (0x1U << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */
11212#define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Port PB4 Pull-Up set */
11213#define PWR_PUCRB_PB3_Pos (3U)
11214#define PWR_PUCRB_PB3_Msk (0x1U << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */
11215#define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Port PB3 Pull-Up set */
11216#define PWR_PUCRB_PB2_Pos (2U)
11217#define PWR_PUCRB_PB2_Msk (0x1U << PWR_PUCRB_PB2_Pos) /*!< 0x00000004 */
11218#define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Port PB2 Pull-Up set */
11219#define PWR_PUCRB_PB1_Pos (1U)
11220#define PWR_PUCRB_PB1_Msk (0x1U << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */
11221#define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Port PB1 Pull-Up set */
11222#define PWR_PUCRB_PB0_Pos (0U)
11223#define PWR_PUCRB_PB0_Msk (0x1U << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */
11224#define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Port PB0 Pull-Up set */
11225
11226/******************** Bit definition for PWR_PDCRB register ********************/
11227#define PWR_PDCRB_PB15_Pos (15U)
11228#define PWR_PDCRB_PB15_Msk (0x1U << PWR_PDCRB_PB15_Pos) /*!< 0x00008000 */
11229#define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk /*!< Port PB15 Pull-Down set */
11230#define PWR_PDCRB_PB14_Pos (14U)
11231#define PWR_PDCRB_PB14_Msk (0x1U << PWR_PDCRB_PB14_Pos) /*!< 0x00004000 */
11232#define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk /*!< Port PB14 Pull-Down set */
11233#define PWR_PDCRB_PB13_Pos (13U)
11234#define PWR_PDCRB_PB13_Msk (0x1U << PWR_PDCRB_PB13_Pos) /*!< 0x00002000 */
11235#define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk /*!< Port PB13 Pull-Down set */
11236#define PWR_PDCRB_PB12_Pos (12U)
11237#define PWR_PDCRB_PB12_Msk (0x1U << PWR_PDCRB_PB12_Pos) /*!< 0x00001000 */
11238#define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk /*!< Port PB12 Pull-Down set */
11239#define PWR_PDCRB_PB11_Pos (11U)
11240#define PWR_PDCRB_PB11_Msk (0x1U << PWR_PDCRB_PB11_Pos) /*!< 0x00000800 */
11241#define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk /*!< Port PB11 Pull-Down set */
11242#define PWR_PDCRB_PB10_Pos (10U)
11243#define PWR_PDCRB_PB10_Msk (0x1U << PWR_PDCRB_PB10_Pos) /*!< 0x00000400 */
11244#define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk /*!< Port PB10 Pull-Down set */
11245#define PWR_PDCRB_PB9_Pos (9U)
11246#define PWR_PDCRB_PB9_Msk (0x1U << PWR_PDCRB_PB9_Pos) /*!< 0x00000200 */
11247#define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Port PB9 Pull-Down set */
11248#define PWR_PDCRB_PB8_Pos (8U)
11249#define PWR_PDCRB_PB8_Msk (0x1U << PWR_PDCRB_PB8_Pos) /*!< 0x00000100 */
11250#define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Port PB8 Pull-Down set */
11251#define PWR_PDCRB_PB7_Pos (7U)
11252#define PWR_PDCRB_PB7_Msk (0x1U << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */
11253#define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Port PB7 Pull-Down set */
11254#define PWR_PDCRB_PB6_Pos (6U)
11255#define PWR_PDCRB_PB6_Msk (0x1U << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */
11256#define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Port PB6 Pull-Down set */
11257#define PWR_PDCRB_PB5_Pos (5U)
11258#define PWR_PDCRB_PB5_Msk (0x1U << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */
11259#define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Port PB5 Pull-Down set */
11260#define PWR_PDCRB_PB3_Pos (3U)
11261#define PWR_PDCRB_PB3_Msk (0x1U << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */
11262#define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Port PB3 Pull-Down set */
11263#define PWR_PDCRB_PB2_Pos (2U)
11264#define PWR_PDCRB_PB2_Msk (0x1U << PWR_PDCRB_PB2_Pos) /*!< 0x00000004 */
11265#define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Port PB2 Pull-Down set */
11266#define PWR_PDCRB_PB1_Pos (1U)
11267#define PWR_PDCRB_PB1_Msk (0x1U << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */
11268#define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Port PB1 Pull-Down set */
11269#define PWR_PDCRB_PB0_Pos (0U)
11270#define PWR_PDCRB_PB0_Msk (0x1U << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */
11271#define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Port PB0 Pull-Down set */
11272
11273/******************** Bit definition for PWR_PUCRC register ********************/
11274#define PWR_PUCRC_PC15_Pos (15U)
11275#define PWR_PUCRC_PC15_Msk (0x1U << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */
11276#define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Port PC15 Pull-Up set */
11277#define PWR_PUCRC_PC14_Pos (14U)
11278#define PWR_PUCRC_PC14_Msk (0x1U << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */
11279#define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Port PC14 Pull-Up set */
11280#define PWR_PUCRC_PC13_Pos (13U)
11281#define PWR_PUCRC_PC13_Msk (0x1U << PWR_PUCRC_PC13_Pos) /*!< 0x00002000 */
11282#define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk /*!< Port PC13 Pull-Up set */
11283#define PWR_PUCRC_PC12_Pos (12U)
11284#define PWR_PUCRC_PC12_Msk (0x1U << PWR_PUCRC_PC12_Pos) /*!< 0x00001000 */
11285#define PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk /*!< Port PC12 Pull-Up set */
11286#define PWR_PUCRC_PC11_Pos (11U)
11287#define PWR_PUCRC_PC11_Msk (0x1U << PWR_PUCRC_PC11_Pos) /*!< 0x00000800 */
11288#define PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk /*!< Port PC11 Pull-Up set */
11289#define PWR_PUCRC_PC10_Pos (10U)
11290#define PWR_PUCRC_PC10_Msk (0x1U << PWR_PUCRC_PC10_Pos) /*!< 0x00000400 */
11291#define PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk /*!< Port PC10 Pull-Up set */
11292#define PWR_PUCRC_PC9_Pos (9U)
11293#define PWR_PUCRC_PC9_Msk (0x1U << PWR_PUCRC_PC9_Pos) /*!< 0x00000200 */
11294#define PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk /*!< Port PC9 Pull-Up set */
11295#define PWR_PUCRC_PC8_Pos (8U)
11296#define PWR_PUCRC_PC8_Msk (0x1U << PWR_PUCRC_PC8_Pos) /*!< 0x00000100 */
11297#define PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk /*!< Port PC8 Pull-Up set */
11298#define PWR_PUCRC_PC7_Pos (7U)
11299#define PWR_PUCRC_PC7_Msk (0x1U << PWR_PUCRC_PC7_Pos) /*!< 0x00000080 */
11300#define PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk /*!< Port PC7 Pull-Up set */
11301#define PWR_PUCRC_PC6_Pos (6U)
11302#define PWR_PUCRC_PC6_Msk (0x1U << PWR_PUCRC_PC6_Pos) /*!< 0x00000040 */
11303#define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk /*!< Port PC6 Pull-Up set */
11304#define PWR_PUCRC_PC5_Pos (5U)
11305#define PWR_PUCRC_PC5_Msk (0x1U << PWR_PUCRC_PC5_Pos) /*!< 0x00000020 */
11306#define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk /*!< Port PC5 Pull-Up set */
11307#define PWR_PUCRC_PC4_Pos (4U)
11308#define PWR_PUCRC_PC4_Msk (0x1U << PWR_PUCRC_PC4_Pos) /*!< 0x00000010 */
11309#define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk /*!< Port PC4 Pull-Up set */
11310#define PWR_PUCRC_PC3_Pos (3U)
11311#define PWR_PUCRC_PC3_Msk (0x1U << PWR_PUCRC_PC3_Pos) /*!< 0x00000008 */
11312#define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk /*!< Port PC3 Pull-Up set */
11313#define PWR_PUCRC_PC2_Pos (2U)
11314#define PWR_PUCRC_PC2_Msk (0x1U << PWR_PUCRC_PC2_Pos) /*!< 0x00000004 */
11315#define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk /*!< Port PC2 Pull-Up set */
11316#define PWR_PUCRC_PC1_Pos (1U)
11317#define PWR_PUCRC_PC1_Msk (0x1U << PWR_PUCRC_PC1_Pos) /*!< 0x00000002 */
11318#define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk /*!< Port PC1 Pull-Up set */
11319#define PWR_PUCRC_PC0_Pos (0U)
11320#define PWR_PUCRC_PC0_Msk (0x1U << PWR_PUCRC_PC0_Pos) /*!< 0x00000001 */
11321#define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk /*!< Port PC0 Pull-Up set */
11322
11323/******************** Bit definition for PWR_PDCRC register ********************/
11324#define PWR_PDCRC_PC15_Pos (15U)
11325#define PWR_PDCRC_PC15_Msk (0x1U << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */
11326#define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Port PC15 Pull-Down set */
11327#define PWR_PDCRC_PC14_Pos (14U)
11328#define PWR_PDCRC_PC14_Msk (0x1U << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */
11329#define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Port PC14 Pull-Down set */
11330#define PWR_PDCRC_PC13_Pos (13U)
11331#define PWR_PDCRC_PC13_Msk (0x1U << PWR_PDCRC_PC13_Pos) /*!< 0x00002000 */
11332#define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk /*!< Port PC13 Pull-Down set */
11333#define PWR_PDCRC_PC12_Pos (12U)
11334#define PWR_PDCRC_PC12_Msk (0x1U << PWR_PDCRC_PC12_Pos) /*!< 0x00001000 */
11335#define PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk /*!< Port PC12 Pull-Down set */
11336#define PWR_PDCRC_PC11_Pos (11U)
11337#define PWR_PDCRC_PC11_Msk (0x1U << PWR_PDCRC_PC11_Pos) /*!< 0x00000800 */
11338#define PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk /*!< Port PC11 Pull-Down set */
11339#define PWR_PDCRC_PC10_Pos (10U)
11340#define PWR_PDCRC_PC10_Msk (0x1U << PWR_PDCRC_PC10_Pos) /*!< 0x00000400 */
11341#define PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk /*!< Port PC10 Pull-Down set */
11342#define PWR_PDCRC_PC9_Pos (9U)
11343#define PWR_PDCRC_PC9_Msk (0x1U << PWR_PDCRC_PC9_Pos) /*!< 0x00000200 */
11344#define PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk /*!< Port PC9 Pull-Down set */
11345#define PWR_PDCRC_PC8_Pos (8U)
11346#define PWR_PDCRC_PC8_Msk (0x1U << PWR_PDCRC_PC8_Pos) /*!< 0x00000100 */
11347#define PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk /*!< Port PC8 Pull-Down set */
11348#define PWR_PDCRC_PC7_Pos (7U)
11349#define PWR_PDCRC_PC7_Msk (0x1U << PWR_PDCRC_PC7_Pos) /*!< 0x00000080 */
11350#define PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk /*!< Port PC7 Pull-Down set */
11351#define PWR_PDCRC_PC6_Pos (6U)
11352#define PWR_PDCRC_PC6_Msk (0x1U << PWR_PDCRC_PC6_Pos) /*!< 0x00000040 */
11353#define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk /*!< Port PC6 Pull-Down set */
11354#define PWR_PDCRC_PC5_Pos (5U)
11355#define PWR_PDCRC_PC5_Msk (0x1U << PWR_PDCRC_PC5_Pos) /*!< 0x00000020 */
11356#define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk /*!< Port PC5 Pull-Down set */
11357#define PWR_PDCRC_PC4_Pos (4U)
11358#define PWR_PDCRC_PC4_Msk (0x1U << PWR_PDCRC_PC4_Pos) /*!< 0x00000010 */
11359#define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk /*!< Port PC4 Pull-Down set */
11360#define PWR_PDCRC_PC3_Pos (3U)
11361#define PWR_PDCRC_PC3_Msk (0x1U << PWR_PDCRC_PC3_Pos) /*!< 0x00000008 */
11362#define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk /*!< Port PC3 Pull-Down set */
11363#define PWR_PDCRC_PC2_Pos (2U)
11364#define PWR_PDCRC_PC2_Msk (0x1U << PWR_PDCRC_PC2_Pos) /*!< 0x00000004 */
11365#define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk /*!< Port PC2 Pull-Down set */
11366#define PWR_PDCRC_PC1_Pos (1U)
11367#define PWR_PDCRC_PC1_Msk (0x1U << PWR_PDCRC_PC1_Pos) /*!< 0x00000002 */
11368#define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk /*!< Port PC1 Pull-Down set */
11369#define PWR_PDCRC_PC0_Pos (0U)
11370#define PWR_PDCRC_PC0_Msk (0x1U << PWR_PDCRC_PC0_Pos) /*!< 0x00000001 */
11371#define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk /*!< Port PC0 Pull-Down set */
11372
11373/******************** Bit definition for PWR_PUCRD register ********************/
11374#define PWR_PUCRD_PD15_Pos (15U)
11375#define PWR_PUCRD_PD15_Msk (0x1U << PWR_PUCRD_PD15_Pos) /*!< 0x00008000 */
11376#define PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk /*!< Port PD15 Pull-Up set */
11377#define PWR_PUCRD_PD14_Pos (14U)
11378#define PWR_PUCRD_PD14_Msk (0x1U << PWR_PUCRD_PD14_Pos) /*!< 0x00004000 */
11379#define PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk /*!< Port PD14 Pull-Up set */
11380#define PWR_PUCRD_PD13_Pos (13U)
11381#define PWR_PUCRD_PD13_Msk (0x1U << PWR_PUCRD_PD13_Pos) /*!< 0x00002000 */
11382#define PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk /*!< Port PD13 Pull-Up set */
11383#define PWR_PUCRD_PD12_Pos (12U)
11384#define PWR_PUCRD_PD12_Msk (0x1U << PWR_PUCRD_PD12_Pos) /*!< 0x00001000 */
11385#define PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk /*!< Port PD12 Pull-Up set */
11386#define PWR_PUCRD_PD11_Pos (11U)
11387#define PWR_PUCRD_PD11_Msk (0x1U << PWR_PUCRD_PD11_Pos) /*!< 0x00000800 */
11388#define PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk /*!< Port PD11 Pull-Up set */
11389#define PWR_PUCRD_PD10_Pos (10U)
11390#define PWR_PUCRD_PD10_Msk (0x1U << PWR_PUCRD_PD10_Pos) /*!< 0x00000400 */
11391#define PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk /*!< Port PD10 Pull-Up set */
11392#define PWR_PUCRD_PD9_Pos (9U)
11393#define PWR_PUCRD_PD9_Msk (0x1U << PWR_PUCRD_PD9_Pos) /*!< 0x00000200 */
11394#define PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk /*!< Port PD9 Pull-Up set */
11395#define PWR_PUCRD_PD8_Pos (8U)
11396#define PWR_PUCRD_PD8_Msk (0x1U << PWR_PUCRD_PD8_Pos) /*!< 0x00000100 */
11397#define PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk /*!< Port PD8 Pull-Up set */
11398#define PWR_PUCRD_PD7_Pos (7U)
11399#define PWR_PUCRD_PD7_Msk (0x1U << PWR_PUCRD_PD7_Pos) /*!< 0x00000080 */
11400#define PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk /*!< Port PD7 Pull-Up set */
11401#define PWR_PUCRD_PD6_Pos (6U)
11402#define PWR_PUCRD_PD6_Msk (0x1U << PWR_PUCRD_PD6_Pos) /*!< 0x00000040 */
11403#define PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk /*!< Port PD6 Pull-Up set */
11404#define PWR_PUCRD_PD5_Pos (5U)
11405#define PWR_PUCRD_PD5_Msk (0x1U << PWR_PUCRD_PD5_Pos) /*!< 0x00000020 */
11406#define PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk /*!< Port PD5 Pull-Up set */
11407#define PWR_PUCRD_PD4_Pos (4U)
11408#define PWR_PUCRD_PD4_Msk (0x1U << PWR_PUCRD_PD4_Pos) /*!< 0x00000010 */
11409#define PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk /*!< Port PD4 Pull-Up set */
11410#define PWR_PUCRD_PD3_Pos (3U)
11411#define PWR_PUCRD_PD3_Msk (0x1U << PWR_PUCRD_PD3_Pos) /*!< 0x00000008 */
11412#define PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk /*!< Port PD3 Pull-Up set */
11413#define PWR_PUCRD_PD2_Pos (2U)
11414#define PWR_PUCRD_PD2_Msk (0x1U << PWR_PUCRD_PD2_Pos) /*!< 0x00000004 */
11415#define PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk /*!< Port PD2 Pull-Up set */
11416#define PWR_PUCRD_PD1_Pos (1U)
11417#define PWR_PUCRD_PD1_Msk (0x1U << PWR_PUCRD_PD1_Pos) /*!< 0x00000002 */
11418#define PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk /*!< Port PD1 Pull-Up set */
11419#define PWR_PUCRD_PD0_Pos (0U)
11420#define PWR_PUCRD_PD0_Msk (0x1U << PWR_PUCRD_PD0_Pos) /*!< 0x00000001 */
11421#define PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk /*!< Port PD0 Pull-Up set */
11422
11423/******************** Bit definition for PWR_PDCRD register ********************/
11424#define PWR_PDCRD_PD15_Pos (15U)
11425#define PWR_PDCRD_PD15_Msk (0x1U << PWR_PDCRD_PD15_Pos) /*!< 0x00008000 */
11426#define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk /*!< Port PD15 Pull-Down set */
11427#define PWR_PDCRD_PD14_Pos (14U)
11428#define PWR_PDCRD_PD14_Msk (0x1U << PWR_PDCRD_PD14_Pos) /*!< 0x00004000 */
11429#define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk /*!< Port PD14 Pull-Down set */
11430#define PWR_PDCRD_PD13_Pos (13U)
11431#define PWR_PDCRD_PD13_Msk (0x1U << PWR_PDCRD_PD13_Pos) /*!< 0x00002000 */
11432#define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk /*!< Port PD13 Pull-Down set */
11433#define PWR_PDCRD_PD12_Pos (12U)
11434#define PWR_PDCRD_PD12_Msk (0x1U << PWR_PDCRD_PD12_Pos) /*!< 0x00001000 */
11435#define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk /*!< Port PD12 Pull-Down set */
11436#define PWR_PDCRD_PD11_Pos (11U)
11437#define PWR_PDCRD_PD11_Msk (0x1U << PWR_PDCRD_PD11_Pos) /*!< 0x00000800 */
11438#define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk /*!< Port PD11 Pull-Down set */
11439#define PWR_PDCRD_PD10_Pos (10U)
11440#define PWR_PDCRD_PD10_Msk (0x1U << PWR_PDCRD_PD10_Pos) /*!< 0x00000400 */
11441#define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk /*!< Port PD10 Pull-Down set */
11442#define PWR_PDCRD_PD9_Pos (9U)
11443#define PWR_PDCRD_PD9_Msk (0x1U << PWR_PDCRD_PD9_Pos) /*!< 0x00000200 */
11444#define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk /*!< Port PD9 Pull-Down set */
11445#define PWR_PDCRD_PD8_Pos (8U)
11446#define PWR_PDCRD_PD8_Msk (0x1U << PWR_PDCRD_PD8_Pos) /*!< 0x00000100 */
11447#define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk /*!< Port PD8 Pull-Down set */
11448#define PWR_PDCRD_PD7_Pos (7U)
11449#define PWR_PDCRD_PD7_Msk (0x1U << PWR_PDCRD_PD7_Pos) /*!< 0x00000080 */
11450#define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk /*!< Port PD7 Pull-Down set */
11451#define PWR_PDCRD_PD6_Pos (6U)
11452#define PWR_PDCRD_PD6_Msk (0x1U << PWR_PDCRD_PD6_Pos) /*!< 0x00000040 */
11453#define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk /*!< Port PD6 Pull-Down set */
11454#define PWR_PDCRD_PD5_Pos (5U)
11455#define PWR_PDCRD_PD5_Msk (0x1U << PWR_PDCRD_PD5_Pos) /*!< 0x00000020 */
11456#define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk /*!< Port PD5 Pull-Down set */
11457#define PWR_PDCRD_PD4_Pos (4U)
11458#define PWR_PDCRD_PD4_Msk (0x1U << PWR_PDCRD_PD4_Pos) /*!< 0x00000010 */
11459#define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk /*!< Port PD4 Pull-Down set */
11460#define PWR_PDCRD_PD3_Pos (3U)
11461#define PWR_PDCRD_PD3_Msk (0x1U << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */
11462#define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Port PD3 Pull-Down set */
11463#define PWR_PDCRD_PD2_Pos (2U)
11464#define PWR_PDCRD_PD2_Msk (0x1U << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */
11465#define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Port PD2 Pull-Down set */
11466#define PWR_PDCRD_PD1_Pos (1U)
11467#define PWR_PDCRD_PD1_Msk (0x1U << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */
11468#define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Port PD1 Pull-Down set */
11469#define PWR_PDCRD_PD0_Pos (0U)
11470#define PWR_PDCRD_PD0_Msk (0x1U << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
11471#define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Port PD0 Pull-Down set */
11472
11473/******************** Bit definition for PWR_PUCRE register ********************/
11474#define PWR_PUCRE_PE15_Pos (15U)
11475#define PWR_PUCRE_PE15_Msk (0x1U << PWR_PUCRE_PE15_Pos) /*!< 0x00008000 */
11476#define PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk /*!< Port PE15 Pull-Up set */
11477#define PWR_PUCRE_PE14_Pos (14U)
11478#define PWR_PUCRE_PE14_Msk (0x1U << PWR_PUCRE_PE14_Pos) /*!< 0x00004000 */
11479#define PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk /*!< Port PE14 Pull-Up set */
11480#define PWR_PUCRE_PE13_Pos (13U)
11481#define PWR_PUCRE_PE13_Msk (0x1U << PWR_PUCRE_PE13_Pos) /*!< 0x00002000 */
11482#define PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk /*!< Port PE13 Pull-Up set */
11483#define PWR_PUCRE_PE12_Pos (12U)
11484#define PWR_PUCRE_PE12_Msk (0x1U << PWR_PUCRE_PE12_Pos) /*!< 0x00001000 */
11485#define PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk /*!< Port PE12 Pull-Up set */
11486#define PWR_PUCRE_PE11_Pos (11U)
11487#define PWR_PUCRE_PE11_Msk (0x1U << PWR_PUCRE_PE11_Pos) /*!< 0x00000800 */
11488#define PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk /*!< Port PE11 Pull-Up set */
11489#define PWR_PUCRE_PE10_Pos (10U)
11490#define PWR_PUCRE_PE10_Msk (0x1U << PWR_PUCRE_PE10_Pos) /*!< 0x00000400 */
11491#define PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk /*!< Port PE10 Pull-Up set */
11492#define PWR_PUCRE_PE9_Pos (9U)
11493#define PWR_PUCRE_PE9_Msk (0x1U << PWR_PUCRE_PE9_Pos) /*!< 0x00000200 */
11494#define PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk /*!< Port PE9 Pull-Up set */
11495#define PWR_PUCRE_PE8_Pos (8U)
11496#define PWR_PUCRE_PE8_Msk (0x1U << PWR_PUCRE_PE8_Pos) /*!< 0x00000100 */
11497#define PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk /*!< Port PE8 Pull-Up set */
11498#define PWR_PUCRE_PE7_Pos (7U)
11499#define PWR_PUCRE_PE7_Msk (0x1U << PWR_PUCRE_PE7_Pos) /*!< 0x00000080 */
11500#define PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk /*!< Port PE7 Pull-Up set */
11501#define PWR_PUCRE_PE6_Pos (6U)
11502#define PWR_PUCRE_PE6_Msk (0x1U << PWR_PUCRE_PE6_Pos) /*!< 0x00000040 */
11503#define PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk /*!< Port PE6 Pull-Up set */
11504#define PWR_PUCRE_PE5_Pos (5U)
11505#define PWR_PUCRE_PE5_Msk (0x1U << PWR_PUCRE_PE5_Pos) /*!< 0x00000020 */
11506#define PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk /*!< Port PE5 Pull-Up set */
11507#define PWR_PUCRE_PE4_Pos (4U)
11508#define PWR_PUCRE_PE4_Msk (0x1U << PWR_PUCRE_PE4_Pos) /*!< 0x00000010 */
11509#define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk /*!< Port PE4 Pull-Up set */
11510#define PWR_PUCRE_PE3_Pos (3U)
11511#define PWR_PUCRE_PE3_Msk (0x1U << PWR_PUCRE_PE3_Pos) /*!< 0x00000008 */
11512#define PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk /*!< Port PE3 Pull-Up set */
11513#define PWR_PUCRE_PE2_Pos (2U)
11514#define PWR_PUCRE_PE2_Msk (0x1U << PWR_PUCRE_PE2_Pos) /*!< 0x00000004 */
11515#define PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk /*!< Port PE2 Pull-Up set */
11516#define PWR_PUCRE_PE1_Pos (1U)
11517#define PWR_PUCRE_PE1_Msk (0x1U << PWR_PUCRE_PE1_Pos) /*!< 0x00000002 */
11518#define PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk /*!< Port PE1 Pull-Up set */
11519#define PWR_PUCRE_PE0_Pos (0U)
11520#define PWR_PUCRE_PE0_Msk (0x1U << PWR_PUCRE_PE0_Pos) /*!< 0x00000001 */
11521#define PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk /*!< Port PE0 Pull-Up set */
11522
11523/******************** Bit definition for PWR_PDCRE register ********************/
11524#define PWR_PDCRE_PE15_Pos (15U)
11525#define PWR_PDCRE_PE15_Msk (0x1U << PWR_PDCRE_PE15_Pos) /*!< 0x00008000 */
11526#define PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk /*!< Port PE15 Pull-Down set */
11527#define PWR_PDCRE_PE14_Pos (14U)
11528#define PWR_PDCRE_PE14_Msk (0x1U << PWR_PDCRE_PE14_Pos) /*!< 0x00004000 */
11529#define PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk /*!< Port PE14 Pull-Down set */
11530#define PWR_PDCRE_PE13_Pos (13U)
11531#define PWR_PDCRE_PE13_Msk (0x1U << PWR_PDCRE_PE13_Pos) /*!< 0x00002000 */
11532#define PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk /*!< Port PE13 Pull-Down set */
11533#define PWR_PDCRE_PE12_Pos (12U)
11534#define PWR_PDCRE_PE12_Msk (0x1U << PWR_PDCRE_PE12_Pos) /*!< 0x00001000 */
11535#define PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk /*!< Port PE12 Pull-Down set */
11536#define PWR_PDCRE_PE11_Pos (11U)
11537#define PWR_PDCRE_PE11_Msk (0x1U << PWR_PDCRE_PE11_Pos) /*!< 0x00000800 */
11538#define PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk /*!< Port PE11 Pull-Down set */
11539#define PWR_PDCRE_PE10_Pos (10U)
11540#define PWR_PDCRE_PE10_Msk (0x1U << PWR_PDCRE_PE10_Pos) /*!< 0x00000400 */
11541#define PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk /*!< Port PE10 Pull-Down set */
11542#define PWR_PDCRE_PE9_Pos (9U)
11543#define PWR_PDCRE_PE9_Msk (0x1U << PWR_PDCRE_PE9_Pos) /*!< 0x00000200 */
11544#define PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk /*!< Port PE9 Pull-Down set */
11545#define PWR_PDCRE_PE8_Pos (8U)
11546#define PWR_PDCRE_PE8_Msk (0x1U << PWR_PDCRE_PE8_Pos) /*!< 0x00000100 */
11547#define PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk /*!< Port PE8 Pull-Down set */
11548#define PWR_PDCRE_PE7_Pos (7U)
11549#define PWR_PDCRE_PE7_Msk (0x1U << PWR_PDCRE_PE7_Pos) /*!< 0x00000080 */
11550#define PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk /*!< Port PE7 Pull-Down set */
11551#define PWR_PDCRE_PE6_Pos (6U)
11552#define PWR_PDCRE_PE6_Msk (0x1U << PWR_PDCRE_PE6_Pos) /*!< 0x00000040 */
11553#define PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk /*!< Port PE6 Pull-Down set */
11554#define PWR_PDCRE_PE5_Pos (5U)
11555#define PWR_PDCRE_PE5_Msk (0x1U << PWR_PDCRE_PE5_Pos) /*!< 0x00000020 */
11556#define PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk /*!< Port PE5 Pull-Down set */
11557#define PWR_PDCRE_PE4_Pos (4U)
11558#define PWR_PDCRE_PE4_Msk (0x1U << PWR_PDCRE_PE4_Pos) /*!< 0x00000010 */
11559#define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk /*!< Port PE4 Pull-Down set */
11560#define PWR_PDCRE_PE3_Pos (3U)
11561#define PWR_PDCRE_PE3_Msk (0x1U << PWR_PDCRE_PE3_Pos) /*!< 0x00000008 */
11562#define PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk /*!< Port PE3 Pull-Down set */
11563#define PWR_PDCRE_PE2_Pos (2U)
11564#define PWR_PDCRE_PE2_Msk (0x1U << PWR_PDCRE_PE2_Pos) /*!< 0x00000004 */
11565#define PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk /*!< Port PE2 Pull-Down set */
11566#define PWR_PDCRE_PE1_Pos (1U)
11567#define PWR_PDCRE_PE1_Msk (0x1U << PWR_PDCRE_PE1_Pos) /*!< 0x00000002 */
11568#define PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk /*!< Port PE1 Pull-Down set */
11569#define PWR_PDCRE_PE0_Pos (0U)
11570#define PWR_PDCRE_PE0_Msk (0x1U << PWR_PDCRE_PE0_Pos) /*!< 0x00000001 */
11571#define PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk /*!< Port PE0 Pull-Down set */
11572
11573/******************** Bit definition for PWR_PUCRF register ********************/
11574#define PWR_PUCRF_PF15_Pos (15U)
11575#define PWR_PUCRF_PF15_Msk (0x1U << PWR_PUCRF_PF15_Pos) /*!< 0x00008000 */
11576#define PWR_PUCRF_PF15 PWR_PUCRF_PF15_Msk /*!< Port PF15 Pull-Up set */
11577#define PWR_PUCRF_PF14_Pos (14U)
11578#define PWR_PUCRF_PF14_Msk (0x1U << PWR_PUCRF_PF14_Pos) /*!< 0x00004000 */
11579#define PWR_PUCRF_PF14 PWR_PUCRF_PF14_Msk /*!< Port PF14 Pull-Up set */
11580#define PWR_PUCRF_PF13_Pos (13U)
11581#define PWR_PUCRF_PF13_Msk (0x1U << PWR_PUCRF_PF13_Pos) /*!< 0x00002000 */
11582#define PWR_PUCRF_PF13 PWR_PUCRF_PF13_Msk /*!< Port PF13 Pull-Up set */
11583#define PWR_PUCRF_PF12_Pos (12U)
11584#define PWR_PUCRF_PF12_Msk (0x1U << PWR_PUCRF_PF12_Pos) /*!< 0x00001000 */
11585#define PWR_PUCRF_PF12 PWR_PUCRF_PF12_Msk /*!< Port PF12 Pull-Up set */
11586#define PWR_PUCRF_PF11_Pos (11U)
11587#define PWR_PUCRF_PF11_Msk (0x1U << PWR_PUCRF_PF11_Pos) /*!< 0x00000800 */
11588#define PWR_PUCRF_PF11 PWR_PUCRF_PF11_Msk /*!< Port PF11 Pull-Up set */
11589#define PWR_PUCRF_PF10_Pos (10U)
11590#define PWR_PUCRF_PF10_Msk (0x1U << PWR_PUCRF_PF10_Pos) /*!< 0x00000400 */
11591#define PWR_PUCRF_PF10 PWR_PUCRF_PF10_Msk /*!< Port PF10 Pull-Up set */
11592#define PWR_PUCRF_PF9_Pos (9U)
11593#define PWR_PUCRF_PF9_Msk (0x1U << PWR_PUCRF_PF9_Pos) /*!< 0x00000200 */
11594#define PWR_PUCRF_PF9 PWR_PUCRF_PF9_Msk /*!< Port PF9 Pull-Up set */
11595#define PWR_PUCRF_PF8_Pos (8U)
11596#define PWR_PUCRF_PF8_Msk (0x1U << PWR_PUCRF_PF8_Pos) /*!< 0x00000100 */
11597#define PWR_PUCRF_PF8 PWR_PUCRF_PF8_Msk /*!< Port PF8 Pull-Up set */
11598#define PWR_PUCRF_PF7_Pos (7U)
11599#define PWR_PUCRF_PF7_Msk (0x1U << PWR_PUCRF_PF7_Pos) /*!< 0x00000080 */
11600#define PWR_PUCRF_PF7 PWR_PUCRF_PF7_Msk /*!< Port PF7 Pull-Up set */
11601#define PWR_PUCRF_PF6_Pos (6U)
11602#define PWR_PUCRF_PF6_Msk (0x1U << PWR_PUCRF_PF6_Pos) /*!< 0x00000040 */
11603#define PWR_PUCRF_PF6 PWR_PUCRF_PF6_Msk /*!< Port PF6 Pull-Up set */
11604#define PWR_PUCRF_PF5_Pos (5U)
11605#define PWR_PUCRF_PF5_Msk (0x1U << PWR_PUCRF_PF5_Pos) /*!< 0x00000020 */
11606#define PWR_PUCRF_PF5 PWR_PUCRF_PF5_Msk /*!< Port PF5 Pull-Up set */
11607#define PWR_PUCRF_PF4_Pos (4U)
11608#define PWR_PUCRF_PF4_Msk (0x1U << PWR_PUCRF_PF4_Pos) /*!< 0x00000010 */
11609#define PWR_PUCRF_PF4 PWR_PUCRF_PF4_Msk /*!< Port PF4 Pull-Up set */
11610#define PWR_PUCRF_PF3_Pos (3U)
11611#define PWR_PUCRF_PF3_Msk (0x1U << PWR_PUCRF_PF3_Pos) /*!< 0x00000008 */
11612#define PWR_PUCRF_PF3 PWR_PUCRF_PF3_Msk /*!< Port PF3 Pull-Up set */
11613#define PWR_PUCRF_PF2_Pos (2U)
11614#define PWR_PUCRF_PF2_Msk (0x1U << PWR_PUCRF_PF2_Pos) /*!< 0x00000004 */
11615#define PWR_PUCRF_PF2 PWR_PUCRF_PF2_Msk /*!< Port PF2 Pull-Up set */
11616#define PWR_PUCRF_PF1_Pos (1U)
11617#define PWR_PUCRF_PF1_Msk (0x1U << PWR_PUCRF_PF1_Pos) /*!< 0x00000002 */
11618#define PWR_PUCRF_PF1 PWR_PUCRF_PF1_Msk /*!< Port PF1 Pull-Up set */
11619#define PWR_PUCRF_PF0_Pos (0U)
11620#define PWR_PUCRF_PF0_Msk (0x1U << PWR_PUCRF_PF0_Pos) /*!< 0x00000001 */
11621#define PWR_PUCRF_PF0 PWR_PUCRF_PF0_Msk /*!< Port PF0 Pull-Up set */
11622
11623/******************** Bit definition for PWR_PDCRF register ********************/
11624#define PWR_PDCRF_PF15_Pos (15U)
11625#define PWR_PDCRF_PF15_Msk (0x1U << PWR_PDCRF_PF15_Pos) /*!< 0x00008000 */
11626#define PWR_PDCRF_PF15 PWR_PDCRF_PF15_Msk /*!< Port PF15 Pull-Down set */
11627#define PWR_PDCRF_PF14_Pos (14U)
11628#define PWR_PDCRF_PF14_Msk (0x1U << PWR_PDCRF_PF14_Pos) /*!< 0x00004000 */
11629#define PWR_PDCRF_PF14 PWR_PDCRF_PF14_Msk /*!< Port PF14 Pull-Down set */
11630#define PWR_PDCRF_PF13_Pos (13U)
11631#define PWR_PDCRF_PF13_Msk (0x1U << PWR_PDCRF_PF13_Pos) /*!< 0x00002000 */
11632#define PWR_PDCRF_PF13 PWR_PDCRF_PF13_Msk /*!< Port PF13 Pull-Down set */
11633#define PWR_PDCRF_PF12_Pos (12U)
11634#define PWR_PDCRF_PF12_Msk (0x1U << PWR_PDCRF_PF12_Pos) /*!< 0x00001000 */
11635#define PWR_PDCRF_PF12 PWR_PDCRF_PF12_Msk /*!< Port PF12 Pull-Down set */
11636#define PWR_PDCRF_PF11_Pos (11U)
11637#define PWR_PDCRF_PF11_Msk (0x1U << PWR_PDCRF_PF11_Pos) /*!< 0x00000800 */
11638#define PWR_PDCRF_PF11 PWR_PDCRF_PF11_Msk /*!< Port PF11 Pull-Down set */
11639#define PWR_PDCRF_PF10_Pos (10U)
11640#define PWR_PDCRF_PF10_Msk (0x1U << PWR_PDCRF_PF10_Pos) /*!< 0x00000400 */
11641#define PWR_PDCRF_PF10 PWR_PDCRF_PF10_Msk /*!< Port PF10 Pull-Down set */
11642#define PWR_PDCRF_PF9_Pos (9U)
11643#define PWR_PDCRF_PF9_Msk (0x1U << PWR_PDCRF_PF9_Pos) /*!< 0x00000200 */
11644#define PWR_PDCRF_PF9 PWR_PDCRF_PF9_Msk /*!< Port PF9 Pull-Down set */
11645#define PWR_PDCRF_PF8_Pos (8U)
11646#define PWR_PDCRF_PF8_Msk (0x1U << PWR_PDCRF_PF8_Pos) /*!< 0x00000100 */
11647#define PWR_PDCRF_PF8 PWR_PDCRF_PF8_Msk /*!< Port PF8 Pull-Down set */
11648#define PWR_PDCRF_PF7_Pos (7U)
11649#define PWR_PDCRF_PF7_Msk (0x1U << PWR_PDCRF_PF7_Pos) /*!< 0x00000080 */
11650#define PWR_PDCRF_PF7 PWR_PDCRF_PF7_Msk /*!< Port PF7 Pull-Down set */
11651#define PWR_PDCRF_PF6_Pos (6U)
11652#define PWR_PDCRF_PF6_Msk (0x1U << PWR_PDCRF_PF6_Pos) /*!< 0x00000040 */
11653#define PWR_PDCRF_PF6 PWR_PDCRF_PF6_Msk /*!< Port PF6 Pull-Down set */
11654#define PWR_PDCRF_PF5_Pos (5U)
11655#define PWR_PDCRF_PF5_Msk (0x1U << PWR_PDCRF_PF5_Pos) /*!< 0x00000020 */
11656#define PWR_PDCRF_PF5 PWR_PDCRF_PF5_Msk /*!< Port PF5 Pull-Down set */
11657#define PWR_PDCRF_PF4_Pos (4U)
11658#define PWR_PDCRF_PF4_Msk (0x1U << PWR_PDCRF_PF4_Pos) /*!< 0x00000010 */
11659#define PWR_PDCRF_PF4 PWR_PDCRF_PF4_Msk /*!< Port PF4 Pull-Down set */
11660#define PWR_PDCRF_PF3_Pos (3U)
11661#define PWR_PDCRF_PF3_Msk (0x1U << PWR_PDCRF_PF3_Pos) /*!< 0x00000008 */
11662#define PWR_PDCRF_PF3 PWR_PDCRF_PF3_Msk /*!< Port PF3 Pull-Down set */
11663#define PWR_PDCRF_PF2_Pos (2U)
11664#define PWR_PDCRF_PF2_Msk (0x1U << PWR_PDCRF_PF2_Pos) /*!< 0x00000004 */
11665#define PWR_PDCRF_PF2 PWR_PDCRF_PF2_Msk /*!< Port PF2 Pull-Down set */
11666#define PWR_PDCRF_PF1_Pos (1U)
11667#define PWR_PDCRF_PF1_Msk (0x1U << PWR_PDCRF_PF1_Pos) /*!< 0x00000002 */
11668#define PWR_PDCRF_PF1 PWR_PDCRF_PF1_Msk /*!< Port PF1 Pull-Down set */
11669#define PWR_PDCRF_PF0_Pos (0U)
11670#define PWR_PDCRF_PF0_Msk (0x1U << PWR_PDCRF_PF0_Pos) /*!< 0x00000001 */
11671#define PWR_PDCRF_PF0 PWR_PDCRF_PF0_Msk /*!< Port PF0 Pull-Down set */
11672
11673/******************** Bit definition for PWR_PUCRG register ********************/
11674#define PWR_PUCRG_PG15_Pos (15U)
11675#define PWR_PUCRG_PG15_Msk (0x1U << PWR_PUCRG_PG15_Pos) /*!< 0x00008000 */
11676#define PWR_PUCRG_PG15 PWR_PUCRG_PG15_Msk /*!< Port PG15 Pull-Up set */
11677#define PWR_PUCRG_PG14_Pos (14U)
11678#define PWR_PUCRG_PG14_Msk (0x1U << PWR_PUCRG_PG14_Pos) /*!< 0x00004000 */
11679#define PWR_PUCRG_PG14 PWR_PUCRG_PG14_Msk /*!< Port PG14 Pull-Up set */
11680#define PWR_PUCRG_PG13_Pos (13U)
11681#define PWR_PUCRG_PG13_Msk (0x1U << PWR_PUCRG_PG13_Pos) /*!< 0x00002000 */
11682#define PWR_PUCRG_PG13 PWR_PUCRG_PG13_Msk /*!< Port PG13 Pull-Up set */
11683#define PWR_PUCRG_PG12_Pos (12U)
11684#define PWR_PUCRG_PG12_Msk (0x1U << PWR_PUCRG_PG12_Pos) /*!< 0x00001000 */
11685#define PWR_PUCRG_PG12 PWR_PUCRG_PG12_Msk /*!< Port PG12 Pull-Up set */
11686#define PWR_PUCRG_PG11_Pos (11U)
11687#define PWR_PUCRG_PG11_Msk (0x1U << PWR_PUCRG_PG11_Pos) /*!< 0x00000800 */
11688#define PWR_PUCRG_PG11 PWR_PUCRG_PG11_Msk /*!< Port PG11 Pull-Up set */
11689#define PWR_PUCRG_PG10_Pos (10U)
11690#define PWR_PUCRG_PG10_Msk (0x1U << PWR_PUCRG_PG10_Pos) /*!< 0x00000400 */
11691#define PWR_PUCRG_PG10 PWR_PUCRG_PG10_Msk /*!< Port PG10 Pull-Up set */
11692#define PWR_PUCRG_PG9_Pos (9U)
11693#define PWR_PUCRG_PG9_Msk (0x1U << PWR_PUCRG_PG9_Pos) /*!< 0x00000200 */
11694#define PWR_PUCRG_PG9 PWR_PUCRG_PG9_Msk /*!< Port PG9 Pull-Up set */
11695#define PWR_PUCRG_PG8_Pos (8U)
11696#define PWR_PUCRG_PG8_Msk (0x1U << PWR_PUCRG_PG8_Pos) /*!< 0x00000100 */
11697#define PWR_PUCRG_PG8 PWR_PUCRG_PG8_Msk /*!< Port PG8 Pull-Up set */
11698#define PWR_PUCRG_PG7_Pos (7U)
11699#define PWR_PUCRG_PG7_Msk (0x1U << PWR_PUCRG_PG7_Pos) /*!< 0x00000080 */
11700#define PWR_PUCRG_PG7 PWR_PUCRG_PG7_Msk /*!< Port PG7 Pull-Up set */
11701#define PWR_PUCRG_PG6_Pos (6U)
11702#define PWR_PUCRG_PG6_Msk (0x1U << PWR_PUCRG_PG6_Pos) /*!< 0x00000040 */
11703#define PWR_PUCRG_PG6 PWR_PUCRG_PG6_Msk /*!< Port PG6 Pull-Up set */
11704#define PWR_PUCRG_PG5_Pos (5U)
11705#define PWR_PUCRG_PG5_Msk (0x1U << PWR_PUCRG_PG5_Pos) /*!< 0x00000020 */
11706#define PWR_PUCRG_PG5 PWR_PUCRG_PG5_Msk /*!< Port PG5 Pull-Up set */
11707#define PWR_PUCRG_PG4_Pos (4U)
11708#define PWR_PUCRG_PG4_Msk (0x1U << PWR_PUCRG_PG4_Pos) /*!< 0x00000010 */
11709#define PWR_PUCRG_PG4 PWR_PUCRG_PG4_Msk /*!< Port PG4 Pull-Up set */
11710#define PWR_PUCRG_PG3_Pos (3U)
11711#define PWR_PUCRG_PG3_Msk (0x1U << PWR_PUCRG_PG3_Pos) /*!< 0x00000008 */
11712#define PWR_PUCRG_PG3 PWR_PUCRG_PG3_Msk /*!< Port PG3 Pull-Up set */
11713#define PWR_PUCRG_PG2_Pos (2U)
11714#define PWR_PUCRG_PG2_Msk (0x1U << PWR_PUCRG_PG2_Pos) /*!< 0x00000004 */
11715#define PWR_PUCRG_PG2 PWR_PUCRG_PG2_Msk /*!< Port PG2 Pull-Up set */
11716#define PWR_PUCRG_PG1_Pos (1U)
11717#define PWR_PUCRG_PG1_Msk (0x1U << PWR_PUCRG_PG1_Pos) /*!< 0x00000002 */
11718#define PWR_PUCRG_PG1 PWR_PUCRG_PG1_Msk /*!< Port PG1 Pull-Up set */
11719#define PWR_PUCRG_PG0_Pos (0U)
11720#define PWR_PUCRG_PG0_Msk (0x1U << PWR_PUCRG_PG0_Pos) /*!< 0x00000001 */
11721#define PWR_PUCRG_PG0 PWR_PUCRG_PG0_Msk /*!< Port PG0 Pull-Up set */
11722
11723/******************** Bit definition for PWR_PDCRG register ********************/
11724#define PWR_PDCRG_PG15_Pos (15U)
11725#define PWR_PDCRG_PG15_Msk (0x1U << PWR_PDCRG_PG15_Pos) /*!< 0x00008000 */
11726#define PWR_PDCRG_PG15 PWR_PDCRG_PG15_Msk /*!< Port PG15 Pull-Down set */
11727#define PWR_PDCRG_PG14_Pos (14U)
11728#define PWR_PDCRG_PG14_Msk (0x1U << PWR_PDCRG_PG14_Pos) /*!< 0x00004000 */
11729#define PWR_PDCRG_PG14 PWR_PDCRG_PG14_Msk /*!< Port PG14 Pull-Down set */
11730#define PWR_PDCRG_PG13_Pos (13U)
11731#define PWR_PDCRG_PG13_Msk (0x1U << PWR_PDCRG_PG13_Pos) /*!< 0x00002000 */
11732#define PWR_PDCRG_PG13 PWR_PDCRG_PG13_Msk /*!< Port PG13 Pull-Down set */
11733#define PWR_PDCRG_PG12_Pos (12U)
11734#define PWR_PDCRG_PG12_Msk (0x1U << PWR_PDCRG_PG12_Pos) /*!< 0x00001000 */
11735#define PWR_PDCRG_PG12 PWR_PDCRG_PG12_Msk /*!< Port PG12 Pull-Down set */
11736#define PWR_PDCRG_PG11_Pos (11U)
11737#define PWR_PDCRG_PG11_Msk (0x1U << PWR_PDCRG_PG11_Pos) /*!< 0x00000800 */
11738#define PWR_PDCRG_PG11 PWR_PDCRG_PG11_Msk /*!< Port PG11 Pull-Down set */
11739#define PWR_PDCRG_PG10_Pos (10U)
11740#define PWR_PDCRG_PG10_Msk (0x1U << PWR_PDCRG_PG10_Pos) /*!< 0x00000400 */
11741#define PWR_PDCRG_PG10 PWR_PDCRG_PG10_Msk /*!< Port PG10 Pull-Down set */
11742#define PWR_PDCRG_PG9_Pos (9U)
11743#define PWR_PDCRG_PG9_Msk (0x1U << PWR_PDCRG_PG9_Pos) /*!< 0x00000200 */
11744#define PWR_PDCRG_PG9 PWR_PDCRG_PG9_Msk /*!< Port PG9 Pull-Down set */
11745#define PWR_PDCRG_PG8_Pos (8U)
11746#define PWR_PDCRG_PG8_Msk (0x1U << PWR_PDCRG_PG8_Pos) /*!< 0x00000100 */
11747#define PWR_PDCRG_PG8 PWR_PDCRG_PG8_Msk /*!< Port PG8 Pull-Down set */
11748#define PWR_PDCRG_PG7_Pos (7U)
11749#define PWR_PDCRG_PG7_Msk (0x1U << PWR_PDCRG_PG7_Pos) /*!< 0x00000080 */
11750#define PWR_PDCRG_PG7 PWR_PDCRG_PG7_Msk /*!< Port PG7 Pull-Down set */
11751#define PWR_PDCRG_PG6_Pos (6U)
11752#define PWR_PDCRG_PG6_Msk (0x1U << PWR_PDCRG_PG6_Pos) /*!< 0x00000040 */
11753#define PWR_PDCRG_PG6 PWR_PDCRG_PG6_Msk /*!< Port PG6 Pull-Down set */
11754#define PWR_PDCRG_PG5_Pos (5U)
11755#define PWR_PDCRG_PG5_Msk (0x1U << PWR_PDCRG_PG5_Pos) /*!< 0x00000020 */
11756#define PWR_PDCRG_PG5 PWR_PDCRG_PG5_Msk /*!< Port PG5 Pull-Down set */
11757#define PWR_PDCRG_PG4_Pos (4U)
11758#define PWR_PDCRG_PG4_Msk (0x1U << PWR_PDCRG_PG4_Pos) /*!< 0x00000010 */
11759#define PWR_PDCRG_PG4 PWR_PDCRG_PG4_Msk /*!< Port PG4 Pull-Down set */
11760#define PWR_PDCRG_PG3_Pos (3U)
11761#define PWR_PDCRG_PG3_Msk (0x1U << PWR_PDCRG_PG3_Pos) /*!< 0x00000008 */
11762#define PWR_PDCRG_PG3 PWR_PDCRG_PG3_Msk /*!< Port PG3 Pull-Down set */
11763#define PWR_PDCRG_PG2_Pos (2U)
11764#define PWR_PDCRG_PG2_Msk (0x1U << PWR_PDCRG_PG2_Pos) /*!< 0x00000004 */
11765#define PWR_PDCRG_PG2 PWR_PDCRG_PG2_Msk /*!< Port PG2 Pull-Down set */
11766#define PWR_PDCRG_PG1_Pos (1U)
11767#define PWR_PDCRG_PG1_Msk (0x1U << PWR_PDCRG_PG1_Pos) /*!< 0x00000002 */
11768#define PWR_PDCRG_PG1 PWR_PDCRG_PG1_Msk /*!< Port PG1 Pull-Down set */
11769#define PWR_PDCRG_PG0_Pos (0U)
11770#define PWR_PDCRG_PG0_Msk (0x1U << PWR_PDCRG_PG0_Pos) /*!< 0x00000001 */
11771#define PWR_PDCRG_PG0 PWR_PDCRG_PG0_Msk /*!< Port PG0 Pull-Down set */
11772
11773/******************** Bit definition for PWR_PUCRH register ********************/
11774#define PWR_PUCRH_PH15_Pos (15U)
11775#define PWR_PUCRH_PH15_Msk (0x1U << PWR_PUCRH_PH15_Pos) /*!< 0x00008000 */
11776#define PWR_PUCRH_PH15 PWR_PUCRH_PH15_Msk /*!< Port PH15 Pull-Up set */
11777#define PWR_PUCRH_PH14_Pos (14U)
11778#define PWR_PUCRH_PH14_Msk (0x1U << PWR_PUCRH_PH14_Pos) /*!< 0x00004000 */
11779#define PWR_PUCRH_PH14 PWR_PUCRH_PH14_Msk /*!< Port PH14 Pull-Up set */
11780#define PWR_PUCRH_PH13_Pos (13U)
11781#define PWR_PUCRH_PH13_Msk (0x1U << PWR_PUCRH_PH13_Pos) /*!< 0x00002000 */
11782#define PWR_PUCRH_PH13 PWR_PUCRH_PH13_Msk /*!< Port PH13 Pull-Up set */
11783#define PWR_PUCRH_PH12_Pos (12U)
11784#define PWR_PUCRH_PH12_Msk (0x1U << PWR_PUCRH_PH12_Pos) /*!< 0x00001000 */
11785#define PWR_PUCRH_PH12 PWR_PUCRH_PH12_Msk /*!< Port PH12 Pull-Up set */
11786#define PWR_PUCRH_PH11_Pos (11U)
11787#define PWR_PUCRH_PH11_Msk (0x1U << PWR_PUCRH_PH11_Pos) /*!< 0x00000800 */
11788#define PWR_PUCRH_PH11 PWR_PUCRH_PH11_Msk /*!< Port PH11 Pull-Up set */
11789#define PWR_PUCRH_PH10_Pos (10U)
11790#define PWR_PUCRH_PH10_Msk (0x1U << PWR_PUCRH_PH10_Pos) /*!< 0x00000400 */
11791#define PWR_PUCRH_PH10 PWR_PUCRH_PH10_Msk /*!< Port PH10 Pull-Up set */
11792#define PWR_PUCRH_PH9_Pos (9U)
11793#define PWR_PUCRH_PH9_Msk (0x1U << PWR_PUCRH_PH9_Pos) /*!< 0x00000200 */
11794#define PWR_PUCRH_PH9 PWR_PUCRH_PH9_Msk /*!< Port PH9 Pull-Up set */
11795#define PWR_PUCRH_PH8_Pos (8U)
11796#define PWR_PUCRH_PH8_Msk (0x1U << PWR_PUCRH_PH8_Pos) /*!< 0x00000100 */
11797#define PWR_PUCRH_PH8 PWR_PUCRH_PH8_Msk /*!< Port PH8 Pull-Up set */
11798#define PWR_PUCRH_PH7_Pos (7U)
11799#define PWR_PUCRH_PH7_Msk (0x1U << PWR_PUCRH_PH7_Pos) /*!< 0x00000080 */
11800#define PWR_PUCRH_PH7 PWR_PUCRH_PH7_Msk /*!< Port PH7 Pull-Up set */
11801#define PWR_PUCRH_PH6_Pos (6U)
11802#define PWR_PUCRH_PH6_Msk (0x1U << PWR_PUCRH_PH6_Pos) /*!< 0x00000040 */
11803#define PWR_PUCRH_PH6 PWR_PUCRH_PH6_Msk /*!< Port PH6 Pull-Up set */
11804#define PWR_PUCRH_PH5_Pos (5U)
11805#define PWR_PUCRH_PH5_Msk (0x1U << PWR_PUCRH_PH5_Pos) /*!< 0x00000020 */
11806#define PWR_PUCRH_PH5 PWR_PUCRH_PH5_Msk /*!< Port PH5 Pull-Up set */
11807#define PWR_PUCRH_PH4_Pos (4U)
11808#define PWR_PUCRH_PH4_Msk (0x1U << PWR_PUCRH_PH4_Pos) /*!< 0x00000010 */
11809#define PWR_PUCRH_PH4 PWR_PUCRH_PH4_Msk /*!< Port PH4 Pull-Up set */
11810#define PWR_PUCRH_PH3_Pos (3U)
11811#define PWR_PUCRH_PH3_Msk (0x1U << PWR_PUCRH_PH3_Pos) /*!< 0x00000008 */
11812#define PWR_PUCRH_PH3 PWR_PUCRH_PH3_Msk /*!< Port PH3 Pull-Up set */
11813#define PWR_PUCRH_PH2_Pos (2U)
11814#define PWR_PUCRH_PH2_Msk (0x1U << PWR_PUCRH_PH2_Pos) /*!< 0x00000004 */
11815#define PWR_PUCRH_PH2 PWR_PUCRH_PH2_Msk /*!< Port PH2 Pull-Up set */
11816#define PWR_PUCRH_PH1_Pos (1U)
11817#define PWR_PUCRH_PH1_Msk (0x1U << PWR_PUCRH_PH1_Pos) /*!< 0x00000002 */
11818#define PWR_PUCRH_PH1 PWR_PUCRH_PH1_Msk /*!< Port PH1 Pull-Up set */
11819#define PWR_PUCRH_PH0_Pos (0U)
11820#define PWR_PUCRH_PH0_Msk (0x1U << PWR_PUCRH_PH0_Pos) /*!< 0x00000001 */
11821#define PWR_PUCRH_PH0 PWR_PUCRH_PH0_Msk /*!< Port PH0 Pull-Up set */
11822
11823/******************** Bit definition for PWR_PDCRH register ********************/
11824#define PWR_PDCRH_PH15_Pos (15U)
11825#define PWR_PDCRH_PH15_Msk (0x1U << PWR_PDCRH_PH15_Pos) /*!< 0x00008000 */
11826#define PWR_PDCRH_PH15 PWR_PDCRH_PH15_Msk /*!< Port PH15 Pull-Down set */
11827#define PWR_PDCRH_PH14_Pos (14U)
11828#define PWR_PDCRH_PH14_Msk (0x1U << PWR_PDCRH_PH14_Pos) /*!< 0x00004000 */
11829#define PWR_PDCRH_PH14 PWR_PDCRH_PH14_Msk /*!< Port PH14 Pull-Down set */
11830#define PWR_PDCRH_PH13_Pos (13U)
11831#define PWR_PDCRH_PH13_Msk (0x1U << PWR_PDCRH_PH13_Pos) /*!< 0x00002000 */
11832#define PWR_PDCRH_PH13 PWR_PDCRH_PH13_Msk /*!< Port PH13 Pull-Down set */
11833#define PWR_PDCRH_PH12_Pos (12U)
11834#define PWR_PDCRH_PH12_Msk (0x1U << PWR_PDCRH_PH12_Pos) /*!< 0x00001000 */
11835#define PWR_PDCRH_PH12 PWR_PDCRH_PH12_Msk /*!< Port PH12 Pull-Down set */
11836#define PWR_PDCRH_PH11_Pos (11U)
11837#define PWR_PDCRH_PH11_Msk (0x1U << PWR_PDCRH_PH11_Pos) /*!< 0x00000800 */
11838#define PWR_PDCRH_PH11 PWR_PDCRH_PH11_Msk /*!< Port PH11 Pull-Down set */
11839#define PWR_PDCRH_PH10_Pos (10U)
11840#define PWR_PDCRH_PH10_Msk (0x1U << PWR_PDCRH_PH10_Pos) /*!< 0x00000400 */
11841#define PWR_PDCRH_PH10 PWR_PDCRH_PH10_Msk /*!< Port PH10 Pull-Down set */
11842#define PWR_PDCRH_PH9_Pos (9U)
11843#define PWR_PDCRH_PH9_Msk (0x1U << PWR_PDCRH_PH9_Pos) /*!< 0x00000200 */
11844#define PWR_PDCRH_PH9 PWR_PDCRH_PH9_Msk /*!< Port PH9 Pull-Down set */
11845#define PWR_PDCRH_PH8_Pos (8U)
11846#define PWR_PDCRH_PH8_Msk (0x1U << PWR_PDCRH_PH8_Pos) /*!< 0x00000100 */
11847#define PWR_PDCRH_PH8 PWR_PDCRH_PH8_Msk /*!< Port PH8 Pull-Down set */
11848#define PWR_PDCRH_PH7_Pos (7U)
11849#define PWR_PDCRH_PH7_Msk (0x1U << PWR_PDCRH_PH7_Pos) /*!< 0x00000080 */
11850#define PWR_PDCRH_PH7 PWR_PDCRH_PH7_Msk /*!< Port PH7 Pull-Down set */
11851#define PWR_PDCRH_PH6_Pos (6U)
11852#define PWR_PDCRH_PH6_Msk (0x1U << PWR_PDCRH_PH6_Pos) /*!< 0x00000040 */
11853#define PWR_PDCRH_PH6 PWR_PDCRH_PH6_Msk /*!< Port PH6 Pull-Down set */
11854#define PWR_PDCRH_PH5_Pos (5U)
11855#define PWR_PDCRH_PH5_Msk (0x1U << PWR_PDCRH_PH5_Pos) /*!< 0x00000020 */
11856#define PWR_PDCRH_PH5 PWR_PDCRH_PH5_Msk /*!< Port PH5 Pull-Down set */
11857#define PWR_PDCRH_PH4_Pos (4U)
11858#define PWR_PDCRH_PH4_Msk (0x1U << PWR_PDCRH_PH4_Pos) /*!< 0x00000010 */
11859#define PWR_PDCRH_PH4 PWR_PDCRH_PH4_Msk /*!< Port PH4 Pull-Down set */
11860#define PWR_PDCRH_PH3_Pos (3U)
11861#define PWR_PDCRH_PH3_Msk (0x1U << PWR_PDCRH_PH3_Pos) /*!< 0x00000008 */
11862#define PWR_PDCRH_PH3 PWR_PDCRH_PH3_Msk /*!< Port PH3 Pull-Down set */
11863#define PWR_PDCRH_PH2_Pos (2U)
11864#define PWR_PDCRH_PH2_Msk (0x1U << PWR_PDCRH_PH2_Pos) /*!< 0x00000004 */
11865#define PWR_PDCRH_PH2 PWR_PDCRH_PH2_Msk /*!< Port PH1 Pull-Down set */
11866#define PWR_PDCRH_PH1_Pos (1U)
11867#define PWR_PDCRH_PH1_Msk (0x1U << PWR_PDCRH_PH1_Pos) /*!< 0x00000002 */
11868#define PWR_PDCRH_PH1 PWR_PDCRH_PH1_Msk /*!< Port PH1 Pull-Down set */
11869#define PWR_PDCRH_PH0_Pos (0U)
11870#define PWR_PDCRH_PH0_Msk (0x1U << PWR_PDCRH_PH0_Pos) /*!< 0x00000001 */
11871#define PWR_PDCRH_PH0 PWR_PDCRH_PH0_Msk /*!< Port PH0 Pull-Down set */
11872
11873/******************** Bit definition for PWR_PUCRI register ********************/
11874#define PWR_PUCRI_PI11_Pos (11U)
11875#define PWR_PUCRI_PI11_Msk (0x1U << PWR_PUCRI_PI11_Pos) /*!< 0x00000800 */
11876#define PWR_PUCRI_PI11 PWR_PUCRI_PI11_Msk /*!< Port PI11 Pull-Up set */
11877#define PWR_PUCRI_PI10_Pos (10U)
11878#define PWR_PUCRI_PI10_Msk (0x1U << PWR_PUCRI_PI10_Pos) /*!< 0x00000400 */
11879#define PWR_PUCRI_PI10 PWR_PUCRI_PI10_Msk /*!< Port PI10 Pull-Up set */
11880#define PWR_PUCRI_PI9_Pos (9U)
11881#define PWR_PUCRI_PI9_Msk (0x1U << PWR_PUCRI_PI9_Pos) /*!< 0x00000200 */
11882#define PWR_PUCRI_PI9 PWR_PUCRI_PI9_Msk /*!< Port PI9 Pull-Up set */
11883#define PWR_PUCRI_PI8_Pos (8U)
11884#define PWR_PUCRI_PI8_Msk (0x1U << PWR_PUCRI_PI8_Pos) /*!< 0x00000100 */
11885#define PWR_PUCRI_PI8 PWR_PUCRI_PI8_Msk /*!< Port PI8 Pull-Up set */
11886#define PWR_PUCRI_PI7_Pos (7U)
11887#define PWR_PUCRI_PI7_Msk (0x1U << PWR_PUCRI_PI7_Pos) /*!< 0x00000080 */
11888#define PWR_PUCRI_PI7 PWR_PUCRI_PI7_Msk /*!< Port PI7 Pull-Up set */
11889#define PWR_PUCRI_PI6_Pos (6U)
11890#define PWR_PUCRI_PI6_Msk (0x1U << PWR_PUCRI_PI6_Pos) /*!< 0x00000040 */
11891#define PWR_PUCRI_PI6 PWR_PUCRI_PI6_Msk /*!< Port PI6 Pull-Up set */
11892#define PWR_PUCRI_PI5_Pos (5U)
11893#define PWR_PUCRI_PI5_Msk (0x1U << PWR_PUCRI_PI5_Pos) /*!< 0x00000020 */
11894#define PWR_PUCRI_PI5 PWR_PUCRI_PI5_Msk /*!< Port PI5 Pull-Up set */
11895#define PWR_PUCRI_PI4_Pos (4U)
11896#define PWR_PUCRI_PI4_Msk (0x1U << PWR_PUCRI_PI4_Pos) /*!< 0x00000010 */
11897#define PWR_PUCRI_PI4 PWR_PUCRI_PI4_Msk /*!< Port PI4 Pull-Up set */
11898#define PWR_PUCRI_PI3_Pos (3U)
11899#define PWR_PUCRI_PI3_Msk (0x1U << PWR_PUCRI_PI3_Pos) /*!< 0x00000008 */
11900#define PWR_PUCRI_PI3 PWR_PUCRI_PI3_Msk /*!< Port PI3 Pull-Up set */
11901#define PWR_PUCRI_PI2_Pos (2U)
11902#define PWR_PUCRI_PI2_Msk (0x1U << PWR_PUCRI_PI2_Pos) /*!< 0x00000004 */
11903#define PWR_PUCRI_PI2 PWR_PUCRI_PI2_Msk /*!< Port PI2 Pull-Up set */
11904#define PWR_PUCRI_PI1_Pos (1U)
11905#define PWR_PUCRI_PI1_Msk (0x1U << PWR_PUCRI_PI1_Pos) /*!< 0x00000002 */
11906#define PWR_PUCRI_PI1 PWR_PUCRI_PI1_Msk /*!< Port PI1 Pull-Up set */
11907#define PWR_PUCRI_PI0_Pos (0U)
11908#define PWR_PUCRI_PI0_Msk (0x1U << PWR_PUCRI_PI0_Pos) /*!< 0x00000001 */
11909#define PWR_PUCRI_PI0 PWR_PUCRI_PI0_Msk /*!< Port PI0 Pull-Up set */
11910
11911/******************** Bit definition for PWR_PDCRI register ********************/
11912#define PWR_PDCRI_PI11_Pos (11U)
11913#define PWR_PDCRI_PI11_Msk (0x1U << PWR_PDCRI_PI11_Pos) /*!< 0x00000800 */
11914#define PWR_PDCRI_PI11 PWR_PDCRI_PI11_Msk /*!< Port PI11 Pull-Down set */
11915#define PWR_PDCRI_PI10_Pos (10U)
11916#define PWR_PDCRI_PI10_Msk (0x1U << PWR_PDCRI_PI10_Pos) /*!< 0x00000400 */
11917#define PWR_PDCRI_PI10 PWR_PDCRI_PI10_Msk /*!< Port PI10 Pull-Down set */
11918#define PWR_PDCRI_PI9_Pos (9U)
11919#define PWR_PDCRI_PI9_Msk (0x1U << PWR_PDCRI_PI9_Pos) /*!< 0x00000200 */
11920#define PWR_PDCRI_PI9 PWR_PDCRI_PI9_Msk /*!< Port PI9 Pull-Down set */
11921#define PWR_PDCRI_PI8_Pos (8U)
11922#define PWR_PDCRI_PI8_Msk (0x1U << PWR_PDCRI_PI8_Pos) /*!< 0x00000100 */
11923#define PWR_PDCRI_PI8 PWR_PDCRI_PI8_Msk /*!< Port PI8 Pull-Down set */
11924#define PWR_PDCRI_PI7_Pos (7U)
11925#define PWR_PDCRI_PI7_Msk (0x1U << PWR_PDCRI_PI7_Pos) /*!< 0x00000080 */
11926#define PWR_PDCRI_PI7 PWR_PDCRI_PI7_Msk /*!< Port PI7 Pull-Down set */
11927#define PWR_PDCRI_PI6_Pos (6U)
11928#define PWR_PDCRI_PI6_Msk (0x1U << PWR_PDCRI_PI6_Pos) /*!< 0x00000040 */
11929#define PWR_PDCRI_PI6 PWR_PDCRI_PI6_Msk /*!< Port PI6 Pull-Down set */
11930#define PWR_PDCRI_PI5_Pos (5U)
11931#define PWR_PDCRI_PI5_Msk (0x1U << PWR_PDCRI_PI5_Pos) /*!< 0x00000020 */
11932#define PWR_PDCRI_PI5 PWR_PDCRI_PI5_Msk /*!< Port PI5 Pull-Down set */
11933#define PWR_PDCRI_PI4_Pos (4U)
11934#define PWR_PDCRI_PI4_Msk (0x1U << PWR_PDCRI_PI4_Pos) /*!< 0x00000010 */
11935#define PWR_PDCRI_PI4 PWR_PDCRI_PI4_Msk /*!< Port PI4 Pull-Down set */
11936#define PWR_PDCRI_PI3_Pos (3U)
11937#define PWR_PDCRI_PI3_Msk (0x1U << PWR_PDCRI_PI3_Pos) /*!< 0x00000008 */
11938#define PWR_PDCRI_PI3 PWR_PDCRI_PI3_Msk /*!< Port PI3 Pull-Down set */
11939#define PWR_PDCRI_PI2_Pos (2U)
11940#define PWR_PDCRI_PI2_Msk (0x1U << PWR_PDCRI_PI2_Pos) /*!< 0x00000004 */
11941#define PWR_PDCRI_PI2 PWR_PDCRI_PI2_Msk /*!< Port PI2 Pull-Down set */
11942#define PWR_PDCRI_PI1_Pos (1U)
11943#define PWR_PDCRI_PI1_Msk (0x1U << PWR_PDCRI_PI1_Pos) /*!< 0x00000002 */
11944#define PWR_PDCRI_PI1 PWR_PDCRI_PI1_Msk /*!< Port PI1 Pull-Down set */
11945#define PWR_PDCRI_PI0_Pos (0U)
11946#define PWR_PDCRI_PI0_Msk (0x1U << PWR_PDCRI_PI0_Pos) /*!< 0x00000001 */
11947#define PWR_PDCRI_PI0 PWR_PDCRI_PI0_Msk /*!< Port PI0 Pull-Down set */
11948
11949/******************** Bit definition for PWR_CR5 register ********************/
11950#define PWR_CR5_R1MODE_Pos (8U)
11951#define PWR_CR5_R1MODE_Msk (0x1U << PWR_CR5_R1MODE_Pos) /*!< 0x00000100 */
11952#define PWR_CR5_R1MODE PWR_CR5_R1MODE_Msk /*!< Range 1 normal mode */
11953
11954
11955/******************************************************************************/
11956/* */
11957/* Reset and Clock Control */
11958/* */
11959/******************************************************************************/
11960/*
11961* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
11962*/
11963#define RCC_HSI48_SUPPORT
11964#define RCC_PLLM_DIV_1_16_SUPPORT
11965#define RCC_PLLP_DIV_2_31_SUPPORT
11966#define RCC_PLLSAI1M_DIV_1_16_SUPPORT
11967#define RCC_PLLSAI1P_DIV_2_31_SUPPORT
11968#define RCC_PLLSAI2_SUPPORT
11969#define RCC_PLLSAI2M_DIV_1_16_SUPPORT
11970#define RCC_PLLSAI2P_DIV_2_31_SUPPORT
11971#define RCC_PLLSAI2Q_DIV_SUPPORT
11972
11973/******************** Bit definition for RCC_CR register ********************/
11974#define RCC_CR_MSION_Pos (0U)
11975#define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000001 */
11976#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed oscillator (MSI) clock enable */
11977#define RCC_CR_MSIRDY_Pos (1U)
11978#define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000002 */
11979#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
11980#define RCC_CR_MSIPLLEN_Pos (2U)
11981#define RCC_CR_MSIPLLEN_Msk (0x1U << RCC_CR_MSIPLLEN_Pos) /*!< 0x00000004 */
11982#define RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk /*!< Internal Multi Speed oscillator (MSI) PLL enable */
11983#define RCC_CR_MSIRGSEL_Pos (3U)
11984#define RCC_CR_MSIRGSEL_Msk (0x1U << RCC_CR_MSIRGSEL_Pos) /*!< 0x00000008 */
11985#define RCC_CR_MSIRGSEL RCC_CR_MSIRGSEL_Msk /*!< Internal Multi Speed oscillator (MSI) range selection */
11986
11987/*!< MSIRANGE configuration : 12 frequency ranges available */
11988#define RCC_CR_MSIRANGE_Pos (4U)
11989#define RCC_CR_MSIRANGE_Msk (0xFU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000F0 */
11990#define RCC_CR_MSIRANGE RCC_CR_MSIRANGE_Msk /*!< Internal Multi Speed oscillator (MSI) clock Range */
11991#define RCC_CR_MSIRANGE_0 (0x0U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000000 */
11992#define RCC_CR_MSIRANGE_1 (0x1U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000010 */
11993#define RCC_CR_MSIRANGE_2 (0x2U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000020 */
11994#define RCC_CR_MSIRANGE_3 (0x3U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000030 */
11995#define RCC_CR_MSIRANGE_4 (0x4U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000040 */
11996#define RCC_CR_MSIRANGE_5 (0x5U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000050 */
11997#define RCC_CR_MSIRANGE_6 (0x6U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000060 */
11998#define RCC_CR_MSIRANGE_7 (0x7U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000070 */
11999#define RCC_CR_MSIRANGE_8 (0x8U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000080 */
12000#define RCC_CR_MSIRANGE_9 (0x9U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000090 */
12001#define RCC_CR_MSIRANGE_10 (0xAU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000A0 */
12002#define RCC_CR_MSIRANGE_11 (0xBU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000B0 */
12003
12004#define RCC_CR_HSION_Pos (8U)
12005#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000100 */
12006#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */
12007#define RCC_CR_HSIKERON_Pos (9U)
12008#define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
12009#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
12010#define RCC_CR_HSIRDY_Pos (10U)
12011#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
12012#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */
12013#define RCC_CR_HSIASFS_Pos (11U)
12014#define RCC_CR_HSIASFS_Msk (0x1U << RCC_CR_HSIASFS_Pos) /*!< 0x00000800 */
12015#define RCC_CR_HSIASFS RCC_CR_HSIASFS_Msk /*!< HSI16 Automatic Start from Stop */
12016
12017#define RCC_CR_HSEON_Pos (16U)
12018#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
12019#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */
12020#define RCC_CR_HSERDY_Pos (17U)
12021#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
12022#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
12023#define RCC_CR_HSEBYP_Pos (18U)
12024#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
12025#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
12026#define RCC_CR_CSSON_Pos (19U)
12027#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
12028#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
12029
12030#define RCC_CR_PLLON_Pos (24U)
12031#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
12032#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
12033#define RCC_CR_PLLRDY_Pos (25U)
12034#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
12035#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
12036#define RCC_CR_PLLSAI1ON_Pos (26U)
12037#define RCC_CR_PLLSAI1ON_Msk (0x1U << RCC_CR_PLLSAI1ON_Pos) /*!< 0x04000000 */
12038#define RCC_CR_PLLSAI1ON RCC_CR_PLLSAI1ON_Msk /*!< SAI1 PLL enable */
12039#define RCC_CR_PLLSAI1RDY_Pos (27U)
12040#define RCC_CR_PLLSAI1RDY_Msk (0x1U << RCC_CR_PLLSAI1RDY_Pos) /*!< 0x08000000 */
12041#define RCC_CR_PLLSAI1RDY RCC_CR_PLLSAI1RDY_Msk /*!< SAI1 PLL ready */
12042#define RCC_CR_PLLSAI2ON_Pos (28U)
12043#define RCC_CR_PLLSAI2ON_Msk (0x1U << RCC_CR_PLLSAI2ON_Pos) /*!< 0x10000000 */
12044#define RCC_CR_PLLSAI2ON RCC_CR_PLLSAI2ON_Msk /*!< SAI2 PLL enable */
12045#define RCC_CR_PLLSAI2RDY_Pos (29U)
12046#define RCC_CR_PLLSAI2RDY_Msk (0x1U << RCC_CR_PLLSAI2RDY_Pos) /*!< 0x20000000 */
12047#define RCC_CR_PLLSAI2RDY RCC_CR_PLLSAI2RDY_Msk /*!< SAI2 PLL ready */
12048
12049/******************** Bit definition for RCC_ICSCR register ***************/
12050/*!< MSICAL configuration */
12051#define RCC_ICSCR_MSICAL_Pos (0U)
12052#define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x000000FF */
12053#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< MSICAL[7:0] bits */
12054#define RCC_ICSCR_MSICAL_0 (0x01U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000001 */
12055#define RCC_ICSCR_MSICAL_1 (0x02U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000002 */
12056#define RCC_ICSCR_MSICAL_2 (0x04U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000004 */
12057#define RCC_ICSCR_MSICAL_3 (0x08U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000008 */
12058#define RCC_ICSCR_MSICAL_4 (0x10U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000010 */
12059#define RCC_ICSCR_MSICAL_5 (0x20U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000020 */
12060#define RCC_ICSCR_MSICAL_6 (0x40U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000040 */
12061#define RCC_ICSCR_MSICAL_7 (0x80U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000080 */
12062
12063/*!< MSITRIM configuration */
12064#define RCC_ICSCR_MSITRIM_Pos (8U)
12065#define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */
12066#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< MSITRIM[7:0] bits */
12067#define RCC_ICSCR_MSITRIM_0 (0x01U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000100 */
12068#define RCC_ICSCR_MSITRIM_1 (0x02U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000200 */
12069#define RCC_ICSCR_MSITRIM_2 (0x04U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000400 */
12070#define RCC_ICSCR_MSITRIM_3 (0x08U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000800 */
12071#define RCC_ICSCR_MSITRIM_4 (0x10U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00001000 */
12072#define RCC_ICSCR_MSITRIM_5 (0x20U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00002000 */
12073#define RCC_ICSCR_MSITRIM_6 (0x40U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00004000 */
12074#define RCC_ICSCR_MSITRIM_7 (0x80U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00008000 */
12075
12076/*!< HSICAL configuration */
12077#define RCC_ICSCR_HSICAL_Pos (16U)
12078#define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */
12079#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
12080#define RCC_ICSCR_HSICAL_0 (0x01U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */
12081#define RCC_ICSCR_HSICAL_1 (0x02U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */
12082#define RCC_ICSCR_HSICAL_2 (0x04U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */
12083#define RCC_ICSCR_HSICAL_3 (0x08U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */
12084#define RCC_ICSCR_HSICAL_4 (0x10U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */
12085#define RCC_ICSCR_HSICAL_5 (0x20U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */
12086#define RCC_ICSCR_HSICAL_6 (0x40U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */
12087#define RCC_ICSCR_HSICAL_7 (0x80U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */
12088
12089/*!< HSITRIM configuration */
12090#define RCC_ICSCR_HSITRIM_Pos (24U)
12091#define RCC_ICSCR_HSITRIM_Msk (0x7FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
12092#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
12093#define RCC_ICSCR_HSITRIM_0 (0x01U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
12094#define RCC_ICSCR_HSITRIM_1 (0x02U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
12095#define RCC_ICSCR_HSITRIM_2 (0x04U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
12096#define RCC_ICSCR_HSITRIM_3 (0x08U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
12097#define RCC_ICSCR_HSITRIM_4 (0x10U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
12098#define RCC_ICSCR_HSITRIM_5 (0x20U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
12099#define RCC_ICSCR_HSITRIM_6 (0x40U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
12100
12101/******************** Bit definition for RCC_CFGR register ******************/
12102/*!< SW configuration */
12103#define RCC_CFGR_SW_Pos (0U)
12104#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
12105#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
12106#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
12107#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
12108
12109#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI oscillator selection as system clock */
12110#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI16 oscillator selection as system clock */
12111#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE oscillator selection as system clock */
12112#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selection as system clock */
12113
12114/*!< SWS configuration */
12115#define RCC_CFGR_SWS_Pos (2U)
12116#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
12117#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
12118#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
12119#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
12120
12121#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
12122#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI16 oscillator used as system clock */
12123#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
12124#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
12125
12126/*!< HPRE configuration */
12127#define RCC_CFGR_HPRE_Pos (4U)
12128#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
12129#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
12130#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
12131#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
12132#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
12133#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
12134
12135#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
12136#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
12137#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
12138#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
12139#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
12140#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
12141#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
12142#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
12143#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
12144
12145/*!< PPRE1 configuration */
12146#define RCC_CFGR_PPRE1_Pos (8U)
12147#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
12148#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB2 prescaler) */
12149#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
12150#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
12151#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
12152
12153#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
12154#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
12155#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
12156#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
12157#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
12158
12159/*!< PPRE2 configuration */
12160#define RCC_CFGR_PPRE2_Pos (11U)
12161#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
12162#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
12163#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
12164#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
12165#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
12166
12167#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
12168#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
12169#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
12170#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
12171#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
12172
12173#define RCC_CFGR_STOPWUCK_Pos (15U)
12174#define RCC_CFGR_STOPWUCK_Msk (0x1U << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
12175#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */
12176
12177/*!< MCOSEL configuration */
12178#define RCC_CFGR_MCOSEL_Pos (24U)
12179#define RCC_CFGR_MCOSEL_Msk (0xFU << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
12180#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */
12181#define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
12182#define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
12183#define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
12184#define RCC_CFGR_MCOSEL_3 (0x8U << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
12185
12186#define RCC_CFGR_MCOPRE_Pos (28U)
12187#define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
12188#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
12189#define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
12190#define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
12191#define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
12192
12193#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
12194#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
12195#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
12196#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
12197#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
12198
12199/* Legacy aliases */
12200#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
12201#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
12202#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
12203#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
12204#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
12205#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
12206
12207/******************** Bit definition for RCC_PLLCFGR register ***************/
12208#define RCC_PLLCFGR_PLLSRC_Pos (0U)
12209#define RCC_PLLCFGR_PLLSRC_Msk (0x3U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
12210#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
12211
12212#define RCC_PLLCFGR_PLLSRC_MSI_Pos (0U)
12213#define RCC_PLLCFGR_PLLSRC_MSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */
12214#define RCC_PLLCFGR_PLLSRC_MSI RCC_PLLCFGR_PLLSRC_MSI_Msk /*!< MSI oscillator source clock selected */
12215#define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
12216#define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
12217#define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI16 oscillator source clock selected */
12218#define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
12219#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
12220#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE oscillator source clock selected */
12221
12222#define RCC_PLLCFGR_PLLM_Pos (4U)
12223#define RCC_PLLCFGR_PLLM_Msk (0xFU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x000000F0 */
12224#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
12225#define RCC_PLLCFGR_PLLM_0 (0x1U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
12226#define RCC_PLLCFGR_PLLM_1 (0x2U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
12227#define RCC_PLLCFGR_PLLM_2 (0x4U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
12228#define RCC_PLLCFGR_PLLM_3 (0x8U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000080 */
12229
12230#define RCC_PLLCFGR_PLLN_Pos (8U)
12231#define RCC_PLLCFGR_PLLN_Msk (0x7FU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
12232#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
12233#define RCC_PLLCFGR_PLLN_0 (0x01U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
12234#define RCC_PLLCFGR_PLLN_1 (0x02U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
12235#define RCC_PLLCFGR_PLLN_2 (0x04U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
12236#define RCC_PLLCFGR_PLLN_3 (0x08U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
12237#define RCC_PLLCFGR_PLLN_4 (0x10U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
12238#define RCC_PLLCFGR_PLLN_5 (0x20U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
12239#define RCC_PLLCFGR_PLLN_6 (0x40U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
12240
12241#define RCC_PLLCFGR_PLLPEN_Pos (16U)
12242#define RCC_PLLCFGR_PLLPEN_Msk (0x1U << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
12243#define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
12244#define RCC_PLLCFGR_PLLP_Pos (17U)
12245#define RCC_PLLCFGR_PLLP_Msk (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
12246#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
12247#define RCC_PLLCFGR_PLLQEN_Pos (20U)
12248#define RCC_PLLCFGR_PLLQEN_Msk (0x1U << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
12249#define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
12250
12251#define RCC_PLLCFGR_PLLQ_Pos (21U)
12252#define RCC_PLLCFGR_PLLQ_Msk (0x3U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00600000 */
12253#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
12254#define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00200000 */
12255#define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00400000 */
12256
12257#define RCC_PLLCFGR_PLLREN_Pos (24U)
12258#define RCC_PLLCFGR_PLLREN_Msk (0x1U << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
12259#define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
12260#define RCC_PLLCFGR_PLLR_Pos (25U)
12261#define RCC_PLLCFGR_PLLR_Msk (0x3U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x06000000 */
12262#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
12263#define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x02000000 */
12264#define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x04000000 */
12265
12266#define RCC_PLLCFGR_PLLPDIV_Pos (27U)
12267#define RCC_PLLCFGR_PLLPDIV_Msk (0x1FU << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0xF8000000 */
12268#define RCC_PLLCFGR_PLLPDIV RCC_PLLCFGR_PLLPDIV_Msk
12269#define RCC_PLLCFGR_PLLPDIV_0 (0x01U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x08000000 */
12270#define RCC_PLLCFGR_PLLPDIV_1 (0x02U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x10000000 */
12271#define RCC_PLLCFGR_PLLPDIV_2 (0x04U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x20000000 */
12272#define RCC_PLLCFGR_PLLPDIV_3 (0x08U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x40000000 */
12273#define RCC_PLLCFGR_PLLPDIV_4 (0x10U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x80000000 */
12274
12275/******************** Bit definition for RCC_PLLSAI1CFGR register ************/
12276#define RCC_PLLSAI1CFGR_PLLSAI1M_Pos (4U)
12277#define RCC_PLLSAI1CFGR_PLLSAI1M_Msk (0xFU << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) /*!< 0x000000F0 */
12278#define RCC_PLLSAI1CFGR_PLLSAI1M RCC_PLLSAI1CFGR_PLLSAI1M_Msk
12279#define RCC_PLLSAI1CFGR_PLLSAI1M_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) /*!< 0x00000010 */
12280#define RCC_PLLSAI1CFGR_PLLSAI1M_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) /*!< 0x00000020 */
12281#define RCC_PLLSAI1CFGR_PLLSAI1M_2 (0x4U << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) /*!< 0x00000040 */
12282#define RCC_PLLSAI1CFGR_PLLSAI1M_3 (0x8U << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) /*!< 0x00000080 */
12283
12284#define RCC_PLLSAI1CFGR_PLLSAI1N_Pos (8U)
12285#define RCC_PLLSAI1CFGR_PLLSAI1N_Msk (0x7FU << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */
12286#define RCC_PLLSAI1CFGR_PLLSAI1N RCC_PLLSAI1CFGR_PLLSAI1N_Msk
12287#define RCC_PLLSAI1CFGR_PLLSAI1N_0 (0x01U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */
12288#define RCC_PLLSAI1CFGR_PLLSAI1N_1 (0x02U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */
12289#define RCC_PLLSAI1CFGR_PLLSAI1N_2 (0x04U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */
12290#define RCC_PLLSAI1CFGR_PLLSAI1N_3 (0x08U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */
12291#define RCC_PLLSAI1CFGR_PLLSAI1N_4 (0x10U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */
12292#define RCC_PLLSAI1CFGR_PLLSAI1N_5 (0x20U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */
12293#define RCC_PLLSAI1CFGR_PLLSAI1N_6 (0x40U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */
12294
12295#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos (16U)
12296#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */
12297#define RCC_PLLSAI1CFGR_PLLSAI1PEN RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk
12298#define RCC_PLLSAI1CFGR_PLLSAI1P_Pos (17U)
12299#define RCC_PLLSAI1CFGR_PLLSAI1P_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */
12300#define RCC_PLLSAI1CFGR_PLLSAI1P RCC_PLLSAI1CFGR_PLLSAI1P_Msk
12301
12302#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos (20U)
12303#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */
12304#define RCC_PLLSAI1CFGR_PLLSAI1QEN RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk
12305#define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos (21U)
12306#define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */
12307#define RCC_PLLSAI1CFGR_PLLSAI1Q RCC_PLLSAI1CFGR_PLLSAI1Q_Msk
12308#define RCC_PLLSAI1CFGR_PLLSAI1Q_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */
12309#define RCC_PLLSAI1CFGR_PLLSAI1Q_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */
12310
12311#define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos (24U)
12312#define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */
12313#define RCC_PLLSAI1CFGR_PLLSAI1REN RCC_PLLSAI1CFGR_PLLSAI1REN_Msk
12314#define RCC_PLLSAI1CFGR_PLLSAI1R_Pos (25U)
12315#define RCC_PLLSAI1CFGR_PLLSAI1R_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */
12316#define RCC_PLLSAI1CFGR_PLLSAI1R RCC_PLLSAI1CFGR_PLLSAI1R_Msk
12317#define RCC_PLLSAI1CFGR_PLLSAI1R_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */
12318#define RCC_PLLSAI1CFGR_PLLSAI1R_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */
12319
12320#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos (27U)
12321#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk (0x1FU << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0xF8000000 */
12322#define RCC_PLLSAI1CFGR_PLLSAI1PDIV RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk
12323#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_0 (0x01U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x08000000 */
12324#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_1 (0x02U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x10000000 */
12325#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_2 (0x04U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x20000000 */
12326#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_3 (0x08U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x40000000 */
12327#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_4 (0x10U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x80000000 */
12328
12329/******************** Bit definition for RCC_PLLSAI2CFGR register ************/
12330#define RCC_PLLSAI2CFGR_PLLSAI2M_Pos (4U)
12331#define RCC_PLLSAI2CFGR_PLLSAI2M_Msk (0xFU << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) /*!< 0x000000F0 */
12332#define RCC_PLLSAI2CFGR_PLLSAI2M RCC_PLLSAI2CFGR_PLLSAI2M_Msk
12333#define RCC_PLLSAI2CFGR_PLLSAI2M_0 (0x1U << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) /*!< 0x00000010 */
12334#define RCC_PLLSAI2CFGR_PLLSAI2M_1 (0x2U << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) /*!< 0x00000020 */
12335#define RCC_PLLSAI2CFGR_PLLSAI2M_2 (0x4U << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) /*!< 0x00000040 */
12336#define RCC_PLLSAI2CFGR_PLLSAI2M_3 (0x8U << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) /*!< 0x00000080 */
12337
12338#define RCC_PLLSAI2CFGR_PLLSAI2N_Pos (8U)
12339#define RCC_PLLSAI2CFGR_PLLSAI2N_Msk (0x7FU << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00007F00 */
12340#define RCC_PLLSAI2CFGR_PLLSAI2N RCC_PLLSAI2CFGR_PLLSAI2N_Msk
12341#define RCC_PLLSAI2CFGR_PLLSAI2N_0 (0x01U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000100 */
12342#define RCC_PLLSAI2CFGR_PLLSAI2N_1 (0x02U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000200 */
12343#define RCC_PLLSAI2CFGR_PLLSAI2N_2 (0x04U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000400 */
12344#define RCC_PLLSAI2CFGR_PLLSAI2N_3 (0x08U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000800 */
12345#define RCC_PLLSAI2CFGR_PLLSAI2N_4 (0x10U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00001000 */
12346#define RCC_PLLSAI2CFGR_PLLSAI2N_5 (0x20U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00002000 */
12347#define RCC_PLLSAI2CFGR_PLLSAI2N_6 (0x40U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00004000 */
12348
12349#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos (16U)
12350#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos) /*!< 0x00010000 */
12351#define RCC_PLLSAI2CFGR_PLLSAI2PEN RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk
12352#define RCC_PLLSAI2CFGR_PLLSAI2P_Pos (17U)
12353#define RCC_PLLSAI2CFGR_PLLSAI2P_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) /*!< 0x00020000 */
12354#define RCC_PLLSAI2CFGR_PLLSAI2P RCC_PLLSAI2CFGR_PLLSAI2P_Msk
12355
12356#define RCC_PLLSAI2CFGR_PLLSAI2QEN_Pos (20U)
12357#define RCC_PLLSAI2CFGR_PLLSAI2QEN_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2QEN_Pos) /*!< 0x00100000 */
12358#define RCC_PLLSAI2CFGR_PLLSAI2QEN RCC_PLLSAI2CFGR_PLLSAI2QEN_Msk
12359#define RCC_PLLSAI2CFGR_PLLSAI2Q_Pos (21U)
12360#define RCC_PLLSAI2CFGR_PLLSAI2Q_Msk (0x3U << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) /*!< 0x00600000 */
12361#define RCC_PLLSAI2CFGR_PLLSAI2Q RCC_PLLSAI2CFGR_PLLSAI2Q_Msk
12362#define RCC_PLLSAI2CFGR_PLLSAI2Q_0 (0x1U << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) /*!< 0x00200000 */
12363#define RCC_PLLSAI2CFGR_PLLSAI2Q_1 (0x2U << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) /*!< 0x00400000 */
12364
12365#define RCC_PLLSAI2CFGR_PLLSAI2REN_Pos (24U)
12366#define RCC_PLLSAI2CFGR_PLLSAI2REN_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2REN_Pos) /*!< 0x01000000 */
12367#define RCC_PLLSAI2CFGR_PLLSAI2REN RCC_PLLSAI2CFGR_PLLSAI2REN_Msk
12368#define RCC_PLLSAI2CFGR_PLLSAI2R_Pos (25U)
12369#define RCC_PLLSAI2CFGR_PLLSAI2R_Msk (0x3U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x06000000 */
12370#define RCC_PLLSAI2CFGR_PLLSAI2R RCC_PLLSAI2CFGR_PLLSAI2R_Msk
12371#define RCC_PLLSAI2CFGR_PLLSAI2R_0 (0x1U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x02000000 */
12372#define RCC_PLLSAI2CFGR_PLLSAI2R_1 (0x2U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x04000000 */
12373
12374#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos (27U)
12375#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_Msk (0x1FU << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0xF8000000 */
12376#define RCC_PLLSAI2CFGR_PLLSAI2PDIV RCC_PLLSAI2CFGR_PLLSAI2PDIV_Msk
12377#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_0 (0x01U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x08000000 */
12378#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_1 (0x02U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x10000000 */
12379#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_2 (0x04U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x20000000 */
12380#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_3 (0x08U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x40000000 */
12381#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_4 (0x10U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x80000000 */
12382
12383/******************** Bit definition for RCC_CIER register ******************/
12384#define RCC_CIER_LSIRDYIE_Pos (0U)
12385#define RCC_CIER_LSIRDYIE_Msk (0x1U << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
12386#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
12387#define RCC_CIER_LSERDYIE_Pos (1U)
12388#define RCC_CIER_LSERDYIE_Msk (0x1U << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
12389#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
12390#define RCC_CIER_MSIRDYIE_Pos (2U)
12391#define RCC_CIER_MSIRDYIE_Msk (0x1U << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */
12392#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk
12393#define RCC_CIER_HSIRDYIE_Pos (3U)
12394#define RCC_CIER_HSIRDYIE_Msk (0x1U << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
12395#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
12396#define RCC_CIER_HSERDYIE_Pos (4U)
12397#define RCC_CIER_HSERDYIE_Msk (0x1U << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
12398#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
12399#define RCC_CIER_PLLRDYIE_Pos (5U)
12400#define RCC_CIER_PLLRDYIE_Msk (0x1U << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
12401#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
12402#define RCC_CIER_PLLSAI1RDYIE_Pos (6U)
12403#define RCC_CIER_PLLSAI1RDYIE_Msk (0x1U << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */
12404#define RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE_Msk
12405#define RCC_CIER_PLLSAI2RDYIE_Pos (7U)
12406#define RCC_CIER_PLLSAI2RDYIE_Msk (0x1U << RCC_CIER_PLLSAI2RDYIE_Pos) /*!< 0x00000080 */
12407#define RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE_Msk
12408#define RCC_CIER_LSECSSIE_Pos (9U)
12409#define RCC_CIER_LSECSSIE_Msk (0x1U << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
12410#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
12411#define RCC_CIER_HSI48RDYIE_Pos (10U)
12412#define RCC_CIER_HSI48RDYIE_Msk (0x1U << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000400 */
12413#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
12414
12415/******************** Bit definition for RCC_CIFR register ******************/
12416#define RCC_CIFR_LSIRDYF_Pos (0U)
12417#define RCC_CIFR_LSIRDYF_Msk (0x1U << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
12418#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
12419#define RCC_CIFR_LSERDYF_Pos (1U)
12420#define RCC_CIFR_LSERDYF_Msk (0x1U << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
12421#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
12422#define RCC_CIFR_MSIRDYF_Pos (2U)
12423#define RCC_CIFR_MSIRDYF_Msk (0x1U << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */
12424#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk
12425#define RCC_CIFR_HSIRDYF_Pos (3U)
12426#define RCC_CIFR_HSIRDYF_Msk (0x1U << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
12427#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
12428#define RCC_CIFR_HSERDYF_Pos (4U)
12429#define RCC_CIFR_HSERDYF_Msk (0x1U << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
12430#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
12431#define RCC_CIFR_PLLRDYF_Pos (5U)
12432#define RCC_CIFR_PLLRDYF_Msk (0x1U << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
12433#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
12434#define RCC_CIFR_PLLSAI1RDYF_Pos (6U)
12435#define RCC_CIFR_PLLSAI1RDYF_Msk (0x1U << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */
12436#define RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF_Msk
12437#define RCC_CIFR_PLLSAI2RDYF_Pos (7U)
12438#define RCC_CIFR_PLLSAI2RDYF_Msk (0x1U << RCC_CIFR_PLLSAI2RDYF_Pos) /*!< 0x00000080 */
12439#define RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF_Msk
12440#define RCC_CIFR_CSSF_Pos (8U)
12441#define RCC_CIFR_CSSF_Msk (0x1U << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
12442#define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
12443#define RCC_CIFR_LSECSSF_Pos (9U)
12444#define RCC_CIFR_LSECSSF_Msk (0x1U << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
12445#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
12446#define RCC_CIFR_HSI48RDYF_Pos (10U)
12447#define RCC_CIFR_HSI48RDYF_Msk (0x1U << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
12448#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
12449
12450/******************** Bit definition for RCC_CICR register ******************/
12451#define RCC_CICR_LSIRDYC_Pos (0U)
12452#define RCC_CICR_LSIRDYC_Msk (0x1U << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
12453#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
12454#define RCC_CICR_LSERDYC_Pos (1U)
12455#define RCC_CICR_LSERDYC_Msk (0x1U << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
12456#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
12457#define RCC_CICR_MSIRDYC_Pos (2U)
12458#define RCC_CICR_MSIRDYC_Msk (0x1U << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */
12459#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk
12460#define RCC_CICR_HSIRDYC_Pos (3U)
12461#define RCC_CICR_HSIRDYC_Msk (0x1U << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
12462#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
12463#define RCC_CICR_HSERDYC_Pos (4U)
12464#define RCC_CICR_HSERDYC_Msk (0x1U << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
12465#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
12466#define RCC_CICR_PLLRDYC_Pos (5U)
12467#define RCC_CICR_PLLRDYC_Msk (0x1U << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
12468#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
12469#define RCC_CICR_PLLSAI1RDYC_Pos (6U)
12470#define RCC_CICR_PLLSAI1RDYC_Msk (0x1U << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */
12471#define RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC_Msk
12472#define RCC_CICR_PLLSAI2RDYC_Pos (7U)
12473#define RCC_CICR_PLLSAI2RDYC_Msk (0x1U << RCC_CICR_PLLSAI2RDYC_Pos) /*!< 0x00000080 */
12474#define RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC_Msk
12475#define RCC_CICR_CSSC_Pos (8U)
12476#define RCC_CICR_CSSC_Msk (0x1U << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
12477#define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
12478#define RCC_CICR_LSECSSC_Pos (9U)
12479#define RCC_CICR_LSECSSC_Msk (0x1U << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
12480#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
12481#define RCC_CICR_HSI48RDYC_Pos (10U)
12482#define RCC_CICR_HSI48RDYC_Msk (0x1U << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
12483#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
12484
12485/******************** Bit definition for RCC_AHB1RSTR register **************/
12486#define RCC_AHB1RSTR_DMA1RST_Pos (0U)
12487#define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
12488#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
12489#define RCC_AHB1RSTR_DMA2RST_Pos (1U)
12490#define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
12491#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
12492#define RCC_AHB1RSTR_DMAMUX1RST_Pos (2U)
12493#define RCC_AHB1RSTR_DMAMUX1RST_Msk (0x1U << RCC_AHB1RSTR_DMAMUX1RST_Pos) /*!< 0x00000004 */
12494#define RCC_AHB1RSTR_DMAMUX1RST RCC_AHB1RSTR_DMAMUX1RST_Msk
12495#define RCC_AHB1RSTR_FLASHRST_Pos (8U)
12496#define RCC_AHB1RSTR_FLASHRST_Msk (0x1U << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */
12497#define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
12498#define RCC_AHB1RSTR_CRCRST_Pos (12U)
12499#define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
12500#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
12501#define RCC_AHB1RSTR_TSCRST_Pos (16U)
12502#define RCC_AHB1RSTR_TSCRST_Msk (0x1U << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */
12503#define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk
12504#define RCC_AHB1RSTR_DMA2DRST_Pos (17U)
12505#define RCC_AHB1RSTR_DMA2DRST_Msk (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00020000 */
12506#define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
12507
12508/******************** Bit definition for RCC_AHB2RSTR register **************/
12509#define RCC_AHB2RSTR_GPIOARST_Pos (0U)
12510#define RCC_AHB2RSTR_GPIOARST_Msk (0x1U << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */
12511#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
12512#define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
12513#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1U << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
12514#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
12515#define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
12516#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1U << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
12517#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
12518#define RCC_AHB2RSTR_GPIODRST_Pos (3U)
12519#define RCC_AHB2RSTR_GPIODRST_Msk (0x1U << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */
12520#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk
12521#define RCC_AHB2RSTR_GPIOERST_Pos (4U)
12522#define RCC_AHB2RSTR_GPIOERST_Msk (0x1U << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */
12523#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk
12524#define RCC_AHB2RSTR_GPIOFRST_Pos (5U)
12525#define RCC_AHB2RSTR_GPIOFRST_Msk (0x1U << RCC_AHB2RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
12526#define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk
12527#define RCC_AHB2RSTR_GPIOGRST_Pos (6U)
12528#define RCC_AHB2RSTR_GPIOGRST_Msk (0x1U << RCC_AHB2RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
12529#define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk
12530#define RCC_AHB2RSTR_GPIOHRST_Pos (7U)
12531#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1U << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
12532#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk
12533#define RCC_AHB2RSTR_GPIOIRST_Pos (8U)
12534#define RCC_AHB2RSTR_GPIOIRST_Msk (0x1U << RCC_AHB2RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
12535#define RCC_AHB2RSTR_GPIOIRST RCC_AHB2RSTR_GPIOIRST_Msk
12536#define RCC_AHB2RSTR_OTGFSRST_Pos (12U)
12537#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00001000 */
12538#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
12539#define RCC_AHB2RSTR_ADCRST_Pos (13U)
12540#define RCC_AHB2RSTR_ADCRST_Msk (0x1U << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */
12541#define RCC_AHB2RSTR_ADCRST RCC_AHB2RSTR_ADCRST_Msk
12542#define RCC_AHB2RSTR_DCMIRST_Pos (14U)
12543#define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00004000 */
12544#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
12545#define RCC_AHB2RSTR_AESRST_Pos (16U)
12546#define RCC_AHB2RSTR_AESRST_Msk (0x1U << RCC_AHB2RSTR_AESRST_Pos) /*!< 0x00010000 */
12547#define RCC_AHB2RSTR_AESRST RCC_AHB2RSTR_AESRST_Msk
12548#define RCC_AHB2RSTR_HASHRST_Pos (17U)
12549#define RCC_AHB2RSTR_HASHRST_Msk (0x1U << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00020000 */
12550#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
12551#define RCC_AHB2RSTR_RNGRST_Pos (18U)
12552#define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */
12553#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
12554#define RCC_AHB2RSTR_OSPIMRST_Pos (20U)
12555#define RCC_AHB2RSTR_OSPIMRST_Msk (0x1U << RCC_AHB2RSTR_OSPIMRST_Pos) /*!< 0x00100000 */
12556#define RCC_AHB2RSTR_OSPIMRST RCC_AHB2RSTR_OSPIMRST_Msk
12557#define RCC_AHB2RSTR_SDMMC1RST_Pos (22U)
12558#define RCC_AHB2RSTR_SDMMC1RST_Msk (0x1U << RCC_AHB2RSTR_SDMMC1RST_Pos) /*!< 0x00400000 */
12559#define RCC_AHB2RSTR_SDMMC1RST RCC_AHB2RSTR_SDMMC1RST_Msk
12560
12561/******************** Bit definition for RCC_AHB3RSTR register **************/
12562#define RCC_AHB3RSTR_FMCRST_Pos (0U)
12563#define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
12564#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
12565#define RCC_AHB3RSTR_OSPI1RST_Pos (8U)
12566#define RCC_AHB3RSTR_OSPI1RST_Msk (0x1U << RCC_AHB3RSTR_OSPI1RST_Pos) /*!< 0x00000100 */
12567#define RCC_AHB3RSTR_OSPI1RST RCC_AHB3RSTR_OSPI1RST_Msk
12568#define RCC_AHB3RSTR_OSPI2RST_Pos (9U)
12569#define RCC_AHB3RSTR_OSPI2RST_Msk (0x1U << RCC_AHB3RSTR_OSPI2RST_Pos) /*!< 0x00000200 */
12570#define RCC_AHB3RSTR_OSPI2RST RCC_AHB3RSTR_OSPI2RST_Msk
12571
12572/******************** Bit definition for RCC_APB1RSTR1 register **************/
12573#define RCC_APB1RSTR1_TIM2RST_Pos (0U)
12574#define RCC_APB1RSTR1_TIM2RST_Msk (0x1U << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */
12575#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
12576#define RCC_APB1RSTR1_TIM3RST_Pos (1U)
12577#define RCC_APB1RSTR1_TIM3RST_Msk (0x1U << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */
12578#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk
12579#define RCC_APB1RSTR1_TIM4RST_Pos (2U)
12580#define RCC_APB1RSTR1_TIM4RST_Msk (0x1U << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */
12581#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk
12582#define RCC_APB1RSTR1_TIM5RST_Pos (3U)
12583#define RCC_APB1RSTR1_TIM5RST_Msk (0x1U << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */
12584#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk
12585#define RCC_APB1RSTR1_TIM6RST_Pos (4U)
12586#define RCC_APB1RSTR1_TIM6RST_Msk (0x1U << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */
12587#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
12588#define RCC_APB1RSTR1_TIM7RST_Pos (5U)
12589#define RCC_APB1RSTR1_TIM7RST_Msk (0x1U << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */
12590#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
12591#define RCC_APB1RSTR1_SPI2RST_Pos (14U)
12592#define RCC_APB1RSTR1_SPI2RST_Msk (0x1U << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */
12593#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk
12594#define RCC_APB1RSTR1_SPI3RST_Pos (15U)
12595#define RCC_APB1RSTR1_SPI3RST_Msk (0x1U << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */
12596#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
12597#define RCC_APB1RSTR1_USART2RST_Pos (17U)
12598#define RCC_APB1RSTR1_USART2RST_Msk (0x1U << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */
12599#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
12600#define RCC_APB1RSTR1_USART3RST_Pos (18U)
12601#define RCC_APB1RSTR1_USART3RST_Msk (0x1U << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */
12602#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk
12603#define RCC_APB1RSTR1_UART4RST_Pos (19U)
12604#define RCC_APB1RSTR1_UART4RST_Msk (0x1U << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */
12605#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk
12606#define RCC_APB1RSTR1_UART5RST_Pos (20U)
12607#define RCC_APB1RSTR1_UART5RST_Msk (0x1U << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */
12608#define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk
12609#define RCC_APB1RSTR1_I2C1RST_Pos (21U)
12610#define RCC_APB1RSTR1_I2C1RST_Msk (0x1U << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */
12611#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
12612#define RCC_APB1RSTR1_I2C2RST_Pos (22U)
12613#define RCC_APB1RSTR1_I2C2RST_Msk (0x1U << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */
12614#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk
12615#define RCC_APB1RSTR1_I2C3RST_Pos (23U)
12616#define RCC_APB1RSTR1_I2C3RST_Msk (0x1U << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */
12617#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
12618#define RCC_APB1RSTR1_CRSRST_Pos (24U)
12619#define RCC_APB1RSTR1_CRSRST_Msk (0x1U << RCC_APB1RSTR1_CRSRST_Pos) /*!< 0x01000000 */
12620#define RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk
12621#define RCC_APB1RSTR1_CAN1RST_Pos (25U)
12622#define RCC_APB1RSTR1_CAN1RST_Msk (0x1U << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */
12623#define RCC_APB1RSTR1_CAN1RST RCC_APB1RSTR1_CAN1RST_Msk
12624#define RCC_APB1RSTR1_PWRRST_Pos (28U)
12625#define RCC_APB1RSTR1_PWRRST_Msk (0x1U << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */
12626#define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
12627#define RCC_APB1RSTR1_DAC1RST_Pos (29U)
12628#define RCC_APB1RSTR1_DAC1RST_Msk (0x1U << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */
12629#define RCC_APB1RSTR1_DAC1RST RCC_APB1RSTR1_DAC1RST_Msk
12630#define RCC_APB1RSTR1_OPAMPRST_Pos (30U)
12631#define RCC_APB1RSTR1_OPAMPRST_Msk (0x1U << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */
12632#define RCC_APB1RSTR1_OPAMPRST RCC_APB1RSTR1_OPAMPRST_Msk
12633#define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
12634#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
12635#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
12636
12637/******************** Bit definition for RCC_APB1RSTR2 register **************/
12638#define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
12639#define RCC_APB1RSTR2_LPUART1RST_Msk (0x1U << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */
12640#define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
12641#define RCC_APB1RSTR2_I2C4RST_Pos (1U)
12642#define RCC_APB1RSTR2_I2C4RST_Msk (0x1U << RCC_APB1RSTR2_I2C4RST_Pos) /*!< 0x00000002 */
12643#define RCC_APB1RSTR2_I2C4RST RCC_APB1RSTR2_I2C4RST_Msk
12644#define RCC_APB1RSTR2_LPTIM2RST_Pos (5U)
12645#define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1U << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */
12646#define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk
12647
12648/******************** Bit definition for RCC_APB2RSTR register **************/
12649#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
12650#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
12651#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
12652#define RCC_APB2RSTR_TIM1RST_Pos (11U)
12653#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
12654#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
12655#define RCC_APB2RSTR_SPI1RST_Pos (12U)
12656#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
12657#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
12658#define RCC_APB2RSTR_TIM8RST_Pos (13U)
12659#define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */
12660#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
12661#define RCC_APB2RSTR_USART1RST_Pos (14U)
12662#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
12663#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
12664#define RCC_APB2RSTR_TIM15RST_Pos (16U)
12665#define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
12666#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
12667#define RCC_APB2RSTR_TIM16RST_Pos (17U)
12668#define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
12669#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
12670#define RCC_APB2RSTR_TIM17RST_Pos (18U)
12671#define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
12672#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
12673#define RCC_APB2RSTR_SAI1RST_Pos (21U)
12674#define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
12675#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
12676#define RCC_APB2RSTR_SAI2RST_Pos (22U)
12677#define RCC_APB2RSTR_SAI2RST_Msk (0x1U << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00400000 */
12678#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
12679#define RCC_APB2RSTR_DFSDM1RST_Pos (24U)
12680#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */
12681#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
12682
12683/******************** Bit definition for RCC_AHB1ENR register ***************/
12684#define RCC_AHB1ENR_DMA1EN_Pos (0U)
12685#define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
12686#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
12687#define RCC_AHB1ENR_DMA2EN_Pos (1U)
12688#define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
12689#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
12690#define RCC_AHB1ENR_DMAMUX1EN_Pos (2U)
12691#define RCC_AHB1ENR_DMAMUX1EN_Msk (0x1U << RCC_AHB1ENR_DMAMUX1EN_Pos) /*!< 0x00000004 */
12692#define RCC_AHB1ENR_DMAMUX1EN RCC_AHB1ENR_DMAMUX1EN_Msk
12693#define RCC_AHB1ENR_FLASHEN_Pos (8U)
12694#define RCC_AHB1ENR_FLASHEN_Msk (0x1U << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */
12695#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
12696#define RCC_AHB1ENR_CRCEN_Pos (12U)
12697#define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
12698#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
12699#define RCC_AHB1ENR_TSCEN_Pos (16U)
12700#define RCC_AHB1ENR_TSCEN_Msk (0x1U << RCC_AHB1ENR_TSCEN_Pos) /*!< 0x00010000 */
12701#define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk
12702#define RCC_AHB1ENR_DMA2DEN_Pos (17U)
12703#define RCC_AHB1ENR_DMA2DEN_Msk (0x1U << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00020000 */
12704#define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
12705
12706/******************** Bit definition for RCC_AHB2ENR register ***************/
12707#define RCC_AHB2ENR_GPIOAEN_Pos (0U)
12708#define RCC_AHB2ENR_GPIOAEN_Msk (0x1U << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
12709#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
12710#define RCC_AHB2ENR_GPIOBEN_Pos (1U)
12711#define RCC_AHB2ENR_GPIOBEN_Msk (0x1U << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
12712#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
12713#define RCC_AHB2ENR_GPIOCEN_Pos (2U)
12714#define RCC_AHB2ENR_GPIOCEN_Msk (0x1U << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
12715#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
12716#define RCC_AHB2ENR_GPIODEN_Pos (3U)
12717#define RCC_AHB2ENR_GPIODEN_Msk (0x1U << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */
12718#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk
12719#define RCC_AHB2ENR_GPIOEEN_Pos (4U)
12720#define RCC_AHB2ENR_GPIOEEN_Msk (0x1U << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */
12721#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk
12722#define RCC_AHB2ENR_GPIOFEN_Pos (5U)
12723#define RCC_AHB2ENR_GPIOFEN_Msk (0x1U << RCC_AHB2ENR_GPIOFEN_Pos) /*!< 0x00000020 */
12724#define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk
12725#define RCC_AHB2ENR_GPIOGEN_Pos (6U)
12726#define RCC_AHB2ENR_GPIOGEN_Msk (0x1U << RCC_AHB2ENR_GPIOGEN_Pos) /*!< 0x00000040 */
12727#define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk
12728#define RCC_AHB2ENR_GPIOHEN_Pos (7U)
12729#define RCC_AHB2ENR_GPIOHEN_Msk (0x1U << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
12730#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk
12731#define RCC_AHB2ENR_GPIOIEN_Pos (8U)
12732#define RCC_AHB2ENR_GPIOIEN_Msk (0x1U << RCC_AHB2ENR_GPIOIEN_Pos) /*!< 0x00000100 */
12733#define RCC_AHB2ENR_GPIOIEN RCC_AHB2ENR_GPIOIEN_Msk
12734#define RCC_AHB2ENR_OTGFSEN_Pos (12U)
12735#define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00001000 */
12736#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
12737#define RCC_AHB2ENR_ADCEN_Pos (13U)
12738#define RCC_AHB2ENR_ADCEN_Msk (0x1U << RCC_AHB2ENR_ADCEN_Pos) /*!< 0x00002000 */
12739#define RCC_AHB2ENR_ADCEN RCC_AHB2ENR_ADCEN_Msk
12740#define RCC_AHB2ENR_DCMIEN_Pos (14U)
12741#define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00004000 */
12742#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
12743#define RCC_AHB2ENR_AESEN_Pos (16U)
12744#define RCC_AHB2ENR_AESEN_Msk (0x1U << RCC_AHB2ENR_AESEN_Pos) /*!< 0x00010000 */
12745#define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk
12746#define RCC_AHB2ENR_HASHEN_Pos (17U)
12747#define RCC_AHB2ENR_HASHEN_Msk (0x1U << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00020000 */
12748#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
12749#define RCC_AHB2ENR_RNGEN_Pos (18U)
12750#define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */
12751#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
12752#define RCC_AHB2ENR_OSPIMEN_Pos (20U)
12753#define RCC_AHB2ENR_OSPIMEN_Msk (0x1U << RCC_AHB2ENR_OSPIMEN_Pos) /*!< 0x00100000 */
12754#define RCC_AHB2ENR_OSPIMEN RCC_AHB2ENR_OSPIMEN_Msk
12755#define RCC_AHB2ENR_SDMMC1EN_Pos (22U)
12756#define RCC_AHB2ENR_SDMMC1EN_Msk (0x1U << RCC_AHB2ENR_SDMMC1EN_Pos) /*!< 0x00400000 */
12757#define RCC_AHB2ENR_SDMMC1EN RCC_AHB2ENR_SDMMC1EN_Msk
12758
12759/******************** Bit definition for RCC_AHB3ENR register ***************/
12760#define RCC_AHB3ENR_FMCEN_Pos (0U)
12761#define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
12762#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
12763#define RCC_AHB3ENR_OSPI1EN_Pos (8U)
12764#define RCC_AHB3ENR_OSPI1EN_Msk (0x1U << RCC_AHB3ENR_OSPI1EN_Pos) /*!< 0x00000100 */
12765#define RCC_AHB3ENR_OSPI1EN RCC_AHB3ENR_OSPI1EN_Msk
12766#define RCC_AHB3ENR_OSPI2EN_Pos (9U)
12767#define RCC_AHB3ENR_OSPI2EN_Msk (0x1U << RCC_AHB3ENR_OSPI2EN_Pos) /*!< 0x00000200 */
12768#define RCC_AHB3ENR_OSPI2EN RCC_AHB3ENR_OSPI2EN_Msk
12769
12770/******************** Bit definition for RCC_APB1ENR1 register ***************/
12771#define RCC_APB1ENR1_TIM2EN_Pos (0U)
12772#define RCC_APB1ENR1_TIM2EN_Msk (0x1U << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
12773#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
12774#define RCC_APB1ENR1_TIM3EN_Pos (1U)
12775#define RCC_APB1ENR1_TIM3EN_Msk (0x1U << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */
12776#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk
12777#define RCC_APB1ENR1_TIM4EN_Pos (2U)
12778#define RCC_APB1ENR1_TIM4EN_Msk (0x1U << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */
12779#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk
12780#define RCC_APB1ENR1_TIM5EN_Pos (3U)
12781#define RCC_APB1ENR1_TIM5EN_Msk (0x1U << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */
12782#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk
12783#define RCC_APB1ENR1_TIM6EN_Pos (4U)
12784#define RCC_APB1ENR1_TIM6EN_Msk (0x1U << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */
12785#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
12786#define RCC_APB1ENR1_TIM7EN_Pos (5U)
12787#define RCC_APB1ENR1_TIM7EN_Msk (0x1U << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */
12788#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
12789#define RCC_APB1ENR1_RTCAPBEN_Pos (10U)
12790#define RCC_APB1ENR1_RTCAPBEN_Msk (0x1U << RCC_APB1ENR1_RTCAPBEN_Pos) /*!< 0x00000400 */
12791#define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk
12792#define RCC_APB1ENR1_WWDGEN_Pos (11U)
12793#define RCC_APB1ENR1_WWDGEN_Msk (0x1U << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
12794#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
12795#define RCC_APB1ENR1_SPI2EN_Pos (14U)
12796#define RCC_APB1ENR1_SPI2EN_Msk (0x1U << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */
12797#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk
12798#define RCC_APB1ENR1_SPI3EN_Pos (15U)
12799#define RCC_APB1ENR1_SPI3EN_Msk (0x1U << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */
12800#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
12801#define RCC_APB1ENR1_USART2EN_Pos (17U)
12802#define RCC_APB1ENR1_USART2EN_Msk (0x1U << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
12803#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
12804#define RCC_APB1ENR1_USART3EN_Pos (18U)
12805#define RCC_APB1ENR1_USART3EN_Msk (0x1U << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */
12806#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk
12807#define RCC_APB1ENR1_UART4EN_Pos (19U)
12808#define RCC_APB1ENR1_UART4EN_Msk (0x1U << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */
12809#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk
12810#define RCC_APB1ENR1_UART5EN_Pos (20U)
12811#define RCC_APB1ENR1_UART5EN_Msk (0x1U << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */
12812#define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk
12813#define RCC_APB1ENR1_I2C1EN_Pos (21U)
12814#define RCC_APB1ENR1_I2C1EN_Msk (0x1U << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
12815#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
12816#define RCC_APB1ENR1_I2C2EN_Pos (22U)
12817#define RCC_APB1ENR1_I2C2EN_Msk (0x1U << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */
12818#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk
12819#define RCC_APB1ENR1_I2C3EN_Pos (23U)
12820#define RCC_APB1ENR1_I2C3EN_Msk (0x1U << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
12821#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
12822#define RCC_APB1ENR1_CRSEN_Pos (24U)
12823#define RCC_APB1ENR1_CRSEN_Msk (0x1U << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x01000000 */
12824#define RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk
12825#define RCC_APB1ENR1_CAN1EN_Pos (25U)
12826#define RCC_APB1ENR1_CAN1EN_Msk (0x1U << RCC_APB1ENR1_CAN1EN_Pos) /*!< 0x02000000 */
12827#define RCC_APB1ENR1_CAN1EN RCC_APB1ENR1_CAN1EN_Msk
12828#define RCC_APB1ENR1_PWREN_Pos (28U)
12829#define RCC_APB1ENR1_PWREN_Msk (0x1U << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
12830#define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
12831#define RCC_APB1ENR1_DAC1EN_Pos (29U)
12832#define RCC_APB1ENR1_DAC1EN_Msk (0x1U << RCC_APB1ENR1_DAC1EN_Pos) /*!< 0x20000000 */
12833#define RCC_APB1ENR1_DAC1EN RCC_APB1ENR1_DAC1EN_Msk
12834#define RCC_APB1ENR1_OPAMPEN_Pos (30U)
12835#define RCC_APB1ENR1_OPAMPEN_Msk (0x1U << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */
12836#define RCC_APB1ENR1_OPAMPEN RCC_APB1ENR1_OPAMPEN_Msk
12837#define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
12838#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1U << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
12839#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
12840
12841/******************** Bit definition for RCC_APB1RSTR2 register **************/
12842#define RCC_APB1ENR2_LPUART1EN_Pos (0U)
12843#define RCC_APB1ENR2_LPUART1EN_Msk (0x1U << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */
12844#define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
12845#define RCC_APB1ENR2_I2C4EN_Pos (1U)
12846#define RCC_APB1ENR2_I2C4EN_Msk (0x1U << RCC_APB1ENR2_I2C4EN_Pos) /*!< 0x00000002 */
12847#define RCC_APB1ENR2_I2C4EN RCC_APB1ENR2_I2C4EN_Msk
12848#define RCC_APB1ENR2_LPTIM2EN_Pos (5U)
12849#define RCC_APB1ENR2_LPTIM2EN_Msk (0x1U << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */
12850#define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk
12851
12852/******************** Bit definition for RCC_APB2ENR register ***************/
12853#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
12854#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
12855#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
12856#define RCC_APB2ENR_FWEN_Pos (7U)
12857#define RCC_APB2ENR_FWEN_Msk (0x1U << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
12858#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk
12859#define RCC_APB2ENR_TIM1EN_Pos (11U)
12860#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
12861#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
12862#define RCC_APB2ENR_SPI1EN_Pos (12U)
12863#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
12864#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
12865#define RCC_APB2ENR_TIM8EN_Pos (13U)
12866#define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
12867#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
12868#define RCC_APB2ENR_USART1EN_Pos (14U)
12869#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
12870#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
12871#define RCC_APB2ENR_TIM15EN_Pos (16U)
12872#define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
12873#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
12874#define RCC_APB2ENR_TIM16EN_Pos (17U)
12875#define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
12876#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
12877#define RCC_APB2ENR_TIM17EN_Pos (18U)
12878#define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
12879#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
12880#define RCC_APB2ENR_SAI1EN_Pos (21U)
12881#define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */
12882#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
12883#define RCC_APB2ENR_SAI2EN_Pos (22U)
12884#define RCC_APB2ENR_SAI2EN_Msk (0x1U << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00400000 */
12885#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
12886#define RCC_APB2ENR_DFSDM1EN_Pos (24U)
12887#define RCC_APB2ENR_DFSDM1EN_Msk (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */
12888#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
12889
12890/******************** Bit definition for RCC_AHB1SMENR register ***************/
12891#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
12892#define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
12893#define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
12894#define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
12895#define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */
12896#define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
12897#define RCC_AHB1SMENR_DMAMUX1SMEN_Pos (2U)
12898#define RCC_AHB1SMENR_DMAMUX1SMEN_Msk (0x1U << RCC_AHB1SMENR_DMAMUX1SMEN_Pos) /*!< 0x00000004 */
12899#define RCC_AHB1SMENR_DMAMUX1SMEN RCC_AHB1SMENR_DMAMUX1SMEN_Msk
12900#define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
12901#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1U << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
12902#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
12903#define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
12904#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1U << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */
12905#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
12906#define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
12907#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1U << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
12908#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
12909#define RCC_AHB1SMENR_TSCSMEN_Pos (16U)
12910#define RCC_AHB1SMENR_TSCSMEN_Msk (0x1U << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
12911#define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk
12912#define RCC_AHB1SMENR_DMA2DSMEN_Pos (17U)
12913#define RCC_AHB1SMENR_DMA2DSMEN_Msk (0x1U << RCC_AHB1SMENR_DMA2DSMEN_Pos) /*!< 0x00020000 */
12914#define RCC_AHB1SMENR_DMA2DSMEN RCC_AHB1SMENR_DMA2DSMEN_Msk
12915
12916/******************** Bit definition for RCC_AHB2SMENR register *************/
12917#define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
12918#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
12919#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
12920#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
12921#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
12922#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
12923#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
12924#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
12925#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
12926#define RCC_AHB2SMENR_GPIODSMEN_Pos (3U)
12927#define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIODSMEN_Pos) /*!< 0x00000008 */
12928#define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk
12929#define RCC_AHB2SMENR_GPIOESMEN_Pos (4U)
12930#define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOESMEN_Pos) /*!< 0x00000010 */
12931#define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk
12932#define RCC_AHB2SMENR_GPIOFSMEN_Pos (5U)
12933#define RCC_AHB2SMENR_GPIOFSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOFSMEN_Pos) /*!< 0x00000020 */
12934#define RCC_AHB2SMENR_GPIOFSMEN RCC_AHB2SMENR_GPIOFSMEN_Msk
12935#define RCC_AHB2SMENR_GPIOGSMEN_Pos (6U)
12936#define RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOGSMEN_Pos) /*!< 0x00000040 */
12937#define RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk
12938#define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U)
12939#define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */
12940#define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk
12941#define RCC_AHB2SMENR_GPIOISMEN_Pos (8U)
12942#define RCC_AHB2SMENR_GPIOISMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOISMEN_Pos) /*!< 0x00000100 */
12943#define RCC_AHB2SMENR_GPIOISMEN RCC_AHB2SMENR_GPIOISMEN_Msk
12944#define RCC_AHB2SMENR_SRAM2SMEN_Pos (9U)
12945#define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1U << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */
12946#define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
12947#define RCC_AHB2SMENR_SRAM3SMEN_Pos (10U)
12948#define RCC_AHB2SMENR_SRAM3SMEN_Msk (0x1U << RCC_AHB2SMENR_SRAM3SMEN_Pos) /*!< 0x00000400 */
12949#define RCC_AHB2SMENR_SRAM3SMEN RCC_AHB2SMENR_SRAM3SMEN_Msk
12950#define RCC_AHB2SMENR_OTGFSSMEN_Pos (12U)
12951#define RCC_AHB2SMENR_OTGFSSMEN_Msk (0x1U << RCC_AHB2SMENR_OTGFSSMEN_Pos) /*!< 0x00001000 */
12952#define RCC_AHB2SMENR_OTGFSSMEN RCC_AHB2SMENR_OTGFSSMEN_Msk
12953#define RCC_AHB2SMENR_ADCSMEN_Pos (13U)
12954#define RCC_AHB2SMENR_ADCSMEN_Msk (0x1U << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */
12955#define RCC_AHB2SMENR_ADCSMEN RCC_AHB2SMENR_ADCSMEN_Msk
12956#define RCC_AHB2SMENR_DCMISMEN_Pos (14U)
12957#define RCC_AHB2SMENR_DCMISMEN_Msk (0x1U << RCC_AHB2SMENR_DCMISMEN_Pos) /*!< 0x00004000 */
12958#define RCC_AHB2SMENR_DCMISMEN RCC_AHB2SMENR_DCMISMEN_Msk
12959#define RCC_AHB2SMENR_AESSMEN_Pos (16U)
12960#define RCC_AHB2SMENR_AESSMEN_Msk (0x1U << RCC_AHB2SMENR_AESSMEN_Pos) /*!< 0x00010000 */
12961#define RCC_AHB2SMENR_AESSMEN RCC_AHB2SMENR_AESSMEN_Msk
12962#define RCC_AHB2SMENR_HASHSMEN_Pos (17U)
12963#define RCC_AHB2SMENR_HASHSMEN_Msk (0x1U << RCC_AHB2SMENR_HASHSMEN_Pos) /*!< 0x00020000 */
12964#define RCC_AHB2SMENR_HASHSMEN RCC_AHB2SMENR_HASHSMEN_Msk
12965#define RCC_AHB2SMENR_RNGSMEN_Pos (18U)
12966#define RCC_AHB2SMENR_RNGSMEN_Msk (0x1U << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */
12967#define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
12968#define RCC_AHB2SMENR_OSPIMSMEN_Pos (20U)
12969#define RCC_AHB2SMENR_OSPIMSMEN_Msk (0x1U << RCC_AHB2SMENR_OSPIMSMEN_Pos) /*!< 0x00100000 */
12970#define RCC_AHB2SMENR_OSPIMSMEN RCC_AHB2SMENR_OSPIMSMEN_Msk
12971#define RCC_AHB2SMENR_SDMMC1SMEN_Pos (22U)
12972#define RCC_AHB2SMENR_SDMMC1SMEN_Msk (0x1U << RCC_AHB2SMENR_SDMMC1SMEN_Pos) /*!< 0x00400000 */
12973#define RCC_AHB2SMENR_SDMMC1SMEN RCC_AHB2SMENR_SDMMC1SMEN_Msk
12974
12975/******************** Bit definition for RCC_AHB3SMENR register *************/
12976#define RCC_AHB3SMENR_FMCSMEN_Pos (0U)
12977#define RCC_AHB3SMENR_FMCSMEN_Msk (0x1U << RCC_AHB3SMENR_FMCSMEN_Pos) /*!< 0x00000001 */
12978#define RCC_AHB3SMENR_FMCSMEN RCC_AHB3SMENR_FMCSMEN_Msk
12979#define RCC_AHB3SMENR_OSPI1SMEN_Pos (8U)
12980#define RCC_AHB3SMENR_OSPI1SMEN_Msk (0x1U << RCC_AHB3SMENR_OSPI1SMEN_Pos) /*!< 0x00000100 */
12981#define RCC_AHB3SMENR_OSPI1SMEN RCC_AHB3SMENR_OSPI1SMEN_Msk
12982#define RCC_AHB3SMENR_OSPI2SMEN_Pos (9U)
12983#define RCC_AHB3SMENR_OSPI2SMEN_Msk (0x1U << RCC_AHB3SMENR_OSPI2SMEN_Pos) /*!< 0x00000200 */
12984#define RCC_AHB3SMENR_OSPI2SMEN RCC_AHB3SMENR_OSPI2SMEN_Msk
12985
12986/******************** Bit definition for RCC_APB1SMENR1 register *************/
12987#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
12988#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
12989#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
12990#define RCC_APB1SMENR1_TIM3SMEN_Pos (1U)
12991#define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */
12992#define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk
12993#define RCC_APB1SMENR1_TIM4SMEN_Pos (2U)
12994#define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM4SMEN_Pos) /*!< 0x00000004 */
12995#define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk
12996#define RCC_APB1SMENR1_TIM5SMEN_Pos (3U)
12997#define RCC_APB1SMENR1_TIM5SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM5SMEN_Pos) /*!< 0x00000008 */
12998#define RCC_APB1SMENR1_TIM5SMEN RCC_APB1SMENR1_TIM5SMEN_Msk
12999#define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
13000#define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
13001#define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
13002#define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
13003#define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */
13004#define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
13005#define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U)
13006#define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1U << RCC_APB1SMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
13007#define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk
13008#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
13009#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1U << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
13010#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
13011#define RCC_APB1SMENR1_SPI2SMEN_Pos (14U)
13012#define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1U << RCC_APB1SMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
13013#define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk
13014#define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
13015#define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1U << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */
13016#define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
13017#define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
13018#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1U << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
13019#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
13020#define RCC_APB1SMENR1_USART3SMEN_Pos (18U)
13021#define RCC_APB1SMENR1_USART3SMEN_Msk (0x1U << RCC_APB1SMENR1_USART3SMEN_Pos) /*!< 0x00040000 */
13022#define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk
13023#define RCC_APB1SMENR1_UART4SMEN_Pos (19U)
13024#define RCC_APB1SMENR1_UART4SMEN_Msk (0x1U << RCC_APB1SMENR1_UART4SMEN_Pos) /*!< 0x00080000 */
13025#define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk
13026#define RCC_APB1SMENR1_UART5SMEN_Pos (20U)
13027#define RCC_APB1SMENR1_UART5SMEN_Msk (0x1U << RCC_APB1SMENR1_UART5SMEN_Pos) /*!< 0x00100000 */
13028#define RCC_APB1SMENR1_UART5SMEN RCC_APB1SMENR1_UART5SMEN_Msk
13029#define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
13030#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
13031#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
13032#define RCC_APB1SMENR1_I2C2SMEN_Pos (22U)
13033#define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */
13034#define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk
13035#define RCC_APB1SMENR1_I2C3SMEN_Pos (23U)
13036#define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */
13037#define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
13038#define RCC_APB1SMENR1_CRSSMEN_Pos (24U)
13039#define RCC_APB1SMENR1_CRSSMEN_Msk (0x1U << RCC_APB1SMENR1_CRSSMEN_Pos) /*!< 0x01000000 */
13040#define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk
13041#define RCC_APB1SMENR1_CAN1SMEN_Pos (25U)
13042#define RCC_APB1SMENR1_CAN1SMEN_Msk (0x1U << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */
13043#define RCC_APB1SMENR1_CAN1SMEN RCC_APB1SMENR1_CAN1SMEN_Msk
13044#define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
13045#define RCC_APB1SMENR1_PWRSMEN_Msk (0x1U << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
13046#define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
13047#define RCC_APB1SMENR1_DAC1SMEN_Pos (29U)
13048#define RCC_APB1SMENR1_DAC1SMEN_Msk (0x1U << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */
13049#define RCC_APB1SMENR1_DAC1SMEN RCC_APB1SMENR1_DAC1SMEN_Msk
13050#define RCC_APB1SMENR1_OPAMPSMEN_Pos (30U)
13051#define RCC_APB1SMENR1_OPAMPSMEN_Msk (0x1U << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */
13052#define RCC_APB1SMENR1_OPAMPSMEN RCC_APB1SMENR1_OPAMPSMEN_Msk
13053#define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
13054#define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1U << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
13055#define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
13056
13057/******************** Bit definition for RCC_APB1SMENR2 register *************/
13058#define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
13059#define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1U << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */
13060#define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
13061#define RCC_APB1SMENR2_I2C4SMEN_Pos (1U)
13062#define RCC_APB1SMENR2_I2C4SMEN_Msk (0x1U << RCC_APB1SMENR2_I2C4SMEN_Pos) /*!< 0x00000002 */
13063#define RCC_APB1SMENR2_I2C4SMEN RCC_APB1SMENR2_I2C4SMEN_Msk
13064#define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U)
13065#define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1U << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
13066#define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk
13067
13068/******************** Bit definition for RCC_APB2SMENR register *************/
13069#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
13070#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
13071#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
13072#define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
13073#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1U << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
13074#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
13075#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
13076#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
13077#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
13078#define RCC_APB2SMENR_TIM8SMEN_Pos (13U)
13079#define RCC_APB2SMENR_TIM8SMEN_Msk (0x1U << RCC_APB2SMENR_TIM8SMEN_Pos) /*!< 0x00002000 */
13080#define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk
13081#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
13082#define RCC_APB2SMENR_USART1SMEN_Msk (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
13083#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
13084#define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
13085#define RCC_APB2SMENR_TIM15SMEN_Msk (0x1U << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */
13086#define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
13087#define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
13088#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1U << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
13089#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
13090#define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
13091#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1U << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */
13092#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk
13093#define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
13094#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1U << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
13095#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
13096#define RCC_APB2SMENR_SAI2SMEN_Pos (22U)
13097#define RCC_APB2SMENR_SAI2SMEN_Msk (0x1U << RCC_APB2SMENR_SAI2SMEN_Pos) /*!< 0x00400000 */
13098#define RCC_APB2SMENR_SAI2SMEN RCC_APB2SMENR_SAI2SMEN_Msk
13099#define RCC_APB2SMENR_DFSDM1SMEN_Pos (24U)
13100#define RCC_APB2SMENR_DFSDM1SMEN_Msk (0x1U << RCC_APB2SMENR_DFSDM1SMEN_Pos) /*!< 0x01000000 */
13101#define RCC_APB2SMENR_DFSDM1SMEN RCC_APB2SMENR_DFSDM1SMEN_Msk
13102
13103/******************** Bit definition for RCC_CCIPR register ******************/
13104#define RCC_CCIPR_USART1SEL_Pos (0U)
13105#define RCC_CCIPR_USART1SEL_Msk (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
13106#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
13107#define RCC_CCIPR_USART1SEL_0 (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
13108#define RCC_CCIPR_USART1SEL_1 (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
13109
13110#define RCC_CCIPR_USART2SEL_Pos (2U)
13111#define RCC_CCIPR_USART2SEL_Msk (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
13112#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
13113#define RCC_CCIPR_USART2SEL_0 (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
13114#define RCC_CCIPR_USART2SEL_1 (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
13115
13116#define RCC_CCIPR_USART3SEL_Pos (4U)
13117#define RCC_CCIPR_USART3SEL_Msk (0x3U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000030 */
13118#define RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk
13119#define RCC_CCIPR_USART3SEL_0 (0x1U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000010 */
13120#define RCC_CCIPR_USART3SEL_1 (0x2U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000020 */
13121
13122#define RCC_CCIPR_UART4SEL_Pos (6U)
13123#define RCC_CCIPR_UART4SEL_Msk (0x3U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */
13124#define RCC_CCIPR_UART4SEL RCC_CCIPR_UART4SEL_Msk
13125#define RCC_CCIPR_UART4SEL_0 (0x1U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */
13126#define RCC_CCIPR_UART4SEL_1 (0x2U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */
13127
13128#define RCC_CCIPR_UART5SEL_Pos (8U)
13129#define RCC_CCIPR_UART5SEL_Msk (0x3U << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000300 */
13130#define RCC_CCIPR_UART5SEL RCC_CCIPR_UART5SEL_Msk
13131#define RCC_CCIPR_UART5SEL_0 (0x1U << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000100 */
13132#define RCC_CCIPR_UART5SEL_1 (0x2U << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000200 */
13133
13134#define RCC_CCIPR_LPUART1SEL_Pos (10U)
13135#define RCC_CCIPR_LPUART1SEL_Msk (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
13136#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
13137#define RCC_CCIPR_LPUART1SEL_0 (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
13138#define RCC_CCIPR_LPUART1SEL_1 (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
13139
13140#define RCC_CCIPR_I2C1SEL_Pos (12U)
13141#define RCC_CCIPR_I2C1SEL_Msk (0x3U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
13142#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
13143#define RCC_CCIPR_I2C1SEL_0 (0x1U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
13144#define RCC_CCIPR_I2C1SEL_1 (0x2U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
13145
13146#define RCC_CCIPR_I2C2SEL_Pos (14U)
13147#define RCC_CCIPR_I2C2SEL_Msk (0x3U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x0000C000 */
13148#define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk
13149#define RCC_CCIPR_I2C2SEL_0 (0x1U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00004000 */
13150#define RCC_CCIPR_I2C2SEL_1 (0x2U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00008000 */
13151
13152#define RCC_CCIPR_I2C3SEL_Pos (16U)
13153#define RCC_CCIPR_I2C3SEL_Msk (0x3U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
13154#define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
13155#define RCC_CCIPR_I2C3SEL_0 (0x1U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
13156#define RCC_CCIPR_I2C3SEL_1 (0x2U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
13157
13158#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
13159#define RCC_CCIPR_LPTIM1SEL_Msk (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
13160#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
13161#define RCC_CCIPR_LPTIM1SEL_0 (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
13162#define RCC_CCIPR_LPTIM1SEL_1 (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
13163
13164#define RCC_CCIPR_LPTIM2SEL_Pos (20U)
13165#define RCC_CCIPR_LPTIM2SEL_Msk (0x3U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
13166#define RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk
13167#define RCC_CCIPR_LPTIM2SEL_0 (0x1U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
13168#define RCC_CCIPR_LPTIM2SEL_1 (0x2U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
13169
13170#define RCC_CCIPR_CLK48SEL_Pos (26U)
13171#define RCC_CCIPR_CLK48SEL_Msk (0x3U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
13172#define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
13173#define RCC_CCIPR_CLK48SEL_0 (0x1U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
13174#define RCC_CCIPR_CLK48SEL_1 (0x2U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
13175
13176#define RCC_CCIPR_ADCSEL_Pos (28U)
13177#define RCC_CCIPR_ADCSEL_Msk (0x3U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x30000000 */
13178#define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk
13179#define RCC_CCIPR_ADCSEL_0 (0x1U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x10000000 */
13180#define RCC_CCIPR_ADCSEL_1 (0x2U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x20000000 */
13181
13182/******************** Bit definition for RCC_BDCR register ******************/
13183#define RCC_BDCR_LSEON_Pos (0U)
13184#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
13185#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
13186#define RCC_BDCR_LSERDY_Pos (1U)
13187#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
13188#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
13189#define RCC_BDCR_LSEBYP_Pos (2U)
13190#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
13191#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
13192
13193#define RCC_BDCR_LSEDRV_Pos (3U)
13194#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
13195#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
13196#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
13197#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
13198
13199#define RCC_BDCR_LSECSSON_Pos (5U)
13200#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
13201#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
13202#define RCC_BDCR_LSECSSD_Pos (6U)
13203#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
13204#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
13205
13206#define RCC_BDCR_RTCSEL_Pos (8U)
13207#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
13208#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
13209#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
13210#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
13211
13212#define RCC_BDCR_RTCEN_Pos (15U)
13213#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
13214#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
13215#define RCC_BDCR_BDRST_Pos (16U)
13216#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
13217#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
13218#define RCC_BDCR_LSCOEN_Pos (24U)
13219#define RCC_BDCR_LSCOEN_Msk (0x1U << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
13220#define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
13221#define RCC_BDCR_LSCOSEL_Pos (25U)
13222#define RCC_BDCR_LSCOSEL_Msk (0x1U << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
13223#define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
13224
13225/******************** Bit definition for RCC_CSR register *******************/
13226#define RCC_CSR_LSION_Pos (0U)
13227#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
13228#define RCC_CSR_LSION RCC_CSR_LSION_Msk
13229#define RCC_CSR_LSIRDY_Pos (1U)
13230#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
13231#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
13232
13233#define RCC_CSR_MSISRANGE_Pos (8U)
13234#define RCC_CSR_MSISRANGE_Msk (0xFU << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000F00 */
13235#define RCC_CSR_MSISRANGE RCC_CSR_MSISRANGE_Msk
13236#define RCC_CSR_MSISRANGE_1 (0x4U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000400 */
13237#define RCC_CSR_MSISRANGE_2 (0x5U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000500 */
13238#define RCC_CSR_MSISRANGE_4 (0x6U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000600 */
13239#define RCC_CSR_MSISRANGE_8 (0x7U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000700 */
13240
13241#define RCC_CSR_RMVF_Pos (23U)
13242#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
13243#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
13244#define RCC_CSR_FWRSTF_Pos (24U)
13245#define RCC_CSR_FWRSTF_Msk (0x1U << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
13246#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk
13247#define RCC_CSR_OBLRSTF_Pos (25U)
13248#define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
13249#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
13250#define RCC_CSR_PINRSTF_Pos (26U)
13251#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
13252#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
13253#define RCC_CSR_BORRSTF_Pos (27U)
13254#define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */
13255#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
13256#define RCC_CSR_SFTRSTF_Pos (28U)
13257#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
13258#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
13259#define RCC_CSR_IWDGRSTF_Pos (29U)
13260#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
13261#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
13262#define RCC_CSR_WWDGRSTF_Pos (30U)
13263#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
13264#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
13265#define RCC_CSR_LPWRRSTF_Pos (31U)
13266#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
13267#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
13268
13269/******************** Bit definition for RCC_CRRCR register *****************/
13270#define RCC_CRRCR_HSI48ON_Pos (0U)
13271#define RCC_CRRCR_HSI48ON_Msk (0x1U << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
13272#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk
13273#define RCC_CRRCR_HSI48RDY_Pos (1U)
13274#define RCC_CRRCR_HSI48RDY_Msk (0x1U << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
13275#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk
13276
13277/*!< HSI48CAL configuration */
13278#define RCC_CRRCR_HSI48CAL_Pos (7U)
13279#define RCC_CRRCR_HSI48CAL_Msk (0x1FFU << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF80 */
13280#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[8:0] bits */
13281#define RCC_CRRCR_HSI48CAL_0 (0x001U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
13282#define RCC_CRRCR_HSI48CAL_1 (0x002U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
13283#define RCC_CRRCR_HSI48CAL_2 (0x004U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
13284#define RCC_CRRCR_HSI48CAL_3 (0x008U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000400 */
13285#define RCC_CRRCR_HSI48CAL_4 (0x010U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000800 */
13286#define RCC_CRRCR_HSI48CAL_5 (0x020U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00001000 */
13287#define RCC_CRRCR_HSI48CAL_6 (0x040U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00002000 */
13288#define RCC_CRRCR_HSI48CAL_7 (0x080U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00004000 */
13289#define RCC_CRRCR_HSI48CAL_8 (0x100U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00008000 */
13290
13291/******************** Bit definition for RCC_CCIPR2 register ******************/
13292#define RCC_CCIPR2_I2C4SEL_Pos (0U)
13293#define RCC_CCIPR2_I2C4SEL_Msk (0x3U << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000003 */
13294#define RCC_CCIPR2_I2C4SEL RCC_CCIPR2_I2C4SEL_Msk
13295#define RCC_CCIPR2_I2C4SEL_0 (0x1U << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000001 */
13296#define RCC_CCIPR2_I2C4SEL_1 (0x2U << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000002 */
13297
13298#define RCC_CCIPR2_DFSDM1SEL_Pos (2U)
13299#define RCC_CCIPR2_DFSDM1SEL_Msk (0x1U << RCC_CCIPR2_DFSDM1SEL_Pos) /*!< 0x00000004 */
13300#define RCC_CCIPR2_DFSDM1SEL RCC_CCIPR2_DFSDM1SEL_Msk
13301
13302#define RCC_CCIPR2_ADFSDM1SEL_Pos (3U)
13303#define RCC_CCIPR2_ADFSDM1SEL_Msk (0x3U << RCC_CCIPR2_ADFSDM1SEL_Pos) /*!< 0x00000018 */
13304#define RCC_CCIPR2_ADFSDM1SEL RCC_CCIPR2_ADFSDM1SEL_Msk
13305#define RCC_CCIPR2_ADFSDM1SEL_0 (0x1U << RCC_CCIPR2_ADFSDM1SEL_Pos) /*!< 0x00000008 */
13306#define RCC_CCIPR2_ADFSDM1SEL_1 (0x2U << RCC_CCIPR2_ADFSDM1SEL_Pos) /*!< 0x00000010 */
13307
13308#define RCC_CCIPR2_SAI1SEL_Pos (5U)
13309#define RCC_CCIPR2_SAI1SEL_Msk (0x7U << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E0 */
13310#define RCC_CCIPR2_SAI1SEL RCC_CCIPR2_SAI1SEL_Msk
13311#define RCC_CCIPR2_SAI1SEL_0 (0x1U << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000020 */
13312#define RCC_CCIPR2_SAI1SEL_1 (0x2U << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000040 */
13313#define RCC_CCIPR2_SAI1SEL_2 (0x4U << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000080 */
13314
13315#define RCC_CCIPR2_SAI2SEL_Pos (8U)
13316#define RCC_CCIPR2_SAI2SEL_Msk (0x7U << RCC_CCIPR2_SAI2SEL_Pos) /*!< 0x00000700 */
13317#define RCC_CCIPR2_SAI2SEL RCC_CCIPR2_SAI2SEL_Msk
13318#define RCC_CCIPR2_SAI2SEL_0 (0x1U << RCC_CCIPR2_SAI2SEL_Pos) /*!< 0x00000100 */
13319#define RCC_CCIPR2_SAI2SEL_1 (0x2U << RCC_CCIPR2_SAI2SEL_Pos) /*!< 0x00000200 */
13320#define RCC_CCIPR2_SAI2SEL_2 (0x4U << RCC_CCIPR2_SAI2SEL_Pos) /*!< 0x00000400 */
13321
13322#define RCC_CCIPR2_SDMMCSEL_Pos (14U)
13323#define RCC_CCIPR2_SDMMCSEL_Msk (0x1U << RCC_CCIPR2_SDMMCSEL_Pos) /*!< 0x00004000 */
13324#define RCC_CCIPR2_SDMMCSEL RCC_CCIPR2_SDMMCSEL_Msk
13325
13326#define RCC_CCIPR2_PLLSAI2DIVR_Pos (16U)
13327#define RCC_CCIPR2_PLLSAI2DIVR_Msk (0x3U << RCC_CCIPR2_PLLSAI2DIVR_Pos) /*!< 0x00030000 */
13328#define RCC_CCIPR2_PLLSAI2DIVR RCC_CCIPR2_PLLSAI2DIVR_Msk
13329#define RCC_CCIPR2_PLLSAI2DIVR_0 (0x1U << RCC_CCIPR2_PLLSAI2DIVR_Pos) /*!< 0x00010000 */
13330#define RCC_CCIPR2_PLLSAI2DIVR_1 (0x2U << RCC_CCIPR2_PLLSAI2DIVR_Pos) /*!< 0x00020000 */
13331
13332#define RCC_CCIPR2_OSPISEL_Pos (20U)
13333#define RCC_CCIPR2_OSPISEL_Msk (0x3U << RCC_CCIPR2_OSPISEL_Pos) /*!< 0x00300000 */
13334#define RCC_CCIPR2_OSPISEL RCC_CCIPR2_OSPISEL_Msk
13335#define RCC_CCIPR2_OSPISEL_0 (0x1U << RCC_CCIPR2_OSPISEL_Pos) /*!< 0x00100000 */
13336#define RCC_CCIPR2_OSPISEL_1 (0x2U << RCC_CCIPR2_OSPISEL_Pos) /*!< 0x00200000 */
13337
13338/******************************************************************************/
13339/* */
13340/* RNG */
13341/* */
13342/******************************************************************************/
13343/******************** Bits definition for RNG_CR register *******************/
13344#define RNG_CR_RNGEN_Pos (2U)
13345#define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
13346#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
13347#define RNG_CR_IE_Pos (3U)
13348#define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
13349#define RNG_CR_IE RNG_CR_IE_Msk
13350#define RNG_CR_CED_Pos (5U)
13351#define RNG_CR_CED_Msk (0x1U << RNG_CR_CED_Pos) /*!< 0x00000020 */
13352#define RNG_CR_CED RNG_CR_CED_Msk
13353
13354/******************** Bits definition for RNG_SR register *******************/
13355#define RNG_SR_DRDY_Pos (0U)
13356#define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
13357#define RNG_SR_DRDY RNG_SR_DRDY_Msk
13358#define RNG_SR_CECS_Pos (1U)
13359#define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
13360#define RNG_SR_CECS RNG_SR_CECS_Msk
13361#define RNG_SR_SECS_Pos (2U)
13362#define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
13363#define RNG_SR_SECS RNG_SR_SECS_Msk
13364#define RNG_SR_CEIS_Pos (5U)
13365#define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
13366#define RNG_SR_CEIS RNG_SR_CEIS_Msk
13367#define RNG_SR_SEIS_Pos (6U)
13368#define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
13369#define RNG_SR_SEIS RNG_SR_SEIS_Msk
13370
13371/******************************************************************************/
13372/* */
13373/* Real-Time Clock (RTC) */
13374/* */
13375/******************************************************************************/
13376/*
13377* @brief Specific device feature definitions
13378*/
13379#define RTC_TAMPER1_SUPPORT
13380#define RTC_TAMPER2_SUPPORT
13381#define RTC_TAMPER3_SUPPORT
13382#define RTC_WAKEUP_SUPPORT
13383#define RTC_BACKUP_SUPPORT
13384
13385/******************** Bits definition for RTC_TR register *******************/
13386#define RTC_TR_PM_Pos (22U)
13387#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
13388#define RTC_TR_PM RTC_TR_PM_Msk
13389#define RTC_TR_HT_Pos (20U)
13390#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
13391#define RTC_TR_HT RTC_TR_HT_Msk
13392#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
13393#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
13394#define RTC_TR_HU_Pos (16U)
13395#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
13396#define RTC_TR_HU RTC_TR_HU_Msk
13397#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
13398#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
13399#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
13400#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
13401#define RTC_TR_MNT_Pos (12U)
13402#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
13403#define RTC_TR_MNT RTC_TR_MNT_Msk
13404#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
13405#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
13406#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
13407#define RTC_TR_MNU_Pos (8U)
13408#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
13409#define RTC_TR_MNU RTC_TR_MNU_Msk
13410#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
13411#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
13412#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
13413#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
13414#define RTC_TR_ST_Pos (4U)
13415#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
13416#define RTC_TR_ST RTC_TR_ST_Msk
13417#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
13418#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
13419#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
13420#define RTC_TR_SU_Pos (0U)
13421#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
13422#define RTC_TR_SU RTC_TR_SU_Msk
13423#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
13424#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
13425#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
13426#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
13427
13428/******************** Bits definition for RTC_DR register *******************/
13429#define RTC_DR_YT_Pos (20U)
13430#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
13431#define RTC_DR_YT RTC_DR_YT_Msk
13432#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
13433#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
13434#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
13435#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
13436#define RTC_DR_YU_Pos (16U)
13437#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
13438#define RTC_DR_YU RTC_DR_YU_Msk
13439#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
13440#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
13441#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
13442#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
13443#define RTC_DR_WDU_Pos (13U)
13444#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
13445#define RTC_DR_WDU RTC_DR_WDU_Msk
13446#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
13447#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
13448#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
13449#define RTC_DR_MT_Pos (12U)
13450#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
13451#define RTC_DR_MT RTC_DR_MT_Msk
13452#define RTC_DR_MU_Pos (8U)
13453#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
13454#define RTC_DR_MU RTC_DR_MU_Msk
13455#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
13456#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
13457#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
13458#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
13459#define RTC_DR_DT_Pos (4U)
13460#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
13461#define RTC_DR_DT RTC_DR_DT_Msk
13462#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
13463#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
13464#define RTC_DR_DU_Pos (0U)
13465#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
13466#define RTC_DR_DU RTC_DR_DU_Msk
13467#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
13468#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
13469#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
13470#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
13471
13472/******************** Bits definition for RTC_CR register *******************/
13473#define RTC_CR_ITSE_Pos (24U)
13474#define RTC_CR_ITSE_Msk (0x1U << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
13475#define RTC_CR_ITSE RTC_CR_ITSE_Msk
13476#define RTC_CR_COE_Pos (23U)
13477#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
13478#define RTC_CR_COE RTC_CR_COE_Msk
13479#define RTC_CR_OSEL_Pos (21U)
13480#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
13481#define RTC_CR_OSEL RTC_CR_OSEL_Msk
13482#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
13483#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
13484#define RTC_CR_POL_Pos (20U)
13485#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
13486#define RTC_CR_POL RTC_CR_POL_Msk
13487#define RTC_CR_COSEL_Pos (19U)
13488#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
13489#define RTC_CR_COSEL RTC_CR_COSEL_Msk
13490#define RTC_CR_BKP_Pos (18U)
13491#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
13492#define RTC_CR_BKP RTC_CR_BKP_Msk
13493#define RTC_CR_SUB1H_Pos (17U)
13494#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
13495#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
13496#define RTC_CR_ADD1H_Pos (16U)
13497#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
13498#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
13499#define RTC_CR_TSIE_Pos (15U)
13500#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
13501#define RTC_CR_TSIE RTC_CR_TSIE_Msk
13502#define RTC_CR_WUTIE_Pos (14U)
13503#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
13504#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
13505#define RTC_CR_ALRBIE_Pos (13U)
13506#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
13507#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
13508#define RTC_CR_ALRAIE_Pos (12U)
13509#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
13510#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
13511#define RTC_CR_TSE_Pos (11U)
13512#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
13513#define RTC_CR_TSE RTC_CR_TSE_Msk
13514#define RTC_CR_WUTE_Pos (10U)
13515#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
13516#define RTC_CR_WUTE RTC_CR_WUTE_Msk
13517#define RTC_CR_ALRBE_Pos (9U)
13518#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
13519#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
13520#define RTC_CR_ALRAE_Pos (8U)
13521#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
13522#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
13523#define RTC_CR_FMT_Pos (6U)
13524#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
13525#define RTC_CR_FMT RTC_CR_FMT_Msk
13526#define RTC_CR_BYPSHAD_Pos (5U)
13527#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
13528#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
13529#define RTC_CR_REFCKON_Pos (4U)
13530#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
13531#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
13532#define RTC_CR_TSEDGE_Pos (3U)
13533#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
13534#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
13535#define RTC_CR_WUCKSEL_Pos (0U)
13536#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
13537#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
13538#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
13539#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
13540#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
13541
13542/* Legacy defines */
13543#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
13544#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
13545#define RTC_CR_BCK RTC_CR_BKP
13546
13547/******************** Bits definition for RTC_ISR register ******************/
13548#define RTC_ISR_ITSF_Pos (17U)
13549#define RTC_ISR_ITSF_Msk (0x1U << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */
13550#define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
13551#define RTC_ISR_RECALPF_Pos (16U)
13552#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
13553#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
13554#define RTC_ISR_TAMP3F_Pos (15U)
13555#define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
13556#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
13557#define RTC_ISR_TAMP2F_Pos (14U)
13558#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
13559#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
13560#define RTC_ISR_TAMP1F_Pos (13U)
13561#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
13562#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
13563#define RTC_ISR_TSOVF_Pos (12U)
13564#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
13565#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
13566#define RTC_ISR_TSF_Pos (11U)
13567#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
13568#define RTC_ISR_TSF RTC_ISR_TSF_Msk
13569#define RTC_ISR_WUTF_Pos (10U)
13570#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
13571#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
13572#define RTC_ISR_ALRBF_Pos (9U)
13573#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
13574#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
13575#define RTC_ISR_ALRAF_Pos (8U)
13576#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
13577#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
13578#define RTC_ISR_INIT_Pos (7U)
13579#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
13580#define RTC_ISR_INIT RTC_ISR_INIT_Msk
13581#define RTC_ISR_INITF_Pos (6U)
13582#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
13583#define RTC_ISR_INITF RTC_ISR_INITF_Msk
13584#define RTC_ISR_RSF_Pos (5U)
13585#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
13586#define RTC_ISR_RSF RTC_ISR_RSF_Msk
13587#define RTC_ISR_INITS_Pos (4U)
13588#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
13589#define RTC_ISR_INITS RTC_ISR_INITS_Msk
13590#define RTC_ISR_SHPF_Pos (3U)
13591#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
13592#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
13593#define RTC_ISR_WUTWF_Pos (2U)
13594#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
13595#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
13596#define RTC_ISR_ALRBWF_Pos (1U)
13597#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
13598#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
13599#define RTC_ISR_ALRAWF_Pos (0U)
13600#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
13601#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
13602
13603/******************** Bits definition for RTC_PRER register *****************/
13604#define RTC_PRER_PREDIV_A_Pos (16U)
13605#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
13606#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
13607#define RTC_PRER_PREDIV_S_Pos (0U)
13608#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
13609#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
13610
13611/******************** Bits definition for RTC_WUTR register *****************/
13612#define RTC_WUTR_WUT_Pos (0U)
13613#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
13614#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
13615
13616/******************** Bits definition for RTC_ALRMAR register ***************/
13617#define RTC_ALRMAR_MSK4_Pos (31U)
13618#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
13619#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
13620#define RTC_ALRMAR_WDSEL_Pos (30U)
13621#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
13622#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
13623#define RTC_ALRMAR_DT_Pos (28U)
13624#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
13625#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
13626#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
13627#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
13628#define RTC_ALRMAR_DU_Pos (24U)
13629#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
13630#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
13631#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
13632#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
13633#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
13634#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
13635#define RTC_ALRMAR_MSK3_Pos (23U)
13636#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
13637#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
13638#define RTC_ALRMAR_PM_Pos (22U)
13639#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
13640#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
13641#define RTC_ALRMAR_HT_Pos (20U)
13642#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
13643#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
13644#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
13645#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
13646#define RTC_ALRMAR_HU_Pos (16U)
13647#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
13648#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
13649#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
13650#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
13651#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
13652#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
13653#define RTC_ALRMAR_MSK2_Pos (15U)
13654#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
13655#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
13656#define RTC_ALRMAR_MNT_Pos (12U)
13657#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
13658#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
13659#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
13660#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
13661#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
13662#define RTC_ALRMAR_MNU_Pos (8U)
13663#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
13664#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
13665#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
13666#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
13667#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
13668#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
13669#define RTC_ALRMAR_MSK1_Pos (7U)
13670#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
13671#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
13672#define RTC_ALRMAR_ST_Pos (4U)
13673#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
13674#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
13675#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
13676#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
13677#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
13678#define RTC_ALRMAR_SU_Pos (0U)
13679#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
13680#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
13681#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
13682#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
13683#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
13684#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
13685
13686/******************** Bits definition for RTC_ALRMBR register ***************/
13687#define RTC_ALRMBR_MSK4_Pos (31U)
13688#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
13689#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
13690#define RTC_ALRMBR_WDSEL_Pos (30U)
13691#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
13692#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
13693#define RTC_ALRMBR_DT_Pos (28U)
13694#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
13695#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
13696#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
13697#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
13698#define RTC_ALRMBR_DU_Pos (24U)
13699#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
13700#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
13701#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
13702#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
13703#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
13704#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
13705#define RTC_ALRMBR_MSK3_Pos (23U)
13706#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
13707#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
13708#define RTC_ALRMBR_PM_Pos (22U)
13709#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
13710#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
13711#define RTC_ALRMBR_HT_Pos (20U)
13712#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
13713#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
13714#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
13715#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
13716#define RTC_ALRMBR_HU_Pos (16U)
13717#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
13718#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
13719#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
13720#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
13721#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
13722#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
13723#define RTC_ALRMBR_MSK2_Pos (15U)
13724#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
13725#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
13726#define RTC_ALRMBR_MNT_Pos (12U)
13727#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
13728#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
13729#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
13730#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
13731#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
13732#define RTC_ALRMBR_MNU_Pos (8U)
13733#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
13734#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
13735#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
13736#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
13737#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
13738#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
13739#define RTC_ALRMBR_MSK1_Pos (7U)
13740#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
13741#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
13742#define RTC_ALRMBR_ST_Pos (4U)
13743#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
13744#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
13745#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
13746#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
13747#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
13748#define RTC_ALRMBR_SU_Pos (0U)
13749#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
13750#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
13751#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
13752#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
13753#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
13754#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
13755
13756/******************** Bits definition for RTC_WPR register ******************/
13757#define RTC_WPR_KEY_Pos (0U)
13758#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
13759#define RTC_WPR_KEY RTC_WPR_KEY_Msk
13760
13761/******************** Bits definition for RTC_SSR register ******************/
13762#define RTC_SSR_SS_Pos (0U)
13763#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
13764#define RTC_SSR_SS RTC_SSR_SS_Msk
13765
13766/******************** Bits definition for RTC_SHIFTR register ***************/
13767#define RTC_SHIFTR_SUBFS_Pos (0U)
13768#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
13769#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
13770#define RTC_SHIFTR_ADD1S_Pos (31U)
13771#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
13772#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
13773
13774/******************** Bits definition for RTC_TSTR register *****************/
13775#define RTC_TSTR_PM_Pos (22U)
13776#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
13777#define RTC_TSTR_PM RTC_TSTR_PM_Msk
13778#define RTC_TSTR_HT_Pos (20U)
13779#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
13780#define RTC_TSTR_HT RTC_TSTR_HT_Msk
13781#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
13782#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
13783#define RTC_TSTR_HU_Pos (16U)
13784#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
13785#define RTC_TSTR_HU RTC_TSTR_HU_Msk
13786#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
13787#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
13788#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
13789#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
13790#define RTC_TSTR_MNT_Pos (12U)
13791#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
13792#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
13793#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
13794#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
13795#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
13796#define RTC_TSTR_MNU_Pos (8U)
13797#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
13798#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
13799#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
13800#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
13801#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
13802#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
13803#define RTC_TSTR_ST_Pos (4U)
13804#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
13805#define RTC_TSTR_ST RTC_TSTR_ST_Msk
13806#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
13807#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
13808#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
13809#define RTC_TSTR_SU_Pos (0U)
13810#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
13811#define RTC_TSTR_SU RTC_TSTR_SU_Msk
13812#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
13813#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
13814#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
13815#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
13816
13817/******************** Bits definition for RTC_TSDR register *****************/
13818#define RTC_TSDR_WDU_Pos (13U)
13819#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
13820#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
13821#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
13822#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
13823#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
13824#define RTC_TSDR_MT_Pos (12U)
13825#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
13826#define RTC_TSDR_MT RTC_TSDR_MT_Msk
13827#define RTC_TSDR_MU_Pos (8U)
13828#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
13829#define RTC_TSDR_MU RTC_TSDR_MU_Msk
13830#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
13831#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
13832#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
13833#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
13834#define RTC_TSDR_DT_Pos (4U)
13835#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
13836#define RTC_TSDR_DT RTC_TSDR_DT_Msk
13837#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
13838#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
13839#define RTC_TSDR_DU_Pos (0U)
13840#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
13841#define RTC_TSDR_DU RTC_TSDR_DU_Msk
13842#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
13843#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
13844#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
13845#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
13846
13847/******************** Bits definition for RTC_TSSSR register ****************/
13848#define RTC_TSSSR_SS_Pos (0U)
13849#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
13850#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
13851
13852/******************** Bits definition for RTC_CAL register *****************/
13853#define RTC_CALR_CALP_Pos (15U)
13854#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
13855#define RTC_CALR_CALP RTC_CALR_CALP_Msk
13856#define RTC_CALR_CALW8_Pos (14U)
13857#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
13858#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
13859#define RTC_CALR_CALW16_Pos (13U)
13860#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
13861#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
13862#define RTC_CALR_CALM_Pos (0U)
13863#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
13864#define RTC_CALR_CALM RTC_CALR_CALM_Msk
13865#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
13866#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
13867#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
13868#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
13869#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
13870#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
13871#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
13872#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
13873#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
13874
13875/******************** Bits definition for RTC_TAMPCR register ***************/
13876#define RTC_TAMPCR_TAMP3MF_Pos (24U)
13877#define RTC_TAMPCR_TAMP3MF_Msk (0x1U << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
13878#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
13879#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
13880#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
13881#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
13882#define RTC_TAMPCR_TAMP3IE_Pos (22U)
13883#define RTC_TAMPCR_TAMP3IE_Msk (0x1U << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
13884#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
13885#define RTC_TAMPCR_TAMP2MF_Pos (21U)
13886#define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
13887#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
13888#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
13889#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
13890#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
13891#define RTC_TAMPCR_TAMP2IE_Pos (19U)
13892#define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
13893#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
13894#define RTC_TAMPCR_TAMP1MF_Pos (18U)
13895#define RTC_TAMPCR_TAMP1MF_Msk (0x1U << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
13896#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
13897#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
13898#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
13899#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
13900#define RTC_TAMPCR_TAMP1IE_Pos (16U)
13901#define RTC_TAMPCR_TAMP1IE_Msk (0x1U << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
13902#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
13903#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
13904#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
13905#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
13906#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
13907#define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
13908#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
13909#define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
13910#define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
13911#define RTC_TAMPCR_TAMPFLT_Pos (11U)
13912#define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
13913#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
13914#define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
13915#define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
13916#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
13917#define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
13918#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
13919#define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
13920#define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
13921#define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
13922#define RTC_TAMPCR_TAMPTS_Pos (7U)
13923#define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
13924#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
13925#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
13926#define RTC_TAMPCR_TAMP3TRG_Msk (0x1U << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
13927#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
13928#define RTC_TAMPCR_TAMP3E_Pos (5U)
13929#define RTC_TAMPCR_TAMP3E_Msk (0x1U << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
13930#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
13931#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
13932#define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
13933#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
13934#define RTC_TAMPCR_TAMP2E_Pos (3U)
13935#define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
13936#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
13937#define RTC_TAMPCR_TAMPIE_Pos (2U)
13938#define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
13939#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
13940#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
13941#define RTC_TAMPCR_TAMP1TRG_Msk (0x1U << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
13942#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
13943#define RTC_TAMPCR_TAMP1E_Pos (0U)
13944#define RTC_TAMPCR_TAMP1E_Msk (0x1U << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
13945#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
13946
13947/******************** Bits definition for RTC_ALRMASSR register *************/
13948#define RTC_ALRMASSR_MASKSS_Pos (24U)
13949#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
13950#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
13951#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
13952#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
13953#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
13954#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
13955#define RTC_ALRMASSR_SS_Pos (0U)
13956#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
13957#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
13958
13959/******************** Bits definition for RTC_ALRMBSSR register *************/
13960#define RTC_ALRMBSSR_MASKSS_Pos (24U)
13961#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
13962#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
13963#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
13964#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
13965#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
13966#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
13967#define RTC_ALRMBSSR_SS_Pos (0U)
13968#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
13969#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
13970
13971/******************** Bits definition for RTC_0R register *******************/
13972#define RTC_OR_OUT_RMP_Pos (1U)
13973#define RTC_OR_OUT_RMP_Msk (0x1U << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
13974#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
13975#define RTC_OR_ALARMOUTTYPE_Pos (0U)
13976#define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
13977#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
13978
13979
13980/******************** Bits definition for RTC_BKP0R register ****************/
13981#define RTC_BKP0R_Pos (0U)
13982#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
13983#define RTC_BKP0R RTC_BKP0R_Msk
13984
13985/******************** Bits definition for RTC_BKP1R register ****************/
13986#define RTC_BKP1R_Pos (0U)
13987#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
13988#define RTC_BKP1R RTC_BKP1R_Msk
13989
13990/******************** Bits definition for RTC_BKP2R register ****************/
13991#define RTC_BKP2R_Pos (0U)
13992#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
13993#define RTC_BKP2R RTC_BKP2R_Msk
13994
13995/******************** Bits definition for RTC_BKP3R register ****************/
13996#define RTC_BKP3R_Pos (0U)
13997#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
13998#define RTC_BKP3R RTC_BKP3R_Msk
13999
14000/******************** Bits definition for RTC_BKP4R register ****************/
14001#define RTC_BKP4R_Pos (0U)
14002#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
14003#define RTC_BKP4R RTC_BKP4R_Msk
14004
14005/******************** Bits definition for RTC_BKP5R register ****************/
14006#define RTC_BKP5R_Pos (0U)
14007#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
14008#define RTC_BKP5R RTC_BKP5R_Msk
14009
14010/******************** Bits definition for RTC_BKP6R register ****************/
14011#define RTC_BKP6R_Pos (0U)
14012#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
14013#define RTC_BKP6R RTC_BKP6R_Msk
14014
14015/******************** Bits definition for RTC_BKP7R register ****************/
14016#define RTC_BKP7R_Pos (0U)
14017#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
14018#define RTC_BKP7R RTC_BKP7R_Msk
14019
14020/******************** Bits definition for RTC_BKP8R register ****************/
14021#define RTC_BKP8R_Pos (0U)
14022#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
14023#define RTC_BKP8R RTC_BKP8R_Msk
14024
14025/******************** Bits definition for RTC_BKP9R register ****************/
14026#define RTC_BKP9R_Pos (0U)
14027#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
14028#define RTC_BKP9R RTC_BKP9R_Msk
14029
14030/******************** Bits definition for RTC_BKP10R register ***************/
14031#define RTC_BKP10R_Pos (0U)
14032#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
14033#define RTC_BKP10R RTC_BKP10R_Msk
14034
14035/******************** Bits definition for RTC_BKP11R register ***************/
14036#define RTC_BKP11R_Pos (0U)
14037#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
14038#define RTC_BKP11R RTC_BKP11R_Msk
14039
14040/******************** Bits definition for RTC_BKP12R register ***************/
14041#define RTC_BKP12R_Pos (0U)
14042#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
14043#define RTC_BKP12R RTC_BKP12R_Msk
14044
14045/******************** Bits definition for RTC_BKP13R register ***************/
14046#define RTC_BKP13R_Pos (0U)
14047#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
14048#define RTC_BKP13R RTC_BKP13R_Msk
14049
14050/******************** Bits definition for RTC_BKP14R register ***************/
14051#define RTC_BKP14R_Pos (0U)
14052#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
14053#define RTC_BKP14R RTC_BKP14R_Msk
14054
14055/******************** Bits definition for RTC_BKP15R register ***************/
14056#define RTC_BKP15R_Pos (0U)
14057#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
14058#define RTC_BKP15R RTC_BKP15R_Msk
14059
14060/******************** Bits definition for RTC_BKP16R register ***************/
14061#define RTC_BKP16R_Pos (0U)
14062#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
14063#define RTC_BKP16R RTC_BKP16R_Msk
14064
14065/******************** Bits definition for RTC_BKP17R register ***************/
14066#define RTC_BKP17R_Pos (0U)
14067#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
14068#define RTC_BKP17R RTC_BKP17R_Msk
14069
14070/******************** Bits definition for RTC_BKP18R register ***************/
14071#define RTC_BKP18R_Pos (0U)
14072#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
14073#define RTC_BKP18R RTC_BKP18R_Msk
14074
14075/******************** Bits definition for RTC_BKP19R register ***************/
14076#define RTC_BKP19R_Pos (0U)
14077#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
14078#define RTC_BKP19R RTC_BKP19R_Msk
14079
14080/******************** Bits definition for RTC_BKP20R register ***************/
14081#define RTC_BKP20R_Pos (0U)
14082#define RTC_BKP20R_Msk (0xFFFFFFFFU << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
14083#define RTC_BKP20R RTC_BKP20R_Msk
14084
14085/******************** Bits definition for RTC_BKP21R register ***************/
14086#define RTC_BKP21R_Pos (0U)
14087#define RTC_BKP21R_Msk (0xFFFFFFFFU << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
14088#define RTC_BKP21R RTC_BKP21R_Msk
14089
14090/******************** Bits definition for RTC_BKP22R register ***************/
14091#define RTC_BKP22R_Pos (0U)
14092#define RTC_BKP22R_Msk (0xFFFFFFFFU << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
14093#define RTC_BKP22R RTC_BKP22R_Msk
14094
14095/******************** Bits definition for RTC_BKP23R register ***************/
14096#define RTC_BKP23R_Pos (0U)
14097#define RTC_BKP23R_Msk (0xFFFFFFFFU << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
14098#define RTC_BKP23R RTC_BKP23R_Msk
14099
14100/******************** Bits definition for RTC_BKP24R register ***************/
14101#define RTC_BKP24R_Pos (0U)
14102#define RTC_BKP24R_Msk (0xFFFFFFFFU << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
14103#define RTC_BKP24R RTC_BKP24R_Msk
14104
14105/******************** Bits definition for RTC_BKP25R register ***************/
14106#define RTC_BKP25R_Pos (0U)
14107#define RTC_BKP25R_Msk (0xFFFFFFFFU << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
14108#define RTC_BKP25R RTC_BKP25R_Msk
14109
14110/******************** Bits definition for RTC_BKP26R register ***************/
14111#define RTC_BKP26R_Pos (0U)
14112#define RTC_BKP26R_Msk (0xFFFFFFFFU << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
14113#define RTC_BKP26R RTC_BKP26R_Msk
14114
14115/******************** Bits definition for RTC_BKP27R register ***************/
14116#define RTC_BKP27R_Pos (0U)
14117#define RTC_BKP27R_Msk (0xFFFFFFFFU << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
14118#define RTC_BKP27R RTC_BKP27R_Msk
14119
14120/******************** Bits definition for RTC_BKP28R register ***************/
14121#define RTC_BKP28R_Pos (0U)
14122#define RTC_BKP28R_Msk (0xFFFFFFFFU << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
14123#define RTC_BKP28R RTC_BKP28R_Msk
14124
14125/******************** Bits definition for RTC_BKP29R register ***************/
14126#define RTC_BKP29R_Pos (0U)
14127#define RTC_BKP29R_Msk (0xFFFFFFFFU << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
14128#define RTC_BKP29R RTC_BKP29R_Msk
14129
14130/******************** Bits definition for RTC_BKP30R register ***************/
14131#define RTC_BKP30R_Pos (0U)
14132#define RTC_BKP30R_Msk (0xFFFFFFFFU << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
14133#define RTC_BKP30R RTC_BKP30R_Msk
14134
14135/******************** Bits definition for RTC_BKP31R register ***************/
14136#define RTC_BKP31R_Pos (0U)
14137#define RTC_BKP31R_Msk (0xFFFFFFFFU << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
14138#define RTC_BKP31R RTC_BKP31R_Msk
14139
14140/******************** Number of backup registers ******************************/
14141#define RTC_BKP_NUMBER 32U
14142
14143/******************************************************************************/
14144/* */
14145/* Serial Audio Interface */
14146/* */
14147/******************************************************************************/
14148/******************** Bit definition for SAI_GCR register *******************/
14149#define SAI_GCR_SYNCIN_Pos (0U)
14150#define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
14151#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
14152#define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
14153#define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
14154
14155#define SAI_GCR_SYNCOUT_Pos (4U)
14156#define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
14157#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
14158#define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
14159#define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
14160
14161/******************* Bit definition for SAI_xCR1 register *******************/
14162#define SAI_xCR1_MODE_Pos (0U)
14163#define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
14164#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
14165#define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
14166#define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
14167
14168#define SAI_xCR1_PRTCFG_Pos (2U)
14169#define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
14170#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
14171#define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
14172#define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
14173
14174#define SAI_xCR1_DS_Pos (5U)
14175#define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
14176#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
14177#define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
14178#define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
14179#define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
14180
14181#define SAI_xCR1_LSBFIRST_Pos (8U)
14182#define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
14183#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
14184#define SAI_xCR1_CKSTR_Pos (9U)
14185#define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
14186#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
14187
14188#define SAI_xCR1_SYNCEN_Pos (10U)
14189#define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
14190#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
14191#define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
14192#define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
14193
14194#define SAI_xCR1_MONO_Pos (12U)
14195#define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
14196#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
14197#define SAI_xCR1_OUTDRIV_Pos (13U)
14198#define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
14199#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
14200#define SAI_xCR1_SAIEN_Pos (16U)
14201#define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
14202#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
14203#define SAI_xCR1_DMAEN_Pos (17U)
14204#define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
14205#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
14206#define SAI_xCR1_NOMCK_Pos (19U)
14207#define SAI_xCR1_NOMCK_Msk (0x1U << SAI_xCR1_NOMCK_Pos) /*!< 0x00080000 */
14208#define SAI_xCR1_NOMCK SAI_xCR1_NOMCK_Msk /*!<No Divider Configuration */
14209
14210#define SAI_xCR1_MCKDIV_Pos (20U)
14211#define SAI_xCR1_MCKDIV_Msk (0x3FU << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */
14212#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[5:0] (Master ClocK Divider) */
14213#define SAI_xCR1_MCKDIV_0 (0x00100000U) /*!<Bit 0 */
14214#define SAI_xCR1_MCKDIV_1 (0x00200000U) /*!<Bit 1 */
14215#define SAI_xCR1_MCKDIV_2 (0x00400000U) /*!<Bit 2 */
14216#define SAI_xCR1_MCKDIV_3 (0x00800000U) /*!<Bit 3 */
14217#define SAI_xCR1_MCKDIV_4 (0x01000000U) /*!<Bit 4 */
14218#define SAI_xCR1_MCKDIV_5 (0x02000000U) /*!<Bit 5 */
14219
14220#define SAI_xCR1_OSR_Pos (26U)
14221#define SAI_xCR1_OSR_Msk (0x1U << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */
14222#define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<Oversampling ratio for master clock */
14223
14224/******************* Bit definition for SAI_xCR2 register *******************/
14225#define SAI_xCR2_FTH_Pos (0U)
14226#define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
14227#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
14228#define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
14229#define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
14230#define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
14231
14232#define SAI_xCR2_FFLUSH_Pos (3U)
14233#define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
14234#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
14235#define SAI_xCR2_TRIS_Pos (4U)
14236#define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
14237#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
14238#define SAI_xCR2_MUTE_Pos (5U)
14239#define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
14240#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
14241#define SAI_xCR2_MUTEVAL_Pos (6U)
14242#define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
14243#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
14244
14245
14246#define SAI_xCR2_MUTECNT_Pos (7U)
14247#define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
14248#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
14249#define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
14250#define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
14251#define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
14252#define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
14253#define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
14254#define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
14255
14256#define SAI_xCR2_CPL_Pos (13U)
14257#define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
14258#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */
14259#define SAI_xCR2_COMP_Pos (14U)
14260#define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
14261#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
14262#define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
14263#define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
14264
14265
14266/****************** Bit definition for SAI_xFRCR register *******************/
14267#define SAI_xFRCR_FRL_Pos (0U)
14268#define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
14269#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
14270#define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
14271#define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
14272#define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
14273#define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
14274#define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
14275#define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
14276#define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
14277#define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
14278
14279#define SAI_xFRCR_FSALL_Pos (8U)
14280#define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
14281#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
14282#define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
14283#define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
14284#define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
14285#define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
14286#define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
14287#define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
14288#define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
14289
14290#define SAI_xFRCR_FSDEF_Pos (16U)
14291#define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
14292#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
14293#define SAI_xFRCR_FSPOL_Pos (17U)
14294#define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
14295#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
14296#define SAI_xFRCR_FSOFF_Pos (18U)
14297#define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
14298#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
14299
14300/****************** Bit definition for SAI_xSLOTR register *******************/
14301#define SAI_xSLOTR_FBOFF_Pos (0U)
14302#define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
14303#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
14304#define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
14305#define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
14306#define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
14307#define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
14308#define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
14309
14310#define SAI_xSLOTR_SLOTSZ_Pos (6U)
14311#define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
14312#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
14313#define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
14314#define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
14315
14316#define SAI_xSLOTR_NBSLOT_Pos (8U)
14317#define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
14318#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
14319#define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
14320#define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
14321#define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
14322#define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
14323
14324#define SAI_xSLOTR_SLOTEN_Pos (16U)
14325#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
14326#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
14327
14328/******************* Bit definition for SAI_xIMR register *******************/
14329#define SAI_xIMR_OVRUDRIE_Pos (0U)
14330#define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
14331#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
14332#define SAI_xIMR_MUTEDETIE_Pos (1U)
14333#define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
14334#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
14335#define SAI_xIMR_WCKCFGIE_Pos (2U)
14336#define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
14337#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
14338#define SAI_xIMR_FREQIE_Pos (3U)
14339#define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
14340#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
14341#define SAI_xIMR_CNRDYIE_Pos (4U)
14342#define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
14343#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
14344#define SAI_xIMR_AFSDETIE_Pos (5U)
14345#define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
14346#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
14347#define SAI_xIMR_LFSDETIE_Pos (6U)
14348#define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
14349#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
14350
14351/******************** Bit definition for SAI_xSR register *******************/
14352#define SAI_xSR_OVRUDR_Pos (0U)
14353#define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
14354#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
14355#define SAI_xSR_MUTEDET_Pos (1U)
14356#define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
14357#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
14358#define SAI_xSR_WCKCFG_Pos (2U)
14359#define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
14360#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
14361#define SAI_xSR_FREQ_Pos (3U)
14362#define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
14363#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
14364#define SAI_xSR_CNRDY_Pos (4U)
14365#define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
14366#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
14367#define SAI_xSR_AFSDET_Pos (5U)
14368#define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
14369#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
14370#define SAI_xSR_LFSDET_Pos (6U)
14371#define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
14372#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
14373
14374#define SAI_xSR_FLVL_Pos (16U)
14375#define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
14376#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
14377#define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
14378#define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
14379#define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
14380
14381/****************** Bit definition for SAI_xCLRFR register ******************/
14382#define SAI_xCLRFR_COVRUDR_Pos (0U)
14383#define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
14384#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
14385#define SAI_xCLRFR_CMUTEDET_Pos (1U)
14386#define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
14387#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
14388#define SAI_xCLRFR_CWCKCFG_Pos (2U)
14389#define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
14390#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
14391#define SAI_xCLRFR_CFREQ_Pos (3U)
14392#define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
14393#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
14394#define SAI_xCLRFR_CCNRDY_Pos (4U)
14395#define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
14396#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
14397#define SAI_xCLRFR_CAFSDET_Pos (5U)
14398#define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
14399#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
14400#define SAI_xCLRFR_CLFSDET_Pos (6U)
14401#define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
14402#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
14403
14404/****************** Bit definition for SAI_xDR register ******************/
14405#define SAI_xDR_DATA_Pos (0U)
14406#define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
14407#define SAI_xDR_DATA SAI_xDR_DATA_Msk
14408
14409/****************** Bit definition for SAI_PDMCR register *******************/
14410#define SAI_PDMCR_PDMEN_Pos (0U)
14411#define SAI_PDMCR_PDMEN_Msk (0x1U << SAI_PDMCR_PDMEN_Pos) /*!< 0x00000001 */
14412#define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk /*!<PDM enable */
14413
14414#define SAI_PDMCR_MICNBR_Pos (4U)
14415#define SAI_PDMCR_MICNBR_Msk (0x3U << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000030 */
14416#define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk /*!<MICNBR[1:0] (Number of microphones) */
14417#define SAI_PDMCR_MICNBR_0 (0x1U << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000010 */
14418#define SAI_PDMCR_MICNBR_1 (0x2U << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000020 */
14419
14420#define SAI_PDMCR_CKEN1_Pos (8U)
14421#define SAI_PDMCR_CKEN1_Msk (0x1U << SAI_PDMCR_CKEN1_Pos) /*!< 0x00000100 */
14422#define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk /*!<Clock 1 enable */
14423#define SAI_PDMCR_CKEN2_Pos (9U)
14424#define SAI_PDMCR_CKEN2_Msk (0x1U << SAI_PDMCR_CKEN2_Pos) /*!< 0x00000200 */
14425#define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk /*!<Clock 2 enable */
14426#define SAI_PDMCR_CKEN3_Pos (10U)
14427#define SAI_PDMCR_CKEN3_Msk (0x1U << SAI_PDMCR_CKEN3_Pos) /*!< 0x00000400 */
14428#define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk /*!<Clock 3 enable */
14429#define SAI_PDMCR_CKEN4_Pos (11U)
14430#define SAI_PDMCR_CKEN4_Msk (0x1U << SAI_PDMCR_CKEN4_Pos) /*!< 0x00000800 */
14431#define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk /*!<Clock 4 enable */
14432
14433/****************** Bit definition for SAI_PDMDLY register ******************/
14434#define SAI_PDMDLY_DLYM1L_Pos (0U)
14435#define SAI_PDMDLY_DLYM1L_Msk (0x7U << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000007 */
14436#define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
14437#define SAI_PDMDLY_DLYM1L_0 (0x1U << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000001 */
14438#define SAI_PDMDLY_DLYM1L_1 (0x2U << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000002 */
14439#define SAI_PDMDLY_DLYM1L_2 (0x4U << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000004 */
14440
14441#define SAI_PDMDLY_DLYM1R_Pos (4U)
14442#define SAI_PDMDLY_DLYM1R_Msk (0x7U << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000070 */
14443#define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
14444#define SAI_PDMDLY_DLYM1R_0 (0x1U << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000010 */
14445#define SAI_PDMDLY_DLYM1R_1 (0x2U << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000020 */
14446#define SAI_PDMDLY_DLYM1R_2 (0x4U << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000040 */
14447
14448#define SAI_PDMDLY_DLYM2L_Pos (8U)
14449#define SAI_PDMDLY_DLYM2L_Msk (0x7U << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000700 */
14450#define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
14451#define SAI_PDMDLY_DLYM2L_0 (0x1U << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000100 */
14452#define SAI_PDMDLY_DLYM2L_1 (0x2U << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000200 */
14453#define SAI_PDMDLY_DLYM2L_2 (0x4U << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000400 */
14454
14455#define SAI_PDMDLY_DLYM2R_Pos (12U)
14456#define SAI_PDMDLY_DLYM2R_Msk (0x7U << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00007000 */
14457#define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
14458#define SAI_PDMDLY_DLYM2R_0 (0x1U << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00001000 */
14459#define SAI_PDMDLY_DLYM2R_1 (0x2U << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00002000 */
14460#define SAI_PDMDLY_DLYM2R_2 (0x4U << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00004000 */
14461
14462#define SAI_PDMDLY_DLYM3L_Pos (16U)
14463#define SAI_PDMDLY_DLYM3L_Msk (0x7U << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00070000 */
14464#define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
14465#define SAI_PDMDLY_DLYM3L_0 (0x1U << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00010000 */
14466#define SAI_PDMDLY_DLYM3L_1 (0x2U << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00020000 */
14467#define SAI_PDMDLY_DLYM3L_2 (0x4U << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00040000 */
14468
14469#define SAI_PDMDLY_DLYM3R_Pos (20U)
14470#define SAI_PDMDLY_DLYM3R_Msk (0x7U << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00700000 */
14471#define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
14472#define SAI_PDMDLY_DLYM3R_0 (0x1U << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00100000 */
14473#define SAI_PDMDLY_DLYM3R_1 (0x2U << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00200000 */
14474#define SAI_PDMDLY_DLYM3R_2 (0x4U << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00400000 */
14475
14476#define SAI_PDMDLY_DLYM4L_Pos (24U)
14477#define SAI_PDMDLY_DLYM4L_Msk (0x7U << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x07000000 */
14478#define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
14479#define SAI_PDMDLY_DLYM4L_0 (0x1U << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x01000000 */
14480#define SAI_PDMDLY_DLYM4L_1 (0x2U << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x02000000 */
14481#define SAI_PDMDLY_DLYM4L_2 (0x4U << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x04000000 */
14482
14483#define SAI_PDMDLY_DLYM4R_Pos (28U)
14484#define SAI_PDMDLY_DLYM4R_Msk (0x7U << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x70000000 */
14485#define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
14486#define SAI_PDMDLY_DLYM4R_0 (0x1U << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x10000000 */
14487#define SAI_PDMDLY_DLYM4R_1 (0x2U << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */
14488#define SAI_PDMDLY_DLYM4R_2 (0x4U << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */
14489
14490/******************************************************************************/
14491/* */
14492/* SDMMC Interface */
14493/* */
14494/******************************************************************************/
14495/****************** Bit definition for SDMMC_POWER register ******************/
14496#define SDMMC_POWER_PWRCTRL_Pos (0U)
14497#define SDMMC_POWER_PWRCTRL_Msk (0x3U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
14498#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
14499#define SDMMC_POWER_PWRCTRL_0 (0x1U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000001 */
14500#define SDMMC_POWER_PWRCTRL_1 (0x2U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000002 */
14501#define SDMMC_POWER_VSWITCH_Pos (2U)
14502#define SDMMC_POWER_VSWITCH_Msk (0x1U << SDMMC_POWER_VSWITCH_Pos) /*!< 0x00000004 */
14503#define SDMMC_POWER_VSWITCH SDMMC_POWER_VSWITCH_Pos /*!<Voltage switch sequence start */
14504#define SDMMC_POWER_VSWITCHEN_Pos (3U)
14505#define SDMMC_POWER_VSWITCHEN_Msk (0x1U << SDMMC_POWER_VSWITCHEN_Pos) /*!< 0x00000008 */
14506#define SDMMC_POWER_VSWITCHEN SDMMC_POWER_VSWITCHEN_Pos /*!<Voltage switch procedure enable */
14507#define SDMMC_POWER_DIRPOL_Pos (4U)
14508#define SDMMC_POWER_DIRPOL_Msk (0x1U << SDMMC_POWER_DIRPOL_Pos) /*!< 0x00000010 */
14509#define SDMMC_POWER_DIRPOL SDMMC_POWER_DIRPOL_Pos /*!<Data and Command direction signals polarity selection */
14510
14511/****************** Bit definition for SDMMC_CLKCR register ******************/
14512#define SDMMC_CLKCR_CLKDIV_Pos (0U)
14513#define SDMMC_CLKCR_CLKDIV_Msk (0x3FFU << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000003FF */
14514#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
14515#define SDMMC_CLKCR_PWRSAV_Pos (12U)
14516#define SDMMC_CLKCR_PWRSAV_Msk (0x1U << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00001000 */
14517#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
14518
14519#define SDMMC_CLKCR_WIDBUS_Pos (14U)
14520#define SDMMC_CLKCR_WIDBUS_Msk (0x3U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x0000C000 */
14521#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
14522#define SDMMC_CLKCR_WIDBUS_0 (0x1U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00000800 */
14523#define SDMMC_CLKCR_WIDBUS_1 (0x2U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00001000 */
14524
14525#define SDMMC_CLKCR_NEGEDGE_Pos (16U)
14526#define SDMMC_CLKCR_NEGEDGE_Msk (0x1U << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00010000 */
14527#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */
14528#define SDMMC_CLKCR_HWFC_EN_Pos (17U)
14529#define SDMMC_CLKCR_HWFC_EN_Msk (0x1U << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00020000 */
14530#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
14531#define SDMMC_CLKCR_DDR_Pos (18U)
14532#define SDMMC_CLKCR_DDR_Msk (0x1U << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
14533#define SDMMC_CLKCR_DDR SDMMC_CLKCR_DDR_Msk /*!<Data rate signaling selection */
14534#define SDMMC_CLKCR_BUSSPEED_Pos (19U)
14535#define SDMMC_CLKCR_BUSSPEED_Msk (0x1U << SDMMC_CLKCR_BUSSPEED_Pos) /*!< 0x00080000 */
14536#define SDMMC_CLKCR_BUSSPEED SDMMC_CLKCR_BUSSPEED_Msk /*!<Bus speed mode selection */
14537
14538#define SDMMC_CLKCR_SELCLKRX_Pos (20U)
14539#define SDMMC_CLKCR_SELCLKRX_Msk (0x3U << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00030000 */
14540#define SDMMC_CLKCR_SELCLKRX SDMMC_CLKCR_SELCLKRX_Msk /*!<SELCLKRX[1:0] bits (Receive clock selection) */
14541#define SDMMC_CLKCR_SELCLKRX_0 (0x1U << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00010000 */
14542#define SDMMC_CLKCR_SELCLKRX_1 (0x2U << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00020000 */
14543
14544/******************* Bit definition for SDMMC_ARG register *******************/
14545#define SDMMC_ARG_CMDARG_Pos (0U)
14546#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
14547#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */
14548
14549/******************* Bit definition for SDMMC_CMD register *******************/
14550#define SDMMC_CMD_CMDINDEX_Pos (0U)
14551#define SDMMC_CMD_CMDINDEX_Msk (0x3FU << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
14552#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */
14553#define SDMMC_CMD_CMDTRANS_Pos (6U)
14554#define SDMMC_CMD_CMDTRANS_Msk (0x1U << SDMMC_CMD_CMDTRANS_Pos) /*!< 0x00000040 */
14555#define SDMMC_CMD_CMDTRANS SDMMC_CMD_CMDTRANS_Msk /*!<CPSM Treats command as a Data Transfer */
14556#define SDMMC_CMD_CMDSTOP_Pos (7U)
14557#define SDMMC_CMD_CMDSTOP_Msk (0x1U << SDMMC_CMD_CMDSTOP_Pos) /*!< 0x00000080 */
14558#define SDMMC_CMD_CMDSTOP SDMMC_CMD_CMDSTOP_Msk /*!<CPSM Treats command as a Stop */
14559
14560#define SDMMC_CMD_WAITRESP_Pos (8U)
14561#define SDMMC_CMD_WAITRESP_Msk (0x3U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000300 */
14562#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
14563#define SDMMC_CMD_WAITRESP_0 (0x1U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000100 */
14564#define SDMMC_CMD_WAITRESP_1 (0x2U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000200 */
14565
14566#define SDMMC_CMD_WAITINT_Pos (10U)
14567#define SDMMC_CMD_WAITINT_Msk (0x1U << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000400 */
14568#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
14569#define SDMMC_CMD_WAITPEND_Pos (11U)
14570#define SDMMC_CMD_WAITPEND_Msk (0x1U << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000800 */
14571#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
14572#define SDMMC_CMD_CPSMEN_Pos (12U)
14573#define SDMMC_CMD_CPSMEN_Msk (0x1U << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00001000 */
14574#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
14575#define SDMMC_CMD_DTHOLD_Pos (13U)
14576#define SDMMC_CMD_DTHOLD_Msk (0x1U << SDMMC_CMD_DTHOLD_Pos) /*!< 0x00002000 */
14577#define SDMMC_CMD_DTHOLD SDMMC_CMD_DTHOLD_Msk /*!<Hold new data block transmission and reception in the DPSM */
14578#define SDMMC_CMD_BOOTMODE_Pos (14U)
14579#define SDMMC_CMD_BOOTMODE_Msk (0x1U << SDMMC_CMD_BOOTMODE_Pos) /*!< 0x00004000 */
14580#define SDMMC_CMD_BOOTMODE SDMMC_CMD_BOOTMODE_Msk /*!<Boot mode */
14581#define SDMMC_CMD_BOOTEN_Pos (15U)
14582#define SDMMC_CMD_BOOTEN_Msk (0x1U << SDMMC_CMD_BOOTEN_Pos) /*!< 0x00008000 */
14583#define SDMMC_CMD_BOOTEN SDMMC_CMD_BOOTEN_Msk /*!<Enable Boot mode procedure */
14584#define SDMMC_CMD_CMDSUSPEND_Pos (16U)
14585#define SDMMC_CMD_CMDSUSPEND_Msk (0x1U << SDMMC_CMD_CMDSUSPEND_Pos) /*!< 0x00010000 */
14586#define SDMMC_CMD_CMDSUSPEND SDMMC_CMD_CMDSUSPEND_Msk /*!<CPSM treats command as a Suspend or Resume command */
14587
14588/***************** Bit definition for SDMMC_RESPCMD register *****************/
14589#define SDMMC_RESPCMD_RESPCMD_Pos (0U)
14590#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
14591#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */
14592
14593/****************** Bit definition for SDMMC_RESP1 register ******************/
14594#define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
14595#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
14596#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */
14597
14598/****************** Bit definition for SDMMC_RESP2 register ******************/
14599#define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
14600#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
14601#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */
14602
14603/****************** Bit definition for SDMMC_RESP3 register ******************/
14604#define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
14605#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
14606#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */
14607
14608/****************** Bit definition for SDMMC_RESP4 register ******************/
14609#define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
14610#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
14611#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */
14612
14613/****************** Bit definition for SDMMC_DTIMER register *****************/
14614#define SDMMC_DTIMER_DATATIME_Pos (0U)
14615#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
14616#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */
14617
14618/****************** Bit definition for SDMMC_DLEN register *******************/
14619#define SDMMC_DLEN_DATALENGTH_Pos (0U)
14620#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
14621#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */
14622
14623/****************** Bit definition for SDMMC_DCTRL register ******************/
14624#define SDMMC_DCTRL_DTEN_Pos (0U)
14625#define SDMMC_DCTRL_DTEN_Msk (0x1U << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */
14626#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
14627#define SDMMC_DCTRL_DTDIR_Pos (1U)
14628#define SDMMC_DCTRL_DTDIR_Msk (0x1U << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
14629#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
14630
14631#define SDMMC_DCTRL_DTMODE_Pos (2U)
14632#define SDMMC_DCTRL_DTMODE_Msk (0x3U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x0000000C */
14633#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
14634#define SDMMC_DCTRL_DTMODE_0 (0x1U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
14635#define SDMMC_DCTRL_DTMODE_1 (0x2U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000008 */
14636
14637#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
14638#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
14639#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
14640#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */
14641#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */
14642#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */
14643#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */
14644
14645#define SDMMC_DCTRL_RWSTART_Pos (8U)
14646#define SDMMC_DCTRL_RWSTART_Msk (0x1U << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
14647#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */
14648#define SDMMC_DCTRL_RWSTOP_Pos (9U)
14649#define SDMMC_DCTRL_RWSTOP_Msk (0x1U << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
14650#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */
14651#define SDMMC_DCTRL_RWMOD_Pos (10U)
14652#define SDMMC_DCTRL_RWMOD_Msk (0x1U << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
14653#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */
14654#define SDMMC_DCTRL_SDIOEN_Pos (11U)
14655#define SDMMC_DCTRL_SDIOEN_Msk (0x1U << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
14656#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
14657#define SDMMC_DCTRL_BOOTACKEN_Pos (12U)
14658#define SDMMC_DCTRL_BOOTACKEN_Msk (0x1U << SDMMC_DCTRL_BOOTACKEN_Pos) /*!< 0x00001000 */
14659#define SDMMC_DCTRL_BOOTACKEN SDMMC_DCTRL_BOOTACKEN_Msk /*!<Data transfer mode selection */
14660#define SDMMC_DCTRL_FIFORST_Pos (13U)
14661#define SDMMC_DCTRL_FIFORST_Msk (0x1U << SDMMC_DCTRL_FIFORST_Pos) /*!< 0x00002000 */
14662#define SDMMC_DCTRL_FIFORST SDMMC_DCTRL_FIFORST_Msk /*!<FIFO reset */
14663
14664/****************** Bit definition for SDMMC_DCOUNT register *****************/
14665#define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
14666#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
14667#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
14668
14669/****************** Bit definition for SDMMC_STA register ********************/
14670#define SDMMC_STA_CCRCFAIL_Pos (0U)
14671#define SDMMC_STA_CCRCFAIL_Msk (0x1U << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
14672#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
14673#define SDMMC_STA_DCRCFAIL_Pos (1U)
14674#define SDMMC_STA_DCRCFAIL_Msk (0x1U << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
14675#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
14676#define SDMMC_STA_CTIMEOUT_Pos (2U)
14677#define SDMMC_STA_CTIMEOUT_Msk (0x1U << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
14678#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */
14679#define SDMMC_STA_DTIMEOUT_Pos (3U)
14680#define SDMMC_STA_DTIMEOUT_Msk (0x1U << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
14681#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */
14682#define SDMMC_STA_TXUNDERR_Pos (4U)
14683#define SDMMC_STA_TXUNDERR_Msk (0x1U << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */
14684#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
14685#define SDMMC_STA_RXOVERR_Pos (5U)
14686#define SDMMC_STA_RXOVERR_Msk (0x1U << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */
14687#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
14688#define SDMMC_STA_CMDREND_Pos (6U)
14689#define SDMMC_STA_CMDREND_Msk (0x1U << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */
14690#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
14691#define SDMMC_STA_CMDSENT_Pos (7U)
14692#define SDMMC_STA_CMDSENT_Msk (0x1U << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */
14693#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */
14694#define SDMMC_STA_DATAEND_Pos (8U)
14695#define SDMMC_STA_DATAEND_Msk (0x1U << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
14696#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
14697#define SDMMC_STA_DHOLD_Pos (9U)
14698#define SDMMC_STA_DHOLD_Msk (0x1U << SDMMC_STA_DHOLD_Pos) /*!< 0x00000200 */
14699#define SDMMC_STA_DHOLD SDMMC_STA_DHOLD_Msk /*!<Data transfer Hold */
14700#define SDMMC_STA_DBCKEND_Pos (10U)
14701#define SDMMC_STA_DBCKEND_Msk (0x1U << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
14702#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
14703#define SDMMC_STA_DABORT_Pos (11U)
14704#define SDMMC_STA_DABORT_Msk (0x1U << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
14705#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
14706#define SDMMC_STA_DPSMACT_Pos (12U)
14707#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
14708#define SDMMC_STA_DPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
14709#define SDMMC_STA_CPSMACT_Pos (13U)
14710#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
14711#define SDMMC_STA_CPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
14712#define SDMMC_STA_TXFIFOHE_Pos (14U)
14713#define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
14714#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
14715#define SDMMC_STA_RXFIFOHF_Pos (15U)
14716#define SDMMC_STA_RXFIFOHF_Msk (0x1U << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
14717#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
14718#define SDMMC_STA_TXFIFOF_Pos (16U)
14719#define SDMMC_STA_TXFIFOF_Msk (0x1U << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */
14720#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
14721#define SDMMC_STA_RXFIFOF_Pos (17U)
14722#define SDMMC_STA_RXFIFOF_Msk (0x1U << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */
14723#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */
14724#define SDMMC_STA_TXFIFOE_Pos (18U)
14725#define SDMMC_STA_TXFIFOE_Msk (0x1U << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */
14726#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
14727#define SDMMC_STA_RXFIFOE_Pos (19U)
14728#define SDMMC_STA_RXFIFOE_Msk (0x1U << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */
14729#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
14730#define SDMMC_STA_BUSYD0_Pos (20U)
14731#define SDMMC_STA_BUSYD0_Msk (0x1U << SDMMC_STA_BUSYD0_Pos) /*!< 0x00100000 */
14732#define SDMMC_STA_BUSYD0 SDMMC_STA_BUSYD0_Msk /*!<Inverted value of SDMMC_D0 line (Busy) */
14733#define SDMMC_STA_BUSYD0END_Pos (21U)
14734#define SDMMC_STA_BUSYD0END_Msk (0x1U << SDMMC_STA_BUSYD0END_Pos) /*!< 0x00200000 */
14735#define SDMMC_STA_BUSYD0END SDMMC_STA_BUSYD0END_Msk /*!<End of SDMMC_D0 Busy following a CMD response detected */
14736#define SDMMC_STA_SDIOIT_Pos (22U)
14737#define SDMMC_STA_SDIOIT_Msk (0x1U << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
14738#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDIO interrupt received */
14739#define SDMMC_STA_ACKFAIL_Pos (23U)
14740#define SDMMC_STA_ACKFAIL_Msk (0x1U << SDMMC_STA_ACKFAIL_Pos) /*!< 0x00800000 */
14741#define SDMMC_STA_ACKFAIL SDMMC_STA_ACKFAIL_Msk /*!<Boot Acknowledgment received (BootAck check fail) */
14742#define SDMMC_STA_ACKTIMEOUT_Pos (24U)
14743#define SDMMC_STA_ACKTIMEOUT_Msk (0x1U << SDMMC_STA_ACKTIMEOUT_Pos) /*!< 0x01000000 */
14744#define SDMMC_STA_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT_Msk /*!<Boot Acknowledgment timeout */
14745#define SDMMC_STA_VSWEND_Pos (25U)
14746#define SDMMC_STA_VSWEND_Msk (0x1U << SDMMC_STA_VSWEND_Pos) /*!< 0x02000000 */
14747#define SDMMC_STA_VSWEND SDMMC_STA_VSWEND_Msk /*!<Voltage switch critical timing section completion */
14748#define SDMMC_STA_CKSTOP_Pos (26U)
14749#define SDMMC_STA_CKSTOP_Msk (0x1U << SDMMC_STA_CKSTOP_Pos) /*!< 0x04000000 */
14750#define SDMMC_STA_CKSTOP SDMMC_STA_CKSTOP_Msk /*!<SDMMC_CK stopped in Voltage switch procedure */
14751#define SDMMC_STA_IDMATE_Pos (27U)
14752#define SDMMC_STA_IDMATE_Msk (0x1U << SDMMC_STA_IDMATE_Pos) /*!< 0x08000000 */
14753#define SDMMC_STA_IDMATE SDMMC_STA_IDMATE_Msk /*!<IDMA transfer error */
14754#define SDMMC_STA_IDMABTC_Pos (28U)
14755#define SDMMC_STA_IDMABTC_Msk (0x1U << SDMMC_STA_IDMABTC_Pos) /*!< 0x10000000 */
14756#define SDMMC_STA_IDMABTC SDMMC_STA_IDMABTC_Msk /*!<IDMA buffer transfer complete */
14757
14758/******************* Bit definition for SDMMC_ICR register *******************/
14759#define SDMMC_ICR_CCRCFAILC_Pos (0U)
14760#define SDMMC_ICR_CCRCFAILC_Msk (0x1U << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
14761#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
14762#define SDMMC_ICR_DCRCFAILC_Pos (1U)
14763#define SDMMC_ICR_DCRCFAILC_Msk (0x1U << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
14764#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
14765#define SDMMC_ICR_CTIMEOUTC_Pos (2U)
14766#define SDMMC_ICR_CTIMEOUTC_Msk (0x1U << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
14767#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
14768#define SDMMC_ICR_DTIMEOUTC_Pos (3U)
14769#define SDMMC_ICR_DTIMEOUTC_Msk (0x1U << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
14770#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
14771#define SDMMC_ICR_TXUNDERRC_Pos (4U)
14772#define SDMMC_ICR_TXUNDERRC_Msk (0x1U << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
14773#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
14774#define SDMMC_ICR_RXOVERRC_Pos (5U)
14775#define SDMMC_ICR_RXOVERRC_Msk (0x1U << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
14776#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
14777#define SDMMC_ICR_CMDRENDC_Pos (6U)
14778#define SDMMC_ICR_CMDRENDC_Msk (0x1U << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
14779#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
14780#define SDMMC_ICR_CMDSENTC_Pos (7U)
14781#define SDMMC_ICR_CMDSENTC_Msk (0x1U << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
14782#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
14783#define SDMMC_ICR_DATAENDC_Pos (8U)
14784#define SDMMC_ICR_DATAENDC_Msk (0x1U << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */
14785#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
14786#define SDMMC_ICR_DHOLDC_Pos (9U)
14787#define SDMMC_ICR_DHOLDC_Msk (0x1U << SDMMC_ICR_DHOLDC_Pos) /*!< 0x00000200 */
14788#define SDMMC_ICR_DHOLDC SDMMC_ICR_DHOLDC_Msk /*!<DHOLD flag clear bit */
14789#define SDMMC_ICR_DBCKENDC_Pos (10U)
14790#define SDMMC_ICR_DBCKENDC_Msk (0x1U << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
14791#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
14792#define SDMMC_ICR_DABORTC_Pos (11U)
14793#define SDMMC_ICR_DABORTC_Msk (0x1U << SDMMC_ICR_DABORTC_Pos) /*!< 0x00000800 */
14794#define SDMMC_ICR_DABORTC SDMMC_ICR_DABORTC_Msk /*!<DABORTC flag clear bit */
14795#define SDMMC_ICR_BUSYD0ENDC_Pos (21U)
14796#define SDMMC_ICR_BUSYD0ENDC_Msk (0x1U << SDMMC_ICR_BUSYD0ENDC_Pos) /*!< 0x00200000 */
14797#define SDMMC_ICR_BUSYD0ENDC SDMMC_ICR_BUSYD0ENDC_Msk /*!<BUSYD0ENDC flag clear bit */
14798#define SDMMC_ICR_SDIOITC_Pos (22U)
14799#define SDMMC_ICR_SDIOITC_Msk (0x1U << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */
14800#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
14801#define SDMMC_ICR_ACKFAILC_Pos (23U)
14802#define SDMMC_ICR_ACKFAILC_Msk (0x1U << SDMMC_ICR_ACKFAILC_Pos) /*!< 0x00800000 */
14803#define SDMMC_ICR_ACKFAILC SDMMC_ICR_ACKFAILC_Msk /*!<ACKFAILC flag clear bit */
14804#define SDMMC_ICR_ACKTIMEOUTC_Pos (24U)
14805#define SDMMC_ICR_ACKTIMEOUTC_Msk (0x1U << SDMMC_ICR_ACKTIMEOUTC_Pos) /*!< 0x01000000 */
14806#define SDMMC_ICR_ACKTIMEOUTC SDMMC_ICR_ACKTIMEOUTC_Msk /*!<ACKTIMEOUTC flag clear bit */
14807#define SDMMC_ICR_VSWENDC_Pos (25U)
14808#define SDMMC_ICR_VSWENDC_Msk (0x1U << SDMMC_ICR_VSWENDC_Pos) /*!< 0x02000000 */
14809#define SDMMC_ICR_VSWENDC SDMMC_ICR_VSWENDC_Msk /*!<VSWENDC flag clear bit */
14810#define SDMMC_ICR_CKSTOPC_Pos (26U)
14811#define SDMMC_ICR_CKSTOPC_Msk (0x1U << SDMMC_ICR_CKSTOPC_Pos) /*!< 0x04000000 */
14812#define SDMMC_ICR_CKSTOPC SDMMC_ICR_CKSTOPC_Msk /*!<CKSTOPC flag clear bit */
14813#define SDMMC_ICR_IDMATEC_Pos (27U)
14814#define SDMMC_ICR_IDMATEC_Msk (0x1U << SDMMC_ICR_IDMATEC_Pos) /*!< 0x08000000 */
14815#define SDMMC_ICR_IDMATEC SDMMC_ICR_IDMATEC_Msk /*!<IDMATEC flag clear bit */
14816#define SDMMC_ICR_IDMABTCC_Pos (28U)
14817#define SDMMC_ICR_IDMABTCC_Msk (0x1U << SDMMC_ICR_IDMABTCC_Pos) /*!< 0x10000000 */
14818#define SDMMC_ICR_IDMABTCC SDMMC_ICR_IDMABTCC_Msk /*!<IDMABTCC flag clear bit */
14819
14820/****************** Bit definition for SDMMC_MASK register *******************/
14821#define SDMMC_MASK_CCRCFAILIE_Pos (0U)
14822#define SDMMC_MASK_CCRCFAILIE_Msk (0x1U << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
14823#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
14824#define SDMMC_MASK_DCRCFAILIE_Pos (1U)
14825#define SDMMC_MASK_DCRCFAILIE_Msk (0x1U << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
14826#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
14827#define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
14828#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
14829#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
14830#define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
14831#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
14832#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
14833#define SDMMC_MASK_TXUNDERRIE_Pos (4U)
14834#define SDMMC_MASK_TXUNDERRIE_Msk (0x1U << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
14835#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
14836#define SDMMC_MASK_RXOVERRIE_Pos (5U)
14837#define SDMMC_MASK_RXOVERRIE_Msk (0x1U << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
14838#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
14839#define SDMMC_MASK_CMDRENDIE_Pos (6U)
14840#define SDMMC_MASK_CMDRENDIE_Msk (0x1U << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
14841#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
14842#define SDMMC_MASK_CMDSENTIE_Pos (7U)
14843#define SDMMC_MASK_CMDSENTIE_Msk (0x1U << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
14844#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
14845#define SDMMC_MASK_DATAENDIE_Pos (8U)
14846#define SDMMC_MASK_DATAENDIE_Msk (0x1U << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
14847#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
14848#define SDMMC_MASK_DHOLDIE_Pos (9U)
14849#define SDMMC_MASK_DHOLDIE_Msk (0x1U << SDMMC_MASK_DHOLDIE_Pos) /*!< 0x00000200 */
14850#define SDMMC_MASK_DHOLDIE SDMMC_MASK_DHOLDIE_Msk /*!<Data Hold Interrupt Enable */
14851#define SDMMC_MASK_DBCKENDIE_Pos (10U)
14852#define SDMMC_MASK_DBCKENDIE_Msk (0x1U << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
14853#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
14854#define SDMMC_MASK_DABORTIE_Pos (11U)
14855#define SDMMC_MASK_DABORTIE_Msk (0x1U << SDMMC_MASK_DABORTIE_Pos) /*!< 0x00000800 */
14856#define SDMMC_MASK_DABORTIE SDMMC_MASK_DABORTIE_Msk /*!<Data transfer aborted Interrupt Enable */
14857#define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
14858#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
14859#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
14860#define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
14861#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
14862#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
14863#define SDMMC_MASK_RXFIFOFIE_Pos (17U)
14864#define SDMMC_MASK_RXFIFOFIE_Msk (0x1U << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
14865#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
14866#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
14867#define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
14868#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
14869#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
14870#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1U << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
14871#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0END interrupt Enable */
14872#define SDMMC_MASK_SDIOITIE_Pos (22U)
14873#define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
14874#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
14875#define SDMMC_MASK_ACKFAILIE_Pos (23U)
14876#define SDMMC_MASK_ACKFAILIE_Msk (0x1U << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
14877#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
14878#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
14879#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1U << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
14880#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
14881#define SDMMC_MASK_VSWENDIE_Pos (25U)
14882#define SDMMC_MASK_VSWENDIE_Msk (0x1U << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
14883#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
14884#define SDMMC_MASK_CKSTOPIE_Pos (26U)
14885#define SDMMC_MASK_CKSTOPIE_Msk (0x1U << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x03000000 */
14886#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
14887#define SDMMC_MASK_IDMABTCIE_Pos (28U)
14888#define SDMMC_MASK_IDMABTCIE_Msk (0x1U << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
14889#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
14890
14891/***************** Bit definition for SDMMC_FIFOCNT register *****************/
14892#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
14893#define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
14894#define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
14895
14896/****************** Bit definition for SDMMC_FIFO register *******************/
14897#define SDMMC_FIFO_FIFODATA_Pos (0U)
14898#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
14899#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
14900
14901/****************** Bit definition for SDMMC_IDMACTRL register ****************/
14902#define SDMMC_IDMA_IDMAEN_Pos (0U)
14903#define SDMMC_IDMA_IDMAEN_Msk (0x1U << SDMMC_IDMA_IDMAEN_Pos) /*!< 0x00000001 */
14904#define SDMMC_IDMA_IDMAEN SDMMC_IDMA_IDMAEN_Msk /*!< Enable the internal DMA of the SDMMC peripheral */
14905#define SDMMC_IDMA_IDMABMODE_Pos (1U)
14906#define SDMMC_IDMA_IDMABMODE_Msk (0x1U << SDMMC_IDMA_IDMABMODE_Pos) /*!< 0x00000002 */
14907#define SDMMC_IDMA_IDMABMODE SDMMC_IDMA_IDMABMODE_Msk /*!< Enable double buffer mode for IDMA */
14908#define SDMMC_IDMA_IDMABACT_Pos (2U)
14909#define SDMMC_IDMA_IDMABACT_Msk (0x1U << SDMMC_IDMA_IDMABACT_Pos) /*!< 0x00000004 */
14910#define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk /*!< Uses buffer 1 when double buffer mode is selected */
14911
14912/******************************************************************************/
14913/* */
14914/* Serial Peripheral Interface (SPI) */
14915/* */
14916/******************************************************************************/
14917/******************* Bit definition for SPI_CR1 register ********************/
14918#define SPI_CR1_CPHA_Pos (0U)
14919#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
14920#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
14921#define SPI_CR1_CPOL_Pos (1U)
14922#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
14923#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
14924#define SPI_CR1_MSTR_Pos (2U)
14925#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
14926#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
14927
14928#define SPI_CR1_BR_Pos (3U)
14929#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
14930#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
14931#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
14932#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
14933#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
14934
14935#define SPI_CR1_SPE_Pos (6U)
14936#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
14937#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
14938#define SPI_CR1_LSBFIRST_Pos (7U)
14939#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
14940#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
14941#define SPI_CR1_SSI_Pos (8U)
14942#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
14943#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
14944#define SPI_CR1_SSM_Pos (9U)
14945#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
14946#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
14947#define SPI_CR1_RXONLY_Pos (10U)
14948#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
14949#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
14950#define SPI_CR1_CRCL_Pos (11U)
14951#define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
14952#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
14953#define SPI_CR1_CRCNEXT_Pos (12U)
14954#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
14955#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
14956#define SPI_CR1_CRCEN_Pos (13U)
14957#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
14958#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
14959#define SPI_CR1_BIDIOE_Pos (14U)
14960#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
14961#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
14962#define SPI_CR1_BIDIMODE_Pos (15U)
14963#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
14964#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
14965
14966/******************* Bit definition for SPI_CR2 register ********************/
14967#define SPI_CR2_RXDMAEN_Pos (0U)
14968#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
14969#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
14970#define SPI_CR2_TXDMAEN_Pos (1U)
14971#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
14972#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
14973#define SPI_CR2_SSOE_Pos (2U)
14974#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
14975#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
14976#define SPI_CR2_NSSP_Pos (3U)
14977#define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
14978#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
14979#define SPI_CR2_FRF_Pos (4U)
14980#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
14981#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
14982#define SPI_CR2_ERRIE_Pos (5U)
14983#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
14984#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
14985#define SPI_CR2_RXNEIE_Pos (6U)
14986#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
14987#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
14988#define SPI_CR2_TXEIE_Pos (7U)
14989#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
14990#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
14991#define SPI_CR2_DS_Pos (8U)
14992#define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
14993#define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
14994#define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
14995#define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
14996#define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
14997#define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
14998#define SPI_CR2_FRXTH_Pos (12U)
14999#define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
15000#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
15001#define SPI_CR2_LDMARX_Pos (13U)
15002#define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
15003#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
15004#define SPI_CR2_LDMATX_Pos (14U)
15005#define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
15006#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
15007
15008/******************** Bit definition for SPI_SR register ********************/
15009#define SPI_SR_RXNE_Pos (0U)
15010#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
15011#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
15012#define SPI_SR_TXE_Pos (1U)
15013#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
15014#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
15015#define SPI_SR_CHSIDE_Pos (2U)
15016#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
15017#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
15018#define SPI_SR_UDR_Pos (3U)
15019#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
15020#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
15021#define SPI_SR_CRCERR_Pos (4U)
15022#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
15023#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
15024#define SPI_SR_MODF_Pos (5U)
15025#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
15026#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
15027#define SPI_SR_OVR_Pos (6U)
15028#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
15029#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
15030#define SPI_SR_BSY_Pos (7U)
15031#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
15032#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
15033#define SPI_SR_FRE_Pos (8U)
15034#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
15035#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
15036#define SPI_SR_FRLVL_Pos (9U)
15037#define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
15038#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
15039#define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
15040#define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
15041#define SPI_SR_FTLVL_Pos (11U)
15042#define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
15043#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
15044#define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
15045#define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
15046
15047/******************** Bit definition for SPI_DR register ********************/
15048#define SPI_DR_DR_Pos (0U)
15049#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
15050#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
15051
15052/******************* Bit definition for SPI_CRCPR register ******************/
15053#define SPI_CRCPR_CRCPOLY_Pos (0U)
15054#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
15055#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
15056
15057/****************** Bit definition for SPI_RXCRCR register ******************/
15058#define SPI_RXCRCR_RXCRC_Pos (0U)
15059#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
15060#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
15061
15062/****************** Bit definition for SPI_TXCRCR register ******************/
15063#define SPI_TXCRCR_TXCRC_Pos (0U)
15064#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
15065#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
15066
15067/******************************************************************************/
15068/* */
15069/* OCTOSPI */
15070/* */
15071/******************************************************************************/
15072/***************** Bit definition for OCTOSPI_CR register *******************/
15073#define OCTOSPI_CR_EN_Pos (0U)
15074#define OCTOSPI_CR_EN_Msk (0x1U << OCTOSPI_CR_EN_Pos) /*!< 0x00000001 */
15075#define OCTOSPI_CR_EN OCTOSPI_CR_EN_Msk /*!< Enable */
15076#define OCTOSPI_CR_ABORT_Pos (1U)
15077#define OCTOSPI_CR_ABORT_Msk (0x1U << OCTOSPI_CR_ABORT_Pos) /*!< 0x00000002 */
15078#define OCTOSPI_CR_ABORT OCTOSPI_CR_ABORT_Msk /*!< Abort request */
15079#define OCTOSPI_CR_DMAEN_Pos (2U)
15080#define OCTOSPI_CR_DMAEN_Msk (0x1U << OCTOSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
15081#define OCTOSPI_CR_DMAEN OCTOSPI_CR_DMAEN_Msk /*!< DMA Enable */
15082#define OCTOSPI_CR_TCEN_Pos (3U)
15083#define OCTOSPI_CR_TCEN_Msk (0x1U << OCTOSPI_CR_TCEN_Pos) /*!< 0x00000008 */
15084#define OCTOSPI_CR_TCEN OCTOSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
15085#define OCTOSPI_CR_DQM_Pos (6U)
15086#define OCTOSPI_CR_DQM_Msk (0x1U << OCTOSPI_CR_DQM_Pos) /*!< 0x00000040 */
15087#define OCTOSPI_CR_DQM OCTOSPI_CR_DQM_Msk /*!< Dual-Quad Mode */
15088#define OCTOSPI_CR_FSEL_Pos (7U)
15089#define OCTOSPI_CR_FSEL_Msk (0x1U << OCTOSPI_CR_FSEL_Pos) /*!< 0x00000080 */
15090#define OCTOSPI_CR_FSEL OCTOSPI_CR_FSEL_Msk /*!< Flash Select */
15091#define OCTOSPI_CR_FTHRES_Pos (8U)
15092#define OCTOSPI_CR_FTHRES_Msk (0x1FU << OCTOSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
15093#define OCTOSPI_CR_FTHRES OCTOSPI_CR_FTHRES_Msk /*!< FIFO Threshold Level */
15094#define OCTOSPI_CR_TEIE_Pos (16U)
15095#define OCTOSPI_CR_TEIE_Msk (0x1U << OCTOSPI_CR_TEIE_Pos) /*!< 0x00010000 */
15096#define OCTOSPI_CR_TEIE OCTOSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
15097#define OCTOSPI_CR_TCIE_Pos (17U)
15098#define OCTOSPI_CR_TCIE_Msk (0x1U << OCTOSPI_CR_TCIE_Pos) /*!< 0x00020000 */
15099#define OCTOSPI_CR_TCIE OCTOSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
15100#define OCTOSPI_CR_FTIE_Pos (18U)
15101#define OCTOSPI_CR_FTIE_Msk (0x1U << OCTOSPI_CR_FTIE_Pos) /*!< 0x00040000 */
15102#define OCTOSPI_CR_FTIE OCTOSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
15103#define OCTOSPI_CR_SMIE_Pos (19U)
15104#define OCTOSPI_CR_SMIE_Msk (0x1U << OCTOSPI_CR_SMIE_Pos) /*!< 0x00080000 */
15105#define OCTOSPI_CR_SMIE OCTOSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
15106#define OCTOSPI_CR_TOIE_Pos (20U)
15107#define OCTOSPI_CR_TOIE_Msk (0x1U << OCTOSPI_CR_TOIE_Pos) /*!< 0x00100000 */
15108#define OCTOSPI_CR_TOIE OCTOSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
15109#define OCTOSPI_CR_APMS_Pos (22U)
15110#define OCTOSPI_CR_APMS_Msk (0x1U << OCTOSPI_CR_APMS_Pos) /*!< 0x00400000 */
15111#define OCTOSPI_CR_APMS OCTOSPI_CR_APMS_Msk /*!< Automatic Poll Mode Stop */
15112#define OCTOSPI_CR_PMM_Pos (23U)
15113#define OCTOSPI_CR_PMM_Msk (0x1U << OCTOSPI_CR_PMM_Pos) /*!< 0x00800000 */
15114#define OCTOSPI_CR_PMM OCTOSPI_CR_PMM_Msk /*!< Polling Match Mode */
15115#define OCTOSPI_CR_FMODE_Pos (28U)
15116#define OCTOSPI_CR_FMODE_Msk (0x3U << OCTOSPI_CR_FMODE_Pos) /*!< 0x30000000 */
15117#define OCTOSPI_CR_FMODE OCTOSPI_CR_FMODE_Msk /*!< Functional Mode */
15118#define OCTOSPI_CR_FMODE_0 (0x1U << OCTOSPI_CR_FMODE_Pos) /*!< 0x10000000 */
15119#define OCTOSPI_CR_FMODE_1 (0x2U << OCTOSPI_CR_FMODE_Pos) /*!< 0x20000000 */
15120
15121/**************** Bit definition for OCTOSPI_DCR1 register ******************/
15122#define OCTOSPI_DCR1_CKMODE_Pos (0U)
15123#define OCTOSPI_DCR1_CKMODE_Msk (0x1U << OCTOSPI_DCR1_CKMODE_Pos) /*!< 0x00000001 */
15124#define OCTOSPI_DCR1_CKMODE OCTOSPI_DCR1_CKMODE_Msk /*!< Mode 0 / Mode 3 */
15125#define OCTOSPI_DCR1_FRCK_Pos (1U)
15126#define OCTOSPI_DCR1_FRCK_Msk (0x1U << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */
15127#define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */
15128#define OCTOSPI_DCR1_CSHT_Pos (8U)
15129#define OCTOSPI_DCR1_CSHT_Msk (0x7U << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
15130#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
15131#define OCTOSPI_DCR1_DEVSIZE_Pos (16U)
15132#define OCTOSPI_DCR1_DEVSIZE_Msk (0x1FU << OCTOSPI_DCR1_DEVSIZE_Pos) /*!< 0x001F0000 */
15133#define OCTOSPI_DCR1_DEVSIZE OCTOSPI_DCR1_DEVSIZE_Msk /*!< Device Size */
15134#define OCTOSPI_DCR1_MTYP_Pos (24U)
15135#define OCTOSPI_DCR1_MTYP_Msk (0x7U << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x07000000 */
15136#define OCTOSPI_DCR1_MTYP OCTOSPI_DCR1_MTYP_Msk /*!< Memory Type */
15137#define OCTOSPI_DCR1_MTYP_0 (0x1U << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x01000000 */
15138#define OCTOSPI_DCR1_MTYP_1 (0x2U << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
15139#define OCTOSPI_DCR1_MTYP_2 (0x4U << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
15140
15141/**************** Bit definition for OCTOSPI_DCR2 register ******************/
15142#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
15143#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFU << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
15144#define OCTOSPI_DCR2_PRESCALER OCTOSPI_DCR2_PRESCALER_Msk /*!< Clock prescaler */
15145#define OCTOSPI_DCR2_WRAPSIZE_Pos (16U)
15146#define OCTOSPI_DCR2_WRAPSIZE_Msk (0x7U << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00070000 */
15147#define OCTOSPI_DCR2_WRAPSIZE OCTOSPI_DCR2_WRAPSIZE_Msk /*!< Wrap Size */
15148#define OCTOSPI_DCR2_WRAPSIZE_0 (0x1U << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00010000 */
15149#define OCTOSPI_DCR2_WRAPSIZE_1 (0x2U << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00020000 */
15150#define OCTOSPI_DCR2_WRAPSIZE_2 (0x4U << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */
15151
15152/**************** Bit definition for OCTOSPI_DCR3 register ******************/
15153#define OCTOSPI_DCR3_CSBOUND_Pos (16U)
15154#define OCTOSPI_DCR3_CSBOUND_Msk (0x1FU << OCTOSPI_DCR3_CSBOUND_Pos) /*!< 0x001F0000 */
15155#define OCTOSPI_DCR3_CSBOUND OCTOSPI_DCR3_CSBOUND_Msk /*!< CS Boundary */
15156
15157/***************** Bit definition for OCTOSPI_SR register *******************/
15158#define OCTOSPI_SR_TEF_Pos (0U)
15159#define OCTOSPI_SR_TEF_Msk (0x1U << OCTOSPI_SR_TEF_Pos) /*!< 0x00000001 */
15160#define OCTOSPI_SR_TEF OCTOSPI_SR_TEF_Msk /*!< Transfer Error Flag */
15161#define OCTOSPI_SR_TCF_Pos (1U)
15162#define OCTOSPI_SR_TCF_Msk (0x1U << OCTOSPI_SR_TCF_Pos) /*!< 0x00000002 */
15163#define OCTOSPI_SR_TCF OCTOSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
15164#define OCTOSPI_SR_FTF_Pos (2U)
15165#define OCTOSPI_SR_FTF_Msk (0x1U << OCTOSPI_SR_FTF_Pos) /*!< 0x00000004 */
15166#define OCTOSPI_SR_FTF OCTOSPI_SR_FTF_Msk /*!< FIFO Threshold Flag */
15167#define OCTOSPI_SR_SMF_Pos (3U)
15168#define OCTOSPI_SR_SMF_Msk (0x1U << OCTOSPI_SR_SMF_Pos) /*!< 0x00000008 */
15169#define OCTOSPI_SR_SMF OCTOSPI_SR_SMF_Msk /*!< Status Match Flag */
15170#define OCTOSPI_SR_TOF_Pos (4U)
15171#define OCTOSPI_SR_TOF_Msk (0x1U << OCTOSPI_SR_TOF_Pos) /*!< 0x00000010 */
15172#define OCTOSPI_SR_TOF OCTOSPI_SR_TOF_Msk /*!< Timeout Flag */
15173#define OCTOSPI_SR_BUSY_Pos (5U)
15174#define OCTOSPI_SR_BUSY_Msk (0x1U << OCTOSPI_SR_BUSY_Pos) /*!< 0x00000020 */
15175#define OCTOSPI_SR_BUSY OCTOSPI_SR_BUSY_Msk /*!< Busy */
15176#define OCTOSPI_SR_FLEVEL_Pos (8U)
15177#define OCTOSPI_SR_FLEVEL_Msk (0x3FU << OCTOSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
15178#define OCTOSPI_SR_FLEVEL OCTOSPI_SR_FLEVEL_Msk /*!< FIFO Level */
15179
15180/**************** Bit definition for OCTOSPI_FCR register *******************/
15181#define OCTOSPI_FCR_CTEF_Pos (0U)
15182#define OCTOSPI_FCR_CTEF_Msk (0x1U << OCTOSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
15183#define OCTOSPI_FCR_CTEF OCTOSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
15184#define OCTOSPI_FCR_CTCF_Pos (1U)
15185#define OCTOSPI_FCR_CTCF_Msk (0x1U << OCTOSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
15186#define OCTOSPI_FCR_CTCF OCTOSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
15187#define OCTOSPI_FCR_CSMF_Pos (3U)
15188#define OCTOSPI_FCR_CSMF_Msk (0x1U << OCTOSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
15189#define OCTOSPI_FCR_CSMF OCTOSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
15190#define OCTOSPI_FCR_TOF_Pos (8U)
15191#define OCTOSPI_FCR_TOF_Msk (0x1U << OCTOSPI_FCR_TOF_Pos) /*!< 0x00000100 */
15192#define OCTOSPI_FCR_TOF OCTOSPI_FCR_TOF_Msk /*!< Clear Timeout Flag */
15193
15194/**************** Bit definition for OCTOSPI_DLR register *******************/
15195#define OCTOSPI_DLR_DL_Pos (0U)
15196#define OCTOSPI_DLR_DL_Msk (0xFFFFFFFFU << OCTOSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
15197#define OCTOSPI_DLR_DL OCTOSPI_DLR_DL_Msk /*!< Data Length */
15198
15199/***************** Bit definition for OCTOSPI_AR register *******************/
15200#define OCTOSPI_AR_ADDRESS_Pos (0U)
15201#define OCTOSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << OCTOSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
15202#define OCTOSPI_AR_ADDRESS OCTOSPI_AR_ADDRESS_Msk /*!< Address */
15203
15204/***************** Bit definition for OCTOSPI_DR register *******************/
15205#define OCTOSPI_DR_DATA_Pos (0U)
15206#define OCTOSPI_DR_DATA_Msk (0xFFFFFFFFU << OCTOSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
15207#define OCTOSPI_DR_DATA OCTOSPI_DR_DATA_Msk /*!< Data */
15208
15209/*************** Bit definition for OCTOSPI_PSMKR register ******************/
15210#define OCTOSPI_PSMKR_MASK_Pos (0U)
15211#define OCTOSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << OCTOSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
15212#define OCTOSPI_PSMKR_MASK OCTOSPI_PSMKR_MASK_Msk /*!< Status mask */
15213
15214/*************** Bit definition for OCTOSPI_PSMAR register ******************/
15215#define OCTOSPI_PSMAR_MATCH_Pos (0U)
15216#define OCTOSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << OCTOSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
15217#define OCTOSPI_PSMAR_MATCH OCTOSPI_PSMAR_MATCH_Msk /*!< Status match */
15218
15219/**************** Bit definition for OCTOSPI_PIR register *******************/
15220#define OCTOSPI_PIR_INTERVAL_Pos (0U)
15221#define OCTOSPI_PIR_INTERVAL_Msk (0xFFFFU << OCTOSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
15222#define OCTOSPI_PIR_INTERVAL OCTOSPI_PIR_INTERVAL_Msk /*!< Polling Interval */
15223
15224/**************** Bit definition for OCTOSPI_CCR register *******************/
15225#define OCTOSPI_CCR_IMODE_Pos (0U)
15226#define OCTOSPI_CCR_IMODE_Msk (0x7U << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000007 */
15227#define OCTOSPI_CCR_IMODE OCTOSPI_CCR_IMODE_Msk /*!< Instruction Mode */
15228#define OCTOSPI_CCR_IMODE_0 (0x1U << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000001 */
15229#define OCTOSPI_CCR_IMODE_1 (0x2U << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000002 */
15230#define OCTOSPI_CCR_IMODE_2 (0x4U << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000004 */
15231#define OCTOSPI_CCR_IDTR_Pos (3U)
15232#define OCTOSPI_CCR_IDTR_Msk (0x1U << OCTOSPI_CCR_IDTR_Pos) /*!< 0x00000008 */
15233#define OCTOSPI_CCR_IDTR OCTOSPI_CCR_IDTR_Msk /*!< Instruction Double Transfer Rate */
15234#define OCTOSPI_CCR_ISIZE_Pos (4U)
15235#define OCTOSPI_CCR_ISIZE_Msk (0x3U << OCTOSPI_CCR_ISIZE_Pos) /*!< 0x00000030 */
15236#define OCTOSPI_CCR_ISIZE OCTOSPI_CCR_ISIZE_Msk /*!< Instruction Size */
15237#define OCTOSPI_CCR_ISIZE_0 (0x1U << OCTOSPI_CCR_ISIZE_Pos) /*!< 0x00000010 */
15238#define OCTOSPI_CCR_ISIZE_1 (0x2U << OCTOSPI_CCR_ISIZE_Pos) /*!< 0x00000020 */
15239#define OCTOSPI_CCR_ADMODE_Pos (8U)
15240#define OCTOSPI_CCR_ADMODE_Msk (0x7U << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000700 */
15241#define OCTOSPI_CCR_ADMODE OCTOSPI_CCR_ADMODE_Msk /*!< Address Mode */
15242#define OCTOSPI_CCR_ADMODE_0 (0x1U << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000100 */
15243#define OCTOSPI_CCR_ADMODE_1 (0x2U << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000200 */
15244#define OCTOSPI_CCR_ADMODE_2 (0x4U << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
15245#define OCTOSPI_CCR_ADDTR_Pos (11U)
15246#define OCTOSPI_CCR_ADDTR_Msk (0x1U << OCTOSPI_CCR_ADDTR_Pos) /*!< 0x00000800 */
15247#define OCTOSPI_CCR_ADDTR OCTOSPI_CCR_ADDTR_Msk /*!< Address Double Transfer Rate */
15248#define OCTOSPI_CCR_ADSIZE_Pos (12U)
15249#define OCTOSPI_CCR_ADSIZE_Msk (0x3U << OCTOSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
15250#define OCTOSPI_CCR_ADSIZE OCTOSPI_CCR_ADSIZE_Msk /*!< Address Size */
15251#define OCTOSPI_CCR_ADSIZE_0 (0x1U << OCTOSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
15252#define OCTOSPI_CCR_ADSIZE_1 (0x2U << OCTOSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
15253#define OCTOSPI_CCR_ABMODE_Pos (16U)
15254#define OCTOSPI_CCR_ABMODE_Msk (0x7U << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00070000 */
15255#define OCTOSPI_CCR_ABMODE OCTOSPI_CCR_ABMODE_Msk /*!< Alternate Bytes Mode */
15256#define OCTOSPI_CCR_ABMODE_0 (0x1U << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00010000 */
15257#define OCTOSPI_CCR_ABMODE_1 (0x2U << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00020000 */
15258#define OCTOSPI_CCR_ABMODE_2 (0x4U << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00040000 */
15259#define OCTOSPI_CCR_ABDTR_Pos (19U)
15260#define OCTOSPI_CCR_ABDTR_Msk (0x1U << OCTOSPI_CCR_ABDTR_Pos) /*!< 0x00080000 */
15261#define OCTOSPI_CCR_ABDTR OCTOSPI_CCR_ABDTR_Msk /*!< Alternate Bytes Double Transfer Rate */
15262#define OCTOSPI_CCR_ABSIZE_Pos (20U)
15263#define OCTOSPI_CCR_ABSIZE_Msk (0x3U << OCTOSPI_CCR_ABSIZE_Pos) /*!< 0x00300000 */
15264#define OCTOSPI_CCR_ABSIZE OCTOSPI_CCR_ABSIZE_Msk /*!< Alternate Bytes Size */
15265#define OCTOSPI_CCR_ABSIZE_0 (0x1U << OCTOSPI_CCR_ABSIZE_Pos) /*!< 0x00100000 */
15266#define OCTOSPI_CCR_ABSIZE_1 (0x2U << OCTOSPI_CCR_ABSIZE_Pos) /*!< 0x00200000 */
15267#define OCTOSPI_CCR_DMODE_Pos (24U)
15268#define OCTOSPI_CCR_DMODE_Msk (0x7U << OCTOSPI_CCR_DMODE_Pos) /*!< 0x07000000 */
15269#define OCTOSPI_CCR_DMODE OCTOSPI_CCR_DMODE_Msk /*!< Data Mode */
15270#define OCTOSPI_CCR_DMODE_0 (0x1U << OCTOSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
15271#define OCTOSPI_CCR_DMODE_1 (0x2U << OCTOSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
15272#define OCTOSPI_CCR_DMODE_2 (0x4U << OCTOSPI_CCR_DMODE_Pos) /*!< 0x04000000 */
15273#define OCTOSPI_CCR_DDTR_Pos (27U)
15274#define OCTOSPI_CCR_DDTR_Msk (0x1U << OCTOSPI_CCR_DDTR_Pos) /*!< 0x08000000 */
15275#define OCTOSPI_CCR_DDTR OCTOSPI_CCR_DDTR_Msk /*!< Data Double Transfer Rate */
15276#define OCTOSPI_CCR_DQSE_Pos (29U)
15277#define OCTOSPI_CCR_DQSE_Msk (0x1U << OCTOSPI_CCR_DQSE_Pos) /*!< 0x20000000 */
15278#define OCTOSPI_CCR_DQSE OCTOSPI_CCR_DQSE_Msk /*!< DQS Enable */
15279#define OCTOSPI_CCR_SIOO_Pos (31U)
15280#define OCTOSPI_CCR_SIOO_Msk (0x1U << OCTOSPI_CCR_SIOO_Pos) /*!< 0x80000000 */
15281#define OCTOSPI_CCR_SIOO OCTOSPI_CCR_SIOO_Msk /*!< Send Instruction Only Once Mode */
15282
15283/**************** Bit definition for OCTOSPI_TCR register *******************/
15284#define OCTOSPI_TCR_DCYC_Pos (0U)
15285#define OCTOSPI_TCR_DCYC_Msk (0x1FU << OCTOSPI_TCR_DCYC_Pos) /*!< 0x0000001F */
15286#define OCTOSPI_TCR_DCYC OCTOSPI_TCR_DCYC_Msk /*!< Number of Dummy Cycles */
15287#define OCTOSPI_TCR_DHQC_Pos (28U)
15288#define OCTOSPI_TCR_DHQC_Msk (0x1U << OCTOSPI_TCR_DHQC_Pos) /*!< 0x10000000 */
15289#define OCTOSPI_TCR_DHQC OCTOSPI_TCR_DHQC_Msk /*!< Delay Hold Quarter Cycle */
15290#define OCTOSPI_TCR_SSHIFT_Pos (30U)
15291#define OCTOSPI_TCR_SSHIFT_Msk (0x1U << OCTOSPI_TCR_SSHIFT_Pos) /*!< 0x40000000 */
15292#define OCTOSPI_TCR_SSHIFT OCTOSPI_TCR_SSHIFT_Msk /*!< Sample Shift */
15293
15294/***************** Bit definition for OCTOSPI_IR register *******************/
15295#define OCTOSPI_IR_INSTRUCTION_Pos (0U)
15296#define OCTOSPI_IR_INSTRUCTION_Msk (0xFFFFFFFFU << OCTOSPI_IR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
15297#define OCTOSPI_IR_INSTRUCTION OCTOSPI_IR_INSTRUCTION_Msk /*!< Instruction */
15298
15299/**************** Bit definition for OCTOSPI_ABR register *******************/
15300#define OCTOSPI_ABR_ALTERNATE_Pos (0U)
15301#define OCTOSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << OCTOSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
15302#define OCTOSPI_ABR_ALTERNATE OCTOSPI_ABR_ALTERNATE_Msk /*!< Alternate Bytes */
15303
15304/**************** Bit definition for OCTOSPI_LPTR register ******************/
15305#define OCTOSPI_LPTR_TIMEOUT_Pos (0U)
15306#define OCTOSPI_LPTR_TIMEOUT_Msk (0xFFFFU << OCTOSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
15307#define OCTOSPI_LPTR_TIMEOUT OCTOSPI_LPTR_TIMEOUT_Msk /*!< Timeout period */
15308
15309/**************** Bit definition for OCTOSPI_WCCR register ******************/
15310#define OCTOSPI_WCCR_IMODE_Pos (0U)
15311#define OCTOSPI_WCCR_IMODE_Msk (0x7U << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000007 */
15312#define OCTOSPI_WCCR_IMODE OCTOSPI_WCCR_IMODE_Msk /*!< Instruction Mode */
15313#define OCTOSPI_WCCR_IMODE_0 (0x1U << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000001 */
15314#define OCTOSPI_WCCR_IMODE_1 (0x2U << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000002 */
15315#define OCTOSPI_WCCR_IMODE_2 (0x4U << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000004 */
15316#define OCTOSPI_WCCR_IDTR_Pos (3U)
15317#define OCTOSPI_WCCR_IDTR_Msk (0x1U << OCTOSPI_WCCR_IDTR_Pos) /*!< 0x00000008 */
15318#define OCTOSPI_WCCR_IDTR OCTOSPI_WCCR_IDTR_Msk /*!< Instruction Double Transfer Rate */
15319#define OCTOSPI_WCCR_ISIZE_Pos (4U)
15320#define OCTOSPI_WCCR_ISIZE_Msk (0x3U << OCTOSPI_WCCR_ISIZE_Pos) /*!< 0x00000030 */
15321#define OCTOSPI_WCCR_ISIZE OCTOSPI_WCCR_ISIZE_Msk /*!< Instruction Size */
15322#define OCTOSPI_WCCR_ISIZE_0 (0x1U << OCTOSPI_WCCR_ISIZE_Pos) /*!< 0x00000010 */
15323#define OCTOSPI_WCCR_ISIZE_1 (0x2U << OCTOSPI_WCCR_ISIZE_Pos) /*!< 0x00000020 */
15324#define OCTOSPI_WCCR_ADMODE_Pos (8U)
15325#define OCTOSPI_WCCR_ADMODE_Msk (0x7U << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000700 */
15326#define OCTOSPI_WCCR_ADMODE OCTOSPI_WCCR_ADMODE_Msk /*!< Address Mode */
15327#define OCTOSPI_WCCR_ADMODE_0 (0x1U << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000100 */
15328#define OCTOSPI_WCCR_ADMODE_1 (0x2U << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000200 */
15329#define OCTOSPI_WCCR_ADMODE_2 (0x4U << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000400 */
15330#define OCTOSPI_WCCR_ADDTR_Pos (11U)
15331#define OCTOSPI_WCCR_ADDTR_Msk (0x1U << OCTOSPI_WCCR_ADDTR_Pos) /*!< 0x00000800 */
15332#define OCTOSPI_WCCR_ADDTR OCTOSPI_WCCR_ADDTR_Msk /*!< Address Double Transfer Rate */
15333#define OCTOSPI_WCCR_ADSIZE_Pos (12U)
15334#define OCTOSPI_WCCR_ADSIZE_Msk (0x3U << OCTOSPI_WCCR_ADSIZE_Pos) /*!< 0x00003000 */
15335#define OCTOSPI_WCCR_ADSIZE OCTOSPI_WCCR_ADSIZE_Msk /*!< Address Size */
15336#define OCTOSPI_WCCR_ADSIZE_0 (0x1U << OCTOSPI_WCCR_ADSIZE_Pos) /*!< 0x00001000 */
15337#define OCTOSPI_WCCR_ADSIZE_1 (0x2U << OCTOSPI_WCCR_ADSIZE_Pos) /*!< 0x00002000 */
15338#define OCTOSPI_WCCR_ABMODE_Pos (16U)
15339#define OCTOSPI_WCCR_ABMODE_Msk (0x7U << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00070000 */
15340#define OCTOSPI_WCCR_ABMODE OCTOSPI_WCCR_ABMODE_Msk /*!< Alternate Bytes Mode */
15341#define OCTOSPI_WCCR_ABMODE_0 (0x1U << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00010000 */
15342#define OCTOSPI_WCCR_ABMODE_1 (0x2U << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00020000 */
15343#define OCTOSPI_WCCR_ABMODE_2 (0x4U << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00040000 */
15344#define OCTOSPI_WCCR_ABDTR_Pos (19U)
15345#define OCTOSPI_WCCR_ABDTR_Msk (0x1U << OCTOSPI_WCCR_ABDTR_Pos) /*!< 0x00080000 */
15346#define OCTOSPI_WCCR_ABDTR OCTOSPI_WCCR_ABDTR_Msk /*!< Alternate Bytes Double Transfer Rate */
15347#define OCTOSPI_WCCR_ABSIZE_Pos (20U)
15348#define OCTOSPI_WCCR_ABSIZE_Msk (0x3U << OCTOSPI_WCCR_ABSIZE_Pos) /*!< 0x00300000 */
15349#define OCTOSPI_WCCR_ABSIZE OCTOSPI_WCCR_ABSIZE_Msk /*!< Alternate Bytes Size */
15350#define OCTOSPI_WCCR_ABSIZE_0 (0x1U << OCTOSPI_WCCR_ABSIZE_Pos) /*!< 0x00100000 */
15351#define OCTOSPI_WCCR_ABSIZE_1 (0x2U << OCTOSPI_WCCR_ABSIZE_Pos) /*!< 0x00200000 */
15352#define OCTOSPI_WCCR_DMODE_Pos (24U)
15353#define OCTOSPI_WCCR_DMODE_Msk (0x7U << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x07000000 */
15354#define OCTOSPI_WCCR_DMODE OCTOSPI_WCCR_DMODE_Msk /*!< Data Mode */
15355#define OCTOSPI_WCCR_DMODE_0 (0x1U << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x01000000 */
15356#define OCTOSPI_WCCR_DMODE_1 (0x2U << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x02000000 */
15357#define OCTOSPI_WCCR_DMODE_2 (0x4U << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x04000000 */
15358#define OCTOSPI_WCCR_DDTR_Pos (27U)
15359#define OCTOSPI_WCCR_DDTR_Msk (0x1U << OCTOSPI_WCCR_DDTR_Pos) /*!< 0x08000000 */
15360#define OCTOSPI_WCCR_DDTR OCTOSPI_WCCR_DDTR_Msk /*!< Data Double Transfer Rate */
15361#define OCTOSPI_WCCR_DQSE_Pos (29U)
15362#define OCTOSPI_WCCR_DQSE_Msk (0x1U << OCTOSPI_WCCR_DQSE_Pos) /*!< 0x20000000 */
15363#define OCTOSPI_WCCR_DQSE OCTOSPI_WCCR_DQSE_Msk /*!< DQS Enable */
15364#define OCTOSPI_WCCR_SIOO_Pos (31U)
15365#define OCTOSPI_WCCR_SIOO_Msk (0x1U << OCTOSPI_WCCR_SIOO_Pos) /*!< 0x80000000 */
15366#define OCTOSPI_WCCR_SIOO OCTOSPI_WCCR_SIOO_Msk /*!< Send Instruction Only Once Mode */
15367
15368/**************** Bit definition for OCTOSPI_WTCR register ******************/
15369#define OCTOSPI_WTCR_DCYC_Pos (0U)
15370#define OCTOSPI_WTCR_DCYC_Msk (0x1FU << OCTOSPI_WTCR_DCYC_Pos) /*!< 0x0000001F */
15371#define OCTOSPI_WTCR_DCYC OCTOSPI_WTCR_DCYC_Msk /*!< Number of Dummy Cycles */
15372
15373/**************** Bit definition for OCTOSPI_WIR register *******************/
15374#define OCTOSPI_WIR_INSTRUCTION_Pos (0U)
15375#define OCTOSPI_WIR_INSTRUCTION_Msk (0xFFFFFFFFU << OCTOSPI_WIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
15376#define OCTOSPI_WIR_INSTRUCTION OCTOSPI_WIR_INSTRUCTION_Msk /*!< Instruction */
15377
15378/**************** Bit definition for OCTOSPI_WABR register ******************/
15379#define OCTOSPI_WABR_ALTERNATE_Pos (0U)
15380#define OCTOSPI_WABR_ALTERNATE_Msk (0xFFFFFFFFU << OCTOSPI_WABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
15381#define OCTOSPI_WABR_ALTERNATE OCTOSPI_WABR_ALTERNATE_Msk /*!< Alternate Bytes */
15382
15383/**************** Bit definition for OCTOSPI_HLCR register ******************/
15384#define OCTOSPI_HLCR_LM_Pos (0U)
15385#define OCTOSPI_HLCR_LM_Msk (0x1U << OCTOSPI_HLCR_LM_Pos) /*!< 0x00000001 */
15386#define OCTOSPI_HLCR_LM OCTOSPI_HLCR_LM_Msk /*!< Latency Mode */
15387#define OCTOSPI_HLCR_WZL_Pos (1U)
15388#define OCTOSPI_HLCR_WZL_Msk (0x1U << OCTOSPI_HLCR_WZL_Pos) /*!< 0x00000002 */
15389#define OCTOSPI_HLCR_WZL OCTOSPI_HLCR_WZL_Msk /*!< Write Zero Latency */
15390#define OCTOSPI_HLCR_TACC_Pos (8U)
15391#define OCTOSPI_HLCR_TACC_Msk (0xFFU << OCTOSPI_HLCR_TACC_Pos) /*!< 0x0000FF00 */
15392#define OCTOSPI_HLCR_TACC OCTOSPI_HLCR_TACC_Msk /*!< Access Time */
15393#define OCTOSPI_HLCR_TRWR_Pos (16U)
15394#define OCTOSPI_HLCR_TRWR_Msk (0xFFU << OCTOSPI_HLCR_TRWR_Pos) /*!< 0x00FF0000 */
15395#define OCTOSPI_HLCR_TRWR OCTOSPI_HLCR_TRWR_Msk /*!< Read Write Recovery Time */
15396
15397/******************************************************************************/
15398/* */
15399/* OCTOSPIM */
15400/* */
15401/******************************************************************************/
15402/*************** Bit definition for OCTOSPIM_PCR register *******************/
15403#define OCTOSPIM_PCR_CLKEN_Pos (0U)
15404#define OCTOSPIM_PCR_CLKEN_Msk (0x1U << OCTOSPIM_PCR_CLKEN_Pos) /*!< 0x00000001 */
15405#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */
15406#define OCTOSPIM_PCR_CLKSRC_Pos (1U)
15407#define OCTOSPIM_PCR_CLKSRC_Msk (0x1U << OCTOSPIM_PCR_CLKSRC_Pos) /*!< 0x00000002 */
15408#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */
15409#define OCTOSPIM_PCR_DQSEN_Pos (4U)
15410#define OCTOSPIM_PCR_DQSEN_Msk (0x1U << OCTOSPIM_PCR_DQSEN_Pos) /*!< 0x00000010 */
15411#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */
15412#define OCTOSPIM_PCR_DQSSRC_Pos (5U)
15413#define OCTOSPIM_PCR_DQSSRC_Msk (0x1U << OCTOSPIM_PCR_DQSSRC_Pos) /*!< 0x00000020 */
15414#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */
15415#define OCTOSPIM_PCR_NCSEN_Pos (8U)
15416#define OCTOSPIM_PCR_NCSEN_Msk (0x1U << OCTOSPIM_PCR_NCSEN_Pos) /*!< 0x00000100 */
15417#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */
15418#define OCTOSPIM_PCR_NCSSRC_Pos (9U)
15419#define OCTOSPIM_PCR_NCSSRC_Msk (0x1U << OCTOSPIM_PCR_NCSSRC_Pos) /*!< 0x00000200 */
15420#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */
15421#define OCTOSPIM_PCR_IOLEN_Pos (16U)
15422#define OCTOSPIM_PCR_IOLEN_Msk (0x1U << OCTOSPIM_PCR_IOLEN_Pos) /*!< 0x00010000 */
15423#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */
15424#define OCTOSPIM_PCR_IOLSRC_Pos (17U)
15425#define OCTOSPIM_PCR_IOLSRC_Msk (0x3U << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00060000 */
15426#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */
15427#define OCTOSPIM_PCR_IOLSRC_0 (0x1U << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00020000 */
15428#define OCTOSPIM_PCR_IOLSRC_1 (0x2U << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00040000 */
15429#define OCTOSPIM_PCR_IOHEN_Pos (24U)
15430#define OCTOSPIM_PCR_IOHEN_Msk (0x1U << OCTOSPIM_PCR_IOHEN_Pos) /*!< 0x01000000 */
15431#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */
15432#define OCTOSPIM_PCR_IOHSRC_Pos (25U)
15433#define OCTOSPIM_PCR_IOHSRC_Msk (0x3U << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x06000000 */
15434#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */
15435#define OCTOSPIM_PCR_IOHSRC_0 (0x1U << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x02000000 */
15436#define OCTOSPIM_PCR_IOHSRC_1 (0x2U << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x04000000 */
15437
15438/******************************************************************************/
15439/* */
15440/* SYSCFG */
15441/* */
15442/******************************************************************************/
15443/****************** Bit definition for SYSCFG_MEMRMP register ***************/
15444#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
15445#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
15446#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
15447#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
15448#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
15449#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
15450
15451#define SYSCFG_MEMRMP_FB_MODE_Pos (8U)
15452#define SYSCFG_MEMRMP_FB_MODE_Msk (0x1U << SYSCFG_MEMRMP_FB_MODE_Pos) /*!< 0x00000100 */
15453#define SYSCFG_MEMRMP_FB_MODE SYSCFG_MEMRMP_FB_MODE_Msk /*!< Flash Bank mode selection */
15454
15455/****************** Bit definition for SYSCFG_CFGR1 register ******************/
15456#define SYSCFG_CFGR1_FWDIS_Pos (0U)
15457#define SYSCFG_CFGR1_FWDIS_Msk (0x1U << SYSCFG_CFGR1_FWDIS_Pos) /*!< 0x00000001 */
15458#define SYSCFG_CFGR1_FWDIS SYSCFG_CFGR1_FWDIS_Msk /*!< FIREWALL access enable*/
15459#define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
15460#define SYSCFG_CFGR1_BOOSTEN_Msk (0x1U << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
15461#define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
15462#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
15463#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
15464#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
15465#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
15466#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
15467#define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
15468#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
15469#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
15470#define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
15471#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
15472#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
15473#define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
15474#define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
15475#define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
15476#define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
15477#define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
15478#define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
15479#define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
15480#define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
15481#define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */
15482#define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
15483#define SYSCFG_CFGR1_I2C4_FMP_Pos (23U)
15484#define SYSCFG_CFGR1_I2C4_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C4_FMP_Pos) /*!< 0x00800000 */
15485#define SYSCFG_CFGR1_I2C4_FMP SYSCFG_CFGR1_I2C4_FMP_Msk /*!< I2C4 Fast mode plus */
15486#define SYSCFG_CFGR1_FPU_IE_0 (0x04000000U) /*!< Invalid operation Interrupt enable */
15487#define SYSCFG_CFGR1_FPU_IE_1 (0x08000000U) /*!< Divide-by-zero Interrupt enable */
15488#define SYSCFG_CFGR1_FPU_IE_2 (0x10000000U) /*!< Underflow Interrupt enable */
15489#define SYSCFG_CFGR1_FPU_IE_3 (0x20000000U) /*!< Overflow Interrupt enable */
15490#define SYSCFG_CFGR1_FPU_IE_4 (0x40000000U) /*!< Input denormal Interrupt enable */
15491#define SYSCFG_CFGR1_FPU_IE_5 (0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */
15492
15493/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
15494#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
15495#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
15496#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
15497#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
15498#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
15499#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
15500#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
15501#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
15502#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
15503#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
15504#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
15505#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
15506
15507/**
15508 * @brief EXTI0 configuration
15509 */
15510#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!<PA[0] pin */
15511#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
15512#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
15513#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
15514#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
15515#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
15516#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
15517#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */
15518#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */
15519
15520/**
15521 * @brief EXTI1 configuration
15522 */
15523#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!<PA[1] pin */
15524#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
15525#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
15526#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
15527#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
15528#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
15529#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
15530#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */
15531#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */
15532
15533/**
15534 * @brief EXTI2 configuration
15535 */
15536#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!<PA[2] pin */
15537#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
15538#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
15539#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
15540#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
15541#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
15542#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
15543#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */
15544#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */
15545
15546/**
15547 * @brief EXTI3 configuration
15548 */
15549#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!<PA[3] pin */
15550#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
15551#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
15552#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
15553#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
15554#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
15555#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
15556#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */
15557#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */
15558
15559/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
15560#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
15561#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
15562#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
15563#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
15564#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
15565#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
15566#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
15567#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
15568#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
15569#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
15570#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
15571#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
15572/**
15573 * @brief EXTI4 configuration
15574 */
15575#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!<PA[4] pin */
15576#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
15577#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
15578#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
15579#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
15580#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
15581#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
15582#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */
15583#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */
15584
15585/**
15586 * @brief EXTI5 configuration
15587 */
15588#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!<PA[5] pin */
15589#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
15590#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
15591#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
15592#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
15593#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
15594#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
15595#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */
15596#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */
15597
15598/**
15599 * @brief EXTI6 configuration
15600 */
15601#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!<PA[6] pin */
15602#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
15603#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
15604#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
15605#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
15606#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
15607#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
15608#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */
15609#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */
15610
15611/**
15612 * @brief EXTI7 configuration
15613 */
15614#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!<PA[7] pin */
15615#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
15616#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
15617#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
15618#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
15619#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
15620#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
15621#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */
15622#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */
15623
15624/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
15625#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
15626#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
15627#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
15628#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
15629#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
15630#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
15631#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
15632#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
15633#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
15634#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
15635#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
15636#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
15637
15638/**
15639 * @brief EXTI8 configuration
15640 */
15641#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!<PA[8] pin */
15642#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
15643#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
15644#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
15645#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
15646#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
15647#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
15648#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */
15649#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */
15650
15651/**
15652 * @brief EXTI9 configuration
15653 */
15654#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!<PA[9] pin */
15655#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
15656#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
15657#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
15658#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
15659#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
15660#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
15661#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */
15662#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */
15663
15664/**
15665 * @brief EXTI10 configuration
15666 */
15667#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!<PA[10] pin */
15668#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
15669#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
15670#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
15671#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
15672#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
15673#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */
15674#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */
15675#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */
15676
15677/**
15678 * @brief EXTI11 configuration
15679 */
15680#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!<PA[11] pin */
15681#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
15682#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
15683#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
15684#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
15685#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
15686#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */
15687#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */
15688#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */
15689
15690/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
15691#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
15692#define SYSCFG_EXTICR4_EXTI12_Msk (0x7U << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
15693#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
15694#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
15695#define SYSCFG_EXTICR4_EXTI13_Msk (0x7U << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */
15696#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
15697#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
15698#define SYSCFG_EXTICR4_EXTI14_Msk (0x7U << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */
15699#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
15700#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
15701#define SYSCFG_EXTICR4_EXTI15_Msk (0x7U << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */
15702#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
15703
15704/**
15705 * @brief EXTI12 configuration
15706 */
15707#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!<PA[12] pin */
15708#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
15709#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
15710#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
15711#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
15712#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
15713#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */
15714#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */
15715
15716/**
15717 * @brief EXTI13 configuration
15718 */
15719#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!<PA[13] pin */
15720#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
15721#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
15722#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
15723#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
15724#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
15725#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */
15726#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */
15727
15728/**
15729 * @brief EXTI14 configuration
15730 */
15731#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!<PA[14] pin */
15732#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
15733#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
15734#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
15735#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
15736#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
15737#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */
15738#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */
15739
15740/**
15741 * @brief EXTI15 configuration
15742 */
15743#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!<PA[15] pin */
15744#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
15745#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
15746#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
15747#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
15748#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
15749#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */
15750#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */
15751
15752/****************** Bit definition for SYSCFG_SCSR register ****************/
15753#define SYSCFG_SCSR_SRAM2ER_Pos (0U)
15754#define SYSCFG_SCSR_SRAM2ER_Msk (0x1U << SYSCFG_SCSR_SRAM2ER_Pos) /*!< 0x00000001 */
15755#define SYSCFG_SCSR_SRAM2ER SYSCFG_SCSR_SRAM2ER_Msk /*!< SRAM2 Erase Request */
15756#define SYSCFG_SCSR_SRAM2BSY_Pos (1U)
15757#define SYSCFG_SCSR_SRAM2BSY_Msk (0x1U << SYSCFG_SCSR_SRAM2BSY_Pos) /*!< 0x00000002 */
15758#define SYSCFG_SCSR_SRAM2BSY SYSCFG_SCSR_SRAM2BSY_Msk /*!< SRAM2 Erase Ongoing */
15759
15760/****************** Bit definition for SYSCFG_CFGR2 register ****************/
15761#define SYSCFG_CFGR2_CLL_Pos (0U)
15762#define SYSCFG_CFGR2_CLL_Msk (0x1U << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
15763#define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Core Lockup Lock */
15764#define SYSCFG_CFGR2_SPL_Pos (1U)
15765#define SYSCFG_CFGR2_SPL_Msk (0x1U << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
15766#define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM Parity Lock*/
15767#define SYSCFG_CFGR2_PVDL_Pos (2U)
15768#define SYSCFG_CFGR2_PVDL_Msk (0x1U << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */
15769#define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */
15770#define SYSCFG_CFGR2_ECCL_Pos (3U)
15771#define SYSCFG_CFGR2_ECCL_Msk (0x1U << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
15772#define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock*/
15773#define SYSCFG_CFGR2_SPF_Pos (8U)
15774#define SYSCFG_CFGR2_SPF_Msk (0x1U << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
15775#define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity Flag */
15776
15777/****************** Bit definition for SYSCFG_SWPR register ****************/
15778#define SYSCFG_SWPR_PAGE0_Pos (0U)
15779#define SYSCFG_SWPR_PAGE0_Msk (0x1U << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
15780#define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk /*!< SRAM2 Write protection page 0 */
15781#define SYSCFG_SWPR_PAGE1_Pos (1U)
15782#define SYSCFG_SWPR_PAGE1_Msk (0x1U << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
15783#define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk /*!< SRAM2 Write protection page 1 */
15784#define SYSCFG_SWPR_PAGE2_Pos (2U)
15785#define SYSCFG_SWPR_PAGE2_Msk (0x1U << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
15786#define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk /*!< SRAM2 Write protection page 2 */
15787#define SYSCFG_SWPR_PAGE3_Pos (3U)
15788#define SYSCFG_SWPR_PAGE3_Msk (0x1U << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
15789#define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk /*!< SRAM2 Write protection page 3 */
15790#define SYSCFG_SWPR_PAGE4_Pos (4U)
15791#define SYSCFG_SWPR_PAGE4_Msk (0x1U << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
15792#define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk /*!< SRAM2 Write protection page 4 */
15793#define SYSCFG_SWPR_PAGE5_Pos (5U)
15794#define SYSCFG_SWPR_PAGE5_Msk (0x1U << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
15795#define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk /*!< SRAM2 Write protection page 5 */
15796#define SYSCFG_SWPR_PAGE6_Pos (6U)
15797#define SYSCFG_SWPR_PAGE6_Msk (0x1U << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
15798#define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk /*!< SRAM2 Write protection page 6 */
15799#define SYSCFG_SWPR_PAGE7_Pos (7U)
15800#define SYSCFG_SWPR_PAGE7_Msk (0x1U << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
15801#define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk /*!< SRAM2 Write protection page 7 */
15802#define SYSCFG_SWPR_PAGE8_Pos (8U)
15803#define SYSCFG_SWPR_PAGE8_Msk (0x1U << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
15804#define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk /*!< SRAM2 Write protection page 8 */
15805#define SYSCFG_SWPR_PAGE9_Pos (9U)
15806#define SYSCFG_SWPR_PAGE9_Msk (0x1U << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
15807#define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk /*!< SRAM2 Write protection page 9 */
15808#define SYSCFG_SWPR_PAGE10_Pos (10U)
15809#define SYSCFG_SWPR_PAGE10_Msk (0x1U << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
15810#define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk /*!< SRAM2 Write protection page 10*/
15811#define SYSCFG_SWPR_PAGE11_Pos (11U)
15812#define SYSCFG_SWPR_PAGE11_Msk (0x1U << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
15813#define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk /*!< SRAM2 Write protection page 11*/
15814#define SYSCFG_SWPR_PAGE12_Pos (12U)
15815#define SYSCFG_SWPR_PAGE12_Msk (0x1U << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
15816#define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk /*!< SRAM2 Write protection page 12*/
15817#define SYSCFG_SWPR_PAGE13_Pos (13U)
15818#define SYSCFG_SWPR_PAGE13_Msk (0x1U << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
15819#define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk /*!< SRAM2 Write protection page 13*/
15820#define SYSCFG_SWPR_PAGE14_Pos (14U)
15821#define SYSCFG_SWPR_PAGE14_Msk (0x1U << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
15822#define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk /*!< SRAM2 Write protection page 14*/
15823#define SYSCFG_SWPR_PAGE15_Pos (15U)
15824#define SYSCFG_SWPR_PAGE15_Msk (0x1U << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
15825#define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk /*!< SRAM2 Write protection page 15*/
15826#define SYSCFG_SWPR_PAGE16_Pos (16U)
15827#define SYSCFG_SWPR_PAGE16_Msk (0x1U << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
15828#define SYSCFG_SWPR_PAGE16 SYSCFG_SWPR_PAGE16_Msk /*!< SRAM2 Write protection page 16*/
15829#define SYSCFG_SWPR_PAGE17_Pos (17U)
15830#define SYSCFG_SWPR_PAGE17_Msk (0x1U << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
15831#define SYSCFG_SWPR_PAGE17 SYSCFG_SWPR_PAGE17_Msk /*!< SRAM2 Write protection page 17*/
15832#define SYSCFG_SWPR_PAGE18_Pos (18U)
15833#define SYSCFG_SWPR_PAGE18_Msk (0x1U << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
15834#define SYSCFG_SWPR_PAGE18 SYSCFG_SWPR_PAGE18_Msk /*!< SRAM2 Write protection page 18*/
15835#define SYSCFG_SWPR_PAGE19_Pos (19U)
15836#define SYSCFG_SWPR_PAGE19_Msk (0x1U << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
15837#define SYSCFG_SWPR_PAGE19 SYSCFG_SWPR_PAGE19_Msk /*!< SRAM2 Write protection page 19*/
15838#define SYSCFG_SWPR_PAGE20_Pos (20U)
15839#define SYSCFG_SWPR_PAGE20_Msk (0x1U << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
15840#define SYSCFG_SWPR_PAGE20 SYSCFG_SWPR_PAGE20_Msk /*!< SRAM2 Write protection page 20*/
15841#define SYSCFG_SWPR_PAGE21_Pos (21U)
15842#define SYSCFG_SWPR_PAGE21_Msk (0x1U << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
15843#define SYSCFG_SWPR_PAGE21 SYSCFG_SWPR_PAGE21_Msk /*!< SRAM2 Write protection page 21*/
15844#define SYSCFG_SWPR_PAGE22_Pos (22U)
15845#define SYSCFG_SWPR_PAGE22_Msk (0x1U << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
15846#define SYSCFG_SWPR_PAGE22 SYSCFG_SWPR_PAGE22_Msk /*!< SRAM2 Write protection page 22*/
15847#define SYSCFG_SWPR_PAGE23_Pos (23U)
15848#define SYSCFG_SWPR_PAGE23_Msk (0x1U << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
15849#define SYSCFG_SWPR_PAGE23 SYSCFG_SWPR_PAGE23_Msk /*!< SRAM2 Write protection page 23*/
15850#define SYSCFG_SWPR_PAGE24_Pos (24U)
15851#define SYSCFG_SWPR_PAGE24_Msk (0x1U << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
15852#define SYSCFG_SWPR_PAGE24 SYSCFG_SWPR_PAGE24_Msk /*!< SRAM2 Write protection page 24*/
15853#define SYSCFG_SWPR_PAGE25_Pos (25U)
15854#define SYSCFG_SWPR_PAGE25_Msk (0x1U << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
15855#define SYSCFG_SWPR_PAGE25 SYSCFG_SWPR_PAGE25_Msk /*!< SRAM2 Write protection page 25*/
15856#define SYSCFG_SWPR_PAGE26_Pos (26U)
15857#define SYSCFG_SWPR_PAGE26_Msk (0x1U << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
15858#define SYSCFG_SWPR_PAGE26 SYSCFG_SWPR_PAGE26_Msk /*!< SRAM2 Write protection page 26*/
15859#define SYSCFG_SWPR_PAGE27_Pos (27U)
15860#define SYSCFG_SWPR_PAGE27_Msk (0x1U << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
15861#define SYSCFG_SWPR_PAGE27 SYSCFG_SWPR_PAGE27_Msk /*!< SRAM2 Write protection page 27*/
15862#define SYSCFG_SWPR_PAGE28_Pos (28U)
15863#define SYSCFG_SWPR_PAGE28_Msk (0x1U << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
15864#define SYSCFG_SWPR_PAGE28 SYSCFG_SWPR_PAGE28_Msk /*!< SRAM2 Write protection page 28*/
15865#define SYSCFG_SWPR_PAGE29_Pos (29U)
15866#define SYSCFG_SWPR_PAGE29_Msk (0x1U << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
15867#define SYSCFG_SWPR_PAGE29 SYSCFG_SWPR_PAGE29_Msk /*!< SRAM2 Write protection page 29*/
15868#define SYSCFG_SWPR_PAGE30_Pos (30U)
15869#define SYSCFG_SWPR_PAGE30_Msk (0x1U << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
15870#define SYSCFG_SWPR_PAGE30 SYSCFG_SWPR_PAGE30_Msk /*!< SRAM2 Write protection page 30*/
15871#define SYSCFG_SWPR_PAGE31_Pos (31U)
15872#define SYSCFG_SWPR_PAGE31_Msk (0x1U << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
15873#define SYSCFG_SWPR_PAGE31 SYSCFG_SWPR_PAGE31_Msk /*!< SRAM2 Write protection page 31*/
15874
15875/****************** Bit definition for SYSCFG_SWPR2 register ***************/
15876#define SYSCFG_SWPR2_PAGE32_Pos (0U)
15877#define SYSCFG_SWPR2_PAGE32_Msk (0x1U << SYSCFG_SWPR2_PAGE32_Pos) /*!< 0x00000001 */
15878#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2 Write protection page 32*/
15879#define SYSCFG_SWPR2_PAGE33_Pos (1U)
15880#define SYSCFG_SWPR2_PAGE33_Msk (0x1U << SYSCFG_SWPR2_PAGE33_Pos) /*!< 0x00000002 */
15881#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2 Write protection page 33*/
15882#define SYSCFG_SWPR2_PAGE34_Pos (2U)
15883#define SYSCFG_SWPR2_PAGE34_Msk (0x1U << SYSCFG_SWPR2_PAGE34_Pos) /*!< 0x00000004 */
15884#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2 Write protection page 34*/
15885#define SYSCFG_SWPR2_PAGE35_Pos (3U)
15886#define SYSCFG_SWPR2_PAGE35_Msk (0x1U << SYSCFG_SWPR2_PAGE35_Pos) /*!< 0x00000008 */
15887#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2 Write protection page 35*/
15888#define SYSCFG_SWPR2_PAGE36_Pos (4U)
15889#define SYSCFG_SWPR2_PAGE36_Msk (0x1U << SYSCFG_SWPR2_PAGE36_Pos) /*!< 0x00000010 */
15890#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2 Write protection page 36*/
15891#define SYSCFG_SWPR2_PAGE37_Pos (5U)
15892#define SYSCFG_SWPR2_PAGE37_Msk (0x1U << SYSCFG_SWPR2_PAGE37_Pos) /*!< 0x00000020 */
15893#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2 Write protection page 37*/
15894#define SYSCFG_SWPR2_PAGE38_Pos (6U)
15895#define SYSCFG_SWPR2_PAGE38_Msk (0x1U << SYSCFG_SWPR2_PAGE38_Pos) /*!< 0x00000040 */
15896#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2 Write protection page 38*/
15897#define SYSCFG_SWPR2_PAGE39_Pos (7U)
15898#define SYSCFG_SWPR2_PAGE39_Msk (0x1U << SYSCFG_SWPR2_PAGE39_Pos) /*!< 0x00000080 */
15899#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2 Write protection page 39*/
15900#define SYSCFG_SWPR2_PAGE40_Pos (8U)
15901#define SYSCFG_SWPR2_PAGE40_Msk (0x1U << SYSCFG_SWPR2_PAGE40_Pos) /*!< 0x00000100 */
15902#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2 Write protection page 40*/
15903#define SYSCFG_SWPR2_PAGE41_Pos (9U)
15904#define SYSCFG_SWPR2_PAGE41_Msk (0x1U << SYSCFG_SWPR2_PAGE41_Pos) /*!< 0x00000200 */
15905#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2 Write protection page 41*/
15906#define SYSCFG_SWPR2_PAGE42_Pos (10U)
15907#define SYSCFG_SWPR2_PAGE42_Msk (0x1U << SYSCFG_SWPR2_PAGE42_Pos) /*!< 0x00000400 */
15908#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2 Write protection page 42*/
15909#define SYSCFG_SWPR2_PAGE43_Pos (11U)
15910#define SYSCFG_SWPR2_PAGE43_Msk (0x1U << SYSCFG_SWPR2_PAGE43_Pos) /*!< 0x00000800 */
15911#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2 Write protection page 43*/
15912#define SYSCFG_SWPR2_PAGE44_Pos (12U)
15913#define SYSCFG_SWPR2_PAGE44_Msk (0x1U << SYSCFG_SWPR2_PAGE44_Pos) /*!< 0x00001000 */
15914#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2 Write protection page 44*/
15915#define SYSCFG_SWPR2_PAGE45_Pos (13U)
15916#define SYSCFG_SWPR2_PAGE45_Msk (0x1U << SYSCFG_SWPR2_PAGE45_Pos) /*!< 0x00002000 */
15917#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2 Write protection page 45*/
15918#define SYSCFG_SWPR2_PAGE46_Pos (14U)
15919#define SYSCFG_SWPR2_PAGE46_Msk (0x1U << SYSCFG_SWPR2_PAGE46_Pos) /*!< 0x00004000 */
15920#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2 Write protection page 46*/
15921#define SYSCFG_SWPR2_PAGE47_Pos (15U)
15922#define SYSCFG_SWPR2_PAGE47_Msk (0x1U << SYSCFG_SWPR2_PAGE47_Pos) /*!< 0x00008000 */
15923#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2 Write protection page 47*/
15924#define SYSCFG_SWPR2_PAGE48_Pos (16U)
15925#define SYSCFG_SWPR2_PAGE48_Msk (0x1U << SYSCFG_SWPR2_PAGE48_Pos) /*!< 0x00010000 */
15926#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2 Write protection page 48*/
15927#define SYSCFG_SWPR2_PAGE49_Pos (17U)
15928#define SYSCFG_SWPR2_PAGE49_Msk (0x1U << SYSCFG_SWPR2_PAGE49_Pos) /*!< 0x00020000 */
15929#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2 Write protection page 49*/
15930#define SYSCFG_SWPR2_PAGE50_Pos (18U)
15931#define SYSCFG_SWPR2_PAGE50_Msk (0x1U << SYSCFG_SWPR2_PAGE50_Pos) /*!< 0x00040000 */
15932#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2 Write protection page 50*/
15933#define SYSCFG_SWPR2_PAGE51_Pos (19U)
15934#define SYSCFG_SWPR2_PAGE51_Msk (0x1U << SYSCFG_SWPR2_PAGE51_Pos) /*!< 0x00080000 */
15935#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2 Write protection page 51*/
15936#define SYSCFG_SWPR2_PAGE52_Pos (20U)
15937#define SYSCFG_SWPR2_PAGE52_Msk (0x1U << SYSCFG_SWPR2_PAGE52_Pos) /*!< 0x00100000 */
15938#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2 Write protection page 52*/
15939#define SYSCFG_SWPR2_PAGE53_Pos (21U)
15940#define SYSCFG_SWPR2_PAGE53_Msk (0x1U << SYSCFG_SWPR2_PAGE53_Pos) /*!< 0x00200000 */
15941#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2 Write protection page 53*/
15942#define SYSCFG_SWPR2_PAGE54_Pos (22U)
15943#define SYSCFG_SWPR2_PAGE54_Msk (0x1U << SYSCFG_SWPR2_PAGE54_Pos) /*!< 0x00400000 */
15944#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2 Write protection page 54*/
15945#define SYSCFG_SWPR2_PAGE55_Pos (23U)
15946#define SYSCFG_SWPR2_PAGE55_Msk (0x1U << SYSCFG_SWPR2_PAGE55_Pos) /*!< 0x00800000 */
15947#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2 Write protection page 55*/
15948#define SYSCFG_SWPR2_PAGE56_Pos (24U)
15949#define SYSCFG_SWPR2_PAGE56_Msk (0x1U << SYSCFG_SWPR2_PAGE56_Pos) /*!< 0x01000000 */
15950#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2 Write protection page 56*/
15951#define SYSCFG_SWPR2_PAGE57_Pos (25U)
15952#define SYSCFG_SWPR2_PAGE57_Msk (0x1U << SYSCFG_SWPR2_PAGE57_Pos) /*!< 0x02000000 */
15953#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2 Write protection page 57*/
15954#define SYSCFG_SWPR2_PAGE58_Pos (26U)
15955#define SYSCFG_SWPR2_PAGE58_Msk (0x1U << SYSCFG_SWPR2_PAGE58_Pos) /*!< 0x04000000 */
15956#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2 Write protection page 58*/
15957#define SYSCFG_SWPR2_PAGE59_Pos (27U)
15958#define SYSCFG_SWPR2_PAGE59_Msk (0x1U << SYSCFG_SWPR2_PAGE59_Pos) /*!< 0x08000000 */
15959#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2 Write protection page 59*/
15960#define SYSCFG_SWPR2_PAGE60_Pos (28U)
15961#define SYSCFG_SWPR2_PAGE60_Msk (0x1U << SYSCFG_SWPR2_PAGE60_Pos) /*!< 0x10000000 */
15962#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2 Write protection page 60*/
15963#define SYSCFG_SWPR2_PAGE61_Pos (29U)
15964#define SYSCFG_SWPR2_PAGE61_Msk (0x1U << SYSCFG_SWPR2_PAGE61_Pos) /*!< 0x20000000 */
15965#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2 Write protection page 61*/
15966#define SYSCFG_SWPR2_PAGE62_Pos (30U)
15967#define SYSCFG_SWPR2_PAGE62_Msk (0x1U << SYSCFG_SWPR2_PAGE62_Pos) /*!< 0x40000000 */
15968#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2 Write protection page 62*/
15969#define SYSCFG_SWPR2_PAGE63_Pos (31U)
15970#define SYSCFG_SWPR2_PAGE63_Msk (0x1U << SYSCFG_SWPR2_PAGE63_Pos) /*!< 0x80000000 */
15971#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2 Write protection page 63*/
15972
15973/****************** Bit definition for SYSCFG_SKR register ****************/
15974#define SYSCFG_SKR_KEY_Pos (0U)
15975#define SYSCFG_SKR_KEY_Msk (0xFFU << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
15976#define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< SRAM2 write protection key for software erase */
15977
15978
15979
15980
15981/******************************************************************************/
15982/* */
15983/* TIM */
15984/* */
15985/******************************************************************************/
15986/******************* Bit definition for TIM_CR1 register ********************/
15987#define TIM_CR1_CEN_Pos (0U)
15988#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
15989#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
15990#define TIM_CR1_UDIS_Pos (1U)
15991#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
15992#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
15993#define TIM_CR1_URS_Pos (2U)
15994#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
15995#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
15996#define TIM_CR1_OPM_Pos (3U)
15997#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
15998#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
15999#define TIM_CR1_DIR_Pos (4U)
16000#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
16001#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
16002
16003#define TIM_CR1_CMS_Pos (5U)
16004#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
16005#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
16006#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
16007#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
16008
16009#define TIM_CR1_ARPE_Pos (7U)
16010#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
16011#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
16012
16013#define TIM_CR1_CKD_Pos (8U)
16014#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
16015#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
16016#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
16017#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
16018
16019#define TIM_CR1_UIFREMAP_Pos (11U)
16020#define TIM_CR1_UIFREMAP_Msk (0x1U << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
16021#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
16022
16023/******************* Bit definition for TIM_CR2 register ********************/
16024#define TIM_CR2_CCPC_Pos (0U)
16025#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
16026#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
16027#define TIM_CR2_CCUS_Pos (2U)
16028#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
16029#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
16030#define TIM_CR2_CCDS_Pos (3U)
16031#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
16032#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
16033
16034#define TIM_CR2_MMS_Pos (4U)
16035#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
16036#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
16037#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
16038#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
16039#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
16040
16041#define TIM_CR2_TI1S_Pos (7U)
16042#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
16043#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
16044#define TIM_CR2_OIS1_Pos (8U)
16045#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
16046#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
16047#define TIM_CR2_OIS1N_Pos (9U)
16048#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
16049#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
16050#define TIM_CR2_OIS2_Pos (10U)
16051#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
16052#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
16053#define TIM_CR2_OIS2N_Pos (11U)
16054#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
16055#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
16056#define TIM_CR2_OIS3_Pos (12U)
16057#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
16058#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
16059#define TIM_CR2_OIS3N_Pos (13U)
16060#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
16061#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
16062#define TIM_CR2_OIS4_Pos (14U)
16063#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
16064#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
16065#define TIM_CR2_OIS5_Pos (16U)
16066#define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
16067#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
16068#define TIM_CR2_OIS6_Pos (18U)
16069#define TIM_CR2_OIS6_Msk (0x1U << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
16070#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
16071
16072#define TIM_CR2_MMS2_Pos (20U)
16073#define TIM_CR2_MMS2_Msk (0xFU << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
16074#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
16075#define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
16076#define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
16077#define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
16078#define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
16079
16080/******************* Bit definition for TIM_SMCR register *******************/
16081#define TIM_SMCR_SMS_Pos (0U)
16082#define TIM_SMCR_SMS_Msk (0x10007U << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
16083#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
16084#define TIM_SMCR_SMS_0 (0x00001U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
16085#define TIM_SMCR_SMS_1 (0x00002U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
16086#define TIM_SMCR_SMS_2 (0x00004U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
16087#define TIM_SMCR_SMS_3 (0x10000U << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
16088
16089#define TIM_SMCR_OCCS_Pos (3U)
16090#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
16091#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
16092
16093#define TIM_SMCR_TS_Pos (4U)
16094#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
16095#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
16096#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
16097#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
16098#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
16099
16100#define TIM_SMCR_MSM_Pos (7U)
16101#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
16102#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
16103
16104#define TIM_SMCR_ETF_Pos (8U)
16105#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
16106#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
16107#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
16108#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
16109#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
16110#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
16111
16112#define TIM_SMCR_ETPS_Pos (12U)
16113#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
16114#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
16115#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
16116#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
16117
16118#define TIM_SMCR_ECE_Pos (14U)
16119#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
16120#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
16121#define TIM_SMCR_ETP_Pos (15U)
16122#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
16123#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
16124
16125/******************* Bit definition for TIM_DIER register *******************/
16126#define TIM_DIER_UIE_Pos (0U)
16127#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
16128#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
16129#define TIM_DIER_CC1IE_Pos (1U)
16130#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
16131#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
16132#define TIM_DIER_CC2IE_Pos (2U)
16133#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
16134#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
16135#define TIM_DIER_CC3IE_Pos (3U)
16136#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
16137#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
16138#define TIM_DIER_CC4IE_Pos (4U)
16139#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
16140#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
16141#define TIM_DIER_COMIE_Pos (5U)
16142#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
16143#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
16144#define TIM_DIER_TIE_Pos (6U)
16145#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
16146#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
16147#define TIM_DIER_BIE_Pos (7U)
16148#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
16149#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
16150#define TIM_DIER_UDE_Pos (8U)
16151#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
16152#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
16153#define TIM_DIER_CC1DE_Pos (9U)
16154#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
16155#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
16156#define TIM_DIER_CC2DE_Pos (10U)
16157#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
16158#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
16159#define TIM_DIER_CC3DE_Pos (11U)
16160#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
16161#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
16162#define TIM_DIER_CC4DE_Pos (12U)
16163#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
16164#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
16165#define TIM_DIER_COMDE_Pos (13U)
16166#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
16167#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
16168#define TIM_DIER_TDE_Pos (14U)
16169#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
16170#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
16171
16172/******************** Bit definition for TIM_SR register ********************/
16173#define TIM_SR_UIF_Pos (0U)
16174#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
16175#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
16176#define TIM_SR_CC1IF_Pos (1U)
16177#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
16178#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
16179#define TIM_SR_CC2IF_Pos (2U)
16180#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
16181#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
16182#define TIM_SR_CC3IF_Pos (3U)
16183#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
16184#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
16185#define TIM_SR_CC4IF_Pos (4U)
16186#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
16187#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
16188#define TIM_SR_COMIF_Pos (5U)
16189#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
16190#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
16191#define TIM_SR_TIF_Pos (6U)
16192#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
16193#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
16194#define TIM_SR_BIF_Pos (7U)
16195#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
16196#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
16197#define TIM_SR_B2IF_Pos (8U)
16198#define TIM_SR_B2IF_Msk (0x1U << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
16199#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
16200#define TIM_SR_CC1OF_Pos (9U)
16201#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
16202#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
16203#define TIM_SR_CC2OF_Pos (10U)
16204#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
16205#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
16206#define TIM_SR_CC3OF_Pos (11U)
16207#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
16208#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
16209#define TIM_SR_CC4OF_Pos (12U)
16210#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
16211#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
16212#define TIM_SR_SBIF_Pos (13U)
16213#define TIM_SR_SBIF_Msk (0x1U << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
16214#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
16215#define TIM_SR_CC5IF_Pos (16U)
16216#define TIM_SR_CC5IF_Msk (0x1U << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
16217#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
16218#define TIM_SR_CC6IF_Pos (17U)
16219#define TIM_SR_CC6IF_Msk (0x1U << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
16220#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
16221
16222
16223/******************* Bit definition for TIM_EGR register ********************/
16224#define TIM_EGR_UG_Pos (0U)
16225#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
16226#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
16227#define TIM_EGR_CC1G_Pos (1U)
16228#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
16229#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
16230#define TIM_EGR_CC2G_Pos (2U)
16231#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
16232#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
16233#define TIM_EGR_CC3G_Pos (3U)
16234#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
16235#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
16236#define TIM_EGR_CC4G_Pos (4U)
16237#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
16238#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
16239#define TIM_EGR_COMG_Pos (5U)
16240#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
16241#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
16242#define TIM_EGR_TG_Pos (6U)
16243#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
16244#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
16245#define TIM_EGR_BG_Pos (7U)
16246#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
16247#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
16248#define TIM_EGR_B2G_Pos (8U)
16249#define TIM_EGR_B2G_Msk (0x1U << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
16250#define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
16251
16252
16253/****************** Bit definition for TIM_CCMR1 register *******************/
16254#define TIM_CCMR1_CC1S_Pos (0U)
16255#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
16256#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
16257#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
16258#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
16259
16260#define TIM_CCMR1_OC1FE_Pos (2U)
16261#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
16262#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
16263#define TIM_CCMR1_OC1PE_Pos (3U)
16264#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
16265#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
16266
16267#define TIM_CCMR1_OC1M_Pos (4U)
16268#define TIM_CCMR1_OC1M_Msk (0x1007U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
16269#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
16270#define TIM_CCMR1_OC1M_0 (0x0001U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
16271#define TIM_CCMR1_OC1M_1 (0x0002U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
16272#define TIM_CCMR1_OC1M_2 (0x0004U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
16273#define TIM_CCMR1_OC1M_3 (0x1000U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
16274
16275#define TIM_CCMR1_OC1CE_Pos (7U)
16276#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
16277#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
16278
16279#define TIM_CCMR1_CC2S_Pos (8U)
16280#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
16281#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
16282#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
16283#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
16284
16285#define TIM_CCMR1_OC2FE_Pos (10U)
16286#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
16287#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
16288#define TIM_CCMR1_OC2PE_Pos (11U)
16289#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
16290#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
16291
16292#define TIM_CCMR1_OC2M_Pos (12U)
16293#define TIM_CCMR1_OC2M_Msk (0x1007U << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
16294#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
16295#define TIM_CCMR1_OC2M_0 (0x0001U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
16296#define TIM_CCMR1_OC2M_1 (0x0002U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
16297#define TIM_CCMR1_OC2M_2 (0x0004U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
16298#define TIM_CCMR1_OC2M_3 (0x1000U << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
16299
16300#define TIM_CCMR1_OC2CE_Pos (15U)
16301#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
16302#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
16303
16304/*----------------------------------------------------------------------------*/
16305#define TIM_CCMR1_IC1PSC_Pos (2U)
16306#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
16307#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
16308#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
16309#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
16310
16311#define TIM_CCMR1_IC1F_Pos (4U)
16312#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
16313#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
16314#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
16315#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
16316#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
16317#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
16318
16319#define TIM_CCMR1_IC2PSC_Pos (10U)
16320#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
16321#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
16322#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
16323#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
16324
16325#define TIM_CCMR1_IC2F_Pos (12U)
16326#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
16327#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
16328#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
16329#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
16330#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
16331#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
16332
16333/****************** Bit definition for TIM_CCMR2 register *******************/
16334#define TIM_CCMR2_CC3S_Pos (0U)
16335#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
16336#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
16337#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
16338#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
16339
16340#define TIM_CCMR2_OC3FE_Pos (2U)
16341#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
16342#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
16343#define TIM_CCMR2_OC3PE_Pos (3U)
16344#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
16345#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
16346
16347#define TIM_CCMR2_OC3M_Pos (4U)
16348#define TIM_CCMR2_OC3M_Msk (0x1007U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
16349#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
16350#define TIM_CCMR2_OC3M_0 (0x0001U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
16351#define TIM_CCMR2_OC3M_1 (0x0002U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
16352#define TIM_CCMR2_OC3M_2 (0x0004U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
16353#define TIM_CCMR2_OC3M_3 (0x1000U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
16354
16355#define TIM_CCMR2_OC3CE_Pos (7U)
16356#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
16357#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
16358
16359#define TIM_CCMR2_CC4S_Pos (8U)
16360#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
16361#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
16362#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
16363#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
16364
16365#define TIM_CCMR2_OC4FE_Pos (10U)
16366#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
16367#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
16368#define TIM_CCMR2_OC4PE_Pos (11U)
16369#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
16370#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
16371
16372#define TIM_CCMR2_OC4M_Pos (12U)
16373#define TIM_CCMR2_OC4M_Msk (0x1007U << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
16374#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
16375#define TIM_CCMR2_OC4M_0 (0x0001U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
16376#define TIM_CCMR2_OC4M_1 (0x0002U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
16377#define TIM_CCMR2_OC4M_2 (0x0004U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
16378#define TIM_CCMR2_OC4M_3 (0x1000U << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
16379
16380#define TIM_CCMR2_OC4CE_Pos (15U)
16381#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
16382#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
16383
16384/*----------------------------------------------------------------------------*/
16385#define TIM_CCMR2_IC3PSC_Pos (2U)
16386#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
16387#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
16388#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
16389#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
16390
16391#define TIM_CCMR2_IC3F_Pos (4U)
16392#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
16393#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
16394#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
16395#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
16396#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
16397#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
16398
16399#define TIM_CCMR2_IC4PSC_Pos (10U)
16400#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
16401#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
16402#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
16403#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
16404
16405#define TIM_CCMR2_IC4F_Pos (12U)
16406#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
16407#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
16408#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
16409#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
16410#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
16411#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
16412
16413/****************** Bit definition for TIM_CCMR3 register *******************/
16414#define TIM_CCMR3_OC5FE_Pos (2U)
16415#define TIM_CCMR3_OC5FE_Msk (0x1U << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
16416#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
16417#define TIM_CCMR3_OC5PE_Pos (3U)
16418#define TIM_CCMR3_OC5PE_Msk (0x1U << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
16419#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
16420
16421#define TIM_CCMR3_OC5M_Pos (4U)
16422#define TIM_CCMR3_OC5M_Msk (0x1007U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
16423#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
16424#define TIM_CCMR3_OC5M_0 (0x0001U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
16425#define TIM_CCMR3_OC5M_1 (0x0002U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
16426#define TIM_CCMR3_OC5M_2 (0x0004U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
16427#define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
16428
16429#define TIM_CCMR3_OC5CE_Pos (7U)
16430#define TIM_CCMR3_OC5CE_Msk (0x1U << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
16431#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
16432
16433#define TIM_CCMR3_OC6FE_Pos (10U)
16434#define TIM_CCMR3_OC6FE_Msk (0x1U << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
16435#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
16436#define TIM_CCMR3_OC6PE_Pos (11U)
16437#define TIM_CCMR3_OC6PE_Msk (0x1U << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
16438#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
16439
16440#define TIM_CCMR3_OC6M_Pos (12U)
16441#define TIM_CCMR3_OC6M_Msk (0x1007U << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
16442#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
16443#define TIM_CCMR3_OC6M_0 (0x0001U << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
16444#define TIM_CCMR3_OC6M_1 (0x0002U << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
16445#define TIM_CCMR3_OC6M_2 (0x0004U << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
16446#define TIM_CCMR3_OC6M_3 (0x1000U << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
16447
16448#define TIM_CCMR3_OC6CE_Pos (15U)
16449#define TIM_CCMR3_OC6CE_Msk (0x1U << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
16450#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
16451
16452/******************* Bit definition for TIM_CCER register *******************/
16453#define TIM_CCER_CC1E_Pos (0U)
16454#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
16455#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
16456#define TIM_CCER_CC1P_Pos (1U)
16457#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
16458#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
16459#define TIM_CCER_CC1NE_Pos (2U)
16460#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
16461#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
16462#define TIM_CCER_CC1NP_Pos (3U)
16463#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
16464#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
16465#define TIM_CCER_CC2E_Pos (4U)
16466#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
16467#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
16468#define TIM_CCER_CC2P_Pos (5U)
16469#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
16470#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
16471#define TIM_CCER_CC2NE_Pos (6U)
16472#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
16473#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
16474#define TIM_CCER_CC2NP_Pos (7U)
16475#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
16476#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
16477#define TIM_CCER_CC3E_Pos (8U)
16478#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
16479#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
16480#define TIM_CCER_CC3P_Pos (9U)
16481#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
16482#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
16483#define TIM_CCER_CC3NE_Pos (10U)
16484#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
16485#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
16486#define TIM_CCER_CC3NP_Pos (11U)
16487#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
16488#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
16489#define TIM_CCER_CC4E_Pos (12U)
16490#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
16491#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
16492#define TIM_CCER_CC4P_Pos (13U)
16493#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
16494#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
16495#define TIM_CCER_CC4NP_Pos (15U)
16496#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
16497#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
16498#define TIM_CCER_CC5E_Pos (16U)
16499#define TIM_CCER_CC5E_Msk (0x1U << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
16500#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
16501#define TIM_CCER_CC5P_Pos (17U)
16502#define TIM_CCER_CC5P_Msk (0x1U << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
16503#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
16504#define TIM_CCER_CC6E_Pos (20U)
16505#define TIM_CCER_CC6E_Msk (0x1U << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
16506#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
16507#define TIM_CCER_CC6P_Pos (21U)
16508#define TIM_CCER_CC6P_Msk (0x1U << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
16509#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
16510
16511/******************* Bit definition for TIM_CNT register ********************/
16512#define TIM_CNT_CNT_Pos (0U)
16513#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
16514#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
16515#define TIM_CNT_UIFCPY_Pos (31U)
16516#define TIM_CNT_UIFCPY_Msk (0x1U << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
16517#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
16518
16519/******************* Bit definition for TIM_PSC register ********************/
16520#define TIM_PSC_PSC_Pos (0U)
16521#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
16522#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
16523
16524/******************* Bit definition for TIM_ARR register ********************/
16525#define TIM_ARR_ARR_Pos (0U)
16526#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
16527#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
16528
16529/******************* Bit definition for TIM_RCR register ********************/
16530#define TIM_RCR_REP_Pos (0U)
16531#define TIM_RCR_REP_Msk (0xFFFFU << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
16532#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
16533
16534/******************* Bit definition for TIM_CCR1 register *******************/
16535#define TIM_CCR1_CCR1_Pos (0U)
16536#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
16537#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
16538
16539/******************* Bit definition for TIM_CCR2 register *******************/
16540#define TIM_CCR2_CCR2_Pos (0U)
16541#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
16542#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
16543
16544/******************* Bit definition for TIM_CCR3 register *******************/
16545#define TIM_CCR3_CCR3_Pos (0U)
16546#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
16547#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
16548
16549/******************* Bit definition for TIM_CCR4 register *******************/
16550#define TIM_CCR4_CCR4_Pos (0U)
16551#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
16552#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
16553
16554/******************* Bit definition for TIM_CCR5 register *******************/
16555#define TIM_CCR5_CCR5_Pos (0U)
16556#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
16557#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
16558#define TIM_CCR5_GC5C1_Pos (29U)
16559#define TIM_CCR5_GC5C1_Msk (0x1U << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
16560#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
16561#define TIM_CCR5_GC5C2_Pos (30U)
16562#define TIM_CCR5_GC5C2_Msk (0x1U << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
16563#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
16564#define TIM_CCR5_GC5C3_Pos (31U)
16565#define TIM_CCR5_GC5C3_Msk (0x1U << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
16566#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
16567
16568/******************* Bit definition for TIM_CCR6 register *******************/
16569#define TIM_CCR6_CCR6_Pos (0U)
16570#define TIM_CCR6_CCR6_Msk (0xFFFFU << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
16571#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
16572
16573/******************* Bit definition for TIM_BDTR register *******************/
16574#define TIM_BDTR_DTG_Pos (0U)
16575#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
16576#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
16577#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
16578#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
16579#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
16580#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
16581#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
16582#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
16583#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
16584#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
16585
16586#define TIM_BDTR_LOCK_Pos (8U)
16587#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
16588#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
16589#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
16590#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
16591
16592#define TIM_BDTR_OSSI_Pos (10U)
16593#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
16594#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
16595#define TIM_BDTR_OSSR_Pos (11U)
16596#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
16597#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
16598#define TIM_BDTR_BKE_Pos (12U)
16599#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
16600#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
16601#define TIM_BDTR_BKP_Pos (13U)
16602#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
16603#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
16604#define TIM_BDTR_AOE_Pos (14U)
16605#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
16606#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
16607#define TIM_BDTR_MOE_Pos (15U)
16608#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
16609#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
16610
16611#define TIM_BDTR_BKF_Pos (16U)
16612#define TIM_BDTR_BKF_Msk (0xFU << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
16613#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
16614#define TIM_BDTR_BK2F_Pos (20U)
16615#define TIM_BDTR_BK2F_Msk (0xFU << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
16616#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
16617
16618#define TIM_BDTR_BK2E_Pos (24U)
16619#define TIM_BDTR_BK2E_Msk (0x1U << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
16620#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
16621#define TIM_BDTR_BK2P_Pos (25U)
16622#define TIM_BDTR_BK2P_Msk (0x1U << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
16623#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
16624
16625/******************* Bit definition for TIM_DCR register ********************/
16626#define TIM_DCR_DBA_Pos (0U)
16627#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
16628#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
16629#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
16630#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
16631#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
16632#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
16633#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
16634
16635#define TIM_DCR_DBL_Pos (8U)
16636#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
16637#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
16638#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
16639#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
16640#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
16641#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
16642#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
16643
16644/******************* Bit definition for TIM_DMAR register *******************/
16645#define TIM_DMAR_DMAB_Pos (0U)
16646#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
16647#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
16648
16649/******************* Bit definition for TIM1_OR1 register *******************/
16650#define TIM1_OR1_ETR_ADC1_RMP_Pos (0U)
16651#define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */
16652#define TIM1_OR1_ETR_ADC1_RMP TIM1_OR1_ETR_ADC1_RMP_Msk /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
16653#define TIM1_OR1_ETR_ADC1_RMP_0 (0x1U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */
16654#define TIM1_OR1_ETR_ADC1_RMP_1 (0x2U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */
16655
16656#define TIM1_OR1_TI1_RMP_Pos (4U)
16657#define TIM1_OR1_TI1_RMP_Msk (0x1U << TIM1_OR1_TI1_RMP_Pos) /*!< 0x00000010 */
16658#define TIM1_OR1_TI1_RMP TIM1_OR1_TI1_RMP_Msk /*!<TIM1 Input Capture 1 remap */
16659
16660/******************* Bit definition for TIM1_OR2 register *******************/
16661#define TIM1_OR2_BKINE_Pos (0U)
16662#define TIM1_OR2_BKINE_Msk (0x1U << TIM1_OR2_BKINE_Pos) /*!< 0x00000001 */
16663#define TIM1_OR2_BKINE TIM1_OR2_BKINE_Msk /*!<BRK BKIN input enable */
16664#define TIM1_OR2_BKCMP1E_Pos (1U)
16665#define TIM1_OR2_BKCMP1E_Msk (0x1U << TIM1_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
16666#define TIM1_OR2_BKCMP1E TIM1_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
16667#define TIM1_OR2_BKCMP2E_Pos (2U)
16668#define TIM1_OR2_BKCMP2E_Msk (0x1U << TIM1_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
16669#define TIM1_OR2_BKCMP2E TIM1_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
16670#define TIM1_OR2_BKDF1BK0E_Pos (8U)
16671#define TIM1_OR2_BKDF1BK0E_Msk (0x1U << TIM1_OR2_BKDF1BK0E_Pos) /*!< 0x00000100 */
16672#define TIM1_OR2_BKDF1BK0E TIM1_OR2_BKDF1BK0E_Msk /*!<BRK DFSDM1_BREAK[0] enable */
16673#define TIM1_OR2_BKINP_Pos (9U)
16674#define TIM1_OR2_BKINP_Msk (0x1U << TIM1_OR2_BKINP_Pos) /*!< 0x00000200 */
16675#define TIM1_OR2_BKINP TIM1_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
16676#define TIM1_OR2_BKCMP1P_Pos (10U)
16677#define TIM1_OR2_BKCMP1P_Msk (0x1U << TIM1_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
16678#define TIM1_OR2_BKCMP1P TIM1_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
16679#define TIM1_OR2_BKCMP2P_Pos (11U)
16680#define TIM1_OR2_BKCMP2P_Msk (0x1U << TIM1_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
16681#define TIM1_OR2_BKCMP2P TIM1_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
16682
16683#define TIM1_OR2_ETRSEL_Pos (14U)
16684#define TIM1_OR2_ETRSEL_Msk (0x7U << TIM1_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
16685#define TIM1_OR2_ETRSEL TIM1_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
16686#define TIM1_OR2_ETRSEL_0 (0x1U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00004000 */
16687#define TIM1_OR2_ETRSEL_1 (0x2U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */
16688#define TIM1_OR2_ETRSEL_2 (0x4U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00010000 */
16689
16690/******************* Bit definition for TIM1_OR3 register *******************/
16691#define TIM1_OR3_BK2INE_Pos (0U)
16692#define TIM1_OR3_BK2INE_Msk (0x1U << TIM1_OR3_BK2INE_Pos) /*!< 0x00000001 */
16693#define TIM1_OR3_BK2INE TIM1_OR3_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
16694#define TIM1_OR3_BK2CMP1E_Pos (1U)
16695#define TIM1_OR3_BK2CMP1E_Msk (0x1U << TIM1_OR3_BK2CMP1E_Pos) /*!< 0x00000002 */
16696#define TIM1_OR3_BK2CMP1E TIM1_OR3_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
16697#define TIM1_OR3_BK2CMP2E_Pos (2U)
16698#define TIM1_OR3_BK2CMP2E_Msk (0x1U << TIM1_OR3_BK2CMP2E_Pos) /*!< 0x00000004 */
16699#define TIM1_OR3_BK2CMP2E TIM1_OR3_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
16700#define TIM1_OR3_BK2DF1BK1E_Pos (8U)
16701#define TIM1_OR3_BK2DF1BK1E_Msk (0x1U << TIM1_OR3_BK2DF1BK1E_Pos) /*!< 0x00000100 */
16702#define TIM1_OR3_BK2DF1BK1E TIM1_OR3_BK2DF1BK1E_Msk /*!<BRK2 DFSDM1_BREAK[1] enable */
16703#define TIM1_OR3_BK2INP_Pos (9U)
16704#define TIM1_OR3_BK2INP_Msk (0x1U << TIM1_OR3_BK2INP_Pos) /*!< 0x00000200 */
16705#define TIM1_OR3_BK2INP TIM1_OR3_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */
16706#define TIM1_OR3_BK2CMP1P_Pos (10U)
16707#define TIM1_OR3_BK2CMP1P_Msk (0x1U << TIM1_OR3_BK2CMP1P_Pos) /*!< 0x00000400 */
16708#define TIM1_OR3_BK2CMP1P TIM1_OR3_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
16709#define TIM1_OR3_BK2CMP2P_Pos (11U)
16710#define TIM1_OR3_BK2CMP2P_Msk (0x1U << TIM1_OR3_BK2CMP2P_Pos) /*!< 0x00000800 */
16711#define TIM1_OR3_BK2CMP2P TIM1_OR3_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
16712
16713/******************* Bit definition for TIM8_OR1 register *******************/
16714#define TIM8_OR1_TI1_RMP_Pos (4U)
16715#define TIM8_OR1_TI1_RMP_Msk (0x1U << TIM8_OR1_TI1_RMP_Pos) /*!< 0x00000010 */
16716#define TIM8_OR1_TI1_RMP TIM8_OR1_TI1_RMP_Msk /*!<TIM8 Input Capture 1 remap */
16717
16718/******************* Bit definition for TIM8_OR2 register *******************/
16719#define TIM8_OR2_BKINE_Pos (0U)
16720#define TIM8_OR2_BKINE_Msk (0x1U << TIM8_OR2_BKINE_Pos) /*!< 0x00000001 */
16721#define TIM8_OR2_BKINE TIM8_OR2_BKINE_Msk /*!<BRK BKIN input enable */
16722#define TIM8_OR2_BKCMP1E_Pos (1U)
16723#define TIM8_OR2_BKCMP1E_Msk (0x1U << TIM8_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
16724#define TIM8_OR2_BKCMP1E TIM8_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
16725#define TIM8_OR2_BKCMP2E_Pos (2U)
16726#define TIM8_OR2_BKCMP2E_Msk (0x1U << TIM8_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
16727#define TIM8_OR2_BKCMP2E TIM8_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
16728#define TIM8_OR2_BKDF1BK2E_Pos (8U)
16729#define TIM8_OR2_BKDF1BK2E_Msk (0x1U << TIM8_OR2_BKDF1BK2E_Pos) /*!< 0x00000100 */
16730#define TIM8_OR2_BKDF1BK2E TIM8_OR2_BKDF1BK2E_Msk /*!<BRK DFSDM1_BREAK[2] enable */
16731#define TIM8_OR2_BKINP_Pos (9U)
16732#define TIM8_OR2_BKINP_Msk (0x1U << TIM8_OR2_BKINP_Pos) /*!< 0x00000200 */
16733#define TIM8_OR2_BKINP TIM8_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
16734#define TIM8_OR2_BKCMP1P_Pos (10U)
16735#define TIM8_OR2_BKCMP1P_Msk (0x1U << TIM8_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
16736#define TIM8_OR2_BKCMP1P TIM8_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
16737#define TIM8_OR2_BKCMP2P_Pos (11U)
16738#define TIM8_OR2_BKCMP2P_Msk (0x1U << TIM8_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
16739#define TIM8_OR2_BKCMP2P TIM8_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
16740
16741#define TIM8_OR2_ETRSEL_Pos (14U)
16742#define TIM8_OR2_ETRSEL_Msk (0x7U << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
16743#define TIM8_OR2_ETRSEL TIM8_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM8 ETR source selection) */
16744#define TIM8_OR2_ETRSEL_0 (0x1U << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */
16745#define TIM8_OR2_ETRSEL_1 (0x2U << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */
16746#define TIM8_OR2_ETRSEL_2 (0x4U << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */
16747
16748/******************* Bit definition for TIM8_OR3 register *******************/
16749#define TIM8_OR3_BK2INE_Pos (0U)
16750#define TIM8_OR3_BK2INE_Msk (0x1U << TIM8_OR3_BK2INE_Pos) /*!< 0x00000001 */
16751#define TIM8_OR3_BK2INE TIM8_OR3_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
16752#define TIM8_OR3_BK2CMP1E_Pos (1U)
16753#define TIM8_OR3_BK2CMP1E_Msk (0x1U << TIM8_OR3_BK2CMP1E_Pos) /*!< 0x00000002 */
16754#define TIM8_OR3_BK2CMP1E TIM8_OR3_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
16755#define TIM8_OR3_BK2CMP2E_Pos (2U)
16756#define TIM8_OR3_BK2CMP2E_Msk (0x1U << TIM8_OR3_BK2CMP2E_Pos) /*!< 0x00000004 */
16757#define TIM8_OR3_BK2CMP2E TIM8_OR3_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
16758#define TIM8_OR3_BK2DF1BK3E_Pos (8U)
16759#define TIM8_OR3_BK2DF1BK3E_Msk (0x1U << TIM8_OR3_BK2DF1BK3E_Pos) /*!< 0x00000100 */
16760#define TIM8_OR3_BK2DF1BK3E TIM8_OR3_BK2DF1BK3E_Msk /*!<BRK2 DFSDM1_BREAK[3] enable */
16761#define TIM8_OR3_BK2INP_Pos (9U)
16762#define TIM8_OR3_BK2INP_Msk (0x1U << TIM8_OR3_BK2INP_Pos) /*!< 0x00000200 */
16763#define TIM8_OR3_BK2INP TIM8_OR3_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */
16764#define TIM8_OR3_BK2CMP1P_Pos (10U)
16765#define TIM8_OR3_BK2CMP1P_Msk (0x1U << TIM8_OR3_BK2CMP1P_Pos) /*!< 0x00000400 */
16766#define TIM8_OR3_BK2CMP1P TIM8_OR3_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
16767#define TIM8_OR3_BK2CMP2P_Pos (11U)
16768#define TIM8_OR3_BK2CMP2P_Msk (0x1U << TIM8_OR3_BK2CMP2P_Pos) /*!< 0x00000800 */
16769#define TIM8_OR3_BK2CMP2P TIM8_OR3_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
16770
16771/******************* Bit definition for TIM2_OR1 register *******************/
16772#define TIM2_OR1_ITR1_RMP_Pos (0U)
16773#define TIM2_OR1_ITR1_RMP_Msk (0x1U << TIM2_OR1_ITR1_RMP_Pos) /*!< 0x00000001 */
16774#define TIM2_OR1_ITR1_RMP TIM2_OR1_ITR1_RMP_Msk /*!<TIM2 Internal trigger 1 remap */
16775#define TIM2_OR1_ETR1_RMP_Pos (1U)
16776#define TIM2_OR1_ETR1_RMP_Msk (0x1U << TIM2_OR1_ETR1_RMP_Pos) /*!< 0x00000002 */
16777#define TIM2_OR1_ETR1_RMP TIM2_OR1_ETR1_RMP_Msk /*!<TIM2 External trigger 1 remap */
16778
16779#define TIM2_OR1_TI4_RMP_Pos (2U)
16780#define TIM2_OR1_TI4_RMP_Msk (0x3U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x0000000C */
16781#define TIM2_OR1_TI4_RMP TIM2_OR1_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
16782#define TIM2_OR1_TI4_RMP_0 (0x1U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000004 */
16783#define TIM2_OR1_TI4_RMP_1 (0x2U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000008 */
16784
16785/******************* Bit definition for TIM2_OR2 register *******************/
16786#define TIM2_OR2_ETRSEL_Pos (14U)
16787#define TIM2_OR2_ETRSEL_Msk (0x7U << TIM2_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
16788#define TIM2_OR2_ETRSEL TIM2_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
16789#define TIM2_OR2_ETRSEL_0 (0x1U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00004000 */
16790#define TIM2_OR2_ETRSEL_1 (0x2U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00008000 */
16791#define TIM2_OR2_ETRSEL_2 (0x4U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00010000 */
16792
16793/******************* Bit definition for TIM3_OR1 register *******************/
16794#define TIM3_OR1_TI1_RMP_Pos (0U)
16795#define TIM3_OR1_TI1_RMP_Msk (0x3U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
16796#define TIM3_OR1_TI1_RMP TIM3_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) */
16797#define TIM3_OR1_TI1_RMP_0 (0x1U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
16798#define TIM3_OR1_TI1_RMP_1 (0x2U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
16799
16800/******************* Bit definition for TIM3_OR2 register *******************/
16801#define TIM3_OR2_ETRSEL_Pos (14U)
16802#define TIM3_OR2_ETRSEL_Msk (0x7U << TIM3_OR2_ETRSEL_Pos) /*!< 0x0001C000 */
16803#define TIM3_OR2_ETRSEL TIM3_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM3 ETR source selection) */
16804#define TIM3_OR2_ETRSEL_0 (0x1U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00004000 */
16805#define TIM3_OR2_ETRSEL_1 (0x2U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00008000 */
16806#define TIM3_OR2_ETRSEL_2 (0x4U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00010000 */
16807
16808/******************* Bit definition for TIM15_OR1 register ******************/
16809#define TIM15_OR1_TI1_RMP_Pos (0U)
16810#define TIM15_OR1_TI1_RMP_Msk (0x1U << TIM15_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
16811#define TIM15_OR1_TI1_RMP TIM15_OR1_TI1_RMP_Msk /*!<TIM15 Input Capture 1 remap */
16812
16813#define TIM15_OR1_ENCODER_MODE_Pos (1U)
16814#define TIM15_OR1_ENCODER_MODE_Msk (0x3U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000006 */
16815#define TIM15_OR1_ENCODER_MODE TIM15_OR1_ENCODER_MODE_Msk /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
16816#define TIM15_OR1_ENCODER_MODE_0 (0x1U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000002 */
16817#define TIM15_OR1_ENCODER_MODE_1 (0x2U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000004 */
16818
16819/******************* Bit definition for TIM15_OR2 register ******************/
16820#define TIM15_OR2_BKINE_Pos (0U)
16821#define TIM15_OR2_BKINE_Msk (0x1U << TIM15_OR2_BKINE_Pos) /*!< 0x00000001 */
16822#define TIM15_OR2_BKINE TIM15_OR2_BKINE_Msk /*!<BRK BKIN input enable */
16823#define TIM15_OR2_BKCMP1E_Pos (1U)
16824#define TIM15_OR2_BKCMP1E_Msk (0x1U << TIM15_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
16825#define TIM15_OR2_BKCMP1E TIM15_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
16826#define TIM15_OR2_BKCMP2E_Pos (2U)
16827#define TIM15_OR2_BKCMP2E_Msk (0x1U << TIM15_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
16828#define TIM15_OR2_BKCMP2E TIM15_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
16829#define TIM15_OR2_BKDF1BK0E_Pos (8U)
16830#define TIM15_OR2_BKDF1BK0E_Msk (0x1U << TIM15_OR2_BKDF1BK0E_Pos) /*!< 0x00000100 */
16831#define TIM15_OR2_BKDF1BK0E TIM15_OR2_BKDF1BK0E_Msk /*!<BRK DFSDM1_BREAK[0] enable */
16832#define TIM15_OR2_BKINP_Pos (9U)
16833#define TIM15_OR2_BKINP_Msk (0x1U << TIM15_OR2_BKINP_Pos) /*!< 0x00000200 */
16834#define TIM15_OR2_BKINP TIM15_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
16835#define TIM15_OR2_BKCMP1P_Pos (10U)
16836#define TIM15_OR2_BKCMP1P_Msk (0x1U << TIM15_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
16837#define TIM15_OR2_BKCMP1P TIM15_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
16838#define TIM15_OR2_BKCMP2P_Pos (11U)
16839#define TIM15_OR2_BKCMP2P_Msk (0x1U << TIM15_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
16840#define TIM15_OR2_BKCMP2P TIM15_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
16841
16842/******************* Bit definition for TIM16_OR1 register ******************/
16843#define TIM16_OR1_TI1_RMP_Pos (0U)
16844#define TIM16_OR1_TI1_RMP_Msk (0x3U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
16845#define TIM16_OR1_TI1_RMP TIM16_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM16 Input Capture 1 remap) */
16846#define TIM16_OR1_TI1_RMP_0 (0x1U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
16847#define TIM16_OR1_TI1_RMP_1 (0x2U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
16848
16849/******************* Bit definition for TIM16_OR2 register ******************/
16850#define TIM16_OR2_BKINE_Pos (0U)
16851#define TIM16_OR2_BKINE_Msk (0x1U << TIM16_OR2_BKINE_Pos) /*!< 0x00000001 */
16852#define TIM16_OR2_BKINE TIM16_OR2_BKINE_Msk /*!<BRK BKIN input enable */
16853#define TIM16_OR2_BKCMP1E_Pos (1U)
16854#define TIM16_OR2_BKCMP1E_Msk (0x1U << TIM16_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
16855#define TIM16_OR2_BKCMP1E TIM16_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
16856#define TIM16_OR2_BKCMP2E_Pos (2U)
16857#define TIM16_OR2_BKCMP2E_Msk (0x1U << TIM16_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
16858#define TIM16_OR2_BKCMP2E TIM16_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
16859#define TIM16_OR2_BKDF1BK1E_Pos (8U)
16860#define TIM16_OR2_BKDF1BK1E_Msk (0x1U << TIM16_OR2_BKDF1BK1E_Pos) /*!< 0x00000100 */
16861#define TIM16_OR2_BKDF1BK1E TIM16_OR2_BKDF1BK1E_Msk /*!<BRK DFSDM1_BREAK[1] enable */
16862#define TIM16_OR2_BKINP_Pos (9U)
16863#define TIM16_OR2_BKINP_Msk (0x1U << TIM16_OR2_BKINP_Pos) /*!< 0x00000200 */
16864#define TIM16_OR2_BKINP TIM16_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
16865#define TIM16_OR2_BKCMP1P_Pos (10U)
16866#define TIM16_OR2_BKCMP1P_Msk (0x1U << TIM16_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
16867#define TIM16_OR2_BKCMP1P TIM16_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
16868#define TIM16_OR2_BKCMP2P_Pos (11U)
16869#define TIM16_OR2_BKCMP2P_Msk (0x1U << TIM16_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
16870#define TIM16_OR2_BKCMP2P TIM16_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
16871
16872/******************* Bit definition for TIM17_OR1 register ******************/
16873#define TIM17_OR1_TI1_RMP_Pos (0U)
16874#define TIM17_OR1_TI1_RMP_Msk (0x3U << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */
16875#define TIM17_OR1_TI1_RMP TIM17_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM17 Input Capture 1 remap) */
16876#define TIM17_OR1_TI1_RMP_0 (0x1U << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */
16877#define TIM17_OR1_TI1_RMP_1 (0x2U << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */
16878
16879/******************* Bit definition for TIM17_OR2 register ******************/
16880#define TIM17_OR2_BKINE_Pos (0U)
16881#define TIM17_OR2_BKINE_Msk (0x1U << TIM17_OR2_BKINE_Pos) /*!< 0x00000001 */
16882#define TIM17_OR2_BKINE TIM17_OR2_BKINE_Msk /*!<BRK BKIN input enable */
16883#define TIM17_OR2_BKCMP1E_Pos (1U)
16884#define TIM17_OR2_BKCMP1E_Msk (0x1U << TIM17_OR2_BKCMP1E_Pos) /*!< 0x00000002 */
16885#define TIM17_OR2_BKCMP1E TIM17_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */
16886#define TIM17_OR2_BKCMP2E_Pos (2U)
16887#define TIM17_OR2_BKCMP2E_Msk (0x1U << TIM17_OR2_BKCMP2E_Pos) /*!< 0x00000004 */
16888#define TIM17_OR2_BKCMP2E TIM17_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */
16889#define TIM17_OR2_BKDF1BK2E_Pos (8U)
16890#define TIM17_OR2_BKDF1BK2E_Msk (0x1U << TIM17_OR2_BKDF1BK2E_Pos) /*!< 0x00000100 */
16891#define TIM17_OR2_BKDF1BK2E TIM17_OR2_BKDF1BK2E_Msk /*!<BRK DFSDM1_BREAK[2] enable */
16892#define TIM17_OR2_BKINP_Pos (9U)
16893#define TIM17_OR2_BKINP_Msk (0x1U << TIM17_OR2_BKINP_Pos) /*!< 0x00000200 */
16894#define TIM17_OR2_BKINP TIM17_OR2_BKINP_Msk /*!<BRK BKIN input polarity */
16895#define TIM17_OR2_BKCMP1P_Pos (10U)
16896#define TIM17_OR2_BKCMP1P_Msk (0x1U << TIM17_OR2_BKCMP1P_Pos) /*!< 0x00000400 */
16897#define TIM17_OR2_BKCMP1P TIM17_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
16898#define TIM17_OR2_BKCMP2P_Pos (11U)
16899#define TIM17_OR2_BKCMP2P_Msk (0x1U << TIM17_OR2_BKCMP2P_Pos) /*!< 0x00000800 */
16900#define TIM17_OR2_BKCMP2P TIM17_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
16901
16902/******************************************************************************/
16903/* */
16904/* Low Power Timer (LPTTIM) */
16905/* */
16906/******************************************************************************/
16907/****************** Bit definition for LPTIM_ISR register *******************/
16908#define LPTIM_ISR_CMPM_Pos (0U)
16909#define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
16910#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
16911#define LPTIM_ISR_ARRM_Pos (1U)
16912#define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
16913#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
16914#define LPTIM_ISR_EXTTRIG_Pos (2U)
16915#define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
16916#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
16917#define LPTIM_ISR_CMPOK_Pos (3U)
16918#define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
16919#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
16920#define LPTIM_ISR_ARROK_Pos (4U)
16921#define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
16922#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
16923#define LPTIM_ISR_UP_Pos (5U)
16924#define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
16925#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
16926#define LPTIM_ISR_DOWN_Pos (6U)
16927#define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
16928#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
16929
16930/****************** Bit definition for LPTIM_ICR register *******************/
16931#define LPTIM_ICR_CMPMCF_Pos (0U)
16932#define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
16933#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
16934#define LPTIM_ICR_ARRMCF_Pos (1U)
16935#define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
16936#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
16937#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
16938#define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
16939#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
16940#define LPTIM_ICR_CMPOKCF_Pos (3U)
16941#define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
16942#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
16943#define LPTIM_ICR_ARROKCF_Pos (4U)
16944#define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
16945#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
16946#define LPTIM_ICR_UPCF_Pos (5U)
16947#define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
16948#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
16949#define LPTIM_ICR_DOWNCF_Pos (6U)
16950#define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
16951#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
16952
16953/****************** Bit definition for LPTIM_IER register ********************/
16954#define LPTIM_IER_CMPMIE_Pos (0U)
16955#define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
16956#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
16957#define LPTIM_IER_ARRMIE_Pos (1U)
16958#define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
16959#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
16960#define LPTIM_IER_EXTTRIGIE_Pos (2U)
16961#define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
16962#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
16963#define LPTIM_IER_CMPOKIE_Pos (3U)
16964#define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
16965#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
16966#define LPTIM_IER_ARROKIE_Pos (4U)
16967#define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
16968#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
16969#define LPTIM_IER_UPIE_Pos (5U)
16970#define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
16971#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
16972#define LPTIM_IER_DOWNIE_Pos (6U)
16973#define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
16974#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
16975
16976/****************** Bit definition for LPTIM_CFGR register *******************/
16977#define LPTIM_CFGR_CKSEL_Pos (0U)
16978#define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
16979#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
16980
16981#define LPTIM_CFGR_CKPOL_Pos (1U)
16982#define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
16983#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
16984#define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
16985#define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
16986
16987#define LPTIM_CFGR_CKFLT_Pos (3U)
16988#define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
16989#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
16990#define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
16991#define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
16992
16993#define LPTIM_CFGR_TRGFLT_Pos (6U)
16994#define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
16995#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
16996#define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
16997#define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
16998
16999#define LPTIM_CFGR_PRESC_Pos (9U)
17000#define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
17001#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
17002#define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
17003#define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
17004#define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
17005
17006#define LPTIM_CFGR_TRIGSEL_Pos (13U)
17007#define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
17008#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
17009#define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
17010#define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
17011#define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
17012
17013#define LPTIM_CFGR_TRIGEN_Pos (17U)
17014#define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
17015#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
17016#define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
17017#define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
17018
17019#define LPTIM_CFGR_TIMOUT_Pos (19U)
17020#define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
17021#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
17022#define LPTIM_CFGR_WAVE_Pos (20U)
17023#define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
17024#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
17025#define LPTIM_CFGR_WAVPOL_Pos (21U)
17026#define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
17027#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
17028#define LPTIM_CFGR_PRELOAD_Pos (22U)
17029#define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
17030#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
17031#define LPTIM_CFGR_COUNTMODE_Pos (23U)
17032#define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
17033#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
17034#define LPTIM_CFGR_ENC_Pos (24U)
17035#define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
17036#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
17037
17038/****************** Bit definition for LPTIM_CR register ********************/
17039#define LPTIM_CR_ENABLE_Pos (0U)
17040#define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
17041#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
17042#define LPTIM_CR_SNGSTRT_Pos (1U)
17043#define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
17044#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
17045#define LPTIM_CR_CNTSTRT_Pos (2U)
17046#define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
17047#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
17048
17049/****************** Bit definition for LPTIM_CMP register *******************/
17050#define LPTIM_CMP_CMP_Pos (0U)
17051#define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
17052#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
17053
17054/****************** Bit definition for LPTIM_ARR register *******************/
17055#define LPTIM_ARR_ARR_Pos (0U)
17056#define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
17057#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
17058
17059/****************** Bit definition for LPTIM_CNT register *******************/
17060#define LPTIM_CNT_CNT_Pos (0U)
17061#define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
17062#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
17063
17064/****************** Bit definition for LPTIM_OR register ********************/
17065#define LPTIM_OR_OR_Pos (0U)
17066#define LPTIM_OR_OR_Msk (0x3U << LPTIM_OR_OR_Pos) /*!< 0x00000003 */
17067#define LPTIM_OR_OR LPTIM_OR_OR_Msk /*!< OR[1:0] bits (Remap selection) */
17068#define LPTIM_OR_OR_0 (0x1U << LPTIM_OR_OR_Pos) /*!< 0x00000001 */
17069#define LPTIM_OR_OR_1 (0x2U << LPTIM_OR_OR_Pos) /*!< 0x00000002 */
17070
17071/******************************************************************************/
17072/* */
17073/* Analog Comparators (COMP) */
17074/* */
17075/******************************************************************************/
17076/********************** Bit definition for COMP_CSR register ****************/
17077#define COMP_CSR_EN_Pos (0U)
17078#define COMP_CSR_EN_Msk (0x1U << COMP_CSR_EN_Pos) /*!< 0x00000001 */
17079#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
17080
17081#define COMP_CSR_PWRMODE_Pos (2U)
17082#define COMP_CSR_PWRMODE_Msk (0x3U << COMP_CSR_PWRMODE_Pos) /*!< 0x0000000C */
17083#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */
17084#define COMP_CSR_PWRMODE_0 (0x1U << COMP_CSR_PWRMODE_Pos) /*!< 0x00000004 */
17085#define COMP_CSR_PWRMODE_1 (0x2U << COMP_CSR_PWRMODE_Pos) /*!< 0x00000008 */
17086
17087#define COMP_CSR_INMSEL_Pos (4U)
17088#define COMP_CSR_INMSEL_Msk (0x7U << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */
17089#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
17090#define COMP_CSR_INMSEL_0 (0x1U << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */
17091#define COMP_CSR_INMSEL_1 (0x2U << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */
17092#define COMP_CSR_INMSEL_2 (0x4U << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */
17093
17094#define COMP_CSR_INPSEL_Pos (7U)
17095#define COMP_CSR_INPSEL_Msk (0x1U << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */
17096#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */
17097#define COMP_CSR_INPSEL_0 (0x1U << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */
17098
17099#define COMP_CSR_WINMODE_Pos (9U)
17100#define COMP_CSR_WINMODE_Msk (0x1U << COMP_CSR_WINMODE_Pos) /*!< 0x00000200 */
17101#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
17102
17103#define COMP_CSR_POLARITY_Pos (15U)
17104#define COMP_CSR_POLARITY_Msk (0x1U << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
17105#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
17106
17107#define COMP_CSR_HYST_Pos (16U)
17108#define COMP_CSR_HYST_Msk (0x3U << COMP_CSR_HYST_Pos) /*!< 0x00030000 */
17109#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */
17110#define COMP_CSR_HYST_0 (0x1U << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
17111#define COMP_CSR_HYST_1 (0x2U << COMP_CSR_HYST_Pos) /*!< 0x00020000 */
17112
17113#define COMP_CSR_BLANKING_Pos (18U)
17114#define COMP_CSR_BLANKING_Msk (0x7U << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */
17115#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */
17116#define COMP_CSR_BLANKING_0 (0x1U << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */
17117#define COMP_CSR_BLANKING_1 (0x2U << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
17118#define COMP_CSR_BLANKING_2 (0x4U << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
17119
17120#define COMP_CSR_BRGEN_Pos (22U)
17121#define COMP_CSR_BRGEN_Msk (0x1U << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
17122#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */
17123#define COMP_CSR_SCALEN_Pos (23U)
17124#define COMP_CSR_SCALEN_Msk (0x1U << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
17125#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */
17126
17127#define COMP_CSR_VALUE_Pos (30U)
17128#define COMP_CSR_VALUE_Msk (0x1U << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
17129#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */
17130
17131#define COMP_CSR_LOCK_Pos (31U)
17132#define COMP_CSR_LOCK_Msk (0x1U << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */
17133#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */
17134
17135/******************************************************************************/
17136/* */
17137/* Operational Amplifier (OPAMP) */
17138/* */
17139/******************************************************************************/
17140/********************* Bit definition for OPAMPx_CSR register ***************/
17141#define OPAMP_CSR_OPAMPxEN_Pos (0U)
17142#define OPAMP_CSR_OPAMPxEN_Msk (0x1U << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
17143#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
17144#define OPAMP_CSR_OPALPM_Pos (1U)
17145#define OPAMP_CSR_OPALPM_Msk (0x1U << OPAMP_CSR_OPALPM_Pos) /*!< 0x00000002 */
17146#define OPAMP_CSR_OPALPM OPAMP_CSR_OPALPM_Msk /*!< Operational amplifier Low Power Mode */
17147
17148#define OPAMP_CSR_OPAMODE_Pos (2U)
17149#define OPAMP_CSR_OPAMODE_Msk (0x3U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x0000000C */
17150#define OPAMP_CSR_OPAMODE OPAMP_CSR_OPAMODE_Msk /*!< Operational amplifier PGA mode */
17151#define OPAMP_CSR_OPAMODE_0 (0x1U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000004 */
17152#define OPAMP_CSR_OPAMODE_1 (0x2U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000008 */
17153
17154#define OPAMP_CSR_PGGAIN_Pos (4U)
17155#define OPAMP_CSR_PGGAIN_Msk (0x3U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000030 */
17156#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */
17157#define OPAMP_CSR_PGGAIN_0 (0x1U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000010 */
17158#define OPAMP_CSR_PGGAIN_1 (0x2U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000020 */
17159
17160#define OPAMP_CSR_VMSEL_Pos (8U)
17161#define OPAMP_CSR_VMSEL_Msk (0x3U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000300 */
17162#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
17163#define OPAMP_CSR_VMSEL_0 (0x1U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000100 */
17164#define OPAMP_CSR_VMSEL_1 (0x2U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000200 */
17165
17166#define OPAMP_CSR_VPSEL_Pos (10U)
17167#define OPAMP_CSR_VPSEL_Msk (0x1U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000400 */
17168#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */
17169#define OPAMP_CSR_CALON_Pos (12U)
17170#define OPAMP_CSR_CALON_Msk (0x1U << OPAMP_CSR_CALON_Pos) /*!< 0x00001000 */
17171#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
17172#define OPAMP_CSR_CALSEL_Pos (13U)
17173#define OPAMP_CSR_CALSEL_Msk (0x1U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
17174#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
17175#define OPAMP_CSR_USERTRIM_Pos (14U)
17176#define OPAMP_CSR_USERTRIM_Msk (0x1U << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00004000 */
17177#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
17178#define OPAMP_CSR_CALOUT_Pos (15U)
17179#define OPAMP_CSR_CALOUT_Msk (0x1U << OPAMP_CSR_CALOUT_Pos) /*!< 0x00008000 */
17180#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
17181
17182/********************* Bit definition for OPAMP1_CSR register ***************/
17183#define OPAMP1_CSR_OPAEN_Pos (0U)
17184#define OPAMP1_CSR_OPAEN_Msk (0x1U << OPAMP1_CSR_OPAEN_Pos) /*!< 0x00000001 */
17185#define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk /*!< Operational amplifier1 Enable */
17186#define OPAMP1_CSR_OPALPM_Pos (1U)
17187#define OPAMP1_CSR_OPALPM_Msk (0x1U << OPAMP1_CSR_OPALPM_Pos) /*!< 0x00000002 */
17188#define OPAMP1_CSR_OPALPM OPAMP1_CSR_OPALPM_Msk /*!< Operational amplifier1 Low Power Mode */
17189
17190#define OPAMP1_CSR_OPAMODE_Pos (2U)
17191#define OPAMP1_CSR_OPAMODE_Msk (0x3U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x0000000C */
17192#define OPAMP1_CSR_OPAMODE OPAMP1_CSR_OPAMODE_Msk /*!< Operational amplifier1 PGA mode */
17193#define OPAMP1_CSR_OPAMODE_0 (0x1U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000004 */
17194#define OPAMP1_CSR_OPAMODE_1 (0x2U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000008 */
17195
17196#define OPAMP1_CSR_PGAGAIN_Pos (4U)
17197#define OPAMP1_CSR_PGAGAIN_Msk (0x3U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000030 */
17198#define OPAMP1_CSR_PGAGAIN OPAMP1_CSR_PGAGAIN_Msk /*!< Operational amplifier1 Programmable amplifier gain value */
17199#define OPAMP1_CSR_PGAGAIN_0 (0x1U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000010 */
17200#define OPAMP1_CSR_PGAGAIN_1 (0x2U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000020 */
17201
17202#define OPAMP1_CSR_VMSEL_Pos (8U)
17203#define OPAMP1_CSR_VMSEL_Msk (0x3U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000300 */
17204#define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */
17205#define OPAMP1_CSR_VMSEL_0 (0x1U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000100 */
17206#define OPAMP1_CSR_VMSEL_1 (0x2U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000200 */
17207
17208#define OPAMP1_CSR_VPSEL_Pos (10U)
17209#define OPAMP1_CSR_VPSEL_Msk (0x1U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000400 */
17210#define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverted input selection */
17211#define OPAMP1_CSR_CALON_Pos (12U)
17212#define OPAMP1_CSR_CALON_Msk (0x1U << OPAMP1_CSR_CALON_Pos) /*!< 0x00001000 */
17213#define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */
17214#define OPAMP1_CSR_CALSEL_Pos (13U)
17215#define OPAMP1_CSR_CALSEL_Msk (0x1U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */
17216#define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */
17217#define OPAMP1_CSR_USERTRIM_Pos (14U)
17218#define OPAMP1_CSR_USERTRIM_Msk (0x1U << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00004000 */
17219#define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */
17220#define OPAMP1_CSR_CALOUT_Pos (15U)
17221#define OPAMP1_CSR_CALOUT_Msk (0x1U << OPAMP1_CSR_CALOUT_Pos) /*!< 0x00008000 */
17222#define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
17223
17224#define OPAMP1_CSR_OPARANGE_Pos (31U)
17225#define OPAMP1_CSR_OPARANGE_Msk (0x1U << OPAMP1_CSR_OPARANGE_Pos) /*!< 0x80000000 */
17226#define OPAMP1_CSR_OPARANGE OPAMP1_CSR_OPARANGE_Msk /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
17227
17228/********************* Bit definition for OPAMP2_CSR register ***************/
17229#define OPAMP2_CSR_OPAEN_Pos (0U)
17230#define OPAMP2_CSR_OPAEN_Msk (0x1U << OPAMP2_CSR_OPAEN_Pos) /*!< 0x00000001 */
17231#define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk /*!< Operational amplifier2 Enable */
17232#define OPAMP2_CSR_OPALPM_Pos (1U)
17233#define OPAMP2_CSR_OPALPM_Msk (0x1U << OPAMP2_CSR_OPALPM_Pos) /*!< 0x00000002 */
17234#define OPAMP2_CSR_OPALPM OPAMP2_CSR_OPALPM_Msk /*!< Operational amplifier2 Low Power Mode */
17235
17236#define OPAMP2_CSR_OPAMODE_Pos (2U)
17237#define OPAMP2_CSR_OPAMODE_Msk (0x3U << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x0000000C */
17238#define OPAMP2_CSR_OPAMODE OPAMP2_CSR_OPAMODE_Msk /*!< Operational amplifier2 PGA mode */
17239#define OPAMP2_CSR_OPAMODE_0 (0x1U << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x00000004 */
17240#define OPAMP2_CSR_OPAMODE_1 (0x2U << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x00000008 */
17241
17242#define OPAMP2_CSR_PGAGAIN_Pos (4U)
17243#define OPAMP2_CSR_PGAGAIN_Msk (0x3U << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000030 */
17244#define OPAMP2_CSR_PGAGAIN OPAMP2_CSR_PGAGAIN_Msk /*!< Operational amplifier2 Programmable amplifier gain value */
17245#define OPAMP2_CSR_PGAGAIN_0 (0x1U << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000010 */
17246#define OPAMP2_CSR_PGAGAIN_1 (0x2U << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000020 */
17247
17248#define OPAMP2_CSR_VMSEL_Pos (8U)
17249#define OPAMP2_CSR_VMSEL_Msk (0x3U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000300 */
17250#define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */
17251#define OPAMP2_CSR_VMSEL_0 (0x1U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000100 */
17252#define OPAMP2_CSR_VMSEL_1 (0x2U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000200 */
17253
17254#define OPAMP2_CSR_VPSEL_Pos (10U)
17255#define OPAMP2_CSR_VPSEL_Msk (0x1U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000400 */
17256#define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverted input selection */
17257#define OPAMP2_CSR_CALON_Pos (12U)
17258#define OPAMP2_CSR_CALON_Msk (0x1U << OPAMP2_CSR_CALON_Pos) /*!< 0x00001000 */
17259#define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */
17260#define OPAMP2_CSR_CALSEL_Pos (13U)
17261#define OPAMP2_CSR_CALSEL_Msk (0x1U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */
17262#define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */
17263#define OPAMP2_CSR_USERTRIM_Pos (14U)
17264#define OPAMP2_CSR_USERTRIM_Msk (0x1U << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00004000 */
17265#define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */
17266#define OPAMP2_CSR_CALOUT_Pos (15U)
17267#define OPAMP2_CSR_CALOUT_Msk (0x1U << OPAMP2_CSR_CALOUT_Pos) /*!< 0x00008000 */
17268#define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk /*!< Operational amplifier2 calibration output */
17269
17270/******************* Bit definition for OPAMP_OTR register ******************/
17271#define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
17272#define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
17273#define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
17274#define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
17275#define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
17276#define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
17277
17278/******************* Bit definition for OPAMP1_OTR register ******************/
17279#define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
17280#define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
17281#define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
17282#define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
17283#define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
17284#define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
17285
17286/******************* Bit definition for OPAMP2_OTR register ******************/
17287#define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
17288#define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
17289#define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
17290#define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
17291#define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
17292#define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
17293
17294/******************* Bit definition for OPAMP_LPOTR register ****************/
17295#define OPAMP_LPOTR_TRIMLPOFFSETN_Pos (0U)
17296#define OPAMP_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
17297#define OPAMP_LPOTR_TRIMLPOFFSETN OPAMP_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
17298#define OPAMP_LPOTR_TRIMLPOFFSETP_Pos (8U)
17299#define OPAMP_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
17300#define OPAMP_LPOTR_TRIMLPOFFSETP OPAMP_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
17301
17302/******************* Bit definition for OPAMP1_LPOTR register ****************/
17303#define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos (0U)
17304#define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
17305#define OPAMP1_LPOTR_TRIMLPOFFSETN OPAMP1_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
17306#define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos (8U)
17307#define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
17308#define OPAMP1_LPOTR_TRIMLPOFFSETP OPAMP1_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
17309
17310/******************* Bit definition for OPAMP2_LPOTR register ****************/
17311#define OPAMP2_LPOTR_TRIMLPOFFSETN_Pos (0U)
17312#define OPAMP2_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
17313#define OPAMP2_LPOTR_TRIMLPOFFSETN OPAMP2_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */
17314#define OPAMP2_LPOTR_TRIMLPOFFSETP_Pos (8U)
17315#define OPAMP2_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
17316#define OPAMP2_LPOTR_TRIMLPOFFSETP OPAMP2_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */
17317
17318/******************************************************************************/
17319/* */
17320/* Touch Sensing Controller (TSC) */
17321/* */
17322/******************************************************************************/
17323/******************* Bit definition for TSC_CR register *********************/
17324#define TSC_CR_TSCE_Pos (0U)
17325#define TSC_CR_TSCE_Msk (0x1U << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
17326#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
17327#define TSC_CR_START_Pos (1U)
17328#define TSC_CR_START_Msk (0x1U << TSC_CR_START_Pos) /*!< 0x00000002 */
17329#define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
17330#define TSC_CR_AM_Pos (2U)
17331#define TSC_CR_AM_Msk (0x1U << TSC_CR_AM_Pos) /*!< 0x00000004 */
17332#define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
17333#define TSC_CR_SYNCPOL_Pos (3U)
17334#define TSC_CR_SYNCPOL_Msk (0x1U << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
17335#define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
17336#define TSC_CR_IODEF_Pos (4U)
17337#define TSC_CR_IODEF_Msk (0x1U << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
17338#define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
17339
17340#define TSC_CR_MCV_Pos (5U)
17341#define TSC_CR_MCV_Msk (0x7U << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
17342#define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
17343#define TSC_CR_MCV_0 (0x1U << TSC_CR_MCV_Pos) /*!< 0x00000020 */
17344#define TSC_CR_MCV_1 (0x2U << TSC_CR_MCV_Pos) /*!< 0x00000040 */
17345#define TSC_CR_MCV_2 (0x4U << TSC_CR_MCV_Pos) /*!< 0x00000080 */
17346
17347#define TSC_CR_PGPSC_Pos (12U)
17348#define TSC_CR_PGPSC_Msk (0x7U << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
17349#define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
17350#define TSC_CR_PGPSC_0 (0x1U << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
17351#define TSC_CR_PGPSC_1 (0x2U << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
17352#define TSC_CR_PGPSC_2 (0x4U << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
17353
17354#define TSC_CR_SSPSC_Pos (15U)
17355#define TSC_CR_SSPSC_Msk (0x1U << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
17356#define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
17357#define TSC_CR_SSE_Pos (16U)
17358#define TSC_CR_SSE_Msk (0x1U << TSC_CR_SSE_Pos) /*!< 0x00010000 */
17359#define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
17360
17361#define TSC_CR_SSD_Pos (17U)
17362#define TSC_CR_SSD_Msk (0x7FU << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
17363#define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
17364#define TSC_CR_SSD_0 (0x01U << TSC_CR_SSD_Pos) /*!< 0x00020000 */
17365#define TSC_CR_SSD_1 (0x02U << TSC_CR_SSD_Pos) /*!< 0x00040000 */
17366#define TSC_CR_SSD_2 (0x04U << TSC_CR_SSD_Pos) /*!< 0x00080000 */
17367#define TSC_CR_SSD_3 (0x08U << TSC_CR_SSD_Pos) /*!< 0x00100000 */
17368#define TSC_CR_SSD_4 (0x10U << TSC_CR_SSD_Pos) /*!< 0x00200000 */
17369#define TSC_CR_SSD_5 (0x20U << TSC_CR_SSD_Pos) /*!< 0x00400000 */
17370#define TSC_CR_SSD_6 (0x40U << TSC_CR_SSD_Pos) /*!< 0x00800000 */
17371
17372#define TSC_CR_CTPL_Pos (24U)
17373#define TSC_CR_CTPL_Msk (0xFU << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
17374#define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
17375#define TSC_CR_CTPL_0 (0x1U << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
17376#define TSC_CR_CTPL_1 (0x2U << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
17377#define TSC_CR_CTPL_2 (0x4U << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
17378#define TSC_CR_CTPL_3 (0x8U << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
17379
17380#define TSC_CR_CTPH_Pos (28U)
17381#define TSC_CR_CTPH_Msk (0xFU << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
17382#define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
17383#define TSC_CR_CTPH_0 (0x1U << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
17384#define TSC_CR_CTPH_1 (0x2U << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
17385#define TSC_CR_CTPH_2 (0x4U << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
17386#define TSC_CR_CTPH_3 (0x8U << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
17387
17388/******************* Bit definition for TSC_IER register ********************/
17389#define TSC_IER_EOAIE_Pos (0U)
17390#define TSC_IER_EOAIE_Msk (0x1U << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
17391#define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
17392#define TSC_IER_MCEIE_Pos (1U)
17393#define TSC_IER_MCEIE_Msk (0x1U << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
17394#define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
17395
17396/******************* Bit definition for TSC_ICR register ********************/
17397#define TSC_ICR_EOAIC_Pos (0U)
17398#define TSC_ICR_EOAIC_Msk (0x1U << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
17399#define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
17400#define TSC_ICR_MCEIC_Pos (1U)
17401#define TSC_ICR_MCEIC_Msk (0x1U << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
17402#define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
17403
17404/******************* Bit definition for TSC_ISR register ********************/
17405#define TSC_ISR_EOAF_Pos (0U)
17406#define TSC_ISR_EOAF_Msk (0x1U << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
17407#define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
17408#define TSC_ISR_MCEF_Pos (1U)
17409#define TSC_ISR_MCEF_Msk (0x1U << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
17410#define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
17411
17412/******************* Bit definition for TSC_IOHCR register ******************/
17413#define TSC_IOHCR_G1_IO1_Pos (0U)
17414#define TSC_IOHCR_G1_IO1_Msk (0x1U << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
17415#define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
17416#define TSC_IOHCR_G1_IO2_Pos (1U)
17417#define TSC_IOHCR_G1_IO2_Msk (0x1U << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
17418#define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
17419#define TSC_IOHCR_G1_IO3_Pos (2U)
17420#define TSC_IOHCR_G1_IO3_Msk (0x1U << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
17421#define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
17422#define TSC_IOHCR_G1_IO4_Pos (3U)
17423#define TSC_IOHCR_G1_IO4_Msk (0x1U << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
17424#define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
17425#define TSC_IOHCR_G2_IO1_Pos (4U)
17426#define TSC_IOHCR_G2_IO1_Msk (0x1U << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
17427#define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
17428#define TSC_IOHCR_G2_IO2_Pos (5U)
17429#define TSC_IOHCR_G2_IO2_Msk (0x1U << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
17430#define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
17431#define TSC_IOHCR_G2_IO3_Pos (6U)
17432#define TSC_IOHCR_G2_IO3_Msk (0x1U << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
17433#define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
17434#define TSC_IOHCR_G2_IO4_Pos (7U)
17435#define TSC_IOHCR_G2_IO4_Msk (0x1U << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
17436#define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
17437#define TSC_IOHCR_G3_IO1_Pos (8U)
17438#define TSC_IOHCR_G3_IO1_Msk (0x1U << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
17439#define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
17440#define TSC_IOHCR_G3_IO2_Pos (9U)
17441#define TSC_IOHCR_G3_IO2_Msk (0x1U << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
17442#define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
17443#define TSC_IOHCR_G3_IO3_Pos (10U)
17444#define TSC_IOHCR_G3_IO3_Msk (0x1U << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
17445#define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
17446#define TSC_IOHCR_G3_IO4_Pos (11U)
17447#define TSC_IOHCR_G3_IO4_Msk (0x1U << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
17448#define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
17449#define TSC_IOHCR_G4_IO1_Pos (12U)
17450#define TSC_IOHCR_G4_IO1_Msk (0x1U << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
17451#define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
17452#define TSC_IOHCR_G4_IO2_Pos (13U)
17453#define TSC_IOHCR_G4_IO2_Msk (0x1U << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
17454#define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
17455#define TSC_IOHCR_G4_IO3_Pos (14U)
17456#define TSC_IOHCR_G4_IO3_Msk (0x1U << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
17457#define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
17458#define TSC_IOHCR_G4_IO4_Pos (15U)
17459#define TSC_IOHCR_G4_IO4_Msk (0x1U << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
17460#define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
17461#define TSC_IOHCR_G5_IO1_Pos (16U)
17462#define TSC_IOHCR_G5_IO1_Msk (0x1U << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
17463#define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
17464#define TSC_IOHCR_G5_IO2_Pos (17U)
17465#define TSC_IOHCR_G5_IO2_Msk (0x1U << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
17466#define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
17467#define TSC_IOHCR_G5_IO3_Pos (18U)
17468#define TSC_IOHCR_G5_IO3_Msk (0x1U << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
17469#define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
17470#define TSC_IOHCR_G5_IO4_Pos (19U)
17471#define TSC_IOHCR_G5_IO4_Msk (0x1U << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
17472#define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
17473#define TSC_IOHCR_G6_IO1_Pos (20U)
17474#define TSC_IOHCR_G6_IO1_Msk (0x1U << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
17475#define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
17476#define TSC_IOHCR_G6_IO2_Pos (21U)
17477#define TSC_IOHCR_G6_IO2_Msk (0x1U << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
17478#define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
17479#define TSC_IOHCR_G6_IO3_Pos (22U)
17480#define TSC_IOHCR_G6_IO3_Msk (0x1U << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
17481#define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
17482#define TSC_IOHCR_G6_IO4_Pos (23U)
17483#define TSC_IOHCR_G6_IO4_Msk (0x1U << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
17484#define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
17485#define TSC_IOHCR_G7_IO1_Pos (24U)
17486#define TSC_IOHCR_G7_IO1_Msk (0x1U << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
17487#define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
17488#define TSC_IOHCR_G7_IO2_Pos (25U)
17489#define TSC_IOHCR_G7_IO2_Msk (0x1U << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
17490#define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
17491#define TSC_IOHCR_G7_IO3_Pos (26U)
17492#define TSC_IOHCR_G7_IO3_Msk (0x1U << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
17493#define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
17494#define TSC_IOHCR_G7_IO4_Pos (27U)
17495#define TSC_IOHCR_G7_IO4_Msk (0x1U << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
17496#define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
17497#define TSC_IOHCR_G8_IO1_Pos (28U)
17498#define TSC_IOHCR_G8_IO1_Msk (0x1U << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */
17499#define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
17500#define TSC_IOHCR_G8_IO2_Pos (29U)
17501#define TSC_IOHCR_G8_IO2_Msk (0x1U << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */
17502#define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
17503#define TSC_IOHCR_G8_IO3_Pos (30U)
17504#define TSC_IOHCR_G8_IO3_Msk (0x1U << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */
17505#define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
17506#define TSC_IOHCR_G8_IO4_Pos (31U)
17507#define TSC_IOHCR_G8_IO4_Msk (0x1U << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */
17508#define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
17509
17510/******************* Bit definition for TSC_IOASCR register *****************/
17511#define TSC_IOASCR_G1_IO1_Pos (0U)
17512#define TSC_IOASCR_G1_IO1_Msk (0x1U << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
17513#define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
17514#define TSC_IOASCR_G1_IO2_Pos (1U)
17515#define TSC_IOASCR_G1_IO2_Msk (0x1U << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
17516#define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
17517#define TSC_IOASCR_G1_IO3_Pos (2U)
17518#define TSC_IOASCR_G1_IO3_Msk (0x1U << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
17519#define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
17520#define TSC_IOASCR_G1_IO4_Pos (3U)
17521#define TSC_IOASCR_G1_IO4_Msk (0x1U << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
17522#define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
17523#define TSC_IOASCR_G2_IO1_Pos (4U)
17524#define TSC_IOASCR_G2_IO1_Msk (0x1U << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
17525#define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
17526#define TSC_IOASCR_G2_IO2_Pos (5U)
17527#define TSC_IOASCR_G2_IO2_Msk (0x1U << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
17528#define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
17529#define TSC_IOASCR_G2_IO3_Pos (6U)
17530#define TSC_IOASCR_G2_IO3_Msk (0x1U << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
17531#define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
17532#define TSC_IOASCR_G2_IO4_Pos (7U)
17533#define TSC_IOASCR_G2_IO4_Msk (0x1U << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
17534#define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
17535#define TSC_IOASCR_G3_IO1_Pos (8U)
17536#define TSC_IOASCR_G3_IO1_Msk (0x1U << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
17537#define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
17538#define TSC_IOASCR_G3_IO2_Pos (9U)
17539#define TSC_IOASCR_G3_IO2_Msk (0x1U << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
17540#define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
17541#define TSC_IOASCR_G3_IO3_Pos (10U)
17542#define TSC_IOASCR_G3_IO3_Msk (0x1U << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
17543#define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
17544#define TSC_IOASCR_G3_IO4_Pos (11U)
17545#define TSC_IOASCR_G3_IO4_Msk (0x1U << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
17546#define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
17547#define TSC_IOASCR_G4_IO1_Pos (12U)
17548#define TSC_IOASCR_G4_IO1_Msk (0x1U << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
17549#define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
17550#define TSC_IOASCR_G4_IO2_Pos (13U)
17551#define TSC_IOASCR_G4_IO2_Msk (0x1U << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
17552#define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
17553#define TSC_IOASCR_G4_IO3_Pos (14U)
17554#define TSC_IOASCR_G4_IO3_Msk (0x1U << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
17555#define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
17556#define TSC_IOASCR_G4_IO4_Pos (15U)
17557#define TSC_IOASCR_G4_IO4_Msk (0x1U << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
17558#define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
17559#define TSC_IOASCR_G5_IO1_Pos (16U)
17560#define TSC_IOASCR_G5_IO1_Msk (0x1U << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
17561#define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
17562#define TSC_IOASCR_G5_IO2_Pos (17U)
17563#define TSC_IOASCR_G5_IO2_Msk (0x1U << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
17564#define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
17565#define TSC_IOASCR_G5_IO3_Pos (18U)
17566#define TSC_IOASCR_G5_IO3_Msk (0x1U << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
17567#define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
17568#define TSC_IOASCR_G5_IO4_Pos (19U)
17569#define TSC_IOASCR_G5_IO4_Msk (0x1U << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
17570#define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
17571#define TSC_IOASCR_G6_IO1_Pos (20U)
17572#define TSC_IOASCR_G6_IO1_Msk (0x1U << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
17573#define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
17574#define TSC_IOASCR_G6_IO2_Pos (21U)
17575#define TSC_IOASCR_G6_IO2_Msk (0x1U << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
17576#define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
17577#define TSC_IOASCR_G6_IO3_Pos (22U)
17578#define TSC_IOASCR_G6_IO3_Msk (0x1U << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
17579#define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
17580#define TSC_IOASCR_G6_IO4_Pos (23U)
17581#define TSC_IOASCR_G6_IO4_Msk (0x1U << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
17582#define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
17583#define TSC_IOASCR_G7_IO1_Pos (24U)
17584#define TSC_IOASCR_G7_IO1_Msk (0x1U << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
17585#define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
17586#define TSC_IOASCR_G7_IO2_Pos (25U)
17587#define TSC_IOASCR_G7_IO2_Msk (0x1U << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
17588#define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
17589#define TSC_IOASCR_G7_IO3_Pos (26U)
17590#define TSC_IOASCR_G7_IO3_Msk (0x1U << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
17591#define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
17592#define TSC_IOASCR_G7_IO4_Pos (27U)
17593#define TSC_IOASCR_G7_IO4_Msk (0x1U << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
17594#define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
17595#define TSC_IOASCR_G8_IO1_Pos (28U)
17596#define TSC_IOASCR_G8_IO1_Msk (0x1U << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */
17597#define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */
17598#define TSC_IOASCR_G8_IO2_Pos (29U)
17599#define TSC_IOASCR_G8_IO2_Msk (0x1U << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */
17600#define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */
17601#define TSC_IOASCR_G8_IO3_Pos (30U)
17602#define TSC_IOASCR_G8_IO3_Msk (0x1U << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */
17603#define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */
17604#define TSC_IOASCR_G8_IO4_Pos (31U)
17605#define TSC_IOASCR_G8_IO4_Msk (0x1U << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */
17606#define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */
17607
17608/******************* Bit definition for TSC_IOSCR register ******************/
17609#define TSC_IOSCR_G1_IO1_Pos (0U)
17610#define TSC_IOSCR_G1_IO1_Msk (0x1U << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
17611#define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
17612#define TSC_IOSCR_G1_IO2_Pos (1U)
17613#define TSC_IOSCR_G1_IO2_Msk (0x1U << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
17614#define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
17615#define TSC_IOSCR_G1_IO3_Pos (2U)
17616#define TSC_IOSCR_G1_IO3_Msk (0x1U << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
17617#define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
17618#define TSC_IOSCR_G1_IO4_Pos (3U)
17619#define TSC_IOSCR_G1_IO4_Msk (0x1U << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
17620#define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
17621#define TSC_IOSCR_G2_IO1_Pos (4U)
17622#define TSC_IOSCR_G2_IO1_Msk (0x1U << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
17623#define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
17624#define TSC_IOSCR_G2_IO2_Pos (5U)
17625#define TSC_IOSCR_G2_IO2_Msk (0x1U << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
17626#define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
17627#define TSC_IOSCR_G2_IO3_Pos (6U)
17628#define TSC_IOSCR_G2_IO3_Msk (0x1U << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
17629#define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
17630#define TSC_IOSCR_G2_IO4_Pos (7U)
17631#define TSC_IOSCR_G2_IO4_Msk (0x1U << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
17632#define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
17633#define TSC_IOSCR_G3_IO1_Pos (8U)
17634#define TSC_IOSCR_G3_IO1_Msk (0x1U << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
17635#define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
17636#define TSC_IOSCR_G3_IO2_Pos (9U)
17637#define TSC_IOSCR_G3_IO2_Msk (0x1U << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
17638#define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
17639#define TSC_IOSCR_G3_IO3_Pos (10U)
17640#define TSC_IOSCR_G3_IO3_Msk (0x1U << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
17641#define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
17642#define TSC_IOSCR_G3_IO4_Pos (11U)
17643#define TSC_IOSCR_G3_IO4_Msk (0x1U << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
17644#define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
17645#define TSC_IOSCR_G4_IO1_Pos (12U)
17646#define TSC_IOSCR_G4_IO1_Msk (0x1U << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
17647#define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
17648#define TSC_IOSCR_G4_IO2_Pos (13U)
17649#define TSC_IOSCR_G4_IO2_Msk (0x1U << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
17650#define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
17651#define TSC_IOSCR_G4_IO3_Pos (14U)
17652#define TSC_IOSCR_G4_IO3_Msk (0x1U << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
17653#define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
17654#define TSC_IOSCR_G4_IO4_Pos (15U)
17655#define TSC_IOSCR_G4_IO4_Msk (0x1U << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
17656#define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
17657#define TSC_IOSCR_G5_IO1_Pos (16U)
17658#define TSC_IOSCR_G5_IO1_Msk (0x1U << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
17659#define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
17660#define TSC_IOSCR_G5_IO2_Pos (17U)
17661#define TSC_IOSCR_G5_IO2_Msk (0x1U << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
17662#define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
17663#define TSC_IOSCR_G5_IO3_Pos (18U)
17664#define TSC_IOSCR_G5_IO3_Msk (0x1U << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
17665#define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
17666#define TSC_IOSCR_G5_IO4_Pos (19U)
17667#define TSC_IOSCR_G5_IO4_Msk (0x1U << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
17668#define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
17669#define TSC_IOSCR_G6_IO1_Pos (20U)
17670#define TSC_IOSCR_G6_IO1_Msk (0x1U << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
17671#define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
17672#define TSC_IOSCR_G6_IO2_Pos (21U)
17673#define TSC_IOSCR_G6_IO2_Msk (0x1U << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
17674#define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
17675#define TSC_IOSCR_G6_IO3_Pos (22U)
17676#define TSC_IOSCR_G6_IO3_Msk (0x1U << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
17677#define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
17678#define TSC_IOSCR_G6_IO4_Pos (23U)
17679#define TSC_IOSCR_G6_IO4_Msk (0x1U << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
17680#define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
17681#define TSC_IOSCR_G7_IO1_Pos (24U)
17682#define TSC_IOSCR_G7_IO1_Msk (0x1U << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
17683#define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
17684#define TSC_IOSCR_G7_IO2_Pos (25U)
17685#define TSC_IOSCR_G7_IO2_Msk (0x1U << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
17686#define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
17687#define TSC_IOSCR_G7_IO3_Pos (26U)
17688#define TSC_IOSCR_G7_IO3_Msk (0x1U << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
17689#define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
17690#define TSC_IOSCR_G7_IO4_Pos (27U)
17691#define TSC_IOSCR_G7_IO4_Msk (0x1U << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
17692#define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
17693#define TSC_IOSCR_G8_IO1_Pos (28U)
17694#define TSC_IOSCR_G8_IO1_Msk (0x1U << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */
17695#define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */
17696#define TSC_IOSCR_G8_IO2_Pos (29U)
17697#define TSC_IOSCR_G8_IO2_Msk (0x1U << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */
17698#define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */
17699#define TSC_IOSCR_G8_IO3_Pos (30U)
17700#define TSC_IOSCR_G8_IO3_Msk (0x1U << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */
17701#define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */
17702#define TSC_IOSCR_G8_IO4_Pos (31U)
17703#define TSC_IOSCR_G8_IO4_Msk (0x1U << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */
17704#define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */
17705
17706/******************* Bit definition for TSC_IOCCR register ******************/
17707#define TSC_IOCCR_G1_IO1_Pos (0U)
17708#define TSC_IOCCR_G1_IO1_Msk (0x1U << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
17709#define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
17710#define TSC_IOCCR_G1_IO2_Pos (1U)
17711#define TSC_IOCCR_G1_IO2_Msk (0x1U << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
17712#define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
17713#define TSC_IOCCR_G1_IO3_Pos (2U)
17714#define TSC_IOCCR_G1_IO3_Msk (0x1U << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
17715#define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
17716#define TSC_IOCCR_G1_IO4_Pos (3U)
17717#define TSC_IOCCR_G1_IO4_Msk (0x1U << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
17718#define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
17719#define TSC_IOCCR_G2_IO1_Pos (4U)
17720#define TSC_IOCCR_G2_IO1_Msk (0x1U << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
17721#define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
17722#define TSC_IOCCR_G2_IO2_Pos (5U)
17723#define TSC_IOCCR_G2_IO2_Msk (0x1U << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
17724#define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
17725#define TSC_IOCCR_G2_IO3_Pos (6U)
17726#define TSC_IOCCR_G2_IO3_Msk (0x1U << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
17727#define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
17728#define TSC_IOCCR_G2_IO4_Pos (7U)
17729#define TSC_IOCCR_G2_IO4_Msk (0x1U << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
17730#define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
17731#define TSC_IOCCR_G3_IO1_Pos (8U)
17732#define TSC_IOCCR_G3_IO1_Msk (0x1U << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
17733#define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
17734#define TSC_IOCCR_G3_IO2_Pos (9U)
17735#define TSC_IOCCR_G3_IO2_Msk (0x1U << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
17736#define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
17737#define TSC_IOCCR_G3_IO3_Pos (10U)
17738#define TSC_IOCCR_G3_IO3_Msk (0x1U << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
17739#define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
17740#define TSC_IOCCR_G3_IO4_Pos (11U)
17741#define TSC_IOCCR_G3_IO4_Msk (0x1U << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
17742#define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
17743#define TSC_IOCCR_G4_IO1_Pos (12U)
17744#define TSC_IOCCR_G4_IO1_Msk (0x1U << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
17745#define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
17746#define TSC_IOCCR_G4_IO2_Pos (13U)
17747#define TSC_IOCCR_G4_IO2_Msk (0x1U << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
17748#define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
17749#define TSC_IOCCR_G4_IO3_Pos (14U)
17750#define TSC_IOCCR_G4_IO3_Msk (0x1U << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
17751#define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
17752#define TSC_IOCCR_G4_IO4_Pos (15U)
17753#define TSC_IOCCR_G4_IO4_Msk (0x1U << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
17754#define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
17755#define TSC_IOCCR_G5_IO1_Pos (16U)
17756#define TSC_IOCCR_G5_IO1_Msk (0x1U << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
17757#define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
17758#define TSC_IOCCR_G5_IO2_Pos (17U)
17759#define TSC_IOCCR_G5_IO2_Msk (0x1U << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
17760#define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
17761#define TSC_IOCCR_G5_IO3_Pos (18U)
17762#define TSC_IOCCR_G5_IO3_Msk (0x1U << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
17763#define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
17764#define TSC_IOCCR_G5_IO4_Pos (19U)
17765#define TSC_IOCCR_G5_IO4_Msk (0x1U << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
17766#define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
17767#define TSC_IOCCR_G6_IO1_Pos (20U)
17768#define TSC_IOCCR_G6_IO1_Msk (0x1U << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
17769#define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
17770#define TSC_IOCCR_G6_IO2_Pos (21U)
17771#define TSC_IOCCR_G6_IO2_Msk (0x1U << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
17772#define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
17773#define TSC_IOCCR_G6_IO3_Pos (22U)
17774#define TSC_IOCCR_G6_IO3_Msk (0x1U << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
17775#define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
17776#define TSC_IOCCR_G6_IO4_Pos (23U)
17777#define TSC_IOCCR_G6_IO4_Msk (0x1U << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
17778#define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
17779#define TSC_IOCCR_G7_IO1_Pos (24U)
17780#define TSC_IOCCR_G7_IO1_Msk (0x1U << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
17781#define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
17782#define TSC_IOCCR_G7_IO2_Pos (25U)
17783#define TSC_IOCCR_G7_IO2_Msk (0x1U << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
17784#define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
17785#define TSC_IOCCR_G7_IO3_Pos (26U)
17786#define TSC_IOCCR_G7_IO3_Msk (0x1U << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
17787#define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
17788#define TSC_IOCCR_G7_IO4_Pos (27U)
17789#define TSC_IOCCR_G7_IO4_Msk (0x1U << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
17790#define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
17791#define TSC_IOCCR_G8_IO1_Pos (28U)
17792#define TSC_IOCCR_G8_IO1_Msk (0x1U << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */
17793#define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */
17794#define TSC_IOCCR_G8_IO2_Pos (29U)
17795#define TSC_IOCCR_G8_IO2_Msk (0x1U << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */
17796#define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */
17797#define TSC_IOCCR_G8_IO3_Pos (30U)
17798#define TSC_IOCCR_G8_IO3_Msk (0x1U << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */
17799#define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */
17800#define TSC_IOCCR_G8_IO4_Pos (31U)
17801#define TSC_IOCCR_G8_IO4_Msk (0x1U << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */
17802#define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */
17803
17804/******************* Bit definition for TSC_IOGCSR register *****************/
17805#define TSC_IOGCSR_G1E_Pos (0U)
17806#define TSC_IOGCSR_G1E_Msk (0x1U << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
17807#define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
17808#define TSC_IOGCSR_G2E_Pos (1U)
17809#define TSC_IOGCSR_G2E_Msk (0x1U << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
17810#define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
17811#define TSC_IOGCSR_G3E_Pos (2U)
17812#define TSC_IOGCSR_G3E_Msk (0x1U << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
17813#define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
17814#define TSC_IOGCSR_G4E_Pos (3U)
17815#define TSC_IOGCSR_G4E_Msk (0x1U << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
17816#define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
17817#define TSC_IOGCSR_G5E_Pos (4U)
17818#define TSC_IOGCSR_G5E_Msk (0x1U << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
17819#define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
17820#define TSC_IOGCSR_G6E_Pos (5U)
17821#define TSC_IOGCSR_G6E_Msk (0x1U << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
17822#define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
17823#define TSC_IOGCSR_G7E_Pos (6U)
17824#define TSC_IOGCSR_G7E_Msk (0x1U << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
17825#define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
17826#define TSC_IOGCSR_G8E_Pos (7U)
17827#define TSC_IOGCSR_G8E_Msk (0x1U << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */
17828#define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */
17829#define TSC_IOGCSR_G1S_Pos (16U)
17830#define TSC_IOGCSR_G1S_Msk (0x1U << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
17831#define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
17832#define TSC_IOGCSR_G2S_Pos (17U)
17833#define TSC_IOGCSR_G2S_Msk (0x1U << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
17834#define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
17835#define TSC_IOGCSR_G3S_Pos (18U)
17836#define TSC_IOGCSR_G3S_Msk (0x1U << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
17837#define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
17838#define TSC_IOGCSR_G4S_Pos (19U)
17839#define TSC_IOGCSR_G4S_Msk (0x1U << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
17840#define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
17841#define TSC_IOGCSR_G5S_Pos (20U)
17842#define TSC_IOGCSR_G5S_Msk (0x1U << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
17843#define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
17844#define TSC_IOGCSR_G6S_Pos (21U)
17845#define TSC_IOGCSR_G6S_Msk (0x1U << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
17846#define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
17847#define TSC_IOGCSR_G7S_Pos (22U)
17848#define TSC_IOGCSR_G7S_Msk (0x1U << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
17849#define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
17850#define TSC_IOGCSR_G8S_Pos (23U)
17851#define TSC_IOGCSR_G8S_Msk (0x1U << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */
17852#define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */
17853
17854/******************* Bit definition for TSC_IOGXCR register *****************/
17855#define TSC_IOGXCR_CNT_Pos (0U)
17856#define TSC_IOGXCR_CNT_Msk (0x3FFFU << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
17857#define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
17858
17859/******************************************************************************/
17860/* */
17861/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
17862/* */
17863/******************************************************************************/
17864
17865/*
17866* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
17867*/
17868#define USART_TCBGT_SUPPORT
17869
17870/****************** Bit definition for USART_CR1 register *******************/
17871#define USART_CR1_UE_Pos (0U)
17872#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
17873#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
17874#define USART_CR1_UESM_Pos (1U)
17875#define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
17876#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
17877#define USART_CR1_RE_Pos (2U)
17878#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
17879#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
17880#define USART_CR1_TE_Pos (3U)
17881#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
17882#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
17883#define USART_CR1_IDLEIE_Pos (4U)
17884#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
17885#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
17886#define USART_CR1_RXNEIE_RXFNEIE_Pos (5U)
17887#define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1U << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
17888#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk /*!< RXNE/RXFIFO not empty Interrupt Enable */
17889#define USART_CR1_TCIE_Pos (6U)
17890#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
17891#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
17892#define USART_CR1_TXEIE_TXFNFIE_Pos (7U)
17893#define USART_CR1_TXEIE_TXFNFIE_Msk (0x1U << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */
17894#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk /*!< TXE/TXFIFO not full Interrupt Enable */
17895#define USART_CR1_PEIE_Pos (8U)
17896#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
17897#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
17898#define USART_CR1_PS_Pos (9U)
17899#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
17900#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
17901#define USART_CR1_PCE_Pos (10U)
17902#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
17903#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
17904#define USART_CR1_WAKE_Pos (11U)
17905#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
17906#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
17907#define USART_CR1_M_Pos (12U)
17908#define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
17909#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
17910#define USART_CR1_M0_Pos (12U)
17911#define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */
17912#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
17913#define USART_CR1_MME_Pos (13U)
17914#define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
17915#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
17916#define USART_CR1_CMIE_Pos (14U)
17917#define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
17918#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
17919#define USART_CR1_OVER8_Pos (15U)
17920#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
17921#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
17922#define USART_CR1_DEDT_Pos (16U)
17923#define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
17924#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
17925#define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
17926#define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
17927#define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
17928#define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
17929#define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
17930#define USART_CR1_DEAT_Pos (21U)
17931#define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
17932#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
17933#define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
17934#define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
17935#define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
17936#define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
17937#define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
17938#define USART_CR1_RTOIE_Pos (26U)
17939#define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
17940#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
17941#define USART_CR1_EOBIE_Pos (27U)
17942#define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
17943#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
17944#define USART_CR1_M1_Pos (28U)
17945#define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */
17946#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
17947#define USART_CR1_FIFOEN_Pos (29U)
17948#define USART_CR1_FIFOEN_Msk (0x1U << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
17949#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
17950#define USART_CR1_TXFEIE_Pos (30U)
17951#define USART_CR1_TXFEIE_Msk (0x1U << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
17952#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */
17953#define USART_CR1_RXFFIE_Pos (31U)
17954#define USART_CR1_RXFFIE_Msk (0x1U << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
17955#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */
17956
17957/****************** Bit definition for USART_CR2 register *******************/
17958#define USART_CR2_SLVEN_Pos (0U)
17959#define USART_CR2_SLVEN_Msk (0x1U << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
17960#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */
17961#define USART_CR2_DIS_NSS_Pos (3U)
17962#define USART_CR2_DIS_NSS_Msk (0x1U << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
17963#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< NSS input pin disable for SPI slave selection */
17964#define USART_CR2_ADDM7_Pos (4U)
17965#define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
17966#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
17967#define USART_CR2_LBDL_Pos (5U)
17968#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
17969#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
17970#define USART_CR2_LBDIE_Pos (6U)
17971#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
17972#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
17973#define USART_CR2_LBCL_Pos (8U)
17974#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
17975#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
17976#define USART_CR2_CPHA_Pos (9U)
17977#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
17978#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
17979#define USART_CR2_CPOL_Pos (10U)
17980#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
17981#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
17982#define USART_CR2_CLKEN_Pos (11U)
17983#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
17984#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
17985#define USART_CR2_STOP_Pos (12U)
17986#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
17987#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
17988#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
17989#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
17990#define USART_CR2_LINEN_Pos (14U)
17991#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
17992#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
17993#define USART_CR2_SWAP_Pos (15U)
17994#define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
17995#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
17996#define USART_CR2_RXINV_Pos (16U)
17997#define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
17998#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
17999#define USART_CR2_TXINV_Pos (17U)
18000#define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
18001#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
18002#define USART_CR2_DATAINV_Pos (18U)
18003#define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
18004#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
18005#define USART_CR2_MSBFIRST_Pos (19U)
18006#define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
18007#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
18008#define USART_CR2_ABREN_Pos (20U)
18009#define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
18010#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
18011#define USART_CR2_ABRMODE_Pos (21U)
18012#define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
18013#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
18014#define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
18015#define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
18016#define USART_CR2_RTOEN_Pos (23U)
18017#define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
18018#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
18019#define USART_CR2_ADD_Pos (24U)
18020#define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
18021#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
18022
18023/****************** Bit definition for USART_CR3 register *******************/
18024#define USART_CR3_EIE_Pos (0U)
18025#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
18026#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
18027#define USART_CR3_IREN_Pos (1U)
18028#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
18029#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
18030#define USART_CR3_IRLP_Pos (2U)
18031#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
18032#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
18033#define USART_CR3_HDSEL_Pos (3U)
18034#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
18035#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
18036#define USART_CR3_NACK_Pos (4U)
18037#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
18038#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
18039#define USART_CR3_SCEN_Pos (5U)
18040#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
18041#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
18042#define USART_CR3_DMAR_Pos (6U)
18043#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
18044#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
18045#define USART_CR3_DMAT_Pos (7U)
18046#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
18047#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
18048#define USART_CR3_RTSE_Pos (8U)
18049#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
18050#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
18051#define USART_CR3_CTSE_Pos (9U)
18052#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
18053#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
18054#define USART_CR3_CTSIE_Pos (10U)
18055#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
18056#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
18057#define USART_CR3_ONEBIT_Pos (11U)
18058#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
18059#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
18060#define USART_CR3_OVRDIS_Pos (12U)
18061#define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
18062#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
18063#define USART_CR3_DDRE_Pos (13U)
18064#define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
18065#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
18066#define USART_CR3_DEM_Pos (14U)
18067#define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
18068#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
18069#define USART_CR3_DEP_Pos (15U)
18070#define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
18071#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
18072#define USART_CR3_SCARCNT_Pos (17U)
18073#define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
18074#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
18075#define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
18076#define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
18077#define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
18078#define USART_CR3_WUS_Pos (20U)
18079#define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
18080#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
18081#define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
18082#define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
18083#define USART_CR3_WUFIE_Pos (22U)
18084#define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
18085#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
18086#define USART_CR3_TXFTIE_Pos (23U)
18087#define USART_CR3_TXFTIE_Msk (0x1U << USART_CR3_TXFTIE_Pos) /*!< 0x02000000 */
18088#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */
18089#define USART_CR3_TCBGTIE_Pos (24U)
18090#define USART_CR3_TCBGTIE_Msk (0x1U << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
18091#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
18092#define USART_CR3_RXFTCFG_Pos (25U)
18093#define USART_CR3_RXFTCFG_Msk (0x7U << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
18094#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFTCFG[2:0] bits (RXFIFO threshold configuration) */
18095#define USART_CR3_RXFTCFG_0 (0x1U << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
18096#define USART_CR3_RXFTCFG_1 (0x2U << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
18097#define USART_CR3_RXFTCFG_2 (0x4U << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
18098#define USART_CR3_RXFTIE_Pos (28U)
18099#define USART_CR3_RXFTIE_Msk (0x1U << USART_CR3_RXFTIE_Pos) /*!< 0x02000000 */
18100#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */
18101#define USART_CR3_TXFTCFG_Pos (29U)
18102#define USART_CR3_TXFTCFG_Msk (0x7U << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
18103#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFTCFG[2:0] bits (TXFIFO threshold configuration) */
18104#define USART_CR3_TXFTCFG_0 (0x1U << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
18105#define USART_CR3_TXFTCFG_1 (0x2U << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
18106#define USART_CR3_TXFTCFG_2 (0x4U << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
18107
18108/****************** Bit definition for USART_BRR register *******************/
18109#define USART_BRR_DIV_FRACTION_Pos (0U)
18110#define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
18111#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
18112#define USART_BRR_DIV_MANTISSA_Pos (4U)
18113#define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
18114#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
18115
18116/****************** Bit definition for USART_GTPR register ******************/
18117#define USART_GTPR_PSC_Pos (0U)
18118#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
18119#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
18120#define USART_GTPR_GT_Pos (8U)
18121#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
18122#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
18123
18124/******************* Bit definition for USART_RTOR register *****************/
18125#define USART_RTOR_RTO_Pos (0U)
18126#define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
18127#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
18128#define USART_RTOR_BLEN_Pos (24U)
18129#define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
18130#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
18131
18132/******************* Bit definition for USART_RQR register ******************/
18133#define USART_RQR_ABRRQ_Pos (0U)
18134#define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
18135#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
18136#define USART_RQR_SBKRQ_Pos (1U)
18137#define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
18138#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
18139#define USART_RQR_MMRQ_Pos (2U)
18140#define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
18141#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
18142#define USART_RQR_RXFRQ_Pos (3U)
18143#define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
18144#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
18145#define USART_RQR_TXFRQ_Pos (4U)
18146#define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
18147#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
18148
18149/******************* Bit definition for USART_ISR register ******************/
18150#define USART_ISR_PE_Pos (0U)
18151#define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
18152#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
18153#define USART_ISR_FE_Pos (1U)
18154#define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
18155#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
18156#define USART_ISR_NE_Pos (2U)
18157#define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
18158#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise Error detected Flag */
18159#define USART_ISR_ORE_Pos (3U)
18160#define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
18161#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
18162#define USART_ISR_IDLE_Pos (4U)
18163#define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
18164#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
18165#define USART_ISR_RXNE_RXFNE_Pos (5U)
18166#define USART_ISR_RXNE_RXFNE_Msk (0x1U << USART_ISR_RXNE_RXFNE_Pos) /*!< 0x00000020 */
18167#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk /*!< Read Data Register Not Empty/RXFIFO Not Empty */
18168#define USART_ISR_TC_Pos (6U)
18169#define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
18170#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
18171#define USART_ISR_TXE_TXFNF_Pos (7U)
18172#define USART_ISR_TXE_TXFNF_Msk (0x1U << USART_ISR_TXE_TXFNF_Pos) /*!< 0x00000080 */
18173#define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk /*!< Transmit Data Register Empty/TXFIFO Not Full */
18174#define USART_ISR_LBDF_Pos (8U)
18175#define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
18176#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
18177#define USART_ISR_CTSIF_Pos (9U)
18178#define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
18179#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
18180#define USART_ISR_CTS_Pos (10U)
18181#define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
18182#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
18183#define USART_ISR_RTOF_Pos (11U)
18184#define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
18185#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
18186#define USART_ISR_EOBF_Pos (12U)
18187#define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
18188#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
18189#define USART_ISR_UDR_Pos (13U)
18190#define USART_ISR_UDR_Msk (0x1U << USART_ISR_UDR_Pos) /*!< 0x00002000 */
18191#define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI Slave Underrun Error Flag */
18192#define USART_ISR_ABRE_Pos (14U)
18193#define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
18194#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
18195#define USART_ISR_ABRF_Pos (15U)
18196#define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
18197#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
18198#define USART_ISR_BUSY_Pos (16U)
18199#define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
18200#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
18201#define USART_ISR_CMF_Pos (17U)
18202#define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
18203#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
18204#define USART_ISR_SBKF_Pos (18U)
18205#define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
18206#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
18207#define USART_ISR_RWU_Pos (19U)
18208#define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
18209#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
18210#define USART_ISR_WUF_Pos (20U)
18211#define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
18212#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
18213#define USART_ISR_TEACK_Pos (21U)
18214#define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
18215#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
18216#define USART_ISR_REACK_Pos (22U)
18217#define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
18218#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
18219#define USART_ISR_TXFE_Pos (23U)
18220#define USART_ISR_TXFE_Msk (0x1U << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
18221#define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty Flag */
18222#define USART_ISR_RXFF_Pos (24U)
18223#define USART_ISR_RXFF_Msk (0x1U << USART_ISR_RXFF_Pos) /*!< 0x00800000 */
18224#define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full Flag */
18225#define USART_ISR_TCBGT_Pos (25U)
18226#define USART_ISR_TCBGT_Msk (0x1U << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
18227#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time Completion Flag */
18228#define USART_ISR_RXFT_Pos (26U)
18229#define USART_ISR_RXFT_Msk (0x1U << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
18230#define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO Threshold Flag */
18231#define USART_ISR_TXFT_Pos (27U)
18232#define USART_ISR_TXFT_Msk (0x1U << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
18233#define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO Threshold Flag */
18234
18235/******************* Bit definition for USART_ICR register ******************/
18236#define USART_ICR_PECF_Pos (0U)
18237#define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
18238#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
18239#define USART_ICR_FECF_Pos (1U)
18240#define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
18241#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
18242#define USART_ICR_NECF_Pos (2U)
18243#define USART_ICR_NECF_Msk (0x1U << USART_ICR_NECF_Pos) /*!< 0x00000004 */
18244#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
18245#define USART_ICR_ORECF_Pos (3U)
18246#define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
18247#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
18248#define USART_ICR_IDLECF_Pos (4U)
18249#define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
18250#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
18251#define USART_ICR_TXFECF_Pos (5U)
18252#define USART_ICR_TXFECF_Msk (0x1U << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
18253#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO Empty Clear Flag */
18254#define USART_ICR_TCCF_Pos (6U)
18255#define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
18256#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
18257#define USART_ICR_TCBGTCF_Pos (7U)
18258#define USART_ICR_TCBGTCF_Msk (0x1U << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
18259#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
18260#define USART_ICR_LBDCF_Pos (8U)
18261#define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
18262#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
18263#define USART_ICR_CTSCF_Pos (9U)
18264#define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
18265#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
18266#define USART_ICR_RTOCF_Pos (11U)
18267#define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
18268#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
18269#define USART_ICR_EOBCF_Pos (12U)
18270#define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
18271#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
18272#define USART_ICR_UDRCF_Pos (13U)
18273#define USART_ICR_UDRCF_Msk (0x1U << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
18274#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */
18275#define USART_ICR_CMCF_Pos (17U)
18276#define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
18277#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
18278#define USART_ICR_WUCF_Pos (20U)
18279#define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
18280#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
18281
18282/* Legacy defines */
18283#define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
18284#define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
18285#define USART_ICR_NCF USART_ICR_NECF
18286
18287/******************* Bit definition for USART_RDR register ******************/
18288#define USART_RDR_RDR_Pos (0U)
18289#define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */
18290#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
18291
18292/******************* Bit definition for USART_TDR register ******************/
18293#define USART_TDR_TDR_Pos (0U)
18294#define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */
18295#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
18296
18297/******************* Bit definition for USART_PRESC register ******************/
18298#define USART_PRESC_PRESCALER_Pos (0U)
18299#define USART_PRESC_PRESCALER_Msk (0xFU << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
18300#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
18301#define USART_PRESC_PRESCALER_0 (0x1U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
18302#define USART_PRESC_PRESCALER_1 (0x2U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
18303#define USART_PRESC_PRESCALER_2 (0x4U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
18304#define USART_PRESC_PRESCALER_3 (0x8U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
18305
18306/******************************************************************************/
18307/* */
18308/* VREFBUF */
18309/* */
18310/******************************************************************************/
18311/******************* Bit definition for VREFBUF_CSR register ****************/
18312#define VREFBUF_CSR_ENVR_Pos (0U)
18313#define VREFBUF_CSR_ENVR_Msk (0x1U << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
18314#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
18315#define VREFBUF_CSR_HIZ_Pos (1U)
18316#define VREFBUF_CSR_HIZ_Msk (0x1U << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
18317#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
18318#define VREFBUF_CSR_VRS_Pos (2U)
18319#define VREFBUF_CSR_VRS_Msk (0x1U << VREFBUF_CSR_VRS_Pos) /*!< 0x00000004 */
18320#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
18321#define VREFBUF_CSR_VRR_Pos (3U)
18322#define VREFBUF_CSR_VRR_Msk (0x1U << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
18323#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
18324
18325/******************* Bit definition for VREFBUF_CCR register ******************/
18326#define VREFBUF_CCR_TRIM_Pos (0U)
18327#define VREFBUF_CCR_TRIM_Msk (0x3FU << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
18328#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
18329
18330/******************************************************************************/
18331/* */
18332/* Window WATCHDOG */
18333/* */
18334/******************************************************************************/
18335/******************* Bit definition for WWDG_CR register ********************/
18336#define WWDG_CR_T_Pos (0U)
18337#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
18338#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
18339#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
18340#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
18341#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
18342#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
18343#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
18344#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
18345#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
18346
18347#define WWDG_CR_WDGA_Pos (7U)
18348#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
18349#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
18350
18351/******************* Bit definition for WWDG_CFR register *******************/
18352#define WWDG_CFR_W_Pos (0U)
18353#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
18354#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
18355#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
18356#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
18357#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
18358#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
18359#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
18360#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
18361#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
18362
18363#define WWDG_CFR_WDGTB_Pos (7U)
18364#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
18365#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
18366#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
18367#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
18368
18369#define WWDG_CFR_EWI_Pos (9U)
18370#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
18371#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
18372
18373/******************* Bit definition for WWDG_SR register ********************/
18374#define WWDG_SR_EWIF_Pos (0U)
18375#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
18376#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
18377
18378
18379/******************************************************************************/
18380/* */
18381/* Debug MCU */
18382/* */
18383/******************************************************************************/
18384/******************** Bit definition for DBGMCU_IDCODE register *************/
18385#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
18386#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
18387#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
18388#define DBGMCU_IDCODE_REV_ID_Pos (16U)
18389#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
18390#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
18391
18392/******************** Bit definition for DBGMCU_CR register *****************/
18393#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
18394#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
18395#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
18396#define DBGMCU_CR_DBG_STOP_Pos (1U)
18397#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
18398#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
18399#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
18400#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
18401#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
18402#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
18403#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
18404#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
18405
18406#define DBGMCU_CR_TRACE_MODE_Pos (6U)
18407#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
18408#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
18409#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
18410#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
18411
18412/******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
18413#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
18414#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
18415#define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
18416#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U)
18417#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
18418#define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
18419#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)
18420#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
18421#define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
18422#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U)
18423#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
18424#define DBGMCU_APB1FZR1_DBG_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk
18425#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
18426#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
18427#define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
18428#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
18429#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
18430#define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
18431#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
18432#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
18433#define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
18434#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
18435#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
18436#define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
18437#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
18438#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
18439#define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
18440#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
18441#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
18442#define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
18443#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)
18444#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
18445#define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
18446#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (23U)
18447#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
18448#define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
18449#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos (25U)
18450#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
18451#define DBGMCU_APB1FZR1_DBG_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk
18452#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
18453#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
18454#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
18455
18456/******************** Bit definition for DBGMCU_APB1FZR2 register **********/
18457#define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos (1U)
18458#define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk (0x1U << DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos) /*!< 0x00000002 */
18459#define DBGMCU_APB1FZR2_DBG_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk
18460#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U)
18461#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1U << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */
18462#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
18463
18464/******************** Bit definition for DBGMCU_APB2FZ register ************/
18465#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
18466#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
18467#define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
18468#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)
18469#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */
18470#define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
18471#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
18472#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
18473#define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
18474#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
18475#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
18476#define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
18477#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
18478#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
18479#define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
18480
18481/******************************************************************************/
18482/* */
18483/* USB_OTG */
18484/* */
18485/******************************************************************************/
18486/******************** Bit definition for USB_OTG_GOTGCTL register ********************/
18487#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
18488#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
18489#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
18490#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
18491#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
18492#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
18493#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
18494#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
18495#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
18496#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
18497#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
18498#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
18499#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
18500#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
18501#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
18502#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
18503#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
18504#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
18505#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
18506#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
18507#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
18508#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
18509#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
18510#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
18511#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
18512#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
18513#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/
18514
18515/******************** Bit definition for USB_OTG_HCFG register ********************/
18516
18517#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
18518#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
18519#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
18520#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
18521#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
18522#define USB_OTG_HCFG_FSLSS_Pos (2U)
18523#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
18524#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
18525
18526/******************** Bit definition for USB_OTG_DCFG register ********************/
18527
18528#define USB_OTG_DCFG_DSPD_Pos (0U)
18529#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
18530#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
18531#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
18532#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
18533#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
18534#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
18535#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
18536#define USB_OTG_DCFG_DAD_Pos (4U)
18537#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
18538#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
18539#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
18540#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
18541#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
18542#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
18543#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
18544#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
18545#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
18546#define USB_OTG_DCFG_PFIVL_Pos (11U)
18547#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
18548#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
18549#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
18550#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
18551#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
18552#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
18553#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
18554#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
18555#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
18556
18557/******************** Bit definition for USB_OTG_PCGCR register ********************/
18558#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
18559#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
18560#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
18561#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
18562#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
18563#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
18564#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
18565#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
18566#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
18567
18568/******************** Bit definition for USB_OTG_GOTGINT register ********************/
18569#define USB_OTG_GOTGINT_SEDET_Pos (2U)
18570#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
18571#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
18572#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
18573#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
18574#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
18575#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
18576#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
18577#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
18578#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
18579#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
18580#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
18581#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
18582#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
18583#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
18584#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
18585#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
18586#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
18587
18588/******************** Bit definition for USB_OTG_DCTL register ********************/
18589#define USB_OTG_DCTL_RWUSIG_Pos (0U)
18590#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
18591#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
18592#define USB_OTG_DCTL_SDIS_Pos (1U)
18593#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
18594#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
18595#define USB_OTG_DCTL_GINSTS_Pos (2U)
18596#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
18597#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
18598#define USB_OTG_DCTL_GONSTS_Pos (3U)
18599#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
18600#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
18601
18602#define USB_OTG_DCTL_TCTL_Pos (4U)
18603#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
18604#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
18605#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
18606#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
18607#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
18608#define USB_OTG_DCTL_SGINAK_Pos (7U)
18609#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
18610#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
18611#define USB_OTG_DCTL_CGINAK_Pos (8U)
18612#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
18613#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
18614#define USB_OTG_DCTL_SGONAK_Pos (9U)
18615#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
18616#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
18617#define USB_OTG_DCTL_CGONAK_Pos (10U)
18618#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
18619#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
18620#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
18621#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
18622#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
18623
18624/******************** Bit definition for USB_OTG_HFIR register ********************/
18625#define USB_OTG_HFIR_FRIVL_Pos (0U)
18626#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
18627#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
18628
18629/******************** Bit definition for USB_OTG_HFNUM register ********************/
18630#define USB_OTG_HFNUM_FRNUM_Pos (0U)
18631#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
18632#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
18633#define USB_OTG_HFNUM_FTREM_Pos (16U)
18634#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
18635#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
18636
18637/******************** Bit definition for USB_OTG_DSTS register ********************/
18638#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
18639#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
18640#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
18641
18642#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
18643#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
18644#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
18645#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
18646#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
18647#define USB_OTG_DSTS_EERR_Pos (3U)
18648#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
18649#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
18650#define USB_OTG_DSTS_FNSOF_Pos (8U)
18651#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
18652#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
18653
18654/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
18655#define USB_OTG_GAHBCFG_GINT_Pos (0U)
18656#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
18657#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
18658#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
18659#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
18660#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
18661#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
18662#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
18663#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
18664#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
18665#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
18666#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
18667#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
18668#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
18669#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
18670#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
18671#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
18672#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
18673#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
18674
18675/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
18676
18677#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
18678#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
18679#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
18680#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
18681#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
18682#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
18683#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
18684#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
18685#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
18686#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
18687#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
18688#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
18689#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
18690#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
18691#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
18692#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
18693#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
18694#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
18695#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
18696#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
18697#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
18698#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
18699#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
18700#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
18701#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
18702#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
18703#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
18704#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
18705#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
18706#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
18707#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
18708#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
18709#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
18710#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
18711#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
18712#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
18713#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
18714#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
18715#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
18716#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
18717#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
18718#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
18719#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
18720#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
18721#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
18722#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
18723#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
18724#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
18725#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
18726#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
18727#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
18728#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
18729#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
18730#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
18731#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
18732#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
18733#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
18734#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
18735#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
18736#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
18737#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
18738
18739/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
18740#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
18741#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
18742#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
18743#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
18744#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
18745#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
18746#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
18747#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
18748#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
18749#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
18750#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
18751#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
18752#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
18753#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
18754#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
18755#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
18756#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
18757#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
18758#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
18759#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
18760#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
18761#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
18762#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
18763#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
18764#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
18765#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
18766#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
18767#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
18768#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
18769
18770/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
18771#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
18772#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
18773#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
18774#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
18775#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
18776#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
18777#define USB_OTG_DIEPMSK_TOM_Pos (3U)
18778#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
18779#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
18780#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
18781#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
18782#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
18783#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
18784#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
18785#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
18786#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
18787#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
18788#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
18789#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
18790#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
18791#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
18792#define USB_OTG_DIEPMSK_BIM_Pos (9U)
18793#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
18794#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
18795
18796/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
18797#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
18798#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
18799#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
18800#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
18801#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
18802#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
18803#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
18804#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
18805#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
18806#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
18807#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
18808#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
18809#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
18810#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
18811
18812#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
18813#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
18814#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
18815#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
18816#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
18817#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
18818#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
18819#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
18820#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
18821#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
18822#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
18823
18824/******************** Bit definition for USB_OTG_HAINT register ********************/
18825#define USB_OTG_HAINT_HAINT_Pos (0U)
18826#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
18827#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
18828
18829/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
18830#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
18831#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
18832#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
18833#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
18834#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
18835#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
18836#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
18837#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
18838#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
18839#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
18840#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
18841#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
18842#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
18843#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
18844#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
18845#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
18846#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
18847#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
18848#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
18849#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
18850#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
18851
18852/******************** Bit definition for USB_OTG_GINTSTS register ********************/
18853#define USB_OTG_GINTSTS_CMOD_Pos (0U)
18854#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
18855#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
18856#define USB_OTG_GINTSTS_MMIS_Pos (1U)
18857#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
18858#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
18859#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
18860#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
18861#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
18862#define USB_OTG_GINTSTS_SOF_Pos (3U)
18863#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
18864#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
18865#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
18866#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
18867#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
18868#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
18869#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
18870#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
18871#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
18872#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
18873#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
18874#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
18875#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
18876#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
18877#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
18878#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
18879#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
18880#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
18881#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
18882#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
18883#define USB_OTG_GINTSTS_USBRST_Pos (12U)
18884#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
18885#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
18886#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
18887#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
18888#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
18889#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
18890#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
18891#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
18892#define USB_OTG_GINTSTS_EOPF_Pos (15U)
18893#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
18894#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
18895#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
18896#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
18897#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
18898#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
18899#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
18900#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
18901#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
18902#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
18903#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
18904#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
18905#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
18906#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
18907#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
18908#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
18909#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
18910#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
18911#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
18912#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
18913#define USB_OTG_GINTSTS_HCINT_Pos (25U)
18914#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
18915#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
18916#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
18917#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
18918#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
18919#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
18920#define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
18921#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
18922#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
18923#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
18924#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
18925#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
18926#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
18927#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
18928#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
18929#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
18930#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
18931#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
18932#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
18933#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
18934
18935/******************** Bit definition for USB_OTG_GINTMSK register ********************/
18936
18937#define USB_OTG_GINTMSK_MMISM_Pos (1U)
18938#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
18939#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
18940#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
18941#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
18942#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
18943#define USB_OTG_GINTMSK_SOFM_Pos (3U)
18944#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
18945#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
18946#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
18947#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
18948#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
18949#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
18950#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
18951#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
18952#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
18953#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
18954#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
18955#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
18956#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
18957#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
18958#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
18959#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
18960#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
18961#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
18962#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
18963#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
18964#define USB_OTG_GINTMSK_USBRST_Pos (12U)
18965#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
18966#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
18967#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
18968#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
18969#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
18970#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
18971#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
18972#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
18973#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
18974#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
18975#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
18976#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
18977#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
18978#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
18979#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
18980#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
18981#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
18982#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
18983#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
18984#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
18985#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
18986#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
18987#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
18988#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
18989#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
18990#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
18991#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
18992#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
18993#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
18994#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
18995#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
18996#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
18997#define USB_OTG_GINTMSK_HCIM_Pos (25U)
18998#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
18999#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
19000#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
19001#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
19002#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
19003#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
19004#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
19005#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
19006#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
19007#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
19008#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
19009#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
19010#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
19011#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
19012#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
19013#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
19014#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
19015#define USB_OTG_GINTMSK_WUIM_Pos (31U)
19016#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
19017#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
19018
19019/******************** Bit definition for USB_OTG_DAINT register ********************/
19020#define USB_OTG_DAINT_IEPINT_Pos (0U)
19021#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
19022#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
19023#define USB_OTG_DAINT_OEPINT_Pos (16U)
19024#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
19025#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
19026
19027/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
19028#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
19029#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
19030#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
19031
19032/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
19033#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
19034#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
19035#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
19036#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
19037#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
19038#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
19039#define USB_OTG_GRXSTSP_DPID_Pos (15U)
19040#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
19041#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
19042#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
19043#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
19044#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
19045
19046/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
19047#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
19048#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
19049#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
19050#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
19051#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
19052#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
19053
19054/******************** Bit definition for OTG register ********************/
19055
19056#define USB_OTG_CHNUM_Pos (0U)
19057#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
19058#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
19059#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
19060#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
19061#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
19062#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
19063#define USB_OTG_BCNT_Pos (4U)
19064#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
19065#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
19066#define USB_OTG_DPID_Pos (15U)
19067#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
19068#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
19069#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
19070#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
19071#define USB_OTG_PKTSTS_Pos (17U)
19072#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
19073#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
19074#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
19075#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
19076#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
19077#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
19078#define USB_OTG_EPNUM_Pos (0U)
19079#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
19080#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
19081#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
19082#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
19083#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
19084#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
19085#define USB_OTG_FRMNUM_Pos (21U)
19086#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
19087#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
19088#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
19089#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
19090#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
19091#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
19092
19093/******************** Bit definition for OTG register ********************/
19094
19095#define USB_OTG_CHNUM_Pos (0U)
19096#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
19097#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
19098#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
19099#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
19100#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
19101#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
19102#define USB_OTG_BCNT_Pos (4U)
19103#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
19104#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
19105#define USB_OTG_DPID_Pos (15U)
19106#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
19107#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
19108#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
19109#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
19110#define USB_OTG_PKTSTS_Pos (17U)
19111#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
19112#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
19113#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
19114#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
19115#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
19116#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
19117#define USB_OTG_EPNUM_Pos (0U)
19118#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
19119#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
19120#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
19121#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
19122#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
19123#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
19124#define USB_OTG_FRMNUM_Pos (21U)
19125#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
19126#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
19127#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
19128#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
19129#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
19130#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
19131
19132/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
19133#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
19134#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
19135#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
19136
19137/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
19138#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
19139#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
19140#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
19141
19142/******************** Bit definition for OTG register ********************/
19143#define USB_OTG_NPTXFSA_Pos (0U)
19144#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
19145#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
19146#define USB_OTG_NPTXFD_Pos (16U)
19147#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
19148#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
19149#define USB_OTG_TX0FSA_Pos (0U)
19150#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
19151#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
19152#define USB_OTG_TX0FD_Pos (16U)
19153#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
19154#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
19155
19156/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
19157#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
19158#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
19159#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
19160
19161/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
19162#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
19163#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
19164#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
19165
19166#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
19167#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
19168#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
19169#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
19170#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
19171#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
19172#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
19173#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
19174#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
19175#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
19176#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
19177
19178#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
19179#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
19180#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
19181#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
19182#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
19183#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
19184#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
19185#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
19186#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
19187#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
19188
19189/******************** Bit definition for USB_OTG_DTHRCTL register ***************/
19190#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
19191#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
19192#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
19193#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
19194#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
19195#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
19196
19197#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
19198#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
19199#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
19200#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
19201#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
19202#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
19203#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
19204#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
19205#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
19206#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
19207#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
19208#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
19209#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
19210#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
19211#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
19212
19213#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
19214#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
19215#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
19216#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
19217#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
19218#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
19219#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
19220#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
19221#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
19222#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
19223#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
19224#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
19225#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
19226#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
19227#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
19228
19229/******************** Bit definition for USB_OTG_DIEPEMPMSK register ***************/
19230#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
19231#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
19232#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
19233
19234/******************** Bit definition for USB_OTG_DEACHINT register ********************/
19235#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
19236#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
19237#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
19238#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
19239#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
19240#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
19241
19242/******************** Bit definition for USB_OTG_GCCFG register ********************/
19243#define USB_OTG_GCCFG_DCDET_Pos (0U)
19244#define USB_OTG_GCCFG_DCDET_Msk (0x1U << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
19245#define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */
19246#define USB_OTG_GCCFG_PDET_Pos (1U)
19247#define USB_OTG_GCCFG_PDET_Msk (0x1U << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
19248#define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */
19249#define USB_OTG_GCCFG_SDET_Pos (2U)
19250#define USB_OTG_GCCFG_SDET_Msk (0x1U << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
19251#define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */
19252#define USB_OTG_GCCFG_PS2DET_Pos (3U)
19253#define USB_OTG_GCCFG_PS2DET_Msk (0x1U << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
19254#define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
19255#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
19256#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
19257#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
19258#define USB_OTG_GCCFG_BCDEN_Pos (17U)
19259#define USB_OTG_GCCFG_BCDEN_Msk (0x1U << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
19260#define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */
19261#define USB_OTG_GCCFG_DCDEN_Pos (18U)
19262#define USB_OTG_GCCFG_DCDEN_Msk (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
19263#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/
19264#define USB_OTG_GCCFG_PDEN_Pos (19U)
19265#define USB_OTG_GCCFG_PDEN_Msk (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
19266#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/
19267#define USB_OTG_GCCFG_SDEN_Pos (20U)
19268#define USB_OTG_GCCFG_SDEN_Msk (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
19269#define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */
19270#define USB_OTG_GCCFG_VBDEN_Pos (21U)
19271#define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
19272#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Secondary detection (SD) mode enable */
19273
19274/******************** Bit definition for USB_OTG_GPWRDN) register ********************/
19275#define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U)
19276#define USB_OTG_GPWRDN_DISABLEVBUS_Msk (0x1U << USB_OTG_GPWRDN_DISABLEVBUS_Pos) /*!< 0x00000040 */
19277#define USB_OTG_GPWRDN_DISABLEVBUS USB_OTG_GPWRDN_DISABLEVBUS_Msk /*!< Power down */
19278
19279/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
19280#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
19281#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
19282#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
19283#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
19284#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
19285#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
19286
19287/******************** Bit definition for USB_OTG_CID register ********************/
19288#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
19289#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
19290#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
19291
19292
19293/******************** Bit definition for USB_OTG_GHWCFG3 register ********************/
19294#define USB_OTG_GHWCFG3_LPMMode_Pos (14U)
19295#define USB_OTG_GHWCFG3_LPMMode_Msk (0x1U << USB_OTG_GHWCFG3_LPMMode_Pos) /*!< 0x00004000 */
19296#define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */
19297
19298/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
19299#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
19300#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
19301#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */
19302#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
19303#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
19304#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */
19305#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
19306#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
19307#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */
19308#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
19309#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
19310#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */
19311#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
19312#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
19313#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */
19314#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U)
19315#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */
19316#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */
19317#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
19318#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
19319#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */
19320#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
19321#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
19322#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */
19323#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
19324#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
19325#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */
19326#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
19327#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
19328#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */
19329#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
19330#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
19331#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */
19332#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
19333#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
19334#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */
19335#define USB_OTG_GLPMCFG_BESL_Pos (2U)
19336#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
19337#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */
19338#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
19339#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
19340#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/
19341#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
19342#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
19343#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */
19344
19345
19346/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
19347#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
19348#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
19349#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
19350#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
19351#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
19352#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
19353#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
19354#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
19355#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
19356#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
19357#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
19358#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
19359#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
19360#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
19361#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
19362#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
19363#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
19364#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
19365#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
19366#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
19367#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
19368#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
19369#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
19370#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
19371#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
19372#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
19373#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
19374
19375/******************** Bit definition for USB_OTG_HPRT register ********************/
19376#define USB_OTG_HPRT_PCSTS_Pos (0U)
19377#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
19378#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
19379#define USB_OTG_HPRT_PCDET_Pos (1U)
19380#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
19381#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
19382#define USB_OTG_HPRT_PENA_Pos (2U)
19383#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
19384#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
19385#define USB_OTG_HPRT_PENCHNG_Pos (3U)
19386#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
19387#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
19388#define USB_OTG_HPRT_POCA_Pos (4U)
19389#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
19390#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
19391#define USB_OTG_HPRT_POCCHNG_Pos (5U)
19392#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
19393#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
19394#define USB_OTG_HPRT_PRES_Pos (6U)
19395#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
19396#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
19397#define USB_OTG_HPRT_PSUSP_Pos (7U)
19398#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
19399#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
19400#define USB_OTG_HPRT_PRST_Pos (8U)
19401#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
19402#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
19403
19404#define USB_OTG_HPRT_PLSTS_Pos (10U)
19405#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
19406#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
19407#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
19408#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
19409#define USB_OTG_HPRT_PPWR_Pos (12U)
19410#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
19411#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
19412
19413#define USB_OTG_HPRT_PTCTL_Pos (13U)
19414#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
19415#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
19416#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
19417#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
19418#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
19419#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
19420
19421#define USB_OTG_HPRT_PSPD_Pos (17U)
19422#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
19423#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
19424#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
19425#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
19426
19427/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
19428#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
19429#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
19430#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
19431#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
19432#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
19433#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
19434#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
19435#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
19436#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
19437#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
19438#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
19439#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
19440#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
19441#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
19442#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
19443#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
19444#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
19445#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
19446#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
19447#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
19448#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
19449#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
19450#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
19451#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
19452#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
19453#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
19454#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
19455#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
19456#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
19457#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
19458#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
19459#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
19460#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
19461
19462/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
19463#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
19464#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
19465#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
19466#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
19467#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
19468#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
19469
19470/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
19471#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
19472#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
19473#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
19474#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
19475#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
19476#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
19477#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
19478#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
19479#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
19480#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
19481#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
19482#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
19483
19484#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
19485#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
19486#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
19487#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
19488#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
19489#define USB_OTG_DIEPCTL_STALL_Pos (21U)
19490#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
19491#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
19492
19493#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
19494#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
19495#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
19496#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
19497#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
19498#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
19499#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
19500#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
19501#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
19502#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
19503#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
19504#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
19505#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
19506#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
19507#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
19508#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
19509#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
19510#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
19511#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
19512#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
19513#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
19514#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
19515#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
19516#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
19517#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
19518
19519/******************** Bit definition for USB_OTG_HCCHAR register ********************/
19520#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
19521#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
19522#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
19523
19524#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
19525#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
19526#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
19527#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
19528#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
19529#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
19530#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
19531#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
19532#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
19533#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
19534#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
19535#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
19536#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
19537
19538#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
19539#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
19540#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
19541#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
19542#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
19543
19544#define USB_OTG_HCCHAR_MC_Pos (20U)
19545#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
19546#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
19547#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
19548#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
19549
19550#define USB_OTG_HCCHAR_DAD_Pos (22U)
19551#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
19552#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
19553#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
19554#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
19555#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
19556#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
19557#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
19558#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
19559#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
19560#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
19561#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
19562#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
19563#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
19564#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
19565#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
19566#define USB_OTG_HCCHAR_CHENA_Pos (31U)
19567#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
19568#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
19569
19570/******************** Bit definition for USB_OTG_HCSPLT register ********************/
19571
19572#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
19573#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
19574#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
19575#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
19576#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
19577#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
19578#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
19579#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
19580#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
19581#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
19582
19583#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
19584#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
19585#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
19586#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
19587#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
19588#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
19589#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
19590#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
19591#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
19592#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
19593
19594#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
19595#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
19596#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
19597#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
19598#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
19599#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
19600#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
19601#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
19602#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
19603#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
19604#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
19605
19606/******************** Bit definition for USB_OTG_HCINT register ********************/
19607#define USB_OTG_HCINT_XFRC_Pos (0U)
19608#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
19609#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
19610#define USB_OTG_HCINT_CHH_Pos (1U)
19611#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
19612#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
19613#define USB_OTG_HCINT_AHBERR_Pos (2U)
19614#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
19615#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
19616#define USB_OTG_HCINT_STALL_Pos (3U)
19617#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
19618#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
19619#define USB_OTG_HCINT_NAK_Pos (4U)
19620#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
19621#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
19622#define USB_OTG_HCINT_ACK_Pos (5U)
19623#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
19624#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
19625#define USB_OTG_HCINT_NYET_Pos (6U)
19626#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
19627#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
19628#define USB_OTG_HCINT_TXERR_Pos (7U)
19629#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
19630#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
19631#define USB_OTG_HCINT_BBERR_Pos (8U)
19632#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
19633#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
19634#define USB_OTG_HCINT_FRMOR_Pos (9U)
19635#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
19636#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
19637#define USB_OTG_HCINT_DTERR_Pos (10U)
19638#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
19639#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
19640
19641/******************** Bit definition for USB_OTG_DIEPINT register ********************/
19642#define USB_OTG_DIEPINT_XFRC_Pos (0U)
19643#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
19644#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
19645#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
19646#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
19647#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
19648#define USB_OTG_DIEPINT_TOC_Pos (3U)
19649#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
19650#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
19651#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
19652#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
19653#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
19654#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
19655#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
19656#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
19657#define USB_OTG_DIEPINT_TXFE_Pos (7U)
19658#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
19659#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
19660#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
19661#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
19662#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
19663#define USB_OTG_DIEPINT_BNA_Pos (9U)
19664#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
19665#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
19666#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
19667#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
19668#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
19669#define USB_OTG_DIEPINT_BERR_Pos (12U)
19670#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
19671#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
19672#define USB_OTG_DIEPINT_NAK_Pos (13U)
19673#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
19674#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
19675
19676/******************** Bit definition for USB_OTG_HCINTMSK register ********************/
19677#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
19678#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
19679#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
19680#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
19681#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
19682#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
19683#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
19684#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
19685#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
19686#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
19687#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
19688#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
19689#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
19690#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
19691#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
19692#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
19693#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
19694#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
19695#define USB_OTG_HCINTMSK_NYET_Pos (6U)
19696#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
19697#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
19698#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
19699#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
19700#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
19701#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
19702#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
19703#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
19704#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
19705#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
19706#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
19707#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
19708#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
19709#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
19710
19711/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
19712
19713#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
19714#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
19715#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
19716#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
19717#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
19718#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
19719#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
19720#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
19721#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
19722/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
19723#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
19724#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
19725#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
19726#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
19727#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
19728#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
19729#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
19730#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
19731#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
19732#define USB_OTG_HCTSIZ_DPID_Pos (29U)
19733#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
19734#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
19735#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
19736#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
19737
19738/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
19739#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
19740#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
19741#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
19742
19743/******************** Bit definition for USB_OTG_HCDMA register ********************/
19744#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
19745#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
19746#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
19747
19748/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
19749#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
19750#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
19751#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space avail */
19752
19753/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
19754#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
19755#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
19756#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
19757#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
19758#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
19759#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
19760
19761/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
19762
19763#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
19764#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
19765#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
19766#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
19767#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
19768#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
19769#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
19770#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
19771#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
19772#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
19773#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
19774#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
19775#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
19776#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
19777#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
19778#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
19779#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
19780#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
19781#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
19782#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
19783#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
19784#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
19785#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
19786#define USB_OTG_DOEPCTL_STALL_Pos (21U)
19787#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
19788#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
19789#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
19790#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
19791#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
19792#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
19793#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
19794#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
19795#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
19796#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
19797#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
19798#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
19799#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
19800#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
19801
19802/******************** Bit definition for USB_OTG_DOEPINT register ********************/
19803#define USB_OTG_DOEPINT_XFRC_Pos (0U)
19804#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
19805#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
19806#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
19807#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
19808#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
19809#define USB_OTG_DOEPINT_STUP_Pos (3U)
19810#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
19811#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
19812#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
19813#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
19814#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
19815#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
19816#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
19817#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
19818#define USB_OTG_DOEPINT_NYET_Pos (14U)
19819#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
19820#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
19821
19822/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
19823
19824#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
19825#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
19826#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
19827#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
19828#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
19829#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
19830
19831#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
19832#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
19833#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
19834#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
19835#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
19836
19837/******************** Bit definition for PCGCCTL register ********************/
19838#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
19839#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
19840#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
19841#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
19842#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
19843#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
19844#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
19845#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
19846#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
19847
19848
19849/**
19850 * @}
19851 */
19852
19853/**
19854 * @}
19855 */
19856
19857/** @addtogroup Exported_macros
19858 * @{
19859 */
19860
19861/******************************* ADC Instances ********************************/
19862#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
19863
19864#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
19865
19866/******************************* AES Instances ********************************/
19867#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
19868
19869/******************************** CAN Instances ******************************/
19870#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
19871
19872/******************************** COMP Instances ******************************/
19873#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
19874 ((INSTANCE) == COMP2))
19875
19876#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
19877
19878/******************** COMP Instances with window mode capability **************/
19879#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
19880
19881/******************************* CRC Instances ********************************/
19882#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
19883
19884/******************************* DAC Instances ********************************/
19885#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
19886
19887/****************************** DFSDM Instances *******************************/
19888#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
19889 ((INSTANCE) == DFSDM1_Filter1) || \
19890 ((INSTANCE) == DFSDM1_Filter2) || \
19891 ((INSTANCE) == DFSDM1_Filter3))
19892
19893#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
19894 ((INSTANCE) == DFSDM1_Channel1) || \
19895 ((INSTANCE) == DFSDM1_Channel2) || \
19896 ((INSTANCE) == DFSDM1_Channel3) || \
19897 ((INSTANCE) == DFSDM1_Channel4) || \
19898 ((INSTANCE) == DFSDM1_Channel5) || \
19899 ((INSTANCE) == DFSDM1_Channel6) || \
19900 ((INSTANCE) == DFSDM1_Channel7))
19901
19902/******************************* DCMI Instances *******************************/
19903#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
19904
19905/******************************* DMA2D Instances *******************************/
19906#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
19907
19908/******************************** DMA Instances *******************************/
19909#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
19910 ((INSTANCE) == DMA1_Channel2) || \
19911 ((INSTANCE) == DMA1_Channel3) || \
19912 ((INSTANCE) == DMA1_Channel4) || \
19913 ((INSTANCE) == DMA1_Channel5) || \
19914 ((INSTANCE) == DMA1_Channel6) || \
19915 ((INSTANCE) == DMA1_Channel7) || \
19916 ((INSTANCE) == DMA2_Channel1) || \
19917 ((INSTANCE) == DMA2_Channel2) || \
19918 ((INSTANCE) == DMA2_Channel3) || \
19919 ((INSTANCE) == DMA2_Channel4) || \
19920 ((INSTANCE) == DMA2_Channel5) || \
19921 ((INSTANCE) == DMA2_Channel6) || \
19922 ((INSTANCE) == DMA2_Channel7))
19923
19924/******************************* GPIO Instances *******************************/
19925#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
19926 ((INSTANCE) == GPIOB) || \
19927 ((INSTANCE) == GPIOC) || \
19928 ((INSTANCE) == GPIOD) || \
19929 ((INSTANCE) == GPIOE) || \
19930 ((INSTANCE) == GPIOF) || \
19931 ((INSTANCE) == GPIOG) || \
19932 ((INSTANCE) == GPIOH) || \
19933 ((INSTANCE) == GPIOI))
19934
19935/******************************* GPIO AF Instances ****************************/
19936/* On L4, all GPIO Bank support AF */
19937#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
19938
19939/**************************** GPIO Lock Instances *****************************/
19940/* On L4, all GPIO Bank support the Lock mechanism */
19941#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
19942
19943/******************************** I2C Instances *******************************/
19944#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
19945 ((INSTANCE) == I2C2) || \
19946 ((INSTANCE) == I2C3) || \
19947 ((INSTANCE) == I2C4))
19948
19949/****************** I2C Instances : wakeup capability from stop modes *********/
19950#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
19951
19952/******************************* HCD Instances *******************************/
19953#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
19954
19955/****************************** OPAMP Instances *******************************/
19956#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
19957 ((INSTANCE) == OPAMP2))
19958
19959#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
19960
19961/******************************* OSPI Instances *******************************/
19962#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1) || \
19963 ((INSTANCE) == OCTOSPI2))
19964
19965/******************************* PCD Instances *******************************/
19966#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
19967
19968/******************************* RNG Instances ********************************/
19969#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
19970
19971/****************************** RTC Instances *********************************/
19972#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
19973
19974/******************************** SAI Instances *******************************/
19975#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
19976 ((INSTANCE) == SAI1_Block_B) || \
19977 ((INSTANCE) == SAI2_Block_A) || \
19978 ((INSTANCE) == SAI2_Block_B))
19979
19980/****************************** SDMMC Instances *******************************/
19981#define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
19982
19983/****************************** SMBUS Instances *******************************/
19984#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
19985 ((INSTANCE) == I2C2) || \
19986 ((INSTANCE) == I2C3) || \
19987 ((INSTANCE) == I2C4))
19988
19989/******************************** SPI Instances *******************************/
19990#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
19991 ((INSTANCE) == SPI2) || \
19992 ((INSTANCE) == SPI3))
19993
19994/****************** LPTIM Instances : All supported instances *****************/
19995#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
19996 ((INSTANCE) == LPTIM2))
19997
19998/****************** TIM Instances : All supported instances *******************/
19999#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20000 ((INSTANCE) == TIM2) || \
20001 ((INSTANCE) == TIM3) || \
20002 ((INSTANCE) == TIM4) || \
20003 ((INSTANCE) == TIM5) || \
20004 ((INSTANCE) == TIM6) || \
20005 ((INSTANCE) == TIM7) || \
20006 ((INSTANCE) == TIM8) || \
20007 ((INSTANCE) == TIM15) || \
20008 ((INSTANCE) == TIM16) || \
20009 ((INSTANCE) == TIM17))
20010
20011/****************** TIM Instances : supporting 32 bits counter ****************/
20012#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
20013 ((INSTANCE) == TIM5))
20014
20015/****************** TIM Instances : supporting the break function *************/
20016#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20017 ((INSTANCE) == TIM8) || \
20018 ((INSTANCE) == TIM15) || \
20019 ((INSTANCE) == TIM16) || \
20020 ((INSTANCE) == TIM17))
20021
20022/************** TIM Instances : supporting Break source selection *************/
20023#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20024 ((INSTANCE) == TIM8) || \
20025 ((INSTANCE) == TIM15) || \
20026 ((INSTANCE) == TIM16) || \
20027 ((INSTANCE) == TIM17))
20028
20029/****************** TIM Instances : supporting 2 break inputs *****************/
20030#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20031 ((INSTANCE) == TIM8))
20032
20033/************* TIM Instances : at least 1 capture/compare channel *************/
20034#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20035 ((INSTANCE) == TIM2) || \
20036 ((INSTANCE) == TIM3) || \
20037 ((INSTANCE) == TIM4) || \
20038 ((INSTANCE) == TIM5) || \
20039 ((INSTANCE) == TIM8) || \
20040 ((INSTANCE) == TIM15) || \
20041 ((INSTANCE) == TIM16) || \
20042 ((INSTANCE) == TIM17))
20043
20044/************ TIM Instances : at least 2 capture/compare channels *************/
20045#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20046 ((INSTANCE) == TIM2) || \
20047 ((INSTANCE) == TIM3) || \
20048 ((INSTANCE) == TIM4) || \
20049 ((INSTANCE) == TIM5) || \
20050 ((INSTANCE) == TIM8) || \
20051 ((INSTANCE) == TIM15))
20052
20053/************ TIM Instances : at least 3 capture/compare channels *************/
20054#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20055 ((INSTANCE) == TIM2) || \
20056 ((INSTANCE) == TIM3) || \
20057 ((INSTANCE) == TIM4) || \
20058 ((INSTANCE) == TIM5) || \
20059 ((INSTANCE) == TIM8))
20060
20061/************ TIM Instances : at least 4 capture/compare channels *************/
20062#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20063 ((INSTANCE) == TIM2) || \
20064 ((INSTANCE) == TIM3) || \
20065 ((INSTANCE) == TIM4) || \
20066 ((INSTANCE) == TIM5) || \
20067 ((INSTANCE) == TIM8))
20068
20069/****************** TIM Instances : at least 5 capture/compare channels *******/
20070#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20071 ((INSTANCE) == TIM8))
20072
20073/****************** TIM Instances : at least 6 capture/compare channels *******/
20074#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20075 ((INSTANCE) == TIM8))
20076
20077/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
20078#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20079 ((INSTANCE) == TIM8) || \
20080 ((INSTANCE) == TIM15) || \
20081 ((INSTANCE) == TIM16) || \
20082 ((INSTANCE) == TIM17))
20083
20084/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
20085#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20086 ((INSTANCE) == TIM2) || \
20087 ((INSTANCE) == TIM3) || \
20088 ((INSTANCE) == TIM4) || \
20089 ((INSTANCE) == TIM5) || \
20090 ((INSTANCE) == TIM6) || \
20091 ((INSTANCE) == TIM7) || \
20092 ((INSTANCE) == TIM8) || \
20093 ((INSTANCE) == TIM15) || \
20094 ((INSTANCE) == TIM16) || \
20095 ((INSTANCE) == TIM17))
20096
20097/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
20098#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20099 ((INSTANCE) == TIM2) || \
20100 ((INSTANCE) == TIM3) || \
20101 ((INSTANCE) == TIM4) || \
20102 ((INSTANCE) == TIM5) || \
20103 ((INSTANCE) == TIM8) || \
20104 ((INSTANCE) == TIM15) || \
20105 ((INSTANCE) == TIM16) || \
20106 ((INSTANCE) == TIM17))
20107
20108/******************** TIM Instances : DMA burst feature ***********************/
20109#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20110 ((INSTANCE) == TIM2) || \
20111 ((INSTANCE) == TIM3) || \
20112 ((INSTANCE) == TIM4) || \
20113 ((INSTANCE) == TIM5) || \
20114 ((INSTANCE) == TIM8) || \
20115 ((INSTANCE) == TIM15) || \
20116 ((INSTANCE) == TIM16) || \
20117 ((INSTANCE) == TIM17))
20118
20119/******************* TIM Instances : output(s) available **********************/
20120#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
20121 ((((INSTANCE) == TIM1) && \
20122 (((CHANNEL) == TIM_CHANNEL_1) || \
20123 ((CHANNEL) == TIM_CHANNEL_2) || \
20124 ((CHANNEL) == TIM_CHANNEL_3) || \
20125 ((CHANNEL) == TIM_CHANNEL_4) || \
20126 ((CHANNEL) == TIM_CHANNEL_5) || \
20127 ((CHANNEL) == TIM_CHANNEL_6))) \
20128 || \
20129 (((INSTANCE) == TIM2) && \
20130 (((CHANNEL) == TIM_CHANNEL_1) || \
20131 ((CHANNEL) == TIM_CHANNEL_2) || \
20132 ((CHANNEL) == TIM_CHANNEL_3) || \
20133 ((CHANNEL) == TIM_CHANNEL_4))) \
20134 || \
20135 (((INSTANCE) == TIM3) && \
20136 (((CHANNEL) == TIM_CHANNEL_1) || \
20137 ((CHANNEL) == TIM_CHANNEL_2) || \
20138 ((CHANNEL) == TIM_CHANNEL_3) || \
20139 ((CHANNEL) == TIM_CHANNEL_4))) \
20140 || \
20141 (((INSTANCE) == TIM4) && \
20142 (((CHANNEL) == TIM_CHANNEL_1) || \
20143 ((CHANNEL) == TIM_CHANNEL_2) || \
20144 ((CHANNEL) == TIM_CHANNEL_3) || \
20145 ((CHANNEL) == TIM_CHANNEL_4))) \
20146 || \
20147 (((INSTANCE) == TIM5) && \
20148 (((CHANNEL) == TIM_CHANNEL_1) || \
20149 ((CHANNEL) == TIM_CHANNEL_2) || \
20150 ((CHANNEL) == TIM_CHANNEL_3) || \
20151 ((CHANNEL) == TIM_CHANNEL_4))) \
20152 || \
20153 (((INSTANCE) == TIM8) && \
20154 (((CHANNEL) == TIM_CHANNEL_1) || \
20155 ((CHANNEL) == TIM_CHANNEL_2) || \
20156 ((CHANNEL) == TIM_CHANNEL_3) || \
20157 ((CHANNEL) == TIM_CHANNEL_4) || \
20158 ((CHANNEL) == TIM_CHANNEL_5) || \
20159 ((CHANNEL) == TIM_CHANNEL_6))) \
20160 || \
20161 (((INSTANCE) == TIM15) && \
20162 (((CHANNEL) == TIM_CHANNEL_1) || \
20163 ((CHANNEL) == TIM_CHANNEL_2))) \
20164 || \
20165 (((INSTANCE) == TIM16) && \
20166 (((CHANNEL) == TIM_CHANNEL_1))) \
20167 || \
20168 (((INSTANCE) == TIM17) && \
20169 (((CHANNEL) == TIM_CHANNEL_1))))
20170
20171/****************** TIM Instances : supporting complementary output(s) ********/
20172#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
20173 ((((INSTANCE) == TIM1) && \
20174 (((CHANNEL) == TIM_CHANNEL_1) || \
20175 ((CHANNEL) == TIM_CHANNEL_2) || \
20176 ((CHANNEL) == TIM_CHANNEL_3))) \
20177 || \
20178 (((INSTANCE) == TIM8) && \
20179 (((CHANNEL) == TIM_CHANNEL_1) || \
20180 ((CHANNEL) == TIM_CHANNEL_2) || \
20181 ((CHANNEL) == TIM_CHANNEL_3))) \
20182 || \
20183 (((INSTANCE) == TIM15) && \
20184 ((CHANNEL) == TIM_CHANNEL_1)) \
20185 || \
20186 (((INSTANCE) == TIM16) && \
20187 ((CHANNEL) == TIM_CHANNEL_1)) \
20188 || \
20189 (((INSTANCE) == TIM17) && \
20190 ((CHANNEL) == TIM_CHANNEL_1)))
20191
20192/****************** TIM Instances : supporting clock division *****************/
20193#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20194 ((INSTANCE) == TIM2) || \
20195 ((INSTANCE) == TIM3) || \
20196 ((INSTANCE) == TIM4) || \
20197 ((INSTANCE) == TIM5) || \
20198 ((INSTANCE) == TIM8) || \
20199 ((INSTANCE) == TIM15) || \
20200 ((INSTANCE) == TIM16) || \
20201 ((INSTANCE) == TIM17))
20202
20203/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
20204#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20205 ((INSTANCE) == TIM2) || \
20206 ((INSTANCE) == TIM3) || \
20207 ((INSTANCE) == TIM4) || \
20208 ((INSTANCE) == TIM5) || \
20209 ((INSTANCE) == TIM8) || \
20210 ((INSTANCE) == TIM15))
20211
20212/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
20213#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20214 ((INSTANCE) == TIM2) || \
20215 ((INSTANCE) == TIM3) || \
20216 ((INSTANCE) == TIM4) || \
20217 ((INSTANCE) == TIM5) || \
20218 ((INSTANCE) == TIM8))
20219
20220/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
20221#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20222 ((INSTANCE) == TIM2) || \
20223 ((INSTANCE) == TIM3) || \
20224 ((INSTANCE) == TIM4) || \
20225 ((INSTANCE) == TIM5) || \
20226 ((INSTANCE) == TIM8) || \
20227 ((INSTANCE) == TIM15))
20228
20229/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
20230#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20231 ((INSTANCE) == TIM2) || \
20232 ((INSTANCE) == TIM3) || \
20233 ((INSTANCE) == TIM4) || \
20234 ((INSTANCE) == TIM5) || \
20235 ((INSTANCE) == TIM8) || \
20236 ((INSTANCE) == TIM15))
20237
20238/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
20239#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20240 ((INSTANCE) == TIM8))
20241
20242/****************** TIM Instances : supporting commutation event generation ***/
20243#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20244 ((INSTANCE) == TIM8) || \
20245 ((INSTANCE) == TIM15) || \
20246 ((INSTANCE) == TIM16) || \
20247 ((INSTANCE) == TIM17))
20248
20249/****************** TIM Instances : supporting counting mode selection ********/
20250#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20251 ((INSTANCE) == TIM2) || \
20252 ((INSTANCE) == TIM3) || \
20253 ((INSTANCE) == TIM4) || \
20254 ((INSTANCE) == TIM5) || \
20255 ((INSTANCE) == TIM8))
20256
20257/****************** TIM Instances : supporting encoder interface **************/
20258#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20259 ((INSTANCE) == TIM2) || \
20260 ((INSTANCE) == TIM3) || \
20261 ((INSTANCE) == TIM4) || \
20262 ((INSTANCE) == TIM5) || \
20263 ((INSTANCE) == TIM8))
20264
20265/****************** TIM Instances : supporting Hall sensor interface **********/
20266#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20267 ((INSTANCE) == TIM2) || \
20268 ((INSTANCE) == TIM3) || \
20269 ((INSTANCE) == TIM4) || \
20270 ((INSTANCE) == TIM5) || \
20271 ((INSTANCE) == TIM8))
20272
20273/**************** TIM Instances : external trigger input available ************/
20274#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20275 ((INSTANCE) == TIM2) || \
20276 ((INSTANCE) == TIM3) || \
20277 ((INSTANCE) == TIM4) || \
20278 ((INSTANCE) == TIM5) || \
20279 ((INSTANCE) == TIM8))
20280
20281/************* TIM Instances : supporting ETR source selection ***************/
20282#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20283 ((INSTANCE) == TIM2) || \
20284 ((INSTANCE) == TIM3) || \
20285 ((INSTANCE) == TIM8))
20286
20287/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
20288#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20289 ((INSTANCE) == TIM2) || \
20290 ((INSTANCE) == TIM3) || \
20291 ((INSTANCE) == TIM4) || \
20292 ((INSTANCE) == TIM5) || \
20293 ((INSTANCE) == TIM6) || \
20294 ((INSTANCE) == TIM7) || \
20295 ((INSTANCE) == TIM8) || \
20296 ((INSTANCE) == TIM15))
20297
20298/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
20299#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20300 ((INSTANCE) == TIM2) || \
20301 ((INSTANCE) == TIM3) || \
20302 ((INSTANCE) == TIM4) || \
20303 ((INSTANCE) == TIM5) || \
20304 ((INSTANCE) == TIM8) || \
20305 ((INSTANCE) == TIM15))
20306
20307/****************** TIM Instances : supporting OCxREF clear *******************/
20308#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20309 ((INSTANCE) == TIM2) || \
20310 ((INSTANCE) == TIM3) || \
20311 ((INSTANCE) == TIM4) || \
20312 ((INSTANCE) == TIM5) || \
20313 ((INSTANCE) == TIM8))
20314
20315/****************** TIM Instances : remapping capability **********************/
20316#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20317 ((INSTANCE) == TIM2) || \
20318 ((INSTANCE) == TIM3) || \
20319 ((INSTANCE) == TIM8) || \
20320 ((INSTANCE) == TIM15) || \
20321 ((INSTANCE) == TIM16) || \
20322 ((INSTANCE) == TIM17))
20323
20324/****************** TIM Instances : supporting repetition counter *************/
20325#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20326 ((INSTANCE) == TIM8) || \
20327 ((INSTANCE) == TIM15) || \
20328 ((INSTANCE) == TIM16) || \
20329 ((INSTANCE) == TIM17))
20330
20331/****************** TIM Instances : supporting synchronization ****************/
20332#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
20333
20334/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
20335#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20336 ((INSTANCE) == TIM8))
20337
20338/******************* TIM Instances : Timer input XOR function *****************/
20339#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20340 ((INSTANCE) == TIM2) || \
20341 ((INSTANCE) == TIM3) || \
20342 ((INSTANCE) == TIM4) || \
20343 ((INSTANCE) == TIM5) || \
20344 ((INSTANCE) == TIM8) || \
20345 ((INSTANCE) == TIM15))
20346
20347/****************** TIM Instances : Advanced timer instances *******************/
20348#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20349 ((INSTANCE) == TIM8))
20350
20351/****************************** TSC Instances *********************************/
20352#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
20353
20354/******************** USART Instances : Synchronous mode **********************/
20355#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20356 ((INSTANCE) == USART2) || \
20357 ((INSTANCE) == USART3))
20358
20359/******************** UART Instances : Asynchronous mode **********************/
20360#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20361 ((INSTANCE) == USART2) || \
20362 ((INSTANCE) == USART3) || \
20363 ((INSTANCE) == UART4) || \
20364 ((INSTANCE) == UART5))
20365
20366/*********************** UART Instances : FIFO mode ***************************/
20367#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20368 ((INSTANCE) == USART2) || \
20369 ((INSTANCE) == USART3) || \
20370 ((INSTANCE) == UART4) || \
20371 ((INSTANCE) == UART5) || \
20372 ((INSTANCE) == LPUART1))
20373
20374/*********************** UART Instances : SPI Slave mode **********************/
20375#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20376 ((INSTANCE) == USART2) || \
20377 ((INSTANCE) == USART3))
20378
20379/****************** UART Instances : Auto Baud Rate detection ****************/
20380#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20381 ((INSTANCE) == USART2) || \
20382 ((INSTANCE) == USART3) || \
20383 ((INSTANCE) == UART4) || \
20384 ((INSTANCE) == UART5))
20385
20386/****************** UART Instances : Driver Enable *****************/
20387#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20388 ((INSTANCE) == USART2) || \
20389 ((INSTANCE) == USART3) || \
20390 ((INSTANCE) == UART4) || \
20391 ((INSTANCE) == UART5) || \
20392 ((INSTANCE) == LPUART1))
20393
20394/******************** UART Instances : Half-Duplex mode **********************/
20395#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20396 ((INSTANCE) == USART2) || \
20397 ((INSTANCE) == USART3) || \
20398 ((INSTANCE) == UART4) || \
20399 ((INSTANCE) == UART5) || \
20400 ((INSTANCE) == LPUART1))
20401
20402/****************** UART Instances : Hardware Flow control ********************/
20403#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20404 ((INSTANCE) == USART2) || \
20405 ((INSTANCE) == USART3) || \
20406 ((INSTANCE) == UART4) || \
20407 ((INSTANCE) == UART5) || \
20408 ((INSTANCE) == LPUART1))
20409
20410/******************** UART Instances : LIN mode **********************/
20411#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20412 ((INSTANCE) == USART2) || \
20413 ((INSTANCE) == USART3) || \
20414 ((INSTANCE) == UART4) || \
20415 ((INSTANCE) == UART5))
20416
20417/******************** UART Instances : Wake-up from Stop mode **********************/
20418#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20419 ((INSTANCE) == USART2) || \
20420 ((INSTANCE) == USART3) || \
20421 ((INSTANCE) == UART4) || \
20422 ((INSTANCE) == UART5) || \
20423 ((INSTANCE) == LPUART1))
20424
20425/*********************** UART Instances : IRDA mode ***************************/
20426#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20427 ((INSTANCE) == USART2) || \
20428 ((INSTANCE) == USART3) || \
20429 ((INSTANCE) == UART4) || \
20430 ((INSTANCE) == UART5))
20431
20432/********************* USART Instances : Smard card mode ***********************/
20433#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20434 ((INSTANCE) == USART2) || \
20435 ((INSTANCE) == USART3))
20436
20437/******************** LPUART Instance *****************************************/
20438#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
20439
20440/****************************** IWDG Instances ********************************/
20441#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
20442
20443/****************************** WWDG Instances ********************************/
20444#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
20445
20446/**
20447 * @}
20448 */
20449
20450
20451/******************************************************************************/
20452/* For a painless codes migration between the STM32L4xx device product */
20453/* lines, the aliases defined below are put in place to overcome the */
20454/* differences in the interrupt handlers and IRQn definitions. */
20455/* No need to update developed interrupt code when moving across */
20456/* product lines within the same STM32L4 Family */
20457/******************************************************************************/
20458
20459/* Aliases for __IRQn */
20460#define ADC1_2_IRQn ADC1_IRQn
20461#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
20462#define TIM8_IRQn TIM8_UP_IRQn
20463#define HASH_RNG_IRQn RNG_IRQn
20464#define CRS_IRQn HASH_CRS_IRQn
20465#define DFSDM0_IRQn DFSDM1_FLT0_IRQn
20466#define DFSDM1_IRQn DFSDM1_FLT1_IRQn
20467#define DFSDM2_IRQn DFSDM1_FLT2_IRQn
20468#define DFSDM3_IRQn DFSDM1_FLT3_IRQn
20469
20470/* Aliases for __IRQHandler */
20471#define ADC1_2_IRQHandler ADC1_IRQHandler
20472#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
20473#define TIM8_IRQHandler TIM8_UP_IRQHandler
20474#define HASH_RNG_IRQHandler RNG_IRQHandler
20475#define CRS_IRQHandler HASH_CRS_IRQHandler
20476#define DFSDM0_IRQHandler DFSDM1_FLT0_IRQHandler
20477#define DFSDM1_IRQHandler DFSDM1_FLT1_IRQHandler
20478#define DFSDM2_IRQHandler DFSDM1_FLT2_IRQHandler
20479#define DFSDM3_IRQHandler DFSDM1_FLT3_IRQHandler
20480
20481#ifdef __cplusplus
20482}
20483#endif /* __cplusplus */
20484
20485#endif /* __STM32L4S5xx_H */
20486
20487/**
20488 * @}
20489 */
20490
20491 /**
20492 * @}
20493 */
20494
20495/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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