diff options
Diffstat (limited to 'lib/chibios/demos/SPC5/RT-SPC56EL-EVB/mcuconf.h')
| -rw-r--r-- | lib/chibios/demos/SPC5/RT-SPC56EL-EVB/mcuconf.h | 294 |
1 files changed, 294 insertions, 0 deletions
diff --git a/lib/chibios/demos/SPC5/RT-SPC56EL-EVB/mcuconf.h b/lib/chibios/demos/SPC5/RT-SPC56EL-EVB/mcuconf.h new file mode 100644 index 000000000..31e52feb5 --- /dev/null +++ b/lib/chibios/demos/SPC5/RT-SPC56EL-EVB/mcuconf.h | |||
| @@ -0,0 +1,294 @@ | |||
| 1 | /* | ||
| 2 | ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio | ||
| 3 | |||
| 4 | Licensed under the Apache License, Version 2.0 (the "License"); | ||
| 5 | you may not use this file except in compliance with the License. | ||
| 6 | You may obtain a copy of the License at | ||
| 7 | |||
| 8 | http://www.apache.org/licenses/LICENSE-2.0 | ||
| 9 | |||
| 10 | Unless required by applicable law or agreed to in writing, software | ||
| 11 | distributed under the License is distributed on an "AS IS" BASIS, | ||
| 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
| 13 | See the License for the specific language governing permissions and | ||
| 14 | limitations under the License. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef MCUCONF_H | ||
| 18 | #define MCUCONF_H | ||
| 19 | |||
| 20 | /* | ||
| 21 | * SPC56ELxx drivers configuration. | ||
| 22 | * The following settings override the default settings present in | ||
| 23 | * the various device driver implementation headers. | ||
| 24 | * Note that the settings for each driver only have effect if the whole | ||
| 25 | * driver is enabled in halconf.h. | ||
| 26 | * | ||
| 27 | * IRQ priorities: | ||
| 28 | * 1...15 Lowest...Highest. | ||
| 29 | * DMA priorities: | ||
| 30 | * 0...15 Highest...Lowest. | ||
| 31 | */ | ||
| 32 | |||
| 33 | #define SPC56ELxx_MCUCONF | ||
| 34 | |||
| 35 | /* | ||
| 36 | * HAL driver system settings. | ||
| 37 | */ | ||
| 38 | #define SPC5_NO_INIT FALSE | ||
| 39 | #define SPC5_ALLOW_OVERCLOCK FALSE | ||
| 40 | #define SPC5_DISABLE_WATCHDOG TRUE | ||
| 41 | #define SPC5_FMPLL0_CLK_SRC SPC5_FMPLL_SRC_XOSC | ||
| 42 | #define SPC5_FMPLL0_IDF_VALUE 5 | ||
| 43 | #define SPC5_FMPLL0_NDIV_VALUE 60 | ||
| 44 | #define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4 | ||
| 45 | #define SPC5_FMPLL1_CLK_SRC SPC5_FMPLL_SRC_XOSC | ||
| 46 | #define SPC5_FMPLL1_IDF_VALUE 5 | ||
| 47 | #define SPC5_FMPLL1_NDIV_VALUE 60 | ||
| 48 | #define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4 | ||
| 49 | #define SPC5_SYSCLK_DIVIDER_VALUE 2 | ||
| 50 | #define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL1 | ||
| 51 | #define SPC5_MCONTROL_DIVIDER_VALUE 15 | ||
| 52 | #define SPC5_SWG_DIVIDER_VALUE 2 | ||
| 53 | #define SPC5_AUX1CLK_SRC SPC5_CGM_SS_FMPLL1 | ||
| 54 | #define SPC5_FLEXRAY_DIVIDER_VALUE 2 | ||
| 55 | #define SPC5_AUX2CLK_SRC SPC5_CGM_SS_FMPLL1 | ||
| 56 | #define SPC5_FLEXCAN_DIVIDER_VALUE 2 | ||
| 57 | #define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \ | ||
| 58 | SPC5_ME_ME_RUN2 | \ | ||
| 59 | SPC5_ME_ME_RUN3 | \ | ||
| 60 | SPC5_ME_ME_HALT0 | \ | ||
| 61 | SPC5_ME_ME_STOP0) | ||
| 62 | #define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO) | ||
| 63 | #define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ | ||
| 64 | SPC5_ME_MC_IRCON | \ | ||
| 65 | SPC5_ME_MC_XOSC0ON | \ | ||
| 66 | SPC5_ME_MC_PLL0ON | \ | ||
| 67 | SPC5_ME_MC_PLL1ON | \ | ||
| 68 | SPC5_ME_MC_FLAON_NORMAL | \ | ||
| 69 | SPC5_ME_MC_MVRON) | ||
| 70 | #define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ | ||
| 71 | SPC5_ME_MC_IRCON | \ | ||
| 72 | SPC5_ME_MC_XOSC0ON | \ | ||
| 73 | SPC5_ME_MC_PLL0ON | \ | ||
| 74 | SPC5_ME_MC_PLL1ON | \ | ||
| 75 | SPC5_ME_MC_FLAON_NORMAL | \ | ||
| 76 | SPC5_ME_MC_MVRON) | ||
| 77 | #define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ | ||
| 78 | SPC5_ME_MC_IRCON | \ | ||
| 79 | SPC5_ME_MC_XOSC0ON | \ | ||
| 80 | SPC5_ME_MC_PLL0ON | \ | ||
| 81 | SPC5_ME_MC_PLL1ON | \ | ||
| 82 | SPC5_ME_MC_FLAON_NORMAL | \ | ||
| 83 | SPC5_ME_MC_MVRON) | ||
| 84 | #define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ | ||
| 85 | SPC5_ME_MC_IRCON | \ | ||
| 86 | SPC5_ME_MC_XOSC0ON | \ | ||
| 87 | SPC5_ME_MC_PLL0ON | \ | ||
| 88 | SPC5_ME_MC_PLL1ON | \ | ||
| 89 | SPC5_ME_MC_FLAON_NORMAL | \ | ||
| 90 | SPC5_ME_MC_MVRON) | ||
| 91 | #define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ | ||
| 92 | SPC5_ME_MC_IRCON | \ | ||
| 93 | SPC5_ME_MC_XOSC0ON | \ | ||
| 94 | SPC5_ME_MC_PLL0ON | \ | ||
| 95 | SPC5_ME_MC_PLL1ON | \ | ||
| 96 | SPC5_ME_MC_FLAON_NORMAL | \ | ||
| 97 | SPC5_ME_MC_MVRON) | ||
| 98 | #define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ | ||
| 99 | SPC5_ME_MC_IRCON | \ | ||
| 100 | SPC5_ME_MC_XOSC0ON | \ | ||
| 101 | SPC5_ME_MC_PLL0ON | \ | ||
| 102 | SPC5_ME_MC_PLL1ON | \ | ||
| 103 | SPC5_ME_MC_FLAON_NORMAL | \ | ||
| 104 | SPC5_ME_MC_MVRON) | ||
| 105 | #define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ | ||
| 106 | SPC5_ME_MC_IRCON | \ | ||
| 107 | SPC5_ME_MC_XOSC0ON | \ | ||
| 108 | SPC5_ME_MC_PLL0ON | \ | ||
| 109 | SPC5_ME_MC_PLL1ON | \ | ||
| 110 | SPC5_ME_MC_FLAON_NORMAL | \ | ||
| 111 | SPC5_ME_MC_MVRON) | ||
| 112 | #define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ | ||
| 113 | SPC5_ME_RUN_PC_RUN1 | \ | ||
| 114 | SPC5_ME_RUN_PC_RUN2 | \ | ||
| 115 | SPC5_ME_RUN_PC_RUN3) | ||
| 116 | #define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \ | ||
| 117 | SPC5_ME_RUN_PC_RUN1 | \ | ||
| 118 | SPC5_ME_RUN_PC_RUN2 | \ | ||
| 119 | SPC5_ME_RUN_PC_RUN3) | ||
| 120 | #define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \ | ||
| 121 | SPC5_ME_RUN_PC_RUN1 | \ | ||
| 122 | SPC5_ME_RUN_PC_RUN2 | \ | ||
| 123 | SPC5_ME_RUN_PC_RUN3) | ||
| 124 | #define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \ | ||
| 125 | SPC5_ME_RUN_PC_RUN1 | \ | ||
| 126 | SPC5_ME_RUN_PC_RUN2 | \ | ||
| 127 | SPC5_ME_RUN_PC_RUN3) | ||
| 128 | #define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \ | ||
| 129 | SPC5_ME_RUN_PC_RUN1 | \ | ||
| 130 | SPC5_ME_RUN_PC_RUN2 | \ | ||
| 131 | SPC5_ME_RUN_PC_RUN3) | ||
| 132 | #define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ | ||
| 133 | SPC5_ME_LP_PC_STOP0) | ||
| 134 | #define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ | ||
| 135 | SPC5_ME_LP_PC_STOP0) | ||
| 136 | #define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \ | ||
| 137 | SPC5_ME_LP_PC_STOP0) | ||
| 138 | #define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ | ||
| 139 | SPC5_ME_LP_PC_STOP0) | ||
| 140 | #define SPC5_CLOCK_FAILURE_HOOK() chSysHalt("Clock failure") | ||
| 141 | |||
| 142 | /* | ||
| 143 | * EDMA driver settings. | ||
| 144 | */ | ||
| 145 | #define SPC5_EDMA_CR_SETTING 0 | ||
| 146 | #define SPC5_EDMA_GROUP0_PRIORITIES \ | ||
| 147 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 | ||
| 148 | #define SPC5_EDMA_ERROR_IRQ_PRIO 12 | ||
| 149 | #define SPC5_EDMA_ERROR_HANDLER() chSysHalt("DMA failure") | ||
| 150 | |||
| 151 | /* | ||
| 152 | * SERIAL driver system settings. | ||
| 153 | */ | ||
| 154 | #define SPC5_SERIAL_USE_LINFLEX0 TRUE | ||
| 155 | #define SPC5_SERIAL_USE_LINFLEX1 TRUE | ||
| 156 | #define SPC5_SERIAL_LINFLEX0_PRIORITY 8 | ||
| 157 | #define SPC5_SERIAL_LINFLEX1_PRIORITY 8 | ||
| 158 | #define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ | ||
| 159 | SPC5_ME_PCTL_LP(2)) | ||
| 160 | #define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ | ||
| 161 | SPC5_ME_PCTL_LP(0)) | ||
| 162 | #define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ | ||
| 163 | SPC5_ME_PCTL_LP(2)) | ||
| 164 | #define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ | ||
| 165 | SPC5_ME_PCTL_LP(0)) | ||
| 166 | |||
| 167 | /* | ||
| 168 | * PWM driver system settings. | ||
| 169 | */ | ||
| 170 | #define SPC5_PWM_USE_SMOD0 FALSE | ||
| 171 | #define SPC5_PWM_USE_SMOD1 FALSE | ||
| 172 | #define SPC5_PWM_USE_SMOD2 FALSE | ||
| 173 | #define SPC5_PWM_USE_SMOD3 FALSE | ||
| 174 | #define SPC5_PWM_SMOD0_PRIORITY 7 | ||
| 175 | #define SPC5_PWM_SMOD1_PRIORITY 7 | ||
| 176 | #define SPC5_PWM_SMOD2_PRIORITY 7 | ||
| 177 | #define SPC5_PWM_SMOD3_PRIORITY 7 | ||
| 178 | #define SPC5_PWM_FLEXPWM0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ | ||
| 179 | SPC5_ME_PCTL_LP(2)) | ||
| 180 | #define SPC5_PWM_FLEXPWM0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ | ||
| 181 | SPC5_ME_PCTL_LP(0)) | ||
| 182 | |||
| 183 | #define SPC5_PWM_USE_SMOD4 FALSE | ||
| 184 | #define SPC5_PWM_USE_SMOD5 FALSE | ||
| 185 | #define SPC5_PWM_USE_SMOD6 FALSE | ||
| 186 | #define SPC5_PWM_USE_SMOD7 FALSE | ||
| 187 | #define SPC5_PWM_SMOD4_PRIORITY 7 | ||
| 188 | #define SPC5_PWM_SMOD5_PRIORITY 7 | ||
| 189 | #define SPC5_PWM_SMOD6_PRIORITY 7 | ||
| 190 | #define SPC5_PWM_SMOD7_PRIORITY 7 | ||
| 191 | #define SPC5_PWM_FLEXPWM1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ | ||
| 192 | SPC5_ME_PCTL_LP(2)) | ||
| 193 | #define SPC5_PWM_FLEXPWM1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ | ||
| 194 | SPC5_ME_PCTL_LP(0)) | ||
| 195 | |||
| 196 | /* | ||
| 197 | * ICU driver system settings. | ||
| 198 | */ | ||
| 199 | #define SPC5_ICU_USE_SMOD0 FALSE | ||
| 200 | #define SPC5_ICU_USE_SMOD1 FALSE | ||
| 201 | #define SPC5_ICU_USE_SMOD2 FALSE | ||
| 202 | #define SPC5_ICU_USE_SMOD3 FALSE | ||
| 203 | #define SPC5_ICU_USE_SMOD4 FALSE | ||
| 204 | #define SPC5_ICU_USE_SMOD5 FALSE | ||
| 205 | #define SPC5_ICU_ETIMER0_PRIORITY 7 | ||
| 206 | #define SPC5_ICU_ETIMER0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ | ||
| 207 | SPC5_ME_PCTL_LP(2)) | ||
| 208 | #define SPC5_ICU_ETIMER0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ | ||
| 209 | SPC5_ME_PCTL_LP(0)) | ||
| 210 | |||
| 211 | #define SPC5_ICU_USE_SMOD6 FALSE | ||
| 212 | #define SPC5_ICU_USE_SMOD7 FALSE | ||
| 213 | #define SPC5_ICU_USE_SMOD8 FALSE | ||
| 214 | #define SPC5_ICU_USE_SMOD9 FALSE | ||
| 215 | #define SPC5_ICU_USE_SMOD10 FALSE | ||
| 216 | #define SPC5_ICU_USE_SMOD11 FALSE | ||
| 217 | #define SPC5_ICU_ETIMER1_PRIORITY 7 | ||
| 218 | #define SPC5_ICU_ETIMER1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ | ||
| 219 | SPC5_ME_PCTL_LP(2)) | ||
| 220 | #define SPC5_ICU_ETIMER1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ | ||
| 221 | SPC5_ME_PCTL_LP(0)) | ||
| 222 | |||
| 223 | #define SPC5_ICU_USE_SMOD12 FALSE | ||
| 224 | #define SPC5_ICU_USE_SMOD13 FALSE | ||
| 225 | #define SPC5_ICU_USE_SMOD14 FALSE | ||
| 226 | #define SPC5_ICU_USE_SMOD15 FALSE | ||
| 227 | #define SPC5_ICU_USE_SMOD16 FALSE | ||
| 228 | #define SPC5_ICU_USE_SMOD17 FALSE | ||
| 229 | #define SPC5_ICU_ETIMER2_PRIORITY 7 | ||
| 230 | #define SPC5_ICU_ETIMER2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ | ||
| 231 | SPC5_ME_PCTL_LP(2)) | ||
| 232 | #define SPC5_ICU_ETIMER2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ | ||
| 233 | SPC5_ME_PCTL_LP(0)) | ||
| 234 | |||
| 235 | /* | ||
| 236 | * SPI driver system settings. | ||
| 237 | */ | ||
| 238 | #define SPC5_SPI_USE_DSPI0 FALSE | ||
| 239 | #define SPC5_SPI_USE_DSPI1 FALSE | ||
| 240 | #define SPC5_SPI_USE_DSPI2 FALSE | ||
| 241 | #define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \ | ||
| 242 | SPC5_MCR_PCSIS1 | \ | ||
| 243 | SPC5_MCR_PCSIS2 | \ | ||
| 244 | SPC5_MCR_PCSIS3 | \ | ||
| 245 | SPC5_MCR_PCSIS4 | \ | ||
| 246 | SPC5_MCR_PCSIS5 | \ | ||
| 247 | SPC5_MCR_PCSIS6 | \ | ||
| 248 | SPC5_MCR_PCSIS7) | ||
| 249 | #define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \ | ||
| 250 | SPC5_MCR_PCSIS1 | \ | ||
| 251 | SPC5_MCR_PCSIS2 | \ | ||
| 252 | SPC5_MCR_PCSIS3 | \ | ||
| 253 | SPC5_MCR_PCSIS4 | \ | ||
| 254 | SPC5_MCR_PCSIS5 | \ | ||
| 255 | SPC5_MCR_PCSIS6 | \ | ||
| 256 | SPC5_MCR_PCSIS7) | ||
| 257 | #define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \ | ||
| 258 | SPC5_MCR_PCSIS1 | \ | ||
| 259 | SPC5_MCR_PCSIS2 | \ | ||
| 260 | SPC5_MCR_PCSIS3 | \ | ||
| 261 | SPC5_MCR_PCSIS4 | \ | ||
| 262 | SPC5_MCR_PCSIS5 | \ | ||
| 263 | SPC5_MCR_PCSIS6 | \ | ||
| 264 | SPC5_MCR_PCSIS7) | ||
| 265 | #define SPC5_SPI_DSPI0_TX1_DMA_CH_ID 4 | ||
| 266 | #define SPC5_SPI_DSPI0_TX2_DMA_CH_ID 5 | ||
| 267 | #define SPC5_SPI_DSPI0_RX_DMA_CH_ID 6 | ||
| 268 | #define SPC5_SPI_DSPI1_TX1_DMA_CH_ID 7 | ||
| 269 | #define SPC5_SPI_DSPI1_TX2_DMA_CH_ID 8 | ||
| 270 | #define SPC5_SPI_DSPI1_RX_DMA_CH_ID 9 | ||
| 271 | #define SPC5_SPI_DSPI2_TX1_DMA_CH_ID 10 | ||
| 272 | #define SPC5_SPI_DSPI2_TX2_DMA_CH_ID 11 | ||
| 273 | #define SPC5_SPI_DSPI2_RX_DMA_CH_ID 12 | ||
| 274 | #define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10 | ||
| 275 | #define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 | ||
| 276 | #define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 | ||
| 277 | #define SPC5_SPI_DSPI0_IRQ_PRIO 10 | ||
| 278 | #define SPC5_SPI_DSPI1_IRQ_PRIO 10 | ||
| 279 | #define SPC5_SPI_DSPI2_IRQ_PRIO 10 | ||
| 280 | #define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt("DMA failure") | ||
| 281 | #define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ | ||
| 282 | SPC5_ME_PCTL_LP(2)) | ||
| 283 | #define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ | ||
| 284 | SPC5_ME_PCTL_LP(0)) | ||
| 285 | #define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ | ||
| 286 | SPC5_ME_PCTL_LP(2)) | ||
| 287 | #define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ | ||
| 288 | SPC5_ME_PCTL_LP(0)) | ||
| 289 | #define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ | ||
| 290 | SPC5_ME_PCTL_LP(2)) | ||
| 291 | #define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ | ||
| 292 | SPC5_ME_PCTL_LP(0)) | ||
| 293 | |||
| 294 | #endif /* MCUCONF_H */ | ||