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1/**
2 ******************************************************************************
3 * @file stm32f030x8.h
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
6 * This file contains all the peripheral register's definitions, bits
7 * definitions and memory mapping for STM32F0xx devices.
8 *
9 * This file contains:
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral�s registers hardware
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
18 *
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ******************************************************************************
42 */
43
44/** @addtogroup CMSIS
45 * @{
46 */
47
48/** @addtogroup stm32f030x8
49 * @{
50 */
51
52#ifndef __STM32F030x8_H
53#define __STM32F030x8_H
54
55#ifdef __cplusplus
56 extern "C" {
57#endif /* __cplusplus */
58
59 /** @addtogroup Configuration_section_for_CMSIS
60 * @{
61 */
62/**
63 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
64 */
65#define __CM0_REV 0 /*!< Core Revision r0p0 */
66#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
67#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
68#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
69
70/**
71 * @}
72 */
73
74/** @addtogroup Peripheral_interrupt_number_definition
75 * @{
76 */
77
78/**
79 * @brief STM32F0xx Interrupt Number Definition, according to the selected device
80 * in @ref Library_configuration_section
81 */
82
83 /*!< Interrupt Number Definition */
84typedef enum
85{
86/****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
87 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
88 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
89 SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
90 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
91 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
92
93/****** STM32F0 specific Interrupt Numbers ******************************************************************/
94 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
95 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
96 FLASH_IRQn = 3, /*!< FLASH global Interrupt */
97 RCC_IRQn = 4, /*!< RCC global Interrupt */
98 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupt */
99 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupt */
100 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupt */
101 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
102 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupt */
103 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt */
104 ADC1_IRQn = 12, /*!< ADC1 Interrupt */
105 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupt */
106 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
107 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
108 TIM6_IRQn = 17, /*!< TIM6 global Interrupt */
109 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
110 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
111 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
112 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
113 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt */
114 I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */
115 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
116 SPI2_IRQn = 26, /*!< SPI2 global Interrupt */
117 USART1_IRQn = 27, /*!< USART1 global Interrupt */
118 USART2_IRQn = 28 /*!< USART2 global Interrupt */
119} IRQn_Type;
120
121/**
122 * @}
123 */
124
125#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
126#include "system_stm32f0xx.h" /* STM32F0xx System Header */
127#include <stdint.h>
128
129/** @addtogroup Peripheral_registers_structures
130 * @{
131 */
132
133/**
134 * @brief Analog to Digital Converter
135 */
136
137typedef struct
138{
139 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
140 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
141 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
142 __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */
143 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
144 __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */
145 uint32_t RESERVED1; /*!< Reserved, 0x18 */
146 uint32_t RESERVED2; /*!< Reserved, 0x1C */
147 __IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
148 uint32_t RESERVED3; /*!< Reserved, 0x24 */
149 __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */
150 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
151 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
152} ADC_TypeDef;
153
154typedef struct
155{
156 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
157} ADC_Common_TypeDef;
158
159/**
160 * @brief CRC calculation unit
161 */
162
163typedef struct
164{
165 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
166 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
167 uint8_t RESERVED0; /*!< Reserved, 0x05 */
168 uint16_t RESERVED1; /*!< Reserved, 0x06 */
169 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
170 uint32_t RESERVED2; /*!< Reserved, 0x0C */
171 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
172 __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */
173} CRC_TypeDef;
174
175/**
176 * @brief Debug MCU
177 */
178
179typedef struct
180{
181 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
182 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
183 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
184 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
185}DBGMCU_TypeDef;
186
187/**
188 * @brief DMA Controller
189 */
190
191typedef struct
192{
193 __IO uint32_t CCR; /*!< DMA channel x configuration register */
194 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
195 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
196 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
197} DMA_Channel_TypeDef;
198
199typedef struct
200{
201 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
202 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
203} DMA_TypeDef;
204
205/**
206 * @brief External Interrupt/Event Controller
207 */
208
209typedef struct
210{
211 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
212 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
213 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
214 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
215 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
216 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
217} EXTI_TypeDef;
218
219/**
220 * @brief FLASH Registers
221 */
222typedef struct
223{
224 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
225 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
226 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
227 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
228 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
229 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
230 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
231 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
232 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
233} FLASH_TypeDef;
234
235/**
236 * @brief Option Bytes Registers
237 */
238typedef struct
239{
240 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
241 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
242 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
243 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
244 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
245 __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
246} OB_TypeDef;
247
248/**
249 * @brief General Purpose I/O
250 */
251
252typedef struct
253{
254 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
255 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
256 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
257 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
258 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
259 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
260 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
261 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
262 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
263 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
264} GPIO_TypeDef;
265
266/**
267 * @brief SysTem Configuration
268 */
269
270typedef struct
271{
272 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
273 uint32_t RESERVED; /*!< Reserved, 0x04 */
274 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
275 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
276} SYSCFG_TypeDef;
277
278/**
279 * @brief Inter-integrated Circuit Interface
280 */
281
282typedef struct
283{
284 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
285 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
286 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
287 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
288 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
289 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
290 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
291 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
292 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
293 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
294 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
295} I2C_TypeDef;
296
297/**
298 * @brief Independent WATCHDOG
299 */
300
301typedef struct
302{
303 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
304 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
305 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
306 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
307 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
308} IWDG_TypeDef;
309
310/**
311 * @brief Power Control
312 */
313
314typedef struct
315{
316 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
317 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
318} PWR_TypeDef;
319
320/**
321 * @brief Reset and Clock Control
322 */
323
324typedef struct
325{
326 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
327 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
328 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
329 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
330 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
331 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
332 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
333 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
334 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
335 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
336 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
337 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
338 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
339 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
340} RCC_TypeDef;
341
342/**
343 * @brief Real-Time Clock
344 */
345typedef struct
346{
347 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
348 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
349 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
350 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
351 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
352 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
353 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
354 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
355 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */
356 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
357 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
358 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
359 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
360 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
361 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
362 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
363 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
364 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
365} RTC_TypeDef;
366
367/**
368 * @brief Serial Peripheral Interface
369 */
370
371typedef struct
372{
373 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
374 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
375 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
376 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
377 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
378 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
379 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
380 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
381} SPI_TypeDef;
382
383/**
384 * @brief TIM
385 */
386typedef struct
387{
388 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
389 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
390 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
391 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
392 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
393 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
394 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
395 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
396 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
397 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
398 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
399 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
400 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
401 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
402 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
403 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
404 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
405 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
406 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
407 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
408 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
409} TIM_TypeDef;
410
411/**
412 * @brief Universal Synchronous Asynchronous Receiver Transmitter
413 */
414
415typedef struct
416{
417 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
418 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
419 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
420 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
421 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
422 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
423 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
424 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
425 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
426 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
427 uint16_t RESERVED1; /*!< Reserved, 0x26 */
428 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
429 uint16_t RESERVED2; /*!< Reserved, 0x2A */
430} USART_TypeDef;
431
432/**
433 * @brief Window WATCHDOG
434 */
435typedef struct
436{
437 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
438 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
439 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
440} WWDG_TypeDef;
441
442/**
443 * @}
444 */
445
446/** @addtogroup Peripheral_memory_map
447 * @{
448 */
449
450#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
451#define FLASH_BANK1_END ((uint32_t)0x0800FFFFU) /*!< FLASH END address of bank1 */
452#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
453#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
454
455/*!< Peripheral memory map */
456#define APBPERIPH_BASE PERIPH_BASE
457#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
458#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
459
460/*!< APB peripherals */
461#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
462#define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
463#define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
464#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
465#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
466#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
467#define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
468#define USART2_BASE (APBPERIPH_BASE + 0x00004400)
469#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
470#define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
471#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
472#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
473#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
474#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
475#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
476#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
477#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
478#define USART1_BASE (APBPERIPH_BASE + 0x00013800)
479#define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
480#define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
481#define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
482#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
483
484/*!< AHB peripherals */
485#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
486#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
487#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
488#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
489#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
490#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
491
492#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
493#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
494#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< FLASH Option Bytes base address */
495#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7CCU) /*!< FLASH Size register base address */
496#define UID_BASE ((uint32_t)0x1FFFF7ACU) /*!< Unique device ID register base address */
497#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
498
499/*!< AHB2 peripherals */
500#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
501#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
502#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
503#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
504#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
505
506/**
507 * @}
508 */
509
510/** @addtogroup Peripheral_declaration
511 * @{
512 */
513
514#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
515#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
516#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
517#define RTC ((RTC_TypeDef *) RTC_BASE)
518#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
519#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
520#define USART2 ((USART_TypeDef *) USART2_BASE)
521#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
522#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
523#define PWR ((PWR_TypeDef *) PWR_BASE)
524#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
525#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
526#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
527#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
528#define ADC ((ADC_Common_TypeDef *) ADC_BASE) /* Kept for legacy purpose */
529#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
530#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
531#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
532#define USART1 ((USART_TypeDef *) USART1_BASE)
533#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
534#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
535#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
536#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
537#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
538#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
539#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
540#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
541#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
542#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
543#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
544#define OB ((OB_TypeDef *) OB_BASE)
545#define RCC ((RCC_TypeDef *) RCC_BASE)
546#define CRC ((CRC_TypeDef *) CRC_BASE)
547#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
548#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
549#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
550#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
551#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
552/**
553 * @}
554 */
555
556/** @addtogroup Exported_constants
557 * @{
558 */
559
560 /** @addtogroup Peripheral_Registers_Bits_Definition
561 * @{
562 */
563
564/******************************************************************************/
565/* Peripheral Registers Bits Definition */
566/******************************************************************************/
567
568/******************************************************************************/
569/* */
570/* Analog to Digital Converter (ADC) */
571/* */
572/******************************************************************************/
573
574/*
575 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
576 */
577/* Note: No specific macro feature on this device */
578
579/******************** Bits definition for ADC_ISR register ******************/
580#define ADC_ISR_ADRDY_Pos (0U)
581#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
582#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
583#define ADC_ISR_EOSMP_Pos (1U)
584#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
585#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
586#define ADC_ISR_EOC_Pos (2U)
587#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
588#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
589#define ADC_ISR_EOS_Pos (3U)
590#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
591#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
592#define ADC_ISR_OVR_Pos (4U)
593#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
594#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
595#define ADC_ISR_AWD1_Pos (7U)
596#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
597#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
598
599/* Legacy defines */
600#define ADC_ISR_AWD (ADC_ISR_AWD1)
601#define ADC_ISR_EOSEQ (ADC_ISR_EOS)
602
603/******************** Bits definition for ADC_IER register ******************/
604#define ADC_IER_ADRDYIE_Pos (0U)
605#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
606#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
607#define ADC_IER_EOSMPIE_Pos (1U)
608#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
609#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
610#define ADC_IER_EOCIE_Pos (2U)
611#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
612#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
613#define ADC_IER_EOSIE_Pos (3U)
614#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
615#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
616#define ADC_IER_OVRIE_Pos (4U)
617#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
618#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
619#define ADC_IER_AWD1IE_Pos (7U)
620#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
621#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
622
623/* Legacy defines */
624#define ADC_IER_AWDIE (ADC_IER_AWD1IE)
625#define ADC_IER_EOSEQIE (ADC_IER_EOSIE)
626
627/******************** Bits definition for ADC_CR register *******************/
628#define ADC_CR_ADEN_Pos (0U)
629#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
630#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
631#define ADC_CR_ADDIS_Pos (1U)
632#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
633#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
634#define ADC_CR_ADSTART_Pos (2U)
635#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
636#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
637#define ADC_CR_ADSTP_Pos (4U)
638#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
639#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
640#define ADC_CR_ADCAL_Pos (31U)
641#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
642#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
643
644/******************* Bits definition for ADC_CFGR1 register *****************/
645#define ADC_CFGR1_DMAEN_Pos (0U)
646#define ADC_CFGR1_DMAEN_Msk (0x1U << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
647#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */
648#define ADC_CFGR1_DMACFG_Pos (1U)
649#define ADC_CFGR1_DMACFG_Msk (0x1U << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
650#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */
651#define ADC_CFGR1_SCANDIR_Pos (2U)
652#define ADC_CFGR1_SCANDIR_Msk (0x1U << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
653#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */
654
655#define ADC_CFGR1_RES_Pos (3U)
656#define ADC_CFGR1_RES_Msk (0x3U << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
657#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */
658#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
659#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
660
661#define ADC_CFGR1_ALIGN_Pos (5U)
662#define ADC_CFGR1_ALIGN_Msk (0x1U << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
663#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */
664
665#define ADC_CFGR1_EXTSEL_Pos (6U)
666#define ADC_CFGR1_EXTSEL_Msk (0x7U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
667#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */
668#define ADC_CFGR1_EXTSEL_0 (0x1U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
669#define ADC_CFGR1_EXTSEL_1 (0x2U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
670#define ADC_CFGR1_EXTSEL_2 (0x4U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
671
672#define ADC_CFGR1_EXTEN_Pos (10U)
673#define ADC_CFGR1_EXTEN_Msk (0x3U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
674#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */
675#define ADC_CFGR1_EXTEN_0 (0x1U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
676#define ADC_CFGR1_EXTEN_1 (0x2U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
677
678#define ADC_CFGR1_OVRMOD_Pos (12U)
679#define ADC_CFGR1_OVRMOD_Msk (0x1U << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
680#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */
681#define ADC_CFGR1_CONT_Pos (13U)
682#define ADC_CFGR1_CONT_Msk (0x1U << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
683#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */
684#define ADC_CFGR1_WAIT_Pos (14U)
685#define ADC_CFGR1_WAIT_Msk (0x1U << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
686#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */
687#define ADC_CFGR1_AUTOFF_Pos (15U)
688#define ADC_CFGR1_AUTOFF_Msk (0x1U << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
689#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */
690#define ADC_CFGR1_DISCEN_Pos (16U)
691#define ADC_CFGR1_DISCEN_Msk (0x1U << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
692#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
693
694#define ADC_CFGR1_AWD1SGL_Pos (22U)
695#define ADC_CFGR1_AWD1SGL_Msk (0x1U << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
696#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
697#define ADC_CFGR1_AWD1EN_Pos (23U)
698#define ADC_CFGR1_AWD1EN_Msk (0x1U << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
699#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
700
701#define ADC_CFGR1_AWD1CH_Pos (26U)
702#define ADC_CFGR1_AWD1CH_Msk (0x1FU << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */
703#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
704#define ADC_CFGR1_AWD1CH_0 (0x01U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */
705#define ADC_CFGR1_AWD1CH_1 (0x02U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */
706#define ADC_CFGR1_AWD1CH_2 (0x04U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */
707#define ADC_CFGR1_AWD1CH_3 (0x08U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */
708#define ADC_CFGR1_AWD1CH_4 (0x10U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */
709
710/* Legacy defines */
711#define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT)
712#define ADC_CFGR1_AWDSGL (ADC_CFGR1_AWD1SGL)
713#define ADC_CFGR1_AWDEN (ADC_CFGR1_AWD1EN)
714#define ADC_CFGR1_AWDCH (ADC_CFGR1_AWD1CH)
715#define ADC_CFGR1_AWDCH_0 (ADC_CFGR1_AWD1CH_0)
716#define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1)
717#define ADC_CFGR1_AWDCH_2 (ADC_CFGR1_AWD1CH_2)
718#define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3)
719#define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4)
720
721/******************* Bits definition for ADC_CFGR2 register *****************/
722#define ADC_CFGR2_CKMODE_Pos (30U)
723#define ADC_CFGR2_CKMODE_Msk (0x3U << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
724#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */
725#define ADC_CFGR2_CKMODE_1 (0x2U << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
726#define ADC_CFGR2_CKMODE_0 (0x1U << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
727
728/* Legacy defines */
729#define ADC_CFGR2_JITOFFDIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC clocked by PCLK div4 */
730#define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */
731
732/****************** Bit definition for ADC_SMPR register ********************/
733#define ADC_SMPR_SMP_Pos (0U)
734#define ADC_SMPR_SMP_Msk (0x7U << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
735#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< ADC group of channels sampling time 2 */
736#define ADC_SMPR_SMP_0 (0x1U << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
737#define ADC_SMPR_SMP_1 (0x2U << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
738#define ADC_SMPR_SMP_2 (0x4U << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
739
740/* Legacy defines */
741#define ADC_SMPR1_SMPR (ADC_SMPR_SMP) /*!< SMP[2:0] bits (Sampling time selection) */
742#define ADC_SMPR1_SMPR_0 (ADC_SMPR_SMP_0) /*!< bit 0 */
743#define ADC_SMPR1_SMPR_1 (ADC_SMPR_SMP_1) /*!< bit 1 */
744#define ADC_SMPR1_SMPR_2 (ADC_SMPR_SMP_2) /*!< bit 2 */
745
746/******************* Bit definition for ADC_TR register ********************/
747#define ADC_TR1_LT1_Pos (0U)
748#define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
749#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
750#define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
751#define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
752#define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
753#define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
754#define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
755#define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
756#define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
757#define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
758#define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
759#define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
760#define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
761#define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
762
763#define ADC_TR1_HT1_Pos (16U)
764#define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
765#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
766#define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
767#define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
768#define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
769#define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
770#define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
771#define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
772#define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
773#define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
774#define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
775#define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
776#define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
777#define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
778
779/* Legacy defines */
780#define ADC_TR_HT (ADC_TR1_HT1)
781#define ADC_TR_LT (ADC_TR1_LT1)
782#define ADC_HTR_HT (ADC_TR1_HT1)
783#define ADC_LTR_LT (ADC_TR1_LT1)
784
785/****************** Bit definition for ADC_CHSELR register ******************/
786#define ADC_CHSELR_CHSEL_Pos (0U)
787#define ADC_CHSELR_CHSEL_Msk (0x7FFFFU << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
788#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
789#define ADC_CHSELR_CHSEL18_Pos (18U)
790#define ADC_CHSELR_CHSEL18_Msk (0x1U << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
791#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
792#define ADC_CHSELR_CHSEL17_Pos (17U)
793#define ADC_CHSELR_CHSEL17_Msk (0x1U << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
794#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
795#define ADC_CHSELR_CHSEL16_Pos (16U)
796#define ADC_CHSELR_CHSEL16_Msk (0x1U << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */
797#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
798#define ADC_CHSELR_CHSEL15_Pos (15U)
799#define ADC_CHSELR_CHSEL15_Msk (0x1U << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
800#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
801#define ADC_CHSELR_CHSEL14_Pos (14U)
802#define ADC_CHSELR_CHSEL14_Msk (0x1U << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
803#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
804#define ADC_CHSELR_CHSEL13_Pos (13U)
805#define ADC_CHSELR_CHSEL13_Msk (0x1U << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
806#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
807#define ADC_CHSELR_CHSEL12_Pos (12U)
808#define ADC_CHSELR_CHSEL12_Msk (0x1U << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
809#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
810#define ADC_CHSELR_CHSEL11_Pos (11U)
811#define ADC_CHSELR_CHSEL11_Msk (0x1U << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
812#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
813#define ADC_CHSELR_CHSEL10_Pos (10U)
814#define ADC_CHSELR_CHSEL10_Msk (0x1U << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
815#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
816#define ADC_CHSELR_CHSEL9_Pos (9U)
817#define ADC_CHSELR_CHSEL9_Msk (0x1U << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
818#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
819#define ADC_CHSELR_CHSEL8_Pos (8U)
820#define ADC_CHSELR_CHSEL8_Msk (0x1U << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
821#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
822#define ADC_CHSELR_CHSEL7_Pos (7U)
823#define ADC_CHSELR_CHSEL7_Msk (0x1U << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
824#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
825#define ADC_CHSELR_CHSEL6_Pos (6U)
826#define ADC_CHSELR_CHSEL6_Msk (0x1U << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
827#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
828#define ADC_CHSELR_CHSEL5_Pos (5U)
829#define ADC_CHSELR_CHSEL5_Msk (0x1U << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
830#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
831#define ADC_CHSELR_CHSEL4_Pos (4U)
832#define ADC_CHSELR_CHSEL4_Msk (0x1U << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
833#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
834#define ADC_CHSELR_CHSEL3_Pos (3U)
835#define ADC_CHSELR_CHSEL3_Msk (0x1U << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
836#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
837#define ADC_CHSELR_CHSEL2_Pos (2U)
838#define ADC_CHSELR_CHSEL2_Msk (0x1U << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
839#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
840#define ADC_CHSELR_CHSEL1_Pos (1U)
841#define ADC_CHSELR_CHSEL1_Msk (0x1U << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
842#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
843#define ADC_CHSELR_CHSEL0_Pos (0U)
844#define ADC_CHSELR_CHSEL0_Msk (0x1U << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
845#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
846
847/******************** Bit definition for ADC_DR register ********************/
848#define ADC_DR_DATA_Pos (0U)
849#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
850#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
851#define ADC_DR_DATA_0 (0x0001U << ADC_DR_DATA_Pos) /*!< 0x00000001 */
852#define ADC_DR_DATA_1 (0x0002U << ADC_DR_DATA_Pos) /*!< 0x00000002 */
853#define ADC_DR_DATA_2 (0x0004U << ADC_DR_DATA_Pos) /*!< 0x00000004 */
854#define ADC_DR_DATA_3 (0x0008U << ADC_DR_DATA_Pos) /*!< 0x00000008 */
855#define ADC_DR_DATA_4 (0x0010U << ADC_DR_DATA_Pos) /*!< 0x00000010 */
856#define ADC_DR_DATA_5 (0x0020U << ADC_DR_DATA_Pos) /*!< 0x00000020 */
857#define ADC_DR_DATA_6 (0x0040U << ADC_DR_DATA_Pos) /*!< 0x00000040 */
858#define ADC_DR_DATA_7 (0x0080U << ADC_DR_DATA_Pos) /*!< 0x00000080 */
859#define ADC_DR_DATA_8 (0x0100U << ADC_DR_DATA_Pos) /*!< 0x00000100 */
860#define ADC_DR_DATA_9 (0x0200U << ADC_DR_DATA_Pos) /*!< 0x00000200 */
861#define ADC_DR_DATA_10 (0x0400U << ADC_DR_DATA_Pos) /*!< 0x00000400 */
862#define ADC_DR_DATA_11 (0x0800U << ADC_DR_DATA_Pos) /*!< 0x00000800 */
863#define ADC_DR_DATA_12 (0x1000U << ADC_DR_DATA_Pos) /*!< 0x00001000 */
864#define ADC_DR_DATA_13 (0x2000U << ADC_DR_DATA_Pos) /*!< 0x00002000 */
865#define ADC_DR_DATA_14 (0x4000U << ADC_DR_DATA_Pos) /*!< 0x00004000 */
866#define ADC_DR_DATA_15 (0x8000U << ADC_DR_DATA_Pos) /*!< 0x00008000 */
867
868/************************* ADC Common registers *****************************/
869/******************* Bit definition for ADC_CCR register ********************/
870#define ADC_CCR_VREFEN_Pos (22U)
871#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
872#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
873#define ADC_CCR_TSEN_Pos (23U)
874#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
875#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
876
877
878/******************************************************************************/
879/* */
880/* CRC calculation unit (CRC) */
881/* */
882/******************************************************************************/
883/******************* Bit definition for CRC_DR register *********************/
884#define CRC_DR_DR_Pos (0U)
885#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
886#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
887
888/******************* Bit definition for CRC_IDR register ********************/
889#define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
890
891/******************** Bit definition for CRC_CR register ********************/
892#define CRC_CR_RESET_Pos (0U)
893#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
894#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
895#define CRC_CR_REV_IN_Pos (5U)
896#define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
897#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
898#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
899#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
900#define CRC_CR_REV_OUT_Pos (7U)
901#define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
902#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
903
904/******************* Bit definition for CRC_INIT register *******************/
905#define CRC_INIT_INIT_Pos (0U)
906#define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
907#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
908
909/******************************************************************************/
910/* */
911/* Debug MCU (DBGMCU) */
912/* */
913/******************************************************************************/
914
915/**************** Bit definition for DBGMCU_IDCODE register *****************/
916#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
917#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
918#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
919
920#define DBGMCU_IDCODE_REV_ID_Pos (16U)
921#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
922#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
923#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
924#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
925#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
926#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
927#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
928#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
929#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
930#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
931#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
932#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
933#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
934#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
935#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
936#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
937#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
938#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
939
940/****************** Bit definition for DBGMCU_CR register *******************/
941#define DBGMCU_CR_DBG_STOP_Pos (1U)
942#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
943#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
944#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
945#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
946#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
947
948/****************** Bit definition for DBGMCU_APB1_FZ register **************/
949#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
950#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
951#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
952#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
953#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
954#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
955#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
956#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
957#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk /*!< TIM14 counter stopped when core is halted */
958#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
959#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
960#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
961#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
962#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
963#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
964#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
965#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
966#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
967#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
968#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
969#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
970
971/****************** Bit definition for DBGMCU_APB2_FZ register **************/
972#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (11U)
973#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
974#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
975#define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (16U)
976#define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
977#define DBGMCU_APB2_FZ_DBG_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk /*!< TIM15 counter stopped when core is halted */
978#define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (17U)
979#define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
980#define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk /*!< TIM16 counter stopped when core is halted */
981#define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (18U)
982#define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
983#define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk /*!< TIM17 counter stopped when core is halted */
984
985/******************************************************************************/
986/* */
987/* DMA Controller (DMA) */
988/* */
989/******************************************************************************/
990/******************* Bit definition for DMA_ISR register ********************/
991#define DMA_ISR_GIF1_Pos (0U)
992#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
993#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
994#define DMA_ISR_TCIF1_Pos (1U)
995#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
996#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
997#define DMA_ISR_HTIF1_Pos (2U)
998#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
999#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
1000#define DMA_ISR_TEIF1_Pos (3U)
1001#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
1002#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
1003#define DMA_ISR_GIF2_Pos (4U)
1004#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
1005#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
1006#define DMA_ISR_TCIF2_Pos (5U)
1007#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
1008#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
1009#define DMA_ISR_HTIF2_Pos (6U)
1010#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
1011#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
1012#define DMA_ISR_TEIF2_Pos (7U)
1013#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
1014#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
1015#define DMA_ISR_GIF3_Pos (8U)
1016#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
1017#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
1018#define DMA_ISR_TCIF3_Pos (9U)
1019#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
1020#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
1021#define DMA_ISR_HTIF3_Pos (10U)
1022#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
1023#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
1024#define DMA_ISR_TEIF3_Pos (11U)
1025#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
1026#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
1027#define DMA_ISR_GIF4_Pos (12U)
1028#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
1029#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
1030#define DMA_ISR_TCIF4_Pos (13U)
1031#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
1032#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
1033#define DMA_ISR_HTIF4_Pos (14U)
1034#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
1035#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
1036#define DMA_ISR_TEIF4_Pos (15U)
1037#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
1038#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
1039#define DMA_ISR_GIF5_Pos (16U)
1040#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
1041#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
1042#define DMA_ISR_TCIF5_Pos (17U)
1043#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
1044#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
1045#define DMA_ISR_HTIF5_Pos (18U)
1046#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
1047#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
1048#define DMA_ISR_TEIF5_Pos (19U)
1049#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
1050#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
1051
1052/******************* Bit definition for DMA_IFCR register *******************/
1053#define DMA_IFCR_CGIF1_Pos (0U)
1054#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
1055#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
1056#define DMA_IFCR_CTCIF1_Pos (1U)
1057#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
1058#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
1059#define DMA_IFCR_CHTIF1_Pos (2U)
1060#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1061#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
1062#define DMA_IFCR_CTEIF1_Pos (3U)
1063#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
1064#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
1065#define DMA_IFCR_CGIF2_Pos (4U)
1066#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
1067#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
1068#define DMA_IFCR_CTCIF2_Pos (5U)
1069#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
1070#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
1071#define DMA_IFCR_CHTIF2_Pos (6U)
1072#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
1073#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
1074#define DMA_IFCR_CTEIF2_Pos (7U)
1075#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
1076#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
1077#define DMA_IFCR_CGIF3_Pos (8U)
1078#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
1079#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
1080#define DMA_IFCR_CTCIF3_Pos (9U)
1081#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
1082#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
1083#define DMA_IFCR_CHTIF3_Pos (10U)
1084#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
1085#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
1086#define DMA_IFCR_CTEIF3_Pos (11U)
1087#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
1088#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
1089#define DMA_IFCR_CGIF4_Pos (12U)
1090#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
1091#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
1092#define DMA_IFCR_CTCIF4_Pos (13U)
1093#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
1094#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
1095#define DMA_IFCR_CHTIF4_Pos (14U)
1096#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
1097#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
1098#define DMA_IFCR_CTEIF4_Pos (15U)
1099#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
1100#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
1101#define DMA_IFCR_CGIF5_Pos (16U)
1102#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
1103#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
1104#define DMA_IFCR_CTCIF5_Pos (17U)
1105#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
1106#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
1107#define DMA_IFCR_CHTIF5_Pos (18U)
1108#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
1109#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
1110#define DMA_IFCR_CTEIF5_Pos (19U)
1111#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
1112#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
1113
1114/******************* Bit definition for DMA_CCR register ********************/
1115#define DMA_CCR_EN_Pos (0U)
1116#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
1117#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
1118#define DMA_CCR_TCIE_Pos (1U)
1119#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
1120#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
1121#define DMA_CCR_HTIE_Pos (2U)
1122#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
1123#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
1124#define DMA_CCR_TEIE_Pos (3U)
1125#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
1126#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
1127#define DMA_CCR_DIR_Pos (4U)
1128#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
1129#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
1130#define DMA_CCR_CIRC_Pos (5U)
1131#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
1132#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
1133#define DMA_CCR_PINC_Pos (6U)
1134#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
1135#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
1136#define DMA_CCR_MINC_Pos (7U)
1137#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
1138#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
1139
1140#define DMA_CCR_PSIZE_Pos (8U)
1141#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
1142#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
1143#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
1144#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
1145
1146#define DMA_CCR_MSIZE_Pos (10U)
1147#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
1148#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
1149#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
1150#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
1151
1152#define DMA_CCR_PL_Pos (12U)
1153#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
1154#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
1155#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
1156#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
1157
1158#define DMA_CCR_MEM2MEM_Pos (14U)
1159#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
1160#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
1161
1162/****************** Bit definition for DMA_CNDTR register *******************/
1163#define DMA_CNDTR_NDT_Pos (0U)
1164#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
1165#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
1166
1167/****************** Bit definition for DMA_CPAR register ********************/
1168#define DMA_CPAR_PA_Pos (0U)
1169#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
1170#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
1171
1172/****************** Bit definition for DMA_CMAR register ********************/
1173#define DMA_CMAR_MA_Pos (0U)
1174#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
1175#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
1176
1177/******************************************************************************/
1178/* */
1179/* External Interrupt/Event Controller (EXTI) */
1180/* */
1181/******************************************************************************/
1182/******************* Bit definition for EXTI_IMR register *******************/
1183#define EXTI_IMR_MR0_Pos (0U)
1184#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
1185#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
1186#define EXTI_IMR_MR1_Pos (1U)
1187#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
1188#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
1189#define EXTI_IMR_MR2_Pos (2U)
1190#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
1191#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
1192#define EXTI_IMR_MR3_Pos (3U)
1193#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
1194#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
1195#define EXTI_IMR_MR4_Pos (4U)
1196#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
1197#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
1198#define EXTI_IMR_MR5_Pos (5U)
1199#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
1200#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
1201#define EXTI_IMR_MR6_Pos (6U)
1202#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
1203#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
1204#define EXTI_IMR_MR7_Pos (7U)
1205#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
1206#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
1207#define EXTI_IMR_MR8_Pos (8U)
1208#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
1209#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
1210#define EXTI_IMR_MR9_Pos (9U)
1211#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
1212#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
1213#define EXTI_IMR_MR10_Pos (10U)
1214#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
1215#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
1216#define EXTI_IMR_MR11_Pos (11U)
1217#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
1218#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
1219#define EXTI_IMR_MR12_Pos (12U)
1220#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
1221#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
1222#define EXTI_IMR_MR13_Pos (13U)
1223#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
1224#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
1225#define EXTI_IMR_MR14_Pos (14U)
1226#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
1227#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
1228#define EXTI_IMR_MR15_Pos (15U)
1229#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
1230#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
1231#define EXTI_IMR_MR17_Pos (17U)
1232#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
1233#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
1234#define EXTI_IMR_MR18_Pos (18U)
1235#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
1236#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
1237#define EXTI_IMR_MR19_Pos (19U)
1238#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
1239#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
1240#define EXTI_IMR_MR23_Pos (23U)
1241#define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
1242#define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
1243
1244/* References Defines */
1245#define EXTI_IMR_IM0 EXTI_IMR_MR0
1246#define EXTI_IMR_IM1 EXTI_IMR_MR1
1247#define EXTI_IMR_IM2 EXTI_IMR_MR2
1248#define EXTI_IMR_IM3 EXTI_IMR_MR3
1249#define EXTI_IMR_IM4 EXTI_IMR_MR4
1250#define EXTI_IMR_IM5 EXTI_IMR_MR5
1251#define EXTI_IMR_IM6 EXTI_IMR_MR6
1252#define EXTI_IMR_IM7 EXTI_IMR_MR7
1253#define EXTI_IMR_IM8 EXTI_IMR_MR8
1254#define EXTI_IMR_IM9 EXTI_IMR_MR9
1255#define EXTI_IMR_IM10 EXTI_IMR_MR10
1256#define EXTI_IMR_IM11 EXTI_IMR_MR11
1257#define EXTI_IMR_IM12 EXTI_IMR_MR12
1258#define EXTI_IMR_IM13 EXTI_IMR_MR13
1259#define EXTI_IMR_IM14 EXTI_IMR_MR14
1260#define EXTI_IMR_IM15 EXTI_IMR_MR15
1261#define EXTI_IMR_IM17 EXTI_IMR_MR17
1262#define EXTI_IMR_IM18 EXTI_IMR_MR18
1263#define EXTI_IMR_IM19 EXTI_IMR_MR19
1264#define EXTI_IMR_IM23 EXTI_IMR_MR23
1265
1266#define EXTI_IMR_IM_Pos (0U)
1267#define EXTI_IMR_IM_Msk (0x8EFFFFU << EXTI_IMR_IM_Pos) /*!< 0x008EFFFF */
1268#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
1269
1270
1271/****************** Bit definition for EXTI_EMR register ********************/
1272#define EXTI_EMR_MR0_Pos (0U)
1273#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
1274#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
1275#define EXTI_EMR_MR1_Pos (1U)
1276#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
1277#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
1278#define EXTI_EMR_MR2_Pos (2U)
1279#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
1280#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
1281#define EXTI_EMR_MR3_Pos (3U)
1282#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
1283#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
1284#define EXTI_EMR_MR4_Pos (4U)
1285#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
1286#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
1287#define EXTI_EMR_MR5_Pos (5U)
1288#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
1289#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
1290#define EXTI_EMR_MR6_Pos (6U)
1291#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
1292#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
1293#define EXTI_EMR_MR7_Pos (7U)
1294#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
1295#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
1296#define EXTI_EMR_MR8_Pos (8U)
1297#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
1298#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
1299#define EXTI_EMR_MR9_Pos (9U)
1300#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
1301#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
1302#define EXTI_EMR_MR10_Pos (10U)
1303#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
1304#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
1305#define EXTI_EMR_MR11_Pos (11U)
1306#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
1307#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
1308#define EXTI_EMR_MR12_Pos (12U)
1309#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
1310#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
1311#define EXTI_EMR_MR13_Pos (13U)
1312#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
1313#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
1314#define EXTI_EMR_MR14_Pos (14U)
1315#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
1316#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
1317#define EXTI_EMR_MR15_Pos (15U)
1318#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
1319#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
1320#define EXTI_EMR_MR17_Pos (17U)
1321#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
1322#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
1323#define EXTI_EMR_MR18_Pos (18U)
1324#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
1325#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
1326#define EXTI_EMR_MR19_Pos (19U)
1327#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
1328#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
1329#define EXTI_EMR_MR23_Pos (23U)
1330#define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
1331#define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
1332
1333/* References Defines */
1334#define EXTI_EMR_EM0 EXTI_EMR_MR0
1335#define EXTI_EMR_EM1 EXTI_EMR_MR1
1336#define EXTI_EMR_EM2 EXTI_EMR_MR2
1337#define EXTI_EMR_EM3 EXTI_EMR_MR3
1338#define EXTI_EMR_EM4 EXTI_EMR_MR4
1339#define EXTI_EMR_EM5 EXTI_EMR_MR5
1340#define EXTI_EMR_EM6 EXTI_EMR_MR6
1341#define EXTI_EMR_EM7 EXTI_EMR_MR7
1342#define EXTI_EMR_EM8 EXTI_EMR_MR8
1343#define EXTI_EMR_EM9 EXTI_EMR_MR9
1344#define EXTI_EMR_EM10 EXTI_EMR_MR10
1345#define EXTI_EMR_EM11 EXTI_EMR_MR11
1346#define EXTI_EMR_EM12 EXTI_EMR_MR12
1347#define EXTI_EMR_EM13 EXTI_EMR_MR13
1348#define EXTI_EMR_EM14 EXTI_EMR_MR14
1349#define EXTI_EMR_EM15 EXTI_EMR_MR15
1350#define EXTI_EMR_EM17 EXTI_EMR_MR17
1351#define EXTI_EMR_EM18 EXTI_EMR_MR18
1352#define EXTI_EMR_EM19 EXTI_EMR_MR19
1353#define EXTI_EMR_EM23 EXTI_EMR_MR23
1354
1355/******************* Bit definition for EXTI_RTSR register ******************/
1356#define EXTI_RTSR_TR0_Pos (0U)
1357#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
1358#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
1359#define EXTI_RTSR_TR1_Pos (1U)
1360#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
1361#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
1362#define EXTI_RTSR_TR2_Pos (2U)
1363#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
1364#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
1365#define EXTI_RTSR_TR3_Pos (3U)
1366#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
1367#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
1368#define EXTI_RTSR_TR4_Pos (4U)
1369#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
1370#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
1371#define EXTI_RTSR_TR5_Pos (5U)
1372#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
1373#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
1374#define EXTI_RTSR_TR6_Pos (6U)
1375#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
1376#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
1377#define EXTI_RTSR_TR7_Pos (7U)
1378#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
1379#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
1380#define EXTI_RTSR_TR8_Pos (8U)
1381#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
1382#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
1383#define EXTI_RTSR_TR9_Pos (9U)
1384#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
1385#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
1386#define EXTI_RTSR_TR10_Pos (10U)
1387#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
1388#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
1389#define EXTI_RTSR_TR11_Pos (11U)
1390#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
1391#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
1392#define EXTI_RTSR_TR12_Pos (12U)
1393#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
1394#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
1395#define EXTI_RTSR_TR13_Pos (13U)
1396#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
1397#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
1398#define EXTI_RTSR_TR14_Pos (14U)
1399#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
1400#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
1401#define EXTI_RTSR_TR15_Pos (15U)
1402#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
1403#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
1404#define EXTI_RTSR_TR16_Pos (16U)
1405#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
1406#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
1407#define EXTI_RTSR_TR17_Pos (17U)
1408#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
1409#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
1410#define EXTI_RTSR_TR19_Pos (19U)
1411#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
1412#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
1413
1414/* References Defines */
1415#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
1416#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
1417#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
1418#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
1419#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
1420#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
1421#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
1422#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
1423#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
1424#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
1425#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
1426#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
1427#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
1428#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
1429#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
1430#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
1431#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
1432#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
1433#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
1434
1435/******************* Bit definition for EXTI_FTSR register *******************/
1436#define EXTI_FTSR_TR0_Pos (0U)
1437#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
1438#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
1439#define EXTI_FTSR_TR1_Pos (1U)
1440#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
1441#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
1442#define EXTI_FTSR_TR2_Pos (2U)
1443#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
1444#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
1445#define EXTI_FTSR_TR3_Pos (3U)
1446#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
1447#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
1448#define EXTI_FTSR_TR4_Pos (4U)
1449#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
1450#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
1451#define EXTI_FTSR_TR5_Pos (5U)
1452#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
1453#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
1454#define EXTI_FTSR_TR6_Pos (6U)
1455#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
1456#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
1457#define EXTI_FTSR_TR7_Pos (7U)
1458#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
1459#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
1460#define EXTI_FTSR_TR8_Pos (8U)
1461#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
1462#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
1463#define EXTI_FTSR_TR9_Pos (9U)
1464#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
1465#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
1466#define EXTI_FTSR_TR10_Pos (10U)
1467#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
1468#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
1469#define EXTI_FTSR_TR11_Pos (11U)
1470#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
1471#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
1472#define EXTI_FTSR_TR12_Pos (12U)
1473#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
1474#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
1475#define EXTI_FTSR_TR13_Pos (13U)
1476#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
1477#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
1478#define EXTI_FTSR_TR14_Pos (14U)
1479#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
1480#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
1481#define EXTI_FTSR_TR15_Pos (15U)
1482#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
1483#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
1484#define EXTI_FTSR_TR16_Pos (16U)
1485#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
1486#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
1487#define EXTI_FTSR_TR17_Pos (17U)
1488#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
1489#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
1490#define EXTI_FTSR_TR19_Pos (19U)
1491#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
1492#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
1493
1494/* References Defines */
1495#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
1496#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
1497#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
1498#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
1499#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
1500#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
1501#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
1502#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
1503#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
1504#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
1505#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
1506#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
1507#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
1508#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
1509#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
1510#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
1511#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
1512#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
1513#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
1514
1515/******************* Bit definition for EXTI_SWIER register *******************/
1516#define EXTI_SWIER_SWIER0_Pos (0U)
1517#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
1518#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
1519#define EXTI_SWIER_SWIER1_Pos (1U)
1520#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
1521#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
1522#define EXTI_SWIER_SWIER2_Pos (2U)
1523#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
1524#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
1525#define EXTI_SWIER_SWIER3_Pos (3U)
1526#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
1527#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
1528#define EXTI_SWIER_SWIER4_Pos (4U)
1529#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
1530#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
1531#define EXTI_SWIER_SWIER5_Pos (5U)
1532#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
1533#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
1534#define EXTI_SWIER_SWIER6_Pos (6U)
1535#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
1536#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
1537#define EXTI_SWIER_SWIER7_Pos (7U)
1538#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
1539#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
1540#define EXTI_SWIER_SWIER8_Pos (8U)
1541#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
1542#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
1543#define EXTI_SWIER_SWIER9_Pos (9U)
1544#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
1545#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
1546#define EXTI_SWIER_SWIER10_Pos (10U)
1547#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
1548#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
1549#define EXTI_SWIER_SWIER11_Pos (11U)
1550#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
1551#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
1552#define EXTI_SWIER_SWIER12_Pos (12U)
1553#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
1554#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
1555#define EXTI_SWIER_SWIER13_Pos (13U)
1556#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
1557#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
1558#define EXTI_SWIER_SWIER14_Pos (14U)
1559#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
1560#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
1561#define EXTI_SWIER_SWIER15_Pos (15U)
1562#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
1563#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
1564#define EXTI_SWIER_SWIER16_Pos (16U)
1565#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
1566#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
1567#define EXTI_SWIER_SWIER17_Pos (17U)
1568#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
1569#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
1570#define EXTI_SWIER_SWIER19_Pos (19U)
1571#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
1572#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
1573
1574/* References Defines */
1575#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
1576#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
1577#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
1578#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
1579#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
1580#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
1581#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
1582#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
1583#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
1584#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
1585#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
1586#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
1587#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
1588#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
1589#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
1590#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
1591#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
1592#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
1593#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
1594
1595/****************** Bit definition for EXTI_PR register *********************/
1596#define EXTI_PR_PR0_Pos (0U)
1597#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
1598#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit 0 */
1599#define EXTI_PR_PR1_Pos (1U)
1600#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
1601#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit 1 */
1602#define EXTI_PR_PR2_Pos (2U)
1603#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
1604#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit 2 */
1605#define EXTI_PR_PR3_Pos (3U)
1606#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
1607#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit 3 */
1608#define EXTI_PR_PR4_Pos (4U)
1609#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
1610#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit 4 */
1611#define EXTI_PR_PR5_Pos (5U)
1612#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
1613#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit 5 */
1614#define EXTI_PR_PR6_Pos (6U)
1615#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
1616#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit 6 */
1617#define EXTI_PR_PR7_Pos (7U)
1618#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
1619#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit 7 */
1620#define EXTI_PR_PR8_Pos (8U)
1621#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
1622#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit 8 */
1623#define EXTI_PR_PR9_Pos (9U)
1624#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
1625#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit 9 */
1626#define EXTI_PR_PR10_Pos (10U)
1627#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
1628#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit 10 */
1629#define EXTI_PR_PR11_Pos (11U)
1630#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
1631#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit 11 */
1632#define EXTI_PR_PR12_Pos (12U)
1633#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
1634#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit 12 */
1635#define EXTI_PR_PR13_Pos (13U)
1636#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
1637#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit 13 */
1638#define EXTI_PR_PR14_Pos (14U)
1639#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
1640#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit 14 */
1641#define EXTI_PR_PR15_Pos (15U)
1642#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
1643#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit 15 */
1644#define EXTI_PR_PR16_Pos (16U)
1645#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
1646#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit 16 */
1647#define EXTI_PR_PR17_Pos (17U)
1648#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
1649#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit 17 */
1650#define EXTI_PR_PR19_Pos (19U)
1651#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
1652#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit 19 */
1653
1654/* References Defines */
1655#define EXTI_PR_PIF0 EXTI_PR_PR0
1656#define EXTI_PR_PIF1 EXTI_PR_PR1
1657#define EXTI_PR_PIF2 EXTI_PR_PR2
1658#define EXTI_PR_PIF3 EXTI_PR_PR3
1659#define EXTI_PR_PIF4 EXTI_PR_PR4
1660#define EXTI_PR_PIF5 EXTI_PR_PR5
1661#define EXTI_PR_PIF6 EXTI_PR_PR6
1662#define EXTI_PR_PIF7 EXTI_PR_PR7
1663#define EXTI_PR_PIF8 EXTI_PR_PR8
1664#define EXTI_PR_PIF9 EXTI_PR_PR9
1665#define EXTI_PR_PIF10 EXTI_PR_PR10
1666#define EXTI_PR_PIF11 EXTI_PR_PR11
1667#define EXTI_PR_PIF12 EXTI_PR_PR12
1668#define EXTI_PR_PIF13 EXTI_PR_PR13
1669#define EXTI_PR_PIF14 EXTI_PR_PR14
1670#define EXTI_PR_PIF15 EXTI_PR_PR15
1671#define EXTI_PR_PIF16 EXTI_PR_PR16
1672#define EXTI_PR_PIF17 EXTI_PR_PR17
1673#define EXTI_PR_PIF19 EXTI_PR_PR19
1674
1675/******************************************************************************/
1676/* */
1677/* FLASH and Option Bytes Registers */
1678/* */
1679/******************************************************************************/
1680
1681/******************* Bit definition for FLASH_ACR register ******************/
1682#define FLASH_ACR_LATENCY_Pos (0U)
1683#define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
1684#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
1685
1686#define FLASH_ACR_PRFTBE_Pos (4U)
1687#define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
1688#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
1689#define FLASH_ACR_PRFTBS_Pos (5U)
1690#define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
1691#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
1692
1693/****************** Bit definition for FLASH_KEYR register ******************/
1694#define FLASH_KEYR_FKEYR_Pos (0U)
1695#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
1696#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
1697
1698/***************** Bit definition for FLASH_OPTKEYR register ****************/
1699#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
1700#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
1701#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
1702
1703/****************** FLASH Keys **********************************************/
1704#define FLASH_KEY1_Pos (0U)
1705#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
1706#define FLASH_KEY1 FLASH_KEY1_Msk /*!< Flash program erase key1 */
1707#define FLASH_KEY2_Pos (0U)
1708#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
1709#define FLASH_KEY2 FLASH_KEY2_Msk /*!< Flash program erase key2: used with FLASH_PEKEY1
1710 to unlock the write access to the FPEC. */
1711
1712#define FLASH_OPTKEY1_Pos (0U)
1713#define FLASH_OPTKEY1_Msk (0x45670123U << FLASH_OPTKEY1_Pos) /*!< 0x45670123 */
1714#define FLASH_OPTKEY1 FLASH_OPTKEY1_Msk /*!< Flash option key1 */
1715#define FLASH_OPTKEY2_Pos (0U)
1716#define FLASH_OPTKEY2_Msk (0xCDEF89ABU << FLASH_OPTKEY2_Pos) /*!< 0xCDEF89AB */
1717#define FLASH_OPTKEY2 FLASH_OPTKEY2_Msk /*!< Flash option key2: used with FLASH_OPTKEY1 to
1718 unlock the write access to the option byte block */
1719
1720/****************** Bit definition for FLASH_SR register *******************/
1721#define FLASH_SR_BSY_Pos (0U)
1722#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
1723#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
1724#define FLASH_SR_PGERR_Pos (2U)
1725#define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
1726#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
1727#define FLASH_SR_WRPRTERR_Pos (4U)
1728#define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
1729#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
1730#define FLASH_SR_EOP_Pos (5U)
1731#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
1732#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
1733#define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
1734
1735/******************* Bit definition for FLASH_CR register *******************/
1736#define FLASH_CR_PG_Pos (0U)
1737#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
1738#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
1739#define FLASH_CR_PER_Pos (1U)
1740#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
1741#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
1742#define FLASH_CR_MER_Pos (2U)
1743#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
1744#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
1745#define FLASH_CR_OPTPG_Pos (4U)
1746#define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
1747#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
1748#define FLASH_CR_OPTER_Pos (5U)
1749#define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
1750#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
1751#define FLASH_CR_STRT_Pos (6U)
1752#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
1753#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
1754#define FLASH_CR_LOCK_Pos (7U)
1755#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
1756#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
1757#define FLASH_CR_OPTWRE_Pos (9U)
1758#define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
1759#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
1760#define FLASH_CR_ERRIE_Pos (10U)
1761#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
1762#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
1763#define FLASH_CR_EOPIE_Pos (12U)
1764#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
1765#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
1766#define FLASH_CR_OBL_LAUNCH_Pos (13U)
1767#define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x00002000 */
1768#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Option Bytes Loader Launch */
1769
1770/******************* Bit definition for FLASH_AR register *******************/
1771#define FLASH_AR_FAR_Pos (0U)
1772#define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
1773#define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
1774
1775/****************** Bit definition for FLASH_OBR register *******************/
1776#define FLASH_OBR_OPTERR_Pos (0U)
1777#define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
1778#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
1779#define FLASH_OBR_RDPRT1_Pos (1U)
1780#define FLASH_OBR_RDPRT1_Msk (0x1U << FLASH_OBR_RDPRT1_Pos) /*!< 0x00000002 */
1781#define FLASH_OBR_RDPRT1 FLASH_OBR_RDPRT1_Msk /*!< Read protection Level 1 */
1782#define FLASH_OBR_RDPRT2_Pos (2U)
1783#define FLASH_OBR_RDPRT2_Msk (0x1U << FLASH_OBR_RDPRT2_Pos) /*!< 0x00000004 */
1784#define FLASH_OBR_RDPRT2 FLASH_OBR_RDPRT2_Msk /*!< Read protection Level 2 */
1785
1786#define FLASH_OBR_USER_Pos (8U)
1787#define FLASH_OBR_USER_Msk (0x77U << FLASH_OBR_USER_Pos) /*!< 0x00007700 */
1788#define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
1789#define FLASH_OBR_IWDG_SW_Pos (8U)
1790#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000100 */
1791#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
1792#define FLASH_OBR_nRST_STOP_Pos (9U)
1793#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000200 */
1794#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
1795#define FLASH_OBR_nRST_STDBY_Pos (10U)
1796#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000400 */
1797#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
1798#define FLASH_OBR_nBOOT1_Pos (12U)
1799#define FLASH_OBR_nBOOT1_Msk (0x1U << FLASH_OBR_nBOOT1_Pos) /*!< 0x00001000 */
1800#define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk /*!< nBOOT1 */
1801#define FLASH_OBR_VDDA_MONITOR_Pos (13U)
1802#define FLASH_OBR_VDDA_MONITOR_Msk (0x1U << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */
1803#define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk /*!< VDDA power supply supervisor */
1804#define FLASH_OBR_RAM_PARITY_CHECK_Pos (14U)
1805#define FLASH_OBR_RAM_PARITY_CHECK_Msk (0x1U << FLASH_OBR_RAM_PARITY_CHECK_Pos) /*!< 0x00004000 */
1806#define FLASH_OBR_RAM_PARITY_CHECK FLASH_OBR_RAM_PARITY_CHECK_Msk /*!< RAM parity check */
1807#define FLASH_OBR_DATA0_Pos (16U)
1808#define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x00FF0000 */
1809#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
1810#define FLASH_OBR_DATA1_Pos (24U)
1811#define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0xFF000000 */
1812#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
1813
1814/* Old BOOT1 bit definition, maintained for legacy purpose */
1815#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
1816
1817/* Old OBR_VDDA bit definition, maintained for legacy purpose */
1818#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
1819
1820/****************** Bit definition for FLASH_WRPR register ******************/
1821#define FLASH_WRPR_WRP_Pos (0U)
1822#define FLASH_WRPR_WRP_Msk (0xFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
1823#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
1824
1825/*----------------------------------------------------------------------------*/
1826
1827/****************** Bit definition for OB_RDP register **********************/
1828#define OB_RDP_RDP_Pos (0U)
1829#define OB_RDP_RDP_Msk (0xFFU << OB_RDP_RDP_Pos) /*!< 0x000000FF */
1830#define OB_RDP_RDP OB_RDP_RDP_Msk /*!< Read protection option byte */
1831#define OB_RDP_nRDP_Pos (8U)
1832#define OB_RDP_nRDP_Msk (0xFFU << OB_RDP_nRDP_Pos) /*!< 0x0000FF00 */
1833#define OB_RDP_nRDP OB_RDP_nRDP_Msk /*!< Read protection complemented option byte */
1834
1835/****************** Bit definition for OB_USER register *********************/
1836#define OB_USER_USER_Pos (16U)
1837#define OB_USER_USER_Msk (0xFFU << OB_USER_USER_Pos) /*!< 0x00FF0000 */
1838#define OB_USER_USER OB_USER_USER_Msk /*!< User option byte */
1839#define OB_USER_nUSER_Pos (24U)
1840#define OB_USER_nUSER_Msk (0xFFU << OB_USER_nUSER_Pos) /*!< 0xFF000000 */
1841#define OB_USER_nUSER OB_USER_nUSER_Msk /*!< User complemented option byte */
1842
1843/****************** Bit definition for OB_WRP0 register *********************/
1844#define OB_WRP0_WRP0_Pos (0U)
1845#define OB_WRP0_WRP0_Msk (0xFFU << OB_WRP0_WRP0_Pos) /*!< 0x000000FF */
1846#define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
1847#define OB_WRP0_nWRP0_Pos (8U)
1848#define OB_WRP0_nWRP0_Msk (0xFFU << OB_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
1849#define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
1850
1851/****************** Bit definition for OB_WRP1 register *********************/
1852#define OB_WRP1_WRP1_Pos (16U)
1853#define OB_WRP1_WRP1_Msk (0xFFU << OB_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
1854#define OB_WRP1_WRP1 OB_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
1855#define OB_WRP1_nWRP1_Pos (24U)
1856#define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
1857#define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
1858
1859/******************************************************************************/
1860/* */
1861/* General Purpose IOs (GPIO) */
1862/* */
1863/******************************************************************************/
1864/******************* Bit definition for GPIO_MODER register *****************/
1865#define GPIO_MODER_MODER0_Pos (0U)
1866#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
1867#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
1868#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
1869#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
1870#define GPIO_MODER_MODER1_Pos (2U)
1871#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
1872#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
1873#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
1874#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
1875#define GPIO_MODER_MODER2_Pos (4U)
1876#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
1877#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
1878#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
1879#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
1880#define GPIO_MODER_MODER3_Pos (6U)
1881#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
1882#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
1883#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
1884#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
1885#define GPIO_MODER_MODER4_Pos (8U)
1886#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
1887#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
1888#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
1889#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
1890#define GPIO_MODER_MODER5_Pos (10U)
1891#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
1892#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
1893#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
1894#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
1895#define GPIO_MODER_MODER6_Pos (12U)
1896#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
1897#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
1898#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
1899#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
1900#define GPIO_MODER_MODER7_Pos (14U)
1901#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
1902#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
1903#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
1904#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
1905#define GPIO_MODER_MODER8_Pos (16U)
1906#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
1907#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
1908#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
1909#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
1910#define GPIO_MODER_MODER9_Pos (18U)
1911#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
1912#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
1913#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
1914#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
1915#define GPIO_MODER_MODER10_Pos (20U)
1916#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
1917#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
1918#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
1919#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
1920#define GPIO_MODER_MODER11_Pos (22U)
1921#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
1922#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
1923#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
1924#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
1925#define GPIO_MODER_MODER12_Pos (24U)
1926#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
1927#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
1928#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
1929#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
1930#define GPIO_MODER_MODER13_Pos (26U)
1931#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
1932#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
1933#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
1934#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
1935#define GPIO_MODER_MODER14_Pos (28U)
1936#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
1937#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
1938#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
1939#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
1940#define GPIO_MODER_MODER15_Pos (30U)
1941#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
1942#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
1943#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
1944#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
1945
1946/****************** Bit definition for GPIO_OTYPER register *****************/
1947#define GPIO_OTYPER_OT_0 (0x00000001U)
1948#define GPIO_OTYPER_OT_1 (0x00000002U)
1949#define GPIO_OTYPER_OT_2 (0x00000004U)
1950#define GPIO_OTYPER_OT_3 (0x00000008U)
1951#define GPIO_OTYPER_OT_4 (0x00000010U)
1952#define GPIO_OTYPER_OT_5 (0x00000020U)
1953#define GPIO_OTYPER_OT_6 (0x00000040U)
1954#define GPIO_OTYPER_OT_7 (0x00000080U)
1955#define GPIO_OTYPER_OT_8 (0x00000100U)
1956#define GPIO_OTYPER_OT_9 (0x00000200U)
1957#define GPIO_OTYPER_OT_10 (0x00000400U)
1958#define GPIO_OTYPER_OT_11 (0x00000800U)
1959#define GPIO_OTYPER_OT_12 (0x00001000U)
1960#define GPIO_OTYPER_OT_13 (0x00002000U)
1961#define GPIO_OTYPER_OT_14 (0x00004000U)
1962#define GPIO_OTYPER_OT_15 (0x00008000U)
1963
1964/**************** Bit definition for GPIO_OSPEEDR register ******************/
1965#define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)
1966#define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */
1967#define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk
1968#define GPIO_OSPEEDR_OSPEEDR0_0 (0x1U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */
1969#define GPIO_OSPEEDR_OSPEEDR0_1 (0x2U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */
1970#define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)
1971#define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */
1972#define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk
1973#define GPIO_OSPEEDR_OSPEEDR1_0 (0x1U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */
1974#define GPIO_OSPEEDR_OSPEEDR1_1 (0x2U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */
1975#define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)
1976#define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */
1977#define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk
1978#define GPIO_OSPEEDR_OSPEEDR2_0 (0x1U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */
1979#define GPIO_OSPEEDR_OSPEEDR2_1 (0x2U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */
1980#define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)
1981#define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */
1982#define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk
1983#define GPIO_OSPEEDR_OSPEEDR3_0 (0x1U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */
1984#define GPIO_OSPEEDR_OSPEEDR3_1 (0x2U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */
1985#define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)
1986#define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */
1987#define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk
1988#define GPIO_OSPEEDR_OSPEEDR4_0 (0x1U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */
1989#define GPIO_OSPEEDR_OSPEEDR4_1 (0x2U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */
1990#define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)
1991#define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */
1992#define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk
1993#define GPIO_OSPEEDR_OSPEEDR5_0 (0x1U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */
1994#define GPIO_OSPEEDR_OSPEEDR5_1 (0x2U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */
1995#define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)
1996#define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */
1997#define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk
1998#define GPIO_OSPEEDR_OSPEEDR6_0 (0x1U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */
1999#define GPIO_OSPEEDR_OSPEEDR6_1 (0x2U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */
2000#define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)
2001#define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */
2002#define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk
2003#define GPIO_OSPEEDR_OSPEEDR7_0 (0x1U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */
2004#define GPIO_OSPEEDR_OSPEEDR7_1 (0x2U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */
2005#define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)
2006#define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */
2007#define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk
2008#define GPIO_OSPEEDR_OSPEEDR8_0 (0x1U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */
2009#define GPIO_OSPEEDR_OSPEEDR8_1 (0x2U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */
2010#define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)
2011#define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */
2012#define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk
2013#define GPIO_OSPEEDR_OSPEEDR9_0 (0x1U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */
2014#define GPIO_OSPEEDR_OSPEEDR9_1 (0x2U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */
2015#define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)
2016#define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */
2017#define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk
2018#define GPIO_OSPEEDR_OSPEEDR10_0 (0x1U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */
2019#define GPIO_OSPEEDR_OSPEEDR10_1 (0x2U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */
2020#define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)
2021#define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */
2022#define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk
2023#define GPIO_OSPEEDR_OSPEEDR11_0 (0x1U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */
2024#define GPIO_OSPEEDR_OSPEEDR11_1 (0x2U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */
2025#define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)
2026#define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */
2027#define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk
2028#define GPIO_OSPEEDR_OSPEEDR12_0 (0x1U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */
2029#define GPIO_OSPEEDR_OSPEEDR12_1 (0x2U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */
2030#define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)
2031#define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */
2032#define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk
2033#define GPIO_OSPEEDR_OSPEEDR13_0 (0x1U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */
2034#define GPIO_OSPEEDR_OSPEEDR13_1 (0x2U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */
2035#define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)
2036#define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */
2037#define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk
2038#define GPIO_OSPEEDR_OSPEEDR14_0 (0x1U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */
2039#define GPIO_OSPEEDR_OSPEEDR14_1 (0x2U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */
2040#define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)
2041#define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */
2042#define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk
2043#define GPIO_OSPEEDR_OSPEEDR15_0 (0x1U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */
2044#define GPIO_OSPEEDR_OSPEEDR15_1 (0x2U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */
2045
2046/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
2047#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
2048#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
2049#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
2050#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
2051#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
2052#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
2053#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
2054#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
2055#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
2056#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
2057#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
2058#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
2059#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
2060#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
2061#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
2062#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
2063#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
2064#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
2065#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
2066#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
2067#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
2068#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
2069#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
2070#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
2071#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
2072#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
2073#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
2074#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
2075#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
2076#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
2077#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
2078#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
2079#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
2080#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
2081#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
2082#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
2083#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
2084#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
2085#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
2086#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
2087#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
2088#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
2089#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
2090#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
2091#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
2092#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
2093#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
2094#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
2095
2096/******************* Bit definition for GPIO_PUPDR register ******************/
2097#define GPIO_PUPDR_PUPDR0_Pos (0U)
2098#define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */
2099#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
2100#define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */
2101#define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */
2102#define GPIO_PUPDR_PUPDR1_Pos (2U)
2103#define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */
2104#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
2105#define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */
2106#define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */
2107#define GPIO_PUPDR_PUPDR2_Pos (4U)
2108#define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */
2109#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
2110#define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */
2111#define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */
2112#define GPIO_PUPDR_PUPDR3_Pos (6U)
2113#define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */
2114#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
2115#define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */
2116#define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */
2117#define GPIO_PUPDR_PUPDR4_Pos (8U)
2118#define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */
2119#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
2120#define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */
2121#define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */
2122#define GPIO_PUPDR_PUPDR5_Pos (10U)
2123#define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */
2124#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
2125#define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */
2126#define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */
2127#define GPIO_PUPDR_PUPDR6_Pos (12U)
2128#define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */
2129#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
2130#define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */
2131#define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */
2132#define GPIO_PUPDR_PUPDR7_Pos (14U)
2133#define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */
2134#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
2135#define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */
2136#define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */
2137#define GPIO_PUPDR_PUPDR8_Pos (16U)
2138#define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */
2139#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
2140#define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */
2141#define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */
2142#define GPIO_PUPDR_PUPDR9_Pos (18U)
2143#define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */
2144#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
2145#define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */
2146#define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */
2147#define GPIO_PUPDR_PUPDR10_Pos (20U)
2148#define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */
2149#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
2150#define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */
2151#define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */
2152#define GPIO_PUPDR_PUPDR11_Pos (22U)
2153#define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */
2154#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
2155#define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */
2156#define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */
2157#define GPIO_PUPDR_PUPDR12_Pos (24U)
2158#define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */
2159#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
2160#define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */
2161#define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */
2162#define GPIO_PUPDR_PUPDR13_Pos (26U)
2163#define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */
2164#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
2165#define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */
2166#define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */
2167#define GPIO_PUPDR_PUPDR14_Pos (28U)
2168#define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */
2169#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
2170#define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */
2171#define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */
2172#define GPIO_PUPDR_PUPDR15_Pos (30U)
2173#define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */
2174#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
2175#define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */
2176#define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
2177
2178/******************* Bit definition for GPIO_IDR register *******************/
2179#define GPIO_IDR_0 (0x00000001U)
2180#define GPIO_IDR_1 (0x00000002U)
2181#define GPIO_IDR_2 (0x00000004U)
2182#define GPIO_IDR_3 (0x00000008U)
2183#define GPIO_IDR_4 (0x00000010U)
2184#define GPIO_IDR_5 (0x00000020U)
2185#define GPIO_IDR_6 (0x00000040U)
2186#define GPIO_IDR_7 (0x00000080U)
2187#define GPIO_IDR_8 (0x00000100U)
2188#define GPIO_IDR_9 (0x00000200U)
2189#define GPIO_IDR_10 (0x00000400U)
2190#define GPIO_IDR_11 (0x00000800U)
2191#define GPIO_IDR_12 (0x00001000U)
2192#define GPIO_IDR_13 (0x00002000U)
2193#define GPIO_IDR_14 (0x00004000U)
2194#define GPIO_IDR_15 (0x00008000U)
2195
2196/****************** Bit definition for GPIO_ODR register ********************/
2197#define GPIO_ODR_0 (0x00000001U)
2198#define GPIO_ODR_1 (0x00000002U)
2199#define GPIO_ODR_2 (0x00000004U)
2200#define GPIO_ODR_3 (0x00000008U)
2201#define GPIO_ODR_4 (0x00000010U)
2202#define GPIO_ODR_5 (0x00000020U)
2203#define GPIO_ODR_6 (0x00000040U)
2204#define GPIO_ODR_7 (0x00000080U)
2205#define GPIO_ODR_8 (0x00000100U)
2206#define GPIO_ODR_9 (0x00000200U)
2207#define GPIO_ODR_10 (0x00000400U)
2208#define GPIO_ODR_11 (0x00000800U)
2209#define GPIO_ODR_12 (0x00001000U)
2210#define GPIO_ODR_13 (0x00002000U)
2211#define GPIO_ODR_14 (0x00004000U)
2212#define GPIO_ODR_15 (0x00008000U)
2213
2214/****************** Bit definition for GPIO_BSRR register ********************/
2215#define GPIO_BSRR_BS_0 (0x00000001U)
2216#define GPIO_BSRR_BS_1 (0x00000002U)
2217#define GPIO_BSRR_BS_2 (0x00000004U)
2218#define GPIO_BSRR_BS_3 (0x00000008U)
2219#define GPIO_BSRR_BS_4 (0x00000010U)
2220#define GPIO_BSRR_BS_5 (0x00000020U)
2221#define GPIO_BSRR_BS_6 (0x00000040U)
2222#define GPIO_BSRR_BS_7 (0x00000080U)
2223#define GPIO_BSRR_BS_8 (0x00000100U)
2224#define GPIO_BSRR_BS_9 (0x00000200U)
2225#define GPIO_BSRR_BS_10 (0x00000400U)
2226#define GPIO_BSRR_BS_11 (0x00000800U)
2227#define GPIO_BSRR_BS_12 (0x00001000U)
2228#define GPIO_BSRR_BS_13 (0x00002000U)
2229#define GPIO_BSRR_BS_14 (0x00004000U)
2230#define GPIO_BSRR_BS_15 (0x00008000U)
2231#define GPIO_BSRR_BR_0 (0x00010000U)
2232#define GPIO_BSRR_BR_1 (0x00020000U)
2233#define GPIO_BSRR_BR_2 (0x00040000U)
2234#define GPIO_BSRR_BR_3 (0x00080000U)
2235#define GPIO_BSRR_BR_4 (0x00100000U)
2236#define GPIO_BSRR_BR_5 (0x00200000U)
2237#define GPIO_BSRR_BR_6 (0x00400000U)
2238#define GPIO_BSRR_BR_7 (0x00800000U)
2239#define GPIO_BSRR_BR_8 (0x01000000U)
2240#define GPIO_BSRR_BR_9 (0x02000000U)
2241#define GPIO_BSRR_BR_10 (0x04000000U)
2242#define GPIO_BSRR_BR_11 (0x08000000U)
2243#define GPIO_BSRR_BR_12 (0x10000000U)
2244#define GPIO_BSRR_BR_13 (0x20000000U)
2245#define GPIO_BSRR_BR_14 (0x40000000U)
2246#define GPIO_BSRR_BR_15 (0x80000000U)
2247
2248/****************** Bit definition for GPIO_LCKR register ********************/
2249#define GPIO_LCKR_LCK0_Pos (0U)
2250#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
2251#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
2252#define GPIO_LCKR_LCK1_Pos (1U)
2253#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
2254#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
2255#define GPIO_LCKR_LCK2_Pos (2U)
2256#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
2257#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
2258#define GPIO_LCKR_LCK3_Pos (3U)
2259#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
2260#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
2261#define GPIO_LCKR_LCK4_Pos (4U)
2262#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
2263#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
2264#define GPIO_LCKR_LCK5_Pos (5U)
2265#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
2266#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
2267#define GPIO_LCKR_LCK6_Pos (6U)
2268#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
2269#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
2270#define GPIO_LCKR_LCK7_Pos (7U)
2271#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
2272#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
2273#define GPIO_LCKR_LCK8_Pos (8U)
2274#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
2275#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
2276#define GPIO_LCKR_LCK9_Pos (9U)
2277#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
2278#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
2279#define GPIO_LCKR_LCK10_Pos (10U)
2280#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
2281#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
2282#define GPIO_LCKR_LCK11_Pos (11U)
2283#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
2284#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
2285#define GPIO_LCKR_LCK12_Pos (12U)
2286#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
2287#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
2288#define GPIO_LCKR_LCK13_Pos (13U)
2289#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
2290#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
2291#define GPIO_LCKR_LCK14_Pos (14U)
2292#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
2293#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
2294#define GPIO_LCKR_LCK15_Pos (15U)
2295#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
2296#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
2297#define GPIO_LCKR_LCKK_Pos (16U)
2298#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
2299#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
2300
2301/****************** Bit definition for GPIO_AFRL register ********************/
2302#define GPIO_AFRL_AFSEL0_Pos (0U)
2303#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
2304#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
2305#define GPIO_AFRL_AFSEL1_Pos (4U)
2306#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
2307#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
2308#define GPIO_AFRL_AFSEL2_Pos (8U)
2309#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
2310#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
2311#define GPIO_AFRL_AFSEL3_Pos (12U)
2312#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
2313#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
2314#define GPIO_AFRL_AFSEL4_Pos (16U)
2315#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
2316#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
2317#define GPIO_AFRL_AFSEL5_Pos (20U)
2318#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
2319#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
2320#define GPIO_AFRL_AFSEL6_Pos (24U)
2321#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
2322#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
2323#define GPIO_AFRL_AFSEL7_Pos (28U)
2324#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
2325#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
2326
2327/* Legacy aliases */
2328#define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos
2329#define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk
2330#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
2331#define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos
2332#define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk
2333#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
2334#define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos
2335#define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk
2336#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
2337#define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos
2338#define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk
2339#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
2340#define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos
2341#define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk
2342#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
2343#define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos
2344#define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk
2345#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
2346#define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos
2347#define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk
2348#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
2349#define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos
2350#define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk
2351#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
2352
2353/****************** Bit definition for GPIO_AFRH register ********************/
2354#define GPIO_AFRH_AFSEL8_Pos (0U)
2355#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
2356#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
2357#define GPIO_AFRH_AFSEL9_Pos (4U)
2358#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
2359#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
2360#define GPIO_AFRH_AFSEL10_Pos (8U)
2361#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
2362#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
2363#define GPIO_AFRH_AFSEL11_Pos (12U)
2364#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
2365#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
2366#define GPIO_AFRH_AFSEL12_Pos (16U)
2367#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
2368#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
2369#define GPIO_AFRH_AFSEL13_Pos (20U)
2370#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
2371#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
2372#define GPIO_AFRH_AFSEL14_Pos (24U)
2373#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
2374#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
2375#define GPIO_AFRH_AFSEL15_Pos (28U)
2376#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
2377#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
2378
2379/* Legacy aliases */
2380#define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos
2381#define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk
2382#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
2383#define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos
2384#define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk
2385#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
2386#define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos
2387#define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk
2388#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
2389#define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos
2390#define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk
2391#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
2392#define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos
2393#define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk
2394#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
2395#define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos
2396#define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk
2397#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
2398#define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos
2399#define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk
2400#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
2401#define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos
2402#define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk
2403#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
2404
2405/****************** Bit definition for GPIO_BRR register *********************/
2406#define GPIO_BRR_BR_0 (0x00000001U)
2407#define GPIO_BRR_BR_1 (0x00000002U)
2408#define GPIO_BRR_BR_2 (0x00000004U)
2409#define GPIO_BRR_BR_3 (0x00000008U)
2410#define GPIO_BRR_BR_4 (0x00000010U)
2411#define GPIO_BRR_BR_5 (0x00000020U)
2412#define GPIO_BRR_BR_6 (0x00000040U)
2413#define GPIO_BRR_BR_7 (0x00000080U)
2414#define GPIO_BRR_BR_8 (0x00000100U)
2415#define GPIO_BRR_BR_9 (0x00000200U)
2416#define GPIO_BRR_BR_10 (0x00000400U)
2417#define GPIO_BRR_BR_11 (0x00000800U)
2418#define GPIO_BRR_BR_12 (0x00001000U)
2419#define GPIO_BRR_BR_13 (0x00002000U)
2420#define GPIO_BRR_BR_14 (0x00004000U)
2421#define GPIO_BRR_BR_15 (0x00008000U)
2422
2423/******************************************************************************/
2424/* */
2425/* Inter-integrated Circuit Interface (I2C) */
2426/* */
2427/******************************************************************************/
2428
2429/******************* Bit definition for I2C_CR1 register *******************/
2430#define I2C_CR1_PE_Pos (0U)
2431#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
2432#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
2433#define I2C_CR1_TXIE_Pos (1U)
2434#define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
2435#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
2436#define I2C_CR1_RXIE_Pos (2U)
2437#define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
2438#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
2439#define I2C_CR1_ADDRIE_Pos (3U)
2440#define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
2441#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
2442#define I2C_CR1_NACKIE_Pos (4U)
2443#define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
2444#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
2445#define I2C_CR1_STOPIE_Pos (5U)
2446#define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
2447#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
2448#define I2C_CR1_TCIE_Pos (6U)
2449#define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
2450#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
2451#define I2C_CR1_ERRIE_Pos (7U)
2452#define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
2453#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
2454#define I2C_CR1_DNF_Pos (8U)
2455#define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
2456#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
2457#define I2C_CR1_ANFOFF_Pos (12U)
2458#define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
2459#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
2460#define I2C_CR1_SWRST_Pos (13U)
2461#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
2462#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
2463#define I2C_CR1_TXDMAEN_Pos (14U)
2464#define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
2465#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
2466#define I2C_CR1_RXDMAEN_Pos (15U)
2467#define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
2468#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
2469#define I2C_CR1_SBC_Pos (16U)
2470#define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
2471#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
2472#define I2C_CR1_NOSTRETCH_Pos (17U)
2473#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
2474#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
2475#define I2C_CR1_GCEN_Pos (19U)
2476#define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
2477#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
2478#define I2C_CR1_SMBHEN_Pos (20U)
2479#define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
2480#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
2481#define I2C_CR1_SMBDEN_Pos (21U)
2482#define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
2483#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
2484#define I2C_CR1_ALERTEN_Pos (22U)
2485#define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
2486#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
2487#define I2C_CR1_PECEN_Pos (23U)
2488#define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
2489#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
2490
2491/****************** Bit definition for I2C_CR2 register ********************/
2492#define I2C_CR2_SADD_Pos (0U)
2493#define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
2494#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
2495#define I2C_CR2_RD_WRN_Pos (10U)
2496#define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
2497#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
2498#define I2C_CR2_ADD10_Pos (11U)
2499#define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
2500#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
2501#define I2C_CR2_HEAD10R_Pos (12U)
2502#define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
2503#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
2504#define I2C_CR2_START_Pos (13U)
2505#define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
2506#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
2507#define I2C_CR2_STOP_Pos (14U)
2508#define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
2509#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
2510#define I2C_CR2_NACK_Pos (15U)
2511#define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
2512#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
2513#define I2C_CR2_NBYTES_Pos (16U)
2514#define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
2515#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
2516#define I2C_CR2_RELOAD_Pos (24U)
2517#define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
2518#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
2519#define I2C_CR2_AUTOEND_Pos (25U)
2520#define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
2521#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
2522#define I2C_CR2_PECBYTE_Pos (26U)
2523#define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
2524#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
2525
2526/******************* Bit definition for I2C_OAR1 register ******************/
2527#define I2C_OAR1_OA1_Pos (0U)
2528#define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
2529#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
2530#define I2C_OAR1_OA1MODE_Pos (10U)
2531#define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
2532#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
2533#define I2C_OAR1_OA1EN_Pos (15U)
2534#define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
2535#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
2536
2537/******************* Bit definition for I2C_OAR2 register ******************/
2538#define I2C_OAR2_OA2_Pos (1U)
2539#define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
2540#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
2541#define I2C_OAR2_OA2MSK_Pos (8U)
2542#define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
2543#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
2544#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
2545#define I2C_OAR2_OA2MASK01_Pos (8U)
2546#define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
2547#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
2548#define I2C_OAR2_OA2MASK02_Pos (9U)
2549#define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
2550#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
2551#define I2C_OAR2_OA2MASK03_Pos (8U)
2552#define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
2553#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
2554#define I2C_OAR2_OA2MASK04_Pos (10U)
2555#define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
2556#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
2557#define I2C_OAR2_OA2MASK05_Pos (8U)
2558#define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
2559#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
2560#define I2C_OAR2_OA2MASK06_Pos (9U)
2561#define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
2562#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
2563#define I2C_OAR2_OA2MASK07_Pos (8U)
2564#define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
2565#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
2566#define I2C_OAR2_OA2EN_Pos (15U)
2567#define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
2568#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
2569
2570/******************* Bit definition for I2C_TIMINGR register ****************/
2571#define I2C_TIMINGR_SCLL_Pos (0U)
2572#define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
2573#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
2574#define I2C_TIMINGR_SCLH_Pos (8U)
2575#define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
2576#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
2577#define I2C_TIMINGR_SDADEL_Pos (16U)
2578#define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
2579#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
2580#define I2C_TIMINGR_SCLDEL_Pos (20U)
2581#define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
2582#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
2583#define I2C_TIMINGR_PRESC_Pos (28U)
2584#define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
2585#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
2586
2587/******************* Bit definition for I2C_TIMEOUTR register ****************/
2588#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
2589#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
2590#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
2591#define I2C_TIMEOUTR_TIDLE_Pos (12U)
2592#define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
2593#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
2594#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
2595#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
2596#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
2597#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
2598#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
2599#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
2600#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
2601#define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
2602#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
2603
2604/****************** Bit definition for I2C_ISR register ********************/
2605#define I2C_ISR_TXE_Pos (0U)
2606#define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
2607#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
2608#define I2C_ISR_TXIS_Pos (1U)
2609#define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
2610#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
2611#define I2C_ISR_RXNE_Pos (2U)
2612#define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
2613#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
2614#define I2C_ISR_ADDR_Pos (3U)
2615#define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
2616#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
2617#define I2C_ISR_NACKF_Pos (4U)
2618#define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
2619#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
2620#define I2C_ISR_STOPF_Pos (5U)
2621#define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
2622#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
2623#define I2C_ISR_TC_Pos (6U)
2624#define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
2625#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
2626#define I2C_ISR_TCR_Pos (7U)
2627#define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
2628#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
2629#define I2C_ISR_BERR_Pos (8U)
2630#define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
2631#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
2632#define I2C_ISR_ARLO_Pos (9U)
2633#define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
2634#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
2635#define I2C_ISR_OVR_Pos (10U)
2636#define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
2637#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
2638#define I2C_ISR_PECERR_Pos (11U)
2639#define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
2640#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
2641#define I2C_ISR_TIMEOUT_Pos (12U)
2642#define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
2643#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
2644#define I2C_ISR_ALERT_Pos (13U)
2645#define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
2646#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
2647#define I2C_ISR_BUSY_Pos (15U)
2648#define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
2649#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
2650#define I2C_ISR_DIR_Pos (16U)
2651#define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
2652#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
2653#define I2C_ISR_ADDCODE_Pos (17U)
2654#define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
2655#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
2656
2657/****************** Bit definition for I2C_ICR register ********************/
2658#define I2C_ICR_ADDRCF_Pos (3U)
2659#define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
2660#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
2661#define I2C_ICR_NACKCF_Pos (4U)
2662#define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
2663#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
2664#define I2C_ICR_STOPCF_Pos (5U)
2665#define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
2666#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
2667#define I2C_ICR_BERRCF_Pos (8U)
2668#define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
2669#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
2670#define I2C_ICR_ARLOCF_Pos (9U)
2671#define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
2672#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
2673#define I2C_ICR_OVRCF_Pos (10U)
2674#define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
2675#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
2676#define I2C_ICR_PECCF_Pos (11U)
2677#define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
2678#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
2679#define I2C_ICR_TIMOUTCF_Pos (12U)
2680#define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
2681#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
2682#define I2C_ICR_ALERTCF_Pos (13U)
2683#define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
2684#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
2685
2686/****************** Bit definition for I2C_PECR register *******************/
2687#define I2C_PECR_PEC_Pos (0U)
2688#define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
2689#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
2690
2691/****************** Bit definition for I2C_RXDR register *********************/
2692#define I2C_RXDR_RXDATA_Pos (0U)
2693#define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
2694#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
2695
2696/****************** Bit definition for I2C_TXDR register *******************/
2697#define I2C_TXDR_TXDATA_Pos (0U)
2698#define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
2699#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
2700
2701/*****************************************************************************/
2702/* */
2703/* Independent WATCHDOG (IWDG) */
2704/* */
2705/*****************************************************************************/
2706/******************* Bit definition for IWDG_KR register *******************/
2707#define IWDG_KR_KEY_Pos (0U)
2708#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
2709#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
2710
2711/******************* Bit definition for IWDG_PR register *******************/
2712#define IWDG_PR_PR_Pos (0U)
2713#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
2714#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
2715#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
2716#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
2717#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
2718
2719/******************* Bit definition for IWDG_RLR register ******************/
2720#define IWDG_RLR_RL_Pos (0U)
2721#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
2722#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
2723
2724/******************* Bit definition for IWDG_SR register *******************/
2725#define IWDG_SR_PVU_Pos (0U)
2726#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
2727#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
2728#define IWDG_SR_RVU_Pos (1U)
2729#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
2730#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
2731#define IWDG_SR_WVU_Pos (2U)
2732#define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
2733#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
2734
2735/******************* Bit definition for IWDG_KR register *******************/
2736#define IWDG_WINR_WIN_Pos (0U)
2737#define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
2738#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
2739
2740/*****************************************************************************/
2741/* */
2742/* Power Control (PWR) */
2743/* */
2744/*****************************************************************************/
2745
2746/* Note: No specific macro feature on this device */
2747
2748
2749/******************** Bit definition for PWR_CR register *******************/
2750#define PWR_CR_LPDS_Pos (0U)
2751#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
2752#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-power Deepsleep */
2753#define PWR_CR_PDDS_Pos (1U)
2754#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
2755#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
2756#define PWR_CR_CWUF_Pos (2U)
2757#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
2758#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
2759#define PWR_CR_CSBF_Pos (3U)
2760#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
2761#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
2762#define PWR_CR_DBP_Pos (8U)
2763#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
2764#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
2765
2766/******************* Bit definition for PWR_CSR register *******************/
2767#define PWR_CSR_WUF_Pos (0U)
2768#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
2769#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
2770#define PWR_CSR_SBF_Pos (1U)
2771#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
2772#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
2773
2774#define PWR_CSR_EWUP1_Pos (8U)
2775#define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
2776#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
2777#define PWR_CSR_EWUP2_Pos (9U)
2778#define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
2779#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
2780
2781/*****************************************************************************/
2782/* */
2783/* Reset and Clock Control */
2784/* */
2785/*****************************************************************************/
2786/*
2787* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
2788*/
2789
2790/******************** Bit definition for RCC_CR register *******************/
2791#define RCC_CR_HSION_Pos (0U)
2792#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
2793#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
2794#define RCC_CR_HSIRDY_Pos (1U)
2795#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
2796#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
2797
2798#define RCC_CR_HSITRIM_Pos (3U)
2799#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
2800#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
2801#define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
2802#define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
2803#define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
2804#define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
2805#define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
2806
2807#define RCC_CR_HSICAL_Pos (8U)
2808#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
2809#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
2810#define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
2811#define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
2812#define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
2813#define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
2814#define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
2815#define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
2816#define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
2817#define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
2818
2819#define RCC_CR_HSEON_Pos (16U)
2820#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
2821#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
2822#define RCC_CR_HSERDY_Pos (17U)
2823#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
2824#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
2825#define RCC_CR_HSEBYP_Pos (18U)
2826#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
2827#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
2828#define RCC_CR_CSSON_Pos (19U)
2829#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
2830#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
2831#define RCC_CR_PLLON_Pos (24U)
2832#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
2833#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
2834#define RCC_CR_PLLRDY_Pos (25U)
2835#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
2836#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
2837
2838/******************** Bit definition for RCC_CFGR register *****************/
2839/*!< SW configuration */
2840#define RCC_CFGR_SW_Pos (0U)
2841#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
2842#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
2843#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
2844#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
2845
2846#define RCC_CFGR_SW_HSI (0x00000000U) /*!< HSI selected as system clock */
2847#define RCC_CFGR_SW_HSE (0x00000001U) /*!< HSE selected as system clock */
2848#define RCC_CFGR_SW_PLL (0x00000002U) /*!< PLL selected as system clock */
2849
2850/*!< SWS configuration */
2851#define RCC_CFGR_SWS_Pos (2U)
2852#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
2853#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
2854#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
2855#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
2856
2857#define RCC_CFGR_SWS_HSI (0x00000000U) /*!< HSI oscillator used as system clock */
2858#define RCC_CFGR_SWS_HSE (0x00000004U) /*!< HSE oscillator used as system clock */
2859#define RCC_CFGR_SWS_PLL (0x00000008U) /*!< PLL used as system clock */
2860
2861/*!< HPRE configuration */
2862#define RCC_CFGR_HPRE_Pos (4U)
2863#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
2864#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
2865#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
2866#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
2867#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
2868#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
2869
2870#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
2871#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
2872#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
2873#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
2874#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
2875#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
2876#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
2877#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
2878#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
2879
2880/*!< PPRE configuration */
2881#define RCC_CFGR_PPRE_Pos (8U)
2882#define RCC_CFGR_PPRE_Msk (0x7U << RCC_CFGR_PPRE_Pos) /*!< 0x00000700 */
2883#define RCC_CFGR_PPRE RCC_CFGR_PPRE_Msk /*!< PRE[2:0] bits (APB prescaler) */
2884#define RCC_CFGR_PPRE_0 (0x1U << RCC_CFGR_PPRE_Pos) /*!< 0x00000100 */
2885#define RCC_CFGR_PPRE_1 (0x2U << RCC_CFGR_PPRE_Pos) /*!< 0x00000200 */
2886#define RCC_CFGR_PPRE_2 (0x4U << RCC_CFGR_PPRE_Pos) /*!< 0x00000400 */
2887
2888#define RCC_CFGR_PPRE_DIV1 (0x00000000U) /*!< HCLK not divided */
2889#define RCC_CFGR_PPRE_DIV2_Pos (10U)
2890#define RCC_CFGR_PPRE_DIV2_Msk (0x1U << RCC_CFGR_PPRE_DIV2_Pos) /*!< 0x00000400 */
2891#define RCC_CFGR_PPRE_DIV2 RCC_CFGR_PPRE_DIV2_Msk /*!< HCLK divided by 2 */
2892#define RCC_CFGR_PPRE_DIV4_Pos (8U)
2893#define RCC_CFGR_PPRE_DIV4_Msk (0x5U << RCC_CFGR_PPRE_DIV4_Pos) /*!< 0x00000500 */
2894#define RCC_CFGR_PPRE_DIV4 RCC_CFGR_PPRE_DIV4_Msk /*!< HCLK divided by 4 */
2895#define RCC_CFGR_PPRE_DIV8_Pos (9U)
2896#define RCC_CFGR_PPRE_DIV8_Msk (0x3U << RCC_CFGR_PPRE_DIV8_Pos) /*!< 0x00000600 */
2897#define RCC_CFGR_PPRE_DIV8 RCC_CFGR_PPRE_DIV8_Msk /*!< HCLK divided by 8 */
2898#define RCC_CFGR_PPRE_DIV16_Pos (8U)
2899#define RCC_CFGR_PPRE_DIV16_Msk (0x7U << RCC_CFGR_PPRE_DIV16_Pos) /*!< 0x00000700 */
2900#define RCC_CFGR_PPRE_DIV16 RCC_CFGR_PPRE_DIV16_Msk /*!< HCLK divided by 16 */
2901
2902/*!< ADCPPRE configuration */
2903#define RCC_CFGR_ADCPRE_Pos (14U)
2904#define RCC_CFGR_ADCPRE_Msk (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
2905#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE bit (ADC prescaler) */
2906
2907#define RCC_CFGR_ADCPRE_DIV2 (0x00000000U) /*!< PCLK divided by 2 */
2908#define RCC_CFGR_ADCPRE_DIV4 (0x00004000U) /*!< PCLK divided by 4 */
2909
2910#define RCC_CFGR_PLLSRC_Pos (16U)
2911#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
2912#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
2913#define RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U) /*!< HSI clock divided by 2 selected as PLL entry clock source */
2914#define RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U) /*!< HSE/PREDIV clock selected as PLL entry clock source */
2915
2916#define RCC_CFGR_PLLXTPRE_Pos (17U)
2917#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
2918#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
2919#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 (0x00000000U) /*!< HSE/PREDIV clock not divided for PLL entry */
2920#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 (0x00020000U) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
2921
2922/*!< PLLMUL configuration */
2923#define RCC_CFGR_PLLMUL_Pos (18U)
2924#define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
2925#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
2926#define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
2927#define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
2928#define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
2929#define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
2930
2931#define RCC_CFGR_PLLMUL2 (0x00000000U) /*!< PLL input clock*2 */
2932#define RCC_CFGR_PLLMUL3 (0x00040000U) /*!< PLL input clock*3 */
2933#define RCC_CFGR_PLLMUL4 (0x00080000U) /*!< PLL input clock*4 */
2934#define RCC_CFGR_PLLMUL5 (0x000C0000U) /*!< PLL input clock*5 */
2935#define RCC_CFGR_PLLMUL6 (0x00100000U) /*!< PLL input clock*6 */
2936#define RCC_CFGR_PLLMUL7 (0x00140000U) /*!< PLL input clock*7 */
2937#define RCC_CFGR_PLLMUL8 (0x00180000U) /*!< PLL input clock*8 */
2938#define RCC_CFGR_PLLMUL9 (0x001C0000U) /*!< PLL input clock*9 */
2939#define RCC_CFGR_PLLMUL10 (0x00200000U) /*!< PLL input clock10 */
2940#define RCC_CFGR_PLLMUL11 (0x00240000U) /*!< PLL input clock*11 */
2941#define RCC_CFGR_PLLMUL12 (0x00280000U) /*!< PLL input clock*12 */
2942#define RCC_CFGR_PLLMUL13 (0x002C0000U) /*!< PLL input clock*13 */
2943#define RCC_CFGR_PLLMUL14 (0x00300000U) /*!< PLL input clock*14 */
2944#define RCC_CFGR_PLLMUL15 (0x00340000U) /*!< PLL input clock*15 */
2945#define RCC_CFGR_PLLMUL16 (0x00380000U) /*!< PLL input clock*16 */
2946
2947/*!< MCO configuration */
2948#define RCC_CFGR_MCO_Pos (24U)
2949#define RCC_CFGR_MCO_Msk (0xFU << RCC_CFGR_MCO_Pos) /*!< 0x0F000000 */
2950#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
2951#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
2952#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
2953#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
2954
2955#define RCC_CFGR_MCO_NOCLOCK (0x00000000U) /*!< No clock */
2956#define RCC_CFGR_MCO_HSI14 (0x01000000U) /*!< HSI14 clock selected as MCO source */
2957#define RCC_CFGR_MCO_LSI (0x02000000U) /*!< LSI clock selected as MCO source */
2958#define RCC_CFGR_MCO_LSE (0x03000000U) /*!< LSE clock selected as MCO source */
2959#define RCC_CFGR_MCO_SYSCLK (0x04000000U) /*!< System clock selected as MCO source */
2960#define RCC_CFGR_MCO_HSI (0x05000000U) /*!< HSI clock selected as MCO source */
2961#define RCC_CFGR_MCO_HSE (0x06000000U) /*!< HSE clock selected as MCO source */
2962#define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divided by 2 selected as MCO source */
2963
2964/* Reference defines */
2965#define RCC_CFGR_MCOSEL RCC_CFGR_MCO
2966#define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
2967#define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
2968#define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
2969#define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
2970#define RCC_CFGR_MCOSEL_HSI14 RCC_CFGR_MCO_HSI14
2971#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI
2972#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE
2973#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
2974#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
2975#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
2976#define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
2977
2978/*!<****************** Bit definition for RCC_CIR register *****************/
2979#define RCC_CIR_LSIRDYF_Pos (0U)
2980#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
2981#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
2982#define RCC_CIR_LSERDYF_Pos (1U)
2983#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
2984#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
2985#define RCC_CIR_HSIRDYF_Pos (2U)
2986#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
2987#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
2988#define RCC_CIR_HSERDYF_Pos (3U)
2989#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
2990#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
2991#define RCC_CIR_PLLRDYF_Pos (4U)
2992#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
2993#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
2994#define RCC_CIR_HSI14RDYF_Pos (5U)
2995#define RCC_CIR_HSI14RDYF_Msk (0x1U << RCC_CIR_HSI14RDYF_Pos) /*!< 0x00000020 */
2996#define RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF_Msk /*!< HSI14 Ready Interrupt flag */
2997#define RCC_CIR_CSSF_Pos (7U)
2998#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
2999#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
3000#define RCC_CIR_LSIRDYIE_Pos (8U)
3001#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
3002#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
3003#define RCC_CIR_LSERDYIE_Pos (9U)
3004#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
3005#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
3006#define RCC_CIR_HSIRDYIE_Pos (10U)
3007#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
3008#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
3009#define RCC_CIR_HSERDYIE_Pos (11U)
3010#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
3011#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
3012#define RCC_CIR_PLLRDYIE_Pos (12U)
3013#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
3014#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
3015#define RCC_CIR_HSI14RDYIE_Pos (13U)
3016#define RCC_CIR_HSI14RDYIE_Msk (0x1U << RCC_CIR_HSI14RDYIE_Pos) /*!< 0x00002000 */
3017#define RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE_Msk /*!< HSI14 Ready Interrupt Enable */
3018#define RCC_CIR_LSIRDYC_Pos (16U)
3019#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
3020#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
3021#define RCC_CIR_LSERDYC_Pos (17U)
3022#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
3023#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
3024#define RCC_CIR_HSIRDYC_Pos (18U)
3025#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
3026#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
3027#define RCC_CIR_HSERDYC_Pos (19U)
3028#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
3029#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
3030#define RCC_CIR_PLLRDYC_Pos (20U)
3031#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
3032#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
3033#define RCC_CIR_HSI14RDYC_Pos (21U)
3034#define RCC_CIR_HSI14RDYC_Msk (0x1U << RCC_CIR_HSI14RDYC_Pos) /*!< 0x00200000 */
3035#define RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC_Msk /*!< HSI14 Ready Interrupt Clear */
3036#define RCC_CIR_CSSC_Pos (23U)
3037#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
3038#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
3039
3040/***************** Bit definition for RCC_APB2RSTR register ****************/
3041#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
3042#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
3043#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
3044#define RCC_APB2RSTR_ADCRST_Pos (9U)
3045#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
3046#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */
3047#define RCC_APB2RSTR_TIM1RST_Pos (11U)
3048#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
3049#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */
3050#define RCC_APB2RSTR_SPI1RST_Pos (12U)
3051#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
3052#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
3053#define RCC_APB2RSTR_USART1RST_Pos (14U)
3054#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
3055#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
3056#define RCC_APB2RSTR_TIM15RST_Pos (16U)
3057#define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
3058#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */
3059#define RCC_APB2RSTR_TIM16RST_Pos (17U)
3060#define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
3061#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */
3062#define RCC_APB2RSTR_TIM17RST_Pos (18U)
3063#define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
3064#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */
3065#define RCC_APB2RSTR_DBGMCURST_Pos (22U)
3066#define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */
3067#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */
3068
3069/*!< Old ADC1 reset bit definition maintained for legacy purpose */
3070#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
3071
3072/***************** Bit definition for RCC_APB1RSTR register ****************/
3073#define RCC_APB1RSTR_TIM3RST_Pos (1U)
3074#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
3075#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
3076#define RCC_APB1RSTR_TIM6RST_Pos (4U)
3077#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
3078#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
3079#define RCC_APB1RSTR_TIM14RST_Pos (8U)
3080#define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
3081#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */
3082#define RCC_APB1RSTR_WWDGRST_Pos (11U)
3083#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
3084#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
3085#define RCC_APB1RSTR_SPI2RST_Pos (14U)
3086#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
3087#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */
3088#define RCC_APB1RSTR_USART2RST_Pos (17U)
3089#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
3090#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
3091#define RCC_APB1RSTR_I2C1RST_Pos (21U)
3092#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
3093#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
3094#define RCC_APB1RSTR_I2C2RST_Pos (22U)
3095#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
3096#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
3097#define RCC_APB1RSTR_PWRRST_Pos (28U)
3098#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
3099#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
3100
3101/****************** Bit definition for RCC_AHBENR register *****************/
3102#define RCC_AHBENR_DMAEN_Pos (0U)
3103#define RCC_AHBENR_DMAEN_Msk (0x1U << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
3104#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
3105#define RCC_AHBENR_SRAMEN_Pos (2U)
3106#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
3107#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
3108#define RCC_AHBENR_FLITFEN_Pos (4U)
3109#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
3110#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
3111#define RCC_AHBENR_CRCEN_Pos (6U)
3112#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
3113#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
3114#define RCC_AHBENR_GPIOAEN_Pos (17U)
3115#define RCC_AHBENR_GPIOAEN_Msk (0x1U << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00020000 */
3116#define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIOA clock enable */
3117#define RCC_AHBENR_GPIOBEN_Pos (18U)
3118#define RCC_AHBENR_GPIOBEN_Msk (0x1U << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00040000 */
3119#define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIOB clock enable */
3120#define RCC_AHBENR_GPIOCEN_Pos (19U)
3121#define RCC_AHBENR_GPIOCEN_Msk (0x1U << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00080000 */
3122#define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIOC clock enable */
3123#define RCC_AHBENR_GPIODEN_Pos (20U)
3124#define RCC_AHBENR_GPIODEN_Msk (0x1U << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00100000 */
3125#define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIOD clock enable */
3126#define RCC_AHBENR_GPIOFEN_Pos (22U)
3127#define RCC_AHBENR_GPIOFEN_Msk (0x1U << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00400000 */
3128#define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /*!< GPIOF clock enable */
3129
3130/* Old Bit definition maintained for legacy purpose */
3131#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
3132#define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
3133
3134/***************** Bit definition for RCC_APB2ENR register *****************/
3135#define RCC_APB2ENR_SYSCFGCOMPEN_Pos (0U)
3136#define RCC_APB2ENR_SYSCFGCOMPEN_Msk (0x1U << RCC_APB2ENR_SYSCFGCOMPEN_Pos) /*!< 0x00000001 */
3137#define RCC_APB2ENR_SYSCFGCOMPEN RCC_APB2ENR_SYSCFGCOMPEN_Msk /*!< SYSCFG and comparator clock enable */
3138#define RCC_APB2ENR_ADCEN_Pos (9U)
3139#define RCC_APB2ENR_ADCEN_Msk (0x1U << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
3140#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
3141#define RCC_APB2ENR_TIM1EN_Pos (11U)
3142#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
3143#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */
3144#define RCC_APB2ENR_SPI1EN_Pos (12U)
3145#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
3146#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
3147#define RCC_APB2ENR_USART1EN_Pos (14U)
3148#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
3149#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
3150#define RCC_APB2ENR_TIM15EN_Pos (16U)
3151#define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
3152#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 clock enable */
3153#define RCC_APB2ENR_TIM16EN_Pos (17U)
3154#define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
3155#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 clock enable */
3156#define RCC_APB2ENR_TIM17EN_Pos (18U)
3157#define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
3158#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 clock enable */
3159#define RCC_APB2ENR_DBGMCUEN_Pos (22U)
3160#define RCC_APB2ENR_DBGMCUEN_Msk (0x1U << RCC_APB2ENR_DBGMCUEN_Pos) /*!< 0x00400000 */
3161#define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGMCUEN_Msk /*!< DBGMCU clock enable */
3162
3163/* Old Bit definition maintained for legacy purpose */
3164#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
3165#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
3166
3167/***************** Bit definition for RCC_APB1ENR register *****************/
3168#define RCC_APB1ENR_TIM3EN_Pos (1U)
3169#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
3170#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
3171#define RCC_APB1ENR_TIM6EN_Pos (4U)
3172#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
3173#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
3174#define RCC_APB1ENR_TIM14EN_Pos (8U)
3175#define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
3176#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk /*!< Timer 14 clock enable */
3177#define RCC_APB1ENR_WWDGEN_Pos (11U)
3178#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
3179#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
3180#define RCC_APB1ENR_SPI2EN_Pos (14U)
3181#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
3182#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */
3183#define RCC_APB1ENR_USART2EN_Pos (17U)
3184#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
3185#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
3186#define RCC_APB1ENR_I2C1EN_Pos (21U)
3187#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
3188#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
3189#define RCC_APB1ENR_I2C2EN_Pos (22U)
3190#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
3191#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */
3192#define RCC_APB1ENR_PWREN_Pos (28U)
3193#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
3194#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
3195
3196/******************* Bit definition for RCC_BDCR register ******************/
3197#define RCC_BDCR_LSEON_Pos (0U)
3198#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
3199#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
3200#define RCC_BDCR_LSERDY_Pos (1U)
3201#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
3202#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
3203#define RCC_BDCR_LSEBYP_Pos (2U)
3204#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
3205#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
3206
3207#define RCC_BDCR_LSEDRV_Pos (3U)
3208#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
3209#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
3210#define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
3211#define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
3212
3213#define RCC_BDCR_RTCSEL_Pos (8U)
3214#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
3215#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
3216#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
3217#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
3218
3219/*!< RTC configuration */
3220#define RCC_BDCR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
3221#define RCC_BDCR_RTCSEL_LSE (0x00000100U) /*!< LSE oscillator clock used as RTC clock */
3222#define RCC_BDCR_RTCSEL_LSI (0x00000200U) /*!< LSI oscillator clock used as RTC clock */
3223#define RCC_BDCR_RTCSEL_HSE (0x00000300U) /*!< HSE oscillator clock divided by 128 used as RTC clock */
3224
3225#define RCC_BDCR_RTCEN_Pos (15U)
3226#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
3227#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
3228#define RCC_BDCR_BDRST_Pos (16U)
3229#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
3230#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
3231
3232/******************* Bit definition for RCC_CSR register *******************/
3233#define RCC_CSR_LSION_Pos (0U)
3234#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
3235#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
3236#define RCC_CSR_LSIRDY_Pos (1U)
3237#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
3238#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
3239#define RCC_CSR_V18PWRRSTF_Pos (23U)
3240#define RCC_CSR_V18PWRRSTF_Msk (0x1U << RCC_CSR_V18PWRRSTF_Pos) /*!< 0x00800000 */
3241#define RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF_Msk /*!< V1.8 power domain reset flag */
3242#define RCC_CSR_RMVF_Pos (24U)
3243#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
3244#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
3245#define RCC_CSR_OBLRSTF_Pos (25U)
3246#define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
3247#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
3248#define RCC_CSR_PINRSTF_Pos (26U)
3249#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
3250#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
3251#define RCC_CSR_PORRSTF_Pos (27U)
3252#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
3253#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
3254#define RCC_CSR_SFTRSTF_Pos (28U)
3255#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
3256#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
3257#define RCC_CSR_IWDGRSTF_Pos (29U)
3258#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
3259#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
3260#define RCC_CSR_WWDGRSTF_Pos (30U)
3261#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
3262#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
3263#define RCC_CSR_LPWRRSTF_Pos (31U)
3264#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
3265#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
3266
3267/* Old Bit definition maintained for legacy purpose */
3268#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
3269
3270/******************* Bit definition for RCC_AHBRSTR register ***************/
3271#define RCC_AHBRSTR_GPIOARST_Pos (17U)
3272#define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
3273#define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */
3274#define RCC_AHBRSTR_GPIOBRST_Pos (18U)
3275#define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
3276#define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */
3277#define RCC_AHBRSTR_GPIOCRST_Pos (19U)
3278#define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
3279#define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */
3280#define RCC_AHBRSTR_GPIODRST_Pos (20U)
3281#define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */
3282#define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD reset */
3283#define RCC_AHBRSTR_GPIOFRST_Pos (22U)
3284#define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
3285#define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */
3286
3287/******************* Bit definition for RCC_CFGR2 register *****************/
3288/*!< PREDIV configuration */
3289#define RCC_CFGR2_PREDIV_Pos (0U)
3290#define RCC_CFGR2_PREDIV_Msk (0xFU << RCC_CFGR2_PREDIV_Pos) /*!< 0x0000000F */
3291#define RCC_CFGR2_PREDIV RCC_CFGR2_PREDIV_Msk /*!< PREDIV[3:0] bits */
3292#define RCC_CFGR2_PREDIV_0 (0x1U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000001 */
3293#define RCC_CFGR2_PREDIV_1 (0x2U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000002 */
3294#define RCC_CFGR2_PREDIV_2 (0x4U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000004 */
3295#define RCC_CFGR2_PREDIV_3 (0x8U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000008 */
3296
3297#define RCC_CFGR2_PREDIV_DIV1 (0x00000000U) /*!< PREDIV input clock not divided */
3298#define RCC_CFGR2_PREDIV_DIV2 (0x00000001U) /*!< PREDIV input clock divided by 2 */
3299#define RCC_CFGR2_PREDIV_DIV3 (0x00000002U) /*!< PREDIV input clock divided by 3 */
3300#define RCC_CFGR2_PREDIV_DIV4 (0x00000003U) /*!< PREDIV input clock divided by 4 */
3301#define RCC_CFGR2_PREDIV_DIV5 (0x00000004U) /*!< PREDIV input clock divided by 5 */
3302#define RCC_CFGR2_PREDIV_DIV6 (0x00000005U) /*!< PREDIV input clock divided by 6 */
3303#define RCC_CFGR2_PREDIV_DIV7 (0x00000006U) /*!< PREDIV input clock divided by 7 */
3304#define RCC_CFGR2_PREDIV_DIV8 (0x00000007U) /*!< PREDIV input clock divided by 8 */
3305#define RCC_CFGR2_PREDIV_DIV9 (0x00000008U) /*!< PREDIV input clock divided by 9 */
3306#define RCC_CFGR2_PREDIV_DIV10 (0x00000009U) /*!< PREDIV input clock divided by 10 */
3307#define RCC_CFGR2_PREDIV_DIV11 (0x0000000AU) /*!< PREDIV input clock divided by 11 */
3308#define RCC_CFGR2_PREDIV_DIV12 (0x0000000BU) /*!< PREDIV input clock divided by 12 */
3309#define RCC_CFGR2_PREDIV_DIV13 (0x0000000CU) /*!< PREDIV input clock divided by 13 */
3310#define RCC_CFGR2_PREDIV_DIV14 (0x0000000DU) /*!< PREDIV input clock divided by 14 */
3311#define RCC_CFGR2_PREDIV_DIV15 (0x0000000EU) /*!< PREDIV input clock divided by 15 */
3312#define RCC_CFGR2_PREDIV_DIV16 (0x0000000FU) /*!< PREDIV input clock divided by 16 */
3313
3314/******************* Bit definition for RCC_CFGR3 register *****************/
3315/*!< USART1 Clock source selection */
3316#define RCC_CFGR3_USART1SW_Pos (0U)
3317#define RCC_CFGR3_USART1SW_Msk (0x3U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000003 */
3318#define RCC_CFGR3_USART1SW RCC_CFGR3_USART1SW_Msk /*!< USART1SW[1:0] bits */
3319#define RCC_CFGR3_USART1SW_0 (0x1U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000001 */
3320#define RCC_CFGR3_USART1SW_1 (0x2U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000002 */
3321
3322#define RCC_CFGR3_USART1SW_PCLK (0x00000000U) /*!< PCLK clock used as USART1 clock source */
3323#define RCC_CFGR3_USART1SW_SYSCLK (0x00000001U) /*!< System clock selected as USART1 clock source */
3324#define RCC_CFGR3_USART1SW_LSE (0x00000002U) /*!< LSE oscillator clock used as USART1 clock source */
3325#define RCC_CFGR3_USART1SW_HSI (0x00000003U) /*!< HSI oscillator clock used as USART1 clock source */
3326
3327/*!< I2C1 Clock source selection */
3328#define RCC_CFGR3_I2C1SW_Pos (4U)
3329#define RCC_CFGR3_I2C1SW_Msk (0x1U << RCC_CFGR3_I2C1SW_Pos) /*!< 0x00000010 */
3330#define RCC_CFGR3_I2C1SW RCC_CFGR3_I2C1SW_Msk /*!< I2C1SW bits */
3331
3332#define RCC_CFGR3_I2C1SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C1 clock source */
3333#define RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U)
3334#define RCC_CFGR3_I2C1SW_SYSCLK_Msk (0x1U << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /*!< 0x00000010 */
3335#define RCC_CFGR3_I2C1SW_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK_Msk /*!< System clock selected as I2C1 clock source */
3336
3337/******************* Bit definition for RCC_CR2 register *******************/
3338#define RCC_CR2_HSI14ON_Pos (0U)
3339#define RCC_CR2_HSI14ON_Msk (0x1U << RCC_CR2_HSI14ON_Pos) /*!< 0x00000001 */
3340#define RCC_CR2_HSI14ON RCC_CR2_HSI14ON_Msk /*!< Internal High Speed 14MHz clock enable */
3341#define RCC_CR2_HSI14RDY_Pos (1U)
3342#define RCC_CR2_HSI14RDY_Msk (0x1U << RCC_CR2_HSI14RDY_Pos) /*!< 0x00000002 */
3343#define RCC_CR2_HSI14RDY RCC_CR2_HSI14RDY_Msk /*!< Internal High Speed 14MHz clock ready flag */
3344#define RCC_CR2_HSI14DIS_Pos (2U)
3345#define RCC_CR2_HSI14DIS_Msk (0x1U << RCC_CR2_HSI14DIS_Pos) /*!< 0x00000004 */
3346#define RCC_CR2_HSI14DIS RCC_CR2_HSI14DIS_Msk /*!< Internal High Speed 14MHz clock disable */
3347#define RCC_CR2_HSI14TRIM_Pos (3U)
3348#define RCC_CR2_HSI14TRIM_Msk (0x1FU << RCC_CR2_HSI14TRIM_Pos) /*!< 0x000000F8 */
3349#define RCC_CR2_HSI14TRIM RCC_CR2_HSI14TRIM_Msk /*!< Internal High Speed 14MHz clock trimming */
3350#define RCC_CR2_HSI14CAL_Pos (8U)
3351#define RCC_CR2_HSI14CAL_Msk (0xFFU << RCC_CR2_HSI14CAL_Pos) /*!< 0x0000FF00 */
3352#define RCC_CR2_HSI14CAL RCC_CR2_HSI14CAL_Msk /*!< Internal High Speed 14MHz clock Calibration */
3353
3354/*****************************************************************************/
3355/* */
3356/* Real-Time Clock (RTC) */
3357/* */
3358/*****************************************************************************/
3359/*
3360* @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
3361*/
3362#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
3363#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
3364
3365/******************** Bits definition for RTC_TR register ******************/
3366#define RTC_TR_PM_Pos (22U)
3367#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
3368#define RTC_TR_PM RTC_TR_PM_Msk
3369#define RTC_TR_HT_Pos (20U)
3370#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
3371#define RTC_TR_HT RTC_TR_HT_Msk
3372#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
3373#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
3374#define RTC_TR_HU_Pos (16U)
3375#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
3376#define RTC_TR_HU RTC_TR_HU_Msk
3377#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
3378#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
3379#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
3380#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
3381#define RTC_TR_MNT_Pos (12U)
3382#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
3383#define RTC_TR_MNT RTC_TR_MNT_Msk
3384#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
3385#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
3386#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
3387#define RTC_TR_MNU_Pos (8U)
3388#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
3389#define RTC_TR_MNU RTC_TR_MNU_Msk
3390#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
3391#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
3392#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
3393#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
3394#define RTC_TR_ST_Pos (4U)
3395#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
3396#define RTC_TR_ST RTC_TR_ST_Msk
3397#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
3398#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
3399#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
3400#define RTC_TR_SU_Pos (0U)
3401#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
3402#define RTC_TR_SU RTC_TR_SU_Msk
3403#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
3404#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
3405#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
3406#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
3407
3408/******************** Bits definition for RTC_DR register ******************/
3409#define RTC_DR_YT_Pos (20U)
3410#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
3411#define RTC_DR_YT RTC_DR_YT_Msk
3412#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
3413#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
3414#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
3415#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
3416#define RTC_DR_YU_Pos (16U)
3417#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
3418#define RTC_DR_YU RTC_DR_YU_Msk
3419#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
3420#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
3421#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
3422#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
3423#define RTC_DR_WDU_Pos (13U)
3424#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
3425#define RTC_DR_WDU RTC_DR_WDU_Msk
3426#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
3427#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
3428#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
3429#define RTC_DR_MT_Pos (12U)
3430#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
3431#define RTC_DR_MT RTC_DR_MT_Msk
3432#define RTC_DR_MU_Pos (8U)
3433#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
3434#define RTC_DR_MU RTC_DR_MU_Msk
3435#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
3436#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
3437#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
3438#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
3439#define RTC_DR_DT_Pos (4U)
3440#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
3441#define RTC_DR_DT RTC_DR_DT_Msk
3442#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
3443#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
3444#define RTC_DR_DU_Pos (0U)
3445#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
3446#define RTC_DR_DU RTC_DR_DU_Msk
3447#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
3448#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
3449#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
3450#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
3451
3452/******************** Bits definition for RTC_CR register ******************/
3453#define RTC_CR_COE_Pos (23U)
3454#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
3455#define RTC_CR_COE RTC_CR_COE_Msk
3456#define RTC_CR_OSEL_Pos (21U)
3457#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
3458#define RTC_CR_OSEL RTC_CR_OSEL_Msk
3459#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
3460#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
3461#define RTC_CR_POL_Pos (20U)
3462#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
3463#define RTC_CR_POL RTC_CR_POL_Msk
3464#define RTC_CR_COSEL_Pos (19U)
3465#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
3466#define RTC_CR_COSEL RTC_CR_COSEL_Msk
3467#define RTC_CR_BKP_Pos (18U)
3468#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
3469#define RTC_CR_BKP RTC_CR_BKP_Msk
3470#define RTC_CR_SUB1H_Pos (17U)
3471#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
3472#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
3473#define RTC_CR_ADD1H_Pos (16U)
3474#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
3475#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
3476#define RTC_CR_TSIE_Pos (15U)
3477#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
3478#define RTC_CR_TSIE RTC_CR_TSIE_Msk
3479#define RTC_CR_ALRAIE_Pos (12U)
3480#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
3481#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
3482#define RTC_CR_TSE_Pos (11U)
3483#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
3484#define RTC_CR_TSE RTC_CR_TSE_Msk
3485#define RTC_CR_ALRAE_Pos (8U)
3486#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
3487#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
3488#define RTC_CR_FMT_Pos (6U)
3489#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
3490#define RTC_CR_FMT RTC_CR_FMT_Msk
3491#define RTC_CR_BYPSHAD_Pos (5U)
3492#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
3493#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
3494#define RTC_CR_REFCKON_Pos (4U)
3495#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
3496#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
3497#define RTC_CR_TSEDGE_Pos (3U)
3498#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
3499#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
3500
3501/* Legacy defines */
3502#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
3503#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
3504#define RTC_CR_BCK RTC_CR_BKP
3505
3506/******************** Bits definition for RTC_ISR register *****************/
3507#define RTC_ISR_RECALPF_Pos (16U)
3508#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
3509#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
3510#define RTC_ISR_TAMP2F_Pos (14U)
3511#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
3512#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
3513#define RTC_ISR_TAMP1F_Pos (13U)
3514#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
3515#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
3516#define RTC_ISR_TSOVF_Pos (12U)
3517#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
3518#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
3519#define RTC_ISR_TSF_Pos (11U)
3520#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
3521#define RTC_ISR_TSF RTC_ISR_TSF_Msk
3522#define RTC_ISR_ALRAF_Pos (8U)
3523#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
3524#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
3525#define RTC_ISR_INIT_Pos (7U)
3526#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
3527#define RTC_ISR_INIT RTC_ISR_INIT_Msk
3528#define RTC_ISR_INITF_Pos (6U)
3529#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
3530#define RTC_ISR_INITF RTC_ISR_INITF_Msk
3531#define RTC_ISR_RSF_Pos (5U)
3532#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
3533#define RTC_ISR_RSF RTC_ISR_RSF_Msk
3534#define RTC_ISR_INITS_Pos (4U)
3535#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
3536#define RTC_ISR_INITS RTC_ISR_INITS_Msk
3537#define RTC_ISR_SHPF_Pos (3U)
3538#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
3539#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
3540#define RTC_ISR_ALRAWF_Pos (0U)
3541#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
3542#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
3543
3544/******************** Bits definition for RTC_PRER register ****************/
3545#define RTC_PRER_PREDIV_A_Pos (16U)
3546#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
3547#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
3548#define RTC_PRER_PREDIV_S_Pos (0U)
3549#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
3550#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
3551
3552/******************** Bits definition for RTC_ALRMAR register **************/
3553#define RTC_ALRMAR_MSK4_Pos (31U)
3554#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
3555#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
3556#define RTC_ALRMAR_WDSEL_Pos (30U)
3557#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
3558#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
3559#define RTC_ALRMAR_DT_Pos (28U)
3560#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
3561#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
3562#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
3563#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
3564#define RTC_ALRMAR_DU_Pos (24U)
3565#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
3566#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
3567#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
3568#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
3569#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
3570#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
3571#define RTC_ALRMAR_MSK3_Pos (23U)
3572#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
3573#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
3574#define RTC_ALRMAR_PM_Pos (22U)
3575#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
3576#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
3577#define RTC_ALRMAR_HT_Pos (20U)
3578#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
3579#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
3580#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
3581#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
3582#define RTC_ALRMAR_HU_Pos (16U)
3583#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
3584#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
3585#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
3586#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
3587#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
3588#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
3589#define RTC_ALRMAR_MSK2_Pos (15U)
3590#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
3591#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
3592#define RTC_ALRMAR_MNT_Pos (12U)
3593#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
3594#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
3595#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
3596#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
3597#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
3598#define RTC_ALRMAR_MNU_Pos (8U)
3599#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
3600#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
3601#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
3602#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
3603#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
3604#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
3605#define RTC_ALRMAR_MSK1_Pos (7U)
3606#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
3607#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
3608#define RTC_ALRMAR_ST_Pos (4U)
3609#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
3610#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
3611#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
3612#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
3613#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
3614#define RTC_ALRMAR_SU_Pos (0U)
3615#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
3616#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
3617#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
3618#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
3619#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
3620#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
3621
3622/******************** Bits definition for RTC_WPR register *****************/
3623#define RTC_WPR_KEY_Pos (0U)
3624#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
3625#define RTC_WPR_KEY RTC_WPR_KEY_Msk
3626
3627/******************** Bits definition for RTC_SSR register *****************/
3628#define RTC_SSR_SS_Pos (0U)
3629#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
3630#define RTC_SSR_SS RTC_SSR_SS_Msk
3631
3632/******************** Bits definition for RTC_SHIFTR register **************/
3633#define RTC_SHIFTR_SUBFS_Pos (0U)
3634#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
3635#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
3636#define RTC_SHIFTR_ADD1S_Pos (31U)
3637#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
3638#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
3639
3640/******************** Bits definition for RTC_TSTR register ****************/
3641#define RTC_TSTR_PM_Pos (22U)
3642#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
3643#define RTC_TSTR_PM RTC_TSTR_PM_Msk
3644#define RTC_TSTR_HT_Pos (20U)
3645#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
3646#define RTC_TSTR_HT RTC_TSTR_HT_Msk
3647#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
3648#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
3649#define RTC_TSTR_HU_Pos (16U)
3650#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
3651#define RTC_TSTR_HU RTC_TSTR_HU_Msk
3652#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
3653#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
3654#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
3655#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
3656#define RTC_TSTR_MNT_Pos (12U)
3657#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
3658#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
3659#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
3660#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
3661#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
3662#define RTC_TSTR_MNU_Pos (8U)
3663#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
3664#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
3665#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
3666#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
3667#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
3668#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
3669#define RTC_TSTR_ST_Pos (4U)
3670#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
3671#define RTC_TSTR_ST RTC_TSTR_ST_Msk
3672#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
3673#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
3674#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
3675#define RTC_TSTR_SU_Pos (0U)
3676#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
3677#define RTC_TSTR_SU RTC_TSTR_SU_Msk
3678#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
3679#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
3680#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
3681#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
3682
3683/******************** Bits definition for RTC_TSDR register ****************/
3684#define RTC_TSDR_WDU_Pos (13U)
3685#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
3686#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
3687#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
3688#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
3689#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
3690#define RTC_TSDR_MT_Pos (12U)
3691#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
3692#define RTC_TSDR_MT RTC_TSDR_MT_Msk
3693#define RTC_TSDR_MU_Pos (8U)
3694#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
3695#define RTC_TSDR_MU RTC_TSDR_MU_Msk
3696#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
3697#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
3698#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
3699#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
3700#define RTC_TSDR_DT_Pos (4U)
3701#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
3702#define RTC_TSDR_DT RTC_TSDR_DT_Msk
3703#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
3704#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
3705#define RTC_TSDR_DU_Pos (0U)
3706#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
3707#define RTC_TSDR_DU RTC_TSDR_DU_Msk
3708#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
3709#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
3710#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
3711#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
3712
3713/******************** Bits definition for RTC_TSSSR register ***************/
3714#define RTC_TSSSR_SS_Pos (0U)
3715#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
3716#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
3717
3718/******************** Bits definition for RTC_CALR register ****************/
3719#define RTC_CALR_CALP_Pos (15U)
3720#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
3721#define RTC_CALR_CALP RTC_CALR_CALP_Msk
3722#define RTC_CALR_CALW8_Pos (14U)
3723#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
3724#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
3725#define RTC_CALR_CALW16_Pos (13U)
3726#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
3727#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
3728#define RTC_CALR_CALM_Pos (0U)
3729#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
3730#define RTC_CALR_CALM RTC_CALR_CALM_Msk
3731#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
3732#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
3733#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
3734#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
3735#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
3736#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
3737#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
3738#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
3739#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
3740
3741/******************** Bits definition for RTC_TAFCR register ***************/
3742#define RTC_TAFCR_PC15MODE_Pos (23U)
3743#define RTC_TAFCR_PC15MODE_Msk (0x1U << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */
3744#define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk
3745#define RTC_TAFCR_PC15VALUE_Pos (22U)
3746#define RTC_TAFCR_PC15VALUE_Msk (0x1U << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */
3747#define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk
3748#define RTC_TAFCR_PC14MODE_Pos (21U)
3749#define RTC_TAFCR_PC14MODE_Msk (0x1U << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */
3750#define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk
3751#define RTC_TAFCR_PC14VALUE_Pos (20U)
3752#define RTC_TAFCR_PC14VALUE_Msk (0x1U << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */
3753#define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk
3754#define RTC_TAFCR_PC13MODE_Pos (19U)
3755#define RTC_TAFCR_PC13MODE_Msk (0x1U << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */
3756#define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk
3757#define RTC_TAFCR_PC13VALUE_Pos (18U)
3758#define RTC_TAFCR_PC13VALUE_Msk (0x1U << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */
3759#define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk
3760#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
3761#define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
3762#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
3763#define RTC_TAFCR_TAMPPRCH_Pos (13U)
3764#define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
3765#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
3766#define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
3767#define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
3768#define RTC_TAFCR_TAMPFLT_Pos (11U)
3769#define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
3770#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
3771#define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
3772#define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
3773#define RTC_TAFCR_TAMPFREQ_Pos (8U)
3774#define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
3775#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
3776#define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
3777#define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
3778#define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
3779#define RTC_TAFCR_TAMPTS_Pos (7U)
3780#define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
3781#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
3782#define RTC_TAFCR_TAMP2TRG_Pos (4U)
3783#define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
3784#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
3785#define RTC_TAFCR_TAMP2E_Pos (3U)
3786#define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
3787#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
3788#define RTC_TAFCR_TAMPIE_Pos (2U)
3789#define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
3790#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
3791#define RTC_TAFCR_TAMP1TRG_Pos (1U)
3792#define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
3793#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
3794#define RTC_TAFCR_TAMP1E_Pos (0U)
3795#define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
3796#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
3797
3798/* Reference defines */
3799#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE
3800
3801/******************** Bits definition for RTC_ALRMASSR register ************/
3802#define RTC_ALRMASSR_MASKSS_Pos (24U)
3803#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
3804#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
3805#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
3806#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
3807#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
3808#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
3809#define RTC_ALRMASSR_SS_Pos (0U)
3810#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
3811#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
3812
3813/*****************************************************************************/
3814/* */
3815/* Serial Peripheral Interface (SPI) */
3816/* */
3817/*****************************************************************************/
3818
3819/*
3820 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
3821 */
3822/* Note: No specific macro feature on this device */
3823
3824/******************* Bit definition for SPI_CR1 register *******************/
3825#define SPI_CR1_CPHA_Pos (0U)
3826#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
3827#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
3828#define SPI_CR1_CPOL_Pos (1U)
3829#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
3830#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
3831#define SPI_CR1_MSTR_Pos (2U)
3832#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
3833#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
3834#define SPI_CR1_BR_Pos (3U)
3835#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
3836#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
3837#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
3838#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
3839#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
3840#define SPI_CR1_SPE_Pos (6U)
3841#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
3842#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
3843#define SPI_CR1_LSBFIRST_Pos (7U)
3844#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
3845#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
3846#define SPI_CR1_SSI_Pos (8U)
3847#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
3848#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
3849#define SPI_CR1_SSM_Pos (9U)
3850#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
3851#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
3852#define SPI_CR1_RXONLY_Pos (10U)
3853#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
3854#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
3855#define SPI_CR1_CRCL_Pos (11U)
3856#define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
3857#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
3858#define SPI_CR1_CRCNEXT_Pos (12U)
3859#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
3860#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
3861#define SPI_CR1_CRCEN_Pos (13U)
3862#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
3863#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
3864#define SPI_CR1_BIDIOE_Pos (14U)
3865#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
3866#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
3867#define SPI_CR1_BIDIMODE_Pos (15U)
3868#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
3869#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
3870
3871/******************* Bit definition for SPI_CR2 register *******************/
3872#define SPI_CR2_RXDMAEN_Pos (0U)
3873#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
3874#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
3875#define SPI_CR2_TXDMAEN_Pos (1U)
3876#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
3877#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
3878#define SPI_CR2_SSOE_Pos (2U)
3879#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
3880#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
3881#define SPI_CR2_NSSP_Pos (3U)
3882#define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
3883#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
3884#define SPI_CR2_FRF_Pos (4U)
3885#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
3886#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
3887#define SPI_CR2_ERRIE_Pos (5U)
3888#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
3889#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
3890#define SPI_CR2_RXNEIE_Pos (6U)
3891#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
3892#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
3893#define SPI_CR2_TXEIE_Pos (7U)
3894#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
3895#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
3896#define SPI_CR2_DS_Pos (8U)
3897#define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
3898#define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
3899#define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
3900#define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
3901#define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
3902#define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
3903#define SPI_CR2_FRXTH_Pos (12U)
3904#define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
3905#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
3906#define SPI_CR2_LDMARX_Pos (13U)
3907#define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
3908#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
3909#define SPI_CR2_LDMATX_Pos (14U)
3910#define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
3911#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
3912
3913/******************** Bit definition for SPI_SR register *******************/
3914#define SPI_SR_RXNE_Pos (0U)
3915#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
3916#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
3917#define SPI_SR_TXE_Pos (1U)
3918#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
3919#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
3920#define SPI_SR_CRCERR_Pos (4U)
3921#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
3922#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
3923#define SPI_SR_MODF_Pos (5U)
3924#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
3925#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
3926#define SPI_SR_OVR_Pos (6U)
3927#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
3928#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
3929#define SPI_SR_BSY_Pos (7U)
3930#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
3931#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
3932#define SPI_SR_FRE_Pos (8U)
3933#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
3934#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
3935#define SPI_SR_FRLVL_Pos (9U)
3936#define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
3937#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
3938#define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
3939#define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
3940#define SPI_SR_FTLVL_Pos (11U)
3941#define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
3942#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
3943#define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
3944#define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
3945
3946/******************** Bit definition for SPI_DR register *******************/
3947#define SPI_DR_DR_Pos (0U)
3948#define SPI_DR_DR_Msk (0xFFFFFFFFU << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */
3949#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
3950
3951/******************* Bit definition for SPI_CRCPR register *****************/
3952#define SPI_CRCPR_CRCPOLY_Pos (0U)
3953#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
3954#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
3955
3956/****************** Bit definition for SPI_RXCRCR register *****************/
3957#define SPI_RXCRCR_RXCRC_Pos (0U)
3958#define SPI_RXCRCR_RXCRC_Msk (0xFFFFFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0xFFFFFFFF */
3959#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
3960
3961/****************** Bit definition for SPI_TXCRCR register *****************/
3962#define SPI_TXCRCR_TXCRC_Pos (0U)
3963#define SPI_TXCRCR_TXCRC_Msk (0xFFFFFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0xFFFFFFFF */
3964#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
3965
3966/****************** Bit definition for SPI_I2SCFGR register ****************/
3967#define SPI_I2SCFGR_I2SMOD_Pos (11U)
3968#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
3969#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< Keep for compatibility */
3970
3971/*****************************************************************************/
3972/* */
3973/* System Configuration (SYSCFG) */
3974/* */
3975/*****************************************************************************/
3976/***************** Bit definition for SYSCFG_CFGR1 register ****************/
3977#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
3978#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
3979#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
3980#define SYSCFG_CFGR1_MEM_MODE_0 (0x1U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
3981#define SYSCFG_CFGR1_MEM_MODE_1 (0x2U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
3982
3983#define SYSCFG_CFGR1_DMA_RMP_Pos (8U)
3984#define SYSCFG_CFGR1_DMA_RMP_Msk (0x1FU << SYSCFG_CFGR1_DMA_RMP_Pos) /*!< 0x00001F00 */
3985#define SYSCFG_CFGR1_DMA_RMP SYSCFG_CFGR1_DMA_RMP_Msk /*!< DMA remap mask */
3986#define SYSCFG_CFGR1_ADC_DMA_RMP_Pos (8U)
3987#define SYSCFG_CFGR1_ADC_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_ADC_DMA_RMP_Pos) /*!< 0x00000100 */
3988#define SYSCFG_CFGR1_ADC_DMA_RMP SYSCFG_CFGR1_ADC_DMA_RMP_Msk /*!< ADC DMA remap */
3989#define SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos (9U)
3990#define SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos) /*!< 0x00000200 */
3991#define SYSCFG_CFGR1_USART1TX_DMA_RMP SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk /*!< USART1 TX DMA remap */
3992#define SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos (10U)
3993#define SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos) /*!< 0x00000400 */
3994#define SYSCFG_CFGR1_USART1RX_DMA_RMP SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk /*!< USART1 RX DMA remap */
3995#define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos (11U)
3996#define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos) /*!< 0x00000800 */
3997#define SYSCFG_CFGR1_TIM16_DMA_RMP SYSCFG_CFGR1_TIM16_DMA_RMP_Msk /*!< Timer 16 DMA remap */
3998#define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos (12U)
3999#define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos) /*!< 0x00001000 */
4000#define SYSCFG_CFGR1_TIM17_DMA_RMP SYSCFG_CFGR1_TIM17_DMA_RMP_Msk /*!< Timer 17 DMA remap */
4001
4002#define SYSCFG_CFGR1_I2C_FMP_PB6_Pos (16U)
4003#define SYSCFG_CFGR1_I2C_FMP_PB6_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB6_Pos) /*!< 0x00010000 */
4004#define SYSCFG_CFGR1_I2C_FMP_PB6 SYSCFG_CFGR1_I2C_FMP_PB6_Msk /*!< I2C PB6 Fast mode plus */
4005#define SYSCFG_CFGR1_I2C_FMP_PB7_Pos (17U)
4006#define SYSCFG_CFGR1_I2C_FMP_PB7_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB7_Pos) /*!< 0x00020000 */
4007#define SYSCFG_CFGR1_I2C_FMP_PB7 SYSCFG_CFGR1_I2C_FMP_PB7_Msk /*!< I2C PB7 Fast mode plus */
4008#define SYSCFG_CFGR1_I2C_FMP_PB8_Pos (18U)
4009#define SYSCFG_CFGR1_I2C_FMP_PB8_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB8_Pos) /*!< 0x00040000 */
4010#define SYSCFG_CFGR1_I2C_FMP_PB8 SYSCFG_CFGR1_I2C_FMP_PB8_Msk /*!< I2C PB8 Fast mode plus */
4011#define SYSCFG_CFGR1_I2C_FMP_PB9_Pos (19U)
4012#define SYSCFG_CFGR1_I2C_FMP_PB9_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB9_Pos) /*!< 0x00080000 */
4013#define SYSCFG_CFGR1_I2C_FMP_PB9 SYSCFG_CFGR1_I2C_FMP_PB9_Msk /*!< I2C PB9 Fast mode plus */
4014
4015/***************** Bit definition for SYSCFG_EXTICR1 register **************/
4016#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
4017#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
4018#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
4019#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
4020#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
4021#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
4022#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
4023#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
4024#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
4025#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
4026#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
4027#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
4028
4029/**
4030 * @brief EXTI0 configuration
4031 */
4032#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
4033#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
4034#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
4035#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
4036#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!< PF[0] pin */
4037
4038/**
4039 * @brief EXTI1 configuration
4040 */
4041#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
4042#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
4043#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
4044#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
4045#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!< PF[1] pin */
4046
4047/**
4048 * @brief EXTI2 configuration
4049 */
4050#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
4051#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
4052#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
4053#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
4054#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!< PF[2] pin */
4055
4056/**
4057 * @brief EXTI3 configuration
4058 */
4059#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
4060#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
4061#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
4062#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
4063#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!< PF[3] pin */
4064
4065/***************** Bit definition for SYSCFG_EXTICR2 register **************/
4066#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
4067#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
4068#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
4069#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
4070#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
4071#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
4072#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
4073#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
4074#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
4075#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
4076#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
4077#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
4078
4079/**
4080 * @brief EXTI4 configuration
4081 */
4082#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
4083#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
4084#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
4085#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
4086#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!< PF[4] pin */
4087
4088/**
4089 * @brief EXTI5 configuration
4090 */
4091#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
4092#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
4093#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
4094#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
4095#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!< PF[5] pin */
4096
4097/**
4098 * @brief EXTI6 configuration
4099 */
4100#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
4101#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
4102#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
4103#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
4104#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!< PF[6] pin */
4105
4106/**
4107 * @brief EXTI7 configuration
4108 */
4109#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
4110#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
4111#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
4112#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
4113#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!< PF[7] pin */
4114
4115/***************** Bit definition for SYSCFG_EXTICR3 register **************/
4116#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
4117#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
4118#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
4119#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
4120#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
4121#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
4122#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
4123#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
4124#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
4125#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
4126#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
4127#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
4128
4129/**
4130 * @brief EXTI8 configuration
4131 */
4132#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
4133#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
4134#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
4135#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
4136#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!< PF[8] pin */
4137
4138
4139/**
4140 * @brief EXTI9 configuration
4141 */
4142#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
4143#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
4144#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
4145#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
4146#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!< PF[9] pin */
4147
4148/**
4149 * @brief EXTI10 configuration
4150 */
4151#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
4152#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
4153#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
4154#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
4155#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!< PF[10] pin */
4156
4157/**
4158 * @brief EXTI11 configuration
4159 */
4160#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
4161#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
4162#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
4163#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
4164#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!< PF[11] pin */
4165
4166/***************** Bit definition for SYSCFG_EXTICR4 register **************/
4167#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
4168#define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
4169#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
4170#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
4171#define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
4172#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
4173#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
4174#define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
4175#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
4176#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
4177#define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
4178#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
4179
4180/**
4181 * @brief EXTI12 configuration
4182 */
4183#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
4184#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
4185#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
4186#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
4187#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!< PF[12] pin */
4188
4189/**
4190 * @brief EXTI13 configuration
4191 */
4192#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
4193#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
4194#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
4195#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
4196#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!< PF[13] pin */
4197
4198/**
4199 * @brief EXTI14 configuration
4200 */
4201#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
4202#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
4203#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
4204#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
4205#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!< PF[14] pin */
4206
4207/**
4208 * @brief EXTI15 configuration
4209 */
4210#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
4211#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
4212#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
4213#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
4214#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!< PF[15] pin */
4215
4216/***************** Bit definition for SYSCFG_CFGR2 register ****************/
4217#define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)
4218#define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1U << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
4219#define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
4220#define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos (1U)
4221#define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk (0x1U << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos) /*!< 0x00000002 */
4222#define SYSCFG_CFGR2_SRAM_PARITY_LOCK SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
4223#define SYSCFG_CFGR2_SRAM_PEF_Pos (8U)
4224#define SYSCFG_CFGR2_SRAM_PEF_Msk (0x1U << SYSCFG_CFGR2_SRAM_PEF_Pos) /*!< 0x00000100 */
4225#define SYSCFG_CFGR2_SRAM_PEF SYSCFG_CFGR2_SRAM_PEF_Msk /*!< SRAM Parity error flag */
4226#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
4227
4228/*****************************************************************************/
4229/* */
4230/* Timers (TIM) */
4231/* */
4232/*****************************************************************************/
4233/******************* Bit definition for TIM_CR1 register *******************/
4234#define TIM_CR1_CEN_Pos (0U)
4235#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
4236#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
4237#define TIM_CR1_UDIS_Pos (1U)
4238#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
4239#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
4240#define TIM_CR1_URS_Pos (2U)
4241#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
4242#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
4243#define TIM_CR1_OPM_Pos (3U)
4244#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
4245#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
4246#define TIM_CR1_DIR_Pos (4U)
4247#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
4248#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
4249
4250#define TIM_CR1_CMS_Pos (5U)
4251#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
4252#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
4253#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
4254#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
4255
4256#define TIM_CR1_ARPE_Pos (7U)
4257#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
4258#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
4259
4260#define TIM_CR1_CKD_Pos (8U)
4261#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
4262#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
4263#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
4264#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
4265
4266/******************* Bit definition for TIM_CR2 register *******************/
4267#define TIM_CR2_CCPC_Pos (0U)
4268#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
4269#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
4270#define TIM_CR2_CCUS_Pos (2U)
4271#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
4272#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
4273#define TIM_CR2_CCDS_Pos (3U)
4274#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
4275#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
4276
4277#define TIM_CR2_MMS_Pos (4U)
4278#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
4279#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
4280#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
4281#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
4282#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
4283
4284#define TIM_CR2_TI1S_Pos (7U)
4285#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
4286#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
4287#define TIM_CR2_OIS1_Pos (8U)
4288#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
4289#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
4290#define TIM_CR2_OIS1N_Pos (9U)
4291#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
4292#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
4293#define TIM_CR2_OIS2_Pos (10U)
4294#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
4295#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
4296#define TIM_CR2_OIS2N_Pos (11U)
4297#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
4298#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
4299#define TIM_CR2_OIS3_Pos (12U)
4300#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
4301#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
4302#define TIM_CR2_OIS3N_Pos (13U)
4303#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
4304#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
4305#define TIM_CR2_OIS4_Pos (14U)
4306#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
4307#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
4308
4309/******************* Bit definition for TIM_SMCR register ******************/
4310#define TIM_SMCR_SMS_Pos (0U)
4311#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
4312#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
4313#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
4314#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
4315#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
4316
4317#define TIM_SMCR_OCCS_Pos (3U)
4318#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
4319#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
4320
4321#define TIM_SMCR_TS_Pos (4U)
4322#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
4323#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
4324#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
4325#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
4326#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
4327
4328#define TIM_SMCR_MSM_Pos (7U)
4329#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
4330#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
4331
4332#define TIM_SMCR_ETF_Pos (8U)
4333#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
4334#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
4335#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
4336#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
4337#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
4338#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
4339
4340#define TIM_SMCR_ETPS_Pos (12U)
4341#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
4342#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
4343#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
4344#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
4345
4346#define TIM_SMCR_ECE_Pos (14U)
4347#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
4348#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
4349#define TIM_SMCR_ETP_Pos (15U)
4350#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
4351#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
4352
4353/******************* Bit definition for TIM_DIER register ******************/
4354#define TIM_DIER_UIE_Pos (0U)
4355#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
4356#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
4357#define TIM_DIER_CC1IE_Pos (1U)
4358#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
4359#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
4360#define TIM_DIER_CC2IE_Pos (2U)
4361#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
4362#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
4363#define TIM_DIER_CC3IE_Pos (3U)
4364#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
4365#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
4366#define TIM_DIER_CC4IE_Pos (4U)
4367#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
4368#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
4369#define TIM_DIER_COMIE_Pos (5U)
4370#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
4371#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
4372#define TIM_DIER_TIE_Pos (6U)
4373#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
4374#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
4375#define TIM_DIER_BIE_Pos (7U)
4376#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
4377#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
4378#define TIM_DIER_UDE_Pos (8U)
4379#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
4380#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
4381#define TIM_DIER_CC1DE_Pos (9U)
4382#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
4383#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
4384#define TIM_DIER_CC2DE_Pos (10U)
4385#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
4386#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
4387#define TIM_DIER_CC3DE_Pos (11U)
4388#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
4389#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
4390#define TIM_DIER_CC4DE_Pos (12U)
4391#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
4392#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
4393#define TIM_DIER_COMDE_Pos (13U)
4394#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
4395#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
4396#define TIM_DIER_TDE_Pos (14U)
4397#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
4398#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
4399
4400/******************** Bit definition for TIM_SR register *******************/
4401#define TIM_SR_UIF_Pos (0U)
4402#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
4403#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
4404#define TIM_SR_CC1IF_Pos (1U)
4405#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
4406#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
4407#define TIM_SR_CC2IF_Pos (2U)
4408#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
4409#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
4410#define TIM_SR_CC3IF_Pos (3U)
4411#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
4412#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
4413#define TIM_SR_CC4IF_Pos (4U)
4414#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
4415#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
4416#define TIM_SR_COMIF_Pos (5U)
4417#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
4418#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
4419#define TIM_SR_TIF_Pos (6U)
4420#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
4421#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
4422#define TIM_SR_BIF_Pos (7U)
4423#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
4424#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
4425#define TIM_SR_CC1OF_Pos (9U)
4426#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
4427#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
4428#define TIM_SR_CC2OF_Pos (10U)
4429#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
4430#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
4431#define TIM_SR_CC3OF_Pos (11U)
4432#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
4433#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
4434#define TIM_SR_CC4OF_Pos (12U)
4435#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
4436#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
4437
4438/******************* Bit definition for TIM_EGR register *******************/
4439#define TIM_EGR_UG_Pos (0U)
4440#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
4441#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
4442#define TIM_EGR_CC1G_Pos (1U)
4443#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
4444#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
4445#define TIM_EGR_CC2G_Pos (2U)
4446#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
4447#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
4448#define TIM_EGR_CC3G_Pos (3U)
4449#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
4450#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
4451#define TIM_EGR_CC4G_Pos (4U)
4452#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
4453#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
4454#define TIM_EGR_COMG_Pos (5U)
4455#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
4456#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
4457#define TIM_EGR_TG_Pos (6U)
4458#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
4459#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
4460#define TIM_EGR_BG_Pos (7U)
4461#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
4462#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
4463
4464/****************** Bit definition for TIM_CCMR1 register ******************/
4465#define TIM_CCMR1_CC1S_Pos (0U)
4466#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
4467#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
4468#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
4469#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
4470
4471#define TIM_CCMR1_OC1FE_Pos (2U)
4472#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
4473#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
4474#define TIM_CCMR1_OC1PE_Pos (3U)
4475#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
4476#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
4477
4478#define TIM_CCMR1_OC1M_Pos (4U)
4479#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
4480#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
4481#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
4482#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
4483#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
4484
4485#define TIM_CCMR1_OC1CE_Pos (7U)
4486#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
4487#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
4488
4489#define TIM_CCMR1_CC2S_Pos (8U)
4490#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
4491#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
4492#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
4493#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
4494
4495#define TIM_CCMR1_OC2FE_Pos (10U)
4496#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
4497#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
4498#define TIM_CCMR1_OC2PE_Pos (11U)
4499#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
4500#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
4501
4502#define TIM_CCMR1_OC2M_Pos (12U)
4503#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
4504#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
4505#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
4506#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
4507#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
4508
4509#define TIM_CCMR1_OC2CE_Pos (15U)
4510#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
4511#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
4512
4513/*---------------------------------------------------------------------------*/
4514
4515#define TIM_CCMR1_IC1PSC_Pos (2U)
4516#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
4517#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
4518#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
4519#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
4520
4521#define TIM_CCMR1_IC1F_Pos (4U)
4522#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
4523#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
4524#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
4525#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
4526#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
4527#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
4528
4529#define TIM_CCMR1_IC2PSC_Pos (10U)
4530#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
4531#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
4532#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
4533#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
4534
4535#define TIM_CCMR1_IC2F_Pos (12U)
4536#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
4537#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
4538#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
4539#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
4540#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
4541#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
4542
4543/****************** Bit definition for TIM_CCMR2 register ******************/
4544#define TIM_CCMR2_CC3S_Pos (0U)
4545#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
4546#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
4547#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
4548#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
4549
4550#define TIM_CCMR2_OC3FE_Pos (2U)
4551#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
4552#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
4553#define TIM_CCMR2_OC3PE_Pos (3U)
4554#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
4555#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
4556
4557#define TIM_CCMR2_OC3M_Pos (4U)
4558#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
4559#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
4560#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
4561#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
4562#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
4563
4564#define TIM_CCMR2_OC3CE_Pos (7U)
4565#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
4566#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
4567
4568#define TIM_CCMR2_CC4S_Pos (8U)
4569#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
4570#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
4571#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
4572#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
4573
4574#define TIM_CCMR2_OC4FE_Pos (10U)
4575#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
4576#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
4577#define TIM_CCMR2_OC4PE_Pos (11U)
4578#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
4579#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
4580
4581#define TIM_CCMR2_OC4M_Pos (12U)
4582#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
4583#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
4584#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
4585#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
4586#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
4587
4588#define TIM_CCMR2_OC4CE_Pos (15U)
4589#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
4590#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
4591
4592/*---------------------------------------------------------------------------*/
4593
4594#define TIM_CCMR2_IC3PSC_Pos (2U)
4595#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
4596#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
4597#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
4598#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
4599
4600#define TIM_CCMR2_IC3F_Pos (4U)
4601#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
4602#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
4603#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
4604#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
4605#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
4606#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
4607
4608#define TIM_CCMR2_IC4PSC_Pos (10U)
4609#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
4610#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
4611#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
4612#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
4613
4614#define TIM_CCMR2_IC4F_Pos (12U)
4615#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
4616#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
4617#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
4618#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
4619#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
4620#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
4621
4622/******************* Bit definition for TIM_CCER register ******************/
4623#define TIM_CCER_CC1E_Pos (0U)
4624#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
4625#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
4626#define TIM_CCER_CC1P_Pos (1U)
4627#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
4628#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
4629#define TIM_CCER_CC1NE_Pos (2U)
4630#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
4631#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
4632#define TIM_CCER_CC1NP_Pos (3U)
4633#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
4634#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
4635#define TIM_CCER_CC2E_Pos (4U)
4636#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
4637#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
4638#define TIM_CCER_CC2P_Pos (5U)
4639#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
4640#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
4641#define TIM_CCER_CC2NE_Pos (6U)
4642#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
4643#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
4644#define TIM_CCER_CC2NP_Pos (7U)
4645#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
4646#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
4647#define TIM_CCER_CC3E_Pos (8U)
4648#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
4649#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
4650#define TIM_CCER_CC3P_Pos (9U)
4651#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
4652#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
4653#define TIM_CCER_CC3NE_Pos (10U)
4654#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
4655#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
4656#define TIM_CCER_CC3NP_Pos (11U)
4657#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
4658#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
4659#define TIM_CCER_CC4E_Pos (12U)
4660#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
4661#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
4662#define TIM_CCER_CC4P_Pos (13U)
4663#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
4664#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
4665#define TIM_CCER_CC4NP_Pos (15U)
4666#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
4667#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
4668
4669/******************* Bit definition for TIM_CNT register *******************/
4670#define TIM_CNT_CNT_Pos (0U)
4671#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
4672#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
4673
4674/******************* Bit definition for TIM_PSC register *******************/
4675#define TIM_PSC_PSC_Pos (0U)
4676#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
4677#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
4678
4679/******************* Bit definition for TIM_ARR register *******************/
4680#define TIM_ARR_ARR_Pos (0U)
4681#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
4682#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
4683
4684/******************* Bit definition for TIM_RCR register *******************/
4685#define TIM_RCR_REP_Pos (0U)
4686#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
4687#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
4688
4689/******************* Bit definition for TIM_CCR1 register ******************/
4690#define TIM_CCR1_CCR1_Pos (0U)
4691#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
4692#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
4693
4694/******************* Bit definition for TIM_CCR2 register ******************/
4695#define TIM_CCR2_CCR2_Pos (0U)
4696#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
4697#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
4698
4699/******************* Bit definition for TIM_CCR3 register ******************/
4700#define TIM_CCR3_CCR3_Pos (0U)
4701#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
4702#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
4703
4704/******************* Bit definition for TIM_CCR4 register ******************/
4705#define TIM_CCR4_CCR4_Pos (0U)
4706#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
4707#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
4708
4709/******************* Bit definition for TIM_BDTR register ******************/
4710#define TIM_BDTR_DTG_Pos (0U)
4711#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
4712#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
4713#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
4714#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
4715#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
4716#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
4717#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
4718#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
4719#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
4720#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
4721
4722#define TIM_BDTR_LOCK_Pos (8U)
4723#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
4724#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
4725#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
4726#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
4727
4728#define TIM_BDTR_OSSI_Pos (10U)
4729#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
4730#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
4731#define TIM_BDTR_OSSR_Pos (11U)
4732#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
4733#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
4734#define TIM_BDTR_BKE_Pos (12U)
4735#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
4736#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
4737#define TIM_BDTR_BKP_Pos (13U)
4738#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
4739#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
4740#define TIM_BDTR_AOE_Pos (14U)
4741#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
4742#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
4743#define TIM_BDTR_MOE_Pos (15U)
4744#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
4745#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
4746
4747/******************* Bit definition for TIM_DCR register *******************/
4748#define TIM_DCR_DBA_Pos (0U)
4749#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
4750#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
4751#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
4752#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
4753#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
4754#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
4755#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
4756
4757#define TIM_DCR_DBL_Pos (8U)
4758#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
4759#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
4760#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
4761#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
4762#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
4763#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
4764#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
4765
4766/******************* Bit definition for TIM_DMAR register ******************/
4767#define TIM_DMAR_DMAB_Pos (0U)
4768#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
4769#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
4770
4771/******************* Bit definition for TIM14_OR register ********************/
4772#define TIM14_OR_TI1_RMP_Pos (0U)
4773#define TIM14_OR_TI1_RMP_Msk (0x3U << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000003 */
4774#define TIM14_OR_TI1_RMP TIM14_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
4775#define TIM14_OR_TI1_RMP_0 (0x1U << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000001 */
4776#define TIM14_OR_TI1_RMP_1 (0x2U << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000002 */
4777
4778/******************************************************************************/
4779/* */
4780/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
4781/* */
4782/******************************************************************************/
4783/****************** Bit definition for USART_CR1 register *******************/
4784#define USART_CR1_UE_Pos (0U)
4785#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
4786#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
4787#define USART_CR1_RE_Pos (2U)
4788#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
4789#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
4790#define USART_CR1_TE_Pos (3U)
4791#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
4792#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
4793#define USART_CR1_IDLEIE_Pos (4U)
4794#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
4795#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
4796#define USART_CR1_RXNEIE_Pos (5U)
4797#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
4798#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
4799#define USART_CR1_TCIE_Pos (6U)
4800#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
4801#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
4802#define USART_CR1_TXEIE_Pos (7U)
4803#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
4804#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
4805#define USART_CR1_PEIE_Pos (8U)
4806#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
4807#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
4808#define USART_CR1_PS_Pos (9U)
4809#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
4810#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
4811#define USART_CR1_PCE_Pos (10U)
4812#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
4813#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
4814#define USART_CR1_WAKE_Pos (11U)
4815#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
4816#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
4817#define USART_CR1_M_Pos (12U)
4818#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
4819#define USART_CR1_M USART_CR1_M_Msk /*!< Word Length */
4820#define USART_CR1_MME_Pos (13U)
4821#define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
4822#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
4823#define USART_CR1_CMIE_Pos (14U)
4824#define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
4825#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
4826#define USART_CR1_OVER8_Pos (15U)
4827#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
4828#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
4829#define USART_CR1_DEDT_Pos (16U)
4830#define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
4831#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
4832#define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
4833#define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
4834#define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
4835#define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
4836#define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
4837#define USART_CR1_DEAT_Pos (21U)
4838#define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
4839#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
4840#define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
4841#define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
4842#define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
4843#define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
4844#define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
4845#define USART_CR1_RTOIE_Pos (26U)
4846#define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
4847#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
4848#define USART_CR1_EOBIE_Pos (27U)
4849#define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
4850#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
4851
4852/****************** Bit definition for USART_CR2 register *******************/
4853#define USART_CR2_ADDM7_Pos (4U)
4854#define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
4855#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
4856#define USART_CR2_LBCL_Pos (8U)
4857#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
4858#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
4859#define USART_CR2_CPHA_Pos (9U)
4860#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
4861#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
4862#define USART_CR2_CPOL_Pos (10U)
4863#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
4864#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
4865#define USART_CR2_CLKEN_Pos (11U)
4866#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
4867#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
4868#define USART_CR2_STOP_Pos (12U)
4869#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
4870#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
4871#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
4872#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
4873#define USART_CR2_SWAP_Pos (15U)
4874#define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
4875#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
4876#define USART_CR2_RXINV_Pos (16U)
4877#define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
4878#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
4879#define USART_CR2_TXINV_Pos (17U)
4880#define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
4881#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
4882#define USART_CR2_DATAINV_Pos (18U)
4883#define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
4884#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
4885#define USART_CR2_MSBFIRST_Pos (19U)
4886#define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
4887#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
4888#define USART_CR2_ABREN_Pos (20U)
4889#define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
4890#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
4891#define USART_CR2_ABRMODE_Pos (21U)
4892#define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
4893#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
4894#define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
4895#define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
4896#define USART_CR2_RTOEN_Pos (23U)
4897#define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
4898#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
4899#define USART_CR2_ADD_Pos (24U)
4900#define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
4901#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
4902
4903/****************** Bit definition for USART_CR3 register *******************/
4904#define USART_CR3_EIE_Pos (0U)
4905#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
4906#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
4907#define USART_CR3_HDSEL_Pos (3U)
4908#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
4909#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
4910#define USART_CR3_DMAR_Pos (6U)
4911#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
4912#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
4913#define USART_CR3_DMAT_Pos (7U)
4914#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
4915#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
4916#define USART_CR3_RTSE_Pos (8U)
4917#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
4918#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
4919#define USART_CR3_CTSE_Pos (9U)
4920#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
4921#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
4922#define USART_CR3_CTSIE_Pos (10U)
4923#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
4924#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
4925#define USART_CR3_ONEBIT_Pos (11U)
4926#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
4927#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
4928#define USART_CR3_OVRDIS_Pos (12U)
4929#define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
4930#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
4931#define USART_CR3_DDRE_Pos (13U)
4932#define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
4933#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
4934#define USART_CR3_DEM_Pos (14U)
4935#define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
4936#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
4937#define USART_CR3_DEP_Pos (15U)
4938#define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
4939#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
4940
4941/****************** Bit definition for USART_BRR register *******************/
4942#define USART_BRR_DIV_FRACTION_Pos (0U)
4943#define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
4944#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
4945#define USART_BRR_DIV_MANTISSA_Pos (4U)
4946#define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
4947#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
4948
4949/****************** Bit definition for USART_GTPR register ******************/
4950#define USART_GTPR_PSC_Pos (0U)
4951#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
4952#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
4953#define USART_GTPR_GT_Pos (8U)
4954#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
4955#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
4956
4957
4958/******************* Bit definition for USART_RTOR register *****************/
4959#define USART_RTOR_RTO_Pos (0U)
4960#define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
4961#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
4962#define USART_RTOR_BLEN_Pos (24U)
4963#define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
4964#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
4965
4966/******************* Bit definition for USART_RQR register ******************/
4967#define USART_RQR_ABRRQ_Pos (0U)
4968#define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
4969#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
4970#define USART_RQR_SBKRQ_Pos (1U)
4971#define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
4972#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
4973#define USART_RQR_MMRQ_Pos (2U)
4974#define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
4975#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
4976#define USART_RQR_RXFRQ_Pos (3U)
4977#define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
4978#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
4979
4980/******************* Bit definition for USART_ISR register ******************/
4981#define USART_ISR_PE_Pos (0U)
4982#define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
4983#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
4984#define USART_ISR_FE_Pos (1U)
4985#define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
4986#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
4987#define USART_ISR_NE_Pos (2U)
4988#define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
4989#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
4990#define USART_ISR_ORE_Pos (3U)
4991#define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
4992#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
4993#define USART_ISR_IDLE_Pos (4U)
4994#define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
4995#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
4996#define USART_ISR_RXNE_Pos (5U)
4997#define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
4998#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
4999#define USART_ISR_TC_Pos (6U)
5000#define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
5001#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
5002#define USART_ISR_TXE_Pos (7U)
5003#define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
5004#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
5005#define USART_ISR_CTSIF_Pos (9U)
5006#define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
5007#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
5008#define USART_ISR_CTS_Pos (10U)
5009#define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
5010#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
5011#define USART_ISR_RTOF_Pos (11U)
5012#define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
5013#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
5014#define USART_ISR_ABRE_Pos (14U)
5015#define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
5016#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
5017#define USART_ISR_ABRF_Pos (15U)
5018#define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
5019#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
5020#define USART_ISR_BUSY_Pos (16U)
5021#define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
5022#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
5023#define USART_ISR_CMF_Pos (17U)
5024#define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
5025#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
5026#define USART_ISR_SBKF_Pos (18U)
5027#define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
5028#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
5029#define USART_ISR_RWU_Pos (19U)
5030#define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
5031#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
5032#define USART_ISR_TEACK_Pos (21U)
5033#define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
5034#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
5035#define USART_ISR_REACK_Pos (22U)
5036#define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
5037#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
5038
5039/******************* Bit definition for USART_ICR register ******************/
5040#define USART_ICR_PECF_Pos (0U)
5041#define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
5042#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
5043#define USART_ICR_FECF_Pos (1U)
5044#define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
5045#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
5046#define USART_ICR_NCF_Pos (2U)
5047#define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
5048#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
5049#define USART_ICR_ORECF_Pos (3U)
5050#define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
5051#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
5052#define USART_ICR_IDLECF_Pos (4U)
5053#define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
5054#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
5055#define USART_ICR_TCCF_Pos (6U)
5056#define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
5057#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
5058#define USART_ICR_CTSCF_Pos (9U)
5059#define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
5060#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
5061#define USART_ICR_RTOCF_Pos (11U)
5062#define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
5063#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
5064#define USART_ICR_CMCF_Pos (17U)
5065#define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
5066#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
5067
5068/******************* Bit definition for USART_RDR register ******************/
5069#define USART_RDR_RDR ((uint16_t)0x01FFU) /*!< RDR[8:0] bits (Receive Data value) */
5070
5071/******************* Bit definition for USART_TDR register ******************/
5072#define USART_TDR_TDR ((uint16_t)0x01FFU) /*!< TDR[8:0] bits (Transmit Data value) */
5073
5074/******************************************************************************/
5075/* */
5076/* Window WATCHDOG (WWDG) */
5077/* */
5078/******************************************************************************/
5079
5080/******************* Bit definition for WWDG_CR register ********************/
5081#define WWDG_CR_T_Pos (0U)
5082#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
5083#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
5084#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
5085#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
5086#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
5087#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
5088#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
5089#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
5090#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
5091
5092/* Legacy defines */
5093#define WWDG_CR_T0 WWDG_CR_T_0
5094#define WWDG_CR_T1 WWDG_CR_T_1
5095#define WWDG_CR_T2 WWDG_CR_T_2
5096#define WWDG_CR_T3 WWDG_CR_T_3
5097#define WWDG_CR_T4 WWDG_CR_T_4
5098#define WWDG_CR_T5 WWDG_CR_T_5
5099#define WWDG_CR_T6 WWDG_CR_T_6
5100
5101#define WWDG_CR_WDGA_Pos (7U)
5102#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
5103#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
5104
5105/******************* Bit definition for WWDG_CFR register *******************/
5106#define WWDG_CFR_W_Pos (0U)
5107#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
5108#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
5109#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
5110#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
5111#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
5112#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
5113#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
5114#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
5115#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
5116
5117/* Legacy defines */
5118#define WWDG_CFR_W0 WWDG_CFR_W_0
5119#define WWDG_CFR_W1 WWDG_CFR_W_1
5120#define WWDG_CFR_W2 WWDG_CFR_W_2
5121#define WWDG_CFR_W3 WWDG_CFR_W_3
5122#define WWDG_CFR_W4 WWDG_CFR_W_4
5123#define WWDG_CFR_W5 WWDG_CFR_W_5
5124#define WWDG_CFR_W6 WWDG_CFR_W_6
5125
5126#define WWDG_CFR_WDGTB_Pos (7U)
5127#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
5128#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
5129#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
5130#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
5131
5132/* Legacy defines */
5133#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
5134#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
5135
5136#define WWDG_CFR_EWI_Pos (9U)
5137#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
5138#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
5139
5140/******************* Bit definition for WWDG_SR register ********************/
5141#define WWDG_SR_EWIF_Pos (0U)
5142#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
5143#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
5144
5145/**
5146 * @}
5147 */
5148
5149 /**
5150 * @}
5151 */
5152
5153
5154/** @addtogroup Exported_macro
5155 * @{
5156 */
5157
5158/****************************** ADC Instances *********************************/
5159#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
5160
5161#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
5162
5163/****************************** CRC Instances *********************************/
5164#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
5165
5166/******************************* DMA Instances ********************************/
5167#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
5168 ((INSTANCE) == DMA1_Channel2) || \
5169 ((INSTANCE) == DMA1_Channel3) || \
5170 ((INSTANCE) == DMA1_Channel4) || \
5171 ((INSTANCE) == DMA1_Channel5))
5172
5173/****************************** GPIO Instances ********************************/
5174#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
5175 ((INSTANCE) == GPIOB) || \
5176 ((INSTANCE) == GPIOC) || \
5177 ((INSTANCE) == GPIOD) || \
5178 ((INSTANCE) == GPIOF))
5179
5180/**************************** GPIO Alternate Function Instances ***************/
5181#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
5182 ((INSTANCE) == GPIOB))
5183
5184/****************************** GPIO Lock Instances ***************************/
5185#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
5186 ((INSTANCE) == GPIOB))
5187
5188/****************************** I2C Instances *********************************/
5189#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
5190 ((INSTANCE) == I2C2))
5191
5192
5193/****************************** IWDG Instances ********************************/
5194#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
5195
5196/****************************** RTC Instances *********************************/
5197#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
5198
5199/****************************** SMBUS Instances *********************************/
5200#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
5201
5202/****************************** SPI Instances *********************************/
5203#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
5204 ((INSTANCE) == SPI2))
5205
5206/****************************** TIM Instances *********************************/
5207#define IS_TIM_INSTANCE(INSTANCE)\
5208 (((INSTANCE) == TIM1) || \
5209 ((INSTANCE) == TIM3) || \
5210 ((INSTANCE) == TIM6) || \
5211 ((INSTANCE) == TIM14) || \
5212 ((INSTANCE) == TIM15) || \
5213 ((INSTANCE) == TIM16) || \
5214 ((INSTANCE) == TIM17))
5215
5216#define IS_TIM_CC1_INSTANCE(INSTANCE)\
5217 (((INSTANCE) == TIM1) || \
5218 ((INSTANCE) == TIM3) || \
5219 ((INSTANCE) == TIM14) || \
5220 ((INSTANCE) == TIM15) || \
5221 ((INSTANCE) == TIM16) || \
5222 ((INSTANCE) == TIM17))
5223
5224#define IS_TIM_CC2_INSTANCE(INSTANCE)\
5225 (((INSTANCE) == TIM1) || \
5226 ((INSTANCE) == TIM3) || \
5227 ((INSTANCE) == TIM15))
5228
5229#define IS_TIM_CC3_INSTANCE(INSTANCE)\
5230 (((INSTANCE) == TIM1) || \
5231 ((INSTANCE) == TIM3))
5232
5233#define IS_TIM_CC4_INSTANCE(INSTANCE)\
5234 (((INSTANCE) == TIM1) || \
5235 ((INSTANCE) == TIM3))
5236
5237#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
5238 (((INSTANCE) == TIM1) || \
5239 ((INSTANCE) == TIM3))
5240
5241#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
5242 (((INSTANCE) == TIM1) || \
5243 ((INSTANCE) == TIM3))
5244
5245#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
5246 (((INSTANCE) == TIM1) || \
5247 ((INSTANCE) == TIM3) || \
5248 ((INSTANCE) == TIM15))
5249
5250#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
5251 (((INSTANCE) == TIM1) || \
5252 ((INSTANCE) == TIM3) || \
5253 ((INSTANCE) == TIM15))
5254
5255#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
5256 (((INSTANCE) == TIM1) || \
5257 ((INSTANCE) == TIM3))
5258
5259#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
5260 (((INSTANCE) == TIM1) || \
5261 ((INSTANCE) == TIM3))
5262
5263#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
5264 (((INSTANCE) == TIM1))
5265
5266#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\
5267 (((INSTANCE) == TIM1))
5268
5269#define IS_TIM_XOR_INSTANCE(INSTANCE)\
5270 (((INSTANCE) == TIM1) || \
5271 ((INSTANCE) == TIM3))
5272
5273#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
5274 (((INSTANCE) == TIM1) || \
5275 ((INSTANCE) == TIM3) || \
5276 ((INSTANCE) == TIM15))
5277
5278#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
5279 (((INSTANCE) == TIM1) || \
5280 ((INSTANCE) == TIM3) || \
5281 ((INSTANCE) == TIM15))
5282
5283#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0)
5284
5285#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
5286 (((INSTANCE) == TIM1) || \
5287 ((INSTANCE) == TIM3) || \
5288 ((INSTANCE) == TIM15) || \
5289 ((INSTANCE) == TIM16) || \
5290 ((INSTANCE) == TIM17))
5291
5292#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
5293 (((INSTANCE) == TIM1) || \
5294 ((INSTANCE) == TIM15) || \
5295 ((INSTANCE) == TIM16) || \
5296 ((INSTANCE) == TIM17))
5297
5298#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
5299 ((((INSTANCE) == TIM1) && \
5300 (((CHANNEL) == TIM_CHANNEL_1) || \
5301 ((CHANNEL) == TIM_CHANNEL_2) || \
5302 ((CHANNEL) == TIM_CHANNEL_3) || \
5303 ((CHANNEL) == TIM_CHANNEL_4))) \
5304 || \
5305 (((INSTANCE) == TIM3) && \
5306 (((CHANNEL) == TIM_CHANNEL_1) || \
5307 ((CHANNEL) == TIM_CHANNEL_2) || \
5308 ((CHANNEL) == TIM_CHANNEL_3) || \
5309 ((CHANNEL) == TIM_CHANNEL_4))) \
5310 || \
5311 (((INSTANCE) == TIM14) && \
5312 (((CHANNEL) == TIM_CHANNEL_1))) \
5313 || \
5314 (((INSTANCE) == TIM15) && \
5315 (((CHANNEL) == TIM_CHANNEL_1) || \
5316 ((CHANNEL) == TIM_CHANNEL_2))) \
5317 || \
5318 (((INSTANCE) == TIM16) && \
5319 (((CHANNEL) == TIM_CHANNEL_1))) \
5320 || \
5321 (((INSTANCE) == TIM17) && \
5322 (((CHANNEL) == TIM_CHANNEL_1))))
5323
5324#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
5325 ((((INSTANCE) == TIM1) && \
5326 (((CHANNEL) == TIM_CHANNEL_1) || \
5327 ((CHANNEL) == TIM_CHANNEL_2) || \
5328 ((CHANNEL) == TIM_CHANNEL_3))) \
5329 || \
5330 (((INSTANCE) == TIM15) && \
5331 ((CHANNEL) == TIM_CHANNEL_1)) \
5332 || \
5333 (((INSTANCE) == TIM16) && \
5334 ((CHANNEL) == TIM_CHANNEL_1)) \
5335 || \
5336 (((INSTANCE) == TIM17) && \
5337 ((CHANNEL) == TIM_CHANNEL_1)))
5338
5339#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
5340 (((INSTANCE) == TIM1) || \
5341 ((INSTANCE) == TIM3))
5342
5343#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
5344 (((INSTANCE) == TIM1) || \
5345 ((INSTANCE) == TIM15) || \
5346 ((INSTANCE) == TIM16) || \
5347 ((INSTANCE) == TIM17))
5348
5349#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
5350 (((INSTANCE) == TIM1) || \
5351 ((INSTANCE) == TIM3) || \
5352 ((INSTANCE) == TIM14) || \
5353 ((INSTANCE) == TIM15) || \
5354 ((INSTANCE) == TIM16) || \
5355 ((INSTANCE) == TIM17))
5356
5357#define IS_TIM_DMA_INSTANCE(INSTANCE)\
5358 (((INSTANCE) == TIM1) || \
5359 ((INSTANCE) == TIM3) || \
5360 ((INSTANCE) == TIM6) || \
5361 ((INSTANCE) == TIM15) || \
5362 ((INSTANCE) == TIM16) || \
5363 ((INSTANCE) == TIM17))
5364
5365#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
5366 (((INSTANCE) == TIM1) || \
5367 ((INSTANCE) == TIM3) || \
5368 ((INSTANCE) == TIM15) || \
5369 ((INSTANCE) == TIM16) || \
5370 ((INSTANCE) == TIM17))
5371
5372#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
5373 (((INSTANCE) == TIM1) || \
5374 ((INSTANCE) == TIM15) || \
5375 ((INSTANCE) == TIM16) || \
5376 ((INSTANCE) == TIM17))
5377
5378#define IS_TIM_REMAP_INSTANCE(INSTANCE)\
5379 ((INSTANCE) == TIM14)
5380
5381#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
5382 ((INSTANCE) == TIM1)
5383
5384/******************** USART Instances : Synchronous mode **********************/
5385#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5386 ((INSTANCE) == USART2))
5387
5388/******************** USART Instances : auto Baud rate detection **************/
5389#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
5390
5391/******************** UART Instances : Asynchronous mode **********************/
5392#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5393 ((INSTANCE) == USART2))
5394
5395/******************** UART Instances : Half-Duplex mode **********************/
5396#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5397 ((INSTANCE) == USART2))
5398
5399/****************** UART Instances : Hardware Flow control ********************/
5400#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5401 ((INSTANCE) == USART2))
5402
5403/****************** UART Instances : Driver enable detection ********************/
5404#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5405 ((INSTANCE) == USART2))
5406
5407/****************************** WWDG Instances ********************************/
5408#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
5409
5410/**
5411 * @}
5412 */
5413
5414
5415/******************************************************************************/
5416/* For a painless codes migration between the STM32F0xx device product */
5417/* lines, the aliases defined below are put in place to overcome the */
5418/* differences in the interrupt handlers and IRQn definitions. */
5419/* No need to update developed interrupt code when moving across */
5420/* product lines within the same STM32F0 Family */
5421/******************************************************************************/
5422
5423/* Aliases for __IRQn */
5424#define ADC1_COMP_IRQn ADC1_IRQn
5425#define DMA1_Ch1_IRQn DMA1_Channel1_IRQn
5426#define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn
5427#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
5428#define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
5429#define RCC_CRS_IRQn RCC_IRQn
5430#define TIM6_DAC_IRQn TIM6_IRQn
5431
5432
5433/* Aliases for __IRQHandler */
5434#define ADC1_COMP_IRQHandler ADC1_IRQHandler
5435#define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler
5436#define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler
5437#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
5438#define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler
5439#define RCC_CRS_IRQHandler RCC_IRQHandler
5440#define TIM6_DAC_IRQHandler TIM6_IRQHandler
5441
5442
5443#ifdef __cplusplus
5444}
5445#endif /* __cplusplus */
5446
5447#endif /* __STM32F030x8_H */
5448
5449/**
5450 * @}
5451 */
5452
5453 /**
5454 * @}
5455 */
5456
5457/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 18:55:17 +0100