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1/**
2 ******************************************************************************
3 * @file stm32f207xx.h
4 * @author MCD Application Team
5 * @version V2.2.0
6 * @date 17-March-2017
7 * @brief CMSIS STM32F207xx Device Peripheral Access Layer Header File.
8 * This file contains :
9 * - Data structures and the address mapping for all peripherals
10 * - Peripherals registers declarations and bits definition
11 * - Macros to access peripheral�s registers hardware
12 *
13 ******************************************************************************
14 * @attention
15 *
16 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
17 *
18 * Redistribution and use in source and binary forms, with or without modification,
19 * are permitted provided that the following conditions are met:
20 * 1. Redistributions of source code must retain the above copyright notice,
21 * this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright notice,
23 * this list of conditions and the following disclaimer in the documentation
24 * and/or other materials provided with the distribution.
25 * 3. Neither the name of STMicroelectronics nor the names of its contributors
26 * may be used to endorse or promote products derived from this software
27 * without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
32 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 ******************************************************************************
41 */
42
43/** @addtogroup CMSIS
44 * @{
45 */
46
47/** @addtogroup stm32f207xx
48 * @{
49 */
50
51#ifndef __STM32F207xx_H
52#define __STM32F207xx_H
53
54#ifdef __cplusplus
55 extern "C" {
56#endif /* __cplusplus */
57
58
59/** @addtogroup Configuration_section_for_CMSIS
60 * @{
61 */
62
63/**
64 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
65 */
66#define __CM3_REV 0x0200U /*!< Core revision r0p1 */
67#define __MPU_PRESENT 1U /*!< STM32F2XX provides an MPU */
68#define __NVIC_PRIO_BITS 4U /*!< STM32F2XX uses 4 Bits for the Priority Levels */
69#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
70
71/**
72 * @}
73 */
74
75/** @addtogroup Peripheral_interrupt_number_definition
76 * @{
77 */
78
79/**
80 * @brief STM32F2XX Interrupt Number Definition, according to the selected device
81 * in @ref Library_configuration_section
82 */
83typedef enum
84{
85/****** Cortex-M3 Processor Exceptions Numbers ****************************************************************/
86 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
87 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
88 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
89 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
90 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
91 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
92 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
93 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
94/****** STM32 specific Interrupt Numbers **********************************************************************/
95 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
96 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
97 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
98 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
99 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
100 RCC_IRQn = 5, /*!< RCC global Interrupt */
101 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
102 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
103 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
104 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
105 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
106 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
107 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
108 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
109 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
110 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
111 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
112 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
113 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
114 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
115 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
116 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
117 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
118 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
119 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
120 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
121 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
122 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
123 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
124 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
125 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
126 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
127 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
128 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
129 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
130 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
131 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
132 USART1_IRQn = 37, /*!< USART1 global Interrupt */
133 USART2_IRQn = 38, /*!< USART2 global Interrupt */
134 USART3_IRQn = 39, /*!< USART3 global Interrupt */
135 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
136 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
137 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
138 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
139 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
140 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
141 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
142 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
143 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
144 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
145 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
146 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
147 UART4_IRQn = 52, /*!< UART4 global Interrupt */
148 UART5_IRQn = 53, /*!< UART5 global Interrupt */
149 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
150 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
151 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
152 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
153 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
154 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
155 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
156 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
157 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
158 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
159 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
160 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
161 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
162 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
163 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
164 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
165 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
166 USART6_IRQn = 71, /*!< USART6 global interrupt */
167 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
168 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
169 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
170 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
171 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
172 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
173 DCMI_IRQn = 78, /*!< DCMI global interrupt */
174 HASH_RNG_IRQn = 80 /*!< Hash and Rng global interrupt */
175} IRQn_Type;
176
177/**
178 * @}
179 */
180
181#include "core_cm3.h"
182#include "system_stm32f2xx.h"
183#include <stdint.h>
184
185/** @addtogroup Peripheral_registers_structures
186 * @{
187 */
188
189/**
190 * @brief Analog to Digital Converter
191 */
192
193typedef struct
194{
195 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
196 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
197 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
198 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
199 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
200 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
201 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
202 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
203 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
204 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
205 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
206 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
207 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
208 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
209 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
210 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
211 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
212 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
213 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
214 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
215} ADC_TypeDef;
216
217typedef struct
218{
219 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
220 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
221 __IO uint32_t CDR; /*!< ADC common regular data register for dual
222 AND triple modes, Address offset: ADC1 base address + 0x308 */
223} ADC_Common_TypeDef;
224
225
226/**
227 * @brief Controller Area Network TxMailBox
228 */
229
230typedef struct
231{
232 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
233 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
234 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
235 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
236} CAN_TxMailBox_TypeDef;
237
238/**
239 * @brief Controller Area Network FIFOMailBox
240 */
241
242typedef struct
243{
244 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
245 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
246 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
247 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
248} CAN_FIFOMailBox_TypeDef;
249
250/**
251 * @brief Controller Area Network FilterRegister
252 */
253
254typedef struct
255{
256 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
257 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
258} CAN_FilterRegister_TypeDef;
259
260/**
261 * @brief Controller Area Network
262 */
263
264typedef struct
265{
266 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
267 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
268 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
269 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
270 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
271 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
272 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
273 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
274 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
275 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
276 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
277 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
278 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
279 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
280 uint32_t RESERVED2; /*!< Reserved, 0x208 */
281 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
282 uint32_t RESERVED3; /*!< Reserved, 0x210 */
283 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
284 uint32_t RESERVED4; /*!< Reserved, 0x218 */
285 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
286 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
287 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
288} CAN_TypeDef;
289
290/**
291 * @brief CRC calculation unit
292 */
293
294typedef struct
295{
296 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
297 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
298 uint8_t RESERVED0; /*!< Reserved, 0x05 */
299 uint16_t RESERVED1; /*!< Reserved, 0x06 */
300 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
301} CRC_TypeDef;
302
303/**
304 * @brief Digital to Analog Converter
305 */
306
307typedef struct
308{
309 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
310 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
311 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
312 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
313 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
314 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
315 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
316 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
317 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
318 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
319 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
320 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
321 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
322 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
323} DAC_TypeDef;
324
325/**
326 * @brief Debug MCU
327 */
328
329typedef struct
330{
331 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
332 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
333 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
334 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
335}DBGMCU_TypeDef;
336
337/**
338 * @brief DCMI
339 */
340
341typedef struct
342{
343 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
344 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
345 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
346 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
347 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
348 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
349 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
350 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
351 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
352 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
353 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
354} DCMI_TypeDef;
355
356/**
357 * @brief DMA Controller
358 */
359
360typedef struct
361{
362 __IO uint32_t CR; /*!< DMA stream x configuration register */
363 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
364 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
365 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
366 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
367 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
368} DMA_Stream_TypeDef;
369
370typedef struct
371{
372 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
373 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
374 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
375 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
376} DMA_TypeDef;
377
378
379/**
380 * @brief Ethernet MAC
381 */
382
383typedef struct
384{
385 __IO uint32_t MACCR;
386 __IO uint32_t MACFFR;
387 __IO uint32_t MACHTHR;
388 __IO uint32_t MACHTLR;
389 __IO uint32_t MACMIIAR;
390 __IO uint32_t MACMIIDR;
391 __IO uint32_t MACFCR;
392 __IO uint32_t MACVLANTR; /* 8 */
393 uint32_t RESERVED0[2];
394 __IO uint32_t MACRWUFFR; /* 11 */
395 __IO uint32_t MACPMTCSR;
396 uint32_t RESERVED1;
397 __IO uint32_t MACDBGR;
398 __IO uint32_t MACSR; /* 15 */
399 __IO uint32_t MACIMR;
400 __IO uint32_t MACA0HR;
401 __IO uint32_t MACA0LR;
402 __IO uint32_t MACA1HR;
403 __IO uint32_t MACA1LR;
404 __IO uint32_t MACA2HR;
405 __IO uint32_t MACA2LR;
406 __IO uint32_t MACA3HR;
407 __IO uint32_t MACA3LR; /* 24 */
408 uint32_t RESERVED2[40];
409 __IO uint32_t MMCCR; /* 65 */
410 __IO uint32_t MMCRIR;
411 __IO uint32_t MMCTIR;
412 __IO uint32_t MMCRIMR;
413 __IO uint32_t MMCTIMR; /* 69 */
414 uint32_t RESERVED3[14];
415 __IO uint32_t MMCTGFSCCR; /* 84 */
416 __IO uint32_t MMCTGFMSCCR;
417 uint32_t RESERVED4[5];
418 __IO uint32_t MMCTGFCR;
419 uint32_t RESERVED5[10];
420 __IO uint32_t MMCRFCECR;
421 __IO uint32_t MMCRFAECR;
422 uint32_t RESERVED6[10];
423 __IO uint32_t MMCRGUFCR;
424 uint32_t RESERVED7[334];
425 __IO uint32_t PTPTSCR;
426 __IO uint32_t PTPSSIR;
427 __IO uint32_t PTPTSHR;
428 __IO uint32_t PTPTSLR;
429 __IO uint32_t PTPTSHUR;
430 __IO uint32_t PTPTSLUR;
431 __IO uint32_t PTPTSAR;
432 __IO uint32_t PTPTTHR;
433 __IO uint32_t PTPTTLR;
434 __IO uint32_t RESERVED8;
435 __IO uint32_t PTPTSSR;
436 uint32_t RESERVED9[565];
437 __IO uint32_t DMABMR;
438 __IO uint32_t DMATPDR;
439 __IO uint32_t DMARPDR;
440 __IO uint32_t DMARDLAR;
441 __IO uint32_t DMATDLAR;
442 __IO uint32_t DMASR;
443 __IO uint32_t DMAOMR;
444 __IO uint32_t DMAIER;
445 __IO uint32_t DMAMFBOCR;
446 __IO uint32_t DMARSWTR;
447 uint32_t RESERVED10[8];
448 __IO uint32_t DMACHTDR;
449 __IO uint32_t DMACHRDR;
450 __IO uint32_t DMACHTBAR;
451 __IO uint32_t DMACHRBAR;
452} ETH_TypeDef;
453
454/**
455 * @brief External Interrupt/Event Controller
456 */
457
458typedef struct
459{
460 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
461 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
462 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
463 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
464 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
465 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
466} EXTI_TypeDef;
467
468/**
469 * @brief FLASH Registers
470 */
471
472typedef struct
473{
474 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
475 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
476 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
477 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
478 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
479 __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */
480} FLASH_TypeDef;
481
482
483/**
484 * @brief Flexible Static Memory Controller
485 */
486
487typedef struct
488{
489 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
490} FSMC_Bank1_TypeDef;
491
492/**
493 * @brief Flexible Static Memory Controller Bank1E
494 */
495
496typedef struct
497{
498 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
499} FSMC_Bank1E_TypeDef;
500
501/**
502 * @brief Flexible Static Memory Controller Bank2
503 */
504
505typedef struct
506{
507 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
508 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
509 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
510 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
511 uint32_t RESERVED0; /*!< Reserved, 0x70 */
512 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
513 uint32_t RESERVED1; /*!< Reserved, 0x78 */
514 uint32_t RESERVED2; /*!< Reserved, 0x7C */
515 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
516 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
517 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
518 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
519 uint32_t RESERVED3; /*!< Reserved, 0x90 */
520 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
521} FSMC_Bank2_3_TypeDef;
522
523/**
524 * @brief Flexible Static Memory Controller Bank4
525 */
526
527typedef struct
528{
529 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
530 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
531 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
532 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
533 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
534} FSMC_Bank4_TypeDef;
535
536
537/**
538 * @brief General Purpose I/O
539 */
540
541typedef struct
542{
543 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
544 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
545 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
546 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
547 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
548 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
549 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
550 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
551 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
552} GPIO_TypeDef;
553
554/**
555 * @brief System configuration controller
556 */
557
558typedef struct
559{
560 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
561 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
562 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
563 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
564 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
565} SYSCFG_TypeDef;
566
567/**
568 * @brief Inter-integrated Circuit Interface
569 */
570
571typedef struct
572{
573 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
574 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
575 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
576 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
577 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
578 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
579 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
580 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
581 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
582} I2C_TypeDef;
583
584/**
585 * @brief Independent WATCHDOG
586 */
587
588typedef struct
589{
590 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
591 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
592 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
593 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
594} IWDG_TypeDef;
595
596/**
597 * @brief Power Control
598 */
599
600typedef struct
601{
602 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
603 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
604} PWR_TypeDef;
605
606/**
607 * @brief Reset and Clock Control
608 */
609
610typedef struct
611{
612 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
613 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
614 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
615 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
616 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
617 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
618 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
619 uint32_t RESERVED0; /*!< Reserved, 0x1C */
620 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
621 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
622 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
623 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
624 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
625 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
626 uint32_t RESERVED2; /*!< Reserved, 0x3C */
627 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
628 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
629 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
630 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
631 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
632 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
633 uint32_t RESERVED4; /*!< Reserved, 0x5C */
634 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
635 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
636 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
637 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
638 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
639 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
640 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
641 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
642
643} RCC_TypeDef;
644
645/**
646 * @brief Real-Time Clock
647 */
648
649typedef struct
650{
651 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
652 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
653 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
654 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
655 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
656 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
657 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
658 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
659 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
660 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
661 uint32_t RESERVED1; /*!< Reserved, 0x28 */
662 uint32_t RESERVED2; /*!< Reserved, 0x2C */
663 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
664 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
665 uint32_t RESERVED3; /*!< Reserved, 0x38 */
666 uint32_t RESERVED4; /*!< Reserved, 0x3C */
667 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
668 uint32_t RESERVED5; /*!< Reserved, 0x44 */
669 uint32_t RESERVED6; /*!< Reserved, 0x48 */
670 uint32_t RESERVED7; /*!< Reserved, 0x4C */
671 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
672 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
673 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
674 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
675 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
676 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
677 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
678 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
679 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
680 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
681 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
682 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
683 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
684 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
685 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
686 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
687 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
688 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
689 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
690 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
691} RTC_TypeDef;
692
693
694/**
695 * @brief SD host Interface
696 */
697
698typedef struct
699{
700 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
701 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
702 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
703 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
704 __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
705 __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
706 __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
707 __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
708 __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
709 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
710 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
711 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
712 __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
713 __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
714 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
715 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
716 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
717 __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
718 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
719 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
720} SDIO_TypeDef;
721
722/**
723 * @brief Serial Peripheral Interface
724 */
725
726typedef struct
727{
728 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
729 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
730 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
731 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
732 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
733 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
734 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
735 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
736 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
737} SPI_TypeDef;
738
739/**
740 * @brief TIM
741 */
742
743typedef struct
744{
745 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
746 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
747 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
748 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
749 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
750 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
751 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
752 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
753 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
754 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
755 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
756 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
757 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
758 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
759 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
760 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
761 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
762 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
763 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
764 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
765 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
766} TIM_TypeDef;
767
768/**
769 * @brief Universal Synchronous Asynchronous Receiver Transmitter
770 */
771
772typedef struct
773{
774 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
775 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
776 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
777 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
778 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
779 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
780 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
781} USART_TypeDef;
782
783/**
784 * @brief Window WATCHDOG
785 */
786
787typedef struct
788{
789 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
790 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
791 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
792} WWDG_TypeDef;
793
794/**
795 * @brief RNG
796 */
797
798typedef struct
799{
800 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
801 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
802 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
803} RNG_TypeDef;
804
805
806
807/**
808 * @brief __USB_OTG_Core_register
809 */
810typedef struct
811{
812 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */
813 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */
814 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */
815 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */
816 __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */
817 __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */
818 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */
819 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */
820 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */
821 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
822 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */
823 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */
824 uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
825 __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */
826 __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */
827 uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */
828 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */
829 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
830}
831USB_OTG_GlobalTypeDef;
832
833
834
835/**
836 * @brief __device_Registers
837 */
838typedef struct
839{
840 __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
841 __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
842 __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */
843 uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */
844 __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
845 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */
846 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */
847 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */
848 uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */
849 uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */
850 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */
851 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */
852 __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
853 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
854 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
855 __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
856 uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
857 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
858 uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
859 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
860}
861USB_OTG_DeviceTypeDef;
862
863
864/**
865 * @brief __IN_Endpoint-Specific_Register
866 */
867typedef struct
868{
869 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
870 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
871 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
872 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
873 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
874 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
875 __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
876 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
877}
878USB_OTG_INEndpointTypeDef;
879
880
881/**
882 * @brief __OUT_Endpoint-Specific_Registers
883 */
884typedef struct
885{
886 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
887 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
888 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
889 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
890 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
891 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
892 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
893}
894USB_OTG_OUTEndpointTypeDef;
895
896
897/**
898 * @brief __Host_Mode_Register_Structures
899 */
900typedef struct
901{
902 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
903 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
904 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
905 uint32_t Reserved40C; /* Reserved 40Ch*/
906 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
907 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
908 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
909}
910USB_OTG_HostTypeDef;
911
912
913/**
914 * @brief __Host_Channel_Specific_Registers
915 */
916typedef struct
917{
918 __IO uint32_t HCCHAR;
919 __IO uint32_t HCSPLT;
920 __IO uint32_t HCINT;
921 __IO uint32_t HCINTMSK;
922 __IO uint32_t HCTSIZ;
923 __IO uint32_t HCDMA;
924 uint32_t Reserved[2];
925}
926USB_OTG_HostChannelTypeDef;
927
928
929/**
930 * @brief Peripheral_memory_map
931 */
932#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
933#define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
934#define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
935#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
936#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
937#define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
938#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
939#define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
940#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
941#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
942#define FLASH_END 0x080FFFFFU /*!< FLASH end address */
943#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
944#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
945
946/* Legacy defines */
947#define SRAM_BASE SRAM1_BASE
948#define SRAM_BB_BASE SRAM1_BB_BASE
949
950
951/*!< Peripheral memory map */
952#define APB1PERIPH_BASE PERIPH_BASE
953#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
954#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
955#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
956
957/*!< APB1 peripherals */
958#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
959#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
960#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
961#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
962#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
963#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
964#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
965#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
966#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
967#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
968#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
969#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
970#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
971#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
972#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
973#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
974#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
975#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
976#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
977#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
978#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
979#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
980#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
981#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
982#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
983
984/*!< APB2 peripherals */
985#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
986#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
987#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
988#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
989#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
990#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
991#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
992#define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
993/* Legacy define */
994#define ADC_BASE ADC123_COMMON_BASE
995
996#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
997#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
998#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
999#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
1000#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
1001#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
1002#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
1003
1004/*!< AHB1 peripherals */
1005#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
1006#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1007#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1008#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1009#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1010#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1011#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1012#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1013#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
1014#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1015#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1016#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1017#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1018#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1019#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1020#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1021#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1022#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1023#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1024#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1025#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1026#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1027#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1028#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1029#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1030#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1031#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1032#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1033#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1034#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1035#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
1036#define ETH_MAC_BASE (ETH_BASE)
1037#define ETH_MMC_BASE (ETH_BASE + 0x0100U)
1038#define ETH_PTP_BASE (ETH_BASE + 0x0700U)
1039#define ETH_DMA_BASE (ETH_BASE + 0x1000U)
1040
1041/*!< AHB2 peripherals */
1042#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
1043#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1044
1045/*!< FSMC Bankx registers base address */
1046#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000U)
1047#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104U)
1048#define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060U)
1049#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0U)
1050
1051/* Debug MCU registers base address */
1052#define DBGMCU_BASE 0xE0042000U
1053
1054/*!< USB registers base address */
1055#define USB_OTG_HS_PERIPH_BASE 0x40040000U
1056#define USB_OTG_FS_PERIPH_BASE 0x50000000U
1057
1058#define USB_OTG_GLOBAL_BASE 0x000U
1059#define USB_OTG_DEVICE_BASE 0x800U
1060#define USB_OTG_IN_ENDPOINT_BASE 0x900U
1061#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1062#define USB_OTG_EP_REG_SIZE 0x20U
1063#define USB_OTG_HOST_BASE 0x400U
1064#define USB_OTG_HOST_PORT_BASE 0x440U
1065#define USB_OTG_HOST_CHANNEL_BASE 0x500U
1066#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1067#define USB_OTG_PCGCCTL_BASE 0xE00U
1068#define USB_OTG_FIFO_BASE 0x1000U
1069#define USB_OTG_FIFO_SIZE 0x1000U
1070
1071/******************* Device electronic signature ***************/
1072#define UID_BASE 0x1FFF7A10 /*!< Unique device ID register base address */
1073#define FLASHSIZE_BASE 0x1FFF7A22 /*!< FLASH Size register base address */
1074
1075/**
1076 * @}
1077 */
1078
1079/** @addtogroup Peripheral_declaration
1080 * @{
1081 */
1082#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1083#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1084#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1085#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1086#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1087#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1088#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1089#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1090#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1091#define RTC ((RTC_TypeDef *) RTC_BASE)
1092#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1093#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1094#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1095#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1096#define USART2 ((USART_TypeDef *) USART2_BASE)
1097#define USART3 ((USART_TypeDef *) USART3_BASE)
1098#define UART4 ((USART_TypeDef *) UART4_BASE)
1099#define UART5 ((USART_TypeDef *) UART5_BASE)
1100#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1101#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1102#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1103#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1104#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1105#define PWR ((PWR_TypeDef *) PWR_BASE)
1106#define DAC1 ((DAC_TypeDef *) DAC_BASE)
1107#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1108#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1109#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1110#define USART1 ((USART_TypeDef *) USART1_BASE)
1111#define USART6 ((USART_TypeDef *) USART6_BASE)
1112#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1113#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1114#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1115#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1116/* Legacy define */
1117#define ADC ADC123_COMMON
1118#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1119#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1120#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1121#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1122#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1123#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1124#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1125#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1126#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1127#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1128#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1129#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1130#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1131#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1132#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1133#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1134#define CRC ((CRC_TypeDef *) CRC_BASE)
1135#define RCC ((RCC_TypeDef *) RCC_BASE)
1136#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1137#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1138#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1139#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1140#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1141#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1142#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1143#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1144#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1145#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1146#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1147#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1148#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1149#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1150#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1151#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1152#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1153#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1154#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1155#define ETH ((ETH_TypeDef *) ETH_BASE)
1156#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1157#define RNG ((RNG_TypeDef *) RNG_BASE)
1158#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1159#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1160#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
1161#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
1162
1163#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1164
1165#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1166#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1167
1168/**
1169 * @}
1170 */
1171
1172/** @addtogroup Exported_constants
1173 * @{
1174 */
1175
1176 /** @addtogroup Peripheral_Registers_Bits_Definition
1177 * @{
1178 */
1179
1180/******************************************************************************/
1181/* Peripheral Registers_Bits_Definition */
1182/******************************************************************************/
1183
1184/******************************************************************************/
1185/* */
1186/* Analog to Digital Converter */
1187/* */
1188/******************************************************************************/
1189/******************** Bit definition for ADC_SR register ********************/
1190#define ADC_SR_AWD_Pos (0U)
1191#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
1192#define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
1193#define ADC_SR_EOC_Pos (1U)
1194#define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
1195#define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
1196#define ADC_SR_JEOC_Pos (2U)
1197#define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
1198#define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
1199#define ADC_SR_JSTRT_Pos (3U)
1200#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
1201#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
1202#define ADC_SR_STRT_Pos (4U)
1203#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
1204#define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
1205#define ADC_SR_OVR_Pos (5U)
1206#define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
1207#define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
1208
1209/******************* Bit definition for ADC_CR1 register ********************/
1210#define ADC_CR1_AWDCH_Pos (0U)
1211#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
1212#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1213#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
1214#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
1215#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
1216#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
1217#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
1218#define ADC_CR1_EOCIE_Pos (5U)
1219#define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
1220#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
1221#define ADC_CR1_AWDIE_Pos (6U)
1222#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
1223#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
1224#define ADC_CR1_JEOCIE_Pos (7U)
1225#define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
1226#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
1227#define ADC_CR1_SCAN_Pos (8U)
1228#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
1229#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
1230#define ADC_CR1_AWDSGL_Pos (9U)
1231#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
1232#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
1233#define ADC_CR1_JAUTO_Pos (10U)
1234#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
1235#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
1236#define ADC_CR1_DISCEN_Pos (11U)
1237#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
1238#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
1239#define ADC_CR1_JDISCEN_Pos (12U)
1240#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
1241#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
1242#define ADC_CR1_DISCNUM_Pos (13U)
1243#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
1244#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1245#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
1246#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
1247#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
1248#define ADC_CR1_JAWDEN_Pos (22U)
1249#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
1250#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
1251#define ADC_CR1_AWDEN_Pos (23U)
1252#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
1253#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
1254#define ADC_CR1_RES_Pos (24U)
1255#define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
1256#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
1257#define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
1258#define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
1259#define ADC_CR1_OVRIE_Pos (26U)
1260#define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
1261#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
1262
1263/******************* Bit definition for ADC_CR2 register ********************/
1264#define ADC_CR2_ADON_Pos (0U)
1265#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
1266#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
1267#define ADC_CR2_CONT_Pos (1U)
1268#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
1269#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
1270#define ADC_CR2_DMA_Pos (8U)
1271#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
1272#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
1273#define ADC_CR2_DDS_Pos (9U)
1274#define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
1275#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
1276#define ADC_CR2_EOCS_Pos (10U)
1277#define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
1278#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
1279#define ADC_CR2_ALIGN_Pos (11U)
1280#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
1281#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
1282#define ADC_CR2_JEXTSEL_Pos (16U)
1283#define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
1284#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1285#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
1286#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
1287#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
1288#define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
1289#define ADC_CR2_JEXTEN_Pos (20U)
1290#define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
1291#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1292#define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
1293#define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
1294#define ADC_CR2_JSWSTART_Pos (22U)
1295#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
1296#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
1297#define ADC_CR2_EXTSEL_Pos (24U)
1298#define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
1299#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1300#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
1301#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
1302#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
1303#define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
1304#define ADC_CR2_EXTEN_Pos (28U)
1305#define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
1306#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1307#define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
1308#define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
1309#define ADC_CR2_SWSTART_Pos (30U)
1310#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
1311#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
1312
1313/****************** Bit definition for ADC_SMPR1 register *******************/
1314#define ADC_SMPR1_SMP10_Pos (0U)
1315#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
1316#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1317#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
1318#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
1319#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
1320#define ADC_SMPR1_SMP11_Pos (3U)
1321#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
1322#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1323#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
1324#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
1325#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
1326#define ADC_SMPR1_SMP12_Pos (6U)
1327#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
1328#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1329#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
1330#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
1331#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
1332#define ADC_SMPR1_SMP13_Pos (9U)
1333#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
1334#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1335#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
1336#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
1337#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
1338#define ADC_SMPR1_SMP14_Pos (12U)
1339#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
1340#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1341#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
1342#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
1343#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
1344#define ADC_SMPR1_SMP15_Pos (15U)
1345#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
1346#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1347#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
1348#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
1349#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
1350#define ADC_SMPR1_SMP16_Pos (18U)
1351#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
1352#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1353#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
1354#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
1355#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
1356#define ADC_SMPR1_SMP17_Pos (21U)
1357#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
1358#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1359#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
1360#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
1361#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
1362#define ADC_SMPR1_SMP18_Pos (24U)
1363#define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
1364#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1365#define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
1366#define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
1367#define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
1368
1369/****************** Bit definition for ADC_SMPR2 register *******************/
1370#define ADC_SMPR2_SMP0_Pos (0U)
1371#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
1372#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1373#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
1374#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
1375#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
1376#define ADC_SMPR2_SMP1_Pos (3U)
1377#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
1378#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1379#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
1380#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
1381#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
1382#define ADC_SMPR2_SMP2_Pos (6U)
1383#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
1384#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1385#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
1386#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
1387#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
1388#define ADC_SMPR2_SMP3_Pos (9U)
1389#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
1390#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1391#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
1392#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
1393#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
1394#define ADC_SMPR2_SMP4_Pos (12U)
1395#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
1396#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1397#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
1398#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
1399#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
1400#define ADC_SMPR2_SMP5_Pos (15U)
1401#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
1402#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1403#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
1404#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
1405#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
1406#define ADC_SMPR2_SMP6_Pos (18U)
1407#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
1408#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1409#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
1410#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
1411#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
1412#define ADC_SMPR2_SMP7_Pos (21U)
1413#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
1414#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1415#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
1416#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
1417#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
1418#define ADC_SMPR2_SMP8_Pos (24U)
1419#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
1420#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1421#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
1422#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
1423#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
1424#define ADC_SMPR2_SMP9_Pos (27U)
1425#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
1426#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1427#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
1428#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
1429#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
1430
1431/****************** Bit definition for ADC_JOFR1 register *******************/
1432#define ADC_JOFR1_JOFFSET1_Pos (0U)
1433#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
1434#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
1435
1436/****************** Bit definition for ADC_JOFR2 register *******************/
1437#define ADC_JOFR2_JOFFSET2_Pos (0U)
1438#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
1439#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
1440
1441/****************** Bit definition for ADC_JOFR3 register *******************/
1442#define ADC_JOFR3_JOFFSET3_Pos (0U)
1443#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
1444#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
1445
1446/****************** Bit definition for ADC_JOFR4 register *******************/
1447#define ADC_JOFR4_JOFFSET4_Pos (0U)
1448#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
1449#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
1450
1451/******************* Bit definition for ADC_HTR register ********************/
1452#define ADC_HTR_HT_Pos (0U)
1453#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
1454#define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
1455
1456/******************* Bit definition for ADC_LTR register ********************/
1457#define ADC_LTR_LT_Pos (0U)
1458#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
1459#define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
1460
1461/******************* Bit definition for ADC_SQR1 register *******************/
1462#define ADC_SQR1_SQ13_Pos (0U)
1463#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
1464#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1465#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
1466#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
1467#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
1468#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
1469#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
1470#define ADC_SQR1_SQ14_Pos (5U)
1471#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
1472#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1473#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
1474#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
1475#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
1476#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
1477#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
1478#define ADC_SQR1_SQ15_Pos (10U)
1479#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
1480#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1481#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
1482#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
1483#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
1484#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
1485#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
1486#define ADC_SQR1_SQ16_Pos (15U)
1487#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
1488#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1489#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
1490#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
1491#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
1492#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
1493#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
1494#define ADC_SQR1_L_Pos (20U)
1495#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
1496#define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
1497#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
1498#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
1499#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
1500#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
1501
1502/******************* Bit definition for ADC_SQR2 register *******************/
1503#define ADC_SQR2_SQ7_Pos (0U)
1504#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
1505#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1506#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
1507#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
1508#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
1509#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
1510#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
1511#define ADC_SQR2_SQ8_Pos (5U)
1512#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
1513#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1514#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
1515#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
1516#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
1517#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
1518#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
1519#define ADC_SQR2_SQ9_Pos (10U)
1520#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
1521#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1522#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
1523#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
1524#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
1525#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
1526#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
1527#define ADC_SQR2_SQ10_Pos (15U)
1528#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
1529#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1530#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
1531#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
1532#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
1533#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
1534#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
1535#define ADC_SQR2_SQ11_Pos (20U)
1536#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
1537#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1538#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
1539#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
1540#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
1541#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
1542#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
1543#define ADC_SQR2_SQ12_Pos (25U)
1544#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
1545#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1546#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
1547#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
1548#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
1549#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
1550#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
1551
1552/******************* Bit definition for ADC_SQR3 register *******************/
1553#define ADC_SQR3_SQ1_Pos (0U)
1554#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
1555#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1556#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
1557#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
1558#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
1559#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
1560#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
1561#define ADC_SQR3_SQ2_Pos (5U)
1562#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
1563#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1564#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
1565#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
1566#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
1567#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
1568#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
1569#define ADC_SQR3_SQ3_Pos (10U)
1570#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
1571#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1572#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
1573#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
1574#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
1575#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
1576#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
1577#define ADC_SQR3_SQ4_Pos (15U)
1578#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
1579#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1580#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
1581#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
1582#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
1583#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
1584#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
1585#define ADC_SQR3_SQ5_Pos (20U)
1586#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
1587#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1588#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
1589#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
1590#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
1591#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
1592#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
1593#define ADC_SQR3_SQ6_Pos (25U)
1594#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
1595#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1596#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
1597#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
1598#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
1599#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
1600#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
1601
1602/******************* Bit definition for ADC_JSQR register *******************/
1603#define ADC_JSQR_JSQ1_Pos (0U)
1604#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
1605#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1606#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
1607#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
1608#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
1609#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
1610#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
1611#define ADC_JSQR_JSQ2_Pos (5U)
1612#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
1613#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1614#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
1615#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
1616#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
1617#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
1618#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
1619#define ADC_JSQR_JSQ3_Pos (10U)
1620#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
1621#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1622#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
1623#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
1624#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
1625#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
1626#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
1627#define ADC_JSQR_JSQ4_Pos (15U)
1628#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
1629#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1630#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
1631#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
1632#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
1633#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
1634#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
1635#define ADC_JSQR_JL_Pos (20U)
1636#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
1637#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
1638#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
1639#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
1640
1641/******************* Bit definition for ADC_JDR1 register *******************/
1642#define ADC_JDR1_JDATA_Pos (0U)
1643#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
1644#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
1645
1646/******************* Bit definition for ADC_JDR2 register *******************/
1647#define ADC_JDR2_JDATA_Pos (0U)
1648#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
1649#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
1650
1651/******************* Bit definition for ADC_JDR3 register *******************/
1652#define ADC_JDR3_JDATA_Pos (0U)
1653#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
1654#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
1655
1656/******************* Bit definition for ADC_JDR4 register *******************/
1657#define ADC_JDR4_JDATA_Pos (0U)
1658#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
1659#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
1660
1661/******************** Bit definition for ADC_DR register ********************/
1662#define ADC_DR_DATA_Pos (0U)
1663#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
1664#define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
1665#define ADC_DR_ADC2DATA_Pos (16U)
1666#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
1667#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
1668
1669/******************* Bit definition for ADC_CSR register ********************/
1670#define ADC_CSR_AWD1_Pos (0U)
1671#define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
1672#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
1673#define ADC_CSR_EOC1_Pos (1U)
1674#define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
1675#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
1676#define ADC_CSR_JEOC1_Pos (2U)
1677#define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
1678#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
1679#define ADC_CSR_JSTRT1_Pos (3U)
1680#define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
1681#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
1682#define ADC_CSR_STRT1_Pos (4U)
1683#define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
1684#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
1685#define ADC_CSR_OVR1_Pos (5U)
1686#define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
1687#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
1688#define ADC_CSR_AWD2_Pos (8U)
1689#define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
1690#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
1691#define ADC_CSR_EOC2_Pos (9U)
1692#define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
1693#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
1694#define ADC_CSR_JEOC2_Pos (10U)
1695#define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
1696#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
1697#define ADC_CSR_JSTRT2_Pos (11U)
1698#define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
1699#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
1700#define ADC_CSR_STRT2_Pos (12U)
1701#define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
1702#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
1703#define ADC_CSR_OVR2_Pos (13U)
1704#define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
1705#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */
1706#define ADC_CSR_AWD3_Pos (16U)
1707#define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
1708#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
1709#define ADC_CSR_EOC3_Pos (17U)
1710#define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
1711#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
1712#define ADC_CSR_JEOC3_Pos (18U)
1713#define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
1714#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
1715#define ADC_CSR_JSTRT3_Pos (19U)
1716#define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
1717#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
1718#define ADC_CSR_STRT3_Pos (20U)
1719#define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
1720#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
1721#define ADC_CSR_OVR3_Pos (21U)
1722#define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
1723#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */
1724
1725/* Legacy defines */
1726#define ADC_CSR_DOVR1 ADC_CSR_OVR1
1727#define ADC_CSR_DOVR2 ADC_CSR_OVR2
1728#define ADC_CSR_DOVR3 ADC_CSR_OVR3
1729
1730/******************* Bit definition for ADC_CCR register ********************/
1731#define ADC_CCR_MULTI_Pos (0U)
1732#define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
1733#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1734#define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
1735#define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
1736#define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
1737#define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
1738#define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
1739#define ADC_CCR_DELAY_Pos (8U)
1740#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
1741#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1742#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
1743#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
1744#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
1745#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
1746#define ADC_CCR_DDS_Pos (13U)
1747#define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
1748#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
1749#define ADC_CCR_DMA_Pos (14U)
1750#define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
1751#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1752#define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
1753#define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
1754#define ADC_CCR_ADCPRE_Pos (16U)
1755#define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
1756#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
1757#define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
1758#define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
1759#define ADC_CCR_VBATE_Pos (22U)
1760#define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
1761#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
1762#define ADC_CCR_TSVREFE_Pos (23U)
1763#define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
1764#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
1765
1766/******************* Bit definition for ADC_CDR register ********************/
1767#define ADC_CDR_DATA1_Pos (0U)
1768#define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
1769#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
1770#define ADC_CDR_DATA2_Pos (16U)
1771#define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
1772#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
1773
1774/* Legacy defines */
1775#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
1776#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
1777
1778/******************************************************************************/
1779/* */
1780/* Controller Area Network */
1781/* */
1782/******************************************************************************/
1783/*!<CAN control and status registers */
1784/******************* Bit definition for CAN_MCR register ********************/
1785#define CAN_MCR_INRQ_Pos (0U)
1786#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
1787#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
1788#define CAN_MCR_SLEEP_Pos (1U)
1789#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
1790#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
1791#define CAN_MCR_TXFP_Pos (2U)
1792#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
1793#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
1794#define CAN_MCR_RFLM_Pos (3U)
1795#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
1796#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
1797#define CAN_MCR_NART_Pos (4U)
1798#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
1799#define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
1800#define CAN_MCR_AWUM_Pos (5U)
1801#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
1802#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
1803#define CAN_MCR_ABOM_Pos (6U)
1804#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
1805#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
1806#define CAN_MCR_TTCM_Pos (7U)
1807#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
1808#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
1809#define CAN_MCR_RESET_Pos (15U)
1810#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
1811#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
1812#define CAN_MCR_DBF_Pos (16U)
1813#define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
1814#define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
1815/******************* Bit definition for CAN_MSR register ********************/
1816#define CAN_MSR_INAK_Pos (0U)
1817#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
1818#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
1819#define CAN_MSR_SLAK_Pos (1U)
1820#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
1821#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
1822#define CAN_MSR_ERRI_Pos (2U)
1823#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
1824#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
1825#define CAN_MSR_WKUI_Pos (3U)
1826#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
1827#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
1828#define CAN_MSR_SLAKI_Pos (4U)
1829#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
1830#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
1831#define CAN_MSR_TXM_Pos (8U)
1832#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
1833#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
1834#define CAN_MSR_RXM_Pos (9U)
1835#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
1836#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
1837#define CAN_MSR_SAMP_Pos (10U)
1838#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
1839#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
1840#define CAN_MSR_RX_Pos (11U)
1841#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
1842#define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
1843
1844/******************* Bit definition for CAN_TSR register ********************/
1845#define CAN_TSR_RQCP0_Pos (0U)
1846#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
1847#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
1848#define CAN_TSR_TXOK0_Pos (1U)
1849#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
1850#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
1851#define CAN_TSR_ALST0_Pos (2U)
1852#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
1853#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
1854#define CAN_TSR_TERR0_Pos (3U)
1855#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
1856#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
1857#define CAN_TSR_ABRQ0_Pos (7U)
1858#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
1859#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
1860#define CAN_TSR_RQCP1_Pos (8U)
1861#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
1862#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
1863#define CAN_TSR_TXOK1_Pos (9U)
1864#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
1865#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
1866#define CAN_TSR_ALST1_Pos (10U)
1867#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
1868#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
1869#define CAN_TSR_TERR1_Pos (11U)
1870#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
1871#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
1872#define CAN_TSR_ABRQ1_Pos (15U)
1873#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
1874#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
1875#define CAN_TSR_RQCP2_Pos (16U)
1876#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
1877#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
1878#define CAN_TSR_TXOK2_Pos (17U)
1879#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
1880#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
1881#define CAN_TSR_ALST2_Pos (18U)
1882#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
1883#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
1884#define CAN_TSR_TERR2_Pos (19U)
1885#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
1886#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
1887#define CAN_TSR_ABRQ2_Pos (23U)
1888#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
1889#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
1890#define CAN_TSR_CODE_Pos (24U)
1891#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
1892#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
1893
1894#define CAN_TSR_TME_Pos (26U)
1895#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
1896#define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
1897#define CAN_TSR_TME0_Pos (26U)
1898#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
1899#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
1900#define CAN_TSR_TME1_Pos (27U)
1901#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
1902#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
1903#define CAN_TSR_TME2_Pos (28U)
1904#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
1905#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
1906
1907#define CAN_TSR_LOW_Pos (29U)
1908#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
1909#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
1910#define CAN_TSR_LOW0_Pos (29U)
1911#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
1912#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
1913#define CAN_TSR_LOW1_Pos (30U)
1914#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
1915#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
1916#define CAN_TSR_LOW2_Pos (31U)
1917#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
1918#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
1919
1920/******************* Bit definition for CAN_RF0R register *******************/
1921#define CAN_RF0R_FMP0_Pos (0U)
1922#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
1923#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
1924#define CAN_RF0R_FULL0_Pos (3U)
1925#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
1926#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
1927#define CAN_RF0R_FOVR0_Pos (4U)
1928#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
1929#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
1930#define CAN_RF0R_RFOM0_Pos (5U)
1931#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
1932#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
1933
1934/******************* Bit definition for CAN_RF1R register *******************/
1935#define CAN_RF1R_FMP1_Pos (0U)
1936#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
1937#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
1938#define CAN_RF1R_FULL1_Pos (3U)
1939#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
1940#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
1941#define CAN_RF1R_FOVR1_Pos (4U)
1942#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
1943#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
1944#define CAN_RF1R_RFOM1_Pos (5U)
1945#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
1946#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
1947
1948/******************** Bit definition for CAN_IER register *******************/
1949#define CAN_IER_TMEIE_Pos (0U)
1950#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
1951#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
1952#define CAN_IER_FMPIE0_Pos (1U)
1953#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
1954#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
1955#define CAN_IER_FFIE0_Pos (2U)
1956#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
1957#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
1958#define CAN_IER_FOVIE0_Pos (3U)
1959#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
1960#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
1961#define CAN_IER_FMPIE1_Pos (4U)
1962#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
1963#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
1964#define CAN_IER_FFIE1_Pos (5U)
1965#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
1966#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
1967#define CAN_IER_FOVIE1_Pos (6U)
1968#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
1969#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
1970#define CAN_IER_EWGIE_Pos (8U)
1971#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
1972#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
1973#define CAN_IER_EPVIE_Pos (9U)
1974#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
1975#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
1976#define CAN_IER_BOFIE_Pos (10U)
1977#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
1978#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
1979#define CAN_IER_LECIE_Pos (11U)
1980#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
1981#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
1982#define CAN_IER_ERRIE_Pos (15U)
1983#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
1984#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
1985#define CAN_IER_WKUIE_Pos (16U)
1986#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
1987#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
1988#define CAN_IER_SLKIE_Pos (17U)
1989#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
1990#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
1991
1992/******************** Bit definition for CAN_ESR register *******************/
1993#define CAN_ESR_EWGF_Pos (0U)
1994#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
1995#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
1996#define CAN_ESR_EPVF_Pos (1U)
1997#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
1998#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
1999#define CAN_ESR_BOFF_Pos (2U)
2000#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
2001#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
2002
2003#define CAN_ESR_LEC_Pos (4U)
2004#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
2005#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
2006#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
2007#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
2008#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
2009
2010#define CAN_ESR_TEC_Pos (16U)
2011#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
2012#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
2013#define CAN_ESR_REC_Pos (24U)
2014#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
2015#define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
2016
2017/******************* Bit definition for CAN_BTR register ********************/
2018#define CAN_BTR_BRP_Pos (0U)
2019#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
2020#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
2021#define CAN_BTR_TS1_Pos (16U)
2022#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
2023#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
2024#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
2025#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
2026#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
2027#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
2028#define CAN_BTR_TS2_Pos (20U)
2029#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
2030#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
2031#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
2032#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
2033#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
2034#define CAN_BTR_SJW_Pos (24U)
2035#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
2036#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
2037#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
2038#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
2039#define CAN_BTR_LBKM_Pos (30U)
2040#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
2041#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
2042#define CAN_BTR_SILM_Pos (31U)
2043#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
2044#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
2045
2046
2047/*!<Mailbox registers */
2048/****************** Bit definition for CAN_TI0R register ********************/
2049#define CAN_TI0R_TXRQ_Pos (0U)
2050#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
2051#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
2052#define CAN_TI0R_RTR_Pos (1U)
2053#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
2054#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
2055#define CAN_TI0R_IDE_Pos (2U)
2056#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
2057#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
2058#define CAN_TI0R_EXID_Pos (3U)
2059#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
2060#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
2061#define CAN_TI0R_STID_Pos (21U)
2062#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
2063#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2064
2065/****************** Bit definition for CAN_TDT0R register *******************/
2066#define CAN_TDT0R_DLC_Pos (0U)
2067#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
2068#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
2069#define CAN_TDT0R_TGT_Pos (8U)
2070#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
2071#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
2072#define CAN_TDT0R_TIME_Pos (16U)
2073#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2074#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
2075
2076/****************** Bit definition for CAN_TDL0R register *******************/
2077#define CAN_TDL0R_DATA0_Pos (0U)
2078#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
2079#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
2080#define CAN_TDL0R_DATA1_Pos (8U)
2081#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2082#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
2083#define CAN_TDL0R_DATA2_Pos (16U)
2084#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2085#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
2086#define CAN_TDL0R_DATA3_Pos (24U)
2087#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
2088#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
2089
2090/****************** Bit definition for CAN_TDH0R register *******************/
2091#define CAN_TDH0R_DATA4_Pos (0U)
2092#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
2093#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
2094#define CAN_TDH0R_DATA5_Pos (8U)
2095#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2096#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
2097#define CAN_TDH0R_DATA6_Pos (16U)
2098#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2099#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
2100#define CAN_TDH0R_DATA7_Pos (24U)
2101#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
2102#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
2103
2104/******************* Bit definition for CAN_TI1R register *******************/
2105#define CAN_TI1R_TXRQ_Pos (0U)
2106#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
2107#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
2108#define CAN_TI1R_RTR_Pos (1U)
2109#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
2110#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
2111#define CAN_TI1R_IDE_Pos (2U)
2112#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
2113#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
2114#define CAN_TI1R_EXID_Pos (3U)
2115#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
2116#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
2117#define CAN_TI1R_STID_Pos (21U)
2118#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
2119#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2120
2121/******************* Bit definition for CAN_TDT1R register ******************/
2122#define CAN_TDT1R_DLC_Pos (0U)
2123#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
2124#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
2125#define CAN_TDT1R_TGT_Pos (8U)
2126#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
2127#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
2128#define CAN_TDT1R_TIME_Pos (16U)
2129#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2130#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
2131
2132/******************* Bit definition for CAN_TDL1R register ******************/
2133#define CAN_TDL1R_DATA0_Pos (0U)
2134#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
2135#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
2136#define CAN_TDL1R_DATA1_Pos (8U)
2137#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2138#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
2139#define CAN_TDL1R_DATA2_Pos (16U)
2140#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2141#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
2142#define CAN_TDL1R_DATA3_Pos (24U)
2143#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
2144#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
2145
2146/******************* Bit definition for CAN_TDH1R register ******************/
2147#define CAN_TDH1R_DATA4_Pos (0U)
2148#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
2149#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
2150#define CAN_TDH1R_DATA5_Pos (8U)
2151#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2152#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
2153#define CAN_TDH1R_DATA6_Pos (16U)
2154#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2155#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
2156#define CAN_TDH1R_DATA7_Pos (24U)
2157#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
2158#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
2159
2160/******************* Bit definition for CAN_TI2R register *******************/
2161#define CAN_TI2R_TXRQ_Pos (0U)
2162#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
2163#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
2164#define CAN_TI2R_RTR_Pos (1U)
2165#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
2166#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
2167#define CAN_TI2R_IDE_Pos (2U)
2168#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
2169#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
2170#define CAN_TI2R_EXID_Pos (3U)
2171#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
2172#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
2173#define CAN_TI2R_STID_Pos (21U)
2174#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
2175#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2176
2177/******************* Bit definition for CAN_TDT2R register ******************/
2178#define CAN_TDT2R_DLC_Pos (0U)
2179#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
2180#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
2181#define CAN_TDT2R_TGT_Pos (8U)
2182#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
2183#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
2184#define CAN_TDT2R_TIME_Pos (16U)
2185#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
2186#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
2187
2188/******************* Bit definition for CAN_TDL2R register ******************/
2189#define CAN_TDL2R_DATA0_Pos (0U)
2190#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
2191#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
2192#define CAN_TDL2R_DATA1_Pos (8U)
2193#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
2194#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
2195#define CAN_TDL2R_DATA2_Pos (16U)
2196#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
2197#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
2198#define CAN_TDL2R_DATA3_Pos (24U)
2199#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
2200#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
2201
2202/******************* Bit definition for CAN_TDH2R register ******************/
2203#define CAN_TDH2R_DATA4_Pos (0U)
2204#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
2205#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
2206#define CAN_TDH2R_DATA5_Pos (8U)
2207#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
2208#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
2209#define CAN_TDH2R_DATA6_Pos (16U)
2210#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
2211#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
2212#define CAN_TDH2R_DATA7_Pos (24U)
2213#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
2214#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
2215
2216/******************* Bit definition for CAN_RI0R register *******************/
2217#define CAN_RI0R_RTR_Pos (1U)
2218#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
2219#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
2220#define CAN_RI0R_IDE_Pos (2U)
2221#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
2222#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
2223#define CAN_RI0R_EXID_Pos (3U)
2224#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
2225#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
2226#define CAN_RI0R_STID_Pos (21U)
2227#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
2228#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2229
2230/******************* Bit definition for CAN_RDT0R register ******************/
2231#define CAN_RDT0R_DLC_Pos (0U)
2232#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
2233#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
2234#define CAN_RDT0R_FMI_Pos (8U)
2235#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
2236#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
2237#define CAN_RDT0R_TIME_Pos (16U)
2238#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2239#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
2240
2241/******************* Bit definition for CAN_RDL0R register ******************/
2242#define CAN_RDL0R_DATA0_Pos (0U)
2243#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
2244#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
2245#define CAN_RDL0R_DATA1_Pos (8U)
2246#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2247#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
2248#define CAN_RDL0R_DATA2_Pos (16U)
2249#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2250#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
2251#define CAN_RDL0R_DATA3_Pos (24U)
2252#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
2253#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
2254
2255/******************* Bit definition for CAN_RDH0R register ******************/
2256#define CAN_RDH0R_DATA4_Pos (0U)
2257#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
2258#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
2259#define CAN_RDH0R_DATA5_Pos (8U)
2260#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2261#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
2262#define CAN_RDH0R_DATA6_Pos (16U)
2263#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2264#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
2265#define CAN_RDH0R_DATA7_Pos (24U)
2266#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
2267#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
2268
2269/******************* Bit definition for CAN_RI1R register *******************/
2270#define CAN_RI1R_RTR_Pos (1U)
2271#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
2272#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
2273#define CAN_RI1R_IDE_Pos (2U)
2274#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
2275#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
2276#define CAN_RI1R_EXID_Pos (3U)
2277#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
2278#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
2279#define CAN_RI1R_STID_Pos (21U)
2280#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
2281#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2282
2283/******************* Bit definition for CAN_RDT1R register ******************/
2284#define CAN_RDT1R_DLC_Pos (0U)
2285#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
2286#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
2287#define CAN_RDT1R_FMI_Pos (8U)
2288#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
2289#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
2290#define CAN_RDT1R_TIME_Pos (16U)
2291#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2292#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
2293
2294/******************* Bit definition for CAN_RDL1R register ******************/
2295#define CAN_RDL1R_DATA0_Pos (0U)
2296#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
2297#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
2298#define CAN_RDL1R_DATA1_Pos (8U)
2299#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2300#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
2301#define CAN_RDL1R_DATA2_Pos (16U)
2302#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2303#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
2304#define CAN_RDL1R_DATA3_Pos (24U)
2305#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
2306#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
2307
2308/******************* Bit definition for CAN_RDH1R register ******************/
2309#define CAN_RDH1R_DATA4_Pos (0U)
2310#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
2311#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
2312#define CAN_RDH1R_DATA5_Pos (8U)
2313#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2314#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
2315#define CAN_RDH1R_DATA6_Pos (16U)
2316#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2317#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
2318#define CAN_RDH1R_DATA7_Pos (24U)
2319#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
2320#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
2321
2322/*!<CAN filter registers */
2323/******************* Bit definition for CAN_FMR register ********************/
2324#define CAN_FMR_FINIT_Pos (0U)
2325#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
2326#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
2327#define CAN_FMR_CAN2SB_Pos (8U)
2328#define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
2329#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
2330
2331/************* Bit definition for CAN_FM1R register *******************/
2332#define CAN_FM1R_FBM_Pos (0U)
2333#define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
2334#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
2335#define CAN_FM1R_FBM0_Pos (0U)
2336#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
2337#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
2338#define CAN_FM1R_FBM1_Pos (1U)
2339#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
2340#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
2341#define CAN_FM1R_FBM2_Pos (2U)
2342#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
2343#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
2344#define CAN_FM1R_FBM3_Pos (3U)
2345#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
2346#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
2347#define CAN_FM1R_FBM4_Pos (4U)
2348#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
2349#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
2350#define CAN_FM1R_FBM5_Pos (5U)
2351#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
2352#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
2353#define CAN_FM1R_FBM6_Pos (6U)
2354#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
2355#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
2356#define CAN_FM1R_FBM7_Pos (7U)
2357#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
2358#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
2359#define CAN_FM1R_FBM8_Pos (8U)
2360#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
2361#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
2362#define CAN_FM1R_FBM9_Pos (9U)
2363#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
2364#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
2365#define CAN_FM1R_FBM10_Pos (10U)
2366#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
2367#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
2368#define CAN_FM1R_FBM11_Pos (11U)
2369#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
2370#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
2371#define CAN_FM1R_FBM12_Pos (12U)
2372#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
2373#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
2374#define CAN_FM1R_FBM13_Pos (13U)
2375#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
2376#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
2377#define CAN_FM1R_FBM14_Pos (14U)
2378#define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
2379#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
2380#define CAN_FM1R_FBM15_Pos (15U)
2381#define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
2382#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
2383#define CAN_FM1R_FBM16_Pos (16U)
2384#define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
2385#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
2386#define CAN_FM1R_FBM17_Pos (17U)
2387#define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
2388#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
2389#define CAN_FM1R_FBM18_Pos (18U)
2390#define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
2391#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
2392#define CAN_FM1R_FBM19_Pos (19U)
2393#define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
2394#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
2395#define CAN_FM1R_FBM20_Pos (20U)
2396#define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
2397#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
2398#define CAN_FM1R_FBM21_Pos (21U)
2399#define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
2400#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
2401#define CAN_FM1R_FBM22_Pos (22U)
2402#define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
2403#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
2404#define CAN_FM1R_FBM23_Pos (23U)
2405#define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
2406#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
2407#define CAN_FM1R_FBM24_Pos (24U)
2408#define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
2409#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
2410#define CAN_FM1R_FBM25_Pos (25U)
2411#define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
2412#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
2413#define CAN_FM1R_FBM26_Pos (26U)
2414#define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
2415#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
2416#define CAN_FM1R_FBM27_Pos (27U)
2417#define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
2418#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
2419
2420/******************* Bit definition for CAN_FS1R register *******************/
2421#define CAN_FS1R_FSC_Pos (0U)
2422#define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
2423#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
2424#define CAN_FS1R_FSC0_Pos (0U)
2425#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
2426#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
2427#define CAN_FS1R_FSC1_Pos (1U)
2428#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
2429#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
2430#define CAN_FS1R_FSC2_Pos (2U)
2431#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
2432#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
2433#define CAN_FS1R_FSC3_Pos (3U)
2434#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
2435#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
2436#define CAN_FS1R_FSC4_Pos (4U)
2437#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
2438#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
2439#define CAN_FS1R_FSC5_Pos (5U)
2440#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
2441#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
2442#define CAN_FS1R_FSC6_Pos (6U)
2443#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
2444#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
2445#define CAN_FS1R_FSC7_Pos (7U)
2446#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
2447#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
2448#define CAN_FS1R_FSC8_Pos (8U)
2449#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
2450#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
2451#define CAN_FS1R_FSC9_Pos (9U)
2452#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
2453#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
2454#define CAN_FS1R_FSC10_Pos (10U)
2455#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
2456#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
2457#define CAN_FS1R_FSC11_Pos (11U)
2458#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
2459#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
2460#define CAN_FS1R_FSC12_Pos (12U)
2461#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
2462#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
2463#define CAN_FS1R_FSC13_Pos (13U)
2464#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
2465#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
2466#define CAN_FS1R_FSC14_Pos (14U)
2467#define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
2468#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
2469#define CAN_FS1R_FSC15_Pos (15U)
2470#define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
2471#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
2472#define CAN_FS1R_FSC16_Pos (16U)
2473#define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
2474#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
2475#define CAN_FS1R_FSC17_Pos (17U)
2476#define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
2477#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
2478#define CAN_FS1R_FSC18_Pos (18U)
2479#define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
2480#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
2481#define CAN_FS1R_FSC19_Pos (19U)
2482#define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
2483#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
2484#define CAN_FS1R_FSC20_Pos (20U)
2485#define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
2486#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
2487#define CAN_FS1R_FSC21_Pos (21U)
2488#define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
2489#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
2490#define CAN_FS1R_FSC22_Pos (22U)
2491#define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
2492#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
2493#define CAN_FS1R_FSC23_Pos (23U)
2494#define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
2495#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
2496#define CAN_FS1R_FSC24_Pos (24U)
2497#define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
2498#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
2499#define CAN_FS1R_FSC25_Pos (25U)
2500#define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
2501#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
2502#define CAN_FS1R_FSC26_Pos (26U)
2503#define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
2504#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
2505#define CAN_FS1R_FSC27_Pos (27U)
2506#define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
2507#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
2508
2509/****************** Bit definition for CAN_FFA1R register *******************/
2510#define CAN_FFA1R_FFA_Pos (0U)
2511#define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
2512#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
2513#define CAN_FFA1R_FFA0_Pos (0U)
2514#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
2515#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
2516#define CAN_FFA1R_FFA1_Pos (1U)
2517#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
2518#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
2519#define CAN_FFA1R_FFA2_Pos (2U)
2520#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
2521#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
2522#define CAN_FFA1R_FFA3_Pos (3U)
2523#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
2524#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
2525#define CAN_FFA1R_FFA4_Pos (4U)
2526#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
2527#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
2528#define CAN_FFA1R_FFA5_Pos (5U)
2529#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
2530#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
2531#define CAN_FFA1R_FFA6_Pos (6U)
2532#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
2533#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
2534#define CAN_FFA1R_FFA7_Pos (7U)
2535#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
2536#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
2537#define CAN_FFA1R_FFA8_Pos (8U)
2538#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
2539#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
2540#define CAN_FFA1R_FFA9_Pos (9U)
2541#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
2542#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
2543#define CAN_FFA1R_FFA10_Pos (10U)
2544#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
2545#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
2546#define CAN_FFA1R_FFA11_Pos (11U)
2547#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
2548#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
2549#define CAN_FFA1R_FFA12_Pos (12U)
2550#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
2551#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
2552#define CAN_FFA1R_FFA13_Pos (13U)
2553#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
2554#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
2555#define CAN_FFA1R_FFA14_Pos (14U)
2556#define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
2557#define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
2558#define CAN_FFA1R_FFA15_Pos (15U)
2559#define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
2560#define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
2561#define CAN_FFA1R_FFA16_Pos (16U)
2562#define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
2563#define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
2564#define CAN_FFA1R_FFA17_Pos (17U)
2565#define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
2566#define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
2567#define CAN_FFA1R_FFA18_Pos (18U)
2568#define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
2569#define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
2570#define CAN_FFA1R_FFA19_Pos (19U)
2571#define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
2572#define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
2573#define CAN_FFA1R_FFA20_Pos (20U)
2574#define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
2575#define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
2576#define CAN_FFA1R_FFA21_Pos (21U)
2577#define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
2578#define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
2579#define CAN_FFA1R_FFA22_Pos (22U)
2580#define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
2581#define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
2582#define CAN_FFA1R_FFA23_Pos (23U)
2583#define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
2584#define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
2585#define CAN_FFA1R_FFA24_Pos (24U)
2586#define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
2587#define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
2588#define CAN_FFA1R_FFA25_Pos (25U)
2589#define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
2590#define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
2591#define CAN_FFA1R_FFA26_Pos (26U)
2592#define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
2593#define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
2594#define CAN_FFA1R_FFA27_Pos (27U)
2595#define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
2596#define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
2597
2598/******************* Bit definition for CAN_FA1R register *******************/
2599#define CAN_FA1R_FACT_Pos (0U)
2600#define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
2601#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
2602#define CAN_FA1R_FACT0_Pos (0U)
2603#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
2604#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
2605#define CAN_FA1R_FACT1_Pos (1U)
2606#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
2607#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
2608#define CAN_FA1R_FACT2_Pos (2U)
2609#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
2610#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
2611#define CAN_FA1R_FACT3_Pos (3U)
2612#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
2613#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
2614#define CAN_FA1R_FACT4_Pos (4U)
2615#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
2616#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
2617#define CAN_FA1R_FACT5_Pos (5U)
2618#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
2619#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
2620#define CAN_FA1R_FACT6_Pos (6U)
2621#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
2622#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
2623#define CAN_FA1R_FACT7_Pos (7U)
2624#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
2625#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
2626#define CAN_FA1R_FACT8_Pos (8U)
2627#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
2628#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
2629#define CAN_FA1R_FACT9_Pos (9U)
2630#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
2631#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
2632#define CAN_FA1R_FACT10_Pos (10U)
2633#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
2634#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
2635#define CAN_FA1R_FACT11_Pos (11U)
2636#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
2637#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
2638#define CAN_FA1R_FACT12_Pos (12U)
2639#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
2640#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
2641#define CAN_FA1R_FACT13_Pos (13U)
2642#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
2643#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
2644#define CAN_FA1R_FACT14_Pos (14U)
2645#define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
2646#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
2647#define CAN_FA1R_FACT15_Pos (15U)
2648#define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
2649#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
2650#define CAN_FA1R_FACT16_Pos (16U)
2651#define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
2652#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
2653#define CAN_FA1R_FACT17_Pos (17U)
2654#define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
2655#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
2656#define CAN_FA1R_FACT18_Pos (18U)
2657#define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
2658#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
2659#define CAN_FA1R_FACT19_Pos (19U)
2660#define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
2661#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
2662#define CAN_FA1R_FACT20_Pos (20U)
2663#define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
2664#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
2665#define CAN_FA1R_FACT21_Pos (21U)
2666#define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
2667#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
2668#define CAN_FA1R_FACT22_Pos (22U)
2669#define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
2670#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
2671#define CAN_FA1R_FACT23_Pos (23U)
2672#define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
2673#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
2674#define CAN_FA1R_FACT24_Pos (24U)
2675#define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
2676#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
2677#define CAN_FA1R_FACT25_Pos (25U)
2678#define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
2679#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
2680#define CAN_FA1R_FACT26_Pos (26U)
2681#define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
2682#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
2683#define CAN_FA1R_FACT27_Pos (27U)
2684#define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
2685#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
2686
2687/******************* Bit definition for CAN_F0R1 register *******************/
2688#define CAN_F0R1_FB0_Pos (0U)
2689#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
2690#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
2691#define CAN_F0R1_FB1_Pos (1U)
2692#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
2693#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
2694#define CAN_F0R1_FB2_Pos (2U)
2695#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
2696#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
2697#define CAN_F0R1_FB3_Pos (3U)
2698#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
2699#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
2700#define CAN_F0R1_FB4_Pos (4U)
2701#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
2702#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
2703#define CAN_F0R1_FB5_Pos (5U)
2704#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
2705#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
2706#define CAN_F0R1_FB6_Pos (6U)
2707#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
2708#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
2709#define CAN_F0R1_FB7_Pos (7U)
2710#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
2711#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
2712#define CAN_F0R1_FB8_Pos (8U)
2713#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
2714#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
2715#define CAN_F0R1_FB9_Pos (9U)
2716#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
2717#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
2718#define CAN_F0R1_FB10_Pos (10U)
2719#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
2720#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
2721#define CAN_F0R1_FB11_Pos (11U)
2722#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
2723#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
2724#define CAN_F0R1_FB12_Pos (12U)
2725#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
2726#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
2727#define CAN_F0R1_FB13_Pos (13U)
2728#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
2729#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
2730#define CAN_F0R1_FB14_Pos (14U)
2731#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
2732#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
2733#define CAN_F0R1_FB15_Pos (15U)
2734#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
2735#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
2736#define CAN_F0R1_FB16_Pos (16U)
2737#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
2738#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
2739#define CAN_F0R1_FB17_Pos (17U)
2740#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
2741#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
2742#define CAN_F0R1_FB18_Pos (18U)
2743#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
2744#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
2745#define CAN_F0R1_FB19_Pos (19U)
2746#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
2747#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
2748#define CAN_F0R1_FB20_Pos (20U)
2749#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
2750#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
2751#define CAN_F0R1_FB21_Pos (21U)
2752#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
2753#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
2754#define CAN_F0R1_FB22_Pos (22U)
2755#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
2756#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
2757#define CAN_F0R1_FB23_Pos (23U)
2758#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
2759#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
2760#define CAN_F0R1_FB24_Pos (24U)
2761#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
2762#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
2763#define CAN_F0R1_FB25_Pos (25U)
2764#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
2765#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
2766#define CAN_F0R1_FB26_Pos (26U)
2767#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
2768#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
2769#define CAN_F0R1_FB27_Pos (27U)
2770#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
2771#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
2772#define CAN_F0R1_FB28_Pos (28U)
2773#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
2774#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
2775#define CAN_F0R1_FB29_Pos (29U)
2776#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
2777#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
2778#define CAN_F0R1_FB30_Pos (30U)
2779#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
2780#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
2781#define CAN_F0R1_FB31_Pos (31U)
2782#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
2783#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
2784
2785/******************* Bit definition for CAN_F1R1 register *******************/
2786#define CAN_F1R1_FB0_Pos (0U)
2787#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
2788#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
2789#define CAN_F1R1_FB1_Pos (1U)
2790#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
2791#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
2792#define CAN_F1R1_FB2_Pos (2U)
2793#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
2794#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
2795#define CAN_F1R1_FB3_Pos (3U)
2796#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
2797#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
2798#define CAN_F1R1_FB4_Pos (4U)
2799#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
2800#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
2801#define CAN_F1R1_FB5_Pos (5U)
2802#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
2803#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
2804#define CAN_F1R1_FB6_Pos (6U)
2805#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
2806#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
2807#define CAN_F1R1_FB7_Pos (7U)
2808#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
2809#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
2810#define CAN_F1R1_FB8_Pos (8U)
2811#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
2812#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
2813#define CAN_F1R1_FB9_Pos (9U)
2814#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
2815#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
2816#define CAN_F1R1_FB10_Pos (10U)
2817#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
2818#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
2819#define CAN_F1R1_FB11_Pos (11U)
2820#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
2821#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
2822#define CAN_F1R1_FB12_Pos (12U)
2823#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
2824#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
2825#define CAN_F1R1_FB13_Pos (13U)
2826#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
2827#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
2828#define CAN_F1R1_FB14_Pos (14U)
2829#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
2830#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
2831#define CAN_F1R1_FB15_Pos (15U)
2832#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
2833#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
2834#define CAN_F1R1_FB16_Pos (16U)
2835#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
2836#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
2837#define CAN_F1R1_FB17_Pos (17U)
2838#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
2839#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
2840#define CAN_F1R1_FB18_Pos (18U)
2841#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
2842#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
2843#define CAN_F1R1_FB19_Pos (19U)
2844#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
2845#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
2846#define CAN_F1R1_FB20_Pos (20U)
2847#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
2848#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
2849#define CAN_F1R1_FB21_Pos (21U)
2850#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
2851#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
2852#define CAN_F1R1_FB22_Pos (22U)
2853#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
2854#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
2855#define CAN_F1R1_FB23_Pos (23U)
2856#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
2857#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
2858#define CAN_F1R1_FB24_Pos (24U)
2859#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
2860#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
2861#define CAN_F1R1_FB25_Pos (25U)
2862#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
2863#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
2864#define CAN_F1R1_FB26_Pos (26U)
2865#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
2866#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
2867#define CAN_F1R1_FB27_Pos (27U)
2868#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
2869#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
2870#define CAN_F1R1_FB28_Pos (28U)
2871#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
2872#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
2873#define CAN_F1R1_FB29_Pos (29U)
2874#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
2875#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
2876#define CAN_F1R1_FB30_Pos (30U)
2877#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
2878#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
2879#define CAN_F1R1_FB31_Pos (31U)
2880#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
2881#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
2882
2883/******************* Bit definition for CAN_F2R1 register *******************/
2884#define CAN_F2R1_FB0_Pos (0U)
2885#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
2886#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
2887#define CAN_F2R1_FB1_Pos (1U)
2888#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
2889#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
2890#define CAN_F2R1_FB2_Pos (2U)
2891#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
2892#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
2893#define CAN_F2R1_FB3_Pos (3U)
2894#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
2895#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
2896#define CAN_F2R1_FB4_Pos (4U)
2897#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
2898#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
2899#define CAN_F2R1_FB5_Pos (5U)
2900#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
2901#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
2902#define CAN_F2R1_FB6_Pos (6U)
2903#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
2904#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
2905#define CAN_F2R1_FB7_Pos (7U)
2906#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
2907#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
2908#define CAN_F2R1_FB8_Pos (8U)
2909#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
2910#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
2911#define CAN_F2R1_FB9_Pos (9U)
2912#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
2913#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
2914#define CAN_F2R1_FB10_Pos (10U)
2915#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
2916#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
2917#define CAN_F2R1_FB11_Pos (11U)
2918#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
2919#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
2920#define CAN_F2R1_FB12_Pos (12U)
2921#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
2922#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
2923#define CAN_F2R1_FB13_Pos (13U)
2924#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
2925#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
2926#define CAN_F2R1_FB14_Pos (14U)
2927#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
2928#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
2929#define CAN_F2R1_FB15_Pos (15U)
2930#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
2931#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
2932#define CAN_F2R1_FB16_Pos (16U)
2933#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
2934#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
2935#define CAN_F2R1_FB17_Pos (17U)
2936#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
2937#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
2938#define CAN_F2R1_FB18_Pos (18U)
2939#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
2940#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
2941#define CAN_F2R1_FB19_Pos (19U)
2942#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
2943#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
2944#define CAN_F2R1_FB20_Pos (20U)
2945#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
2946#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
2947#define CAN_F2R1_FB21_Pos (21U)
2948#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
2949#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
2950#define CAN_F2R1_FB22_Pos (22U)
2951#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
2952#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
2953#define CAN_F2R1_FB23_Pos (23U)
2954#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
2955#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
2956#define CAN_F2R1_FB24_Pos (24U)
2957#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
2958#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
2959#define CAN_F2R1_FB25_Pos (25U)
2960#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
2961#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
2962#define CAN_F2R1_FB26_Pos (26U)
2963#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
2964#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
2965#define CAN_F2R1_FB27_Pos (27U)
2966#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
2967#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
2968#define CAN_F2R1_FB28_Pos (28U)
2969#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
2970#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
2971#define CAN_F2R1_FB29_Pos (29U)
2972#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
2973#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
2974#define CAN_F2R1_FB30_Pos (30U)
2975#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
2976#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
2977#define CAN_F2R1_FB31_Pos (31U)
2978#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
2979#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
2980
2981/******************* Bit definition for CAN_F3R1 register *******************/
2982#define CAN_F3R1_FB0_Pos (0U)
2983#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
2984#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
2985#define CAN_F3R1_FB1_Pos (1U)
2986#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
2987#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
2988#define CAN_F3R1_FB2_Pos (2U)
2989#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
2990#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
2991#define CAN_F3R1_FB3_Pos (3U)
2992#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
2993#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
2994#define CAN_F3R1_FB4_Pos (4U)
2995#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
2996#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
2997#define CAN_F3R1_FB5_Pos (5U)
2998#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
2999#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
3000#define CAN_F3R1_FB6_Pos (6U)
3001#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
3002#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
3003#define CAN_F3R1_FB7_Pos (7U)
3004#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
3005#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
3006#define CAN_F3R1_FB8_Pos (8U)
3007#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
3008#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
3009#define CAN_F3R1_FB9_Pos (9U)
3010#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
3011#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
3012#define CAN_F3R1_FB10_Pos (10U)
3013#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
3014#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
3015#define CAN_F3R1_FB11_Pos (11U)
3016#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
3017#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
3018#define CAN_F3R1_FB12_Pos (12U)
3019#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
3020#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
3021#define CAN_F3R1_FB13_Pos (13U)
3022#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
3023#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
3024#define CAN_F3R1_FB14_Pos (14U)
3025#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
3026#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
3027#define CAN_F3R1_FB15_Pos (15U)
3028#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
3029#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
3030#define CAN_F3R1_FB16_Pos (16U)
3031#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
3032#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
3033#define CAN_F3R1_FB17_Pos (17U)
3034#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
3035#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
3036#define CAN_F3R1_FB18_Pos (18U)
3037#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
3038#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
3039#define CAN_F3R1_FB19_Pos (19U)
3040#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
3041#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
3042#define CAN_F3R1_FB20_Pos (20U)
3043#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
3044#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
3045#define CAN_F3R1_FB21_Pos (21U)
3046#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
3047#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
3048#define CAN_F3R1_FB22_Pos (22U)
3049#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
3050#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
3051#define CAN_F3R1_FB23_Pos (23U)
3052#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
3053#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
3054#define CAN_F3R1_FB24_Pos (24U)
3055#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
3056#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
3057#define CAN_F3R1_FB25_Pos (25U)
3058#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
3059#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
3060#define CAN_F3R1_FB26_Pos (26U)
3061#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
3062#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
3063#define CAN_F3R1_FB27_Pos (27U)
3064#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
3065#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
3066#define CAN_F3R1_FB28_Pos (28U)
3067#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
3068#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
3069#define CAN_F3R1_FB29_Pos (29U)
3070#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
3071#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
3072#define CAN_F3R1_FB30_Pos (30U)
3073#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
3074#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
3075#define CAN_F3R1_FB31_Pos (31U)
3076#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
3077#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
3078
3079/******************* Bit definition for CAN_F4R1 register *******************/
3080#define CAN_F4R1_FB0_Pos (0U)
3081#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
3082#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
3083#define CAN_F4R1_FB1_Pos (1U)
3084#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
3085#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
3086#define CAN_F4R1_FB2_Pos (2U)
3087#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
3088#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
3089#define CAN_F4R1_FB3_Pos (3U)
3090#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
3091#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
3092#define CAN_F4R1_FB4_Pos (4U)
3093#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
3094#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
3095#define CAN_F4R1_FB5_Pos (5U)
3096#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
3097#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
3098#define CAN_F4R1_FB6_Pos (6U)
3099#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
3100#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
3101#define CAN_F4R1_FB7_Pos (7U)
3102#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
3103#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
3104#define CAN_F4R1_FB8_Pos (8U)
3105#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
3106#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
3107#define CAN_F4R1_FB9_Pos (9U)
3108#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
3109#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
3110#define CAN_F4R1_FB10_Pos (10U)
3111#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
3112#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
3113#define CAN_F4R1_FB11_Pos (11U)
3114#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
3115#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
3116#define CAN_F4R1_FB12_Pos (12U)
3117#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
3118#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
3119#define CAN_F4R1_FB13_Pos (13U)
3120#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
3121#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
3122#define CAN_F4R1_FB14_Pos (14U)
3123#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
3124#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
3125#define CAN_F4R1_FB15_Pos (15U)
3126#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
3127#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
3128#define CAN_F4R1_FB16_Pos (16U)
3129#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
3130#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
3131#define CAN_F4R1_FB17_Pos (17U)
3132#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
3133#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
3134#define CAN_F4R1_FB18_Pos (18U)
3135#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
3136#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
3137#define CAN_F4R1_FB19_Pos (19U)
3138#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
3139#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
3140#define CAN_F4R1_FB20_Pos (20U)
3141#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
3142#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
3143#define CAN_F4R1_FB21_Pos (21U)
3144#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
3145#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
3146#define CAN_F4R1_FB22_Pos (22U)
3147#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
3148#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
3149#define CAN_F4R1_FB23_Pos (23U)
3150#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
3151#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
3152#define CAN_F4R1_FB24_Pos (24U)
3153#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
3154#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
3155#define CAN_F4R1_FB25_Pos (25U)
3156#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
3157#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
3158#define CAN_F4R1_FB26_Pos (26U)
3159#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
3160#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
3161#define CAN_F4R1_FB27_Pos (27U)
3162#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
3163#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
3164#define CAN_F4R1_FB28_Pos (28U)
3165#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
3166#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
3167#define CAN_F4R1_FB29_Pos (29U)
3168#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
3169#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
3170#define CAN_F4R1_FB30_Pos (30U)
3171#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
3172#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
3173#define CAN_F4R1_FB31_Pos (31U)
3174#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
3175#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
3176
3177/******************* Bit definition for CAN_F5R1 register *******************/
3178#define CAN_F5R1_FB0_Pos (0U)
3179#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
3180#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
3181#define CAN_F5R1_FB1_Pos (1U)
3182#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
3183#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
3184#define CAN_F5R1_FB2_Pos (2U)
3185#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
3186#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
3187#define CAN_F5R1_FB3_Pos (3U)
3188#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
3189#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
3190#define CAN_F5R1_FB4_Pos (4U)
3191#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
3192#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
3193#define CAN_F5R1_FB5_Pos (5U)
3194#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
3195#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
3196#define CAN_F5R1_FB6_Pos (6U)
3197#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
3198#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
3199#define CAN_F5R1_FB7_Pos (7U)
3200#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
3201#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
3202#define CAN_F5R1_FB8_Pos (8U)
3203#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
3204#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
3205#define CAN_F5R1_FB9_Pos (9U)
3206#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
3207#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
3208#define CAN_F5R1_FB10_Pos (10U)
3209#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
3210#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
3211#define CAN_F5R1_FB11_Pos (11U)
3212#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
3213#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
3214#define CAN_F5R1_FB12_Pos (12U)
3215#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
3216#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
3217#define CAN_F5R1_FB13_Pos (13U)
3218#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
3219#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
3220#define CAN_F5R1_FB14_Pos (14U)
3221#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
3222#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
3223#define CAN_F5R1_FB15_Pos (15U)
3224#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
3225#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
3226#define CAN_F5R1_FB16_Pos (16U)
3227#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
3228#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
3229#define CAN_F5R1_FB17_Pos (17U)
3230#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
3231#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
3232#define CAN_F5R1_FB18_Pos (18U)
3233#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
3234#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
3235#define CAN_F5R1_FB19_Pos (19U)
3236#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
3237#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
3238#define CAN_F5R1_FB20_Pos (20U)
3239#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
3240#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
3241#define CAN_F5R1_FB21_Pos (21U)
3242#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
3243#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
3244#define CAN_F5R1_FB22_Pos (22U)
3245#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
3246#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
3247#define CAN_F5R1_FB23_Pos (23U)
3248#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
3249#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
3250#define CAN_F5R1_FB24_Pos (24U)
3251#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
3252#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
3253#define CAN_F5R1_FB25_Pos (25U)
3254#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
3255#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
3256#define CAN_F5R1_FB26_Pos (26U)
3257#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
3258#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
3259#define CAN_F5R1_FB27_Pos (27U)
3260#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
3261#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
3262#define CAN_F5R1_FB28_Pos (28U)
3263#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
3264#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
3265#define CAN_F5R1_FB29_Pos (29U)
3266#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
3267#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
3268#define CAN_F5R1_FB30_Pos (30U)
3269#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
3270#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
3271#define CAN_F5R1_FB31_Pos (31U)
3272#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
3273#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
3274
3275/******************* Bit definition for CAN_F6R1 register *******************/
3276#define CAN_F6R1_FB0_Pos (0U)
3277#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
3278#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
3279#define CAN_F6R1_FB1_Pos (1U)
3280#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
3281#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
3282#define CAN_F6R1_FB2_Pos (2U)
3283#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
3284#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
3285#define CAN_F6R1_FB3_Pos (3U)
3286#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
3287#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
3288#define CAN_F6R1_FB4_Pos (4U)
3289#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
3290#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
3291#define CAN_F6R1_FB5_Pos (5U)
3292#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
3293#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
3294#define CAN_F6R1_FB6_Pos (6U)
3295#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
3296#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
3297#define CAN_F6R1_FB7_Pos (7U)
3298#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
3299#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
3300#define CAN_F6R1_FB8_Pos (8U)
3301#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
3302#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
3303#define CAN_F6R1_FB9_Pos (9U)
3304#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
3305#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
3306#define CAN_F6R1_FB10_Pos (10U)
3307#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
3308#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
3309#define CAN_F6R1_FB11_Pos (11U)
3310#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
3311#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
3312#define CAN_F6R1_FB12_Pos (12U)
3313#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
3314#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
3315#define CAN_F6R1_FB13_Pos (13U)
3316#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
3317#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
3318#define CAN_F6R1_FB14_Pos (14U)
3319#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
3320#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
3321#define CAN_F6R1_FB15_Pos (15U)
3322#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
3323#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
3324#define CAN_F6R1_FB16_Pos (16U)
3325#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
3326#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
3327#define CAN_F6R1_FB17_Pos (17U)
3328#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
3329#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
3330#define CAN_F6R1_FB18_Pos (18U)
3331#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
3332#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
3333#define CAN_F6R1_FB19_Pos (19U)
3334#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
3335#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
3336#define CAN_F6R1_FB20_Pos (20U)
3337#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
3338#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
3339#define CAN_F6R1_FB21_Pos (21U)
3340#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
3341#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
3342#define CAN_F6R1_FB22_Pos (22U)
3343#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
3344#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
3345#define CAN_F6R1_FB23_Pos (23U)
3346#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
3347#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
3348#define CAN_F6R1_FB24_Pos (24U)
3349#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
3350#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
3351#define CAN_F6R1_FB25_Pos (25U)
3352#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
3353#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
3354#define CAN_F6R1_FB26_Pos (26U)
3355#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
3356#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
3357#define CAN_F6R1_FB27_Pos (27U)
3358#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
3359#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
3360#define CAN_F6R1_FB28_Pos (28U)
3361#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
3362#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
3363#define CAN_F6R1_FB29_Pos (29U)
3364#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
3365#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
3366#define CAN_F6R1_FB30_Pos (30U)
3367#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
3368#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
3369#define CAN_F6R1_FB31_Pos (31U)
3370#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
3371#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
3372
3373/******************* Bit definition for CAN_F7R1 register *******************/
3374#define CAN_F7R1_FB0_Pos (0U)
3375#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
3376#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
3377#define CAN_F7R1_FB1_Pos (1U)
3378#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
3379#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
3380#define CAN_F7R1_FB2_Pos (2U)
3381#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
3382#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
3383#define CAN_F7R1_FB3_Pos (3U)
3384#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
3385#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
3386#define CAN_F7R1_FB4_Pos (4U)
3387#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
3388#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
3389#define CAN_F7R1_FB5_Pos (5U)
3390#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
3391#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
3392#define CAN_F7R1_FB6_Pos (6U)
3393#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
3394#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
3395#define CAN_F7R1_FB7_Pos (7U)
3396#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
3397#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
3398#define CAN_F7R1_FB8_Pos (8U)
3399#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
3400#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
3401#define CAN_F7R1_FB9_Pos (9U)
3402#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
3403#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
3404#define CAN_F7R1_FB10_Pos (10U)
3405#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
3406#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
3407#define CAN_F7R1_FB11_Pos (11U)
3408#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
3409#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
3410#define CAN_F7R1_FB12_Pos (12U)
3411#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
3412#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
3413#define CAN_F7R1_FB13_Pos (13U)
3414#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
3415#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
3416#define CAN_F7R1_FB14_Pos (14U)
3417#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
3418#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
3419#define CAN_F7R1_FB15_Pos (15U)
3420#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
3421#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
3422#define CAN_F7R1_FB16_Pos (16U)
3423#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
3424#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
3425#define CAN_F7R1_FB17_Pos (17U)
3426#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
3427#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
3428#define CAN_F7R1_FB18_Pos (18U)
3429#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
3430#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
3431#define CAN_F7R1_FB19_Pos (19U)
3432#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
3433#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
3434#define CAN_F7R1_FB20_Pos (20U)
3435#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
3436#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
3437#define CAN_F7R1_FB21_Pos (21U)
3438#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
3439#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
3440#define CAN_F7R1_FB22_Pos (22U)
3441#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
3442#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
3443#define CAN_F7R1_FB23_Pos (23U)
3444#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
3445#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
3446#define CAN_F7R1_FB24_Pos (24U)
3447#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
3448#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
3449#define CAN_F7R1_FB25_Pos (25U)
3450#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
3451#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
3452#define CAN_F7R1_FB26_Pos (26U)
3453#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
3454#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
3455#define CAN_F7R1_FB27_Pos (27U)
3456#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
3457#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
3458#define CAN_F7R1_FB28_Pos (28U)
3459#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
3460#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
3461#define CAN_F7R1_FB29_Pos (29U)
3462#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
3463#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
3464#define CAN_F7R1_FB30_Pos (30U)
3465#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
3466#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
3467#define CAN_F7R1_FB31_Pos (31U)
3468#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
3469#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
3470
3471/******************* Bit definition for CAN_F8R1 register *******************/
3472#define CAN_F8R1_FB0_Pos (0U)
3473#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
3474#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
3475#define CAN_F8R1_FB1_Pos (1U)
3476#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
3477#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
3478#define CAN_F8R1_FB2_Pos (2U)
3479#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
3480#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
3481#define CAN_F8R1_FB3_Pos (3U)
3482#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
3483#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
3484#define CAN_F8R1_FB4_Pos (4U)
3485#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
3486#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
3487#define CAN_F8R1_FB5_Pos (5U)
3488#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
3489#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
3490#define CAN_F8R1_FB6_Pos (6U)
3491#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
3492#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
3493#define CAN_F8R1_FB7_Pos (7U)
3494#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
3495#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
3496#define CAN_F8R1_FB8_Pos (8U)
3497#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
3498#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
3499#define CAN_F8R1_FB9_Pos (9U)
3500#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
3501#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
3502#define CAN_F8R1_FB10_Pos (10U)
3503#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
3504#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
3505#define CAN_F8R1_FB11_Pos (11U)
3506#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
3507#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
3508#define CAN_F8R1_FB12_Pos (12U)
3509#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
3510#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
3511#define CAN_F8R1_FB13_Pos (13U)
3512#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
3513#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
3514#define CAN_F8R1_FB14_Pos (14U)
3515#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
3516#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
3517#define CAN_F8R1_FB15_Pos (15U)
3518#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
3519#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
3520#define CAN_F8R1_FB16_Pos (16U)
3521#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
3522#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
3523#define CAN_F8R1_FB17_Pos (17U)
3524#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
3525#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
3526#define CAN_F8R1_FB18_Pos (18U)
3527#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
3528#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
3529#define CAN_F8R1_FB19_Pos (19U)
3530#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
3531#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
3532#define CAN_F8R1_FB20_Pos (20U)
3533#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
3534#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
3535#define CAN_F8R1_FB21_Pos (21U)
3536#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
3537#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
3538#define CAN_F8R1_FB22_Pos (22U)
3539#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
3540#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
3541#define CAN_F8R1_FB23_Pos (23U)
3542#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
3543#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
3544#define CAN_F8R1_FB24_Pos (24U)
3545#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
3546#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
3547#define CAN_F8R1_FB25_Pos (25U)
3548#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
3549#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
3550#define CAN_F8R1_FB26_Pos (26U)
3551#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
3552#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
3553#define CAN_F8R1_FB27_Pos (27U)
3554#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
3555#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
3556#define CAN_F8R1_FB28_Pos (28U)
3557#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
3558#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
3559#define CAN_F8R1_FB29_Pos (29U)
3560#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
3561#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
3562#define CAN_F8R1_FB30_Pos (30U)
3563#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
3564#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
3565#define CAN_F8R1_FB31_Pos (31U)
3566#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
3567#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
3568
3569/******************* Bit definition for CAN_F9R1 register *******************/
3570#define CAN_F9R1_FB0_Pos (0U)
3571#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
3572#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
3573#define CAN_F9R1_FB1_Pos (1U)
3574#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
3575#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
3576#define CAN_F9R1_FB2_Pos (2U)
3577#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
3578#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
3579#define CAN_F9R1_FB3_Pos (3U)
3580#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
3581#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
3582#define CAN_F9R1_FB4_Pos (4U)
3583#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
3584#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
3585#define CAN_F9R1_FB5_Pos (5U)
3586#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
3587#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
3588#define CAN_F9R1_FB6_Pos (6U)
3589#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
3590#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
3591#define CAN_F9R1_FB7_Pos (7U)
3592#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
3593#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
3594#define CAN_F9R1_FB8_Pos (8U)
3595#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
3596#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
3597#define CAN_F9R1_FB9_Pos (9U)
3598#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
3599#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
3600#define CAN_F9R1_FB10_Pos (10U)
3601#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
3602#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
3603#define CAN_F9R1_FB11_Pos (11U)
3604#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
3605#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
3606#define CAN_F9R1_FB12_Pos (12U)
3607#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
3608#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
3609#define CAN_F9R1_FB13_Pos (13U)
3610#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
3611#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
3612#define CAN_F9R1_FB14_Pos (14U)
3613#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
3614#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
3615#define CAN_F9R1_FB15_Pos (15U)
3616#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
3617#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
3618#define CAN_F9R1_FB16_Pos (16U)
3619#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
3620#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
3621#define CAN_F9R1_FB17_Pos (17U)
3622#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
3623#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
3624#define CAN_F9R1_FB18_Pos (18U)
3625#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
3626#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
3627#define CAN_F9R1_FB19_Pos (19U)
3628#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
3629#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
3630#define CAN_F9R1_FB20_Pos (20U)
3631#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
3632#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
3633#define CAN_F9R1_FB21_Pos (21U)
3634#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
3635#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
3636#define CAN_F9R1_FB22_Pos (22U)
3637#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
3638#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
3639#define CAN_F9R1_FB23_Pos (23U)
3640#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
3641#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
3642#define CAN_F9R1_FB24_Pos (24U)
3643#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
3644#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
3645#define CAN_F9R1_FB25_Pos (25U)
3646#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
3647#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
3648#define CAN_F9R1_FB26_Pos (26U)
3649#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
3650#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
3651#define CAN_F9R1_FB27_Pos (27U)
3652#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
3653#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
3654#define CAN_F9R1_FB28_Pos (28U)
3655#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
3656#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
3657#define CAN_F9R1_FB29_Pos (29U)
3658#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
3659#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
3660#define CAN_F9R1_FB30_Pos (30U)
3661#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
3662#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
3663#define CAN_F9R1_FB31_Pos (31U)
3664#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
3665#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
3666
3667/******************* Bit definition for CAN_F10R1 register ******************/
3668#define CAN_F10R1_FB0_Pos (0U)
3669#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
3670#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
3671#define CAN_F10R1_FB1_Pos (1U)
3672#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
3673#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
3674#define CAN_F10R1_FB2_Pos (2U)
3675#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
3676#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
3677#define CAN_F10R1_FB3_Pos (3U)
3678#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
3679#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
3680#define CAN_F10R1_FB4_Pos (4U)
3681#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
3682#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
3683#define CAN_F10R1_FB5_Pos (5U)
3684#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
3685#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
3686#define CAN_F10R1_FB6_Pos (6U)
3687#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
3688#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
3689#define CAN_F10R1_FB7_Pos (7U)
3690#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
3691#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
3692#define CAN_F10R1_FB8_Pos (8U)
3693#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
3694#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
3695#define CAN_F10R1_FB9_Pos (9U)
3696#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
3697#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
3698#define CAN_F10R1_FB10_Pos (10U)
3699#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
3700#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
3701#define CAN_F10R1_FB11_Pos (11U)
3702#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
3703#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
3704#define CAN_F10R1_FB12_Pos (12U)
3705#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
3706#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
3707#define CAN_F10R1_FB13_Pos (13U)
3708#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
3709#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
3710#define CAN_F10R1_FB14_Pos (14U)
3711#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
3712#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
3713#define CAN_F10R1_FB15_Pos (15U)
3714#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
3715#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
3716#define CAN_F10R1_FB16_Pos (16U)
3717#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
3718#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
3719#define CAN_F10R1_FB17_Pos (17U)
3720#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
3721#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
3722#define CAN_F10R1_FB18_Pos (18U)
3723#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
3724#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
3725#define CAN_F10R1_FB19_Pos (19U)
3726#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
3727#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
3728#define CAN_F10R1_FB20_Pos (20U)
3729#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
3730#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
3731#define CAN_F10R1_FB21_Pos (21U)
3732#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
3733#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
3734#define CAN_F10R1_FB22_Pos (22U)
3735#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
3736#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
3737#define CAN_F10R1_FB23_Pos (23U)
3738#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
3739#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
3740#define CAN_F10R1_FB24_Pos (24U)
3741#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
3742#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
3743#define CAN_F10R1_FB25_Pos (25U)
3744#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
3745#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
3746#define CAN_F10R1_FB26_Pos (26U)
3747#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
3748#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
3749#define CAN_F10R1_FB27_Pos (27U)
3750#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
3751#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
3752#define CAN_F10R1_FB28_Pos (28U)
3753#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
3754#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
3755#define CAN_F10R1_FB29_Pos (29U)
3756#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
3757#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
3758#define CAN_F10R1_FB30_Pos (30U)
3759#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
3760#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
3761#define CAN_F10R1_FB31_Pos (31U)
3762#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
3763#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
3764
3765/******************* Bit definition for CAN_F11R1 register ******************/
3766#define CAN_F11R1_FB0_Pos (0U)
3767#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
3768#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
3769#define CAN_F11R1_FB1_Pos (1U)
3770#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
3771#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
3772#define CAN_F11R1_FB2_Pos (2U)
3773#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
3774#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
3775#define CAN_F11R1_FB3_Pos (3U)
3776#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
3777#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
3778#define CAN_F11R1_FB4_Pos (4U)
3779#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
3780#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
3781#define CAN_F11R1_FB5_Pos (5U)
3782#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
3783#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
3784#define CAN_F11R1_FB6_Pos (6U)
3785#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
3786#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
3787#define CAN_F11R1_FB7_Pos (7U)
3788#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
3789#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
3790#define CAN_F11R1_FB8_Pos (8U)
3791#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
3792#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
3793#define CAN_F11R1_FB9_Pos (9U)
3794#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
3795#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
3796#define CAN_F11R1_FB10_Pos (10U)
3797#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
3798#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
3799#define CAN_F11R1_FB11_Pos (11U)
3800#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
3801#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
3802#define CAN_F11R1_FB12_Pos (12U)
3803#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
3804#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
3805#define CAN_F11R1_FB13_Pos (13U)
3806#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
3807#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
3808#define CAN_F11R1_FB14_Pos (14U)
3809#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
3810#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
3811#define CAN_F11R1_FB15_Pos (15U)
3812#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
3813#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
3814#define CAN_F11R1_FB16_Pos (16U)
3815#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
3816#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
3817#define CAN_F11R1_FB17_Pos (17U)
3818#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
3819#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
3820#define CAN_F11R1_FB18_Pos (18U)
3821#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
3822#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
3823#define CAN_F11R1_FB19_Pos (19U)
3824#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
3825#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
3826#define CAN_F11R1_FB20_Pos (20U)
3827#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
3828#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
3829#define CAN_F11R1_FB21_Pos (21U)
3830#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
3831#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
3832#define CAN_F11R1_FB22_Pos (22U)
3833#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
3834#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
3835#define CAN_F11R1_FB23_Pos (23U)
3836#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
3837#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
3838#define CAN_F11R1_FB24_Pos (24U)
3839#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
3840#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
3841#define CAN_F11R1_FB25_Pos (25U)
3842#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
3843#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
3844#define CAN_F11R1_FB26_Pos (26U)
3845#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
3846#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
3847#define CAN_F11R1_FB27_Pos (27U)
3848#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
3849#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
3850#define CAN_F11R1_FB28_Pos (28U)
3851#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
3852#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
3853#define CAN_F11R1_FB29_Pos (29U)
3854#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
3855#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
3856#define CAN_F11R1_FB30_Pos (30U)
3857#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
3858#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
3859#define CAN_F11R1_FB31_Pos (31U)
3860#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
3861#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
3862
3863/******************* Bit definition for CAN_F12R1 register ******************/
3864#define CAN_F12R1_FB0_Pos (0U)
3865#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
3866#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
3867#define CAN_F12R1_FB1_Pos (1U)
3868#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
3869#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
3870#define CAN_F12R1_FB2_Pos (2U)
3871#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
3872#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
3873#define CAN_F12R1_FB3_Pos (3U)
3874#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
3875#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
3876#define CAN_F12R1_FB4_Pos (4U)
3877#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
3878#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
3879#define CAN_F12R1_FB5_Pos (5U)
3880#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
3881#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
3882#define CAN_F12R1_FB6_Pos (6U)
3883#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
3884#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
3885#define CAN_F12R1_FB7_Pos (7U)
3886#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
3887#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
3888#define CAN_F12R1_FB8_Pos (8U)
3889#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
3890#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
3891#define CAN_F12R1_FB9_Pos (9U)
3892#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
3893#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
3894#define CAN_F12R1_FB10_Pos (10U)
3895#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
3896#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
3897#define CAN_F12R1_FB11_Pos (11U)
3898#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
3899#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
3900#define CAN_F12R1_FB12_Pos (12U)
3901#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
3902#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
3903#define CAN_F12R1_FB13_Pos (13U)
3904#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
3905#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
3906#define CAN_F12R1_FB14_Pos (14U)
3907#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
3908#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
3909#define CAN_F12R1_FB15_Pos (15U)
3910#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
3911#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
3912#define CAN_F12R1_FB16_Pos (16U)
3913#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
3914#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
3915#define CAN_F12R1_FB17_Pos (17U)
3916#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
3917#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
3918#define CAN_F12R1_FB18_Pos (18U)
3919#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
3920#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
3921#define CAN_F12R1_FB19_Pos (19U)
3922#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
3923#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
3924#define CAN_F12R1_FB20_Pos (20U)
3925#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
3926#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
3927#define CAN_F12R1_FB21_Pos (21U)
3928#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
3929#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
3930#define CAN_F12R1_FB22_Pos (22U)
3931#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
3932#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
3933#define CAN_F12R1_FB23_Pos (23U)
3934#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
3935#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
3936#define CAN_F12R1_FB24_Pos (24U)
3937#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
3938#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
3939#define CAN_F12R1_FB25_Pos (25U)
3940#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
3941#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
3942#define CAN_F12R1_FB26_Pos (26U)
3943#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
3944#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
3945#define CAN_F12R1_FB27_Pos (27U)
3946#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
3947#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
3948#define CAN_F12R1_FB28_Pos (28U)
3949#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
3950#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
3951#define CAN_F12R1_FB29_Pos (29U)
3952#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
3953#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
3954#define CAN_F12R1_FB30_Pos (30U)
3955#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
3956#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
3957#define CAN_F12R1_FB31_Pos (31U)
3958#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
3959#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
3960
3961/******************* Bit definition for CAN_F13R1 register ******************/
3962#define CAN_F13R1_FB0_Pos (0U)
3963#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
3964#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
3965#define CAN_F13R1_FB1_Pos (1U)
3966#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
3967#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
3968#define CAN_F13R1_FB2_Pos (2U)
3969#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
3970#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
3971#define CAN_F13R1_FB3_Pos (3U)
3972#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
3973#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
3974#define CAN_F13R1_FB4_Pos (4U)
3975#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
3976#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
3977#define CAN_F13R1_FB5_Pos (5U)
3978#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
3979#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
3980#define CAN_F13R1_FB6_Pos (6U)
3981#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
3982#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
3983#define CAN_F13R1_FB7_Pos (7U)
3984#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
3985#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
3986#define CAN_F13R1_FB8_Pos (8U)
3987#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
3988#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
3989#define CAN_F13R1_FB9_Pos (9U)
3990#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
3991#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
3992#define CAN_F13R1_FB10_Pos (10U)
3993#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
3994#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
3995#define CAN_F13R1_FB11_Pos (11U)
3996#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
3997#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
3998#define CAN_F13R1_FB12_Pos (12U)
3999#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
4000#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
4001#define CAN_F13R1_FB13_Pos (13U)
4002#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
4003#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
4004#define CAN_F13R1_FB14_Pos (14U)
4005#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
4006#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
4007#define CAN_F13R1_FB15_Pos (15U)
4008#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
4009#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
4010#define CAN_F13R1_FB16_Pos (16U)
4011#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
4012#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
4013#define CAN_F13R1_FB17_Pos (17U)
4014#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
4015#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
4016#define CAN_F13R1_FB18_Pos (18U)
4017#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
4018#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
4019#define CAN_F13R1_FB19_Pos (19U)
4020#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
4021#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
4022#define CAN_F13R1_FB20_Pos (20U)
4023#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
4024#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
4025#define CAN_F13R1_FB21_Pos (21U)
4026#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
4027#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
4028#define CAN_F13R1_FB22_Pos (22U)
4029#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
4030#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
4031#define CAN_F13R1_FB23_Pos (23U)
4032#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
4033#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
4034#define CAN_F13R1_FB24_Pos (24U)
4035#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
4036#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
4037#define CAN_F13R1_FB25_Pos (25U)
4038#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
4039#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
4040#define CAN_F13R1_FB26_Pos (26U)
4041#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
4042#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
4043#define CAN_F13R1_FB27_Pos (27U)
4044#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
4045#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
4046#define CAN_F13R1_FB28_Pos (28U)
4047#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
4048#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
4049#define CAN_F13R1_FB29_Pos (29U)
4050#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
4051#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
4052#define CAN_F13R1_FB30_Pos (30U)
4053#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
4054#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
4055#define CAN_F13R1_FB31_Pos (31U)
4056#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
4057#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
4058
4059/******************* Bit definition for CAN_F0R2 register *******************/
4060#define CAN_F0R2_FB0_Pos (0U)
4061#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
4062#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
4063#define CAN_F0R2_FB1_Pos (1U)
4064#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
4065#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
4066#define CAN_F0R2_FB2_Pos (2U)
4067#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
4068#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
4069#define CAN_F0R2_FB3_Pos (3U)
4070#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
4071#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
4072#define CAN_F0R2_FB4_Pos (4U)
4073#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
4074#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
4075#define CAN_F0R2_FB5_Pos (5U)
4076#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
4077#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
4078#define CAN_F0R2_FB6_Pos (6U)
4079#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
4080#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
4081#define CAN_F0R2_FB7_Pos (7U)
4082#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
4083#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
4084#define CAN_F0R2_FB8_Pos (8U)
4085#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
4086#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
4087#define CAN_F0R2_FB9_Pos (9U)
4088#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
4089#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
4090#define CAN_F0R2_FB10_Pos (10U)
4091#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
4092#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
4093#define CAN_F0R2_FB11_Pos (11U)
4094#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
4095#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
4096#define CAN_F0R2_FB12_Pos (12U)
4097#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
4098#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
4099#define CAN_F0R2_FB13_Pos (13U)
4100#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
4101#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
4102#define CAN_F0R2_FB14_Pos (14U)
4103#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
4104#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
4105#define CAN_F0R2_FB15_Pos (15U)
4106#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
4107#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
4108#define CAN_F0R2_FB16_Pos (16U)
4109#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
4110#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
4111#define CAN_F0R2_FB17_Pos (17U)
4112#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
4113#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
4114#define CAN_F0R2_FB18_Pos (18U)
4115#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
4116#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
4117#define CAN_F0R2_FB19_Pos (19U)
4118#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
4119#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
4120#define CAN_F0R2_FB20_Pos (20U)
4121#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
4122#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
4123#define CAN_F0R2_FB21_Pos (21U)
4124#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
4125#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
4126#define CAN_F0R2_FB22_Pos (22U)
4127#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
4128#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
4129#define CAN_F0R2_FB23_Pos (23U)
4130#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
4131#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
4132#define CAN_F0R2_FB24_Pos (24U)
4133#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
4134#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
4135#define CAN_F0R2_FB25_Pos (25U)
4136#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
4137#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
4138#define CAN_F0R2_FB26_Pos (26U)
4139#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
4140#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
4141#define CAN_F0R2_FB27_Pos (27U)
4142#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
4143#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
4144#define CAN_F0R2_FB28_Pos (28U)
4145#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
4146#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
4147#define CAN_F0R2_FB29_Pos (29U)
4148#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
4149#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
4150#define CAN_F0R2_FB30_Pos (30U)
4151#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
4152#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
4153#define CAN_F0R2_FB31_Pos (31U)
4154#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
4155#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
4156
4157/******************* Bit definition for CAN_F1R2 register *******************/
4158#define CAN_F1R2_FB0_Pos (0U)
4159#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
4160#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
4161#define CAN_F1R2_FB1_Pos (1U)
4162#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
4163#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
4164#define CAN_F1R2_FB2_Pos (2U)
4165#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
4166#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
4167#define CAN_F1R2_FB3_Pos (3U)
4168#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
4169#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
4170#define CAN_F1R2_FB4_Pos (4U)
4171#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
4172#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
4173#define CAN_F1R2_FB5_Pos (5U)
4174#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
4175#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
4176#define CAN_F1R2_FB6_Pos (6U)
4177#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
4178#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
4179#define CAN_F1R2_FB7_Pos (7U)
4180#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
4181#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
4182#define CAN_F1R2_FB8_Pos (8U)
4183#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
4184#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
4185#define CAN_F1R2_FB9_Pos (9U)
4186#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
4187#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
4188#define CAN_F1R2_FB10_Pos (10U)
4189#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
4190#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
4191#define CAN_F1R2_FB11_Pos (11U)
4192#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
4193#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
4194#define CAN_F1R2_FB12_Pos (12U)
4195#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
4196#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
4197#define CAN_F1R2_FB13_Pos (13U)
4198#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
4199#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
4200#define CAN_F1R2_FB14_Pos (14U)
4201#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
4202#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
4203#define CAN_F1R2_FB15_Pos (15U)
4204#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
4205#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
4206#define CAN_F1R2_FB16_Pos (16U)
4207#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
4208#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
4209#define CAN_F1R2_FB17_Pos (17U)
4210#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
4211#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
4212#define CAN_F1R2_FB18_Pos (18U)
4213#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
4214#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
4215#define CAN_F1R2_FB19_Pos (19U)
4216#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
4217#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
4218#define CAN_F1R2_FB20_Pos (20U)
4219#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
4220#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
4221#define CAN_F1R2_FB21_Pos (21U)
4222#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
4223#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
4224#define CAN_F1R2_FB22_Pos (22U)
4225#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
4226#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
4227#define CAN_F1R2_FB23_Pos (23U)
4228#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
4229#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
4230#define CAN_F1R2_FB24_Pos (24U)
4231#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
4232#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
4233#define CAN_F1R2_FB25_Pos (25U)
4234#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
4235#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
4236#define CAN_F1R2_FB26_Pos (26U)
4237#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
4238#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
4239#define CAN_F1R2_FB27_Pos (27U)
4240#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
4241#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
4242#define CAN_F1R2_FB28_Pos (28U)
4243#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
4244#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
4245#define CAN_F1R2_FB29_Pos (29U)
4246#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
4247#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
4248#define CAN_F1R2_FB30_Pos (30U)
4249#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
4250#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
4251#define CAN_F1R2_FB31_Pos (31U)
4252#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
4253#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
4254
4255/******************* Bit definition for CAN_F2R2 register *******************/
4256#define CAN_F2R2_FB0_Pos (0U)
4257#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
4258#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
4259#define CAN_F2R2_FB1_Pos (1U)
4260#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
4261#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
4262#define CAN_F2R2_FB2_Pos (2U)
4263#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
4264#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
4265#define CAN_F2R2_FB3_Pos (3U)
4266#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
4267#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
4268#define CAN_F2R2_FB4_Pos (4U)
4269#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
4270#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
4271#define CAN_F2R2_FB5_Pos (5U)
4272#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
4273#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
4274#define CAN_F2R2_FB6_Pos (6U)
4275#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
4276#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
4277#define CAN_F2R2_FB7_Pos (7U)
4278#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
4279#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
4280#define CAN_F2R2_FB8_Pos (8U)
4281#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
4282#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
4283#define CAN_F2R2_FB9_Pos (9U)
4284#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
4285#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
4286#define CAN_F2R2_FB10_Pos (10U)
4287#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
4288#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
4289#define CAN_F2R2_FB11_Pos (11U)
4290#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
4291#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
4292#define CAN_F2R2_FB12_Pos (12U)
4293#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
4294#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
4295#define CAN_F2R2_FB13_Pos (13U)
4296#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
4297#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
4298#define CAN_F2R2_FB14_Pos (14U)
4299#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
4300#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
4301#define CAN_F2R2_FB15_Pos (15U)
4302#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
4303#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
4304#define CAN_F2R2_FB16_Pos (16U)
4305#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
4306#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
4307#define CAN_F2R2_FB17_Pos (17U)
4308#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
4309#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
4310#define CAN_F2R2_FB18_Pos (18U)
4311#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
4312#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
4313#define CAN_F2R2_FB19_Pos (19U)
4314#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
4315#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
4316#define CAN_F2R2_FB20_Pos (20U)
4317#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
4318#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
4319#define CAN_F2R2_FB21_Pos (21U)
4320#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
4321#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
4322#define CAN_F2R2_FB22_Pos (22U)
4323#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
4324#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
4325#define CAN_F2R2_FB23_Pos (23U)
4326#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
4327#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
4328#define CAN_F2R2_FB24_Pos (24U)
4329#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
4330#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
4331#define CAN_F2R2_FB25_Pos (25U)
4332#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
4333#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
4334#define CAN_F2R2_FB26_Pos (26U)
4335#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
4336#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
4337#define CAN_F2R2_FB27_Pos (27U)
4338#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
4339#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
4340#define CAN_F2R2_FB28_Pos (28U)
4341#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
4342#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
4343#define CAN_F2R2_FB29_Pos (29U)
4344#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
4345#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
4346#define CAN_F2R2_FB30_Pos (30U)
4347#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
4348#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
4349#define CAN_F2R2_FB31_Pos (31U)
4350#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
4351#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
4352
4353/******************* Bit definition for CAN_F3R2 register *******************/
4354#define CAN_F3R2_FB0_Pos (0U)
4355#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
4356#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
4357#define CAN_F3R2_FB1_Pos (1U)
4358#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
4359#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
4360#define CAN_F3R2_FB2_Pos (2U)
4361#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
4362#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
4363#define CAN_F3R2_FB3_Pos (3U)
4364#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
4365#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
4366#define CAN_F3R2_FB4_Pos (4U)
4367#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
4368#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
4369#define CAN_F3R2_FB5_Pos (5U)
4370#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
4371#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
4372#define CAN_F3R2_FB6_Pos (6U)
4373#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
4374#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
4375#define CAN_F3R2_FB7_Pos (7U)
4376#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
4377#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
4378#define CAN_F3R2_FB8_Pos (8U)
4379#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
4380#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
4381#define CAN_F3R2_FB9_Pos (9U)
4382#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
4383#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
4384#define CAN_F3R2_FB10_Pos (10U)
4385#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
4386#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
4387#define CAN_F3R2_FB11_Pos (11U)
4388#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
4389#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
4390#define CAN_F3R2_FB12_Pos (12U)
4391#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
4392#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
4393#define CAN_F3R2_FB13_Pos (13U)
4394#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
4395#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
4396#define CAN_F3R2_FB14_Pos (14U)
4397#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
4398#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
4399#define CAN_F3R2_FB15_Pos (15U)
4400#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
4401#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
4402#define CAN_F3R2_FB16_Pos (16U)
4403#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
4404#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
4405#define CAN_F3R2_FB17_Pos (17U)
4406#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
4407#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
4408#define CAN_F3R2_FB18_Pos (18U)
4409#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
4410#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
4411#define CAN_F3R2_FB19_Pos (19U)
4412#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
4413#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
4414#define CAN_F3R2_FB20_Pos (20U)
4415#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
4416#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
4417#define CAN_F3R2_FB21_Pos (21U)
4418#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
4419#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
4420#define CAN_F3R2_FB22_Pos (22U)
4421#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
4422#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
4423#define CAN_F3R2_FB23_Pos (23U)
4424#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
4425#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
4426#define CAN_F3R2_FB24_Pos (24U)
4427#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
4428#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
4429#define CAN_F3R2_FB25_Pos (25U)
4430#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
4431#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
4432#define CAN_F3R2_FB26_Pos (26U)
4433#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
4434#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
4435#define CAN_F3R2_FB27_Pos (27U)
4436#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
4437#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
4438#define CAN_F3R2_FB28_Pos (28U)
4439#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
4440#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
4441#define CAN_F3R2_FB29_Pos (29U)
4442#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
4443#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
4444#define CAN_F3R2_FB30_Pos (30U)
4445#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
4446#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
4447#define CAN_F3R2_FB31_Pos (31U)
4448#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
4449#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
4450
4451/******************* Bit definition for CAN_F4R2 register *******************/
4452#define CAN_F4R2_FB0_Pos (0U)
4453#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
4454#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
4455#define CAN_F4R2_FB1_Pos (1U)
4456#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
4457#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
4458#define CAN_F4R2_FB2_Pos (2U)
4459#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
4460#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
4461#define CAN_F4R2_FB3_Pos (3U)
4462#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
4463#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
4464#define CAN_F4R2_FB4_Pos (4U)
4465#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
4466#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
4467#define CAN_F4R2_FB5_Pos (5U)
4468#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
4469#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
4470#define CAN_F4R2_FB6_Pos (6U)
4471#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
4472#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
4473#define CAN_F4R2_FB7_Pos (7U)
4474#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
4475#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
4476#define CAN_F4R2_FB8_Pos (8U)
4477#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
4478#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
4479#define CAN_F4R2_FB9_Pos (9U)
4480#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
4481#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
4482#define CAN_F4R2_FB10_Pos (10U)
4483#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
4484#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
4485#define CAN_F4R2_FB11_Pos (11U)
4486#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
4487#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
4488#define CAN_F4R2_FB12_Pos (12U)
4489#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
4490#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
4491#define CAN_F4R2_FB13_Pos (13U)
4492#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
4493#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
4494#define CAN_F4R2_FB14_Pos (14U)
4495#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
4496#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
4497#define CAN_F4R2_FB15_Pos (15U)
4498#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
4499#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
4500#define CAN_F4R2_FB16_Pos (16U)
4501#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
4502#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
4503#define CAN_F4R2_FB17_Pos (17U)
4504#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
4505#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
4506#define CAN_F4R2_FB18_Pos (18U)
4507#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
4508#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
4509#define CAN_F4R2_FB19_Pos (19U)
4510#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
4511#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
4512#define CAN_F4R2_FB20_Pos (20U)
4513#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
4514#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
4515#define CAN_F4R2_FB21_Pos (21U)
4516#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
4517#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
4518#define CAN_F4R2_FB22_Pos (22U)
4519#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
4520#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
4521#define CAN_F4R2_FB23_Pos (23U)
4522#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
4523#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
4524#define CAN_F4R2_FB24_Pos (24U)
4525#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
4526#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
4527#define CAN_F4R2_FB25_Pos (25U)
4528#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
4529#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
4530#define CAN_F4R2_FB26_Pos (26U)
4531#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
4532#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
4533#define CAN_F4R2_FB27_Pos (27U)
4534#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
4535#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
4536#define CAN_F4R2_FB28_Pos (28U)
4537#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
4538#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
4539#define CAN_F4R2_FB29_Pos (29U)
4540#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
4541#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
4542#define CAN_F4R2_FB30_Pos (30U)
4543#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
4544#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
4545#define CAN_F4R2_FB31_Pos (31U)
4546#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
4547#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
4548
4549/******************* Bit definition for CAN_F5R2 register *******************/
4550#define CAN_F5R2_FB0_Pos (0U)
4551#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
4552#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
4553#define CAN_F5R2_FB1_Pos (1U)
4554#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
4555#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
4556#define CAN_F5R2_FB2_Pos (2U)
4557#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
4558#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
4559#define CAN_F5R2_FB3_Pos (3U)
4560#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
4561#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
4562#define CAN_F5R2_FB4_Pos (4U)
4563#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
4564#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
4565#define CAN_F5R2_FB5_Pos (5U)
4566#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
4567#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
4568#define CAN_F5R2_FB6_Pos (6U)
4569#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
4570#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
4571#define CAN_F5R2_FB7_Pos (7U)
4572#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
4573#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
4574#define CAN_F5R2_FB8_Pos (8U)
4575#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
4576#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
4577#define CAN_F5R2_FB9_Pos (9U)
4578#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
4579#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
4580#define CAN_F5R2_FB10_Pos (10U)
4581#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
4582#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
4583#define CAN_F5R2_FB11_Pos (11U)
4584#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
4585#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
4586#define CAN_F5R2_FB12_Pos (12U)
4587#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
4588#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
4589#define CAN_F5R2_FB13_Pos (13U)
4590#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
4591#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
4592#define CAN_F5R2_FB14_Pos (14U)
4593#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
4594#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
4595#define CAN_F5R2_FB15_Pos (15U)
4596#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
4597#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
4598#define CAN_F5R2_FB16_Pos (16U)
4599#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
4600#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
4601#define CAN_F5R2_FB17_Pos (17U)
4602#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
4603#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
4604#define CAN_F5R2_FB18_Pos (18U)
4605#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
4606#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
4607#define CAN_F5R2_FB19_Pos (19U)
4608#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
4609#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
4610#define CAN_F5R2_FB20_Pos (20U)
4611#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
4612#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
4613#define CAN_F5R2_FB21_Pos (21U)
4614#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
4615#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
4616#define CAN_F5R2_FB22_Pos (22U)
4617#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
4618#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
4619#define CAN_F5R2_FB23_Pos (23U)
4620#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
4621#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
4622#define CAN_F5R2_FB24_Pos (24U)
4623#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
4624#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
4625#define CAN_F5R2_FB25_Pos (25U)
4626#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
4627#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
4628#define CAN_F5R2_FB26_Pos (26U)
4629#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
4630#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
4631#define CAN_F5R2_FB27_Pos (27U)
4632#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
4633#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
4634#define CAN_F5R2_FB28_Pos (28U)
4635#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
4636#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
4637#define CAN_F5R2_FB29_Pos (29U)
4638#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
4639#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
4640#define CAN_F5R2_FB30_Pos (30U)
4641#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
4642#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
4643#define CAN_F5R2_FB31_Pos (31U)
4644#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
4645#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
4646
4647/******************* Bit definition for CAN_F6R2 register *******************/
4648#define CAN_F6R2_FB0_Pos (0U)
4649#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
4650#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
4651#define CAN_F6R2_FB1_Pos (1U)
4652#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
4653#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
4654#define CAN_F6R2_FB2_Pos (2U)
4655#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
4656#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
4657#define CAN_F6R2_FB3_Pos (3U)
4658#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
4659#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
4660#define CAN_F6R2_FB4_Pos (4U)
4661#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
4662#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
4663#define CAN_F6R2_FB5_Pos (5U)
4664#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
4665#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
4666#define CAN_F6R2_FB6_Pos (6U)
4667#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
4668#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
4669#define CAN_F6R2_FB7_Pos (7U)
4670#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
4671#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
4672#define CAN_F6R2_FB8_Pos (8U)
4673#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
4674#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
4675#define CAN_F6R2_FB9_Pos (9U)
4676#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
4677#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
4678#define CAN_F6R2_FB10_Pos (10U)
4679#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
4680#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
4681#define CAN_F6R2_FB11_Pos (11U)
4682#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
4683#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
4684#define CAN_F6R2_FB12_Pos (12U)
4685#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
4686#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
4687#define CAN_F6R2_FB13_Pos (13U)
4688#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
4689#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
4690#define CAN_F6R2_FB14_Pos (14U)
4691#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
4692#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
4693#define CAN_F6R2_FB15_Pos (15U)
4694#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
4695#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
4696#define CAN_F6R2_FB16_Pos (16U)
4697#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
4698#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
4699#define CAN_F6R2_FB17_Pos (17U)
4700#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
4701#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
4702#define CAN_F6R2_FB18_Pos (18U)
4703#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
4704#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
4705#define CAN_F6R2_FB19_Pos (19U)
4706#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
4707#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
4708#define CAN_F6R2_FB20_Pos (20U)
4709#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
4710#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
4711#define CAN_F6R2_FB21_Pos (21U)
4712#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
4713#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
4714#define CAN_F6R2_FB22_Pos (22U)
4715#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
4716#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
4717#define CAN_F6R2_FB23_Pos (23U)
4718#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
4719#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
4720#define CAN_F6R2_FB24_Pos (24U)
4721#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
4722#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
4723#define CAN_F6R2_FB25_Pos (25U)
4724#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
4725#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
4726#define CAN_F6R2_FB26_Pos (26U)
4727#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
4728#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
4729#define CAN_F6R2_FB27_Pos (27U)
4730#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
4731#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
4732#define CAN_F6R2_FB28_Pos (28U)
4733#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
4734#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
4735#define CAN_F6R2_FB29_Pos (29U)
4736#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
4737#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
4738#define CAN_F6R2_FB30_Pos (30U)
4739#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
4740#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
4741#define CAN_F6R2_FB31_Pos (31U)
4742#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
4743#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
4744
4745/******************* Bit definition for CAN_F7R2 register *******************/
4746#define CAN_F7R2_FB0_Pos (0U)
4747#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
4748#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
4749#define CAN_F7R2_FB1_Pos (1U)
4750#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
4751#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
4752#define CAN_F7R2_FB2_Pos (2U)
4753#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
4754#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
4755#define CAN_F7R2_FB3_Pos (3U)
4756#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
4757#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
4758#define CAN_F7R2_FB4_Pos (4U)
4759#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
4760#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
4761#define CAN_F7R2_FB5_Pos (5U)
4762#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
4763#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
4764#define CAN_F7R2_FB6_Pos (6U)
4765#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
4766#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
4767#define CAN_F7R2_FB7_Pos (7U)
4768#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
4769#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
4770#define CAN_F7R2_FB8_Pos (8U)
4771#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
4772#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
4773#define CAN_F7R2_FB9_Pos (9U)
4774#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
4775#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
4776#define CAN_F7R2_FB10_Pos (10U)
4777#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
4778#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
4779#define CAN_F7R2_FB11_Pos (11U)
4780#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
4781#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
4782#define CAN_F7R2_FB12_Pos (12U)
4783#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
4784#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
4785#define CAN_F7R2_FB13_Pos (13U)
4786#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
4787#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
4788#define CAN_F7R2_FB14_Pos (14U)
4789#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
4790#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
4791#define CAN_F7R2_FB15_Pos (15U)
4792#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
4793#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
4794#define CAN_F7R2_FB16_Pos (16U)
4795#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
4796#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
4797#define CAN_F7R2_FB17_Pos (17U)
4798#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
4799#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
4800#define CAN_F7R2_FB18_Pos (18U)
4801#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
4802#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
4803#define CAN_F7R2_FB19_Pos (19U)
4804#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
4805#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
4806#define CAN_F7R2_FB20_Pos (20U)
4807#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
4808#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
4809#define CAN_F7R2_FB21_Pos (21U)
4810#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
4811#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
4812#define CAN_F7R2_FB22_Pos (22U)
4813#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
4814#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
4815#define CAN_F7R2_FB23_Pos (23U)
4816#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
4817#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
4818#define CAN_F7R2_FB24_Pos (24U)
4819#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
4820#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
4821#define CAN_F7R2_FB25_Pos (25U)
4822#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
4823#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
4824#define CAN_F7R2_FB26_Pos (26U)
4825#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
4826#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
4827#define CAN_F7R2_FB27_Pos (27U)
4828#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
4829#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
4830#define CAN_F7R2_FB28_Pos (28U)
4831#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
4832#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
4833#define CAN_F7R2_FB29_Pos (29U)
4834#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
4835#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
4836#define CAN_F7R2_FB30_Pos (30U)
4837#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
4838#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
4839#define CAN_F7R2_FB31_Pos (31U)
4840#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
4841#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
4842
4843/******************* Bit definition for CAN_F8R2 register *******************/
4844#define CAN_F8R2_FB0_Pos (0U)
4845#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
4846#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
4847#define CAN_F8R2_FB1_Pos (1U)
4848#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
4849#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
4850#define CAN_F8R2_FB2_Pos (2U)
4851#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
4852#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
4853#define CAN_F8R2_FB3_Pos (3U)
4854#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
4855#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
4856#define CAN_F8R2_FB4_Pos (4U)
4857#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
4858#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
4859#define CAN_F8R2_FB5_Pos (5U)
4860#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
4861#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
4862#define CAN_F8R2_FB6_Pos (6U)
4863#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
4864#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
4865#define CAN_F8R2_FB7_Pos (7U)
4866#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
4867#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
4868#define CAN_F8R2_FB8_Pos (8U)
4869#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
4870#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
4871#define CAN_F8R2_FB9_Pos (9U)
4872#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
4873#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
4874#define CAN_F8R2_FB10_Pos (10U)
4875#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
4876#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
4877#define CAN_F8R2_FB11_Pos (11U)
4878#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
4879#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
4880#define CAN_F8R2_FB12_Pos (12U)
4881#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
4882#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
4883#define CAN_F8R2_FB13_Pos (13U)
4884#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
4885#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
4886#define CAN_F8R2_FB14_Pos (14U)
4887#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
4888#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
4889#define CAN_F8R2_FB15_Pos (15U)
4890#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
4891#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
4892#define CAN_F8R2_FB16_Pos (16U)
4893#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
4894#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
4895#define CAN_F8R2_FB17_Pos (17U)
4896#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
4897#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
4898#define CAN_F8R2_FB18_Pos (18U)
4899#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
4900#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
4901#define CAN_F8R2_FB19_Pos (19U)
4902#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
4903#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
4904#define CAN_F8R2_FB20_Pos (20U)
4905#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
4906#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
4907#define CAN_F8R2_FB21_Pos (21U)
4908#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
4909#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
4910#define CAN_F8R2_FB22_Pos (22U)
4911#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
4912#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
4913#define CAN_F8R2_FB23_Pos (23U)
4914#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
4915#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
4916#define CAN_F8R2_FB24_Pos (24U)
4917#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
4918#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
4919#define CAN_F8R2_FB25_Pos (25U)
4920#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
4921#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
4922#define CAN_F8R2_FB26_Pos (26U)
4923#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
4924#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
4925#define CAN_F8R2_FB27_Pos (27U)
4926#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
4927#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
4928#define CAN_F8R2_FB28_Pos (28U)
4929#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
4930#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
4931#define CAN_F8R2_FB29_Pos (29U)
4932#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
4933#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
4934#define CAN_F8R2_FB30_Pos (30U)
4935#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
4936#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
4937#define CAN_F8R2_FB31_Pos (31U)
4938#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
4939#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
4940
4941/******************* Bit definition for CAN_F9R2 register *******************/
4942#define CAN_F9R2_FB0_Pos (0U)
4943#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
4944#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
4945#define CAN_F9R2_FB1_Pos (1U)
4946#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
4947#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
4948#define CAN_F9R2_FB2_Pos (2U)
4949#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
4950#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
4951#define CAN_F9R2_FB3_Pos (3U)
4952#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
4953#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
4954#define CAN_F9R2_FB4_Pos (4U)
4955#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
4956#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
4957#define CAN_F9R2_FB5_Pos (5U)
4958#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
4959#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
4960#define CAN_F9R2_FB6_Pos (6U)
4961#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
4962#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
4963#define CAN_F9R2_FB7_Pos (7U)
4964#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
4965#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
4966#define CAN_F9R2_FB8_Pos (8U)
4967#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
4968#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
4969#define CAN_F9R2_FB9_Pos (9U)
4970#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
4971#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
4972#define CAN_F9R2_FB10_Pos (10U)
4973#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
4974#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
4975#define CAN_F9R2_FB11_Pos (11U)
4976#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
4977#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
4978#define CAN_F9R2_FB12_Pos (12U)
4979#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
4980#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
4981#define CAN_F9R2_FB13_Pos (13U)
4982#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
4983#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
4984#define CAN_F9R2_FB14_Pos (14U)
4985#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
4986#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
4987#define CAN_F9R2_FB15_Pos (15U)
4988#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
4989#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
4990#define CAN_F9R2_FB16_Pos (16U)
4991#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
4992#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
4993#define CAN_F9R2_FB17_Pos (17U)
4994#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
4995#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
4996#define CAN_F9R2_FB18_Pos (18U)
4997#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
4998#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
4999#define CAN_F9R2_FB19_Pos (19U)
5000#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
5001#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
5002#define CAN_F9R2_FB20_Pos (20U)
5003#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
5004#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
5005#define CAN_F9R2_FB21_Pos (21U)
5006#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
5007#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
5008#define CAN_F9R2_FB22_Pos (22U)
5009#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
5010#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
5011#define CAN_F9R2_FB23_Pos (23U)
5012#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
5013#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
5014#define CAN_F9R2_FB24_Pos (24U)
5015#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
5016#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
5017#define CAN_F9R2_FB25_Pos (25U)
5018#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
5019#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
5020#define CAN_F9R2_FB26_Pos (26U)
5021#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
5022#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
5023#define CAN_F9R2_FB27_Pos (27U)
5024#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
5025#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
5026#define CAN_F9R2_FB28_Pos (28U)
5027#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
5028#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
5029#define CAN_F9R2_FB29_Pos (29U)
5030#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
5031#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
5032#define CAN_F9R2_FB30_Pos (30U)
5033#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
5034#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
5035#define CAN_F9R2_FB31_Pos (31U)
5036#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
5037#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
5038
5039/******************* Bit definition for CAN_F10R2 register ******************/
5040#define CAN_F10R2_FB0_Pos (0U)
5041#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
5042#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
5043#define CAN_F10R2_FB1_Pos (1U)
5044#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
5045#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
5046#define CAN_F10R2_FB2_Pos (2U)
5047#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
5048#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
5049#define CAN_F10R2_FB3_Pos (3U)
5050#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
5051#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
5052#define CAN_F10R2_FB4_Pos (4U)
5053#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
5054#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
5055#define CAN_F10R2_FB5_Pos (5U)
5056#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
5057#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
5058#define CAN_F10R2_FB6_Pos (6U)
5059#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
5060#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
5061#define CAN_F10R2_FB7_Pos (7U)
5062#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
5063#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
5064#define CAN_F10R2_FB8_Pos (8U)
5065#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
5066#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
5067#define CAN_F10R2_FB9_Pos (9U)
5068#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
5069#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
5070#define CAN_F10R2_FB10_Pos (10U)
5071#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
5072#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
5073#define CAN_F10R2_FB11_Pos (11U)
5074#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
5075#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
5076#define CAN_F10R2_FB12_Pos (12U)
5077#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
5078#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
5079#define CAN_F10R2_FB13_Pos (13U)
5080#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
5081#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
5082#define CAN_F10R2_FB14_Pos (14U)
5083#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
5084#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
5085#define CAN_F10R2_FB15_Pos (15U)
5086#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
5087#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
5088#define CAN_F10R2_FB16_Pos (16U)
5089#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
5090#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
5091#define CAN_F10R2_FB17_Pos (17U)
5092#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
5093#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
5094#define CAN_F10R2_FB18_Pos (18U)
5095#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
5096#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
5097#define CAN_F10R2_FB19_Pos (19U)
5098#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
5099#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
5100#define CAN_F10R2_FB20_Pos (20U)
5101#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
5102#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
5103#define CAN_F10R2_FB21_Pos (21U)
5104#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
5105#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
5106#define CAN_F10R2_FB22_Pos (22U)
5107#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
5108#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
5109#define CAN_F10R2_FB23_Pos (23U)
5110#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
5111#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
5112#define CAN_F10R2_FB24_Pos (24U)
5113#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
5114#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
5115#define CAN_F10R2_FB25_Pos (25U)
5116#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
5117#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
5118#define CAN_F10R2_FB26_Pos (26U)
5119#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
5120#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
5121#define CAN_F10R2_FB27_Pos (27U)
5122#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
5123#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
5124#define CAN_F10R2_FB28_Pos (28U)
5125#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
5126#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
5127#define CAN_F10R2_FB29_Pos (29U)
5128#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
5129#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
5130#define CAN_F10R2_FB30_Pos (30U)
5131#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
5132#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
5133#define CAN_F10R2_FB31_Pos (31U)
5134#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
5135#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
5136
5137/******************* Bit definition for CAN_F11R2 register ******************/
5138#define CAN_F11R2_FB0_Pos (0U)
5139#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
5140#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
5141#define CAN_F11R2_FB1_Pos (1U)
5142#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
5143#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
5144#define CAN_F11R2_FB2_Pos (2U)
5145#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
5146#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
5147#define CAN_F11R2_FB3_Pos (3U)
5148#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
5149#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
5150#define CAN_F11R2_FB4_Pos (4U)
5151#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
5152#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
5153#define CAN_F11R2_FB5_Pos (5U)
5154#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
5155#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
5156#define CAN_F11R2_FB6_Pos (6U)
5157#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
5158#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
5159#define CAN_F11R2_FB7_Pos (7U)
5160#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
5161#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
5162#define CAN_F11R2_FB8_Pos (8U)
5163#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
5164#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
5165#define CAN_F11R2_FB9_Pos (9U)
5166#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
5167#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
5168#define CAN_F11R2_FB10_Pos (10U)
5169#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
5170#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
5171#define CAN_F11R2_FB11_Pos (11U)
5172#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
5173#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
5174#define CAN_F11R2_FB12_Pos (12U)
5175#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
5176#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
5177#define CAN_F11R2_FB13_Pos (13U)
5178#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
5179#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
5180#define CAN_F11R2_FB14_Pos (14U)
5181#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
5182#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
5183#define CAN_F11R2_FB15_Pos (15U)
5184#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
5185#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
5186#define CAN_F11R2_FB16_Pos (16U)
5187#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
5188#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
5189#define CAN_F11R2_FB17_Pos (17U)
5190#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
5191#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
5192#define CAN_F11R2_FB18_Pos (18U)
5193#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
5194#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
5195#define CAN_F11R2_FB19_Pos (19U)
5196#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
5197#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
5198#define CAN_F11R2_FB20_Pos (20U)
5199#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
5200#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
5201#define CAN_F11R2_FB21_Pos (21U)
5202#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
5203#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
5204#define CAN_F11R2_FB22_Pos (22U)
5205#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
5206#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
5207#define CAN_F11R2_FB23_Pos (23U)
5208#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
5209#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
5210#define CAN_F11R2_FB24_Pos (24U)
5211#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
5212#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
5213#define CAN_F11R2_FB25_Pos (25U)
5214#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
5215#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
5216#define CAN_F11R2_FB26_Pos (26U)
5217#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
5218#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
5219#define CAN_F11R2_FB27_Pos (27U)
5220#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
5221#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
5222#define CAN_F11R2_FB28_Pos (28U)
5223#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
5224#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
5225#define CAN_F11R2_FB29_Pos (29U)
5226#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
5227#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
5228#define CAN_F11R2_FB30_Pos (30U)
5229#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
5230#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
5231#define CAN_F11R2_FB31_Pos (31U)
5232#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
5233#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
5234
5235/******************* Bit definition for CAN_F12R2 register ******************/
5236#define CAN_F12R2_FB0_Pos (0U)
5237#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
5238#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
5239#define CAN_F12R2_FB1_Pos (1U)
5240#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
5241#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
5242#define CAN_F12R2_FB2_Pos (2U)
5243#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
5244#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
5245#define CAN_F12R2_FB3_Pos (3U)
5246#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
5247#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
5248#define CAN_F12R2_FB4_Pos (4U)
5249#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
5250#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
5251#define CAN_F12R2_FB5_Pos (5U)
5252#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
5253#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
5254#define CAN_F12R2_FB6_Pos (6U)
5255#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
5256#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
5257#define CAN_F12R2_FB7_Pos (7U)
5258#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
5259#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
5260#define CAN_F12R2_FB8_Pos (8U)
5261#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
5262#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
5263#define CAN_F12R2_FB9_Pos (9U)
5264#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
5265#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
5266#define CAN_F12R2_FB10_Pos (10U)
5267#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
5268#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
5269#define CAN_F12R2_FB11_Pos (11U)
5270#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
5271#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
5272#define CAN_F12R2_FB12_Pos (12U)
5273#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
5274#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
5275#define CAN_F12R2_FB13_Pos (13U)
5276#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
5277#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
5278#define CAN_F12R2_FB14_Pos (14U)
5279#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
5280#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
5281#define CAN_F12R2_FB15_Pos (15U)
5282#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
5283#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
5284#define CAN_F12R2_FB16_Pos (16U)
5285#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
5286#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
5287#define CAN_F12R2_FB17_Pos (17U)
5288#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
5289#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
5290#define CAN_F12R2_FB18_Pos (18U)
5291#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
5292#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
5293#define CAN_F12R2_FB19_Pos (19U)
5294#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
5295#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
5296#define CAN_F12R2_FB20_Pos (20U)
5297#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
5298#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
5299#define CAN_F12R2_FB21_Pos (21U)
5300#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
5301#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
5302#define CAN_F12R2_FB22_Pos (22U)
5303#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
5304#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
5305#define CAN_F12R2_FB23_Pos (23U)
5306#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
5307#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
5308#define CAN_F12R2_FB24_Pos (24U)
5309#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
5310#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
5311#define CAN_F12R2_FB25_Pos (25U)
5312#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
5313#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
5314#define CAN_F12R2_FB26_Pos (26U)
5315#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
5316#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
5317#define CAN_F12R2_FB27_Pos (27U)
5318#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
5319#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
5320#define CAN_F12R2_FB28_Pos (28U)
5321#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
5322#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
5323#define CAN_F12R2_FB29_Pos (29U)
5324#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
5325#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
5326#define CAN_F12R2_FB30_Pos (30U)
5327#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
5328#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
5329#define CAN_F12R2_FB31_Pos (31U)
5330#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
5331#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
5332
5333/******************* Bit definition for CAN_F13R2 register ******************/
5334#define CAN_F13R2_FB0_Pos (0U)
5335#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
5336#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
5337#define CAN_F13R2_FB1_Pos (1U)
5338#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
5339#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
5340#define CAN_F13R2_FB2_Pos (2U)
5341#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
5342#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
5343#define CAN_F13R2_FB3_Pos (3U)
5344#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
5345#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
5346#define CAN_F13R2_FB4_Pos (4U)
5347#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
5348#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
5349#define CAN_F13R2_FB5_Pos (5U)
5350#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
5351#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
5352#define CAN_F13R2_FB6_Pos (6U)
5353#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
5354#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
5355#define CAN_F13R2_FB7_Pos (7U)
5356#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
5357#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
5358#define CAN_F13R2_FB8_Pos (8U)
5359#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
5360#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
5361#define CAN_F13R2_FB9_Pos (9U)
5362#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
5363#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
5364#define CAN_F13R2_FB10_Pos (10U)
5365#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
5366#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
5367#define CAN_F13R2_FB11_Pos (11U)
5368#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
5369#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
5370#define CAN_F13R2_FB12_Pos (12U)
5371#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
5372#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
5373#define CAN_F13R2_FB13_Pos (13U)
5374#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
5375#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
5376#define CAN_F13R2_FB14_Pos (14U)
5377#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
5378#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
5379#define CAN_F13R2_FB15_Pos (15U)
5380#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
5381#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
5382#define CAN_F13R2_FB16_Pos (16U)
5383#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
5384#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
5385#define CAN_F13R2_FB17_Pos (17U)
5386#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
5387#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
5388#define CAN_F13R2_FB18_Pos (18U)
5389#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
5390#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
5391#define CAN_F13R2_FB19_Pos (19U)
5392#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
5393#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
5394#define CAN_F13R2_FB20_Pos (20U)
5395#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
5396#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
5397#define CAN_F13R2_FB21_Pos (21U)
5398#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
5399#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
5400#define CAN_F13R2_FB22_Pos (22U)
5401#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
5402#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
5403#define CAN_F13R2_FB23_Pos (23U)
5404#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
5405#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
5406#define CAN_F13R2_FB24_Pos (24U)
5407#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
5408#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
5409#define CAN_F13R2_FB25_Pos (25U)
5410#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
5411#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
5412#define CAN_F13R2_FB26_Pos (26U)
5413#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
5414#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
5415#define CAN_F13R2_FB27_Pos (27U)
5416#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
5417#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
5418#define CAN_F13R2_FB28_Pos (28U)
5419#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
5420#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
5421#define CAN_F13R2_FB29_Pos (29U)
5422#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
5423#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
5424#define CAN_F13R2_FB30_Pos (30U)
5425#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
5426#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
5427#define CAN_F13R2_FB31_Pos (31U)
5428#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
5429#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
5430
5431/******************************************************************************/
5432/* */
5433/* CRC calculation unit */
5434/* */
5435/******************************************************************************/
5436/******************* Bit definition for CRC_DR register *********************/
5437#define CRC_DR_DR_Pos (0U)
5438#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
5439#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
5440
5441
5442/******************* Bit definition for CRC_IDR register ********************/
5443#define CRC_IDR_IDR_Pos (0U)
5444#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
5445#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
5446
5447
5448/******************** Bit definition for CRC_CR register ********************/
5449#define CRC_CR_RESET_Pos (0U)
5450#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
5451#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
5452
5453/******************************************************************************/
5454/* */
5455/* Digital to Analog Converter */
5456/* */
5457/******************************************************************************/
5458/******************** Bit definition for DAC_CR register ********************/
5459#define DAC_CR_EN1_Pos (0U)
5460#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
5461#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
5462#define DAC_CR_BOFF1_Pos (1U)
5463#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
5464#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
5465#define DAC_CR_TEN1_Pos (2U)
5466#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
5467#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
5468
5469#define DAC_CR_TSEL1_Pos (3U)
5470#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
5471#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5472#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
5473#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
5474#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
5475
5476#define DAC_CR_WAVE1_Pos (6U)
5477#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
5478#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5479#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
5480#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
5481
5482#define DAC_CR_MAMP1_Pos (8U)
5483#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
5484#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5485#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
5486#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
5487#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
5488#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
5489
5490#define DAC_CR_DMAEN1_Pos (12U)
5491#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
5492#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
5493#define DAC_CR_DMAUDRIE1_Pos (13U)
5494#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
5495#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
5496#define DAC_CR_EN2_Pos (16U)
5497#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
5498#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
5499#define DAC_CR_BOFF2_Pos (17U)
5500#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
5501#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
5502#define DAC_CR_TEN2_Pos (18U)
5503#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
5504#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
5505
5506#define DAC_CR_TSEL2_Pos (19U)
5507#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
5508#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5509#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
5510#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
5511#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
5512
5513#define DAC_CR_WAVE2_Pos (22U)
5514#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
5515#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5516#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
5517#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
5518
5519#define DAC_CR_MAMP2_Pos (24U)
5520#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
5521#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5522#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
5523#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
5524#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
5525#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
5526
5527#define DAC_CR_DMAEN2_Pos (28U)
5528#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
5529#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
5530#define DAC_CR_DMAUDRIE2_Pos (29U)
5531#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
5532#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
5533
5534/***************** Bit definition for DAC_SWTRIGR register ******************/
5535#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5536#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
5537#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
5538#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5539#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
5540#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
5541
5542/***************** Bit definition for DAC_DHR12R1 register ******************/
5543#define DAC_DHR12R1_DACC1DHR_Pos (0U)
5544#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
5545#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5546
5547/***************** Bit definition for DAC_DHR12L1 register ******************/
5548#define DAC_DHR12L1_DACC1DHR_Pos (4U)
5549#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5550#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5551
5552/****************** Bit definition for DAC_DHR8R1 register ******************/
5553#define DAC_DHR8R1_DACC1DHR_Pos (0U)
5554#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
5555#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5556
5557/***************** Bit definition for DAC_DHR12R2 register ******************/
5558#define DAC_DHR12R2_DACC2DHR_Pos (0U)
5559#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
5560#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5561
5562/***************** Bit definition for DAC_DHR12L2 register ******************/
5563#define DAC_DHR12L2_DACC2DHR_Pos (4U)
5564#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
5565#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5566
5567/****************** Bit definition for DAC_DHR8R2 register ******************/
5568#define DAC_DHR8R2_DACC2DHR_Pos (0U)
5569#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
5570#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5571
5572/***************** Bit definition for DAC_DHR12RD register ******************/
5573#define DAC_DHR12RD_DACC1DHR_Pos (0U)
5574#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
5575#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5576#define DAC_DHR12RD_DACC2DHR_Pos (16U)
5577#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
5578#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5579
5580/***************** Bit definition for DAC_DHR12LD register ******************/
5581#define DAC_DHR12LD_DACC1DHR_Pos (4U)
5582#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5583#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5584#define DAC_DHR12LD_DACC2DHR_Pos (20U)
5585#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
5586#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5587
5588/****************** Bit definition for DAC_DHR8RD register ******************/
5589#define DAC_DHR8RD_DACC1DHR_Pos (0U)
5590#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
5591#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5592#define DAC_DHR8RD_DACC2DHR_Pos (8U)
5593#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
5594#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5595
5596/******************* Bit definition for DAC_DOR1 register *******************/
5597#define DAC_DOR1_DACC1DOR_Pos (0U)
5598#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
5599#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
5600
5601/******************* Bit definition for DAC_DOR2 register *******************/
5602#define DAC_DOR2_DACC2DOR_Pos (0U)
5603#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
5604#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
5605
5606/******************** Bit definition for DAC_SR register ********************/
5607#define DAC_SR_DMAUDR1_Pos (13U)
5608#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
5609#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
5610#define DAC_SR_DMAUDR2_Pos (29U)
5611#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
5612#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
5613
5614/******************************************************************************/
5615/* */
5616/* Debug MCU */
5617/* */
5618/******************************************************************************/
5619
5620/******************************************************************************/
5621/* */
5622/* DCMI */
5623/* */
5624/******************************************************************************/
5625/******************** Bits definition for DCMI_CR register ******************/
5626#define DCMI_CR_CAPTURE_Pos (0U)
5627#define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
5628#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
5629#define DCMI_CR_CM_Pos (1U)
5630#define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
5631#define DCMI_CR_CM DCMI_CR_CM_Msk
5632#define DCMI_CR_CROP_Pos (2U)
5633#define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
5634#define DCMI_CR_CROP DCMI_CR_CROP_Msk
5635#define DCMI_CR_JPEG_Pos (3U)
5636#define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
5637#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
5638#define DCMI_CR_ESS_Pos (4U)
5639#define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
5640#define DCMI_CR_ESS DCMI_CR_ESS_Msk
5641#define DCMI_CR_PCKPOL_Pos (5U)
5642#define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
5643#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
5644#define DCMI_CR_HSPOL_Pos (6U)
5645#define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
5646#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
5647#define DCMI_CR_VSPOL_Pos (7U)
5648#define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
5649#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
5650#define DCMI_CR_FCRC_0 0x00000100U
5651#define DCMI_CR_FCRC_1 0x00000200U
5652#define DCMI_CR_EDM_0 0x00000400U
5653#define DCMI_CR_EDM_1 0x00000800U
5654#define DCMI_CR_CRE_Pos (12U)
5655#define DCMI_CR_CRE_Msk (0x1U << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
5656#define DCMI_CR_CRE DCMI_CR_CRE_Msk
5657#define DCMI_CR_ENABLE_Pos (14U)
5658#define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
5659#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
5660
5661/******************** Bits definition for DCMI_SR register ******************/
5662#define DCMI_SR_HSYNC_Pos (0U)
5663#define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
5664#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
5665#define DCMI_SR_VSYNC_Pos (1U)
5666#define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
5667#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
5668#define DCMI_SR_FNE_Pos (2U)
5669#define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
5670#define DCMI_SR_FNE DCMI_SR_FNE_Msk
5671
5672/******************** Bits definition for DCMI_RIS register *****************/
5673#define DCMI_RIS_FRAME_RIS_Pos (0U)
5674#define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
5675#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
5676#define DCMI_RIS_OVR_RIS_Pos (1U)
5677#define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
5678#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
5679#define DCMI_RIS_ERR_RIS_Pos (2U)
5680#define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
5681#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
5682#define DCMI_RIS_VSYNC_RIS_Pos (3U)
5683#define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
5684#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
5685#define DCMI_RIS_LINE_RIS_Pos (4U)
5686#define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
5687#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
5688/* Legacy defines */
5689#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
5690#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
5691#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
5692#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
5693#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
5694
5695/******************** Bits definition for DCMI_IER register *****************/
5696#define DCMI_IER_FRAME_IE_Pos (0U)
5697#define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
5698#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
5699#define DCMI_IER_OVR_IE_Pos (1U)
5700#define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
5701#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
5702#define DCMI_IER_ERR_IE_Pos (2U)
5703#define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
5704#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
5705#define DCMI_IER_VSYNC_IE_Pos (3U)
5706#define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
5707#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
5708#define DCMI_IER_LINE_IE_Pos (4U)
5709#define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
5710#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
5711/* Legacy defines */
5712#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
5713
5714/******************** Bits definition for DCMI_MIS register *****************/
5715#define DCMI_MIS_FRAME_MIS_Pos (0U)
5716#define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
5717#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
5718#define DCMI_MIS_OVR_MIS_Pos (1U)
5719#define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
5720#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
5721#define DCMI_MIS_ERR_MIS_Pos (2U)
5722#define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
5723#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
5724#define DCMI_MIS_VSYNC_MIS_Pos (3U)
5725#define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
5726#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
5727#define DCMI_MIS_LINE_MIS_Pos (4U)
5728#define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
5729#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
5730
5731/* Legacy defines */
5732#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
5733#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
5734#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
5735#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
5736#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
5737
5738/******************** Bits definition for DCMI_ICR register *****************/
5739#define DCMI_ICR_FRAME_ISC_Pos (0U)
5740#define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
5741#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
5742#define DCMI_ICR_OVR_ISC_Pos (1U)
5743#define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
5744#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
5745#define DCMI_ICR_ERR_ISC_Pos (2U)
5746#define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
5747#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
5748#define DCMI_ICR_VSYNC_ISC_Pos (3U)
5749#define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
5750#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
5751#define DCMI_ICR_LINE_ISC_Pos (4U)
5752#define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
5753#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
5754
5755/* Legacy defines */
5756#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
5757
5758/******************** Bits definition for DCMI_ESCR register ******************/
5759#define DCMI_ESCR_FSC_Pos (0U)
5760#define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
5761#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
5762#define DCMI_ESCR_LSC_Pos (8U)
5763#define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
5764#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
5765#define DCMI_ESCR_LEC_Pos (16U)
5766#define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
5767#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
5768#define DCMI_ESCR_FEC_Pos (24U)
5769#define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
5770#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
5771
5772/******************** Bits definition for DCMI_ESUR register ******************/
5773#define DCMI_ESUR_FSU_Pos (0U)
5774#define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
5775#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
5776#define DCMI_ESUR_LSU_Pos (8U)
5777#define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
5778#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
5779#define DCMI_ESUR_LEU_Pos (16U)
5780#define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
5781#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
5782#define DCMI_ESUR_FEU_Pos (24U)
5783#define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
5784#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
5785
5786/******************** Bits definition for DCMI_CWSTRT register ******************/
5787#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
5788#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
5789#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
5790#define DCMI_CWSTRT_VST_Pos (16U)
5791#define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
5792#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
5793
5794/******************** Bits definition for DCMI_CWSIZE register ******************/
5795#define DCMI_CWSIZE_CAPCNT_Pos (0U)
5796#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
5797#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
5798#define DCMI_CWSIZE_VLINE_Pos (16U)
5799#define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
5800#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
5801
5802/******************** Bits definition for DCMI_DR register ******************/
5803#define DCMI_DR_BYTE0_Pos (0U)
5804#define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
5805#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
5806#define DCMI_DR_BYTE1_Pos (8U)
5807#define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
5808#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
5809#define DCMI_DR_BYTE2_Pos (16U)
5810#define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
5811#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
5812#define DCMI_DR_BYTE3_Pos (24U)
5813#define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
5814#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
5815
5816/******************************************************************************/
5817/* */
5818/* DMA Controller */
5819/* */
5820/******************************************************************************/
5821/******************** Bits definition for DMA_SxCR register *****************/
5822#define DMA_SxCR_CHSEL_Pos (25U)
5823#define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
5824#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
5825#define DMA_SxCR_CHSEL_0 (0x1U << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */
5826#define DMA_SxCR_CHSEL_1 (0x2U << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */
5827#define DMA_SxCR_CHSEL_2 (0x4U << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */
5828#define DMA_SxCR_MBURST_Pos (23U)
5829#define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
5830#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
5831#define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
5832#define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
5833#define DMA_SxCR_PBURST_Pos (21U)
5834#define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
5835#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
5836#define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
5837#define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
5838#define DMA_SxCR_CT_Pos (19U)
5839#define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
5840#define DMA_SxCR_CT DMA_SxCR_CT_Msk
5841#define DMA_SxCR_DBM_Pos (18U)
5842#define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
5843#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
5844#define DMA_SxCR_PL_Pos (16U)
5845#define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
5846#define DMA_SxCR_PL DMA_SxCR_PL_Msk
5847#define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
5848#define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
5849#define DMA_SxCR_PINCOS_Pos (15U)
5850#define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
5851#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
5852#define DMA_SxCR_MSIZE_Pos (13U)
5853#define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
5854#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
5855#define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
5856#define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
5857#define DMA_SxCR_PSIZE_Pos (11U)
5858#define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
5859#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
5860#define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
5861#define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
5862#define DMA_SxCR_MINC_Pos (10U)
5863#define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
5864#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
5865#define DMA_SxCR_PINC_Pos (9U)
5866#define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
5867#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
5868#define DMA_SxCR_CIRC_Pos (8U)
5869#define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
5870#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
5871#define DMA_SxCR_DIR_Pos (6U)
5872#define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
5873#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
5874#define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
5875#define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
5876#define DMA_SxCR_PFCTRL_Pos (5U)
5877#define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
5878#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
5879#define DMA_SxCR_TCIE_Pos (4U)
5880#define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
5881#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
5882#define DMA_SxCR_HTIE_Pos (3U)
5883#define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
5884#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
5885#define DMA_SxCR_TEIE_Pos (2U)
5886#define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
5887#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
5888#define DMA_SxCR_DMEIE_Pos (1U)
5889#define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
5890#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
5891#define DMA_SxCR_EN_Pos (0U)
5892#define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
5893#define DMA_SxCR_EN DMA_SxCR_EN_Msk
5894
5895/* Legacy defines */
5896#define DMA_SxCR_ACK_Pos (20U)
5897#define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
5898#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
5899
5900/******************** Bits definition for DMA_SxCNDTR register **************/
5901#define DMA_SxNDT_Pos (0U)
5902#define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
5903#define DMA_SxNDT DMA_SxNDT_Msk
5904#define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
5905#define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
5906#define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
5907#define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
5908#define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
5909#define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
5910#define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
5911#define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
5912#define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
5913#define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
5914#define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
5915#define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
5916#define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
5917#define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
5918#define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
5919#define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
5920
5921/******************** Bits definition for DMA_SxFCR register ****************/
5922#define DMA_SxFCR_FEIE_Pos (7U)
5923#define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
5924#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
5925#define DMA_SxFCR_FS_Pos (3U)
5926#define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
5927#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
5928#define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
5929#define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
5930#define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
5931#define DMA_SxFCR_DMDIS_Pos (2U)
5932#define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
5933#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
5934#define DMA_SxFCR_FTH_Pos (0U)
5935#define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
5936#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
5937#define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
5938#define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
5939
5940/******************** Bits definition for DMA_LISR register *****************/
5941#define DMA_LISR_TCIF3_Pos (27U)
5942#define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
5943#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
5944#define DMA_LISR_HTIF3_Pos (26U)
5945#define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
5946#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
5947#define DMA_LISR_TEIF3_Pos (25U)
5948#define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
5949#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
5950#define DMA_LISR_DMEIF3_Pos (24U)
5951#define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
5952#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
5953#define DMA_LISR_FEIF3_Pos (22U)
5954#define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
5955#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
5956#define DMA_LISR_TCIF2_Pos (21U)
5957#define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
5958#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
5959#define DMA_LISR_HTIF2_Pos (20U)
5960#define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
5961#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
5962#define DMA_LISR_TEIF2_Pos (19U)
5963#define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
5964#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
5965#define DMA_LISR_DMEIF2_Pos (18U)
5966#define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
5967#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
5968#define DMA_LISR_FEIF2_Pos (16U)
5969#define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
5970#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
5971#define DMA_LISR_TCIF1_Pos (11U)
5972#define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
5973#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
5974#define DMA_LISR_HTIF1_Pos (10U)
5975#define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
5976#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
5977#define DMA_LISR_TEIF1_Pos (9U)
5978#define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
5979#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
5980#define DMA_LISR_DMEIF1_Pos (8U)
5981#define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
5982#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
5983#define DMA_LISR_FEIF1_Pos (6U)
5984#define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
5985#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
5986#define DMA_LISR_TCIF0_Pos (5U)
5987#define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
5988#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
5989#define DMA_LISR_HTIF0_Pos (4U)
5990#define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
5991#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
5992#define DMA_LISR_TEIF0_Pos (3U)
5993#define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
5994#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
5995#define DMA_LISR_DMEIF0_Pos (2U)
5996#define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
5997#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
5998#define DMA_LISR_FEIF0_Pos (0U)
5999#define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
6000#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
6001
6002/******************** Bits definition for DMA_HISR register *****************/
6003#define DMA_HISR_TCIF7_Pos (27U)
6004#define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
6005#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
6006#define DMA_HISR_HTIF7_Pos (26U)
6007#define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
6008#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
6009#define DMA_HISR_TEIF7_Pos (25U)
6010#define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
6011#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
6012#define DMA_HISR_DMEIF7_Pos (24U)
6013#define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
6014#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
6015#define DMA_HISR_FEIF7_Pos (22U)
6016#define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
6017#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
6018#define DMA_HISR_TCIF6_Pos (21U)
6019#define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
6020#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
6021#define DMA_HISR_HTIF6_Pos (20U)
6022#define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
6023#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
6024#define DMA_HISR_TEIF6_Pos (19U)
6025#define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
6026#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
6027#define DMA_HISR_DMEIF6_Pos (18U)
6028#define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
6029#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
6030#define DMA_HISR_FEIF6_Pos (16U)
6031#define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
6032#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
6033#define DMA_HISR_TCIF5_Pos (11U)
6034#define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
6035#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
6036#define DMA_HISR_HTIF5_Pos (10U)
6037#define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
6038#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
6039#define DMA_HISR_TEIF5_Pos (9U)
6040#define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
6041#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
6042#define DMA_HISR_DMEIF5_Pos (8U)
6043#define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
6044#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
6045#define DMA_HISR_FEIF5_Pos (6U)
6046#define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
6047#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
6048#define DMA_HISR_TCIF4_Pos (5U)
6049#define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
6050#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
6051#define DMA_HISR_HTIF4_Pos (4U)
6052#define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
6053#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
6054#define DMA_HISR_TEIF4_Pos (3U)
6055#define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
6056#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
6057#define DMA_HISR_DMEIF4_Pos (2U)
6058#define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
6059#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
6060#define DMA_HISR_FEIF4_Pos (0U)
6061#define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
6062#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
6063
6064/******************** Bits definition for DMA_LIFCR register ****************/
6065#define DMA_LIFCR_CTCIF3_Pos (27U)
6066#define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
6067#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
6068#define DMA_LIFCR_CHTIF3_Pos (26U)
6069#define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
6070#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
6071#define DMA_LIFCR_CTEIF3_Pos (25U)
6072#define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
6073#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
6074#define DMA_LIFCR_CDMEIF3_Pos (24U)
6075#define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
6076#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
6077#define DMA_LIFCR_CFEIF3_Pos (22U)
6078#define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
6079#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
6080#define DMA_LIFCR_CTCIF2_Pos (21U)
6081#define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
6082#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
6083#define DMA_LIFCR_CHTIF2_Pos (20U)
6084#define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
6085#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
6086#define DMA_LIFCR_CTEIF2_Pos (19U)
6087#define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
6088#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
6089#define DMA_LIFCR_CDMEIF2_Pos (18U)
6090#define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
6091#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
6092#define DMA_LIFCR_CFEIF2_Pos (16U)
6093#define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
6094#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
6095#define DMA_LIFCR_CTCIF1_Pos (11U)
6096#define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
6097#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
6098#define DMA_LIFCR_CHTIF1_Pos (10U)
6099#define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
6100#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
6101#define DMA_LIFCR_CTEIF1_Pos (9U)
6102#define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
6103#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
6104#define DMA_LIFCR_CDMEIF1_Pos (8U)
6105#define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
6106#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
6107#define DMA_LIFCR_CFEIF1_Pos (6U)
6108#define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
6109#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
6110#define DMA_LIFCR_CTCIF0_Pos (5U)
6111#define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
6112#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
6113#define DMA_LIFCR_CHTIF0_Pos (4U)
6114#define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
6115#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
6116#define DMA_LIFCR_CTEIF0_Pos (3U)
6117#define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
6118#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
6119#define DMA_LIFCR_CDMEIF0_Pos (2U)
6120#define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
6121#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
6122#define DMA_LIFCR_CFEIF0_Pos (0U)
6123#define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
6124#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
6125
6126/******************** Bits definition for DMA_HIFCR register ****************/
6127#define DMA_HIFCR_CTCIF7_Pos (27U)
6128#define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
6129#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
6130#define DMA_HIFCR_CHTIF7_Pos (26U)
6131#define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
6132#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
6133#define DMA_HIFCR_CTEIF7_Pos (25U)
6134#define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
6135#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
6136#define DMA_HIFCR_CDMEIF7_Pos (24U)
6137#define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
6138#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
6139#define DMA_HIFCR_CFEIF7_Pos (22U)
6140#define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
6141#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
6142#define DMA_HIFCR_CTCIF6_Pos (21U)
6143#define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
6144#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
6145#define DMA_HIFCR_CHTIF6_Pos (20U)
6146#define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
6147#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
6148#define DMA_HIFCR_CTEIF6_Pos (19U)
6149#define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
6150#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
6151#define DMA_HIFCR_CDMEIF6_Pos (18U)
6152#define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
6153#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
6154#define DMA_HIFCR_CFEIF6_Pos (16U)
6155#define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
6156#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
6157#define DMA_HIFCR_CTCIF5_Pos (11U)
6158#define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
6159#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
6160#define DMA_HIFCR_CHTIF5_Pos (10U)
6161#define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
6162#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
6163#define DMA_HIFCR_CTEIF5_Pos (9U)
6164#define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
6165#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
6166#define DMA_HIFCR_CDMEIF5_Pos (8U)
6167#define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
6168#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
6169#define DMA_HIFCR_CFEIF5_Pos (6U)
6170#define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
6171#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
6172#define DMA_HIFCR_CTCIF4_Pos (5U)
6173#define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
6174#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
6175#define DMA_HIFCR_CHTIF4_Pos (4U)
6176#define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
6177#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
6178#define DMA_HIFCR_CTEIF4_Pos (3U)
6179#define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
6180#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
6181#define DMA_HIFCR_CDMEIF4_Pos (2U)
6182#define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
6183#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
6184#define DMA_HIFCR_CFEIF4_Pos (0U)
6185#define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
6186#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
6187
6188/****************** Bit definition for DMA_SxPAR register ********************/
6189#define DMA_SxPAR_PA_Pos (0U)
6190#define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
6191#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
6192
6193/****************** Bit definition for DMA_SxM0AR register ********************/
6194#define DMA_SxM0AR_M0A_Pos (0U)
6195#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
6196#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
6197
6198/****************** Bit definition for DMA_SxM1AR register ********************/
6199#define DMA_SxM1AR_M1A_Pos (0U)
6200#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
6201#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
6202
6203/******************************************************************************/
6204/* */
6205/* External Interrupt/Event Controller */
6206/* */
6207/******************************************************************************/
6208/******************* Bit definition for EXTI_IMR register *******************/
6209#define EXTI_IMR_MR0_Pos (0U)
6210#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
6211#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
6212#define EXTI_IMR_MR1_Pos (1U)
6213#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
6214#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
6215#define EXTI_IMR_MR2_Pos (2U)
6216#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
6217#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
6218#define EXTI_IMR_MR3_Pos (3U)
6219#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
6220#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
6221#define EXTI_IMR_MR4_Pos (4U)
6222#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
6223#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
6224#define EXTI_IMR_MR5_Pos (5U)
6225#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
6226#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
6227#define EXTI_IMR_MR6_Pos (6U)
6228#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
6229#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
6230#define EXTI_IMR_MR7_Pos (7U)
6231#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
6232#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
6233#define EXTI_IMR_MR8_Pos (8U)
6234#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
6235#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
6236#define EXTI_IMR_MR9_Pos (9U)
6237#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
6238#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
6239#define EXTI_IMR_MR10_Pos (10U)
6240#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
6241#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
6242#define EXTI_IMR_MR11_Pos (11U)
6243#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
6244#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
6245#define EXTI_IMR_MR12_Pos (12U)
6246#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
6247#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
6248#define EXTI_IMR_MR13_Pos (13U)
6249#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
6250#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
6251#define EXTI_IMR_MR14_Pos (14U)
6252#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
6253#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
6254#define EXTI_IMR_MR15_Pos (15U)
6255#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
6256#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
6257#define EXTI_IMR_MR16_Pos (16U)
6258#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
6259#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
6260#define EXTI_IMR_MR17_Pos (17U)
6261#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
6262#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
6263#define EXTI_IMR_MR18_Pos (18U)
6264#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
6265#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
6266#define EXTI_IMR_MR19_Pos (19U)
6267#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
6268#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
6269#define EXTI_IMR_MR20_Pos (20U)
6270#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
6271#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
6272#define EXTI_IMR_MR21_Pos (21U)
6273#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
6274#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
6275#define EXTI_IMR_MR22_Pos (22U)
6276#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
6277#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
6278
6279/* Reference Defines */
6280#define EXTI_IMR_IM0 EXTI_IMR_MR0
6281#define EXTI_IMR_IM1 EXTI_IMR_MR1
6282#define EXTI_IMR_IM2 EXTI_IMR_MR2
6283#define EXTI_IMR_IM3 EXTI_IMR_MR3
6284#define EXTI_IMR_IM4 EXTI_IMR_MR4
6285#define EXTI_IMR_IM5 EXTI_IMR_MR5
6286#define EXTI_IMR_IM6 EXTI_IMR_MR6
6287#define EXTI_IMR_IM7 EXTI_IMR_MR7
6288#define EXTI_IMR_IM8 EXTI_IMR_MR8
6289#define EXTI_IMR_IM9 EXTI_IMR_MR9
6290#define EXTI_IMR_IM10 EXTI_IMR_MR10
6291#define EXTI_IMR_IM11 EXTI_IMR_MR11
6292#define EXTI_IMR_IM12 EXTI_IMR_MR12
6293#define EXTI_IMR_IM13 EXTI_IMR_MR13
6294#define EXTI_IMR_IM14 EXTI_IMR_MR14
6295#define EXTI_IMR_IM15 EXTI_IMR_MR15
6296#define EXTI_IMR_IM16 EXTI_IMR_MR16
6297#define EXTI_IMR_IM17 EXTI_IMR_MR17
6298#define EXTI_IMR_IM18 EXTI_IMR_MR18
6299#define EXTI_IMR_IM19 EXTI_IMR_MR19
6300#define EXTI_IMR_IM20 EXTI_IMR_MR20
6301#define EXTI_IMR_IM21 EXTI_IMR_MR21
6302#define EXTI_IMR_IM22 EXTI_IMR_MR22
6303#define EXTI_IMR_IM_Pos (0U)
6304#define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
6305#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
6306
6307/******************* Bit definition for EXTI_EMR register *******************/
6308#define EXTI_EMR_MR0_Pos (0U)
6309#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
6310#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
6311#define EXTI_EMR_MR1_Pos (1U)
6312#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
6313#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
6314#define EXTI_EMR_MR2_Pos (2U)
6315#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
6316#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
6317#define EXTI_EMR_MR3_Pos (3U)
6318#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
6319#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
6320#define EXTI_EMR_MR4_Pos (4U)
6321#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
6322#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
6323#define EXTI_EMR_MR5_Pos (5U)
6324#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
6325#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
6326#define EXTI_EMR_MR6_Pos (6U)
6327#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
6328#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
6329#define EXTI_EMR_MR7_Pos (7U)
6330#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
6331#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
6332#define EXTI_EMR_MR8_Pos (8U)
6333#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
6334#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
6335#define EXTI_EMR_MR9_Pos (9U)
6336#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
6337#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
6338#define EXTI_EMR_MR10_Pos (10U)
6339#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
6340#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
6341#define EXTI_EMR_MR11_Pos (11U)
6342#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
6343#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
6344#define EXTI_EMR_MR12_Pos (12U)
6345#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
6346#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
6347#define EXTI_EMR_MR13_Pos (13U)
6348#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
6349#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
6350#define EXTI_EMR_MR14_Pos (14U)
6351#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
6352#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
6353#define EXTI_EMR_MR15_Pos (15U)
6354#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
6355#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
6356#define EXTI_EMR_MR16_Pos (16U)
6357#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
6358#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
6359#define EXTI_EMR_MR17_Pos (17U)
6360#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
6361#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
6362#define EXTI_EMR_MR18_Pos (18U)
6363#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
6364#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
6365#define EXTI_EMR_MR19_Pos (19U)
6366#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
6367#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
6368#define EXTI_EMR_MR20_Pos (20U)
6369#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
6370#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
6371#define EXTI_EMR_MR21_Pos (21U)
6372#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
6373#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
6374#define EXTI_EMR_MR22_Pos (22U)
6375#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
6376#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
6377
6378/* Reference Defines */
6379#define EXTI_EMR_EM0 EXTI_EMR_MR0
6380#define EXTI_EMR_EM1 EXTI_EMR_MR1
6381#define EXTI_EMR_EM2 EXTI_EMR_MR2
6382#define EXTI_EMR_EM3 EXTI_EMR_MR3
6383#define EXTI_EMR_EM4 EXTI_EMR_MR4
6384#define EXTI_EMR_EM5 EXTI_EMR_MR5
6385#define EXTI_EMR_EM6 EXTI_EMR_MR6
6386#define EXTI_EMR_EM7 EXTI_EMR_MR7
6387#define EXTI_EMR_EM8 EXTI_EMR_MR8
6388#define EXTI_EMR_EM9 EXTI_EMR_MR9
6389#define EXTI_EMR_EM10 EXTI_EMR_MR10
6390#define EXTI_EMR_EM11 EXTI_EMR_MR11
6391#define EXTI_EMR_EM12 EXTI_EMR_MR12
6392#define EXTI_EMR_EM13 EXTI_EMR_MR13
6393#define EXTI_EMR_EM14 EXTI_EMR_MR14
6394#define EXTI_EMR_EM15 EXTI_EMR_MR15
6395#define EXTI_EMR_EM16 EXTI_EMR_MR16
6396#define EXTI_EMR_EM17 EXTI_EMR_MR17
6397#define EXTI_EMR_EM18 EXTI_EMR_MR18
6398#define EXTI_EMR_EM19 EXTI_EMR_MR19
6399#define EXTI_EMR_EM20 EXTI_EMR_MR20
6400#define EXTI_EMR_EM21 EXTI_EMR_MR21
6401#define EXTI_EMR_EM22 EXTI_EMR_MR22
6402
6403/****************** Bit definition for EXTI_RTSR register *******************/
6404#define EXTI_RTSR_TR0_Pos (0U)
6405#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
6406#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
6407#define EXTI_RTSR_TR1_Pos (1U)
6408#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
6409#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
6410#define EXTI_RTSR_TR2_Pos (2U)
6411#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
6412#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
6413#define EXTI_RTSR_TR3_Pos (3U)
6414#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
6415#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
6416#define EXTI_RTSR_TR4_Pos (4U)
6417#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
6418#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
6419#define EXTI_RTSR_TR5_Pos (5U)
6420#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
6421#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
6422#define EXTI_RTSR_TR6_Pos (6U)
6423#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
6424#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
6425#define EXTI_RTSR_TR7_Pos (7U)
6426#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
6427#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
6428#define EXTI_RTSR_TR8_Pos (8U)
6429#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
6430#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
6431#define EXTI_RTSR_TR9_Pos (9U)
6432#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
6433#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
6434#define EXTI_RTSR_TR10_Pos (10U)
6435#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
6436#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
6437#define EXTI_RTSR_TR11_Pos (11U)
6438#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
6439#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
6440#define EXTI_RTSR_TR12_Pos (12U)
6441#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
6442#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
6443#define EXTI_RTSR_TR13_Pos (13U)
6444#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
6445#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
6446#define EXTI_RTSR_TR14_Pos (14U)
6447#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
6448#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
6449#define EXTI_RTSR_TR15_Pos (15U)
6450#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
6451#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
6452#define EXTI_RTSR_TR16_Pos (16U)
6453#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
6454#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
6455#define EXTI_RTSR_TR17_Pos (17U)
6456#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
6457#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
6458#define EXTI_RTSR_TR18_Pos (18U)
6459#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
6460#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
6461#define EXTI_RTSR_TR19_Pos (19U)
6462#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
6463#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
6464#define EXTI_RTSR_TR20_Pos (20U)
6465#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
6466#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
6467#define EXTI_RTSR_TR21_Pos (21U)
6468#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
6469#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
6470#define EXTI_RTSR_TR22_Pos (22U)
6471#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
6472#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
6473
6474/****************** Bit definition for EXTI_FTSR register *******************/
6475#define EXTI_FTSR_TR0_Pos (0U)
6476#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
6477#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
6478#define EXTI_FTSR_TR1_Pos (1U)
6479#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
6480#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
6481#define EXTI_FTSR_TR2_Pos (2U)
6482#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
6483#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
6484#define EXTI_FTSR_TR3_Pos (3U)
6485#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
6486#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
6487#define EXTI_FTSR_TR4_Pos (4U)
6488#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
6489#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
6490#define EXTI_FTSR_TR5_Pos (5U)
6491#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
6492#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
6493#define EXTI_FTSR_TR6_Pos (6U)
6494#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
6495#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
6496#define EXTI_FTSR_TR7_Pos (7U)
6497#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
6498#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
6499#define EXTI_FTSR_TR8_Pos (8U)
6500#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
6501#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
6502#define EXTI_FTSR_TR9_Pos (9U)
6503#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
6504#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
6505#define EXTI_FTSR_TR10_Pos (10U)
6506#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
6507#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
6508#define EXTI_FTSR_TR11_Pos (11U)
6509#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
6510#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
6511#define EXTI_FTSR_TR12_Pos (12U)
6512#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
6513#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
6514#define EXTI_FTSR_TR13_Pos (13U)
6515#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
6516#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
6517#define EXTI_FTSR_TR14_Pos (14U)
6518#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
6519#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
6520#define EXTI_FTSR_TR15_Pos (15U)
6521#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
6522#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
6523#define EXTI_FTSR_TR16_Pos (16U)
6524#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
6525#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
6526#define EXTI_FTSR_TR17_Pos (17U)
6527#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
6528#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
6529#define EXTI_FTSR_TR18_Pos (18U)
6530#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
6531#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
6532#define EXTI_FTSR_TR19_Pos (19U)
6533#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
6534#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
6535#define EXTI_FTSR_TR20_Pos (20U)
6536#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
6537#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
6538#define EXTI_FTSR_TR21_Pos (21U)
6539#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
6540#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
6541#define EXTI_FTSR_TR22_Pos (22U)
6542#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
6543#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
6544
6545/****************** Bit definition for EXTI_SWIER register ******************/
6546#define EXTI_SWIER_SWIER0_Pos (0U)
6547#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
6548#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
6549#define EXTI_SWIER_SWIER1_Pos (1U)
6550#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
6551#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
6552#define EXTI_SWIER_SWIER2_Pos (2U)
6553#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
6554#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
6555#define EXTI_SWIER_SWIER3_Pos (3U)
6556#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
6557#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
6558#define EXTI_SWIER_SWIER4_Pos (4U)
6559#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
6560#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
6561#define EXTI_SWIER_SWIER5_Pos (5U)
6562#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
6563#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
6564#define EXTI_SWIER_SWIER6_Pos (6U)
6565#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
6566#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
6567#define EXTI_SWIER_SWIER7_Pos (7U)
6568#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
6569#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
6570#define EXTI_SWIER_SWIER8_Pos (8U)
6571#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
6572#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
6573#define EXTI_SWIER_SWIER9_Pos (9U)
6574#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
6575#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
6576#define EXTI_SWIER_SWIER10_Pos (10U)
6577#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
6578#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
6579#define EXTI_SWIER_SWIER11_Pos (11U)
6580#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
6581#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
6582#define EXTI_SWIER_SWIER12_Pos (12U)
6583#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
6584#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
6585#define EXTI_SWIER_SWIER13_Pos (13U)
6586#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
6587#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
6588#define EXTI_SWIER_SWIER14_Pos (14U)
6589#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
6590#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
6591#define EXTI_SWIER_SWIER15_Pos (15U)
6592#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
6593#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
6594#define EXTI_SWIER_SWIER16_Pos (16U)
6595#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
6596#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
6597#define EXTI_SWIER_SWIER17_Pos (17U)
6598#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
6599#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
6600#define EXTI_SWIER_SWIER18_Pos (18U)
6601#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
6602#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
6603#define EXTI_SWIER_SWIER19_Pos (19U)
6604#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
6605#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
6606#define EXTI_SWIER_SWIER20_Pos (20U)
6607#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
6608#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
6609#define EXTI_SWIER_SWIER21_Pos (21U)
6610#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
6611#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
6612#define EXTI_SWIER_SWIER22_Pos (22U)
6613#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
6614#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
6615
6616/******************* Bit definition for EXTI_PR register ********************/
6617#define EXTI_PR_PR0_Pos (0U)
6618#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
6619#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
6620#define EXTI_PR_PR1_Pos (1U)
6621#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
6622#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
6623#define EXTI_PR_PR2_Pos (2U)
6624#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
6625#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
6626#define EXTI_PR_PR3_Pos (3U)
6627#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
6628#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
6629#define EXTI_PR_PR4_Pos (4U)
6630#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
6631#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
6632#define EXTI_PR_PR5_Pos (5U)
6633#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
6634#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
6635#define EXTI_PR_PR6_Pos (6U)
6636#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
6637#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
6638#define EXTI_PR_PR7_Pos (7U)
6639#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
6640#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
6641#define EXTI_PR_PR8_Pos (8U)
6642#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
6643#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
6644#define EXTI_PR_PR9_Pos (9U)
6645#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
6646#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
6647#define EXTI_PR_PR10_Pos (10U)
6648#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
6649#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
6650#define EXTI_PR_PR11_Pos (11U)
6651#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
6652#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
6653#define EXTI_PR_PR12_Pos (12U)
6654#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
6655#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
6656#define EXTI_PR_PR13_Pos (13U)
6657#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
6658#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
6659#define EXTI_PR_PR14_Pos (14U)
6660#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
6661#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
6662#define EXTI_PR_PR15_Pos (15U)
6663#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
6664#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
6665#define EXTI_PR_PR16_Pos (16U)
6666#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
6667#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
6668#define EXTI_PR_PR17_Pos (17U)
6669#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
6670#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
6671#define EXTI_PR_PR18_Pos (18U)
6672#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
6673#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
6674#define EXTI_PR_PR19_Pos (19U)
6675#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
6676#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
6677#define EXTI_PR_PR20_Pos (20U)
6678#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
6679#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
6680#define EXTI_PR_PR21_Pos (21U)
6681#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
6682#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
6683#define EXTI_PR_PR22_Pos (22U)
6684#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
6685#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
6686
6687/******************************************************************************/
6688/* */
6689/* FLASH */
6690/* */
6691/******************************************************************************/
6692/******************* Bits definition for FLASH_ACR register *****************/
6693#define FLASH_ACR_LATENCY_Pos (0U)
6694#define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
6695#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
6696#define FLASH_ACR_LATENCY_0WS 0x00000000U
6697#define FLASH_ACR_LATENCY_1WS 0x00000001U
6698#define FLASH_ACR_LATENCY_2WS 0x00000002U
6699#define FLASH_ACR_LATENCY_3WS 0x00000003U
6700#define FLASH_ACR_LATENCY_4WS 0x00000004U
6701#define FLASH_ACR_LATENCY_5WS 0x00000005U
6702#define FLASH_ACR_LATENCY_6WS 0x00000006U
6703#define FLASH_ACR_LATENCY_7WS 0x00000007U
6704
6705#define FLASH_ACR_PRFTEN_Pos (8U)
6706#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
6707#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
6708#define FLASH_ACR_ICEN_Pos (9U)
6709#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
6710#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
6711#define FLASH_ACR_DCEN_Pos (10U)
6712#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
6713#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
6714#define FLASH_ACR_ICRST_Pos (11U)
6715#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
6716#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
6717#define FLASH_ACR_DCRST_Pos (12U)
6718#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
6719#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
6720#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
6721#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
6722#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
6723#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
6724#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
6725#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
6726
6727/******************* Bits definition for FLASH_SR register ******************/
6728#define FLASH_SR_EOP_Pos (0U)
6729#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
6730#define FLASH_SR_EOP FLASH_SR_EOP_Msk
6731#define FLASH_SR_SOP_Pos (1U)
6732#define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
6733#define FLASH_SR_SOP FLASH_SR_SOP_Msk
6734#define FLASH_SR_WRPERR_Pos (4U)
6735#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
6736#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
6737#define FLASH_SR_PGAERR_Pos (5U)
6738#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
6739#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
6740#define FLASH_SR_PGPERR_Pos (6U)
6741#define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
6742#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
6743#define FLASH_SR_PGSERR_Pos (7U)
6744#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
6745#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
6746#define FLASH_SR_BSY_Pos (16U)
6747#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
6748#define FLASH_SR_BSY FLASH_SR_BSY_Msk
6749
6750/******************* Bits definition for FLASH_CR register ******************/
6751#define FLASH_CR_PG_Pos (0U)
6752#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
6753#define FLASH_CR_PG FLASH_CR_PG_Msk
6754#define FLASH_CR_SER_Pos (1U)
6755#define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
6756#define FLASH_CR_SER FLASH_CR_SER_Msk
6757#define FLASH_CR_MER_Pos (2U)
6758#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
6759#define FLASH_CR_MER FLASH_CR_MER_Msk
6760#define FLASH_CR_SNB_Pos (3U)
6761#define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
6762#define FLASH_CR_SNB FLASH_CR_SNB_Msk
6763#define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
6764#define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
6765#define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
6766#define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
6767#define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
6768#define FLASH_CR_PSIZE_Pos (8U)
6769#define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
6770#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
6771#define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
6772#define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
6773#define FLASH_CR_STRT_Pos (16U)
6774#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
6775#define FLASH_CR_STRT FLASH_CR_STRT_Msk
6776#define FLASH_CR_EOPIE_Pos (24U)
6777#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
6778#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
6779#define FLASH_CR_LOCK_Pos (31U)
6780#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
6781#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
6782
6783/******************* Bits definition for FLASH_OPTCR register ***************/
6784#define FLASH_OPTCR_OPTLOCK_Pos (0U)
6785#define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
6786#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
6787#define FLASH_OPTCR_OPTSTRT_Pos (1U)
6788#define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
6789#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
6790#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
6791#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
6792#define FLASH_OPTCR_BOR_LEV_Pos (2U)
6793#define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
6794#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
6795
6796#define FLASH_OPTCR_WDG_SW_Pos (5U)
6797#define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
6798#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
6799#define FLASH_OPTCR_nRST_STOP_Pos (6U)
6800#define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
6801#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
6802#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
6803#define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
6804#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
6805#define FLASH_OPTCR_RDP_Pos (8U)
6806#define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
6807#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
6808#define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
6809#define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
6810#define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
6811#define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
6812#define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
6813#define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
6814#define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
6815#define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
6816#define FLASH_OPTCR_nWRP_Pos (16U)
6817#define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
6818#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
6819#define FLASH_OPTCR_nWRP_0 (0x001U << FLASH_OPTCR_nWRP_Pos) /*!< 0x00010000 */
6820#define FLASH_OPTCR_nWRP_1 (0x002U << FLASH_OPTCR_nWRP_Pos) /*!< 0x00020000 */
6821#define FLASH_OPTCR_nWRP_2 (0x004U << FLASH_OPTCR_nWRP_Pos) /*!< 0x00040000 */
6822#define FLASH_OPTCR_nWRP_3 (0x008U << FLASH_OPTCR_nWRP_Pos) /*!< 0x00080000 */
6823#define FLASH_OPTCR_nWRP_4 (0x010U << FLASH_OPTCR_nWRP_Pos) /*!< 0x00100000 */
6824#define FLASH_OPTCR_nWRP_5 (0x020U << FLASH_OPTCR_nWRP_Pos) /*!< 0x00200000 */
6825#define FLASH_OPTCR_nWRP_6 (0x040U << FLASH_OPTCR_nWRP_Pos) /*!< 0x00400000 */
6826#define FLASH_OPTCR_nWRP_7 (0x080U << FLASH_OPTCR_nWRP_Pos) /*!< 0x00800000 */
6827#define FLASH_OPTCR_nWRP_8 (0x100U << FLASH_OPTCR_nWRP_Pos) /*!< 0x01000000 */
6828#define FLASH_OPTCR_nWRP_9 (0x200U << FLASH_OPTCR_nWRP_Pos) /*!< 0x02000000 */
6829#define FLASH_OPTCR_nWRP_10 (0x400U << FLASH_OPTCR_nWRP_Pos) /*!< 0x04000000 */
6830#define FLASH_OPTCR_nWRP_11 (0x800U << FLASH_OPTCR_nWRP_Pos) /*!< 0x08000000 */
6831
6832/******************************************************************************/
6833/* */
6834/* Flexible Static Memory Controller */
6835/* */
6836/******************************************************************************/
6837/****************** Bit definition for FSMC_BCR1 register *******************/
6838#define FSMC_BCR1_MBKEN_Pos (0U)
6839#define FSMC_BCR1_MBKEN_Msk (0x1U << FSMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
6840#define FSMC_BCR1_MBKEN FSMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
6841#define FSMC_BCR1_MUXEN_Pos (1U)
6842#define FSMC_BCR1_MUXEN_Msk (0x1U << FSMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
6843#define FSMC_BCR1_MUXEN FSMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
6844
6845#define FSMC_BCR1_MTYP_Pos (2U)
6846#define FSMC_BCR1_MTYP_Msk (0x3U << FSMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
6847#define FSMC_BCR1_MTYP FSMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
6848#define FSMC_BCR1_MTYP_0 (0x1U << FSMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
6849#define FSMC_BCR1_MTYP_1 (0x2U << FSMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
6850
6851#define FSMC_BCR1_MWID_Pos (4U)
6852#define FSMC_BCR1_MWID_Msk (0x3U << FSMC_BCR1_MWID_Pos) /*!< 0x00000030 */
6853#define FSMC_BCR1_MWID FSMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
6854#define FSMC_BCR1_MWID_0 (0x1U << FSMC_BCR1_MWID_Pos) /*!< 0x00000010 */
6855#define FSMC_BCR1_MWID_1 (0x2U << FSMC_BCR1_MWID_Pos) /*!< 0x00000020 */
6856
6857#define FSMC_BCR1_FACCEN_Pos (6U)
6858#define FSMC_BCR1_FACCEN_Msk (0x1U << FSMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
6859#define FSMC_BCR1_FACCEN FSMC_BCR1_FACCEN_Msk /*!<Flash access enable */
6860#define FSMC_BCR1_BURSTEN_Pos (8U)
6861#define FSMC_BCR1_BURSTEN_Msk (0x1U << FSMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
6862#define FSMC_BCR1_BURSTEN FSMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
6863#define FSMC_BCR1_WAITPOL_Pos (9U)
6864#define FSMC_BCR1_WAITPOL_Msk (0x1U << FSMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
6865#define FSMC_BCR1_WAITPOL FSMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
6866#define FSMC_BCR1_WRAPMOD_Pos (10U)
6867#define FSMC_BCR1_WRAPMOD_Msk (0x1U << FSMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */
6868#define FSMC_BCR1_WRAPMOD FSMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */
6869#define FSMC_BCR1_WAITCFG_Pos (11U)
6870#define FSMC_BCR1_WAITCFG_Msk (0x1U << FSMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
6871#define FSMC_BCR1_WAITCFG FSMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
6872#define FSMC_BCR1_WREN_Pos (12U)
6873#define FSMC_BCR1_WREN_Msk (0x1U << FSMC_BCR1_WREN_Pos) /*!< 0x00001000 */
6874#define FSMC_BCR1_WREN FSMC_BCR1_WREN_Msk /*!<Write enable bit */
6875#define FSMC_BCR1_WAITEN_Pos (13U)
6876#define FSMC_BCR1_WAITEN_Msk (0x1U << FSMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
6877#define FSMC_BCR1_WAITEN FSMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
6878#define FSMC_BCR1_EXTMOD_Pos (14U)
6879#define FSMC_BCR1_EXTMOD_Msk (0x1U << FSMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
6880#define FSMC_BCR1_EXTMOD FSMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
6881#define FSMC_BCR1_ASYNCWAIT_Pos (15U)
6882#define FSMC_BCR1_ASYNCWAIT_Msk (0x1U << FSMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
6883#define FSMC_BCR1_ASYNCWAIT FSMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
6884#define FSMC_BCR1_CBURSTRW_Pos (19U)
6885#define FSMC_BCR1_CBURSTRW_Msk (0x1U << FSMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
6886#define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
6887
6888/****************** Bit definition for FSMC_BCR2 register *******************/
6889#define FSMC_BCR2_MBKEN_Pos (0U)
6890#define FSMC_BCR2_MBKEN_Msk (0x1U << FSMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
6891#define FSMC_BCR2_MBKEN FSMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
6892#define FSMC_BCR2_MUXEN_Pos (1U)
6893#define FSMC_BCR2_MUXEN_Msk (0x1U << FSMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
6894#define FSMC_BCR2_MUXEN FSMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
6895
6896#define FSMC_BCR2_MTYP_Pos (2U)
6897#define FSMC_BCR2_MTYP_Msk (0x3U << FSMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
6898#define FSMC_BCR2_MTYP FSMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
6899#define FSMC_BCR2_MTYP_0 (0x1U << FSMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
6900#define FSMC_BCR2_MTYP_1 (0x2U << FSMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
6901
6902#define FSMC_BCR2_MWID_Pos (4U)
6903#define FSMC_BCR2_MWID_Msk (0x3U << FSMC_BCR2_MWID_Pos) /*!< 0x00000030 */
6904#define FSMC_BCR2_MWID FSMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
6905#define FSMC_BCR2_MWID_0 (0x1U << FSMC_BCR2_MWID_Pos) /*!< 0x00000010 */
6906#define FSMC_BCR2_MWID_1 (0x2U << FSMC_BCR2_MWID_Pos) /*!< 0x00000020 */
6907
6908#define FSMC_BCR2_FACCEN_Pos (6U)
6909#define FSMC_BCR2_FACCEN_Msk (0x1U << FSMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
6910#define FSMC_BCR2_FACCEN FSMC_BCR2_FACCEN_Msk /*!<Flash access enable */
6911#define FSMC_BCR2_BURSTEN_Pos (8U)
6912#define FSMC_BCR2_BURSTEN_Msk (0x1U << FSMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
6913#define FSMC_BCR2_BURSTEN FSMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
6914#define FSMC_BCR2_WAITPOL_Pos (9U)
6915#define FSMC_BCR2_WAITPOL_Msk (0x1U << FSMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
6916#define FSMC_BCR2_WAITPOL FSMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
6917#define FSMC_BCR2_WRAPMOD_Pos (10U)
6918#define FSMC_BCR2_WRAPMOD_Msk (0x1U << FSMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */
6919#define FSMC_BCR2_WRAPMOD FSMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */
6920#define FSMC_BCR2_WAITCFG_Pos (11U)
6921#define FSMC_BCR2_WAITCFG_Msk (0x1U << FSMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
6922#define FSMC_BCR2_WAITCFG FSMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
6923#define FSMC_BCR2_WREN_Pos (12U)
6924#define FSMC_BCR2_WREN_Msk (0x1U << FSMC_BCR2_WREN_Pos) /*!< 0x00001000 */
6925#define FSMC_BCR2_WREN FSMC_BCR2_WREN_Msk /*!<Write enable bit */
6926#define FSMC_BCR2_WAITEN_Pos (13U)
6927#define FSMC_BCR2_WAITEN_Msk (0x1U << FSMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
6928#define FSMC_BCR2_WAITEN FSMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
6929#define FSMC_BCR2_EXTMOD_Pos (14U)
6930#define FSMC_BCR2_EXTMOD_Msk (0x1U << FSMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
6931#define FSMC_BCR2_EXTMOD FSMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
6932#define FSMC_BCR2_ASYNCWAIT_Pos (15U)
6933#define FSMC_BCR2_ASYNCWAIT_Msk (0x1U << FSMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
6934#define FSMC_BCR2_ASYNCWAIT FSMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
6935#define FSMC_BCR2_CBURSTRW_Pos (19U)
6936#define FSMC_BCR2_CBURSTRW_Msk (0x1U << FSMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
6937#define FSMC_BCR2_CBURSTRW FSMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
6938
6939/****************** Bit definition for FSMC_BCR3 register *******************/
6940#define FSMC_BCR3_MBKEN_Pos (0U)
6941#define FSMC_BCR3_MBKEN_Msk (0x1U << FSMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
6942#define FSMC_BCR3_MBKEN FSMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
6943#define FSMC_BCR3_MUXEN_Pos (1U)
6944#define FSMC_BCR3_MUXEN_Msk (0x1U << FSMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
6945#define FSMC_BCR3_MUXEN FSMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
6946
6947#define FSMC_BCR3_MTYP_Pos (2U)
6948#define FSMC_BCR3_MTYP_Msk (0x3U << FSMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
6949#define FSMC_BCR3_MTYP FSMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
6950#define FSMC_BCR3_MTYP_0 (0x1U << FSMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
6951#define FSMC_BCR3_MTYP_1 (0x2U << FSMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
6952
6953#define FSMC_BCR3_MWID_Pos (4U)
6954#define FSMC_BCR3_MWID_Msk (0x3U << FSMC_BCR3_MWID_Pos) /*!< 0x00000030 */
6955#define FSMC_BCR3_MWID FSMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
6956#define FSMC_BCR3_MWID_0 (0x1U << FSMC_BCR3_MWID_Pos) /*!< 0x00000010 */
6957#define FSMC_BCR3_MWID_1 (0x2U << FSMC_BCR3_MWID_Pos) /*!< 0x00000020 */
6958
6959#define FSMC_BCR3_FACCEN_Pos (6U)
6960#define FSMC_BCR3_FACCEN_Msk (0x1U << FSMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
6961#define FSMC_BCR3_FACCEN FSMC_BCR3_FACCEN_Msk /*!<Flash access enable */
6962#define FSMC_BCR3_BURSTEN_Pos (8U)
6963#define FSMC_BCR3_BURSTEN_Msk (0x1U << FSMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
6964#define FSMC_BCR3_BURSTEN FSMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
6965#define FSMC_BCR3_WAITPOL_Pos (9U)
6966#define FSMC_BCR3_WAITPOL_Msk (0x1U << FSMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
6967#define FSMC_BCR3_WAITPOL FSMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
6968#define FSMC_BCR3_WRAPMOD_Pos (10U)
6969#define FSMC_BCR3_WRAPMOD_Msk (0x1U << FSMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */
6970#define FSMC_BCR3_WRAPMOD FSMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */
6971#define FSMC_BCR3_WAITCFG_Pos (11U)
6972#define FSMC_BCR3_WAITCFG_Msk (0x1U << FSMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
6973#define FSMC_BCR3_WAITCFG FSMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
6974#define FSMC_BCR3_WREN_Pos (12U)
6975#define FSMC_BCR3_WREN_Msk (0x1U << FSMC_BCR3_WREN_Pos) /*!< 0x00001000 */
6976#define FSMC_BCR3_WREN FSMC_BCR3_WREN_Msk /*!<Write enable bit */
6977#define FSMC_BCR3_WAITEN_Pos (13U)
6978#define FSMC_BCR3_WAITEN_Msk (0x1U << FSMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
6979#define FSMC_BCR3_WAITEN FSMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
6980#define FSMC_BCR3_EXTMOD_Pos (14U)
6981#define FSMC_BCR3_EXTMOD_Msk (0x1U << FSMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
6982#define FSMC_BCR3_EXTMOD FSMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
6983#define FSMC_BCR3_ASYNCWAIT_Pos (15U)
6984#define FSMC_BCR3_ASYNCWAIT_Msk (0x1U << FSMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
6985#define FSMC_BCR3_ASYNCWAIT FSMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
6986#define FSMC_BCR3_CBURSTRW_Pos (19U)
6987#define FSMC_BCR3_CBURSTRW_Msk (0x1U << FSMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
6988#define FSMC_BCR3_CBURSTRW FSMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
6989
6990/****************** Bit definition for FSMC_BCR4 register *******************/
6991#define FSMC_BCR4_MBKEN_Pos (0U)
6992#define FSMC_BCR4_MBKEN_Msk (0x1U << FSMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
6993#define FSMC_BCR4_MBKEN FSMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
6994#define FSMC_BCR4_MUXEN_Pos (1U)
6995#define FSMC_BCR4_MUXEN_Msk (0x1U << FSMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
6996#define FSMC_BCR4_MUXEN FSMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
6997
6998#define FSMC_BCR4_MTYP_Pos (2U)
6999#define FSMC_BCR4_MTYP_Msk (0x3U << FSMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
7000#define FSMC_BCR4_MTYP FSMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
7001#define FSMC_BCR4_MTYP_0 (0x1U << FSMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
7002#define FSMC_BCR4_MTYP_1 (0x2U << FSMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
7003
7004#define FSMC_BCR4_MWID_Pos (4U)
7005#define FSMC_BCR4_MWID_Msk (0x3U << FSMC_BCR4_MWID_Pos) /*!< 0x00000030 */
7006#define FSMC_BCR4_MWID FSMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
7007#define FSMC_BCR4_MWID_0 (0x1U << FSMC_BCR4_MWID_Pos) /*!< 0x00000010 */
7008#define FSMC_BCR4_MWID_1 (0x2U << FSMC_BCR4_MWID_Pos) /*!< 0x00000020 */
7009
7010#define FSMC_BCR4_FACCEN_Pos (6U)
7011#define FSMC_BCR4_FACCEN_Msk (0x1U << FSMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
7012#define FSMC_BCR4_FACCEN FSMC_BCR4_FACCEN_Msk /*!<Flash access enable */
7013#define FSMC_BCR4_BURSTEN_Pos (8U)
7014#define FSMC_BCR4_BURSTEN_Msk (0x1U << FSMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
7015#define FSMC_BCR4_BURSTEN FSMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
7016#define FSMC_BCR4_WAITPOL_Pos (9U)
7017#define FSMC_BCR4_WAITPOL_Msk (0x1U << FSMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
7018#define FSMC_BCR4_WAITPOL FSMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
7019#define FSMC_BCR4_WRAPMOD_Pos (10U)
7020#define FSMC_BCR4_WRAPMOD_Msk (0x1U << FSMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */
7021#define FSMC_BCR4_WRAPMOD FSMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */
7022#define FSMC_BCR4_WAITCFG_Pos (11U)
7023#define FSMC_BCR4_WAITCFG_Msk (0x1U << FSMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
7024#define FSMC_BCR4_WAITCFG FSMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
7025#define FSMC_BCR4_WREN_Pos (12U)
7026#define FSMC_BCR4_WREN_Msk (0x1U << FSMC_BCR4_WREN_Pos) /*!< 0x00001000 */
7027#define FSMC_BCR4_WREN FSMC_BCR4_WREN_Msk /*!<Write enable bit */
7028#define FSMC_BCR4_WAITEN_Pos (13U)
7029#define FSMC_BCR4_WAITEN_Msk (0x1U << FSMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
7030#define FSMC_BCR4_WAITEN FSMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
7031#define FSMC_BCR4_EXTMOD_Pos (14U)
7032#define FSMC_BCR4_EXTMOD_Msk (0x1U << FSMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
7033#define FSMC_BCR4_EXTMOD FSMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
7034#define FSMC_BCR4_ASYNCWAIT_Pos (15U)
7035#define FSMC_BCR4_ASYNCWAIT_Msk (0x1U << FSMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
7036#define FSMC_BCR4_ASYNCWAIT FSMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
7037#define FSMC_BCR4_CBURSTRW_Pos (19U)
7038#define FSMC_BCR4_CBURSTRW_Msk (0x1U << FSMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
7039#define FSMC_BCR4_CBURSTRW FSMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
7040
7041/****************** Bit definition for FSMC_BTR1 register ******************/
7042#define FSMC_BTR1_ADDSET_Pos (0U)
7043#define FSMC_BTR1_ADDSET_Msk (0xFU << FSMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
7044#define FSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7045#define FSMC_BTR1_ADDSET_0 (0x1U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
7046#define FSMC_BTR1_ADDSET_1 (0x2U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
7047#define FSMC_BTR1_ADDSET_2 (0x4U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
7048#define FSMC_BTR1_ADDSET_3 (0x8U << FSMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
7049
7050#define FSMC_BTR1_ADDHLD_Pos (4U)
7051#define FSMC_BTR1_ADDHLD_Msk (0xFU << FSMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
7052#define FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7053#define FSMC_BTR1_ADDHLD_0 (0x1U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
7054#define FSMC_BTR1_ADDHLD_1 (0x2U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
7055#define FSMC_BTR1_ADDHLD_2 (0x4U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
7056#define FSMC_BTR1_ADDHLD_3 (0x8U << FSMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
7057
7058#define FSMC_BTR1_DATAST_Pos (8U)
7059#define FSMC_BTR1_DATAST_Msk (0xFFU << FSMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
7060#define FSMC_BTR1_DATAST FSMC_BTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7061#define FSMC_BTR1_DATAST_0 (0x01U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
7062#define FSMC_BTR1_DATAST_1 (0x02U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
7063#define FSMC_BTR1_DATAST_2 (0x04U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
7064#define FSMC_BTR1_DATAST_3 (0x08U << FSMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
7065#define FSMC_BTR1_DATAST_4 (0x10U << FSMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
7066#define FSMC_BTR1_DATAST_5 (0x20U << FSMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
7067#define FSMC_BTR1_DATAST_6 (0x40U << FSMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
7068#define FSMC_BTR1_DATAST_7 (0x80U << FSMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
7069
7070#define FSMC_BTR1_BUSTURN_Pos (16U)
7071#define FSMC_BTR1_BUSTURN_Msk (0xFU << FSMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
7072#define FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7073#define FSMC_BTR1_BUSTURN_0 (0x1U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
7074#define FSMC_BTR1_BUSTURN_1 (0x2U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
7075#define FSMC_BTR1_BUSTURN_2 (0x4U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
7076#define FSMC_BTR1_BUSTURN_3 (0x8U << FSMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
7077
7078#define FSMC_BTR1_CLKDIV_Pos (20U)
7079#define FSMC_BTR1_CLKDIV_Msk (0xFU << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
7080#define FSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7081#define FSMC_BTR1_CLKDIV_0 (0x1U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
7082#define FSMC_BTR1_CLKDIV_1 (0x2U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
7083#define FSMC_BTR1_CLKDIV_2 (0x4U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
7084#define FSMC_BTR1_CLKDIV_3 (0x8U << FSMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
7085
7086#define FSMC_BTR1_DATLAT_Pos (24U)
7087#define FSMC_BTR1_DATLAT_Msk (0xFU << FSMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
7088#define FSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7089#define FSMC_BTR1_DATLAT_0 (0x1U << FSMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
7090#define FSMC_BTR1_DATLAT_1 (0x2U << FSMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
7091#define FSMC_BTR1_DATLAT_2 (0x4U << FSMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
7092#define FSMC_BTR1_DATLAT_3 (0x8U << FSMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
7093
7094#define FSMC_BTR1_ACCMOD_Pos (28U)
7095#define FSMC_BTR1_ACCMOD_Msk (0x3U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
7096#define FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7097#define FSMC_BTR1_ACCMOD_0 (0x1U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
7098#define FSMC_BTR1_ACCMOD_1 (0x2U << FSMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
7099
7100/****************** Bit definition for FSMC_BTR2 register *******************/
7101#define FSMC_BTR2_ADDSET_Pos (0U)
7102#define FSMC_BTR2_ADDSET_Msk (0xFU << FSMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
7103#define FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7104#define FSMC_BTR2_ADDSET_0 (0x1U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
7105#define FSMC_BTR2_ADDSET_1 (0x2U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
7106#define FSMC_BTR2_ADDSET_2 (0x4U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
7107#define FSMC_BTR2_ADDSET_3 (0x8U << FSMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
7108
7109#define FSMC_BTR2_ADDHLD_Pos (4U)
7110#define FSMC_BTR2_ADDHLD_Msk (0xFU << FSMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
7111#define FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7112#define FSMC_BTR2_ADDHLD_0 (0x1U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
7113#define FSMC_BTR2_ADDHLD_1 (0x2U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
7114#define FSMC_BTR2_ADDHLD_2 (0x4U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
7115#define FSMC_BTR2_ADDHLD_3 (0x8U << FSMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
7116
7117#define FSMC_BTR2_DATAST_Pos (8U)
7118#define FSMC_BTR2_DATAST_Msk (0xFFU << FSMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
7119#define FSMC_BTR2_DATAST FSMC_BTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7120#define FSMC_BTR2_DATAST_0 (0x01U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
7121#define FSMC_BTR2_DATAST_1 (0x02U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
7122#define FSMC_BTR2_DATAST_2 (0x04U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
7123#define FSMC_BTR2_DATAST_3 (0x08U << FSMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
7124#define FSMC_BTR2_DATAST_4 (0x10U << FSMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
7125#define FSMC_BTR2_DATAST_5 (0x20U << FSMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
7126#define FSMC_BTR2_DATAST_6 (0x40U << FSMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
7127#define FSMC_BTR2_DATAST_7 (0x80U << FSMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
7128
7129#define FSMC_BTR2_BUSTURN_Pos (16U)
7130#define FSMC_BTR2_BUSTURN_Msk (0xFU << FSMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
7131#define FSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7132#define FSMC_BTR2_BUSTURN_0 (0x1U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
7133#define FSMC_BTR2_BUSTURN_1 (0x2U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
7134#define FSMC_BTR2_BUSTURN_2 (0x4U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
7135#define FSMC_BTR2_BUSTURN_3 (0x8U << FSMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
7136
7137#define FSMC_BTR2_CLKDIV_Pos (20U)
7138#define FSMC_BTR2_CLKDIV_Msk (0xFU << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
7139#define FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7140#define FSMC_BTR2_CLKDIV_0 (0x1U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
7141#define FSMC_BTR2_CLKDIV_1 (0x2U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
7142#define FSMC_BTR2_CLKDIV_2 (0x4U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
7143#define FSMC_BTR2_CLKDIV_3 (0x8U << FSMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
7144
7145#define FSMC_BTR2_DATLAT_Pos (24U)
7146#define FSMC_BTR2_DATLAT_Msk (0xFU << FSMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
7147#define FSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7148#define FSMC_BTR2_DATLAT_0 (0x1U << FSMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
7149#define FSMC_BTR2_DATLAT_1 (0x2U << FSMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
7150#define FSMC_BTR2_DATLAT_2 (0x4U << FSMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
7151#define FSMC_BTR2_DATLAT_3 (0x8U << FSMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
7152
7153#define FSMC_BTR2_ACCMOD_Pos (28U)
7154#define FSMC_BTR2_ACCMOD_Msk (0x3U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
7155#define FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7156#define FSMC_BTR2_ACCMOD_0 (0x1U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
7157#define FSMC_BTR2_ACCMOD_1 (0x2U << FSMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
7158
7159/******************* Bit definition for FSMC_BTR3 register *******************/
7160#define FSMC_BTR3_ADDSET_Pos (0U)
7161#define FSMC_BTR3_ADDSET_Msk (0xFU << FSMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
7162#define FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7163#define FSMC_BTR3_ADDSET_0 (0x1U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
7164#define FSMC_BTR3_ADDSET_1 (0x2U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
7165#define FSMC_BTR3_ADDSET_2 (0x4U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
7166#define FSMC_BTR3_ADDSET_3 (0x8U << FSMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
7167
7168#define FSMC_BTR3_ADDHLD_Pos (4U)
7169#define FSMC_BTR3_ADDHLD_Msk (0xFU << FSMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
7170#define FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7171#define FSMC_BTR3_ADDHLD_0 (0x1U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
7172#define FSMC_BTR3_ADDHLD_1 (0x2U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
7173#define FSMC_BTR3_ADDHLD_2 (0x4U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
7174#define FSMC_BTR3_ADDHLD_3 (0x8U << FSMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
7175
7176#define FSMC_BTR3_DATAST_Pos (8U)
7177#define FSMC_BTR3_DATAST_Msk (0xFFU << FSMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
7178#define FSMC_BTR3_DATAST FSMC_BTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7179#define FSMC_BTR3_DATAST_0 (0x01U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
7180#define FSMC_BTR3_DATAST_1 (0x02U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
7181#define FSMC_BTR3_DATAST_2 (0x04U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
7182#define FSMC_BTR3_DATAST_3 (0x08U << FSMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
7183#define FSMC_BTR3_DATAST_4 (0x10U << FSMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
7184#define FSMC_BTR3_DATAST_5 (0x20U << FSMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
7185#define FSMC_BTR3_DATAST_6 (0x40U << FSMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
7186#define FSMC_BTR3_DATAST_7 (0x80U << FSMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
7187
7188#define FSMC_BTR3_BUSTURN_Pos (16U)
7189#define FSMC_BTR3_BUSTURN_Msk (0xFU << FSMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
7190#define FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7191#define FSMC_BTR3_BUSTURN_0 (0x1U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
7192#define FSMC_BTR3_BUSTURN_1 (0x2U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
7193#define FSMC_BTR3_BUSTURN_2 (0x4U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
7194#define FSMC_BTR3_BUSTURN_3 (0x8U << FSMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
7195
7196#define FSMC_BTR3_CLKDIV_Pos (20U)
7197#define FSMC_BTR3_CLKDIV_Msk (0xFU << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
7198#define FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7199#define FSMC_BTR3_CLKDIV_0 (0x1U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
7200#define FSMC_BTR3_CLKDIV_1 (0x2U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
7201#define FSMC_BTR3_CLKDIV_2 (0x4U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
7202#define FSMC_BTR3_CLKDIV_3 (0x8U << FSMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
7203
7204#define FSMC_BTR3_DATLAT_Pos (24U)
7205#define FSMC_BTR3_DATLAT_Msk (0xFU << FSMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
7206#define FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7207#define FSMC_BTR3_DATLAT_0 (0x1U << FSMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
7208#define FSMC_BTR3_DATLAT_1 (0x2U << FSMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
7209#define FSMC_BTR3_DATLAT_2 (0x4U << FSMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
7210#define FSMC_BTR3_DATLAT_3 (0x8U << FSMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
7211
7212#define FSMC_BTR3_ACCMOD_Pos (28U)
7213#define FSMC_BTR3_ACCMOD_Msk (0x3U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
7214#define FSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7215#define FSMC_BTR3_ACCMOD_0 (0x1U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
7216#define FSMC_BTR3_ACCMOD_1 (0x2U << FSMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
7217
7218/****************** Bit definition for FSMC_BTR4 register *******************/
7219#define FSMC_BTR4_ADDSET_Pos (0U)
7220#define FSMC_BTR4_ADDSET_Msk (0xFU << FSMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
7221#define FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7222#define FSMC_BTR4_ADDSET_0 (0x1U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
7223#define FSMC_BTR4_ADDSET_1 (0x2U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
7224#define FSMC_BTR4_ADDSET_2 (0x4U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
7225#define FSMC_BTR4_ADDSET_3 (0x8U << FSMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
7226
7227#define FSMC_BTR4_ADDHLD_Pos (4U)
7228#define FSMC_BTR4_ADDHLD_Msk (0xFU << FSMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
7229#define FSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7230#define FSMC_BTR4_ADDHLD_0 (0x1U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
7231#define FSMC_BTR4_ADDHLD_1 (0x2U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
7232#define FSMC_BTR4_ADDHLD_2 (0x4U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
7233#define FSMC_BTR4_ADDHLD_3 (0x8U << FSMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
7234
7235#define FSMC_BTR4_DATAST_Pos (8U)
7236#define FSMC_BTR4_DATAST_Msk (0xFFU << FSMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
7237#define FSMC_BTR4_DATAST FSMC_BTR4_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7238#define FSMC_BTR4_DATAST_0 (0x01U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
7239#define FSMC_BTR4_DATAST_1 (0x02U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
7240#define FSMC_BTR4_DATAST_2 (0x04U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
7241#define FSMC_BTR4_DATAST_3 (0x08U << FSMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
7242#define FSMC_BTR4_DATAST_4 (0x10U << FSMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
7243#define FSMC_BTR4_DATAST_5 (0x20U << FSMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
7244#define FSMC_BTR4_DATAST_6 (0x40U << FSMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
7245#define FSMC_BTR4_DATAST_7 (0x80U << FSMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
7246
7247#define FSMC_BTR4_BUSTURN_Pos (16U)
7248#define FSMC_BTR4_BUSTURN_Msk (0xFU << FSMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
7249#define FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7250#define FSMC_BTR4_BUSTURN_0 (0x1U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
7251#define FSMC_BTR4_BUSTURN_1 (0x2U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
7252#define FSMC_BTR4_BUSTURN_2 (0x4U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
7253#define FSMC_BTR4_BUSTURN_3 (0x8U << FSMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
7254
7255#define FSMC_BTR4_CLKDIV_Pos (20U)
7256#define FSMC_BTR4_CLKDIV_Msk (0xFU << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
7257#define FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7258#define FSMC_BTR4_CLKDIV_0 (0x1U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
7259#define FSMC_BTR4_CLKDIV_1 (0x2U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
7260#define FSMC_BTR4_CLKDIV_2 (0x4U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
7261#define FSMC_BTR4_CLKDIV_3 (0x8U << FSMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
7262
7263#define FSMC_BTR4_DATLAT_Pos (24U)
7264#define FSMC_BTR4_DATLAT_Msk (0xFU << FSMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
7265#define FSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7266#define FSMC_BTR4_DATLAT_0 (0x1U << FSMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
7267#define FSMC_BTR4_DATLAT_1 (0x2U << FSMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
7268#define FSMC_BTR4_DATLAT_2 (0x4U << FSMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
7269#define FSMC_BTR4_DATLAT_3 (0x8U << FSMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
7270
7271#define FSMC_BTR4_ACCMOD_Pos (28U)
7272#define FSMC_BTR4_ACCMOD_Msk (0x3U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
7273#define FSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7274#define FSMC_BTR4_ACCMOD_0 (0x1U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
7275#define FSMC_BTR4_ACCMOD_1 (0x2U << FSMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
7276
7277/****************** Bit definition for FSMC_BWTR1 register ******************/
7278#define FSMC_BWTR1_ADDSET_Pos (0U)
7279#define FSMC_BWTR1_ADDSET_Msk (0xFU << FSMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
7280#define FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7281#define FSMC_BWTR1_ADDSET_0 (0x1U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
7282#define FSMC_BWTR1_ADDSET_1 (0x2U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
7283#define FSMC_BWTR1_ADDSET_2 (0x4U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
7284#define FSMC_BWTR1_ADDSET_3 (0x8U << FSMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
7285
7286#define FSMC_BWTR1_ADDHLD_Pos (4U)
7287#define FSMC_BWTR1_ADDHLD_Msk (0xFU << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
7288#define FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7289#define FSMC_BWTR1_ADDHLD_0 (0x1U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
7290#define FSMC_BWTR1_ADDHLD_1 (0x2U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
7291#define FSMC_BWTR1_ADDHLD_2 (0x4U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
7292#define FSMC_BWTR1_ADDHLD_3 (0x8U << FSMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
7293
7294#define FSMC_BWTR1_DATAST_Pos (8U)
7295#define FSMC_BWTR1_DATAST_Msk (0xFFU << FSMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
7296#define FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7297#define FSMC_BWTR1_DATAST_0 (0x01U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
7298#define FSMC_BWTR1_DATAST_1 (0x02U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
7299#define FSMC_BWTR1_DATAST_2 (0x04U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
7300#define FSMC_BWTR1_DATAST_3 (0x08U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
7301#define FSMC_BWTR1_DATAST_4 (0x10U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
7302#define FSMC_BWTR1_DATAST_5 (0x20U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
7303#define FSMC_BWTR1_DATAST_6 (0x40U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
7304#define FSMC_BWTR1_DATAST_7 (0x80U << FSMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
7305
7306#define FSMC_BWTR1_BUSTURN_Pos (16U)
7307#define FSMC_BWTR1_BUSTURN_Msk (0xFU << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
7308#define FSMC_BWTR1_BUSTURN FSMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7309#define FSMC_BWTR1_BUSTURN_0 (0x1U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
7310#define FSMC_BWTR1_BUSTURN_1 (0x2U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
7311#define FSMC_BWTR1_BUSTURN_2 (0x4U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
7312#define FSMC_BWTR1_BUSTURN_3 (0x8U << FSMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
7313
7314#define FSMC_BWTR1_ACCMOD_Pos (28U)
7315#define FSMC_BWTR1_ACCMOD_Msk (0x3U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
7316#define FSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7317#define FSMC_BWTR1_ACCMOD_0 (0x1U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
7318#define FSMC_BWTR1_ACCMOD_1 (0x2U << FSMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
7319
7320/****************** Bit definition for FSMC_BWTR2 register ******************/
7321#define FSMC_BWTR2_ADDSET_Pos (0U)
7322#define FSMC_BWTR2_ADDSET_Msk (0xFU << FSMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
7323#define FSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7324#define FSMC_BWTR2_ADDSET_0 (0x1U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
7325#define FSMC_BWTR2_ADDSET_1 (0x2U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
7326#define FSMC_BWTR2_ADDSET_2 (0x4U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
7327#define FSMC_BWTR2_ADDSET_3 (0x8U << FSMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
7328
7329#define FSMC_BWTR2_ADDHLD_Pos (4U)
7330#define FSMC_BWTR2_ADDHLD_Msk (0xFU << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
7331#define FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7332#define FSMC_BWTR2_ADDHLD_0 (0x1U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
7333#define FSMC_BWTR2_ADDHLD_1 (0x2U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
7334#define FSMC_BWTR2_ADDHLD_2 (0x4U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
7335#define FSMC_BWTR2_ADDHLD_3 (0x8U << FSMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
7336
7337#define FSMC_BWTR2_DATAST_Pos (8U)
7338#define FSMC_BWTR2_DATAST_Msk (0xFFU << FSMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
7339#define FSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7340#define FSMC_BWTR2_DATAST_0 (0x01U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
7341#define FSMC_BWTR2_DATAST_1 (0x02U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
7342#define FSMC_BWTR2_DATAST_2 (0x04U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
7343#define FSMC_BWTR2_DATAST_3 (0x08U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
7344#define FSMC_BWTR2_DATAST_4 (0x10U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
7345#define FSMC_BWTR2_DATAST_5 (0x20U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
7346#define FSMC_BWTR2_DATAST_6 (0x40U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
7347#define FSMC_BWTR2_DATAST_7 (0x80U << FSMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
7348
7349#define FSMC_BWTR2_BUSTURN_Pos (16U)
7350#define FSMC_BWTR2_BUSTURN_Msk (0xFU << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
7351#define FSMC_BWTR2_BUSTURN FSMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7352#define FSMC_BWTR2_BUSTURN_0 (0x1U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
7353#define FSMC_BWTR2_BUSTURN_1 (0x2U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
7354#define FSMC_BWTR2_BUSTURN_2 (0x4U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
7355#define FSMC_BWTR2_BUSTURN_3 (0x8U << FSMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
7356
7357#define FSMC_BWTR2_ACCMOD_Pos (28U)
7358#define FSMC_BWTR2_ACCMOD_Msk (0x3U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
7359#define FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7360#define FSMC_BWTR2_ACCMOD_0 (0x1U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
7361#define FSMC_BWTR2_ACCMOD_1 (0x2U << FSMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
7362
7363/****************** Bit definition for FSMC_BWTR3 register ******************/
7364#define FSMC_BWTR3_ADDSET_Pos (0U)
7365#define FSMC_BWTR3_ADDSET_Msk (0xFU << FSMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
7366#define FSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7367#define FSMC_BWTR3_ADDSET_0 (0x1U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
7368#define FSMC_BWTR3_ADDSET_1 (0x2U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
7369#define FSMC_BWTR3_ADDSET_2 (0x4U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
7370#define FSMC_BWTR3_ADDSET_3 (0x8U << FSMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
7371
7372#define FSMC_BWTR3_ADDHLD_Pos (4U)
7373#define FSMC_BWTR3_ADDHLD_Msk (0xFU << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
7374#define FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7375#define FSMC_BWTR3_ADDHLD_0 (0x1U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
7376#define FSMC_BWTR3_ADDHLD_1 (0x2U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
7377#define FSMC_BWTR3_ADDHLD_2 (0x4U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
7378#define FSMC_BWTR3_ADDHLD_3 (0x8U << FSMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
7379
7380#define FSMC_BWTR3_DATAST_Pos (8U)
7381#define FSMC_BWTR3_DATAST_Msk (0xFFU << FSMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
7382#define FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_Msk /*!<DATAST [7:0] bits (Data-phase duration) */
7383#define FSMC_BWTR3_DATAST_0 (0x01U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
7384#define FSMC_BWTR3_DATAST_1 (0x02U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
7385#define FSMC_BWTR3_DATAST_2 (0x04U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
7386#define FSMC_BWTR3_DATAST_3 (0x08U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
7387#define FSMC_BWTR3_DATAST_4 (0x10U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
7388#define FSMC_BWTR3_DATAST_5 (0x20U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
7389#define FSMC_BWTR3_DATAST_6 (0x40U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
7390#define FSMC_BWTR3_DATAST_7 (0x80U << FSMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
7391
7392#define FSMC_BWTR3_BUSTURN_Pos (16U)
7393#define FSMC_BWTR3_BUSTURN_Msk (0xFU << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
7394#define FSMC_BWTR3_BUSTURN FSMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7395#define FSMC_BWTR3_BUSTURN_0 (0x1U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
7396#define FSMC_BWTR3_BUSTURN_1 (0x2U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
7397#define FSMC_BWTR3_BUSTURN_2 (0x4U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
7398#define FSMC_BWTR3_BUSTURN_3 (0x8U << FSMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
7399
7400#define FSMC_BWTR3_ACCMOD_Pos (28U)
7401#define FSMC_BWTR3_ACCMOD_Msk (0x3U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
7402#define FSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7403#define FSMC_BWTR3_ACCMOD_0 (0x1U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
7404#define FSMC_BWTR3_ACCMOD_1 (0x2U << FSMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
7405
7406/****************** Bit definition for FSMC_BWTR4 register ******************/
7407#define FSMC_BWTR4_ADDSET_Pos (0U)
7408#define FSMC_BWTR4_ADDSET_Msk (0xFU << FSMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
7409#define FSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7410#define FSMC_BWTR4_ADDSET_0 (0x1U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
7411#define FSMC_BWTR4_ADDSET_1 (0x2U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
7412#define FSMC_BWTR4_ADDSET_2 (0x4U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
7413#define FSMC_BWTR4_ADDSET_3 (0x8U << FSMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
7414
7415#define FSMC_BWTR4_ADDHLD_Pos (4U)
7416#define FSMC_BWTR4_ADDHLD_Msk (0xFU << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
7417#define FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7418#define FSMC_BWTR4_ADDHLD_0 (0x1U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
7419#define FSMC_BWTR4_ADDHLD_1 (0x2U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
7420#define FSMC_BWTR4_ADDHLD_2 (0x4U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
7421#define FSMC_BWTR4_ADDHLD_3 (0x8U << FSMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
7422
7423#define FSMC_BWTR4_DATAST_Pos (8U)
7424#define FSMC_BWTR4_DATAST_Msk (0xFFU << FSMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
7425#define FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7426#define FSMC_BWTR4_DATAST_0 (0x01U << FSMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
7427#define FSMC_BWTR4_DATAST_1 (0x02U << FSMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
7428#define FSMC_BWTR4_DATAST_2 (0x04U << FSMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
7429#define FSMC_BWTR4_DATAST_3 (0x08U << FSMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
7430#define FSMC_BWTR4_DATAST_4 (0x10U << FSMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
7431#define FSMC_BWTR4_DATAST_5 (0x20U << FSMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
7432#define FSMC_BWTR4_DATAST_6 (0x40U << FSMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
7433#define FSMC_BWTR4_DATAST_7 (0x80U << FSMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
7434
7435#define FSMC_BWTR4_BUSTURN_Pos (16U)
7436#define FSMC_BWTR4_BUSTURN_Msk (0xFU << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
7437#define FSMC_BWTR4_BUSTURN FSMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7438#define FSMC_BWTR4_BUSTURN_0 (0x1U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
7439#define FSMC_BWTR4_BUSTURN_1 (0x2U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
7440#define FSMC_BWTR4_BUSTURN_2 (0x4U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
7441#define FSMC_BWTR4_BUSTURN_3 (0x8U << FSMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
7442
7443#define FSMC_BWTR4_ACCMOD_Pos (28U)
7444#define FSMC_BWTR4_ACCMOD_Msk (0x3U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
7445#define FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7446#define FSMC_BWTR4_ACCMOD_0 (0x1U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
7447#define FSMC_BWTR4_ACCMOD_1 (0x2U << FSMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
7448
7449/****************** Bit definition for FSMC_PCR2 register *******************/
7450#define FSMC_PCR2_PWAITEN_Pos (1U)
7451#define FSMC_PCR2_PWAITEN_Msk (0x1U << FSMC_PCR2_PWAITEN_Pos) /*!< 0x00000002 */
7452#define FSMC_PCR2_PWAITEN FSMC_PCR2_PWAITEN_Msk /*!<Wait feature enable bit */
7453#define FSMC_PCR2_PBKEN_Pos (2U)
7454#define FSMC_PCR2_PBKEN_Msk (0x1U << FSMC_PCR2_PBKEN_Pos) /*!< 0x00000004 */
7455#define FSMC_PCR2_PBKEN FSMC_PCR2_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
7456#define FSMC_PCR2_PTYP_Pos (3U)
7457#define FSMC_PCR2_PTYP_Msk (0x1U << FSMC_PCR2_PTYP_Pos) /*!< 0x00000008 */
7458#define FSMC_PCR2_PTYP FSMC_PCR2_PTYP_Msk /*!<Memory type */
7459
7460#define FSMC_PCR2_PWID_Pos (4U)
7461#define FSMC_PCR2_PWID_Msk (0x3U << FSMC_PCR2_PWID_Pos) /*!< 0x00000030 */
7462#define FSMC_PCR2_PWID FSMC_PCR2_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
7463#define FSMC_PCR2_PWID_0 (0x1U << FSMC_PCR2_PWID_Pos) /*!< 0x00000010 */
7464#define FSMC_PCR2_PWID_1 (0x2U << FSMC_PCR2_PWID_Pos) /*!< 0x00000020 */
7465
7466#define FSMC_PCR2_ECCEN_Pos (6U)
7467#define FSMC_PCR2_ECCEN_Msk (0x1U << FSMC_PCR2_ECCEN_Pos) /*!< 0x00000040 */
7468#define FSMC_PCR2_ECCEN FSMC_PCR2_ECCEN_Msk /*!<ECC computation logic enable bit */
7469
7470#define FSMC_PCR2_TCLR_Pos (9U)
7471#define FSMC_PCR2_TCLR_Msk (0xFU << FSMC_PCR2_TCLR_Pos) /*!< 0x00001E00 */
7472#define FSMC_PCR2_TCLR FSMC_PCR2_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
7473#define FSMC_PCR2_TCLR_0 (0x1U << FSMC_PCR2_TCLR_Pos) /*!< 0x00000200 */
7474#define FSMC_PCR2_TCLR_1 (0x2U << FSMC_PCR2_TCLR_Pos) /*!< 0x00000400 */
7475#define FSMC_PCR2_TCLR_2 (0x4U << FSMC_PCR2_TCLR_Pos) /*!< 0x00000800 */
7476#define FSMC_PCR2_TCLR_3 (0x8U << FSMC_PCR2_TCLR_Pos) /*!< 0x00001000 */
7477
7478#define FSMC_PCR2_TAR_Pos (13U)
7479#define FSMC_PCR2_TAR_Msk (0xFU << FSMC_PCR2_TAR_Pos) /*!< 0x0001E000 */
7480#define FSMC_PCR2_TAR FSMC_PCR2_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
7481#define FSMC_PCR2_TAR_0 (0x1U << FSMC_PCR2_TAR_Pos) /*!< 0x00002000 */
7482#define FSMC_PCR2_TAR_1 (0x2U << FSMC_PCR2_TAR_Pos) /*!< 0x00004000 */
7483#define FSMC_PCR2_TAR_2 (0x4U << FSMC_PCR2_TAR_Pos) /*!< 0x00008000 */
7484#define FSMC_PCR2_TAR_3 (0x8U << FSMC_PCR2_TAR_Pos) /*!< 0x00010000 */
7485
7486#define FSMC_PCR2_ECCPS_Pos (17U)
7487#define FSMC_PCR2_ECCPS_Msk (0x7U << FSMC_PCR2_ECCPS_Pos) /*!< 0x000E0000 */
7488#define FSMC_PCR2_ECCPS FSMC_PCR2_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
7489#define FSMC_PCR2_ECCPS_0 (0x1U << FSMC_PCR2_ECCPS_Pos) /*!< 0x00020000 */
7490#define FSMC_PCR2_ECCPS_1 (0x2U << FSMC_PCR2_ECCPS_Pos) /*!< 0x00040000 */
7491#define FSMC_PCR2_ECCPS_2 (0x4U << FSMC_PCR2_ECCPS_Pos) /*!< 0x00080000 */
7492
7493/****************** Bit definition for FSMC_PCR3 register *******************/
7494#define FSMC_PCR3_PWAITEN_Pos (1U)
7495#define FSMC_PCR3_PWAITEN_Msk (0x1U << FSMC_PCR3_PWAITEN_Pos) /*!< 0x00000002 */
7496#define FSMC_PCR3_PWAITEN FSMC_PCR3_PWAITEN_Msk /*!<Wait feature enable bit */
7497#define FSMC_PCR3_PBKEN_Pos (2U)
7498#define FSMC_PCR3_PBKEN_Msk (0x1U << FSMC_PCR3_PBKEN_Pos) /*!< 0x00000004 */
7499#define FSMC_PCR3_PBKEN FSMC_PCR3_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
7500#define FSMC_PCR3_PTYP_Pos (3U)
7501#define FSMC_PCR3_PTYP_Msk (0x1U << FSMC_PCR3_PTYP_Pos) /*!< 0x00000008 */
7502#define FSMC_PCR3_PTYP FSMC_PCR3_PTYP_Msk /*!<Memory type */
7503
7504#define FSMC_PCR3_PWID_Pos (4U)
7505#define FSMC_PCR3_PWID_Msk (0x3U << FSMC_PCR3_PWID_Pos) /*!< 0x00000030 */
7506#define FSMC_PCR3_PWID FSMC_PCR3_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
7507#define FSMC_PCR3_PWID_0 (0x1U << FSMC_PCR3_PWID_Pos) /*!< 0x00000010 */
7508#define FSMC_PCR3_PWID_1 (0x2U << FSMC_PCR3_PWID_Pos) /*!< 0x00000020 */
7509
7510#define FSMC_PCR3_ECCEN_Pos (6U)
7511#define FSMC_PCR3_ECCEN_Msk (0x1U << FSMC_PCR3_ECCEN_Pos) /*!< 0x00000040 */
7512#define FSMC_PCR3_ECCEN FSMC_PCR3_ECCEN_Msk /*!<ECC computation logic enable bit */
7513
7514#define FSMC_PCR3_TCLR_Pos (9U)
7515#define FSMC_PCR3_TCLR_Msk (0xFU << FSMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */
7516#define FSMC_PCR3_TCLR FSMC_PCR3_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
7517#define FSMC_PCR3_TCLR_0 (0x1U << FSMC_PCR3_TCLR_Pos) /*!< 0x00000200 */
7518#define FSMC_PCR3_TCLR_1 (0x2U << FSMC_PCR3_TCLR_Pos) /*!< 0x00000400 */
7519#define FSMC_PCR3_TCLR_2 (0x4U << FSMC_PCR3_TCLR_Pos) /*!< 0x00000800 */
7520#define FSMC_PCR3_TCLR_3 (0x8U << FSMC_PCR3_TCLR_Pos) /*!< 0x00001000 */
7521
7522#define FSMC_PCR3_TAR_Pos (13U)
7523#define FSMC_PCR3_TAR_Msk (0xFU << FSMC_PCR3_TAR_Pos) /*!< 0x0001E000 */
7524#define FSMC_PCR3_TAR FSMC_PCR3_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
7525#define FSMC_PCR3_TAR_0 (0x1U << FSMC_PCR3_TAR_Pos) /*!< 0x00002000 */
7526#define FSMC_PCR3_TAR_1 (0x2U << FSMC_PCR3_TAR_Pos) /*!< 0x00004000 */
7527#define FSMC_PCR3_TAR_2 (0x4U << FSMC_PCR3_TAR_Pos) /*!< 0x00008000 */
7528#define FSMC_PCR3_TAR_3 (0x8U << FSMC_PCR3_TAR_Pos) /*!< 0x00010000 */
7529
7530#define FSMC_PCR3_ECCPS_Pos (17U)
7531#define FSMC_PCR3_ECCPS_Msk (0x7U << FSMC_PCR3_ECCPS_Pos) /*!< 0x000E0000 */
7532#define FSMC_PCR3_ECCPS FSMC_PCR3_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
7533#define FSMC_PCR3_ECCPS_0 (0x1U << FSMC_PCR3_ECCPS_Pos) /*!< 0x00020000 */
7534#define FSMC_PCR3_ECCPS_1 (0x2U << FSMC_PCR3_ECCPS_Pos) /*!< 0x00040000 */
7535#define FSMC_PCR3_ECCPS_2 (0x4U << FSMC_PCR3_ECCPS_Pos) /*!< 0x00080000 */
7536
7537/****************** Bit definition for FSMC_PCR4 register *******************/
7538#define FSMC_PCR4_PWAITEN_Pos (1U)
7539#define FSMC_PCR4_PWAITEN_Msk (0x1U << FSMC_PCR4_PWAITEN_Pos) /*!< 0x00000002 */
7540#define FSMC_PCR4_PWAITEN FSMC_PCR4_PWAITEN_Msk /*!<Wait feature enable bit */
7541#define FSMC_PCR4_PBKEN_Pos (2U)
7542#define FSMC_PCR4_PBKEN_Msk (0x1U << FSMC_PCR4_PBKEN_Pos) /*!< 0x00000004 */
7543#define FSMC_PCR4_PBKEN FSMC_PCR4_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
7544#define FSMC_PCR4_PTYP_Pos (3U)
7545#define FSMC_PCR4_PTYP_Msk (0x1U << FSMC_PCR4_PTYP_Pos) /*!< 0x00000008 */
7546#define FSMC_PCR4_PTYP FSMC_PCR4_PTYP_Msk /*!<Memory type */
7547
7548#define FSMC_PCR4_PWID_Pos (4U)
7549#define FSMC_PCR4_PWID_Msk (0x3U << FSMC_PCR4_PWID_Pos) /*!< 0x00000030 */
7550#define FSMC_PCR4_PWID FSMC_PCR4_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
7551#define FSMC_PCR4_PWID_0 (0x1U << FSMC_PCR4_PWID_Pos) /*!< 0x00000010 */
7552#define FSMC_PCR4_PWID_1 (0x2U << FSMC_PCR4_PWID_Pos) /*!< 0x00000020 */
7553
7554#define FSMC_PCR4_ECCEN_Pos (6U)
7555#define FSMC_PCR4_ECCEN_Msk (0x1U << FSMC_PCR4_ECCEN_Pos) /*!< 0x00000040 */
7556#define FSMC_PCR4_ECCEN FSMC_PCR4_ECCEN_Msk /*!<ECC computation logic enable bit */
7557
7558#define FSMC_PCR4_TCLR_Pos (9U)
7559#define FSMC_PCR4_TCLR_Msk (0xFU << FSMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */
7560#define FSMC_PCR4_TCLR FSMC_PCR4_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
7561#define FSMC_PCR4_TCLR_0 (0x1U << FSMC_PCR4_TCLR_Pos) /*!< 0x00000200 */
7562#define FSMC_PCR4_TCLR_1 (0x2U << FSMC_PCR4_TCLR_Pos) /*!< 0x00000400 */
7563#define FSMC_PCR4_TCLR_2 (0x4U << FSMC_PCR4_TCLR_Pos) /*!< 0x00000800 */
7564#define FSMC_PCR4_TCLR_3 (0x8U << FSMC_PCR4_TCLR_Pos) /*!< 0x00001000 */
7565
7566#define FSMC_PCR4_TAR_Pos (13U)
7567#define FSMC_PCR4_TAR_Msk (0xFU << FSMC_PCR4_TAR_Pos) /*!< 0x0001E000 */
7568#define FSMC_PCR4_TAR FSMC_PCR4_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
7569#define FSMC_PCR4_TAR_0 (0x1U << FSMC_PCR4_TAR_Pos) /*!< 0x00002000 */
7570#define FSMC_PCR4_TAR_1 (0x2U << FSMC_PCR4_TAR_Pos) /*!< 0x00004000 */
7571#define FSMC_PCR4_TAR_2 (0x4U << FSMC_PCR4_TAR_Pos) /*!< 0x00008000 */
7572#define FSMC_PCR4_TAR_3 (0x8U << FSMC_PCR4_TAR_Pos) /*!< 0x00010000 */
7573
7574#define FSMC_PCR4_ECCPS_Pos (17U)
7575#define FSMC_PCR4_ECCPS_Msk (0x7U << FSMC_PCR4_ECCPS_Pos) /*!< 0x000E0000 */
7576#define FSMC_PCR4_ECCPS FSMC_PCR4_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
7577#define FSMC_PCR4_ECCPS_0 (0x1U << FSMC_PCR4_ECCPS_Pos) /*!< 0x00020000 */
7578#define FSMC_PCR4_ECCPS_1 (0x2U << FSMC_PCR4_ECCPS_Pos) /*!< 0x00040000 */
7579#define FSMC_PCR4_ECCPS_2 (0x4U << FSMC_PCR4_ECCPS_Pos) /*!< 0x00080000 */
7580
7581/******************* Bit definition for FSMC_SR2 register *******************/
7582#define FSMC_SR2_IRS_Pos (0U)
7583#define FSMC_SR2_IRS_Msk (0x1U << FSMC_SR2_IRS_Pos) /*!< 0x00000001 */
7584#define FSMC_SR2_IRS FSMC_SR2_IRS_Msk /*!<Interrupt Rising Edge status */
7585#define FSMC_SR2_ILS_Pos (1U)
7586#define FSMC_SR2_ILS_Msk (0x1U << FSMC_SR2_ILS_Pos) /*!< 0x00000002 */
7587#define FSMC_SR2_ILS FSMC_SR2_ILS_Msk /*!<Interrupt Level status */
7588#define FSMC_SR2_IFS_Pos (2U)
7589#define FSMC_SR2_IFS_Msk (0x1U << FSMC_SR2_IFS_Pos) /*!< 0x00000004 */
7590#define FSMC_SR2_IFS FSMC_SR2_IFS_Msk /*!<Interrupt Falling Edge status */
7591#define FSMC_SR2_IREN_Pos (3U)
7592#define FSMC_SR2_IREN_Msk (0x1U << FSMC_SR2_IREN_Pos) /*!< 0x00000008 */
7593#define FSMC_SR2_IREN FSMC_SR2_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
7594#define FSMC_SR2_ILEN_Pos (4U)
7595#define FSMC_SR2_ILEN_Msk (0x1U << FSMC_SR2_ILEN_Pos) /*!< 0x00000010 */
7596#define FSMC_SR2_ILEN FSMC_SR2_ILEN_Msk /*!<Interrupt Level detection Enable bit */
7597#define FSMC_SR2_IFEN_Pos (5U)
7598#define FSMC_SR2_IFEN_Msk (0x1U << FSMC_SR2_IFEN_Pos) /*!< 0x00000020 */
7599#define FSMC_SR2_IFEN FSMC_SR2_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
7600#define FSMC_SR2_FEMPT_Pos (6U)
7601#define FSMC_SR2_FEMPT_Msk (0x1U << FSMC_SR2_FEMPT_Pos) /*!< 0x00000040 */
7602#define FSMC_SR2_FEMPT FSMC_SR2_FEMPT_Msk /*!<FIFO empty */
7603
7604/******************* Bit definition for FSMC_SR3 register *******************/
7605#define FSMC_SR3_IRS_Pos (0U)
7606#define FSMC_SR3_IRS_Msk (0x1U << FSMC_SR3_IRS_Pos) /*!< 0x00000001 */
7607#define FSMC_SR3_IRS FSMC_SR3_IRS_Msk /*!<Interrupt Rising Edge status */
7608#define FSMC_SR3_ILS_Pos (1U)
7609#define FSMC_SR3_ILS_Msk (0x1U << FSMC_SR3_ILS_Pos) /*!< 0x00000002 */
7610#define FSMC_SR3_ILS FSMC_SR3_ILS_Msk /*!<Interrupt Level status */
7611#define FSMC_SR3_IFS_Pos (2U)
7612#define FSMC_SR3_IFS_Msk (0x1U << FSMC_SR3_IFS_Pos) /*!< 0x00000004 */
7613#define FSMC_SR3_IFS FSMC_SR3_IFS_Msk /*!<Interrupt Falling Edge status */
7614#define FSMC_SR3_IREN_Pos (3U)
7615#define FSMC_SR3_IREN_Msk (0x1U << FSMC_SR3_IREN_Pos) /*!< 0x00000008 */
7616#define FSMC_SR3_IREN FSMC_SR3_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
7617#define FSMC_SR3_ILEN_Pos (4U)
7618#define FSMC_SR3_ILEN_Msk (0x1U << FSMC_SR3_ILEN_Pos) /*!< 0x00000010 */
7619#define FSMC_SR3_ILEN FSMC_SR3_ILEN_Msk /*!<Interrupt Level detection Enable bit */
7620#define FSMC_SR3_IFEN_Pos (5U)
7621#define FSMC_SR3_IFEN_Msk (0x1U << FSMC_SR3_IFEN_Pos) /*!< 0x00000020 */
7622#define FSMC_SR3_IFEN FSMC_SR3_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
7623#define FSMC_SR3_FEMPT_Pos (6U)
7624#define FSMC_SR3_FEMPT_Msk (0x1U << FSMC_SR3_FEMPT_Pos) /*!< 0x00000040 */
7625#define FSMC_SR3_FEMPT FSMC_SR3_FEMPT_Msk /*!<FIFO empty */
7626
7627/******************* Bit definition for FSMC_SR4 register *******************/
7628#define FSMC_SR4_IRS_Pos (0U)
7629#define FSMC_SR4_IRS_Msk (0x1U << FSMC_SR4_IRS_Pos) /*!< 0x00000001 */
7630#define FSMC_SR4_IRS FSMC_SR4_IRS_Msk /*!<Interrupt Rising Edge status */
7631#define FSMC_SR4_ILS_Pos (1U)
7632#define FSMC_SR4_ILS_Msk (0x1U << FSMC_SR4_ILS_Pos) /*!< 0x00000002 */
7633#define FSMC_SR4_ILS FSMC_SR4_ILS_Msk /*!<Interrupt Level status */
7634#define FSMC_SR4_IFS_Pos (2U)
7635#define FSMC_SR4_IFS_Msk (0x1U << FSMC_SR4_IFS_Pos) /*!< 0x00000004 */
7636#define FSMC_SR4_IFS FSMC_SR4_IFS_Msk /*!<Interrupt Falling Edge status */
7637#define FSMC_SR4_IREN_Pos (3U)
7638#define FSMC_SR4_IREN_Msk (0x1U << FSMC_SR4_IREN_Pos) /*!< 0x00000008 */
7639#define FSMC_SR4_IREN FSMC_SR4_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
7640#define FSMC_SR4_ILEN_Pos (4U)
7641#define FSMC_SR4_ILEN_Msk (0x1U << FSMC_SR4_ILEN_Pos) /*!< 0x00000010 */
7642#define FSMC_SR4_ILEN FSMC_SR4_ILEN_Msk /*!<Interrupt Level detection Enable bit */
7643#define FSMC_SR4_IFEN_Pos (5U)
7644#define FSMC_SR4_IFEN_Msk (0x1U << FSMC_SR4_IFEN_Pos) /*!< 0x00000020 */
7645#define FSMC_SR4_IFEN FSMC_SR4_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
7646#define FSMC_SR4_FEMPT_Pos (6U)
7647#define FSMC_SR4_FEMPT_Msk (0x1U << FSMC_SR4_FEMPT_Pos) /*!< 0x00000040 */
7648#define FSMC_SR4_FEMPT FSMC_SR4_FEMPT_Msk /*!<FIFO empty */
7649
7650/****************** Bit definition for FSMC_PMEM2 register ******************/
7651#define FSMC_PMEM2_MEMSET2_Pos (0U)
7652#define FSMC_PMEM2_MEMSET2_Msk (0xFFU << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x000000FF */
7653#define FSMC_PMEM2_MEMSET2 FSMC_PMEM2_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
7654#define FSMC_PMEM2_MEMSET2_0 (0x01U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000001 */
7655#define FSMC_PMEM2_MEMSET2_1 (0x02U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000002 */
7656#define FSMC_PMEM2_MEMSET2_2 (0x04U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000004 */
7657#define FSMC_PMEM2_MEMSET2_3 (0x08U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000008 */
7658#define FSMC_PMEM2_MEMSET2_4 (0x10U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000010 */
7659#define FSMC_PMEM2_MEMSET2_5 (0x20U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000020 */
7660#define FSMC_PMEM2_MEMSET2_6 (0x40U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000040 */
7661#define FSMC_PMEM2_MEMSET2_7 (0x80U << FSMC_PMEM2_MEMSET2_Pos) /*!< 0x00000080 */
7662
7663#define FSMC_PMEM2_MEMWAIT2_Pos (8U)
7664#define FSMC_PMEM2_MEMWAIT2_Msk (0xFFU << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x0000FF00 */
7665#define FSMC_PMEM2_MEMWAIT2 FSMC_PMEM2_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
7666#define FSMC_PMEM2_MEMWAIT2_0 (0x01U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000100 */
7667#define FSMC_PMEM2_MEMWAIT2_1 (0x02U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000200 */
7668#define FSMC_PMEM2_MEMWAIT2_2 (0x04U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000400 */
7669#define FSMC_PMEM2_MEMWAIT2_3 (0x08U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000800 */
7670#define FSMC_PMEM2_MEMWAIT2_4 (0x10U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00001000 */
7671#define FSMC_PMEM2_MEMWAIT2_5 (0x20U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00002000 */
7672#define FSMC_PMEM2_MEMWAIT2_6 (0x40U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00004000 */
7673#define FSMC_PMEM2_MEMWAIT2_7 (0x80U << FSMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00008000 */
7674
7675#define FSMC_PMEM2_MEMHOLD2_Pos (16U)
7676#define FSMC_PMEM2_MEMHOLD2_Msk (0xFFU << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00FF0000 */
7677#define FSMC_PMEM2_MEMHOLD2 FSMC_PMEM2_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
7678#define FSMC_PMEM2_MEMHOLD2_0 (0x01U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00010000 */
7679#define FSMC_PMEM2_MEMHOLD2_1 (0x02U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00020000 */
7680#define FSMC_PMEM2_MEMHOLD2_2 (0x04U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00040000 */
7681#define FSMC_PMEM2_MEMHOLD2_3 (0x08U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00080000 */
7682#define FSMC_PMEM2_MEMHOLD2_4 (0x10U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00100000 */
7683#define FSMC_PMEM2_MEMHOLD2_5 (0x20U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00200000 */
7684#define FSMC_PMEM2_MEMHOLD2_6 (0x40U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00400000 */
7685#define FSMC_PMEM2_MEMHOLD2_7 (0x80U << FSMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00800000 */
7686
7687#define FSMC_PMEM2_MEMHIZ2_Pos (24U)
7688#define FSMC_PMEM2_MEMHIZ2_Msk (0xFFU << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0xFF000000 */
7689#define FSMC_PMEM2_MEMHIZ2 FSMC_PMEM2_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
7690#define FSMC_PMEM2_MEMHIZ2_0 (0x01U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x01000000 */
7691#define FSMC_PMEM2_MEMHIZ2_1 (0x02U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x02000000 */
7692#define FSMC_PMEM2_MEMHIZ2_2 (0x04U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x04000000 */
7693#define FSMC_PMEM2_MEMHIZ2_3 (0x08U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x08000000 */
7694#define FSMC_PMEM2_MEMHIZ2_4 (0x10U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x10000000 */
7695#define FSMC_PMEM2_MEMHIZ2_5 (0x20U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x20000000 */
7696#define FSMC_PMEM2_MEMHIZ2_6 (0x40U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x40000000 */
7697#define FSMC_PMEM2_MEMHIZ2_7 (0x80U << FSMC_PMEM2_MEMHIZ2_Pos) /*!< 0x80000000 */
7698
7699/****************** Bit definition for FSMC_PMEM3 register ******************/
7700#define FSMC_PMEM3_MEMSET3_Pos (0U)
7701#define FSMC_PMEM3_MEMSET3_Msk (0xFFU << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x000000FF */
7702#define FSMC_PMEM3_MEMSET3 FSMC_PMEM3_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
7703#define FSMC_PMEM3_MEMSET3_0 (0x01U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000001 */
7704#define FSMC_PMEM3_MEMSET3_1 (0x02U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000002 */
7705#define FSMC_PMEM3_MEMSET3_2 (0x04U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000004 */
7706#define FSMC_PMEM3_MEMSET3_3 (0x08U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000008 */
7707#define FSMC_PMEM3_MEMSET3_4 (0x10U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000010 */
7708#define FSMC_PMEM3_MEMSET3_5 (0x20U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000020 */
7709#define FSMC_PMEM3_MEMSET3_6 (0x40U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000040 */
7710#define FSMC_PMEM3_MEMSET3_7 (0x80U << FSMC_PMEM3_MEMSET3_Pos) /*!< 0x00000080 */
7711
7712#define FSMC_PMEM3_MEMWAIT3_Pos (8U)
7713#define FSMC_PMEM3_MEMWAIT3_Msk (0xFFU << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x0000FF00 */
7714#define FSMC_PMEM3_MEMWAIT3 FSMC_PMEM3_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
7715#define FSMC_PMEM3_MEMWAIT3_0 (0x01U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000100 */
7716#define FSMC_PMEM3_MEMWAIT3_1 (0x02U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000200 */
7717#define FSMC_PMEM3_MEMWAIT3_2 (0x04U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000400 */
7718#define FSMC_PMEM3_MEMWAIT3_3 (0x08U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000800 */
7719#define FSMC_PMEM3_MEMWAIT3_4 (0x10U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00001000 */
7720#define FSMC_PMEM3_MEMWAIT3_5 (0x20U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00002000 */
7721#define FSMC_PMEM3_MEMWAIT3_6 (0x40U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00004000 */
7722#define FSMC_PMEM3_MEMWAIT3_7 (0x80U << FSMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00008000 */
7723
7724#define FSMC_PMEM3_MEMHOLD3_Pos (16U)
7725#define FSMC_PMEM3_MEMHOLD3_Msk (0xFFU << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00FF0000 */
7726#define FSMC_PMEM3_MEMHOLD3 FSMC_PMEM3_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
7727#define FSMC_PMEM3_MEMHOLD3_0 (0x01U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00010000 */
7728#define FSMC_PMEM3_MEMHOLD3_1 (0x02U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00020000 */
7729#define FSMC_PMEM3_MEMHOLD3_2 (0x04U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00040000 */
7730#define FSMC_PMEM3_MEMHOLD3_3 (0x08U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00080000 */
7731#define FSMC_PMEM3_MEMHOLD3_4 (0x10U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00100000 */
7732#define FSMC_PMEM3_MEMHOLD3_5 (0x20U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00200000 */
7733#define FSMC_PMEM3_MEMHOLD3_6 (0x40U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00400000 */
7734#define FSMC_PMEM3_MEMHOLD3_7 (0x80U << FSMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00800000 */
7735
7736#define FSMC_PMEM3_MEMHIZ3_Pos (24U)
7737#define FSMC_PMEM3_MEMHIZ3_Msk (0xFFU << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0xFF000000 */
7738#define FSMC_PMEM3_MEMHIZ3 FSMC_PMEM3_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
7739#define FSMC_PMEM3_MEMHIZ3_0 (0x01U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x01000000 */
7740#define FSMC_PMEM3_MEMHIZ3_1 (0x02U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x02000000 */
7741#define FSMC_PMEM3_MEMHIZ3_2 (0x04U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x04000000 */
7742#define FSMC_PMEM3_MEMHIZ3_3 (0x08U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x08000000 */
7743#define FSMC_PMEM3_MEMHIZ3_4 (0x10U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x10000000 */
7744#define FSMC_PMEM3_MEMHIZ3_5 (0x20U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x20000000 */
7745#define FSMC_PMEM3_MEMHIZ3_6 (0x40U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x40000000 */
7746#define FSMC_PMEM3_MEMHIZ3_7 (0x80U << FSMC_PMEM3_MEMHIZ3_Pos) /*!< 0x80000000 */
7747
7748/****************** Bit definition for FSMC_PMEM4 register ******************/
7749#define FSMC_PMEM4_MEMSET4_Pos (0U)
7750#define FSMC_PMEM4_MEMSET4_Msk (0xFFU << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x000000FF */
7751#define FSMC_PMEM4_MEMSET4 FSMC_PMEM4_MEMSET4_Msk /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
7752#define FSMC_PMEM4_MEMSET4_0 (0x01U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000001 */
7753#define FSMC_PMEM4_MEMSET4_1 (0x02U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000002 */
7754#define FSMC_PMEM4_MEMSET4_2 (0x04U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000004 */
7755#define FSMC_PMEM4_MEMSET4_3 (0x08U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000008 */
7756#define FSMC_PMEM4_MEMSET4_4 (0x10U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000010 */
7757#define FSMC_PMEM4_MEMSET4_5 (0x20U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000020 */
7758#define FSMC_PMEM4_MEMSET4_6 (0x40U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000040 */
7759#define FSMC_PMEM4_MEMSET4_7 (0x80U << FSMC_PMEM4_MEMSET4_Pos) /*!< 0x00000080 */
7760
7761#define FSMC_PMEM4_MEMWAIT4_Pos (8U)
7762#define FSMC_PMEM4_MEMWAIT4_Msk (0xFFU << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x0000FF00 */
7763#define FSMC_PMEM4_MEMWAIT4 FSMC_PMEM4_MEMWAIT4_Msk /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
7764#define FSMC_PMEM4_MEMWAIT4_0 (0x01U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000100 */
7765#define FSMC_PMEM4_MEMWAIT4_1 (0x02U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000200 */
7766#define FSMC_PMEM4_MEMWAIT4_2 (0x04U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000400 */
7767#define FSMC_PMEM4_MEMWAIT4_3 (0x08U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000800 */
7768#define FSMC_PMEM4_MEMWAIT4_4 (0x10U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00001000 */
7769#define FSMC_PMEM4_MEMWAIT4_5 (0x20U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00002000 */
7770#define FSMC_PMEM4_MEMWAIT4_6 (0x40U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00004000 */
7771#define FSMC_PMEM4_MEMWAIT4_7 (0x80U << FSMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00008000 */
7772
7773#define FSMC_PMEM4_MEMHOLD4_Pos (16U)
7774#define FSMC_PMEM4_MEMHOLD4_Msk (0xFFU << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00FF0000 */
7775#define FSMC_PMEM4_MEMHOLD4 FSMC_PMEM4_MEMHOLD4_Msk /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
7776#define FSMC_PMEM4_MEMHOLD4_0 (0x01U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00010000 */
7777#define FSMC_PMEM4_MEMHOLD4_1 (0x02U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00020000 */
7778#define FSMC_PMEM4_MEMHOLD4_2 (0x04U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00040000 */
7779#define FSMC_PMEM4_MEMHOLD4_3 (0x08U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00080000 */
7780#define FSMC_PMEM4_MEMHOLD4_4 (0x10U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00100000 */
7781#define FSMC_PMEM4_MEMHOLD4_5 (0x20U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00200000 */
7782#define FSMC_PMEM4_MEMHOLD4_6 (0x40U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00400000 */
7783#define FSMC_PMEM4_MEMHOLD4_7 (0x80U << FSMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00800000 */
7784
7785#define FSMC_PMEM4_MEMHIZ4_Pos (24U)
7786#define FSMC_PMEM4_MEMHIZ4_Msk (0xFFU << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0xFF000000 */
7787#define FSMC_PMEM4_MEMHIZ4 FSMC_PMEM4_MEMHIZ4_Msk /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
7788#define FSMC_PMEM4_MEMHIZ4_0 (0x01U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x01000000 */
7789#define FSMC_PMEM4_MEMHIZ4_1 (0x02U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x02000000 */
7790#define FSMC_PMEM4_MEMHIZ4_2 (0x04U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x04000000 */
7791#define FSMC_PMEM4_MEMHIZ4_3 (0x08U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x08000000 */
7792#define FSMC_PMEM4_MEMHIZ4_4 (0x10U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x10000000 */
7793#define FSMC_PMEM4_MEMHIZ4_5 (0x20U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x20000000 */
7794#define FSMC_PMEM4_MEMHIZ4_6 (0x40U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x40000000 */
7795#define FSMC_PMEM4_MEMHIZ4_7 (0x80U << FSMC_PMEM4_MEMHIZ4_Pos) /*!< 0x80000000 */
7796
7797/****************** Bit definition for FSMC_PATT2 register ******************/
7798#define FSMC_PATT2_ATTSET2_Pos (0U)
7799#define FSMC_PATT2_ATTSET2_Msk (0xFFU << FSMC_PATT2_ATTSET2_Pos) /*!< 0x000000FF */
7800#define FSMC_PATT2_ATTSET2 FSMC_PATT2_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
7801#define FSMC_PATT2_ATTSET2_0 (0x01U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000001 */
7802#define FSMC_PATT2_ATTSET2_1 (0x02U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000002 */
7803#define FSMC_PATT2_ATTSET2_2 (0x04U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000004 */
7804#define FSMC_PATT2_ATTSET2_3 (0x08U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000008 */
7805#define FSMC_PATT2_ATTSET2_4 (0x10U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000010 */
7806#define FSMC_PATT2_ATTSET2_5 (0x20U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000020 */
7807#define FSMC_PATT2_ATTSET2_6 (0x40U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000040 */
7808#define FSMC_PATT2_ATTSET2_7 (0x80U << FSMC_PATT2_ATTSET2_Pos) /*!< 0x00000080 */
7809
7810#define FSMC_PATT2_ATTWAIT2_Pos (8U)
7811#define FSMC_PATT2_ATTWAIT2_Msk (0xFFU << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x0000FF00 */
7812#define FSMC_PATT2_ATTWAIT2 FSMC_PATT2_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
7813#define FSMC_PATT2_ATTWAIT2_0 (0x01U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000100 */
7814#define FSMC_PATT2_ATTWAIT2_1 (0x02U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000200 */
7815#define FSMC_PATT2_ATTWAIT2_2 (0x04U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000400 */
7816#define FSMC_PATT2_ATTWAIT2_3 (0x08U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000800 */
7817#define FSMC_PATT2_ATTWAIT2_4 (0x10U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00001000 */
7818#define FSMC_PATT2_ATTWAIT2_5 (0x20U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00002000 */
7819#define FSMC_PATT2_ATTWAIT2_6 (0x40U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00004000 */
7820#define FSMC_PATT2_ATTWAIT2_7 (0x80U << FSMC_PATT2_ATTWAIT2_Pos) /*!< 0x00008000 */
7821
7822#define FSMC_PATT2_ATTHOLD2_Pos (16U)
7823#define FSMC_PATT2_ATTHOLD2_Msk (0xFFU << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00FF0000 */
7824#define FSMC_PATT2_ATTHOLD2 FSMC_PATT2_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
7825#define FSMC_PATT2_ATTHOLD2_0 (0x01U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00010000 */
7826#define FSMC_PATT2_ATTHOLD2_1 (0x02U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00020000 */
7827#define FSMC_PATT2_ATTHOLD2_2 (0x04U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00040000 */
7828#define FSMC_PATT2_ATTHOLD2_3 (0x08U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00080000 */
7829#define FSMC_PATT2_ATTHOLD2_4 (0x10U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00100000 */
7830#define FSMC_PATT2_ATTHOLD2_5 (0x20U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00200000 */
7831#define FSMC_PATT2_ATTHOLD2_6 (0x40U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00400000 */
7832#define FSMC_PATT2_ATTHOLD2_7 (0x80U << FSMC_PATT2_ATTHOLD2_Pos) /*!< 0x00800000 */
7833
7834#define FSMC_PATT2_ATTHIZ2_Pos (24U)
7835#define FSMC_PATT2_ATTHIZ2_Msk (0xFFU << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0xFF000000 */
7836#define FSMC_PATT2_ATTHIZ2 FSMC_PATT2_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
7837#define FSMC_PATT2_ATTHIZ2_0 (0x01U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x01000000 */
7838#define FSMC_PATT2_ATTHIZ2_1 (0x02U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x02000000 */
7839#define FSMC_PATT2_ATTHIZ2_2 (0x04U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x04000000 */
7840#define FSMC_PATT2_ATTHIZ2_3 (0x08U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x08000000 */
7841#define FSMC_PATT2_ATTHIZ2_4 (0x10U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x10000000 */
7842#define FSMC_PATT2_ATTHIZ2_5 (0x20U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x20000000 */
7843#define FSMC_PATT2_ATTHIZ2_6 (0x40U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x40000000 */
7844#define FSMC_PATT2_ATTHIZ2_7 (0x80U << FSMC_PATT2_ATTHIZ2_Pos) /*!< 0x80000000 */
7845
7846/****************** Bit definition for FSMC_PATT3 register ******************/
7847#define FSMC_PATT3_ATTSET3_Pos (0U)
7848#define FSMC_PATT3_ATTSET3_Msk (0xFFU << FSMC_PATT3_ATTSET3_Pos) /*!< 0x000000FF */
7849#define FSMC_PATT3_ATTSET3 FSMC_PATT3_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
7850#define FSMC_PATT3_ATTSET3_0 (0x01U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000001 */
7851#define FSMC_PATT3_ATTSET3_1 (0x02U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000002 */
7852#define FSMC_PATT3_ATTSET3_2 (0x04U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000004 */
7853#define FSMC_PATT3_ATTSET3_3 (0x08U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000008 */
7854#define FSMC_PATT3_ATTSET3_4 (0x10U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000010 */
7855#define FSMC_PATT3_ATTSET3_5 (0x20U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000020 */
7856#define FSMC_PATT3_ATTSET3_6 (0x40U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000040 */
7857#define FSMC_PATT3_ATTSET3_7 (0x80U << FSMC_PATT3_ATTSET3_Pos) /*!< 0x00000080 */
7858
7859#define FSMC_PATT3_ATTWAIT3_Pos (8U)
7860#define FSMC_PATT3_ATTWAIT3_Msk (0xFFU << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x0000FF00 */
7861#define FSMC_PATT3_ATTWAIT3 FSMC_PATT3_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
7862#define FSMC_PATT3_ATTWAIT3_0 (0x01U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000100 */
7863#define FSMC_PATT3_ATTWAIT3_1 (0x02U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000200 */
7864#define FSMC_PATT3_ATTWAIT3_2 (0x04U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000400 */
7865#define FSMC_PATT3_ATTWAIT3_3 (0x08U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000800 */
7866#define FSMC_PATT3_ATTWAIT3_4 (0x10U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00001000 */
7867#define FSMC_PATT3_ATTWAIT3_5 (0x20U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00002000 */
7868#define FSMC_PATT3_ATTWAIT3_6 (0x40U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00004000 */
7869#define FSMC_PATT3_ATTWAIT3_7 (0x80U << FSMC_PATT3_ATTWAIT3_Pos) /*!< 0x00008000 */
7870
7871#define FSMC_PATT3_ATTHOLD3_Pos (16U)
7872#define FSMC_PATT3_ATTHOLD3_Msk (0xFFU << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00FF0000 */
7873#define FSMC_PATT3_ATTHOLD3 FSMC_PATT3_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
7874#define FSMC_PATT3_ATTHOLD3_0 (0x01U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00010000 */
7875#define FSMC_PATT3_ATTHOLD3_1 (0x02U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00020000 */
7876#define FSMC_PATT3_ATTHOLD3_2 (0x04U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00040000 */
7877#define FSMC_PATT3_ATTHOLD3_3 (0x08U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00080000 */
7878#define FSMC_PATT3_ATTHOLD3_4 (0x10U << FSMC_PATT3_ATTHOLD3_Pos) /*!< 0x00