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1/**
2 ******************************************************************************
3 * @file stm32f446xx.h
4 * @author MCD Application Team
5 * @version V2.6.1
6 * @date 14-February-2017
7 * @brief CMSIS STM32F446xx Device Peripheral Access Layer Header File.
8 *
9 * This file contains:
10 * - Data structures and the address mapping for all peripherals
11 * - peripherals registers declarations and bits definition
12 * - Macros to access peripheral’s registers hardware
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
18 *
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ******************************************************************************
42 */
43
44/** @addtogroup CMSIS_Device
45 * @{
46 */
47
48/** @addtogroup stm32f446xx
49 * @{
50 */
51
52#ifndef __STM32F446xx_H
53#define __STM32F446xx_H
54
55#ifdef __cplusplus
56 extern "C" {
57#endif /* __cplusplus */
58
59/** @addtogroup Configuration_section_for_CMSIS
60 * @{
61 */
62
63/**
64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
65 */
66#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
67#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
68#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
69#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
70#define __FPU_PRESENT 1U /*!< FPU present */
71
72/**
73 * @}
74 */
75
76/** @addtogroup Peripheral_interrupt_number_definition
77 * @{
78 */
79
80/**
81 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
82 * in @ref Library_configuration_section
83 */
84typedef enum
85{
86/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
87 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
88 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
89 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
90 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
91 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
92 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
93 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
94 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
95/****** STM32 specific Interrupt Numbers **********************************************************************/
96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
97 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
98 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
99 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
100 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
101 RCC_IRQn = 5, /*!< RCC global Interrupt */
102 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
103 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
104 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
105 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
106 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
107 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
108 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
109 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
110 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
111 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
112 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
113 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
114 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
115 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
116 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
117 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
118 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
119 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
120 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
121 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
122 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
123 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
124 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
125 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
126 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
127 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
128 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
129 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
130 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
131 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
132 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
133 USART1_IRQn = 37, /*!< USART1 global Interrupt */
134 USART2_IRQn = 38, /*!< USART2 global Interrupt */
135 USART3_IRQn = 39, /*!< USART3 global Interrupt */
136 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
137 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
138 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
139 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
140 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
141 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
142 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
143 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
144 FMC_IRQn = 48, /*!< FMC global Interrupt */
145 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
146 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
147 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
148 UART4_IRQn = 52, /*!< UART4 global Interrupt */
149 UART5_IRQn = 53, /*!< UART5 global Interrupt */
150 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
151 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
152 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
153 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
154 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
155 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
156 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
157 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
158 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
159 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
160 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
161 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
162 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
163 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
164 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
165 USART6_IRQn = 71, /*!< USART6 global interrupt */
166 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
167 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
168 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
169 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
170 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
171 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
172 DCMI_IRQn = 78, /*!< DCMI global interrupt */
173 FPU_IRQn = 81, /*!< FPU global interrupt */
174 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
175 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
176 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
177 QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
178 CEC_IRQn = 93, /*!< CEC global Interrupt */
179 SPDIF_RX_IRQn = 94, /*!< SPDIF-RX global Interrupt */
180 FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
181 FMPI2C1_ER_IRQn = 96 /*!< FMPI2C1 Error Interrupt */
182} IRQn_Type;
183
184/**
185 * @}
186 */
187
188#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
189#include "system_stm32f4xx.h"
190#include <stdint.h>
191
192/** @addtogroup Peripheral_registers_structures
193 * @{
194 */
195
196/**
197 * @brief Analog to Digital Converter
198 */
199
200typedef struct
201{
202 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
203 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
204 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
205 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
206 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
207 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
208 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
209 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
210 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
211 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
212 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
213 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
214 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
215 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
216 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
217 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
218 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
219 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
220 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
221 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
222} ADC_TypeDef;
223
224typedef struct
225{
226 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
227 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
228 __IO uint32_t CDR; /*!< ADC common regular data register for dual
229 AND triple modes, Address offset: ADC1 base address + 0x308 */
230} ADC_Common_TypeDef;
231
232
233/**
234 * @brief Controller Area Network TxMailBox
235 */
236
237typedef struct
238{
239 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
240 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
241 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
242 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
243} CAN_TxMailBox_TypeDef;
244
245/**
246 * @brief Controller Area Network FIFOMailBox
247 */
248
249typedef struct
250{
251 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
252 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
253 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
254 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
255} CAN_FIFOMailBox_TypeDef;
256
257/**
258 * @brief Controller Area Network FilterRegister
259 */
260
261typedef struct
262{
263 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
264 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
265} CAN_FilterRegister_TypeDef;
266
267/**
268 * @brief Controller Area Network
269 */
270
271typedef struct
272{
273 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
274 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
275 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
276 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
277 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
278 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
279 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
280 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
281 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
282 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
283 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
284 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
285 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
286 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
287 uint32_t RESERVED2; /*!< Reserved, 0x208 */
288 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
289 uint32_t RESERVED3; /*!< Reserved, 0x210 */
290 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
291 uint32_t RESERVED4; /*!< Reserved, 0x218 */
292 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
293 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
294 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
295} CAN_TypeDef;
296
297
298/**
299 * @brief Consumer Electronics Control
300 */
301
302typedef struct
303{
304 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
305 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
306 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
307 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
308 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
309 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
310}CEC_TypeDef;
311/**
312 * @brief CRC calculation unit
313 */
314
315typedef struct
316{
317 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
318 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
319 uint8_t RESERVED0; /*!< Reserved, 0x05 */
320 uint16_t RESERVED1; /*!< Reserved, 0x06 */
321 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
322} CRC_TypeDef;
323
324/**
325 * @brief Digital to Analog Converter
326 */
327
328typedef struct
329{
330 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
331 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
332 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
333 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
334 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
335 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
336 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
337 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
338 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
339 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
340 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
341 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
342 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
343 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
344} DAC_TypeDef;
345
346/**
347 * @brief Debug MCU
348 */
349
350typedef struct
351{
352 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
353 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
354 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
355 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
356}DBGMCU_TypeDef;
357
358/**
359 * @brief DCMI
360 */
361
362typedef struct
363{
364 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
365 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
366 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
367 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
368 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
369 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
370 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
371 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
372 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
373 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
374 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
375} DCMI_TypeDef;
376
377/**
378 * @brief DMA Controller
379 */
380
381typedef struct
382{
383 __IO uint32_t CR; /*!< DMA stream x configuration register */
384 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
385 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
386 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
387 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
388 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
389} DMA_Stream_TypeDef;
390
391typedef struct
392{
393 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
394 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
395 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
396 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
397} DMA_TypeDef;
398
399/**
400 * @brief External Interrupt/Event Controller
401 */
402
403typedef struct
404{
405 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
406 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
407 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
408 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
409 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
410 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
411} EXTI_TypeDef;
412
413/**
414 * @brief FLASH Registers
415 */
416
417typedef struct
418{
419 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
420 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
421 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
422 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
423 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
424 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
425 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
426} FLASH_TypeDef;
427
428/**
429 * @brief Flexible Memory Controller
430 */
431
432typedef struct
433{
434 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
435} FMC_Bank1_TypeDef;
436
437/**
438 * @brief Flexible Memory Controller Bank1E
439 */
440
441typedef struct
442{
443 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
444} FMC_Bank1E_TypeDef;
445
446/**
447 * @brief Flexible Memory Controller Bank3
448 */
449
450typedef struct
451{
452 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
453 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
454 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
455 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
456 uint32_t RESERVED; /*!< Reserved, 0x90 */
457 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
458} FMC_Bank3_TypeDef;
459
460/**
461 * @brief Flexible Memory Controller Bank5_6
462 */
463
464typedef struct
465{
466 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
467 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
468 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
469 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
470 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
471} FMC_Bank5_6_TypeDef;
472
473/**
474 * @brief General Purpose I/O
475 */
476
477typedef struct
478{
479 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
480 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
481 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
482 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
483 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
484 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
485 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
486 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
487 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
488} GPIO_TypeDef;
489
490/**
491 * @brief System configuration controller
492 */
493
494typedef struct
495{
496 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
497 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
498 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
499 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
500 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
501 uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
502 __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
503} SYSCFG_TypeDef;
504
505/**
506 * @brief Inter-integrated Circuit Interface
507 */
508
509typedef struct
510{
511 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
512 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
513 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
514 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
515 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
516 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
517 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
518 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
519 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
520 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
521} I2C_TypeDef;
522
523/**
524 * @brief Inter-integrated Circuit Interface
525 */
526
527typedef struct
528{
529 __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
530 __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
531 __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
532 __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
533 __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
534 __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
535 __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
536 __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
537 __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
538 __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
539 __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
540} FMPI2C_TypeDef;
541
542/**
543 * @brief Independent WATCHDOG
544 */
545
546typedef struct
547{
548 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
549 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
550 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
551 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
552} IWDG_TypeDef;
553
554
555/**
556 * @brief Power Control
557 */
558
559typedef struct
560{
561 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
562 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
563} PWR_TypeDef;
564
565/**
566 * @brief Reset and Clock Control
567 */
568
569typedef struct
570{
571 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
572 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
573 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
574 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
575 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
576 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
577 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
578 uint32_t RESERVED0; /*!< Reserved, 0x1C */
579 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
580 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
581 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
582 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
583 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
584 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
585 uint32_t RESERVED2; /*!< Reserved, 0x3C */
586 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
587 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
588 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
589 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
590 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
591 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
592 uint32_t RESERVED4; /*!< Reserved, 0x5C */
593 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
594 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
595 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
596 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
597 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
598 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
599 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
600 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
601 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
602 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
603 __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
604 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
605} RCC_TypeDef;
606
607/**
608 * @brief Real-Time Clock
609 */
610
611typedef struct
612{
613 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
614 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
615 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
616 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
617 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
618 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
619 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
620 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
621 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
622 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
623 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
624 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
625 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
626 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
627 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
628 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
629 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
630 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
631 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
632 uint32_t RESERVED7; /*!< Reserved, 0x4C */
633 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
634 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
635 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
636 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
637 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
638 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
639 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
640 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
641 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
642 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
643 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
644 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
645 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
646 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
647 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
648 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
649 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
650 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
651 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
652 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
653} RTC_TypeDef;
654
655/**
656 * @brief Serial Audio Interface
657 */
658
659typedef struct
660{
661 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
662} SAI_TypeDef;
663
664typedef struct
665{
666 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
667 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
668 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
669 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
670 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
671 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
672 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
673 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
674} SAI_Block_TypeDef;
675
676/**
677 * @brief SD host Interface
678 */
679
680typedef struct
681{
682 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
683 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
684 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
685 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
686 __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
687 __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
688 __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
689 __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
690 __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
691 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
692 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
693 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
694 __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
695 __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
696 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
697 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
698 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
699 __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
700 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
701 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
702} SDIO_TypeDef;
703
704/**
705 * @brief Serial Peripheral Interface
706 */
707
708typedef struct
709{
710 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
711 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
712 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
713 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
714 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
715 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
716 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
717 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
718 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
719} SPI_TypeDef;
720
721/**
722 * @brief QUAD Serial Peripheral Interface
723 */
724
725typedef struct
726{
727 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
728 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
729 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
730 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
731 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
732 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
733 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
734 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
735 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
736 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
737 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
738 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
739 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
740} QUADSPI_TypeDef;
741
742/**
743 * @brief SPDIFRX Interface
744 */
745
746typedef struct
747{
748 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
749 __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
750 uint16_t RESERVED0; /*!< Reserved, 0x06 */
751 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
752 __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
753 uint16_t RESERVED1; /*!< Reserved, 0x0E */
754 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
755 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
756 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
757 uint16_t RESERVED2; /*!< Reserved, 0x1A */
758} SPDIFRX_TypeDef;
759
760/**
761 * @brief TIM
762 */
763
764typedef struct
765{
766 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
767 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
768 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
769 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
770 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
771 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
772 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
773 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
774 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
775 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
776 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
777 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
778 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
779 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
780 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
781 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
782 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
783 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
784 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
785 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
786 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
787} TIM_TypeDef;
788
789/**
790 * @brief Universal Synchronous Asynchronous Receiver Transmitter
791 */
792
793typedef struct
794{
795 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
796 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
797 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
798 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
799 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
800 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
801 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
802} USART_TypeDef;
803
804/**
805 * @brief Window WATCHDOG
806 */
807
808typedef struct
809{
810 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
811 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
812 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
813} WWDG_TypeDef;
814/**
815 * @brief USB_OTG_Core_Registers
816 */
817typedef struct
818{
819 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
820 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
821 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
822 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
823 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
824 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
825 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
826 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
827 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
828 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
829 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
830 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
831 uint32_t Reserved30[2]; /*!< Reserved 030h */
832 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
833 __IO uint32_t CID; /*!< User ID Register 03Ch */
834 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
835 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
836 uint32_t Reserved6; /*!< Reserved 050h */
837 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
838 uint32_t Reserved; /*!< Reserved 058h */
839 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
840 uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh */
841 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
842 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
843} USB_OTG_GlobalTypeDef;
844
845/**
846 * @brief USB_OTG_device_Registers
847 */
848typedef struct
849{
850 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
851 __IO uint32_t DCTL; /*!< dev Control Register 804h */
852 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
853 uint32_t Reserved0C; /*!< Reserved 80Ch */
854 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
855 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
856 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
857 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
858 uint32_t Reserved20; /*!< Reserved 820h */
859 uint32_t Reserved9; /*!< Reserved 824h */
860 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
861 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
862 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
863 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
864 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
865 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
866 uint32_t Reserved40; /*!< dedicated EP mask 840h */
867 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
868 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
869 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
870} USB_OTG_DeviceTypeDef;
871
872/**
873 * @brief USB_OTG_IN_Endpoint-Specific_Register
874 */
875typedef struct
876{
877 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
878 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
879 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
880 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
881 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
882 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
883 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
884 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
885} USB_OTG_INEndpointTypeDef;
886
887/**
888 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
889 */
890typedef struct
891{
892 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
893 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
894 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
895 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
896 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
897 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
898 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
899} USB_OTG_OUTEndpointTypeDef;
900
901/**
902 * @brief USB_OTG_Host_Mode_Register_Structures
903 */
904typedef struct
905{
906 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
907 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
908 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
909 uint32_t Reserved40C; /*!< Reserved 40Ch */
910 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
911 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
912 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
913} USB_OTG_HostTypeDef;
914
915/**
916 * @brief USB_OTG_Host_Channel_Specific_Registers
917 */
918typedef struct
919{
920 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
921 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
922 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
923 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
924 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
925 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
926 uint32_t Reserved[2]; /*!< Reserved */
927} USB_OTG_HostChannelTypeDef;
928
929/**
930 * @}
931 */
932
933/** @addtogroup Peripheral_memory_map
934 * @{
935 */
936#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
937#define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
938#define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
939#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
940#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
941#define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */
942#define QSPI_R_BASE 0xA0001000U /*!< QuadSPI registers base address */
943#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
944#define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
945#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
946#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
947#define FLASH_END 0x0807FFFFU /*!< FLASH end address */
948#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
949#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
950
951/* Legacy defines */
952#define SRAM_BASE SRAM1_BASE
953#define SRAM_BB_BASE SRAM1_BB_BASE
954
955/*!< Peripheral memory map */
956#define APB1PERIPH_BASE PERIPH_BASE
957#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
958#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
959#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
960
961/*!< APB1 peripherals */
962#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
963#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
964#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
965#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
966#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
967#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
968#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
969#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
970#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
971#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
972#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
973#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
974#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
975#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
976#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)
977#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
978#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
979#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
980#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
981#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
982#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
983#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
984#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000U)
985#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
986#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
987#define CEC_BASE (APB1PERIPH_BASE + 0x6C00U)
988#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
989#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
990
991/*!< APB2 peripherals */
992#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
993#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
994#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
995#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
996#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
997#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
998#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
999#define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
1000/* Legacy define */
1001#define ADC_BASE ADC123_COMMON_BASE
1002#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
1003#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1004#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
1005#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
1006#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
1007#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
1008#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
1009#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
1010#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
1011#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
1012#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
1013#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
1014#define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
1015#define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
1016
1017/*!< AHB1 peripherals */
1018#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
1019#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1020#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1021#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1022#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1023#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1024#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1025#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1026#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1027#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1028#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1029#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1030#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1031#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1032#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1033#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1034#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1035#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1036#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1037#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1038#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1039#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1040#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1041#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1042#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1043#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1044#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1045#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1046#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1047
1048/*!< AHB2 peripherals */
1049#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
1050
1051/*!< FMC Bankx registers base address */
1052#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1053#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1054#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
1055#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
1056
1057
1058/*!< Debug MCU registers base address */
1059#define DBGMCU_BASE 0xE0042000U
1060/*!< USB registers base address */
1061#define USB_OTG_HS_PERIPH_BASE 0x40040000U
1062#define USB_OTG_FS_PERIPH_BASE 0x50000000U
1063
1064#define USB_OTG_GLOBAL_BASE 0x000U
1065#define USB_OTG_DEVICE_BASE 0x800U
1066#define USB_OTG_IN_ENDPOINT_BASE 0x900U
1067#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1068#define USB_OTG_EP_REG_SIZE 0x20U
1069#define USB_OTG_HOST_BASE 0x400U
1070#define USB_OTG_HOST_PORT_BASE 0x440U
1071#define USB_OTG_HOST_CHANNEL_BASE 0x500U
1072#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1073#define USB_OTG_PCGCCTL_BASE 0xE00U
1074#define USB_OTG_FIFO_BASE 0x1000U
1075#define USB_OTG_FIFO_SIZE 0x1000U
1076
1077#define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
1078#define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
1079#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
1080/**
1081 * @}
1082 */
1083
1084/** @addtogroup Peripheral_declaration
1085 * @{
1086 */
1087#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1088#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1089#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1090#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1091#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1092#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1093#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1094#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1095#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1096#define RTC ((RTC_TypeDef *) RTC_BASE)
1097#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1098#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1099#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1100#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1101#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
1102#define USART2 ((USART_TypeDef *) USART2_BASE)
1103#define USART3 ((USART_TypeDef *) USART3_BASE)
1104#define UART4 ((USART_TypeDef *) UART4_BASE)
1105#define UART5 ((USART_TypeDef *) UART5_BASE)
1106#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1107#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1108#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1109#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
1110#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1111#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1112#define CEC ((CEC_TypeDef *) CEC_BASE)
1113#define PWR ((PWR_TypeDef *) PWR_BASE)
1114#define DAC1 ((DAC_TypeDef *) DAC_BASE)
1115#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1116#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1117#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1118#define USART1 ((USART_TypeDef *) USART1_BASE)
1119#define USART6 ((USART_TypeDef *) USART6_BASE)
1120#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1121#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1122#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1123#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1124/* Legacy define */
1125#define ADC ADC123_COMMON
1126#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1127#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1128#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1129#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1130#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1131#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1132#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1133#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1134#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1135#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1136#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1137#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1138#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1139#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1140#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1141#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1142#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1143#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1144#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1145#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1146#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1147#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1148#define CRC ((CRC_TypeDef *) CRC_BASE)
1149#define RCC ((RCC_TypeDef *) RCC_BASE)
1150#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1151#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1152#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1153#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1154#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1155#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1156#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1157#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1158#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1159#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1160#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1161#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1162#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1163#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1164#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1165#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1166#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1167#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1168#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1169#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1170#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1171#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1172#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1173#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1174#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1175#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1176#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1177#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1178
1179/**
1180 * @}
1181 */
1182
1183/** @addtogroup Exported_constants
1184 * @{
1185 */
1186
1187 /** @addtogroup Peripheral_Registers_Bits_Definition
1188 * @{
1189 */
1190
1191/******************************************************************************/
1192/* Peripheral Registers_Bits_Definition */
1193/******************************************************************************/
1194
1195/******************************************************************************/
1196/* */
1197/* Analog to Digital Converter */
1198/* */
1199/******************************************************************************/
1200/*
1201 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
1202 */
1203#define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */
1204
1205/******************** Bit definition for ADC_SR register ********************/
1206#define ADC_SR_AWD_Pos (0U)
1207#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
1208#define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
1209#define ADC_SR_EOC_Pos (1U)
1210#define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
1211#define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
1212#define ADC_SR_JEOC_Pos (2U)
1213#define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
1214#define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
1215#define ADC_SR_JSTRT_Pos (3U)
1216#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
1217#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
1218#define ADC_SR_STRT_Pos (4U)
1219#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
1220#define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
1221#define ADC_SR_OVR_Pos (5U)
1222#define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
1223#define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
1224
1225/******************* Bit definition for ADC_CR1 register ********************/
1226#define ADC_CR1_AWDCH_Pos (0U)
1227#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
1228#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1229#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
1230#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
1231#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
1232#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
1233#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
1234#define ADC_CR1_EOCIE_Pos (5U)
1235#define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
1236#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
1237#define ADC_CR1_AWDIE_Pos (6U)
1238#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
1239#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
1240#define ADC_CR1_JEOCIE_Pos (7U)
1241#define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
1242#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
1243#define ADC_CR1_SCAN_Pos (8U)
1244#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
1245#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
1246#define ADC_CR1_AWDSGL_Pos (9U)
1247#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
1248#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
1249#define ADC_CR1_JAUTO_Pos (10U)
1250#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
1251#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
1252#define ADC_CR1_DISCEN_Pos (11U)
1253#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
1254#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
1255#define ADC_CR1_JDISCEN_Pos (12U)
1256#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
1257#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
1258#define ADC_CR1_DISCNUM_Pos (13U)
1259#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
1260#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1261#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
1262#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
1263#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
1264#define ADC_CR1_JAWDEN_Pos (22U)
1265#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
1266#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
1267#define ADC_CR1_AWDEN_Pos (23U)
1268#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
1269#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
1270#define ADC_CR1_RES_Pos (24U)
1271#define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
1272#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
1273#define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
1274#define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
1275#define ADC_CR1_OVRIE_Pos (26U)
1276#define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
1277#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
1278
1279/******************* Bit definition for ADC_CR2 register ********************/
1280#define ADC_CR2_ADON_Pos (0U)
1281#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
1282#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
1283#define ADC_CR2_CONT_Pos (1U)
1284#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
1285#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
1286#define ADC_CR2_DMA_Pos (8U)
1287#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
1288#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
1289#define ADC_CR2_DDS_Pos (9U)
1290#define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
1291#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
1292#define ADC_CR2_EOCS_Pos (10U)
1293#define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
1294#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
1295#define ADC_CR2_ALIGN_Pos (11U)
1296#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
1297#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
1298#define ADC_CR2_JEXTSEL_Pos (16U)
1299#define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
1300#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1301#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
1302#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
1303#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
1304#define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
1305#define ADC_CR2_JEXTEN_Pos (20U)
1306#define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
1307#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1308#define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
1309#define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
1310#define ADC_CR2_JSWSTART_Pos (22U)
1311#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
1312#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
1313#define ADC_CR2_EXTSEL_Pos (24U)
1314#define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
1315#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1316#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
1317#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
1318#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
1319#define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
1320#define ADC_CR2_EXTEN_Pos (28U)
1321#define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
1322#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1323#define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
1324#define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
1325#define ADC_CR2_SWSTART_Pos (30U)
1326#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
1327#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
1328
1329/****************** Bit definition for ADC_SMPR1 register *******************/
1330#define ADC_SMPR1_SMP10_Pos (0U)
1331#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
1332#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1333#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
1334#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
1335#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
1336#define ADC_SMPR1_SMP11_Pos (3U)
1337#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
1338#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1339#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
1340#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
1341#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
1342#define ADC_SMPR1_SMP12_Pos (6U)
1343#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
1344#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1345#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
1346#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
1347#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
1348#define ADC_SMPR1_SMP13_Pos (9U)
1349#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
1350#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1351#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
1352#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
1353#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
1354#define ADC_SMPR1_SMP14_Pos (12U)
1355#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
1356#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1357#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
1358#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
1359#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
1360#define ADC_SMPR1_SMP15_Pos (15U)
1361#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
1362#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1363#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
1364#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
1365#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
1366#define ADC_SMPR1_SMP16_Pos (18U)
1367#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
1368#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1369#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
1370#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
1371#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
1372#define ADC_SMPR1_SMP17_Pos (21U)
1373#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
1374#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1375#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
1376#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
1377#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
1378#define ADC_SMPR1_SMP18_Pos (24U)
1379#define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
1380#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1381#define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
1382#define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
1383#define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
1384
1385/****************** Bit definition for ADC_SMPR2 register *******************/
1386#define ADC_SMPR2_SMP0_Pos (0U)
1387#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
1388#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1389#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
1390#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
1391#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
1392#define ADC_SMPR2_SMP1_Pos (3U)
1393#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
1394#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1395#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
1396#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
1397#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
1398#define ADC_SMPR2_SMP2_Pos (6U)
1399#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
1400#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1401#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
1402#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
1403#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
1404#define ADC_SMPR2_SMP3_Pos (9U)
1405#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
1406#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1407#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
1408#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
1409#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
1410#define ADC_SMPR2_SMP4_Pos (12U)
1411#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
1412#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1413#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
1414#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
1415#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
1416#define ADC_SMPR2_SMP5_Pos (15U)
1417#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
1418#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1419#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
1420#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
1421#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
1422#define ADC_SMPR2_SMP6_Pos (18U)
1423#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
1424#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1425#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
1426#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
1427#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
1428#define ADC_SMPR2_SMP7_Pos (21U)
1429#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
1430#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1431#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
1432#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
1433#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
1434#define ADC_SMPR2_SMP8_Pos (24U)
1435#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
1436#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1437#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
1438#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
1439#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
1440#define ADC_SMPR2_SMP9_Pos (27U)
1441#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
1442#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1443#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
1444#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
1445#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
1446
1447/****************** Bit definition for ADC_JOFR1 register *******************/
1448#define ADC_JOFR1_JOFFSET1_Pos (0U)
1449#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
1450#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
1451
1452/****************** Bit definition for ADC_JOFR2 register *******************/
1453#define ADC_JOFR2_JOFFSET2_Pos (0U)
1454#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
1455#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
1456
1457/****************** Bit definition for ADC_JOFR3 register *******************/
1458#define ADC_JOFR3_JOFFSET3_Pos (0U)
1459#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
1460#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
1461
1462/****************** Bit definition for ADC_JOFR4 register *******************/
1463#define ADC_JOFR4_JOFFSET4_Pos (0U)
1464#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
1465#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
1466
1467/******************* Bit definition for ADC_HTR register ********************/
1468#define ADC_HTR_HT_Pos (0U)
1469#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
1470#define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
1471
1472/******************* Bit definition for ADC_LTR register ********************/
1473#define ADC_LTR_LT_Pos (0U)
1474#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
1475#define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
1476
1477/******************* Bit definition for ADC_SQR1 register *******************/
1478#define ADC_SQR1_SQ13_Pos (0U)
1479#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
1480#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1481#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
1482#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
1483#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
1484#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
1485#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
1486#define ADC_SQR1_SQ14_Pos (5U)
1487#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
1488#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1489#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
1490#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
1491#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
1492#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
1493#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
1494#define ADC_SQR1_SQ15_Pos (10U)
1495#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
1496#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1497#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
1498#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
1499#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
1500#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
1501#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
1502#define ADC_SQR1_SQ16_Pos (15U)
1503#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
1504#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1505#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
1506#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
1507#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
1508#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
1509#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
1510#define ADC_SQR1_L_Pos (20U)
1511#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
1512#define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
1513#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
1514#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
1515#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
1516#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
1517
1518/******************* Bit definition for ADC_SQR2 register *******************/
1519#define ADC_SQR2_SQ7_Pos (0U)
1520#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
1521#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1522#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
1523#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
1524#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
1525#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
1526#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
1527#define ADC_SQR2_SQ8_Pos (5U)
1528#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
1529#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1530#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
1531#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
1532#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
1533#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
1534#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
1535#define ADC_SQR2_SQ9_Pos (10U)
1536#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
1537#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1538#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
1539#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
1540#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
1541#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
1542#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
1543#define ADC_SQR2_SQ10_Pos (15U)
1544#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
1545#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1546#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
1547#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
1548#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
1549#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
1550#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
1551#define ADC_SQR2_SQ11_Pos (20U)
1552#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
1553#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1554#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
1555#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
1556#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
1557#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
1558#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
1559#define ADC_SQR2_SQ12_Pos (25U)
1560#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
1561#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1562#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
1563#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
1564#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
1565#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
1566#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
1567
1568/******************* Bit definition for ADC_SQR3 register *******************/
1569#define ADC_SQR3_SQ1_Pos (0U)
1570#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
1571#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1572#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
1573#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
1574#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
1575#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
1576#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
1577#define ADC_SQR3_SQ2_Pos (5U)
1578#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
1579#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1580#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
1581#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
1582#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
1583#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
1584#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
1585#define ADC_SQR3_SQ3_Pos (10U)
1586#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
1587#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1588#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
1589#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
1590#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
1591#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
1592#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
1593#define ADC_SQR3_SQ4_Pos (15U)
1594#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
1595#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1596#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
1597#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
1598#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
1599#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
1600#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
1601#define ADC_SQR3_SQ5_Pos (20U)
1602#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
1603#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1604#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
1605#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
1606#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
1607#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
1608#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
1609#define ADC_SQR3_SQ6_Pos (25U)
1610#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
1611#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1612#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
1613#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
1614#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
1615#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
1616#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
1617
1618/******************* Bit definition for ADC_JSQR register *******************/
1619#define ADC_JSQR_JSQ1_Pos (0U)
1620#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
1621#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1622#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
1623#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
1624#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
1625#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
1626#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
1627#define ADC_JSQR_JSQ2_Pos (5U)
1628#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
1629#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1630#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
1631#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
1632#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
1633#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
1634#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
1635#define ADC_JSQR_JSQ3_Pos (10U)
1636#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
1637#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1638#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
1639#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
1640#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
1641#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
1642#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
1643#define ADC_JSQR_JSQ4_Pos (15U)
1644#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
1645#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1646#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
1647#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
1648#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
1649#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
1650#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
1651#define ADC_JSQR_JL_Pos (20U)
1652#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
1653#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
1654#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
1655#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
1656
1657/******************* Bit definition for ADC_JDR1 register *******************/
1658#define ADC_JDR1_JDATA_Pos (0U)
1659#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
1660#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
1661
1662/******************* Bit definition for ADC_JDR2 register *******************/
1663#define ADC_JDR2_JDATA_Pos (0U)
1664#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
1665#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
1666
1667/******************* Bit definition for ADC_JDR3 register *******************/
1668#define ADC_JDR3_JDATA_Pos (0U)
1669#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
1670#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
1671
1672/******************* Bit definition for ADC_JDR4 register *******************/
1673#define ADC_JDR4_JDATA_Pos (0U)
1674#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
1675#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
1676
1677/******************** Bit definition for ADC_DR register ********************/
1678#define ADC_DR_DATA_Pos (0U)
1679#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
1680#define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
1681#define ADC_DR_ADC2DATA_Pos (16U)
1682#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
1683#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
1684
1685/******************* Bit definition for ADC_CSR register ********************/
1686#define ADC_CSR_AWD1_Pos (0U)
1687#define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
1688#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
1689#define ADC_CSR_EOC1_Pos (1U)
1690#define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
1691#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
1692#define ADC_CSR_JEOC1_Pos (2U)
1693#define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
1694#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
1695#define ADC_CSR_JSTRT1_Pos (3U)
1696#define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
1697#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
1698#define ADC_CSR_STRT1_Pos (4U)
1699#define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
1700#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
1701#define ADC_CSR_OVR1_Pos (5U)
1702#define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
1703#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
1704#define ADC_CSR_AWD2_Pos (8U)
1705#define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
1706#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
1707#define ADC_CSR_EOC2_Pos (9U)
1708#define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
1709#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
1710#define ADC_CSR_JEOC2_Pos (10U)
1711#define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
1712#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
1713#define ADC_CSR_JSTRT2_Pos (11U)
1714#define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
1715#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
1716#define ADC_CSR_STRT2_Pos (12U)
1717#define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
1718#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
1719#define ADC_CSR_OVR2_Pos (13U)
1720#define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
1721#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */
1722#define ADC_CSR_AWD3_Pos (16U)
1723#define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
1724#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
1725#define ADC_CSR_EOC3_Pos (17U)
1726#define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
1727#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
1728#define ADC_CSR_JEOC3_Pos (18U)
1729#define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
1730#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
1731#define ADC_CSR_JSTRT3_Pos (19U)
1732#define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
1733#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
1734#define ADC_CSR_STRT3_Pos (20U)
1735#define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
1736#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
1737#define ADC_CSR_OVR3_Pos (21U)
1738#define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
1739#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */
1740
1741/* Legacy defines */
1742#define ADC_CSR_DOVR1 ADC_CSR_OVR1
1743#define ADC_CSR_DOVR2 ADC_CSR_OVR2
1744#define ADC_CSR_DOVR3 ADC_CSR_OVR3
1745
1746/******************* Bit definition for ADC_CCR register ********************/
1747#define ADC_CCR_MULTI_Pos (0U)
1748#define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
1749#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1750#define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
1751#define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
1752#define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
1753#define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
1754#define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
1755#define ADC_CCR_DELAY_Pos (8U)
1756#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
1757#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1758#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
1759#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
1760#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
1761#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
1762#define ADC_CCR_DDS_Pos (13U)
1763#define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
1764#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
1765#define ADC_CCR_DMA_Pos (14U)
1766#define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
1767#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1768#define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
1769#define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
1770#define ADC_CCR_ADCPRE_Pos (16U)
1771#define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
1772#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
1773#define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
1774#define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
1775#define ADC_CCR_VBATE_Pos (22U)
1776#define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
1777#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
1778#define ADC_CCR_TSVREFE_Pos (23U)
1779#define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
1780#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
1781
1782/******************* Bit definition for ADC_CDR register ********************/
1783#define ADC_CDR_DATA1_Pos (0U)
1784#define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
1785#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
1786#define ADC_CDR_DATA2_Pos (16U)
1787#define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
1788#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
1789
1790/* Legacy defines */
1791#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
1792#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
1793
1794/******************************************************************************/
1795/* */
1796/* Controller Area Network */
1797/* */
1798/******************************************************************************/
1799/*!<CAN control and status registers */
1800/******************* Bit definition for CAN_MCR register ********************/
1801#define CAN_MCR_INRQ_Pos (0U)
1802#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
1803#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
1804#define CAN_MCR_SLEEP_Pos (1U)
1805#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
1806#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
1807#define CAN_MCR_TXFP_Pos (2U)
1808#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
1809#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
1810#define CAN_MCR_RFLM_Pos (3U)
1811#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
1812#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
1813#define CAN_MCR_NART_Pos (4U)
1814#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
1815#define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
1816#define CAN_MCR_AWUM_Pos (5U)
1817#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
1818#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
1819#define CAN_MCR_ABOM_Pos (6U)
1820#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
1821#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
1822#define CAN_MCR_TTCM_Pos (7U)
1823#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
1824#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
1825#define CAN_MCR_RESET_Pos (15U)
1826#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
1827#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
1828#define CAN_MCR_DBF_Pos (16U)
1829#define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
1830#define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
1831/******************* Bit definition for CAN_MSR register ********************/
1832#define CAN_MSR_INAK_Pos (0U)
1833#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
1834#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
1835#define CAN_MSR_SLAK_Pos (1U)
1836#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
1837#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
1838#define CAN_MSR_ERRI_Pos (2U)
1839#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
1840#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
1841#define CAN_MSR_WKUI_Pos (3U)
1842#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
1843#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
1844#define CAN_MSR_SLAKI_Pos (4U)
1845#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
1846#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
1847#define CAN_MSR_TXM_Pos (8U)
1848#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
1849#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
1850#define CAN_MSR_RXM_Pos (9U)
1851#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
1852#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
1853#define CAN_MSR_SAMP_Pos (10U)
1854#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
1855#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
1856#define CAN_MSR_RX_Pos (11U)
1857#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
1858#define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
1859
1860/******************* Bit definition for CAN_TSR register ********************/
1861#define CAN_TSR_RQCP0_Pos (0U)
1862#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
1863#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
1864#define CAN_TSR_TXOK0_Pos (1U)
1865#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
1866#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
1867#define CAN_TSR_ALST0_Pos (2U)
1868#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
1869#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
1870#define CAN_TSR_TERR0_Pos (3U)
1871#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
1872#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
1873#define CAN_TSR_ABRQ0_Pos (7U)
1874#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
1875#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
1876#define CAN_TSR_RQCP1_Pos (8U)
1877#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
1878#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
1879#define CAN_TSR_TXOK1_Pos (9U)
1880#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
1881#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
1882#define CAN_TSR_ALST1_Pos (10U)
1883#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
1884#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
1885#define CAN_TSR_TERR1_Pos (11U)
1886#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
1887#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
1888#define CAN_TSR_ABRQ1_Pos (15U)
1889#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
1890#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
1891#define CAN_TSR_RQCP2_Pos (16U)
1892#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
1893#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
1894#define CAN_TSR_TXOK2_Pos (17U)
1895#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
1896#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
1897#define CAN_TSR_ALST2_Pos (18U)
1898#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
1899#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
1900#define CAN_TSR_TERR2_Pos (19U)
1901#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
1902#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
1903#define CAN_TSR_ABRQ2_Pos (23U)
1904#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
1905#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
1906#define CAN_TSR_CODE_Pos (24U)
1907#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
1908#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
1909
1910#define CAN_TSR_TME_Pos (26U)
1911#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
1912#define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
1913#define CAN_TSR_TME0_Pos (26U)
1914#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
1915#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
1916#define CAN_TSR_TME1_Pos (27U)
1917#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
1918#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
1919#define CAN_TSR_TME2_Pos (28U)
1920#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
1921#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
1922
1923#define CAN_TSR_LOW_Pos (29U)
1924#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
1925#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
1926#define CAN_TSR_LOW0_Pos (29U)
1927#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
1928#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
1929#define CAN_TSR_LOW1_Pos (30U)
1930#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
1931#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
1932#define CAN_TSR_LOW2_Pos (31U)
1933#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
1934#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
1935
1936/******************* Bit definition for CAN_RF0R register *******************/
1937#define CAN_RF0R_FMP0_Pos (0U)
1938#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
1939#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
1940#define CAN_RF0R_FULL0_Pos (3U)
1941#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
1942#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
1943#define CAN_RF0R_FOVR0_Pos (4U)
1944#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
1945#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
1946#define CAN_RF0R_RFOM0_Pos (5U)
1947#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
1948#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
1949
1950/******************* Bit definition for CAN_RF1R register *******************/
1951#define CAN_RF1R_FMP1_Pos (0U)
1952#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
1953#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
1954#define CAN_RF1R_FULL1_Pos (3U)
1955#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
1956#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
1957#define CAN_RF1R_FOVR1_Pos (4U)
1958#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
1959#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
1960#define CAN_RF1R_RFOM1_Pos (5U)
1961#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
1962#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
1963
1964/******************** Bit definition for CAN_IER register *******************/
1965#define CAN_IER_TMEIE_Pos (0U)
1966#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
1967#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
1968#define CAN_IER_FMPIE0_Pos (1U)
1969#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
1970#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
1971#define CAN_IER_FFIE0_Pos (2U)
1972#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
1973#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
1974#define CAN_IER_FOVIE0_Pos (3U)
1975#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
1976#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
1977#define CAN_IER_FMPIE1_Pos (4U)
1978#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
1979#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
1980#define CAN_IER_FFIE1_Pos (5U)
1981#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
1982#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
1983#define CAN_IER_FOVIE1_Pos (6U)
1984#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
1985#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
1986#define CAN_IER_EWGIE_Pos (8U)
1987#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
1988#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
1989#define CAN_IER_EPVIE_Pos (9U)
1990#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
1991#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
1992#define CAN_IER_BOFIE_Pos (10U)
1993#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
1994#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
1995#define CAN_IER_LECIE_Pos (11U)
1996#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
1997#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
1998#define CAN_IER_ERRIE_Pos (15U)
1999#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
2000#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
2001#define CAN_IER_WKUIE_Pos (16U)
2002#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
2003#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
2004#define CAN_IER_SLKIE_Pos (17U)
2005#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
2006#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
2007#define CAN_IER_EWGIE_Pos (8U)
2008
2009/******************** Bit definition for CAN_ESR register *******************/
2010#define CAN_ESR_EWGF_Pos (0U)
2011#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
2012#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
2013#define CAN_ESR_EPVF_Pos (1U)
2014#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
2015#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
2016#define CAN_ESR_BOFF_Pos (2U)
2017#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
2018#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
2019
2020#define CAN_ESR_LEC_Pos (4U)
2021#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
2022#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
2023#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
2024#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
2025#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
2026
2027#define CAN_ESR_TEC_Pos (16U)
2028#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
2029#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
2030#define CAN_ESR_REC_Pos (24U)
2031#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
2032#define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
2033
2034/******************* Bit definition for CAN_BTR register ********************/
2035#define CAN_BTR_BRP_Pos (0U)
2036#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
2037#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
2038#define CAN_BTR_TS1_Pos (16U)
2039#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
2040#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
2041#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
2042#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
2043#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
2044#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
2045#define CAN_BTR_TS2_Pos (20U)
2046#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
2047#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
2048#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
2049#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
2050#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
2051#define CAN_BTR_SJW_Pos (24U)
2052#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
2053#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
2054#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
2055#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
2056#define CAN_BTR_LBKM_Pos (30U)
2057#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
2058#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
2059#define CAN_BTR_SILM_Pos (31U)
2060#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
2061#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
2062
2063
2064/*!<Mailbox registers */
2065/****************** Bit definition for CAN_TI0R register ********************/
2066#define CAN_TI0R_TXRQ_Pos (0U)
2067#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
2068#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
2069#define CAN_TI0R_RTR_Pos (1U)
2070#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
2071#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
2072#define CAN_TI0R_IDE_Pos (2U)
2073#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
2074#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
2075#define CAN_TI0R_EXID_Pos (3U)
2076#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
2077#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
2078#define CAN_TI0R_STID_Pos (21U)
2079#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
2080#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2081
2082/****************** Bit definition for CAN_TDT0R register *******************/
2083#define CAN_TDT0R_DLC_Pos (0U)
2084#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
2085#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
2086#define CAN_TDT0R_TGT_Pos (8U)
2087#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
2088#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
2089#define CAN_TDT0R_TIME_Pos (16U)
2090#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2091#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
2092
2093/****************** Bit definition for CAN_TDL0R register *******************/
2094#define CAN_TDL0R_DATA0_Pos (0U)
2095#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
2096#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
2097#define CAN_TDL0R_DATA1_Pos (8U)
2098#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2099#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
2100#define CAN_TDL0R_DATA2_Pos (16U)
2101#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2102#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
2103#define CAN_TDL0R_DATA3_Pos (24U)
2104#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
2105#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
2106
2107/****************** Bit definition for CAN_TDH0R register *******************/
2108#define CAN_TDH0R_DATA4_Pos (0U)
2109#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
2110#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
2111#define CAN_TDH0R_DATA5_Pos (8U)
2112#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2113#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
2114#define CAN_TDH0R_DATA6_Pos (16U)
2115#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2116#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
2117#define CAN_TDH0R_DATA7_Pos (24U)
2118#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
2119#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
2120
2121/******************* Bit definition for CAN_TI1R register *******************/
2122#define CAN_TI1R_TXRQ_Pos (0U)
2123#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
2124#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
2125#define CAN_TI1R_RTR_Pos (1U)
2126#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
2127#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
2128#define CAN_TI1R_IDE_Pos (2U)
2129#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
2130#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
2131#define CAN_TI1R_EXID_Pos (3U)
2132#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
2133#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
2134#define CAN_TI1R_STID_Pos (21U)
2135#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
2136#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2137
2138/******************* Bit definition for CAN_TDT1R register ******************/
2139#define CAN_TDT1R_DLC_Pos (0U)
2140#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
2141#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
2142#define CAN_TDT1R_TGT_Pos (8U)
2143#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
2144#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
2145#define CAN_TDT1R_TIME_Pos (16U)
2146#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2147#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
2148
2149/******************* Bit definition for CAN_TDL1R register ******************/
2150#define CAN_TDL1R_DATA0_Pos (0U)
2151#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
2152#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
2153#define CAN_TDL1R_DATA1_Pos (8U)
2154#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2155#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
2156#define CAN_TDL1R_DATA2_Pos (16U)
2157#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2158#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
2159#define CAN_TDL1R_DATA3_Pos (24U)
2160#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
2161#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
2162
2163/******************* Bit definition for CAN_TDH1R register ******************/
2164#define CAN_TDH1R_DATA4_Pos (0U)
2165#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
2166#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
2167#define CAN_TDH1R_DATA5_Pos (8U)
2168#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2169#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
2170#define CAN_TDH1R_DATA6_Pos (16U)
2171#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2172#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
2173#define CAN_TDH1R_DATA7_Pos (24U)
2174#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
2175#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
2176
2177/******************* Bit definition for CAN_TI2R register *******************/
2178#define CAN_TI2R_TXRQ_Pos (0U)
2179#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
2180#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
2181#define CAN_TI2R_RTR_Pos (1U)
2182#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
2183#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
2184#define CAN_TI2R_IDE_Pos (2U)
2185#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
2186#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
2187#define CAN_TI2R_EXID_Pos (3U)
2188#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
2189#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
2190#define CAN_TI2R_STID_Pos (21U)
2191#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
2192#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2193
2194/******************* Bit definition for CAN_TDT2R register ******************/
2195#define CAN_TDT2R_DLC_Pos (0U)
2196#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
2197#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
2198#define CAN_TDT2R_TGT_Pos (8U)
2199#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
2200#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
2201#define CAN_TDT2R_TIME_Pos (16U)
2202#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
2203#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
2204
2205/******************* Bit definition for CAN_TDL2R register ******************/
2206#define CAN_TDL2R_DATA0_Pos (0U)
2207#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
2208#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
2209#define CAN_TDL2R_DATA1_Pos (8U)
2210#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
2211#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
2212#define CAN_TDL2R_DATA2_Pos (16U)
2213#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
2214#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
2215#define CAN_TDL2R_DATA3_Pos (24U)
2216#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
2217#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
2218
2219/******************* Bit definition for CAN_TDH2R register ******************/
2220#define CAN_TDH2R_DATA4_Pos (0U)
2221#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
2222#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
2223#define CAN_TDH2R_DATA5_Pos (8U)
2224#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
2225#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
2226#define CAN_TDH2R_DATA6_Pos (16U)
2227#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
2228#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
2229#define CAN_TDH2R_DATA7_Pos (24U)
2230#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
2231#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
2232
2233/******************* Bit definition for CAN_RI0R register *******************/
2234#define CAN_RI0R_RTR_Pos (1U)
2235#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
2236#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
2237#define CAN_RI0R_IDE_Pos (2U)
2238#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
2239#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
2240#define CAN_RI0R_EXID_Pos (3U)
2241#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
2242#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
2243#define CAN_RI0R_STID_Pos (21U)
2244#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
2245#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2246
2247/******************* Bit definition for CAN_RDT0R register ******************/
2248#define CAN_RDT0R_DLC_Pos (0U)
2249#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
2250#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
2251#define CAN_RDT0R_FMI_Pos (8U)
2252#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
2253#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
2254#define CAN_RDT0R_TIME_Pos (16U)
2255#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2256#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
2257
2258/******************* Bit definition for CAN_RDL0R register ******************/
2259#define CAN_RDL0R_DATA0_Pos (0U)
2260#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
2261#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
2262#define CAN_RDL0R_DATA1_Pos (8U)
2263#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2264#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
2265#define CAN_RDL0R_DATA2_Pos (16U)
2266#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2267#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
2268#define CAN_RDL0R_DATA3_Pos (24U)
2269#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
2270#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
2271
2272/******************* Bit definition for CAN_RDH0R register ******************/
2273#define CAN_RDH0R_DATA4_Pos (0U)
2274#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
2275#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
2276#define CAN_RDH0R_DATA5_Pos (8U)
2277#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2278#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
2279#define CAN_RDH0R_DATA6_Pos (16U)
2280#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2281#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
2282#define CAN_RDH0R_DATA7_Pos (24U)
2283#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
2284#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
2285
2286/******************* Bit definition for CAN_RI1R register *******************/
2287#define CAN_RI1R_RTR_Pos (1U)
2288#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
2289#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
2290#define CAN_RI1R_IDE_Pos (2U)
2291#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
2292#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
2293#define CAN_RI1R_EXID_Pos (3U)
2294#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
2295#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
2296#define CAN_RI1R_STID_Pos (21U)
2297#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
2298#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2299
2300/******************* Bit definition for CAN_RDT1R register ******************/
2301#define CAN_RDT1R_DLC_Pos (0U)
2302#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
2303#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
2304#define CAN_RDT1R_FMI_Pos (8U)
2305#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
2306#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
2307#define CAN_RDT1R_TIME_Pos (16U)
2308#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2309#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
2310
2311/******************* Bit definition for CAN_RDL1R register ******************/
2312#define CAN_RDL1R_DATA0_Pos (0U)
2313#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
2314#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
2315#define CAN_RDL1R_DATA1_Pos (8U)
2316#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2317#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
2318#define CAN_RDL1R_DATA2_Pos (16U)
2319#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2320#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
2321#define CAN_RDL1R_DATA3_Pos (24U)
2322#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
2323#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
2324
2325/******************* Bit definition for CAN_RDH1R register ******************/
2326#define CAN_RDH1R_DATA4_Pos (0U)
2327#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
2328#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
2329#define CAN_RDH1R_DATA5_Pos (8U)
2330#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2331#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
2332#define CAN_RDH1R_DATA6_Pos (16U)
2333#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2334#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
2335#define CAN_RDH1R_DATA7_Pos (24U)
2336#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
2337#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
2338
2339/*!<CAN filter registers */
2340/******************* Bit definition for CAN_FMR register ********************/
2341#define CAN_FMR_FINIT_Pos (0U)
2342#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
2343#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
2344#define CAN_FMR_CAN2SB_Pos (8U)
2345#define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
2346#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
2347
2348/******************* Bit definition for CAN_FM1R register *******************/
2349#define CAN_FM1R_FBM_Pos (0U)
2350#define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
2351#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
2352#define CAN_FM1R_FBM0_Pos (0U)
2353#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
2354#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
2355#define CAN_FM1R_FBM1_Pos (1U)
2356#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
2357#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
2358#define CAN_FM1R_FBM2_Pos (2U)
2359#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
2360#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
2361#define CAN_FM1R_FBM3_Pos (3U)
2362#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
2363#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
2364#define CAN_FM1R_FBM4_Pos (4U)
2365#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
2366#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
2367#define CAN_FM1R_FBM5_Pos (5U)
2368#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
2369#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
2370#define CAN_FM1R_FBM6_Pos (6U)
2371#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
2372#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
2373#define CAN_FM1R_FBM7_Pos (7U)
2374#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
2375#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
2376#define CAN_FM1R_FBM8_Pos (8U)
2377#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
2378#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
2379#define CAN_FM1R_FBM9_Pos (9U)
2380#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
2381#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
2382#define CAN_FM1R_FBM10_Pos (10U)
2383#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
2384#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
2385#define CAN_FM1R_FBM11_Pos (11U)
2386#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
2387#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
2388#define CAN_FM1R_FBM12_Pos (12U)
2389#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
2390#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
2391#define CAN_FM1R_FBM13_Pos (13U)
2392#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
2393#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
2394#define CAN_FM1R_FBM14_Pos (14U)
2395#define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
2396#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
2397#define CAN_FM1R_FBM15_Pos (15U)
2398#define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
2399#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
2400#define CAN_FM1R_FBM16_Pos (16U)
2401#define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
2402#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
2403#define CAN_FM1R_FBM17_Pos (17U)
2404#define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
2405#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
2406#define CAN_FM1R_FBM18_Pos (18U)
2407#define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
2408#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
2409#define CAN_FM1R_FBM19_Pos (19U)
2410#define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
2411#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
2412#define CAN_FM1R_FBM20_Pos (20U)
2413#define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
2414#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
2415#define CAN_FM1R_FBM21_Pos (21U)
2416#define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
2417#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
2418#define CAN_FM1R_FBM22_Pos (22U)
2419#define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
2420#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
2421#define CAN_FM1R_FBM23_Pos (23U)
2422#define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
2423#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
2424#define CAN_FM1R_FBM24_Pos (24U)
2425#define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
2426#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
2427#define CAN_FM1R_FBM25_Pos (25U)
2428#define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
2429#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
2430#define CAN_FM1R_FBM26_Pos (26U)
2431#define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
2432#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
2433#define CAN_FM1R_FBM27_Pos (27U)
2434#define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
2435#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
2436
2437/******************* Bit definition for CAN_FS1R register *******************/
2438#define CAN_FS1R_FSC_Pos (0U)
2439#define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
2440#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
2441#define CAN_FS1R_FSC0_Pos (0U)
2442#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
2443#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
2444#define CAN_FS1R_FSC1_Pos (1U)
2445#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
2446#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
2447#define CAN_FS1R_FSC2_Pos (2U)
2448#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
2449#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
2450#define CAN_FS1R_FSC3_Pos (3U)
2451#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
2452#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
2453#define CAN_FS1R_FSC4_Pos (4U)
2454#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
2455#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
2456#define CAN_FS1R_FSC5_Pos (5U)
2457#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
2458#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
2459#define CAN_FS1R_FSC6_Pos (6U)
2460#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
2461#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
2462#define CAN_FS1R_FSC7_Pos (7U)
2463#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
2464#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
2465#define CAN_FS1R_FSC8_Pos (8U)
2466#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
2467#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
2468#define CAN_FS1R_FSC9_Pos (9U)
2469#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
2470#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
2471#define CAN_FS1R_FSC10_Pos (10U)
2472#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
2473#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
2474#define CAN_FS1R_FSC11_Pos (11U)
2475#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
2476#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
2477#define CAN_FS1R_FSC12_Pos (12U)
2478#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
2479#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
2480#define CAN_FS1R_FSC13_Pos (13U)
2481#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
2482#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
2483#define CAN_FS1R_FSC14_Pos (14U)
2484#define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
2485#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
2486#define CAN_FS1R_FSC15_Pos (15U)
2487#define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
2488#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
2489#define CAN_FS1R_FSC16_Pos (16U)
2490#define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
2491#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
2492#define CAN_FS1R_FSC17_Pos (17U)
2493#define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
2494#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
2495#define CAN_FS1R_FSC18_Pos (18U)
2496#define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
2497#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
2498#define CAN_FS1R_FSC19_Pos (19U)
2499#define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
2500#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
2501#define CAN_FS1R_FSC20_Pos (20U)
2502#define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
2503#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
2504#define CAN_FS1R_FSC21_Pos (21U)
2505#define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
2506#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
2507#define CAN_FS1R_FSC22_Pos (22U)
2508#define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
2509#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
2510#define CAN_FS1R_FSC23_Pos (23U)
2511#define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
2512#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
2513#define CAN_FS1R_FSC24_Pos (24U)
2514#define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
2515#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
2516#define CAN_FS1R_FSC25_Pos (25U)
2517#define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
2518#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
2519#define CAN_FS1R_FSC26_Pos (26U)
2520#define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
2521#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
2522#define CAN_FS1R_FSC27_Pos (27U)
2523#define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
2524#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
2525
2526/****************** Bit definition for CAN_FFA1R register *******************/
2527#define CAN_FFA1R_FFA_Pos (0U)
2528#define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
2529#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
2530#define CAN_FFA1R_FFA0_Pos (0U)
2531#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
2532#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
2533#define CAN_FFA1R_FFA1_Pos (1U)
2534#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
2535#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
2536#define CAN_FFA1R_FFA2_Pos (2U)
2537#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
2538#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
2539#define CAN_FFA1R_FFA3_Pos (3U)
2540#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
2541#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
2542#define CAN_FFA1R_FFA4_Pos (4U)
2543#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
2544#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
2545#define CAN_FFA1R_FFA5_Pos (5U)
2546#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
2547#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
2548#define CAN_FFA1R_FFA6_Pos (6U)
2549#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
2550#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
2551#define CAN_FFA1R_FFA7_Pos (7U)
2552#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
2553#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
2554#define CAN_FFA1R_FFA8_Pos (8U)
2555#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
2556#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
2557#define CAN_FFA1R_FFA9_Pos (9U)
2558#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
2559#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
2560#define CAN_FFA1R_FFA10_Pos (10U)
2561#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
2562#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
2563#define CAN_FFA1R_FFA11_Pos (11U)
2564#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
2565#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
2566#define CAN_FFA1R_FFA12_Pos (12U)
2567#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
2568#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
2569#define CAN_FFA1R_FFA13_Pos (13U)
2570#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
2571#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
2572#define CAN_FFA1R_FFA14_Pos (14U)
2573#define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
2574#define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
2575#define CAN_FFA1R_FFA15_Pos (15U)
2576#define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
2577#define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
2578#define CAN_FFA1R_FFA16_Pos (16U)
2579#define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
2580#define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
2581#define CAN_FFA1R_FFA17_Pos (17U)
2582#define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
2583#define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
2584#define CAN_FFA1R_FFA18_Pos (18U)
2585#define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
2586#define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
2587#define CAN_FFA1R_FFA19_Pos (19U)
2588#define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
2589#define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
2590#define CAN_FFA1R_FFA20_Pos (20U)
2591#define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
2592#define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
2593#define CAN_FFA1R_FFA21_Pos (21U)
2594#define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
2595#define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
2596#define CAN_FFA1R_FFA22_Pos (22U)
2597#define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
2598#define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
2599#define CAN_FFA1R_FFA23_Pos (23U)
2600#define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
2601#define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
2602#define CAN_FFA1R_FFA24_Pos (24U)
2603#define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
2604#define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
2605#define CAN_FFA1R_FFA25_Pos (25U)
2606#define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
2607#define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
2608#define CAN_FFA1R_FFA26_Pos (26U)
2609#define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
2610#define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
2611#define CAN_FFA1R_FFA27_Pos (27U)
2612#define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
2613#define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
2614
2615/******************* Bit definition for CAN_FA1R register *******************/
2616#define CAN_FA1R_FACT_Pos (0U)
2617#define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
2618#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
2619#define CAN_FA1R_FACT0_Pos (0U)
2620#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
2621#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
2622#define CAN_FA1R_FACT1_Pos (1U)
2623#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
2624#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
2625#define CAN_FA1R_FACT2_Pos (2U)
2626#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
2627#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
2628#define CAN_FA1R_FACT3_Pos (3U)
2629#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
2630#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
2631#define CAN_FA1R_FACT4_Pos (4U)
2632#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
2633#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
2634#define CAN_FA1R_FACT5_Pos (5U)
2635#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
2636#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
2637#define CAN_FA1R_FACT6_Pos (6U)
2638#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
2639#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
2640#define CAN_FA1R_FACT7_Pos (7U)
2641#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
2642#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
2643#define CAN_FA1R_FACT8_Pos (8U)
2644#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
2645#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
2646#define CAN_FA1R_FACT9_Pos (9U)
2647#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
2648#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
2649#define CAN_FA1R_FACT10_Pos (10U)
2650#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
2651#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
2652#define CAN_FA1R_FACT11_Pos (11U)
2653#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
2654#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
2655#define CAN_FA1R_FACT12_Pos (12U)
2656#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
2657#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
2658#define CAN_FA1R_FACT13_Pos (13U)
2659#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
2660#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
2661#define CAN_FA1R_FACT14_Pos (14U)
2662#define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
2663#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
2664#define CAN_FA1R_FACT15_Pos (15U)
2665#define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
2666#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
2667#define CAN_FA1R_FACT16_Pos (16U)
2668#define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
2669#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
2670#define CAN_FA1R_FACT17_Pos (17U)
2671#define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
2672#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
2673#define CAN_FA1R_FACT18_Pos (18U)
2674#define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
2675#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
2676#define CAN_FA1R_FACT19_Pos (19U)
2677#define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
2678#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
2679#define CAN_FA1R_FACT20_Pos (20U)
2680#define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
2681#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
2682#define CAN_FA1R_FACT21_Pos (21U)
2683#define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
2684#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
2685#define CAN_FA1R_FACT22_Pos (22U)
2686#define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
2687#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
2688#define CAN_FA1R_FACT23_Pos (23U)
2689#define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
2690#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
2691#define CAN_FA1R_FACT24_Pos (24U)
2692#define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
2693#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
2694#define CAN_FA1R_FACT25_Pos (25U)
2695#define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
2696#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
2697#define CAN_FA1R_FACT26_Pos (26U)
2698#define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
2699#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
2700#define CAN_FA1R_FACT27_Pos (27U)
2701#define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
2702#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
2703
2704
2705/******************* Bit definition for CAN_F0R1 register *******************/
2706#define CAN_F0R1_FB0_Pos (0U)
2707#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
2708#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
2709#define CAN_F0R1_FB1_Pos (1U)
2710#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
2711#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
2712#define CAN_F0R1_FB2_Pos (2U)
2713#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
2714#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
2715#define CAN_F0R1_FB3_Pos (3U)
2716#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
2717#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
2718#define CAN_F0R1_FB4_Pos (4U)
2719#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
2720#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
2721#define CAN_F0R1_FB5_Pos (5U)
2722#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
2723#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
2724#define CAN_F0R1_FB6_Pos (6U)
2725#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
2726#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
2727#define CAN_F0R1_FB7_Pos (7U)
2728#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
2729#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
2730#define CAN_F0R1_FB8_Pos (8U)
2731#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
2732#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
2733#define CAN_F0R1_FB9_Pos (9U)
2734#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
2735#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
2736#define CAN_F0R1_FB10_Pos (10U)
2737#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
2738#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
2739#define CAN_F0R1_FB11_Pos (11U)
2740#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
2741#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
2742#define CAN_F0R1_FB12_Pos (12U)
2743#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
2744#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
2745#define CAN_F0R1_FB13_Pos (13U)
2746#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
2747#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
2748#define CAN_F0R1_FB14_Pos (14U)
2749#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
2750#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
2751#define CAN_F0R1_FB15_Pos (15U)
2752#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
2753#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
2754#define CAN_F0R1_FB16_Pos (16U)
2755#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
2756#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
2757#define CAN_F0R1_FB17_Pos (17U)
2758#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
2759#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
2760#define CAN_F0R1_FB18_Pos (18U)
2761#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
2762#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
2763#define CAN_F0R1_FB19_Pos (19U)
2764#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
2765#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
2766#define CAN_F0R1_FB20_Pos (20U)
2767#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
2768#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
2769#define CAN_F0R1_FB21_Pos (21U)
2770#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
2771#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
2772#define CAN_F0R1_FB22_Pos (22U)
2773#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
2774#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
2775#define CAN_F0R1_FB23_Pos (23U)
2776#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
2777#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
2778#define CAN_F0R1_FB24_Pos (24U)
2779#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
2780#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
2781#define CAN_F0R1_FB25_Pos (25U)
2782#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
2783#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
2784#define CAN_F0R1_FB26_Pos (26U)
2785#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
2786#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
2787#define CAN_F0R1_FB27_Pos (27U)
2788#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
2789#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
2790#define CAN_F0R1_FB28_Pos (28U)
2791#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
2792#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
2793#define CAN_F0R1_FB29_Pos (29U)
2794#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
2795#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
2796#define CAN_F0R1_FB30_Pos (30U)
2797#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
2798#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
2799#define CAN_F0R1_FB31_Pos (31U)
2800#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
2801#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
2802
2803/******************* Bit definition for CAN_F1R1 register *******************/
2804#define CAN_F1R1_FB0_Pos (0U)
2805#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
2806#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
2807#define CAN_F1R1_FB1_Pos (1U)
2808#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
2809#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
2810#define CAN_F1R1_FB2_Pos (2U)
2811#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
2812#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
2813#define CAN_F1R1_FB3_Pos (3U)
2814#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
2815#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
2816#define CAN_F1R1_FB4_Pos (4U)
2817#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
2818#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
2819#define CAN_F1R1_FB5_Pos (5U)
2820#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
2821#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
2822#define CAN_F1R1_FB6_Pos (6U)
2823#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
2824#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
2825#define CAN_F1R1_FB7_Pos (7U)
2826#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
2827#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
2828#define CAN_F1R1_FB8_Pos (8U)
2829#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
2830#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
2831#define CAN_F1R1_FB9_Pos (9U)
2832#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
2833#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
2834#define CAN_F1R1_FB10_Pos (10U)
2835#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
2836#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
2837#define CAN_F1R1_FB11_Pos (11U)
2838#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
2839#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
2840#define CAN_F1R1_FB12_Pos (12U)
2841#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
2842#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
2843#define CAN_F1R1_FB13_Pos (13U)
2844#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
2845#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
2846#define CAN_F1R1_FB14_Pos (14U)
2847#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
2848#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
2849#define CAN_F1R1_FB15_Pos (15U)
2850#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
2851#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
2852#define CAN_F1R1_FB16_Pos (16U)
2853#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
2854#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
2855#define CAN_F1R1_FB17_Pos (17U)
2856#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
2857#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
2858#define CAN_F1R1_FB18_Pos (18U)
2859#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
2860#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
2861#define CAN_F1R1_FB19_Pos (19U)
2862#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
2863#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
2864#define CAN_F1R1_FB20_Pos (20U)
2865#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
2866#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
2867#define CAN_F1R1_FB21_Pos (21U)
2868#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
2869#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
2870#define CAN_F1R1_FB22_Pos (22U)
2871#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
2872#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
2873#define CAN_F1R1_FB23_Pos (23U)
2874#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
2875#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
2876#define CAN_F1R1_FB24_Pos (24U)
2877#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
2878#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
2879#define CAN_F1R1_FB25_Pos (25U)
2880#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
2881#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
2882#define CAN_F1R1_FB26_Pos (26U)
2883#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
2884#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
2885#define CAN_F1R1_FB27_Pos (27U)
2886#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
2887#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
2888#define CAN_F1R1_FB28_Pos (28U)
2889#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
2890#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
2891#define CAN_F1R1_FB29_Pos (29U)
2892#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
2893#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
2894#define CAN_F1R1_FB30_Pos (30U)
2895#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
2896#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
2897#define CAN_F1R1_FB31_Pos (31U)
2898#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
2899#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
2900
2901/******************* Bit definition for CAN_F2R1 register *******************/
2902#define CAN_F2R1_FB0_Pos (0U)
2903#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
2904#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
2905#define CAN_F2R1_FB1_Pos (1U)
2906#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
2907#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
2908#define CAN_F2R1_FB2_Pos (2U)
2909#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
2910#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
2911#define CAN_F2R1_FB3_Pos (3U)
2912#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
2913#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
2914#define CAN_F2R1_FB4_Pos (4U)
2915#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
2916#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
2917#define CAN_F2R1_FB5_Pos (5U)
2918#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
2919#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
2920#define CAN_F2R1_FB6_Pos (6U)
2921#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
2922#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
2923#define CAN_F2R1_FB7_Pos (7U)
2924#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
2925#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
2926#define CAN_F2R1_FB8_Pos (8U)
2927#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
2928#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
2929#define CAN_F2R1_FB9_Pos (9U)
2930#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
2931#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
2932#define CAN_F2R1_FB10_Pos (10U)
2933#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
2934#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
2935#define CAN_F2R1_FB11_Pos (11U)
2936#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
2937#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
2938#define CAN_F2R1_FB12_Pos (12U)
2939#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
2940#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
2941#define CAN_F2R1_FB13_Pos (13U)
2942#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
2943#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
2944#define CAN_F2R1_FB14_Pos (14U)
2945#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
2946#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
2947#define CAN_F2R1_FB15_Pos (15U)
2948#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
2949#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
2950#define CAN_F2R1_FB16_Pos (16U)
2951#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
2952#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
2953#define CAN_F2R1_FB17_Pos (17U)
2954#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
2955#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
2956#define CAN_F2R1_FB18_Pos (18U)
2957#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
2958#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
2959#define CAN_F2R1_FB19_Pos (19U)
2960#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
2961#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
2962#define CAN_F2R1_FB20_Pos (20U)
2963#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
2964#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
2965#define CAN_F2R1_FB21_Pos (21U)
2966#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
2967#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
2968#define CAN_F2R1_FB22_Pos (22U)
2969#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
2970#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
2971#define CAN_F2R1_FB23_Pos (23U)
2972#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
2973#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
2974#define CAN_F2R1_FB24_Pos (24U)
2975#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
2976#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
2977#define CAN_F2R1_FB25_Pos (25U)
2978#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
2979#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
2980#define CAN_F2R1_FB26_Pos (26U)
2981#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
2982#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
2983#define CAN_F2R1_FB27_Pos (27U)
2984#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
2985#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
2986#define CAN_F2R1_FB28_Pos (28U)
2987#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
2988#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
2989#define CAN_F2R1_FB29_Pos (29U)
2990#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
2991#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
2992#define CAN_F2R1_FB30_Pos (30U)
2993#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
2994#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
2995#define CAN_F2R1_FB31_Pos (31U)
2996#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
2997#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
2998
2999/******************* Bit definition for CAN_F3R1 register *******************/
3000#define CAN_F3R1_FB0_Pos (0U)
3001#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
3002#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
3003#define CAN_F3R1_FB1_Pos (1U)
3004#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
3005#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
3006#define CAN_F3R1_FB2_Pos (2U)
3007#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
3008#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
3009#define CAN_F3R1_FB3_Pos (3U)
3010#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
3011#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
3012#define CAN_F3R1_FB4_Pos (4U)
3013#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
3014#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
3015#define CAN_F3R1_FB5_Pos (5U)
3016#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
3017#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
3018#define CAN_F3R1_FB6_Pos (6U)
3019#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
3020#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
3021#define CAN_F3R1_FB7_Pos (7U)
3022#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
3023#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
3024#define CAN_F3R1_FB8_Pos (8U)
3025#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
3026#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
3027#define CAN_F3R1_FB9_Pos (9U)
3028#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
3029#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
3030#define CAN_F3R1_FB10_Pos (10U)
3031#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
3032#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
3033#define CAN_F3R1_FB11_Pos (11U)
3034#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
3035#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
3036#define CAN_F3R1_FB12_Pos (12U)
3037#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
3038#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
3039#define CAN_F3R1_FB13_Pos (13U)
3040#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
3041#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
3042#define CAN_F3R1_FB14_Pos (14U)
3043#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
3044#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
3045#define CAN_F3R1_FB15_Pos (15U)
3046#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
3047#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
3048#define CAN_F3R1_FB16_Pos (16U)
3049#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
3050#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
3051#define CAN_F3R1_FB17_Pos (17U)
3052#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
3053#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
3054#define CAN_F3R1_FB18_Pos (18U)
3055#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
3056#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
3057#define CAN_F3R1_FB19_Pos (19U)
3058#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
3059#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
3060#define CAN_F3R1_FB20_Pos (20U)
3061#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
3062#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
3063#define CAN_F3R1_FB21_Pos (21U)
3064#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
3065#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
3066#define CAN_F3R1_FB22_Pos (22U)
3067#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
3068#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
3069#define CAN_F3R1_FB23_Pos (23U)
3070#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
3071#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
3072#define CAN_F3R1_FB24_Pos (24U)
3073#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
3074#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
3075#define CAN_F3R1_FB25_Pos (25U)
3076#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
3077#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
3078#define CAN_F3R1_FB26_Pos (26U)
3079#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
3080#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
3081#define CAN_F3R1_FB27_Pos (27U)
3082#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
3083#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
3084#define CAN_F3R1_FB28_Pos (28U)
3085#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
3086#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
3087#define CAN_F3R1_FB29_Pos (29U)
3088#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
3089#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
3090#define CAN_F3R1_FB30_Pos (30U)
3091#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
3092#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
3093#define CAN_F3R1_FB31_Pos (31U)
3094#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
3095#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
3096
3097/******************* Bit definition for CAN_F4R1 register *******************/
3098#define CAN_F4R1_FB0_Pos (0U)
3099#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
3100#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
3101#define CAN_F4R1_FB1_Pos (1U)
3102#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
3103#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
3104#define CAN_F4R1_FB2_Pos (2U)
3105#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
3106#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
3107#define CAN_F4R1_FB3_Pos (3U)
3108#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
3109#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
3110#define CAN_F4R1_FB4_Pos (4U)
3111#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
3112#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
3113#define CAN_F4R1_FB5_Pos (5U)
3114#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
3115#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
3116#define CAN_F4R1_FB6_Pos (6U)
3117#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
3118#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
3119#define CAN_F4R1_FB7_Pos (7U)
3120#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
3121#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
3122#define CAN_F4R1_FB8_Pos (8U)
3123#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
3124#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
3125#define CAN_F4R1_FB9_Pos (9U)
3126#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
3127#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
3128#define CAN_F4R1_FB10_Pos (10U)
3129#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
3130#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
3131#define CAN_F4R1_FB11_Pos (11U)
3132#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
3133#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
3134#define CAN_F4R1_FB12_Pos (12U)
3135#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
3136#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
3137#define CAN_F4R1_FB13_Pos (13U)
3138#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
3139#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
3140#define CAN_F4R1_FB14_Pos (14U)
3141#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
3142#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
3143#define CAN_F4R1_FB15_Pos (15U)
3144#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
3145#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
3146#define CAN_F4R1_FB16_Pos (16U)
3147#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
3148#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
3149#define CAN_F4R1_FB17_Pos (17U)
3150#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
3151#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
3152#define CAN_F4R1_FB18_Pos (18U)
3153#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
3154#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
3155#define CAN_F4R1_FB19_Pos (19U)
3156#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
3157#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
3158#define CAN_F4R1_FB20_Pos (20U)
3159#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
3160#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
3161#define CAN_F4R1_FB21_Pos (21U)
3162#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
3163#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
3164#define CAN_F4R1_FB22_Pos (22U)
3165#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
3166#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
3167#define CAN_F4R1_FB23_Pos (23U)
3168#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
3169#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
3170#define CAN_F4R1_FB24_Pos (24U)
3171#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
3172#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
3173#define CAN_F4R1_FB25_Pos (25U)
3174#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
3175#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
3176#define CAN_F4R1_FB26_Pos (26U)
3177#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
3178#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
3179#define CAN_F4R1_FB27_Pos (27U)
3180#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
3181#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
3182#define CAN_F4R1_FB28_Pos (28U)
3183#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
3184#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
3185#define CAN_F4R1_FB29_Pos (29U)
3186#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
3187#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
3188#define CAN_F4R1_FB30_Pos (30U)
3189#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
3190#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
3191#define CAN_F4R1_FB31_Pos (31U)
3192#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
3193#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
3194
3195/******************* Bit definition for CAN_F5R1 register *******************/
3196#define CAN_F5R1_FB0_Pos (0U)
3197#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
3198#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
3199#define CAN_F5R1_FB1_Pos (1U)
3200#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
3201#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
3202#define CAN_F5R1_FB2_Pos (2U)
3203#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
3204#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
3205#define CAN_F5R1_FB3_Pos (3U)
3206#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
3207#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
3208#define CAN_F5R1_FB4_Pos (4U)
3209#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
3210#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
3211#define CAN_F5R1_FB5_Pos (5U)
3212#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
3213#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
3214#define CAN_F5R1_FB6_Pos (6U)
3215#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
3216#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
3217#define CAN_F5R1_FB7_Pos (7U)
3218#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
3219#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
3220#define CAN_F5R1_FB8_Pos (8U)
3221#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
3222#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
3223#define CAN_F5R1_FB9_Pos (9U)
3224#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
3225#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
3226#define CAN_F5R1_FB10_Pos (10U)
3227#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
3228#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
3229#define CAN_F5R1_FB11_Pos (11U)
3230#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
3231#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
3232#define CAN_F5R1_FB12_Pos (12U)
3233#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
3234#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
3235#define CAN_F5R1_FB13_Pos (13U)
3236#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
3237#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
3238#define CAN_F5R1_FB14_Pos (14U)
3239#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
3240#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
3241#define CAN_F5R1_FB15_Pos (15U)
3242#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
3243#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
3244#define CAN_F5R1_FB16_Pos (16U)
3245#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
3246#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
3247#define CAN_F5R1_FB17_Pos (17U)
3248#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
3249#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
3250#define CAN_F5R1_FB18_Pos (18U)
3251#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
3252#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
3253#define CAN_F5R1_FB19_Pos (19U)
3254#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
3255#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
3256#define CAN_F5R1_FB20_Pos (20U)
3257#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
3258#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
3259#define CAN_F5R1_FB21_Pos (21U)
3260#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
3261#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
3262#define CAN_F5R1_FB22_Pos (22U)
3263#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
3264#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
3265#define CAN_F5R1_FB23_Pos (23U)
3266#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
3267#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
3268#define CAN_F5R1_FB24_Pos (24U)
3269#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
3270#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
3271#define CAN_F5R1_FB25_Pos (25U)
3272#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
3273#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
3274#define CAN_F5R1_FB26_Pos (26U)
3275#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
3276#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
3277#define CAN_F5R1_FB27_Pos (27U)
3278#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
3279#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
3280#define CAN_F5R1_FB28_Pos (28U)
3281#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
3282#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
3283#define CAN_F5R1_FB29_Pos (29U)
3284#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
3285#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
3286#define CAN_F5R1_FB30_Pos (30U)
3287#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
3288#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
3289#define CAN_F5R1_FB31_Pos (31U)
3290#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
3291#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
3292
3293/******************* Bit definition for CAN_F6R1 register *******************/
3294#define CAN_F6R1_FB0_Pos (0U)
3295#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
3296#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
3297#define CAN_F6R1_FB1_Pos (1U)
3298#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
3299#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
3300#define CAN_F6R1_FB2_Pos (2U)
3301#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
3302#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
3303#define CAN_F6R1_FB3_Pos (3U)
3304#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
3305#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
3306#define CAN_F6R1_FB4_Pos (4U)
3307#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
3308#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
3309#define CAN_F6R1_FB5_Pos (5U)
3310#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
3311#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
3312#define CAN_F6R1_FB6_Pos (6U)
3313#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
3314#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
3315#define CAN_F6R1_FB7_Pos (7U)
3316#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
3317#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
3318#define CAN_F6R1_FB8_Pos (8U)
3319#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
3320#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
3321#define CAN_F6R1_FB9_Pos (9U)
3322#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
3323#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
3324#define CAN_F6R1_FB10_Pos (10U)
3325#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
3326#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
3327#define CAN_F6R1_FB11_Pos (11U)
3328#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
3329#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
3330#define CAN_F6R1_FB12_Pos (12U)
3331#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
3332#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
3333#define CAN_F6R1_FB13_Pos (13U)
3334#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
3335#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
3336#define CAN_F6R1_FB14_Pos (14U)
3337#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
3338#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
3339#define CAN_F6R1_FB15_Pos (15U)
3340#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
3341#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
3342#define CAN_F6R1_FB16_Pos (16U)
3343#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
3344#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
3345#define CAN_F6R1_FB17_Pos (17U)
3346#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
3347#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
3348#define CAN_F6R1_FB18_Pos (18U)
3349#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
3350#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
3351#define CAN_F6R1_FB19_Pos (19U)
3352#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
3353#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
3354#define CAN_F6R1_FB20_Pos (20U)
3355#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
3356#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
3357#define CAN_F6R1_FB21_Pos (21U)
3358#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
3359#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
3360#define CAN_F6R1_FB22_Pos (22U)
3361#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
3362#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
3363#define CAN_F6R1_FB23_Pos (23U)
3364#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
3365#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
3366#define CAN_F6R1_FB24_Pos (24U)
3367#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
3368#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
3369#define CAN_F6R1_FB25_Pos (25U)
3370#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
3371#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
3372#define CAN_F6R1_FB26_Pos (26U)
3373#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
3374#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
3375#define CAN_F6R1_FB27_Pos (27U)
3376#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
3377#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
3378#define CAN_F6R1_FB28_Pos (28U)
3379#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
3380#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
3381#define CAN_F6R1_FB29_Pos (29U)
3382#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
3383#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
3384#define CAN_F6R1_FB30_Pos (30U)
3385#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
3386#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
3387#define CAN_F6R1_FB31_Pos (31U)
3388#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
3389#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
3390
3391/******************* Bit definition for CAN_F7R1 register *******************/
3392#define CAN_F7R1_FB0_Pos (0U)
3393#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
3394#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
3395#define CAN_F7R1_FB1_Pos (1U)
3396#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
3397#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
3398#define CAN_F7R1_FB2_Pos (2U)
3399#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
3400#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
3401#define CAN_F7R1_FB3_Pos (3U)
3402#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
3403#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
3404#define CAN_F7R1_FB4_Pos (4U)
3405#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
3406#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
3407#define CAN_F7R1_FB5_Pos (5U)
3408#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
3409#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
3410#define CAN_F7R1_FB6_Pos (6U)
3411#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
3412#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
3413#define CAN_F7R1_FB7_Pos (7U)
3414#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
3415#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
3416#define CAN_F7R1_FB8_Pos (8U)
3417#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
3418#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
3419#define CAN_F7R1_FB9_Pos (9U)
3420#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
3421#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
3422#define CAN_F7R1_FB10_Pos (10U)
3423#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
3424#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
3425#define CAN_F7R1_FB11_Pos (11U)
3426#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
3427#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
3428#define CAN_F7R1_FB12_Pos (12U)
3429#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
3430#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
3431#define CAN_F7R1_FB13_Pos (13U)
3432#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
3433#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
3434#define CAN_F7R1_FB14_Pos (14U)
3435#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
3436#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
3437#define CAN_F7R1_FB15_Pos (15U)
3438#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
3439#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
3440#define CAN_F7R1_FB16_Pos (16U)
3441#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
3442#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
3443#define CAN_F7R1_FB17_Pos (17U)
3444#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
3445#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
3446#define CAN_F7R1_FB18_Pos (18U)
3447#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
3448#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
3449#define CAN_F7R1_FB19_Pos (19U)
3450#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
3451#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
3452#define CAN_F7R1_FB20_Pos (20U)
3453#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
3454#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
3455#define CAN_F7R1_FB21_Pos (21U)
3456#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
3457#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
3458#define CAN_F7R1_FB22_Pos (22U)
3459#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
3460#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
3461#define CAN_F7R1_FB23_Pos (23U)
3462#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
3463#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
3464#define CAN_F7R1_FB24_Pos (24U)
3465#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
3466#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
3467#define CAN_F7R1_FB25_Pos (25U)
3468#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
3469#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
3470#define CAN_F7R1_FB26_Pos (26U)
3471#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
3472#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
3473#define CAN_F7R1_FB27_Pos (27U)
3474#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
3475#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
3476#define CAN_F7R1_FB28_Pos (28U)
3477#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
3478#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
3479#define CAN_F7R1_FB29_Pos (29U)
3480#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
3481#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
3482#define CAN_F7R1_FB30_Pos (30U)
3483#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
3484#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
3485#define CAN_F7R1_FB31_Pos (31U)
3486#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
3487#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
3488
3489/******************* Bit definition for CAN_F8R1 register *******************/
3490#define CAN_F8R1_FB0_Pos (0U)
3491#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
3492#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
3493#define CAN_F8R1_FB1_Pos (1U)
3494#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
3495#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
3496#define CAN_F8R1_FB2_Pos (2U)
3497#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
3498#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
3499#define CAN_F8R1_FB3_Pos (3U)
3500#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
3501#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
3502#define CAN_F8R1_FB4_Pos (4U)
3503#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
3504#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
3505#define CAN_F8R1_FB5_Pos (5U)
3506#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
3507#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
3508#define CAN_F8R1_FB6_Pos (6U)
3509#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
3510#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
3511#define CAN_F8R1_FB7_Pos (7U)
3512#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
3513#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
3514#define CAN_F8R1_FB8_Pos (8U)
3515#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
3516#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
3517#define CAN_F8R1_FB9_Pos (9U)
3518#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
3519#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
3520#define CAN_F8R1_FB10_Pos (10U)
3521#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
3522#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
3523#define CAN_F8R1_FB11_Pos (11U)
3524#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
3525#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
3526#define CAN_F8R1_FB12_Pos (12U)
3527#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
3528#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
3529#define CAN_F8R1_FB13_Pos (13U)
3530#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
3531#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
3532#define CAN_F8R1_FB14_Pos (14U)
3533#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
3534#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
3535#define CAN_F8R1_FB15_Pos (15U)
3536#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
3537#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
3538#define CAN_F8R1_FB16_Pos (16U)
3539#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
3540#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
3541#define CAN_F8R1_FB17_Pos (17U)
3542#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
3543#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
3544#define CAN_F8R1_FB18_Pos (18U)
3545#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
3546#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
3547#define CAN_F8R1_FB19_Pos (19U)
3548#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
3549#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
3550#define CAN_F8R1_FB20_Pos (20U)
3551#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
3552#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
3553#define CAN_F8R1_FB21_Pos (21U)
3554#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
3555#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
3556#define CAN_F8R1_FB22_Pos (22U)
3557#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
3558#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
3559#define CAN_F8R1_FB23_Pos (23U)
3560#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
3561#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
3562#define CAN_F8R1_FB24_Pos (24U)
3563#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
3564#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
3565#define CAN_F8R1_FB25_Pos (25U)
3566#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
3567#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
3568#define CAN_F8R1_FB26_Pos (26U)
3569#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
3570#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
3571#define CAN_F8R1_FB27_Pos (27U)
3572#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
3573#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
3574#define CAN_F8R1_FB28_Pos (28U)
3575#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
3576#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
3577#define CAN_F8R1_FB29_Pos (29U)
3578#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
3579#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
3580#define CAN_F8R1_FB30_Pos (30U)
3581#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
3582#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
3583#define CAN_F8R1_FB31_Pos (31U)
3584#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
3585#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
3586
3587/******************* Bit definition for CAN_F9R1 register *******************/
3588#define CAN_F9R1_FB0_Pos (0U)
3589#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
3590#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
3591#define CAN_F9R1_FB1_Pos (1U)
3592#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
3593#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
3594#define CAN_F9R1_FB2_Pos (2U)
3595#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
3596#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
3597#define CAN_F9R1_FB3_Pos (3U)
3598#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
3599#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
3600#define CAN_F9R1_FB4_Pos (4U)
3601#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
3602#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
3603#define CAN_F9R1_FB5_Pos (5U)
3604#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
3605#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
3606#define CAN_F9R1_FB6_Pos (6U)
3607#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
3608#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
3609#define CAN_F9R1_FB7_Pos (7U)
3610#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
3611#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
3612#define CAN_F9R1_FB8_Pos (8U)
3613#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
3614#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
3615#define CAN_F9R1_FB9_Pos (9U)
3616#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
3617#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
3618#define CAN_F9R1_FB10_Pos (10U)
3619#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
3620#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
3621#define CAN_F9R1_FB11_Pos (11U)
3622#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
3623#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
3624#define CAN_F9R1_FB12_Pos (12U)
3625#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
3626#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
3627#define CAN_F9R1_FB13_Pos (13U)
3628#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
3629#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
3630#define CAN_F9R1_FB14_Pos (14U)
3631#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
3632#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
3633#define CAN_F9R1_FB15_Pos (15U)
3634#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
3635#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
3636#define CAN_F9R1_FB16_Pos (16U)
3637#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
3638#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
3639#define CAN_F9R1_FB17_Pos (17U)
3640#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
3641#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
3642#define CAN_F9R1_FB18_Pos (18U)
3643#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
3644#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
3645#define CAN_F9R1_FB19_Pos (19U)
3646#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
3647#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
3648#define CAN_F9R1_FB20_Pos (20U)
3649#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
3650#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
3651#define CAN_F9R1_FB21_Pos (21U)
3652#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
3653#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
3654#define CAN_F9R1_FB22_Pos (22U)
3655#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
3656#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
3657#define CAN_F9R1_FB23_Pos (23U)
3658#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
3659#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
3660#define CAN_F9R1_FB24_Pos (24U)
3661#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
3662#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
3663#define CAN_F9R1_FB25_Pos (25U)
3664#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
3665#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
3666#define CAN_F9R1_FB26_Pos (26U)
3667#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
3668#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
3669#define CAN_F9R1_FB27_Pos (27U)
3670#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
3671#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
3672#define CAN_F9R1_FB28_Pos (28U)
3673#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
3674#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
3675#define CAN_F9R1_FB29_Pos (29U)
3676#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
3677#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
3678#define CAN_F9R1_FB30_Pos (30U)
3679#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
3680#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
3681#define CAN_F9R1_FB31_Pos (31U)
3682#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
3683#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
3684
3685/******************* Bit definition for CAN_F10R1 register ******************/
3686#define CAN_F10R1_FB0_Pos (0U)
3687#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
3688#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
3689#define CAN_F10R1_FB1_Pos (1U)
3690#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
3691#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
3692#define CAN_F10R1_FB2_Pos (2U)
3693#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
3694#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
3695#define CAN_F10R1_FB3_Pos (3U)
3696#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
3697#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
3698#define CAN_F10R1_FB4_Pos (4U)
3699#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
3700#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
3701#define CAN_F10R1_FB5_Pos (5U)
3702#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
3703#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
3704#define CAN_F10R1_FB6_Pos (6U)
3705#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
3706#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
3707#define CAN_F10R1_FB7_Pos (7U)
3708#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
3709#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
3710#define CAN_F10R1_FB8_Pos (8U)
3711#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
3712#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
3713#define CAN_F10R1_FB9_Pos (9U)
3714#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
3715#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
3716#define CAN_F10R1_FB10_Pos (10U)
3717#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
3718#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
3719#define CAN_F10R1_FB11_Pos (11U)
3720#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
3721#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
3722#define CAN_F10R1_FB12_Pos (12U)
3723#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
3724#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
3725#define CAN_F10R1_FB13_Pos (13U)
3726#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
3727#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
3728#define CAN_F10R1_FB14_Pos (14U)
3729#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
3730#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
3731#define CAN_F10R1_FB15_Pos (15U)
3732#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
3733#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
3734#define CAN_F10R1_FB16_Pos (16U)
3735#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
3736#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
3737#define CAN_F10R1_FB17_Pos (17U)
3738#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
3739#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
3740#define CAN_F10R1_FB18_Pos (18U)
3741#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
3742#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
3743#define CAN_F10R1_FB19_Pos (19U)
3744#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
3745#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
3746#define CAN_F10R1_FB20_Pos (20U)
3747#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
3748#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
3749#define CAN_F10R1_FB21_Pos (21U)
3750#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
3751#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
3752#define CAN_F10R1_FB22_Pos (22U)
3753#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
3754#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
3755#define CAN_F10R1_FB23_Pos (23U)
3756#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
3757#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
3758#define CAN_F10R1_FB24_Pos (24U)
3759#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
3760#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
3761#define CAN_F10R1_FB25_Pos (25U)
3762#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
3763#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
3764#define CAN_F10R1_FB26_Pos (26U)
3765#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
3766#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
3767#define CAN_F10R1_FB27_Pos (27U)
3768#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
3769#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
3770#define CAN_F10R1_FB28_Pos (28U)
3771#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
3772#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
3773#define CAN_F10R1_FB29_Pos (29U)
3774#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
3775#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
3776#define CAN_F10R1_FB30_Pos (30U)
3777#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
3778#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
3779#define CAN_F10R1_FB31_Pos (31U)
3780#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
3781#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
3782
3783/******************* Bit definition for CAN_F11R1 register ******************/
3784#define CAN_F11R1_FB0_Pos (0U)
3785#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
3786#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
3787#define CAN_F11R1_FB1_Pos (1U)
3788#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
3789#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
3790#define CAN_F11R1_FB2_Pos (2U)
3791#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
3792#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
3793#define CAN_F11R1_FB3_Pos (3U)
3794#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
3795#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
3796#define CAN_F11R1_FB4_Pos (4U)
3797#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
3798#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
3799#define CAN_F11R1_FB5_Pos (5U)
3800#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
3801#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
3802#define CAN_F11R1_FB6_Pos (6U)
3803#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
3804#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
3805#define CAN_F11R1_FB7_Pos (7U)
3806#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
3807#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
3808#define CAN_F11R1_FB8_Pos (8U)
3809#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
3810#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
3811#define CAN_F11R1_FB9_Pos (9U)
3812#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
3813#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
3814#define CAN_F11R1_FB10_Pos (10U)
3815#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
3816#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
3817#define CAN_F11R1_FB11_Pos (11U)
3818#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
3819#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
3820#define CAN_F11R1_FB12_Pos (12U)
3821#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
3822#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
3823#define CAN_F11R1_FB13_Pos (13U)
3824#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
3825#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
3826#define CAN_F11R1_FB14_Pos (14U)
3827#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
3828#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
3829#define CAN_F11R1_FB15_Pos (15U)
3830#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
3831#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
3832#define CAN_F11R1_FB16_Pos (16U)
3833#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
3834#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
3835#define CAN_F11R1_FB17_Pos (17U)
3836#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
3837#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
3838#define CAN_F11R1_FB18_Pos (18U)
3839#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
3840#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
3841#define CAN_F11R1_FB19_Pos (19U)
3842#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
3843#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
3844#define CAN_F11R1_FB20_Pos (20U)
3845#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
3846#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
3847#define CAN_F11R1_FB21_Pos (21U)
3848#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
3849#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
3850#define CAN_F11R1_FB22_Pos (22U)
3851#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
3852#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
3853#define CAN_F11R1_FB23_Pos (23U)
3854#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
3855#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
3856#define CAN_F11R1_FB24_Pos (24U)
3857#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
3858#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
3859#define CAN_F11R1_FB25_Pos (25U)
3860#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
3861#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
3862#define CAN_F11R1_FB26_Pos (26U)
3863#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
3864#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
3865#define CAN_F11R1_FB27_Pos (27U)
3866#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
3867#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
3868#define CAN_F11R1_FB28_Pos (28U)
3869#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
3870#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
3871#define CAN_F11R1_FB29_Pos (29U)
3872#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
3873#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
3874#define CAN_F11R1_FB30_Pos (30U)
3875#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
3876#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
3877#define CAN_F11R1_FB31_Pos (31U)
3878#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
3879#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
3880
3881/******************* Bit definition for CAN_F12R1 register ******************/
3882#define CAN_F12R1_FB0_Pos (0U)
3883#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
3884#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
3885#define CAN_F12R1_FB1_Pos (1U)
3886#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
3887#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
3888#define CAN_F12R1_FB2_Pos (2U)
3889#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
3890#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
3891#define CAN_F12R1_FB3_Pos (3U)
3892#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
3893#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
3894#define CAN_F12R1_FB4_Pos (4U)
3895#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
3896#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
3897#define CAN_F12R1_FB5_Pos (5U)
3898#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
3899#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
3900#define CAN_F12R1_FB6_Pos (6U)
3901#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
3902#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
3903#define CAN_F12R1_FB7_Pos (7U)
3904#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
3905#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
3906#define CAN_F12R1_FB8_Pos (8U)
3907#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
3908#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
3909#define CAN_F12R1_FB9_Pos (9U)
3910#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
3911#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
3912#define CAN_F12R1_FB10_Pos (10U)
3913#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
3914#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
3915#define CAN_F12R1_FB11_Pos (11U)
3916#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
3917#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
3918#define CAN_F12R1_FB12_Pos (12U)
3919#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
3920#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
3921#define CAN_F12R1_FB13_Pos (13U)
3922#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
3923#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
3924#define CAN_F12R1_FB14_Pos (14U)
3925#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
3926#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
3927#define CAN_F12R1_FB15_Pos (15U)
3928#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
3929#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
3930#define CAN_F12R1_FB16_Pos (16U)
3931#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
3932#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
3933#define CAN_F12R1_FB17_Pos (17U)
3934#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
3935#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
3936#define CAN_F12R1_FB18_Pos (18U)
3937#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
3938#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
3939#define CAN_F12R1_FB19_Pos (19U)
3940#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
3941#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
3942#define CAN_F12R1_FB20_Pos (20U)
3943#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
3944#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
3945#define CAN_F12R1_FB21_Pos (21U)
3946#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
3947#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
3948#define CAN_F12R1_FB22_Pos (22U)
3949#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
3950#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
3951#define CAN_F12R1_FB23_Pos (23U)
3952#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
3953#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
3954#define CAN_F12R1_FB24_Pos (24U)
3955#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
3956#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
3957#define CAN_F12R1_FB25_Pos (25U)
3958#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
3959#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
3960#define CAN_F12R1_FB26_Pos (26U)
3961#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
3962#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
3963#define CAN_F12R1_FB27_Pos (27U)
3964#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
3965#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
3966#define CAN_F12R1_FB28_Pos (28U)
3967#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
3968#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
3969#define CAN_F12R1_FB29_Pos (29U)
3970#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
3971#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
3972#define CAN_F12R1_FB30_Pos (30U)
3973#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
3974#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
3975#define CAN_F12R1_FB31_Pos (31U)
3976#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
3977#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
3978
3979/******************* Bit definition for CAN_F13R1 register ******************/
3980#define CAN_F13R1_FB0_Pos (0U)
3981#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
3982#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
3983#define CAN_F13R1_FB1_Pos (1U)
3984#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
3985#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
3986#define CAN_F13R1_FB2_Pos (2U)
3987#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
3988#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
3989#define CAN_F13R1_FB3_Pos (3U)
3990#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
3991#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
3992#define CAN_F13R1_FB4_Pos (4U)
3993#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
3994#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
3995#define CAN_F13R1_FB5_Pos (5U)
3996#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
3997#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
3998#define CAN_F13R1_FB6_Pos (6U)
3999#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
4000#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
4001#define CAN_F13R1_FB7_Pos (7U)
4002#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
4003#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
4004#define CAN_F13R1_FB8_Pos (8U)
4005#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
4006#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
4007#define CAN_F13R1_FB9_Pos (9U)
4008#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
4009#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
4010#define CAN_F13R1_FB10_Pos (10U)
4011#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
4012#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
4013#define CAN_F13R1_FB11_Pos (11U)
4014#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
4015#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
4016#define CAN_F13R1_FB12_Pos (12U)
4017#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
4018#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
4019#define CAN_F13R1_FB13_Pos (13U)
4020#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
4021#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
4022#define CAN_F13R1_FB14_Pos (14U)
4023#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
4024#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
4025#define CAN_F13R1_FB15_Pos (15U)
4026#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
4027#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
4028#define CAN_F13R1_FB16_Pos (16U)
4029#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
4030#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
4031#define CAN_F13R1_FB17_Pos (17U)
4032#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
4033#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
4034#define CAN_F13R1_FB18_Pos (18U)
4035#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
4036#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
4037#define CAN_F13R1_FB19_Pos (19U)
4038#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
4039#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
4040#define CAN_F13R1_FB20_Pos (20U)
4041#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
4042#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
4043#define CAN_F13R1_FB21_Pos (21U)
4044#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
4045#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
4046#define CAN_F13R1_FB22_Pos (22U)
4047#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
4048#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
4049#define CAN_F13R1_FB23_Pos (23U)
4050#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
4051#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
4052#define CAN_F13R1_FB24_Pos (24U)
4053#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
4054#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
4055#define CAN_F13R1_FB25_Pos (25U)
4056#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
4057#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
4058#define CAN_F13R1_FB26_Pos (26U)
4059#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
4060#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
4061#define CAN_F13R1_FB27_Pos (27U)
4062#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
4063#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
4064#define CAN_F13R1_FB28_Pos (28U)
4065#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
4066#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
4067#define CAN_F13R1_FB29_Pos (29U)
4068#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
4069#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
4070#define CAN_F13R1_FB30_Pos (30U)
4071#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
4072#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
4073#define CAN_F13R1_FB31_Pos (31U)
4074#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
4075#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
4076
4077/******************* Bit definition for CAN_F0R2 register *******************/
4078#define CAN_F0R2_FB0_Pos (0U)
4079#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
4080#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
4081#define CAN_F0R2_FB1_Pos (1U)
4082#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
4083#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
4084#define CAN_F0R2_FB2_Pos (2U)
4085#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
4086#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
4087#define CAN_F0R2_FB3_Pos (3U)
4088#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
4089#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
4090#define CAN_F0R2_FB4_Pos (4U)
4091#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
4092#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
4093#define CAN_F0R2_FB5_Pos (5U)
4094#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
4095#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
4096#define CAN_F0R2_FB6_Pos (6U)
4097#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
4098#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
4099#define CAN_F0R2_FB7_Pos (7U)
4100#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
4101#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
4102#define CAN_F0R2_FB8_Pos (8U)
4103#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
4104#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
4105#define CAN_F0R2_FB9_Pos (9U)
4106#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
4107#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
4108#define CAN_F0R2_FB10_Pos (10U)
4109#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
4110#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
4111#define CAN_F0R2_FB11_Pos (11U)
4112#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
4113#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
4114#define CAN_F0R2_FB12_Pos (12U)
4115#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
4116#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
4117#define CAN_F0R2_FB13_Pos (13U)
4118#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
4119#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
4120#define CAN_F0R2_FB14_Pos (14U)
4121#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
4122#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
4123#define CAN_F0R2_FB15_Pos (15U)
4124#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
4125#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
4126#define CAN_F0R2_FB16_Pos (16U)
4127#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
4128#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
4129#define CAN_F0R2_FB17_Pos (17U)
4130#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
4131#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
4132#define CAN_F0R2_FB18_Pos (18U)
4133#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
4134#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
4135#define CAN_F0R2_FB19_Pos (19U)
4136#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
4137#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
4138#define CAN_F0R2_FB20_Pos (20U)
4139#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
4140#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
4141#define CAN_F0R2_FB21_Pos (21U)
4142#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
4143#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
4144#define CAN_F0R2_FB22_Pos (22U)
4145#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
4146#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
4147#define CAN_F0R2_FB23_Pos (23U)
4148#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
4149#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
4150#define CAN_F0R2_FB24_Pos (24U)
4151#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
4152#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
4153#define CAN_F0R2_FB25_Pos (25U)
4154#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
4155#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
4156#define CAN_F0R2_FB26_Pos (26U)
4157#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
4158#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
4159#define CAN_F0R2_FB27_Pos (27U)
4160#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
4161#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
4162#define CAN_F0R2_FB28_Pos (28U)
4163#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
4164#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
4165#define CAN_F0R2_FB29_Pos (29U)
4166#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
4167#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
4168#define CAN_F0R2_FB30_Pos (30U)
4169#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
4170#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
4171#define CAN_F0R2_FB31_Pos (31U)
4172#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
4173#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
4174
4175/******************* Bit definition for CAN_F1R2 register *******************/
4176#define CAN_F1R2_FB0_Pos (0U)
4177#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
4178#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
4179#define CAN_F1R2_FB1_Pos (1U)
4180#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
4181#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
4182#define CAN_F1R2_FB2_Pos (2U)
4183#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
4184#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
4185#define CAN_F1R2_FB3_Pos (3U)
4186#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
4187#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
4188#define CAN_F1R2_FB4_Pos (4U)
4189#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
4190#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
4191#define CAN_F1R2_FB5_Pos (5U)
4192#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
4193#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
4194#define CAN_F1R2_FB6_Pos (6U)
4195#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
4196#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
4197#define CAN_F1R2_FB7_Pos (7U)
4198#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
4199#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
4200#define CAN_F1R2_FB8_Pos (8U)
4201#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
4202#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
4203#define CAN_F1R2_FB9_Pos (9U)
4204#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
4205#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
4206#define CAN_F1R2_FB10_Pos (10U)
4207#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
4208#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
4209#define CAN_F1R2_FB11_Pos (11U)
4210#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
4211#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
4212#define CAN_F1R2_FB12_Pos (12U)
4213#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
4214#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
4215#define CAN_F1R2_FB13_Pos (13U)
4216#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
4217#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
4218#define CAN_F1R2_FB14_Pos (14U)
4219#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
4220#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
4221#define CAN_F1R2_FB15_Pos (15U)
4222#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
4223#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
4224#define CAN_F1R2_FB16_Pos (16U)
4225#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
4226#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
4227#define CAN_F1R2_FB17_Pos (17U)
4228#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
4229#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
4230#define CAN_F1R2_FB18_Pos (18U)
4231#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
4232#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
4233#define CAN_F1R2_FB19_Pos (19U)
4234#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
4235#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
4236#define CAN_F1R2_FB20_Pos (20U)
4237#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
4238#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
4239#define CAN_F1R2_FB21_Pos (21U)
4240#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
4241#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
4242#define CAN_F1R2_FB22_Pos (22U)
4243#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
4244#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
4245#define CAN_F1R2_FB23_Pos (23U)
4246#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
4247#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
4248#define CAN_F1R2_FB24_Pos (24U)
4249#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
4250#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
4251#define CAN_F1R2_FB25_Pos (25U)
4252#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
4253#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
4254#define CAN_F1R2_FB26_Pos (26U)
4255#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
4256#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
4257#define CAN_F1R2_FB27_Pos (27U)
4258#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
4259#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
4260#define CAN_F1R2_FB28_Pos (28U)
4261#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
4262#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
4263#define CAN_F1R2_FB29_Pos (29U)
4264#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
4265#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
4266#define CAN_F1R2_FB30_Pos (30U)
4267#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
4268#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
4269#define CAN_F1R2_FB31_Pos (31U)
4270#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
4271#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
4272
4273/******************* Bit definition for CAN_F2R2 register *******************/
4274#define CAN_F2R2_FB0_Pos (0U)
4275#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
4276#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
4277#define CAN_F2R2_FB1_Pos (1U)
4278#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
4279#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
4280#define CAN_F2R2_FB2_Pos (2U)
4281#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
4282#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
4283#define CAN_F2R2_FB3_Pos (3U)
4284#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
4285#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
4286#define CAN_F2R2_FB4_Pos (4U)
4287#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
4288#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
4289#define CAN_F2R2_FB5_Pos (5U)
4290#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
4291#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
4292#define CAN_F2R2_FB6_Pos (6U)
4293#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
4294#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
4295#define CAN_F2R2_FB7_Pos (7U)
4296#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
4297#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
4298#define CAN_F2R2_FB8_Pos (8U)
4299#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
4300#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
4301#define CAN_F2R2_FB9_Pos (9U)
4302#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
4303#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
4304#define CAN_F2R2_FB10_Pos (10U)
4305#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
4306#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
4307#define CAN_F2R2_FB11_Pos (11U)
4308#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
4309#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
4310#define CAN_F2R2_FB12_Pos (12U)
4311#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
4312#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
4313#define CAN_F2R2_FB13_Pos (13U)
4314#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
4315#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
4316#define CAN_F2R2_FB14_Pos (14U)
4317#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
4318#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
4319#define CAN_F2R2_FB15_Pos (15U)
4320#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
4321#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
4322#define CAN_F2R2_FB16_Pos (16U)
4323#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
4324#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
4325#define CAN_F2R2_FB17_Pos (17U)
4326#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
4327#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
4328#define CAN_F2R2_FB18_Pos (18U)
4329#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
4330#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
4331#define CAN_F2R2_FB19_Pos (19U)
4332#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
4333#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
4334#define CAN_F2R2_FB20_Pos (20U)
4335#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
4336#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
4337#define CAN_F2R2_FB21_Pos (21U)
4338#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
4339#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
4340#define CAN_F2R2_FB22_Pos (22U)
4341#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
4342#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
4343#define CAN_F2R2_FB23_Pos (23U)
4344#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
4345#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
4346#define CAN_F2R2_FB24_Pos (24U)
4347#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
4348#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
4349#define CAN_F2R2_FB25_Pos (25U)
4350#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
4351#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
4352#define CAN_F2R2_FB26_Pos (26U)
4353#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
4354#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
4355#define CAN_F2R2_FB27_Pos (27U)
4356#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
4357#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
4358#define CAN_F2R2_FB28_Pos (28U)
4359#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
4360#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
4361#define CAN_F2R2_FB29_Pos (29U)
4362#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
4363#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
4364#define CAN_F2R2_FB30_Pos (30U)
4365#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
4366#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
4367#define CAN_F2R2_FB31_Pos (31U)
4368#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
4369#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
4370
4371/******************* Bit definition for CAN_F3R2 register *******************/
4372#define CAN_F3R2_FB0_Pos (0U)
4373#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
4374#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
4375#define CAN_F3R2_FB1_Pos (1U)
4376#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
4377#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
4378#define CAN_F3R2_FB2_Pos (2U)
4379#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
4380#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
4381#define CAN_F3R2_FB3_Pos (3U)
4382#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
4383#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
4384#define CAN_F3R2_FB4_Pos (4U)
4385#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
4386#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
4387#define CAN_F3R2_FB5_Pos (5U)
4388#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
4389#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
4390#define CAN_F3R2_FB6_Pos (6U)
4391#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
4392#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
4393#define CAN_F3R2_FB7_Pos (7U)
4394#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
4395#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
4396#define CAN_F3R2_FB8_Pos (8U)
4397#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
4398#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
4399#define CAN_F3R2_FB9_Pos (9U)
4400#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
4401#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
4402#define CAN_F3R2_FB10_Pos (10U)
4403#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
4404#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
4405#define CAN_F3R2_FB11_Pos (11U)
4406#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
4407#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
4408#define CAN_F3R2_FB12_Pos (12U)
4409#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
4410#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
4411#define CAN_F3R2_FB13_Pos (13U)
4412#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
4413#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
4414#define CAN_F3R2_FB14_Pos (14U)
4415#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
4416#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
4417#define CAN_F3R2_FB15_Pos (15U)
4418#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
4419#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
4420#define CAN_F3R2_FB16_Pos (16U)
4421#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
4422#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
4423#define CAN_F3R2_FB17_Pos (17U)
4424#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
4425#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
4426#define CAN_F3R2_FB18_Pos (18U)
4427#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
4428#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
4429#define CAN_F3R2_FB19_Pos (19U)
4430#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
4431#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
4432#define CAN_F3R2_FB20_Pos (20U)
4433#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
4434#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
4435#define CAN_F3R2_FB21_Pos (21U)
4436#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
4437#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
4438#define CAN_F3R2_FB22_Pos (22U)
4439#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
4440#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
4441#define CAN_F3R2_FB23_Pos (23U)
4442#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
4443#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
4444#define CAN_F3R2_FB24_Pos (24U)
4445#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
4446#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
4447#define CAN_F3R2_FB25_Pos (25U)
4448#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
4449#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
4450#define CAN_F3R2_FB26_Pos (26U)
4451#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
4452#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
4453#define CAN_F3R2_FB27_Pos (27U)
4454#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
4455#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
4456#define CAN_F3R2_FB28_Pos (28U)
4457#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
4458#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
4459#define CAN_F3R2_FB29_Pos (29U)
4460#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
4461#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
4462#define CAN_F3R2_FB30_Pos (30U)
4463#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
4464#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
4465#define CAN_F3R2_FB31_Pos (31U)
4466#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
4467#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
4468
4469/******************* Bit definition for CAN_F4R2 register *******************/
4470#define CAN_F4R2_FB0_Pos (0U)
4471#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
4472#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
4473#define CAN_F4R2_FB1_Pos (1U)
4474#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
4475#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
4476#define CAN_F4R2_FB2_Pos (2U)
4477#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
4478#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
4479#define CAN_F4R2_FB3_Pos (3U)
4480#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
4481#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
4482#define CAN_F4R2_FB4_Pos (4U)
4483#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
4484#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
4485#define CAN_F4R2_FB5_Pos (5U)
4486#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
4487#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
4488#define CAN_F4R2_FB6_Pos (6U)
4489#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
4490#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
4491#define CAN_F4R2_FB7_Pos (7U)
4492#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
4493#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
4494#define CAN_F4R2_FB8_Pos (8U)
4495#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
4496#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
4497#define CAN_F4R2_FB9_Pos (9U)
4498#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
4499#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
4500#define CAN_F4R2_FB10_Pos (10U)
4501#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
4502#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
4503#define CAN_F4R2_FB11_Pos (11U)
4504#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
4505#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
4506#define CAN_F4R2_FB12_Pos (12U)
4507#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
4508#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
4509#define CAN_F4R2_FB13_Pos (13U)
4510#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
4511#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
4512#define CAN_F4R2_FB14_Pos (14U)
4513#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
4514#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
4515#define CAN_F4R2_FB15_Pos (15U)
4516#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
4517#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
4518#define CAN_F4R2_FB16_Pos (16U)
4519#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
4520#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
4521#define CAN_F4R2_FB17_Pos (17U)
4522#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
4523#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
4524#define CAN_F4R2_FB18_Pos (18U)
4525#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
4526#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
4527#define CAN_F4R2_FB19_Pos (19U)
4528#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
4529#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
4530#define CAN_F4R2_FB20_Pos (20U)
4531#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
4532#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
4533#define CAN_F4R2_FB21_Pos (21U)
4534#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
4535#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
4536#define CAN_F4R2_FB22_Pos (22U)
4537#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
4538#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
4539#define CAN_F4R2_FB23_Pos (23U)
4540#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
4541#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
4542#define CAN_F4R2_FB24_Pos (24U)
4543#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
4544#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
4545#define CAN_F4R2_FB25_Pos (25U)
4546#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
4547#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
4548#define CAN_F4R2_FB26_Pos (26U)
4549#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
4550#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
4551#define CAN_F4R2_FB27_Pos (27U)
4552#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
4553#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
4554#define CAN_F4R2_FB28_Pos (28U)
4555#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
4556#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
4557#define CAN_F4R2_FB29_Pos (29U)
4558#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
4559#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
4560#define CAN_F4R2_FB30_Pos (30U)
4561#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
4562#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
4563#define CAN_F4R2_FB31_Pos (31U)
4564#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
4565#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
4566
4567/******************* Bit definition for CAN_F5R2 register *******************/
4568#define CAN_F5R2_FB0_Pos (0U)
4569#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
4570#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
4571#define CAN_F5R2_FB1_Pos (1U)
4572#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
4573#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
4574#define CAN_F5R2_FB2_Pos (2U)
4575#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
4576#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
4577#define CAN_F5R2_FB3_Pos (3U)
4578#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
4579#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
4580#define CAN_F5R2_FB4_Pos (4U)
4581#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
4582#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
4583#define CAN_F5R2_FB5_Pos (5U)
4584#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
4585#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
4586#define CAN_F5R2_FB6_Pos (6U)
4587#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
4588#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
4589#define CAN_F5R2_FB7_Pos (7U)
4590#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
4591#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
4592#define CAN_F5R2_FB8_Pos (8U)
4593#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
4594#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
4595#define CAN_F5R2_FB9_Pos (9U)
4596#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
4597#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
4598#define CAN_F5R2_FB10_Pos (10U)
4599#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
4600#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
4601#define CAN_F5R2_FB11_Pos (11U)
4602#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
4603#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
4604#define CAN_F5R2_FB12_Pos (12U)
4605#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
4606#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
4607#define CAN_F5R2_FB13_Pos (13U)
4608#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
4609#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
4610#define CAN_F5R2_FB14_Pos (14U)
4611#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
4612#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
4613#define CAN_F5R2_FB15_Pos (15U)
4614#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
4615#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
4616#define CAN_F5R2_FB16_Pos (16U)
4617#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
4618#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
4619#define CAN_F5R2_FB17_Pos (17U)
4620#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
4621#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
4622#define CAN_F5R2_FB18_Pos (18U)
4623#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
4624#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
4625#define CAN_F5R2_FB19_Pos (19U)
4626#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
4627#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
4628#define CAN_F5R2_FB20_Pos (20U)
4629#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
4630#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
4631#define CAN_F5R2_FB21_Pos (21U)
4632#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
4633#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
4634#define CAN_F5R2_FB22_Pos (22U)
4635#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
4636#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
4637#define CAN_F5R2_FB23_Pos (23U)
4638#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
4639#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
4640#define CAN_F5R2_FB24_Pos (24U)
4641#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
4642#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
4643#define CAN_F5R2_FB25_Pos (25U)
4644#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
4645#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
4646#define CAN_F5R2_FB26_Pos (26U)
4647#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
4648#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
4649#define CAN_F5R2_FB27_Pos (27U)
4650#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
4651#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
4652#define CAN_F5R2_FB28_Pos (28U)
4653#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
4654#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
4655#define CAN_F5R2_FB29_Pos (29U)
4656#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
4657#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
4658#define CAN_F5R2_FB30_Pos (30U)
4659#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
4660#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
4661#define CAN_F5R2_FB31_Pos (31U)
4662#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
4663#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
4664
4665/******************* Bit definition for CAN_F6R2 register *******************/
4666#define CAN_F6R2_FB0_Pos (0U)
4667#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
4668#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
4669#define CAN_F6R2_FB1_Pos (1U)
4670#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
4671#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
4672#define CAN_F6R2_FB2_Pos (2U)
4673#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
4674#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
4675#define CAN_F6R2_FB3_Pos (3U)
4676#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
4677#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
4678#define CAN_F6R2_FB4_Pos (4U)
4679#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
4680#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
4681#define CAN_F6R2_FB5_Pos (5U)
4682#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
4683#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
4684#define CAN_F6R2_FB6_Pos (6U)
4685#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
4686#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
4687#define CAN_F6R2_FB7_Pos (7U)
4688#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
4689#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
4690#define CAN_F6R2_FB8_Pos (8U)
4691#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
4692#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
4693#define CAN_F6R2_FB9_Pos (9U)
4694#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
4695#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
4696#define CAN_F6R2_FB10_Pos (10U)
4697#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
4698#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
4699#define CAN_F6R2_FB11_Pos (11U)
4700#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
4701#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
4702#define CAN_F6R2_FB12_Pos (12U)
4703#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
4704#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
4705#define CAN_F6R2_FB13_Pos (13U)
4706#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
4707#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
4708#define CAN_F6R2_FB14_Pos (14U)
4709#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
4710#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
4711#define CAN_F6R2_FB15_Pos (15U)
4712#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
4713#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
4714#define CAN_F6R2_FB16_Pos (16U)
4715#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
4716#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
4717#define CAN_F6R2_FB17_Pos (17U)
4718#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
4719#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
4720#define CAN_F6R2_FB18_Pos (18U)
4721#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
4722#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
4723#define CAN_F6R2_FB19_Pos (19U)
4724#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
4725#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
4726#define CAN_F6R2_FB20_Pos (20U)
4727#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
4728#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
4729#define CAN_F6R2_FB21_Pos (21U)
4730#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
4731#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
4732#define CAN_F6R2_FB22_Pos (22U)
4733#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
4734#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
4735#define CAN_F6R2_FB23_Pos (23U)
4736#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
4737#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
4738#define CAN_F6R2_FB24_Pos (24U)
4739#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
4740#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
4741#define CAN_F6R2_FB25_Pos (25U)
4742#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
4743#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
4744#define CAN_F6R2_FB26_Pos (26U)
4745#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
4746#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
4747#define CAN_F6R2_FB27_Pos (27U)
4748#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
4749#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
4750#define CAN_F6R2_FB28_Pos (28U)
4751#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
4752#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
4753#define CAN_F6R2_FB29_Pos (29U)
4754#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
4755#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
4756#define CAN_F6R2_FB30_Pos (30U)
4757#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
4758#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
4759#define CAN_F6R2_FB31_Pos (31U)
4760#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
4761#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
4762
4763/******************* Bit definition for CAN_F7R2 register *******************/
4764#define CAN_F7R2_FB0_Pos (0U)
4765#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
4766#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
4767#define CAN_F7R2_FB1_Pos (1U)
4768#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
4769#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
4770#define CAN_F7R2_FB2_Pos (2U)
4771#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
4772#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
4773#define CAN_F7R2_FB3_Pos (3U)
4774#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
4775#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
4776#define CAN_F7R2_FB4_Pos (4U)
4777#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
4778#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
4779#define CAN_F7R2_FB5_Pos (5U)
4780#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
4781#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
4782#define CAN_F7R2_FB6_Pos (6U)
4783#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
4784#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
4785#define CAN_F7R2_FB7_Pos (7U)
4786#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
4787#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
4788#define CAN_F7R2_FB8_Pos (8U)
4789#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
4790#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
4791#define CAN_F7R2_FB9_Pos (9U)
4792#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
4793#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
4794#define CAN_F7R2_FB10_Pos (10U)
4795#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
4796#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
4797#define CAN_F7R2_FB11_Pos (11U)
4798#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
4799#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
4800#define CAN_F7R2_FB12_Pos (12U)
4801#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
4802#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
4803#define CAN_F7R2_FB13_Pos (13U)
4804#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
4805#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
4806#define CAN_F7R2_FB14_Pos (14U)
4807#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
4808#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
4809#define CAN_F7R2_FB15_Pos (15U)
4810#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
4811#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
4812#define CAN_F7R2_FB16_Pos (16U)
4813#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
4814#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
4815#define CAN_F7R2_FB17_Pos (17U)
4816#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
4817#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
4818#define CAN_F7R2_FB18_Pos (18U)
4819#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
4820#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
4821#define CAN_F7R2_FB19_Pos (19U)
4822#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
4823#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
4824#define CAN_F7R2_FB20_Pos (20U)
4825#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
4826#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
4827#define CAN_F7R2_FB21_Pos (21U)
4828#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
4829#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
4830#define CAN_F7R2_FB22_Pos (22U)
4831#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
4832#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
4833#define CAN_F7R2_FB23_Pos (23U)
4834#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
4835#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
4836#define CAN_F7R2_FB24_Pos (24U)
4837#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
4838#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
4839#define CAN_F7R2_FB25_Pos (25U)
4840#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
4841#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
4842#define CAN_F7R2_FB26_Pos (26U)
4843#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
4844#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
4845#define CAN_F7R2_FB27_Pos (27U)
4846#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
4847#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
4848#define CAN_F7R2_FB28_Pos (28U)
4849#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
4850#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
4851#define CAN_F7R2_FB29_Pos (29U)
4852#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
4853#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
4854#define CAN_F7R2_FB30_Pos (30U)
4855#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
4856#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
4857#define CAN_F7R2_FB31_Pos (31U)
4858#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
4859#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
4860
4861/******************* Bit definition for CAN_F8R2 register *******************/
4862#define CAN_F8R2_FB0_Pos (0U)
4863#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
4864#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
4865#define CAN_F8R2_FB1_Pos (1U)
4866#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
4867#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
4868#define CAN_F8R2_FB2_Pos (2U)
4869#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
4870#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
4871#define CAN_F8R2_FB3_Pos (3U)
4872#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
4873#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
4874#define CAN_F8R2_FB4_Pos (4U)
4875#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
4876#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
4877#define CAN_F8R2_FB5_Pos (5U)
4878#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
4879#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
4880#define CAN_F8R2_FB6_Pos (6U)
4881#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
4882#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
4883#define CAN_F8R2_FB7_Pos (7U)
4884#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
4885#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
4886#define CAN_F8R2_FB8_Pos (8U)
4887#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
4888#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
4889#define CAN_F8R2_FB9_Pos (9U)
4890#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
4891#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
4892#define CAN_F8R2_FB10_Pos (10U)
4893#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
4894#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
4895#define CAN_F8R2_FB11_Pos (11U)
4896#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
4897#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
4898#define CAN_F8R2_FB12_Pos (12U)
4899#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
4900#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
4901#define CAN_F8R2_FB13_Pos (13U)
4902#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
4903#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
4904#define CAN_F8R2_FB14_Pos (14U)
4905#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
4906#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
4907#define CAN_F8R2_FB15_Pos (15U)
4908#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
4909#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
4910#define CAN_F8R2_FB16_Pos (16U)
4911#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
4912#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
4913#define CAN_F8R2_FB17_Pos (17U)
4914#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
4915#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
4916#define CAN_F8R2_FB18_Pos (18U)
4917#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
4918#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
4919#define CAN_F8R2_FB19_Pos (19U)
4920#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
4921#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
4922#define CAN_F8R2_FB20_Pos (20U)
4923#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
4924#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
4925#define CAN_F8R2_FB21_Pos (21U)
4926#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
4927#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
4928#define CAN_F8R2_FB22_Pos (22U)
4929#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
4930#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
4931#define CAN_F8R2_FB23_Pos (23U)
4932#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
4933#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
4934#define CAN_F8R2_FB24_Pos (24U)
4935#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
4936#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
4937#define CAN_F8R2_FB25_Pos (25U)
4938#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
4939#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
4940#define CAN_F8R2_FB26_Pos (26U)
4941#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
4942#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
4943#define CAN_F8R2_FB27_Pos (27U)
4944#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
4945#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
4946#define CAN_F8R2_FB28_Pos (28U)
4947#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
4948#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
4949#define CAN_F8R2_FB29_Pos (29U)
4950#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
4951#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
4952#define CAN_F8R2_FB30_Pos (30U)
4953#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
4954#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
4955#define CAN_F8R2_FB31_Pos (31U)
4956#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
4957#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
4958
4959/******************* Bit definition for CAN_F9R2 register *******************/
4960#define CAN_F9R2_FB0_Pos (0U)
4961#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
4962#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
4963#define CAN_F9R2_FB1_Pos (1U)
4964#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
4965#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
4966#define CAN_F9R2_FB2_Pos (2U)
4967#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
4968#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
4969#define CAN_F9R2_FB3_Pos (3U)
4970#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
4971#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
4972#define CAN_F9R2_FB4_Pos (4U)
4973#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
4974#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
4975#define CAN_F9R2_FB5_Pos (5U)
4976#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
4977#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
4978#define CAN_F9R2_FB6_Pos (6U)
4979#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
4980#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
4981#define CAN_F9R2_FB7_Pos (7U)
4982#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
4983#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
4984#define CAN_F9R2_FB8_Pos (8U)
4985#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
4986#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
4987#define CAN_F9R2_FB9_Pos (9U)
4988#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
4989#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
4990#define CAN_F9R2_FB10_Pos (10U)
4991#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
4992#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
4993#define CAN_F9R2_FB11_Pos (11U)
4994#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
4995#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
4996#define CAN_F9R2_FB12_Pos (12U)
4997#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
4998#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
4999#define CAN_F9R2_FB13_Pos (13U)
5000#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
5001#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
5002#define CAN_F9R2_FB14_Pos (14U)
5003#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
5004#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
5005#define CAN_F9R2_FB15_Pos (15U)
5006#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
5007#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
5008#define CAN_F9R2_FB16_Pos (16U)
5009#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
5010#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
5011#define CAN_F9R2_FB17_Pos (17U)
5012#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
5013#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
5014#define CAN_F9R2_FB18_Pos (18U)
5015#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
5016#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
5017#define CAN_F9R2_FB19_Pos (19U)
5018#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
5019#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
5020#define CAN_F9R2_FB20_Pos (20U)
5021#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
5022#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
5023#define CAN_F9R2_FB21_Pos (21U)
5024#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
5025#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
5026#define CAN_F9R2_FB22_Pos (22U)
5027#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
5028#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
5029#define CAN_F9R2_FB23_Pos (23U)
5030#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
5031#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
5032#define CAN_F9R2_FB24_Pos (24U)
5033#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
5034#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
5035#define CAN_F9R2_FB25_Pos (25U)
5036#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
5037#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
5038#define CAN_F9R2_FB26_Pos (26U)
5039#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
5040#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
5041#define CAN_F9R2_FB27_Pos (27U)
5042#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
5043#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
5044#define CAN_F9R2_FB28_Pos (28U)
5045#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
5046#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
5047#define CAN_F9R2_FB29_Pos (29U)
5048#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
5049#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
5050#define CAN_F9R2_FB30_Pos (30U)
5051#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
5052#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
5053#define CAN_F9R2_FB31_Pos (31U)
5054#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
5055#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
5056
5057/******************* Bit definition for CAN_F10R2 register ******************/
5058#define CAN_F10R2_FB0_Pos (0U)
5059#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
5060#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
5061#define CAN_F10R2_FB1_Pos (1U)
5062#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
5063#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
5064#define CAN_F10R2_FB2_Pos (2U)
5065#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
5066#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
5067#define CAN_F10R2_FB3_Pos (3U)
5068#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
5069#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
5070#define CAN_F10R2_FB4_Pos (4U)
5071#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
5072#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
5073#define CAN_F10R2_FB5_Pos (5U)
5074#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
5075#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
5076#define CAN_F10R2_FB6_Pos (6U)
5077#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
5078#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
5079#define CAN_F10R2_FB7_Pos (7U)
5080#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
5081#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
5082#define CAN_F10R2_FB8_Pos (8U)
5083#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
5084#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
5085#define CAN_F10R2_FB9_Pos (9U)
5086#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
5087#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
5088#define CAN_F10R2_FB10_Pos (10U)
5089#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
5090#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
5091#define CAN_F10R2_FB11_Pos (11U)
5092#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
5093#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
5094#define CAN_F10R2_FB12_Pos (12U)
5095#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
5096#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
5097#define CAN_F10R2_FB13_Pos (13U)
5098#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
5099#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
5100#define CAN_F10R2_FB14_Pos (14U)
5101#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
5102#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
5103#define CAN_F10R2_FB15_Pos (15U)
5104#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
5105#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
5106#define CAN_F10R2_FB16_Pos (16U)
5107#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
5108#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
5109#define CAN_F10R2_FB17_Pos (17U)
5110#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
5111#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
5112#define CAN_F10R2_FB18_Pos (18U)
5113#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
5114#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
5115#define CAN_F10R2_FB19_Pos (19U)
5116#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
5117#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
5118#define CAN_F10R2_FB20_Pos (20U)
5119#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
5120#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
5121#define CAN_F10R2_FB21_Pos (21U)
5122#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
5123#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
5124#define CAN_F10R2_FB22_Pos (22U)
5125#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
5126#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
5127#define CAN_F10R2_FB23_Pos (23U)
5128#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
5129#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
5130#define CAN_F10R2_FB24_Pos (24U)
5131#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
5132#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
5133#define CAN_F10R2_FB25_Pos (25U)
5134#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
5135#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
5136#define CAN_F10R2_FB26_Pos (26U)
5137#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
5138#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
5139#define CAN_F10R2_FB27_Pos (27U)
5140#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
5141#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
5142#define CAN_F10R2_FB28_Pos (28U)
5143#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
5144#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
5145#define CAN_F10R2_FB29_Pos (29U)
5146#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
5147#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
5148#define CAN_F10R2_FB30_Pos (30U)
5149#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
5150#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
5151#define CAN_F10R2_FB31_Pos (31U)
5152#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
5153#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
5154
5155/******************* Bit definition for CAN_F11R2 register ******************/
5156#define CAN_F11R2_FB0_Pos (0U)
5157#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
5158#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
5159#define CAN_F11R2_FB1_Pos (1U)
5160#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
5161#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
5162#define CAN_F11R2_FB2_Pos (2U)
5163#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
5164#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
5165#define CAN_F11R2_FB3_Pos (3U)
5166#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
5167#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
5168#define CAN_F11R2_FB4_Pos (4U)
5169#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
5170#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
5171#define CAN_F11R2_FB5_Pos (5U)
5172#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
5173#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
5174#define CAN_F11R2_FB6_Pos (6U)
5175#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
5176#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
5177#define CAN_F11R2_FB7_Pos (7U)
5178#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
5179#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
5180#define CAN_F11R2_FB8_Pos (8U)
5181#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
5182#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
5183#define CAN_F11R2_FB9_Pos (9U)
5184#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
5185#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
5186#define CAN_F11R2_FB10_Pos (10U)
5187#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
5188#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
5189#define CAN_F11R2_FB11_Pos (11U)
5190#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
5191#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
5192#define CAN_F11R2_FB12_Pos (12U)
5193#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
5194#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
5195#define CAN_F11R2_FB13_Pos (13U)
5196#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
5197#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
5198#define CAN_F11R2_FB14_Pos (14U)
5199#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
5200#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
5201#define CAN_F11R2_FB15_Pos (15U)
5202#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
5203#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
5204#define CAN_F11R2_FB16_Pos (16U)
5205#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
5206#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
5207#define CAN_F11R2_FB17_Pos (17U)
5208#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
5209#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
5210#define CAN_F11R2_FB18_Pos (18U)
5211#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
5212#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
5213#define CAN_F11R2_FB19_Pos (19U)
5214#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
5215#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
5216#define CAN_F11R2_FB20_Pos (20U)
5217#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
5218#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
5219#define CAN_F11R2_FB21_Pos (21U)
5220#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
5221#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
5222#define CAN_F11R2_FB22_Pos (22U)
5223#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
5224#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
5225#define CAN_F11R2_FB23_Pos (23U)
5226#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
5227#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
5228#define CAN_F11R2_FB24_Pos (24U)
5229#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
5230#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
5231#define CAN_F11R2_FB25_Pos (25U)
5232#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
5233#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
5234#define CAN_F11R2_FB26_Pos (26U)
5235#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
5236#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
5237#define CAN_F11R2_FB27_Pos (27U)
5238#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
5239#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
5240#define CAN_F11R2_FB28_Pos (28U)
5241#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
5242#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
5243#define CAN_F11R2_FB29_Pos (29U)
5244#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
5245#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
5246#define CAN_F11R2_FB30_Pos (30U)
5247#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
5248#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
5249#define CAN_F11R2_FB31_Pos (31U)
5250#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
5251#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
5252
5253/******************* Bit definition for CAN_F12R2 register ******************/
5254#define CAN_F12R2_FB0_Pos (0U)
5255#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
5256#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
5257#define CAN_F12R2_FB1_Pos (1U)
5258#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
5259#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
5260#define CAN_F12R2_FB2_Pos (2U)
5261#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
5262#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
5263#define CAN_F12R2_FB3_Pos (3U)
5264#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
5265#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
5266#define CAN_F12R2_FB4_Pos (4U)
5267#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
5268#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
5269#define CAN_F12R2_FB5_Pos (5U)
5270#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
5271#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
5272#define CAN_F12R2_FB6_Pos (6U)
5273#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
5274#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
5275#define CAN_F12R2_FB7_Pos (7U)
5276#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
5277#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
5278#define CAN_F12R2_FB8_Pos (8U)
5279#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
5280#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
5281#define CAN_F12R2_FB9_Pos (9U)
5282#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
5283#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
5284#define CAN_F12R2_FB10_Pos (10U)
5285#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
5286#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
5287#define CAN_F12R2_FB11_Pos (11U)
5288#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
5289#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
5290#define CAN_F12R2_FB12_Pos (12U)
5291#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
5292#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
5293#define CAN_F12R2_FB13_Pos (13U)
5294#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
5295#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
5296#define CAN_F12R2_FB14_Pos (14U)
5297#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
5298#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
5299#define CAN_F12R2_FB15_Pos (15U)
5300#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
5301#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
5302#define CAN_F12R2_FB16_Pos (16U)
5303#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
5304#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
5305#define CAN_F12R2_FB17_Pos (17U)
5306#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
5307#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
5308#define CAN_F12R2_FB18_Pos (18U)
5309#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
5310#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
5311#define CAN_F12R2_FB19_Pos (19U)
5312#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
5313#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
5314#define CAN_F12R2_FB20_Pos (20U)
5315#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
5316#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
5317#define CAN_F12R2_FB21_Pos (21U)
5318#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
5319#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
5320#define CAN_F12R2_FB22_Pos (22U)
5321#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
5322#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
5323#define CAN_F12R2_FB23_Pos (23U)
5324#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
5325#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
5326#define CAN_F12R2_FB24_Pos (24U)
5327#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
5328#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
5329#define CAN_F12R2_FB25_Pos (25U)
5330#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
5331#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
5332#define CAN_F12R2_FB26_Pos (26U)
5333#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
5334#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
5335#define CAN_F12R2_FB27_Pos (27U)
5336#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
5337#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
5338#define CAN_F12R2_FB28_Pos (28U)
5339#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
5340#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
5341#define CAN_F12R2_FB29_Pos (29U)
5342#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
5343#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
5344#define CAN_F12R2_FB30_Pos (30U)
5345#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
5346#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
5347#define CAN_F12R2_FB31_Pos (31U)
5348#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
5349#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
5350
5351/******************* Bit definition for CAN_F13R2 register ******************/
5352#define CAN_F13R2_FB0_Pos (0U)
5353#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
5354#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
5355#define CAN_F13R2_FB1_Pos (1U)
5356#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
5357#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
5358#define CAN_F13R2_FB2_Pos (2U)
5359#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
5360#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
5361#define CAN_F13R2_FB3_Pos (3U)
5362#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
5363#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
5364#define CAN_F13R2_FB4_Pos (4U)
5365#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
5366#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
5367#define CAN_F13R2_FB5_Pos (5U)
5368#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
5369#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
5370#define CAN_F13R2_FB6_Pos (6U)
5371#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
5372#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
5373#define CAN_F13R2_FB7_Pos (7U)
5374#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
5375#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
5376#define CAN_F13R2_FB8_Pos (8U)
5377#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
5378#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
5379#define CAN_F13R2_FB9_Pos (9U)
5380#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
5381#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
5382#define CAN_F13R2_FB10_Pos (10U)
5383#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
5384#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
5385#define CAN_F13R2_FB11_Pos (11U)
5386#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
5387#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
5388#define CAN_F13R2_FB12_Pos (12U)
5389#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
5390#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
5391#define CAN_F13R2_FB13_Pos (13U)
5392#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
5393#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
5394#define CAN_F13R2_FB14_Pos (14U)
5395#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
5396#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
5397#define CAN_F13R2_FB15_Pos (15U)
5398#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
5399#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
5400#define CAN_F13R2_FB16_Pos (16U)
5401#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
5402#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
5403#define CAN_F13R2_FB17_Pos (17U)
5404#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
5405#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
5406#define CAN_F13R2_FB18_Pos (18U)
5407#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
5408#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
5409#define CAN_F13R2_FB19_Pos (19U)
5410#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
5411#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
5412#define CAN_F13R2_FB20_Pos (20U)
5413#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
5414#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
5415#define CAN_F13R2_FB21_Pos (21U)
5416#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
5417#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
5418#define CAN_F13R2_FB22_Pos (22U)
5419#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
5420#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
5421#define CAN_F13R2_FB23_Pos (23U)
5422#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
5423#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
5424#define CAN_F13R2_FB24_Pos (24U)
5425#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
5426#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
5427#define CAN_F13R2_FB25_Pos (25U)
5428#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
5429#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
5430#define CAN_F13R2_FB26_Pos (26U)
5431#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
5432#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
5433#define CAN_F13R2_FB27_Pos (27U)
5434#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
5435#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
5436#define CAN_F13R2_FB28_Pos (28U)
5437#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
5438#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
5439#define CAN_F13R2_FB29_Pos (29U)
5440#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
5441#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
5442#define CAN_F13R2_FB30_Pos (30U)
5443#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
5444#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
5445#define CAN_F13R2_FB31_Pos (31U)
5446#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
5447#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
5448
5449/******************************************************************************/
5450/* */
5451/* HDMI-CEC (CEC) */
5452/* */
5453/******************************************************************************/
5454
5455/******************* Bit definition for CEC_CR register *********************/
5456#define CEC_CR_CECEN_Pos (0U)
5457#define CEC_CR_CECEN_Msk (0x1U << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
5458#define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
5459#define CEC_CR_TXSOM_Pos (1U)
5460#define CEC_CR_TXSOM_Msk (0x1U << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
5461#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
5462#define CEC_CR_TXEOM_Pos (2U)
5463#define CEC_CR_TXEOM_Msk (0x1U << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
5464#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
5465
5466/******************* Bit definition for CEC_CFGR register *******************/
5467#define CEC_CFGR_SFT_Pos (0U)
5468#define CEC_CFGR_SFT_Msk (0x7U << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
5469#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
5470#define CEC_CFGR_RXTOL_Pos (3U)
5471#define CEC_CFGR_RXTOL_Msk (0x1U << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
5472#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
5473#define CEC_CFGR_BRESTP_Pos (4U)
5474#define CEC_CFGR_BRESTP_Msk (0x1U << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
5475#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
5476#define CEC_CFGR_BREGEN_Pos (5U)
5477#define CEC_CFGR_BREGEN_Msk (0x1U << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
5478#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
5479#define CEC_CFGR_LBPEGEN_Pos (6U)
5480#define CEC_CFGR_LBPEGEN_Msk (0x1U << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
5481#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error generation */
5482#define CEC_CFGR_SFTOPT_Pos (8U)
5483#define CEC_CFGR_SFTOPT_Msk (0x1U << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
5484#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
5485#define CEC_CFGR_BRDNOGEN_Pos (7U)
5486#define CEC_CFGR_BRDNOGEN_Msk (0x1U << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
5487#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No error generation */
5488#define CEC_CFGR_OAR_Pos (16U)
5489#define CEC_CFGR_OAR_Msk (0x7FFFU << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
5490#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
5491#define CEC_CFGR_LSTN_Pos (31U)
5492#define CEC_CFGR_LSTN_Msk (0x1U << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
5493#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
5494
5495/******************* Bit definition for CEC_TXDR register *******************/
5496#define CEC_TXDR_TXD_Pos (0U)
5497#define CEC_TXDR_TXD_Msk (0xFFU << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
5498#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
5499
5500/******************* Bit definition for CEC_RXDR register *******************/
5501#define CEC_RXDR_RXD_Pos (0U)
5502#define CEC_RXDR_RXD_Msk (0xFFU << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */
5503#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */
5504/*legacy define*/
5505#define CEC_TXDR_RXD CEC_RXDR_RXD /*!< CEC Rx Data */
5506
5507/******************* Bit definition for CEC_ISR register ********************/
5508#define CEC_ISR_RXBR_Pos (0U)
5509#define CEC_ISR_RXBR_Msk (0x1U << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
5510#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
5511#define CEC_ISR_RXEND_Pos (1U)
5512#define CEC_ISR_RXEND_Msk (0x1U << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
5513#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
5514#define CEC_ISR_RXOVR_Pos (2U)
5515#define CEC_ISR_RXOVR_Msk (0x1U << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
5516#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
5517#define CEC_ISR_BRE_Pos (3U)
5518#define CEC_ISR_BRE_Msk (0x1U << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
5519#define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
5520#define CEC_ISR_SBPE_Pos (4U)
5521#define CEC_ISR_SBPE_Msk (0x1U << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
5522#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
5523#define CEC_ISR_LBPE_Pos (5U)
5524#define CEC_ISR_LBPE_Msk (0x1U << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
5525#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
5526#define CEC_ISR_RXACKE_Pos (6U)
5527#define CEC_ISR_RXACKE_Msk (0x1U << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
5528#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
5529#define CEC_ISR_ARBLST_Pos (7U)
5530#define CEC_ISR_ARBLST_Msk (0x1U << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
5531#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
5532#define CEC_ISR_TXBR_Pos (8U)
5533#define CEC_ISR_TXBR_Msk (0x1U << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
5534#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
5535#define CEC_ISR_TXEND_Pos (9U)
5536#define CEC_ISR_TXEND_Msk (0x1U << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
5537#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
5538#define CEC_ISR_TXUDR_Pos (10U)
5539#define CEC_ISR_TXUDR_Msk (0x1U << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
5540#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
5541#define CEC_ISR_TXERR_Pos (11U)
5542#define CEC_ISR_TXERR_Msk (0x1U << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
5543#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
5544#define CEC_ISR_TXACKE_Pos (12U)
5545#define CEC_ISR_TXACKE_Msk (0x1U << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
5546#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
5547
5548/******************* Bit definition for CEC_IER register ********************/
5549#define CEC_IER_RXBRIE_Pos (0U)
5550#define CEC_IER_RXBRIE_Msk (0x1U << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
5551#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
5552#define CEC_IER_RXENDIE_Pos (1U)
5553#define CEC_IER_RXENDIE_Msk (0x1U << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
5554#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
5555#define CEC_IER_RXOVRIE_Pos (2U)
5556#define CEC_IER_RXOVRIE_Msk (0x1U << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
5557#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
5558#define CEC_IER_BREIE_Pos (3U)
5559#define CEC_IER_BREIE_Msk (0x1U << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
5560#define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
5561#define CEC_IER_SBPEIE_Pos (4U)
5562#define CEC_IER_SBPEIE_Msk (0x1U << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
5563#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable */
5564#define CEC_IER_LBPEIE_Pos (5U)
5565#define CEC_IER_LBPEIE_Msk (0x1U << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
5566#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
5567#define CEC_IER_RXACKEIE_Pos (6U)
5568#define CEC_IER_RXACKEIE_Msk (0x1U << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
5569#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
5570#define CEC_IER_ARBLSTIE_Pos (7U)
5571#define CEC_IER_ARBLSTIE_Msk (0x1U << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
5572#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
5573#define CEC_IER_TXBRIE_Pos (8U)
5574#define CEC_IER_TXBRIE_Msk (0x1U << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
5575#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
5576#define CEC_IER_TXENDIE_Pos (9U)
5577#define CEC_IER_TXENDIE_Msk (0x1U << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
5578#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
5579#define CEC_IER_TXUDRIE_Pos (10U)
5580#define CEC_IER_TXUDRIE_Msk (0x1U << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
5581#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
5582#define CEC_IER_TXERRIE_Pos (11U)
5583#define CEC_IER_TXERRIE_Msk (0x1U << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
5584#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
5585#define CEC_IER_TXACKEIE_Pos (12U)
5586#define CEC_IER_TXACKEIE_Msk (0x1U << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
5587#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
5588
5589/******************************************************************************/
5590/* */
5591/* CRC calculation unit */
5592/* */
5593/******************************************************************************/
5594/******************* Bit definition for CRC_DR register *********************/
5595#define CRC_DR_DR_Pos (0U)
5596#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
5597#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
5598
5599
5600/******************* Bit definition for CRC_IDR register ********************/
5601#define CRC_IDR_IDR_Pos (0U)
5602#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
5603#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
5604
5605
5606/******************** Bit definition for CRC_CR register ********************/
5607#define CRC_CR_RESET_Pos (0U)
5608#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
5609#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
5610
5611/******************************************************************************/
5612/* */
5613/* Digital to Analog Converter */
5614/* */
5615/******************************************************************************/
5616/*
5617 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
5618 */
5619#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
5620/******************** Bit definition for DAC_CR register ********************/
5621#define DAC_CR_EN1_Pos (0U)
5622#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
5623#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
5624#define DAC_CR_BOFF1_Pos (1U)
5625#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
5626#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
5627#define DAC_CR_TEN1_Pos (2U)
5628#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
5629#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
5630
5631#define DAC_CR_TSEL1_Pos (3U)
5632#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
5633#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5634#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
5635#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
5636#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
5637
5638#define DAC_CR_WAVE1_Pos (6U)
5639#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
5640#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5641#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
5642#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
5643
5644#define DAC_CR_MAMP1_Pos (8U)
5645#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
5646#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5647#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
5648#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
5649#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
5650#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
5651
5652#define DAC_CR_DMAEN1_Pos (12U)
5653#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
5654#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
5655#define DAC_CR_DMAUDRIE1_Pos (13U)
5656#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
5657#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
5658#define DAC_CR_EN2_Pos (16U)
5659#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
5660#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
5661#define DAC_CR_BOFF2_Pos (17U)
5662#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
5663#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
5664#define DAC_CR_TEN2_Pos (18U)
5665#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
5666#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
5667
5668#define DAC_CR_TSEL2_Pos (19U)
5669#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
5670#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5671#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
5672#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
5673#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
5674
5675#define DAC_CR_WAVE2_Pos (22U)
5676#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
5677#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5678#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
5679#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
5680
5681#define DAC_CR_MAMP2_Pos (24U)
5682#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
5683#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5684#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
5685#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
5686#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
5687#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
5688
5689#define DAC_CR_DMAEN2_Pos (28U)
5690#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
5691#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
5692#define DAC_CR_DMAUDRIE2_Pos (29U)
5693#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
5694#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
5695
5696/***************** Bit definition for DAC_SWTRIGR register ******************/
5697#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5698#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
5699#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
5700#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5701#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
5702#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
5703
5704/***************** Bit definition for DAC_DHR12R1 register ******************/
5705#define DAC_DHR12R1_DACC1DHR_Pos (0U)
5706#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
5707#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5708
5709/***************** Bit definition for DAC_DHR12L1 register ******************/
5710#define DAC_DHR12L1_DACC1DHR_Pos (4U)
5711#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5712#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5713
5714/****************** Bit definition for DAC_DHR8R1 register ******************/
5715#define DAC_DHR8R1_DACC1DHR_Pos (0U)
5716#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
5717#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5718
5719/***************** Bit definition for DAC_DHR12R2 register ******************/
5720#define DAC_DHR12R2_DACC2DHR_Pos (0U)
5721#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
5722#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5723
5724/***************** Bit definition for DAC_DHR12L2 register ******************/
5725#define DAC_DHR12L2_DACC2DHR_Pos (4U)
5726#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
5727#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5728
5729/****************** Bit definition for DAC_DHR8R2 register ******************/
5730#define DAC_DHR8R2_DACC2DHR_Pos (0U)
5731#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
5732#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5733
5734/***************** Bit definition for DAC_DHR12RD register ******************/
5735#define DAC_DHR12RD_DACC1DHR_Pos (0U)
5736#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
5737#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5738#define DAC_DHR12RD_DACC2DHR_Pos (16U)
5739#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
5740#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5741
5742/***************** Bit definition for DAC_DHR12LD register ******************/
5743#define DAC_DHR12LD_DACC1DHR_Pos (4U)
5744#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5745#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5746#define DAC_DHR12LD_DACC2DHR_Pos (20U)
5747#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
5748#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5749
5750/****************** Bit definition for DAC_DHR8RD register ******************/
5751#define DAC_DHR8RD_DACC1DHR_Pos (0U)
5752#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
5753#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5754#define DAC_DHR8RD_DACC2DHR_Pos (8U)
5755#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
5756#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5757
5758/******************* Bit definition for DAC_DOR1 register *******************/
5759#define DAC_DOR1_DACC1DOR_Pos (0U)
5760#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
5761#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
5762
5763/******************* Bit definition for DAC_DOR2 register *******************/
5764#define DAC_DOR2_DACC2DOR_Pos (0U)
5765#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
5766#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
5767
5768/******************** Bit definition for DAC_SR register ********************/
5769#define DAC_SR_DMAUDR1_Pos (13U)
5770#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
5771#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
5772#define DAC_SR_DMAUDR2_Pos (29U)
5773#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
5774#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
5775
5776/******************************************************************************/
5777/* */
5778/* DCMI */
5779/* */
5780/******************************************************************************/
5781/******************** Bits definition for DCMI_CR register ******************/
5782#define DCMI_CR_CAPTURE_Pos (0U)
5783#define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
5784#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
5785#define DCMI_CR_CM_Pos (1U)
5786#define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
5787#define DCMI_CR_CM DCMI_CR_CM_Msk
5788#define DCMI_CR_CROP_Pos (2U)
5789#define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
5790#define DCMI_CR_CROP DCMI_CR_CROP_Msk
5791#define DCMI_CR_JPEG_Pos (3U)
5792#define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
5793#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
5794#define DCMI_CR_ESS_Pos (4U)
5795#define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
5796#define DCMI_CR_ESS DCMI_CR_ESS_Msk
5797#define DCMI_CR_PCKPOL_Pos (5U)
5798#define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
5799#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
5800#define DCMI_CR_HSPOL_Pos (6U)
5801#define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
5802#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
5803#define DCMI_CR_VSPOL_Pos (7U)
5804#define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
5805#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
5806#define DCMI_CR_FCRC_0 0x00000100U
5807#define DCMI_CR_FCRC_1 0x00000200U
5808#define DCMI_CR_EDM_0 0x00000400U
5809#define DCMI_CR_EDM_1 0x00000800U
5810#define DCMI_CR_OUTEN_Pos (13U)
5811#define DCMI_CR_OUTEN_Msk (0x1U << DCMI_CR_OUTEN_Pos) /*!< 0x00002000 */
5812#define DCMI_CR_OUTEN DCMI_CR_OUTEN_Msk
5813#define DCMI_CR_ENABLE_Pos (14U)
5814#define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
5815#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
5816#define DCMI_CR_BSM_0 0x00010000U
5817#define DCMI_CR_BSM_1 0x00020000U
5818#define DCMI_CR_OEBS_Pos (18U)
5819#define DCMI_CR_OEBS_Msk (0x1U << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
5820#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
5821#define DCMI_CR_LSM_Pos (19U)
5822#define DCMI_CR_LSM_Msk (0x1U << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
5823#define DCMI_CR_LSM DCMI_CR_LSM_Msk
5824#define DCMI_CR_OELS_Pos (20U)
5825#define DCMI_CR_OELS_Msk (0x1U << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
5826#define DCMI_CR_OELS DCMI_CR_OELS_Msk
5827
5828/******************** Bits definition for DCMI_SR register ******************/
5829#define DCMI_SR_HSYNC_Pos (0U)
5830#define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
5831#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
5832#define DCMI_SR_VSYNC_Pos (1U)
5833#define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
5834#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
5835#define DCMI_SR_FNE_Pos (2U)
5836#define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
5837#define DCMI_SR_FNE DCMI_SR_FNE_Msk
5838
5839/******************** Bits definition for DCMI_RIS register *****************/
5840#define DCMI_RIS_FRAME_RIS_Pos (0U)
5841#define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
5842#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
5843#define DCMI_RIS_OVR_RIS_Pos (1U)
5844#define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
5845#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
5846#define DCMI_RIS_ERR_RIS_Pos (2U)
5847#define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
5848#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
5849#define DCMI_RIS_VSYNC_RIS_Pos (3U)
5850#define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
5851#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
5852#define DCMI_RIS_LINE_RIS_Pos (4U)
5853#define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
5854#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
5855/* Legacy defines */
5856#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
5857#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
5858#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
5859#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
5860#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
5861#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
5862
5863/******************** Bits definition for DCMI_IER register *****************/
5864#define DCMI_IER_FRAME_IE_Pos (0U)
5865#define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
5866#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
5867#define DCMI_IER_OVR_IE_Pos (1U)
5868#define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
5869#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
5870#define DCMI_IER_ERR_IE_Pos (2U)
5871#define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
5872#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
5873#define DCMI_IER_VSYNC_IE_Pos (3U)
5874#define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
5875#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
5876#define DCMI_IER_LINE_IE_Pos (4U)
5877#define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
5878#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
5879/* Legacy defines */
5880#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
5881
5882/******************** Bits definition for DCMI_MIS register *****************/
5883#define DCMI_MIS_FRAME_MIS_Pos (0U)
5884#define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
5885#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
5886#define DCMI_MIS_OVR_MIS_Pos (1U)
5887#define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
5888#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
5889#define DCMI_MIS_ERR_MIS_Pos (2U)
5890#define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
5891#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
5892#define DCMI_MIS_VSYNC_MIS_Pos (3U)
5893#define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
5894#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
5895#define DCMI_MIS_LINE_MIS_Pos (4U)
5896#define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
5897#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
5898
5899/* Legacy defines */
5900#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
5901#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
5902#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
5903#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
5904#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
5905
5906/******************** Bits definition for DCMI_ICR register *****************/
5907#define DCMI_ICR_FRAME_ISC_Pos (0U)
5908#define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
5909#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
5910#define DCMI_ICR_OVR_ISC_Pos (1U)
5911#define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
5912#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
5913#define DCMI_ICR_ERR_ISC_Pos (2U)
5914#define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
5915#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
5916#define DCMI_ICR_VSYNC_ISC_Pos (3U)
5917#define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
5918#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
5919#define DCMI_ICR_LINE_ISC_Pos (4U)
5920#define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
5921#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
5922
5923/* Legacy defines */
5924#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
5925
5926/******************** Bits definition for DCMI_ESCR register ******************/
5927#define DCMI_ESCR_FSC_Pos (0U)
5928#define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
5929#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
5930#define DCMI_ESCR_LSC_Pos (8U)
5931#define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
5932#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
5933#define DCMI_ESCR_LEC_Pos (16U)
5934#define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
5935#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
5936#define DCMI_ESCR_FEC_Pos (24U)
5937#define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
5938#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
5939
5940/******************** Bits definition for DCMI_ESUR register ******************/
5941#define DCMI_ESUR_FSU_Pos (0U)
5942#define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
5943#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
5944#define DCMI_ESUR_LSU_Pos (8U)
5945#define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
5946#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
5947#define DCMI_ESUR_LEU_Pos (16U)
5948#define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
5949#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
5950#define DCMI_ESUR_FEU_Pos (24U)
5951#define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
5952#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
5953
5954/******************** Bits definition for DCMI_CWSTRT register ******************/
5955#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
5956#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
5957#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
5958#define DCMI_CWSTRT_VST_Pos (16U)
5959#define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
5960#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
5961
5962/******************** Bits definition for DCMI_CWSIZE register ******************/
5963#define DCMI_CWSIZE_CAPCNT_Pos (0U)
5964#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
5965#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
5966#define DCMI_CWSIZE_VLINE_Pos (16U)
5967#define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
5968#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
5969
5970/******************** Bits definition for DCMI_DR register *********************/
5971#define DCMI_DR_BYTE0_Pos (0U)
5972#define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
5973#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
5974#define DCMI_DR_BYTE1_Pos (8U)
5975#define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
5976#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
5977#define DCMI_DR_BYTE2_Pos (16U)
5978#define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
5979#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
5980#define DCMI_DR_BYTE3_Pos (24U)
5981#define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
5982#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
5983
5984/******************************************************************************/
5985/* */
5986/* DMA Controller */
5987/* */
5988/******************************************************************************/
5989/******************** Bits definition for DMA_SxCR register *****************/
5990#define DMA_SxCR_CHSEL_Pos (25U)
5991#define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
5992#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
5993#define DMA_SxCR_CHSEL_0 0x02000000U
5994#define DMA_SxCR_CHSEL_1 0x04000000U
5995#define DMA_SxCR_CHSEL_2 0x08000000U
5996#define DMA_SxCR_MBURST_Pos (23U)
5997#define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
5998#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
5999#define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
6000#define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
6001#define DMA_SxCR_PBURST_Pos (21U)
6002#define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
6003#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
6004#define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
6005#define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
6006#define DMA_SxCR_CT_Pos (19U)
6007#define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
6008#define DMA_SxCR_CT DMA_SxCR_CT_Msk
6009#define DMA_SxCR_DBM_Pos (18U)
6010#define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
6011#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
6012#define DMA_SxCR_PL_Pos (16U)
6013#define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
6014#define DMA_SxCR_PL DMA_SxCR_PL_Msk
6015#define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
6016#define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
6017#define DMA_SxCR_PINCOS_Pos (15U)
6018#define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
6019#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
6020#define DMA_SxCR_MSIZE_Pos (13U)
6021#define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
6022#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
6023#define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
6024#define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
6025#define DMA_SxCR_PSIZE_Pos (11U)
6026#define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
6027#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
6028#define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
6029#define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
6030#define DMA_SxCR_MINC_Pos (10U)
6031#define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
6032#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
6033#define DMA_SxCR_PINC_Pos (9U)
6034#define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
6035#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
6036#define DMA_SxCR_CIRC_Pos (8U)
6037#define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
6038#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
6039#define DMA_SxCR_DIR_Pos (6U)
6040#define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
6041#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
6042#define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
6043#define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
6044#define DMA_SxCR_PFCTRL_Pos (5U)
6045#define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
6046#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
6047#define DMA_SxCR_TCIE_Pos (4U)
6048#define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
6049#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
6050#define DMA_SxCR_HTIE_Pos (3U)
6051#define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
6052#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
6053#define DMA_SxCR_TEIE_Pos (2U)
6054#define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
6055#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
6056#define DMA_SxCR_DMEIE_Pos (1U)
6057#define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
6058#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
6059#define DMA_SxCR_EN_Pos (0U)
6060#define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
6061#define DMA_SxCR_EN DMA_SxCR_EN_Msk
6062
6063/* Legacy defines */
6064#define DMA_SxCR_ACK_Pos (20U)
6065#define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
6066#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
6067
6068/******************** Bits definition for DMA_SxCNDTR register **************/
6069#define DMA_SxNDT_Pos (0U)
6070#define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
6071#define DMA_SxNDT DMA_SxNDT_Msk
6072#define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
6073#define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
6074#define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
6075#define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
6076#define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
6077#define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
6078#define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
6079#define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
6080#define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
6081#define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
6082#define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
6083#define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
6084#define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
6085#define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
6086#define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
6087#define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
6088
6089/******************** Bits definition for DMA_SxFCR register ****************/
6090#define DMA_SxFCR_FEIE_Pos (7U)
6091#define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
6092#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
6093#define DMA_SxFCR_FS_Pos (3U)
6094#define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
6095#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
6096#define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
6097#define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
6098#define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
6099#define DMA_SxFCR_DMDIS_Pos (2U)
6100#define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
6101#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
6102#define DMA_SxFCR_FTH_Pos (0U)
6103#define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
6104#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
6105#define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
6106#define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
6107
6108/******************** Bits definition for DMA_LISR register *****************/
6109#define DMA_LISR_TCIF3_Pos (27U)
6110#define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
6111#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
6112#define DMA_LISR_HTIF3_Pos (26U)
6113#define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
6114#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
6115#define DMA_LISR_TEIF3_Pos (25U)
6116#define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
6117#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
6118#define DMA_LISR_DMEIF3_Pos (24U)
6119#define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
6120#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
6121#define DMA_LISR_FEIF3_Pos (22U)
6122#define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
6123#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
6124#define DMA_LISR_TCIF2_Pos (21U)
6125#define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
6126#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
6127#define DMA_LISR_HTIF2_Pos (20U)
6128#define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
6129#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
6130#define DMA_LISR_TEIF2_Pos (19U)
6131#define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
6132#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
6133#define DMA_LISR_DMEIF2_Pos (18U)
6134#define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
6135#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
6136#define DMA_LISR_FEIF2_Pos (16U)
6137#define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
6138#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
6139#define DMA_LISR_TCIF1_Pos (11U)
6140#define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
6141#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
6142#define DMA_LISR_HTIF1_Pos (10U)
6143#define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
6144#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
6145#define DMA_LISR_TEIF1_Pos (9U)
6146#define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
6147#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
6148#define DMA_LISR_DMEIF1_Pos (8U)
6149#define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
6150#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
6151#define DMA_LISR_FEIF1_Pos (6U)
6152#define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
6153#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
6154#define DMA_LISR_TCIF0_Pos (5U)
6155#define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
6156#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
6157#define DMA_LISR_HTIF0_Pos (4U)
6158#define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
6159#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
6160#define DMA_LISR_TEIF0_Pos (3U)
6161#define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
6162#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
6163#define DMA_LISR_DMEIF0_Pos (2U)
6164#define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
6165#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
6166#define DMA_LISR_FEIF0_Pos (0U)
6167#define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
6168#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
6169
6170/******************** Bits definition for DMA_HISR register *****************/
6171#define DMA_HISR_TCIF7_Pos (27U)
6172#define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
6173#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
6174#define DMA_HISR_HTIF7_Pos (26U)
6175#define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
6176#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
6177#define DMA_HISR_TEIF7_Pos (25U)
6178#define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
6179#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
6180#define DMA_HISR_DMEIF7_Pos (24U)
6181#define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
6182#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
6183#define DMA_HISR_FEIF7_Pos (22U)
6184#define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
6185#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
6186#define DMA_HISR_TCIF6_Pos (21U)
6187#define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
6188#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
6189#define DMA_HISR_HTIF6_Pos (20U)
6190#define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
6191#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
6192#define DMA_HISR_TEIF6_Pos (19U)
6193#define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
6194#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
6195#define DMA_HISR_DMEIF6_Pos (18U)
6196#define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
6197#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
6198#define DMA_HISR_FEIF6_Pos (16U)
6199#define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
6200#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
6201#define DMA_HISR_TCIF5_Pos (11U)
6202#define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
6203#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
6204#define DMA_HISR_HTIF5_Pos (10U)
6205#define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
6206#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
6207#define DMA_HISR_TEIF5_Pos (9U)
6208#define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
6209#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
6210#define DMA_HISR_DMEIF5_Pos (8U)
6211#define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
6212#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
6213#define DMA_HISR_FEIF5_Pos (6U)
6214#define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
6215#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
6216#define DMA_HISR_TCIF4_Pos (5U)
6217#define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
6218#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
6219#define DMA_HISR_HTIF4_Pos (4U)
6220#define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
6221#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
6222#define DMA_HISR_TEIF4_Pos (3U)
6223#define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
6224#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
6225#define DMA_HISR_DMEIF4_Pos (2U)
6226#define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
6227#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
6228#define DMA_HISR_FEIF4_Pos (0U)
6229#define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
6230#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
6231
6232/******************** Bits definition for DMA_LIFCR register ****************/
6233#define DMA_LIFCR_CTCIF3_Pos (27U)
6234#define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
6235#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
6236#define DMA_LIFCR_CHTIF3_Pos (26U)
6237#define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
6238#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
6239#define DMA_LIFCR_CTEIF3_Pos (25U)
6240#define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
6241#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
6242#define DMA_LIFCR_CDMEIF3_Pos (24U)
6243#define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
6244#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
6245#define DMA_LIFCR_CFEIF3_Pos (22U)
6246#define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
6247#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
6248#define DMA_LIFCR_CTCIF2_Pos (21U)
6249#define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
6250#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
6251#define DMA_LIFCR_CHTIF2_Pos (20U)
6252#define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
6253#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
6254#define DMA_LIFCR_CTEIF2_Pos (19U)
6255#define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
6256#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
6257#define DMA_LIFCR_CDMEIF2_Pos (18U)
6258#define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
6259#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
6260#define DMA_LIFCR_CFEIF2_Pos (16U)
6261#define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
6262#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
6263#define DMA_LIFCR_CTCIF1_Pos (11U)
6264#define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
6265#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
6266#define DMA_LIFCR_CHTIF1_Pos (10U)
6267#define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
6268#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
6269#define DMA_LIFCR_CTEIF1_Pos (9U)
6270#define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
6271#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
6272#define DMA_LIFCR_CDMEIF1_Pos (8U)
6273#define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
6274#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
6275#define DMA_LIFCR_CFEIF1_Pos (6U)
6276#define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
6277#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
6278#define DMA_LIFCR_CTCIF0_Pos (5U)
6279#define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
6280#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
6281#define DMA_LIFCR_CHTIF0_Pos (4U)
6282#define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
6283#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
6284#define DMA_LIFCR_CTEIF0_Pos (3U)
6285#define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
6286#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
6287#define DMA_LIFCR_CDMEIF0_Pos (2U)
6288#define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
6289#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
6290#define DMA_LIFCR_CFEIF0_Pos (0U)
6291#define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
6292#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
6293
6294/******************** Bits definition for DMA_HIFCR register ****************/
6295#define DMA_HIFCR_CTCIF7_Pos (27U)
6296#define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
6297#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
6298#define DMA_HIFCR_CHTIF7_Pos (26U)
6299#define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
6300#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
6301#define DMA_HIFCR_CTEIF7_Pos (25U)
6302#define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
6303#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
6304#define DMA_HIFCR_CDMEIF7_Pos (24U)
6305#define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
6306#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
6307#define DMA_HIFCR_CFEIF7_Pos (22U)
6308#define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
6309#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
6310#define DMA_HIFCR_CTCIF6_Pos (21U)
6311#define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
6312#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
6313#define DMA_HIFCR_CHTIF6_Pos (20U)
6314#define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
6315#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
6316#define DMA_HIFCR_CTEIF6_Pos (19U)
6317#define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
6318#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
6319#define DMA_HIFCR_CDMEIF6_Pos (18U)
6320#define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
6321#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
6322#define DMA_HIFCR_CFEIF6_Pos (16U)
6323#define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
6324#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
6325#define DMA_HIFCR_CTCIF5_Pos (11U)
6326#define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
6327#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
6328#define DMA_HIFCR_CHTIF5_Pos (10U)
6329#define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
6330#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
6331#define DMA_HIFCR_CTEIF5_Pos (9U)
6332#define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
6333#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
6334#define DMA_HIFCR_CDMEIF5_Pos (8U)
6335#define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
6336#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
6337#define DMA_HIFCR_CFEIF5_Pos (6U)
6338#define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
6339#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
6340#define DMA_HIFCR_CTCIF4_Pos (5U)
6341#define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
6342#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
6343#define DMA_HIFCR_CHTIF4_Pos (4U)
6344#define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
6345#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
6346#define DMA_HIFCR_CTEIF4_Pos (3U)
6347#define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
6348#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
6349#define DMA_HIFCR_CDMEIF4_Pos (2U)
6350#define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
6351#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
6352#define DMA_HIFCR_CFEIF4_Pos (0U)
6353#define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
6354#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
6355
6356/****************** Bit definition for DMA_SxPAR register ********************/
6357#define DMA_SxPAR_PA_Pos (0U)
6358#define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
6359#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
6360
6361/****************** Bit definition for DMA_SxM0AR register ********************/
6362#define DMA_SxM0AR_M0A_Pos (0U)
6363#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
6364#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
6365
6366/****************** Bit definition for DMA_SxM1AR register ********************/
6367#define DMA_SxM1AR_M1A_Pos (0U)
6368#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
6369#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
6370
6371
6372/******************************************************************************/
6373/* */
6374/* External Interrupt/Event Controller */
6375/* */
6376/******************************************************************************/
6377/******************* Bit definition for EXTI_IMR register *******************/
6378#define EXTI_IMR_MR0_Pos (0U)
6379#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
6380#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
6381#define EXTI_IMR_MR1_Pos (1U)
6382#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
6383#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
6384#define EXTI_IMR_MR2_Pos (2U)
6385#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
6386#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
6387#define EXTI_IMR_MR3_Pos (3U)
6388#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
6389#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
6390#define EXTI_IMR_MR4_Pos (4U)
6391#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
6392#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
6393#define EXTI_IMR_MR5_Pos (5U)
6394#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
6395#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
6396#define EXTI_IMR_MR6_Pos (6U)
6397#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
6398#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
6399#define EXTI_IMR_MR7_Pos (7U)
6400#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
6401#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
6402#define EXTI_IMR_MR8_Pos (8U)
6403#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
6404#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
6405#define EXTI_IMR_MR9_Pos (9U)
6406#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
6407#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
6408#define EXTI_IMR_MR10_Pos (10U)
6409#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
6410#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
6411#define EXTI_IMR_MR11_Pos (11U)
6412#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
6413#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
6414#define EXTI_IMR_MR12_Pos (12U)
6415#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
6416#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
6417#define EXTI_IMR_MR13_Pos (13U)
6418#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
6419#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
6420#define EXTI_IMR_MR14_Pos (14U)
6421#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
6422#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
6423#define EXTI_IMR_MR15_Pos (15U)
6424#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
6425#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
6426#define EXTI_IMR_MR16_Pos (16U)
6427#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
6428#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
6429#define EXTI_IMR_MR17_Pos (17U)
6430#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
6431#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
6432#define EXTI_IMR_MR18_Pos (18U)
6433#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
6434#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
6435#define EXTI_IMR_MR19_Pos (19U)
6436#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
6437#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
6438#define EXTI_IMR_MR20_Pos (20U)
6439#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
6440#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
6441#define EXTI_IMR_MR21_Pos (21U)
6442#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
6443#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
6444#define EXTI_IMR_MR22_Pos (22U)
6445#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
6446#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
6447
6448/* Reference Defines */
6449#define EXTI_IMR_IM0 EXTI_IMR_MR0
6450#define EXTI_IMR_IM1 EXTI_IMR_MR1
6451#define EXTI_IMR_IM2 EXTI_IMR_MR2
6452#define EXTI_IMR_IM3 EXTI_IMR_MR3
6453#define EXTI_IMR_IM4 EXTI_IMR_MR4
6454#define EXTI_IMR_IM5 EXTI_IMR_MR5
6455#define EXTI_IMR_IM6 EXTI_IMR_MR6
6456#define EXTI_IMR_IM7 EXTI_IMR_MR7
6457#define EXTI_IMR_IM8 EXTI_IMR_MR8
6458#define EXTI_IMR_IM9 EXTI_IMR_MR9
6459#define EXTI_IMR_IM10 EXTI_IMR_MR10
6460#define EXTI_IMR_IM11 EXTI_IMR_MR11
6461#define EXTI_IMR_IM12 EXTI_IMR_MR12
6462#define EXTI_IMR_IM13 EXTI_IMR_MR13
6463#define EXTI_IMR_IM14 EXTI_IMR_MR14
6464#define EXTI_IMR_IM15 EXTI_IMR_MR15
6465#define EXTI_IMR_IM16 EXTI_IMR_MR16
6466#define EXTI_IMR_IM17 EXTI_IMR_MR17
6467#define EXTI_IMR_IM18 EXTI_IMR_MR18
6468#define EXTI_IMR_IM19 EXTI_IMR_MR19
6469#define EXTI_IMR_IM20 EXTI_IMR_MR20
6470#define EXTI_IMR_IM21 EXTI_IMR_MR21
6471#define EXTI_IMR_IM22 EXTI_IMR_MR22
6472#define EXTI_IMR_IM_Pos (0U)
6473#define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
6474#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
6475
6476/******************* Bit definition for EXTI_EMR register *******************/
6477#define EXTI_EMR_MR0_Pos (0U)
6478#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
6479#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
6480#define EXTI_EMR_MR1_Pos (1U)
6481#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
6482#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
6483#define EXTI_EMR_MR2_Pos (2U)
6484#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
6485#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
6486#define EXTI_EMR_MR3_Pos (3U)
6487#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
6488#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
6489#define EXTI_EMR_MR4_Pos (4U)
6490#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
6491#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
6492#define EXTI_EMR_MR5_Pos (5U)
6493#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
6494#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
6495#define EXTI_EMR_MR6_Pos (6U)
6496#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
6497#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
6498#define EXTI_EMR_MR7_Pos (7U)
6499#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
6500#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
6501#define EXTI_EMR_MR8_Pos (8U)
6502#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
6503#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
6504#define EXTI_EMR_MR9_Pos (9U)
6505#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
6506#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
6507#define EXTI_EMR_MR10_Pos (10U)
6508#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
6509#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
6510#define EXTI_EMR_MR11_Pos (11U)
6511#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
6512#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
6513#define EXTI_EMR_MR12_Pos (12U)
6514#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
6515#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
6516#define EXTI_EMR_MR13_Pos (13U)
6517#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
6518#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
6519#define EXTI_EMR_MR14_Pos (14U)
6520#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
6521#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
6522#define EXTI_EMR_MR15_Pos (15U)
6523#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
6524#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
6525#define EXTI_EMR_MR16_Pos (16U)
6526#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
6527#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
6528#define EXTI_EMR_MR17_Pos (17U)
6529#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
6530#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
6531#define EXTI_EMR_MR18_Pos (18U)
6532#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
6533#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
6534#define EXTI_EMR_MR19_Pos (19U)
6535#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
6536#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
6537#define EXTI_EMR_MR20_Pos (20U)
6538#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
6539#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
6540#define EXTI_EMR_MR21_Pos (21U)
6541#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
6542#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
6543#define EXTI_EMR_MR22_Pos (22U)
6544#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
6545#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
6546
6547/* Reference Defines */
6548#define EXTI_EMR_EM0 EXTI_EMR_MR0
6549#define EXTI_EMR_EM1 EXTI_EMR_MR1
6550#define EXTI_EMR_EM2 EXTI_EMR_MR2
6551#define EXTI_EMR_EM3 EXTI_EMR_MR3
6552#define EXTI_EMR_EM4 EXTI_EMR_MR4
6553#define EXTI_EMR_EM5 EXTI_EMR_MR5
6554#define EXTI_EMR_EM6 EXTI_EMR_MR6
6555#define EXTI_EMR_EM7 EXTI_EMR_MR7
6556#define EXTI_EMR_EM8 EXTI_EMR_MR8
6557#define EXTI_EMR_EM9 EXTI_EMR_MR9
6558#define EXTI_EMR_EM10 EXTI_EMR_MR10
6559#define EXTI_EMR_EM11 EXTI_EMR_MR11
6560#define EXTI_EMR_EM12 EXTI_EMR_MR12
6561#define EXTI_EMR_EM13 EXTI_EMR_MR13
6562#define EXTI_EMR_EM14 EXTI_EMR_MR14
6563#define EXTI_EMR_EM15 EXTI_EMR_MR15
6564#define EXTI_EMR_EM16 EXTI_EMR_MR16
6565#define EXTI_EMR_EM17 EXTI_EMR_MR17
6566#define EXTI_EMR_EM18 EXTI_EMR_MR18
6567#define EXTI_EMR_EM19 EXTI_EMR_MR19
6568#define EXTI_EMR_EM20 EXTI_EMR_MR20
6569#define EXTI_EMR_EM21 EXTI_EMR_MR21
6570#define EXTI_EMR_EM22 EXTI_EMR_MR22
6571
6572/****************** Bit definition for EXTI_RTSR register *******************/
6573#define EXTI_RTSR_TR0_Pos (0U)
6574#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
6575#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
6576#define EXTI_RTSR_TR1_Pos (1U)
6577#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
6578#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
6579#define EXTI_RTSR_TR2_Pos (2U)
6580#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
6581#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
6582#define EXTI_RTSR_TR3_Pos (3U)
6583#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
6584#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
6585#define EXTI_RTSR_TR4_Pos (4U)
6586#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
6587#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
6588#define EXTI_RTSR_TR5_Pos (5U)
6589#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
6590#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
6591#define EXTI_RTSR_TR6_Pos (6U)
6592#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
6593#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
6594#define EXTI_RTSR_TR7_Pos (7U)
6595#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
6596#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
6597#define EXTI_RTSR_TR8_Pos (8U)
6598#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
6599#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
6600#define EXTI_RTSR_TR9_Pos (9U)
6601#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
6602#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
6603#define EXTI_RTSR_TR10_Pos (10U)
6604#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
6605#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
6606#define EXTI_RTSR_TR11_Pos (11U)
6607#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
6608#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
6609#define EXTI_RTSR_TR12_Pos (12U)
6610#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
6611#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
6612#define EXTI_RTSR_TR13_Pos (13U)
6613#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
6614#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
6615#define EXTI_RTSR_TR14_Pos (14U)
6616#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
6617#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
6618#define EXTI_RTSR_TR15_Pos (15U)
6619#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
6620#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
6621#define EXTI_RTSR_TR16_Pos (16U)
6622#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
6623#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
6624#define EXTI_RTSR_TR17_Pos (17U)
6625#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
6626#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
6627#define EXTI_RTSR_TR18_Pos (18U)
6628#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
6629#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
6630#define EXTI_RTSR_TR19_Pos (19U)
6631#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
6632#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
6633#define EXTI_RTSR_TR20_Pos (20U)
6634#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
6635#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
6636#define EXTI_RTSR_TR21_Pos (21U)
6637#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
6638#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
6639#define EXTI_RTSR_TR22_Pos (22U)
6640#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
6641#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
6642
6643/****************** Bit definition for EXTI_FTSR register *******************/
6644#define EXTI_FTSR_TR0_Pos (0U)
6645#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
6646#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
6647#define EXTI_FTSR_TR1_Pos (1U)
6648#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
6649#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
6650#define EXTI_FTSR_TR2_Pos (2U)
6651#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
6652#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
6653#define EXTI_FTSR_TR3_Pos (3U)
6654#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
6655#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
6656#define EXTI_FTSR_TR4_Pos (4U)
6657#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
6658#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
6659#define EXTI_FTSR_TR5_Pos (5U)
6660#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
6661#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
6662#define EXTI_FTSR_TR6_Pos (6U)
6663#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
6664#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
6665#define EXTI_FTSR_TR7_Pos (7U)
6666#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
6667#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
6668#define EXTI_FTSR_TR8_Pos (8U)
6669#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
6670#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
6671#define EXTI_FTSR_TR9_Pos (9U)
6672#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
6673#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
6674#define EXTI_FTSR_TR10_Pos (10U)
6675#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
6676#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
6677#define EXTI_FTSR_TR11_Pos (11U)
6678#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
6679#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
6680#define EXTI_FTSR_TR12_Pos (12U)
6681#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
6682#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
6683#define EXTI_FTSR_TR13_Pos (13U)
6684#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
6685#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
6686#define EXTI_FTSR_TR14_Pos (14U)
6687#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
6688#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
6689#define EXTI_FTSR_TR15_Pos (15U)
6690#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
6691#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
6692#define EXTI_FTSR_TR16_Pos (16U)
6693#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
6694#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
6695#define EXTI_FTSR_TR17_Pos (17U)
6696#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
6697#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
6698#define EXTI_FTSR_TR18_Pos (18U)
6699#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
6700#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
6701#define EXTI_FTSR_TR19_Pos (19U)
6702#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
6703#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
6704#define EXTI_FTSR_TR20_Pos (20U)
6705#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
6706#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
6707#define EXTI_FTSR_TR21_Pos (21U)
6708#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
6709#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
6710#define EXTI_FTSR_TR22_Pos (22U)
6711#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
6712#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
6713
6714/****************** Bit definition for EXTI_SWIER register ******************/
6715#define EXTI_SWIER_SWIER0_Pos (0U)
6716#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
6717#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
6718#define EXTI_SWIER_SWIER1_Pos (1U)
6719#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
6720#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
6721#define EXTI_SWIER_SWIER2_Pos (2U)
6722#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
6723#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
6724#define EXTI_SWIER_SWIER3_Pos (3U)
6725#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
6726#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
6727#define EXTI_SWIER_SWIER4_Pos (4U)
6728#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
6729#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
6730#define EXTI_SWIER_SWIER5_Pos (5U)
6731#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
6732#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
6733#define EXTI_SWIER_SWIER6_Pos (6U)
6734#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
6735#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
6736#define EXTI_SWIER_SWIER7_Pos (7U)
6737#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
6738#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
6739#define EXTI_SWIER_SWIER8_Pos (8U)
6740#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
6741#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
6742#define EXTI_SWIER_SWIER9_Pos (9U)
6743#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
6744#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
6745#define EXTI_SWIER_SWIER10_Pos (10U)
6746#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
6747#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
6748#define EXTI_SWIER_SWIER11_Pos (11U)
6749#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
6750#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
6751#define EXTI_SWIER_SWIER12_Pos (12U)
6752#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
6753#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
6754#define EXTI_SWIER_SWIER13_Pos (13U)
6755#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
6756#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
6757#define EXTI_SWIER_SWIER14_Pos (14U)
6758#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
6759#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
6760#define EXTI_SWIER_SWIER15_Pos (15U)
6761#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
6762#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
6763#define EXTI_SWIER_SWIER16_Pos (16U)
6764#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
6765#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
6766#define EXTI_SWIER_SWIER17_Pos (17U)
6767#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
6768#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
6769#define EXTI_SWIER_SWIER18_Pos (18U)
6770#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
6771#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
6772#define EXTI_SWIER_SWIER19_Pos (19U)
6773#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
6774#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
6775#define EXTI_SWIER_SWIER20_Pos (20U)
6776#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
6777#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
6778#define EXTI_SWIER_SWIER21_Pos (21U)
6779#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
6780#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
6781#define EXTI_SWIER_SWIER22_Pos (22U)
6782#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
6783#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
6784
6785/******************* Bit definition for EXTI_PR register ********************/
6786#define EXTI_PR_PR0_Pos (0U)
6787#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
6788#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
6789#define EXTI_PR_PR1_Pos (1U)
6790#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
6791#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
6792#define EXTI_PR_PR2_Pos (2U)
6793#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
6794#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
6795#define EXTI_PR_PR3_Pos (3U)
6796#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
6797#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
6798#define EXTI_PR_PR4_Pos (4U)
6799#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
6800#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
6801#define EXTI_PR_PR5_Pos (5U)
6802#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
6803#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
6804#define EXTI_PR_PR6_Pos (6U)
6805#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
6806#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
6807#define EXTI_PR_PR7_Pos (7U)
6808#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
6809#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
6810#define EXTI_PR_PR8_Pos (8U)
6811#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
6812#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
6813#define EXTI_PR_PR9_Pos (9U)
6814#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
6815#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
6816#define EXTI_PR_PR10_Pos (10U)
6817#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
6818#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
6819#define EXTI_PR_PR11_Pos (11U)
6820#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
6821#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
6822#define EXTI_PR_PR12_Pos (12U)
6823#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
6824#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
6825#define EXTI_PR_PR13_Pos (13U)
6826#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
6827#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
6828#define EXTI_PR_PR14_Pos (14U)
6829#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
6830#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
6831#define EXTI_PR_PR15_Pos (15U)
6832#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
6833#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
6834#define EXTI_PR_PR16_Pos (16U)
6835#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
6836#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
6837#define EXTI_PR_PR17_Pos (17U)
6838#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
6839#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
6840#define EXTI_PR_PR18_Pos (18U)
6841#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
6842#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
6843#define EXTI_PR_PR19_Pos (19U)
6844#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
6845#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
6846#define EXTI_PR_PR20_Pos (20U)
6847#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
6848#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
6849#define EXTI_PR_PR21_Pos (21U)
6850#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
6851#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
6852#define EXTI_PR_PR22_Pos (22U)
6853#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
6854#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
6855
6856/******************************************************************************/
6857/* */
6858/* FLASH */
6859/* */
6860/******************************************************************************/
6861/******************* Bits definition for FLASH_ACR register *****************/
6862#define FLASH_ACR_LATENCY_Pos (0U)
6863#define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
6864#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
6865#define FLASH_ACR_LATENCY_0WS 0x00000000U
6866#define FLASH_ACR_LATENCY_1WS 0x00000001U
6867#define FLASH_ACR_LATENCY_2WS 0x00000002U
6868#define FLASH_ACR_LATENCY_3WS 0x00000003U
6869#define FLASH_ACR_LATENCY_4WS 0x00000004U
6870#define FLASH_ACR_LATENCY_5WS 0x00000005U
6871#define FLASH_ACR_LATENCY_6WS 0x00000006U
6872#define FLASH_ACR_LATENCY_7WS 0x00000007U
6873
6874#define FLASH_ACR_LATENCY_8WS 0x00000008U
6875#define FLASH_ACR_LATENCY_9WS 0x00000009U
6876#define FLASH_ACR_LATENCY_10WS 0x0000000AU
6877#define FLASH_ACR_LATENCY_11WS 0x0000000BU
6878#define FLASH_ACR_LATENCY_12WS 0x0000000CU
6879#define FLASH_ACR_LATENCY_13WS 0x0000000DU
6880#define FLASH_ACR_LATENCY_14WS 0x0000000EU
6881#define FLASH_ACR_LATENCY_15WS 0x0000000FU
6882#define FLASH_ACR_PRFTEN_Pos (8U)
6883#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
6884#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
6885#define FLASH_ACR_ICEN_Pos (9U)
6886#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
6887#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
6888#define FLASH_ACR_DCEN_Pos (10U)
6889#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
6890#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
6891#define FLASH_ACR_ICRST_Pos (11U)
6892#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
6893#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
6894#define FLASH_ACR_DCRST_Pos (12U)
6895#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
6896#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
6897#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
6898#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
6899#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
6900#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
6901#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
6902#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
6903
6904/******************* Bits definition for FLASH_SR register ******************/
6905#define FLASH_SR_EOP_Pos (0U)
6906#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
6907#define FLASH_SR_EOP FLASH_SR_EOP_Msk
6908#define FLASH_SR_SOP_Pos (1U)
6909#define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
6910#define FLASH_SR_SOP FLASH_SR_SOP_Msk
6911#define FLASH_SR_WRPERR_Pos (4U)
6912#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
6913#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
6914#define FLASH_SR_PGAERR_Pos (5U)
6915#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
6916#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
6917#define FLASH_SR_PGPERR_Pos (6U)
6918#define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
6919#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
6920#define FLASH_SR_PGSERR_Pos (7U)
6921#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
6922#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
6923#define FLASH_SR_RDERR_Pos (8U)
6924#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
6925#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
6926#define FLASH_SR_BSY_Pos (16U)
6927#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
6928#define FLASH_SR_BSY FLASH_SR_BSY_Msk
6929
6930/******************* Bits definition for FLASH_CR register ******************/
6931#define FLASH_CR_PG_Pos (0U)
6932#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
6933#define FLASH_CR_PG FLASH_CR_PG_Msk
6934#define FLASH_CR_SER_Pos (1U)
6935#define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
6936#define FLASH_CR_SER FLASH_CR_SER_Msk
6937#define FLASH_CR_MER_Pos (2U)
6938#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
6939#define FLASH_CR_MER FLASH_CR_MER_Msk
6940#define FLASH_CR_MER1 FLASH_CR_MER
6941#define FLASH_CR_SNB_Pos (3U)
6942#define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
6943#define FLASH_CR_SNB FLASH_CR_SNB_Msk
6944#define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
6945#define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
6946#define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
6947#define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
6948#define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
6949#define FLASH_CR_PSIZE_Pos (8U)
6950#define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
6951#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
6952#define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
6953#define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
6954#define FLASH_CR_MER2_Pos (15U)
6955#define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
6956#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
6957#define FLASH_CR_STRT_Pos (16U)
6958#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
6959#define FLASH_CR_STRT FLASH_CR_STRT_Msk
6960#define FLASH_CR_EOPIE_Pos (24U)
6961#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
6962#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
6963#define FLASH_CR_LOCK_Pos (31U)
6964#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
6965#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
6966
6967/******************* Bits definition for FLASH_OPTCR register ***************/
6968#define FLASH_OPTCR_OPTLOCK_Pos (0U)
6969#define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
6970#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
6971#define FLASH_OPTCR_OPTSTRT_Pos (1U)
6972#define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
6973#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
6974
6975#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
6976#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
6977#define FLASH_OPTCR_BOR_LEV_Pos (2U)
6978#define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
6979#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
6980#define FLASH_OPTCR_BFB2_Pos (4U)
6981#define FLASH_OPTCR_BFB2_Msk (0x1U << FLASH_OPTCR_BFB2_Pos) /*!< 0x00000010 */
6982#define FLASH_OPTCR_BFB2 FLASH_OPTCR_BFB2_Msk
6983#define FLASH_OPTCR_WDG_SW_Pos (5U)
6984#define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
6985#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
6986#define FLASH_OPTCR_nRST_STOP_Pos (6U)
6987#define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
6988#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
6989#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
6990#define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
6991#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
6992#define FLASH_OPTCR_RDP_Pos (8U)
6993#define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
6994#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
6995#define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
6996#define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
6997#define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
6998#define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
6999#define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
7000#define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
7001#define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
7002#define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
7003#define FLASH_OPTCR_nWRP_Pos (16U)
7004#define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
7005#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
7006#define FLASH_OPTCR_nWRP_0 0x00010000U
7007#define FLASH_OPTCR_nWRP_1 0x00020000U
7008#define FLASH_OPTCR_nWRP_2 0x00040000U
7009#define FLASH_OPTCR_nWRP_3 0x00080000U
7010#define FLASH_OPTCR_nWRP_4 0x00100000U
7011#define FLASH_OPTCR_nWRP_5 0x00200000U
7012#define FLASH_OPTCR_nWRP_6 0x00400000U
7013#define FLASH_OPTCR_nWRP_7 0x00800000U
7014#define FLASH_OPTCR_nWRP_8 0x01000000U
7015#define FLASH_OPTCR_nWRP_9 0x02000000U
7016#define FLASH_OPTCR_nWRP_10 0x04000000U
7017#define FLASH_OPTCR_nWRP_11 0x08000000U
7018#define FLASH_OPTCR_DB1M_Pos (30U)
7019#define FLASH_OPTCR_DB1M_Msk (0x1U << FLASH_OPTCR_DB1M_Pos) /*!< 0x40000000 */
7020#define FLASH_OPTCR_DB1M FLASH_OPTCR_DB1M_Msk
7021#define FLASH_OPTCR_SPRMOD_Pos (31U)
7022#define FLASH_OPTCR_SPRMOD_Msk (0x1U << FLASH_OPTCR_SPRMOD_Pos) /*!< 0x80000000 */
7023#define FLASH_OPTCR_SPRMOD FLASH_OPTCR_SPRMOD_Msk
7024
7025/****************** Bits definition for FLASH_OPTCR1 register ***************/
7026#define FLASH_OPTCR1_nWRP_Pos (16U)
7027#define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
7028#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
7029#define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
7030#define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
7031#define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
7032#define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
7033#define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
7034#define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
7035#define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
7036#define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
7037#define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
7038#define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
7039#define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
7040#define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
7041
7042/******************************************************************************/
7043/* */
7044/* Flexible Memory Controller */
7045/* */
7046/******************************************************************************/
7047/****************** Bit definition for FMC_BCR1 register *******************/
7048#define FMC_BCR1_MBKEN_Pos (0U)
7049#define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
7050#define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
7051#define FMC_BCR1_MUXEN_Pos (1U)
7052#define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
7053#define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
7054
7055#define FMC_BCR1_MTYP_Pos (2U)
7056#define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
7057#define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
7058#define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
7059#define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
7060
7061#define FMC_BCR1_MWID_Pos (4U)
7062#define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
7063#define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
7064#define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
7065#define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
7066
7067#define FMC_BCR1_FACCEN_Pos (6U)
7068#define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
7069#define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
7070#define FMC_BCR1_BURSTEN_Pos (8U)
7071#define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
7072#define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
7073#define FMC_BCR1_WAITPOL_Pos (9U)
7074#define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
7075#define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
7076#define FMC_BCR1_WAITCFG_Pos (11U)
7077#define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
7078#define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
7079#define FMC_BCR1_WREN_Pos (12U)
7080#define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
7081#define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
7082#define FMC_BCR1_WAITEN_Pos (13U)
7083#define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
7084#define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
7085#define FMC_BCR1_EXTMOD_Pos (14U)
7086#define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
7087#define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
7088#define FMC_BCR1_ASYNCWAIT_Pos (15U)
7089#define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
7090#define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
7091#define FMC_BCR1_CPSIZE_Pos (16U)
7092#define FMC_BCR1_CPSIZE_Msk (0x7U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
7093#define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
7094#define FMC_BCR1_CPSIZE_0 (0x1U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
7095#define FMC_BCR1_CPSIZE_1 (0x2U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
7096#define FMC_BCR1_CPSIZE_2 (0x4U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
7097#define FMC_BCR1_CBURSTRW_Pos (19U)
7098#define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
7099#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
7100#define FMC_BCR1_CCLKEN_Pos (20U)
7101#define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
7102#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
7103#define FMC_BCR1_WFDIS_Pos (21U)
7104#define FMC_BCR1_WFDIS_Msk (0x1U << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
7105#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
7106
7107/****************** Bit definition for FMC_BCR2 register *******************/
7108#define FMC_BCR2_MBKEN_Pos (0U)
7109#define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
7110#define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
7111#define FMC_BCR2_MUXEN_Pos (1U)
7112#define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
7113#define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
7114
7115#define FMC_BCR2_MTYP_Pos (2U)
7116#define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
7117#define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
7118#define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
7119#define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
7120
7121#define FMC_BCR2_MWID_Pos (4U)
7122#define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
7123#define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
7124#define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
7125#define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
7126
7127#define FMC_BCR2_FACCEN_Pos (6U)
7128#define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
7129#define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
7130#define FMC_BCR2_BURSTEN_Pos (8U)
7131#define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
7132#define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
7133#define FMC_BCR2_WAITPOL_Pos (9U)
7134#define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
7135#define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
7136#define FMC_BCR2_WAITCFG_Pos (11U)
7137#define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
7138#define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
7139#define FMC_BCR2_WREN_Pos (12U)
7140#define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
7141#define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
7142#define FMC_BCR2_WAITEN_Pos (13U)
7143#define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
7144#define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
7145#define FMC_BCR2_EXTMOD_Pos (14U)
7146#define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
7147#define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
7148#define FMC_BCR2_ASYNCWAIT_Pos (15U)
7149#define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
7150#define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
7151#define FMC_BCR2_CBURSTRW_Pos (19U)
7152#define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
7153#define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
7154
7155/****************** Bit definition for FMC_BCR3 register *******************/
7156#define FMC_BCR3_MBKEN_Pos (0U)
7157#define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
7158#define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
7159#define FMC_BCR3_MUXEN_Pos (1U)
7160#define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
7161#define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
7162
7163#define FMC_BCR3_MTYP_Pos (2U)
7164#define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
7165#define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
7166#define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
7167#define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
7168
7169#define FMC_BCR3_MWID_Pos (4U)
7170#define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
7171#define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
7172#define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
7173#define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
7174
7175#define FMC_BCR3_FACCEN_Pos (6U)
7176#define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
7177#define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
7178#define FMC_BCR3_BURSTEN_Pos (8U)
7179#define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
7180#define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
7181#define FMC_BCR3_WAITPOL_Pos (9U)
7182#define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
7183#define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
7184#define FMC_BCR3_WAITCFG_Pos (11U)
7185#define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
7186#define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
7187#define FMC_BCR3_WREN_Pos (12U)
7188#define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
7189#define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
7190#define FMC_BCR3_WAITEN_Pos (13U)
7191#define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
7192#define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
7193#define FMC_BCR3_EXTMOD_Pos (14U)
7194#define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
7195#define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
7196#define FMC_BCR3_ASYNCWAIT_Pos (15U)
7197#define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
7198#define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
7199#define FMC_BCR3_CBURSTRW_Pos (19U)
7200#define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
7201#define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
7202
7203/****************** Bit definition for FMC_BCR4 register *******************/
7204#define FMC_BCR4_MBKEN_Pos (0U)
7205#define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
7206#define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
7207#define FMC_BCR4_MUXEN_Pos (1U)
7208#define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
7209#define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
7210
7211#define FMC_BCR4_MTYP_Pos (2U)
7212#define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
7213#define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
7214#define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
7215#define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
7216
7217#define FMC_BCR4_MWID_Pos (4U)
7218#define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
7219#define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
7220#define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
7221#define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
7222
7223#define FMC_BCR4_FACCEN_Pos (6U)
7224#define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
7225#define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
7226#define FMC_BCR4_BURSTEN_Pos (8U)
7227#define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
7228#define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
7229#define FMC_BCR4_WAITPOL_Pos (9U)
7230#define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
7231#define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
7232#define FMC_BCR4_WAITCFG_Pos (11U)
7233#define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
7234#define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
7235#define FMC_BCR4_WREN_Pos (12U)
7236#define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
7237#define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
7238#define FMC_BCR4_WAITEN_Pos (13U)
7239#define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
7240#define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
7241#define FMC_BCR4_EXTMOD_Pos (14U)
7242#define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
7243#define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
7244#define FMC_BCR4_ASYNCWAIT_Pos (15U)
7245#define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
7246#define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
7247#define FMC_BCR4_CBURSTRW_Pos (19U)
7248#define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
7249#define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
7250
7251/****************** Bit definition for FMC_BTR1 register ******************/
7252#define FMC_BTR1_ADDSET_Pos (0U)
7253#define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
7254#define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7255#define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
7256#define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
7257#define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
7258#define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
7259
7260#define FMC_BTR1_ADDHLD_Pos (4U)
7261#define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
7262#define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7263#define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
7264#define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
7265#define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
7266#define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
7267
7268#define FMC_BTR1_DATAST_Pos (8U)
7269#define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
7270#define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7271#define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
7272#define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
7273#define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
7274#define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
7275#define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
7276#define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
7277#define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
7278#define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
7279
7280#define FMC_BTR1_BUSTURN_Pos (16U)
7281#define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
7282#define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7283#define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
7284#define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
7285#define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
7286#define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
7287
7288#define FMC_BTR1_CLKDIV_Pos (20U)
7289#define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
7290#define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7291#define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
7292#define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
7293#define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
7294#define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
7295
7296#define FMC_BTR1_DATLAT_Pos (24U)
7297#define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
7298#define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7299#define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
7300#define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
7301#define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
7302#define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
7303
7304#define FMC_BTR1_ACCMOD_Pos (28U)
7305#define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
7306#define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7307#define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
7308#define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
7309
7310/****************** Bit definition for FMC_BTR2 register *******************/
7311#define FMC_BTR2_ADDSET_Pos (0U)
7312#define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
7313#define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7314#define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
7315#define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
7316#define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
7317#define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
7318
7319#define FMC_BTR2_ADDHLD_Pos (4U)
7320#define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
7321#define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7322#define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
7323#define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
7324#define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
7325#define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
7326
7327#define FMC_BTR2_DATAST_Pos (8U)
7328#define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
7329#define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7330#define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
7331#define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
7332#define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
7333#define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
7334#define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
7335#define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
7336#define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
7337#define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
7338
7339#define FMC_BTR2_BUSTURN_Pos (16U)
7340#define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
7341#define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7342#define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
7343#define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
7344#define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
7345#define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
7346
7347#define FMC_BTR2_CLKDIV_Pos (20U)
7348#define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
7349#define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7350#define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
7351#define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
7352#define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
7353#define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
7354
7355#define FMC_BTR2_DATLAT_Pos (24U)
7356#define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
7357#define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7358#define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
7359#define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
7360#define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
7361#define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
7362
7363#define FMC_BTR2_ACCMOD_Pos (28U)
7364#define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
7365#define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7366#define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
7367#define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
7368
7369/******************* Bit definition for FMC_BTR3 register *******************/
7370#define FMC_BTR3_ADDSET_Pos (0U)
7371#define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
7372#define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7373#define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
7374#define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
7375#define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
7376#define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
7377
7378#define FMC_BTR3_ADDHLD_Pos (4U)
7379#define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
7380#define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7381#define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
7382#define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
7383#define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
7384#define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
7385
7386#define FMC_BTR3_DATAST_Pos (8U)
7387#define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
7388#define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7389#define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
7390#define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
7391#define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
7392#define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
7393#define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
7394#define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
7395#define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
7396#define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
7397
7398#define FMC_BTR3_BUSTURN_Pos (16U)
7399#define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
7400#define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7401#define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
7402#define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
7403#define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
7404#define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
7405
7406#define FMC_BTR3_CLKDIV_Pos (20U)
7407#define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
7408#define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7409#define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
7410#define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
7411#define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
7412#define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
7413
7414#define FMC_BTR3_DATLAT_Pos (24U)
7415#define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
7416#define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7417#define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
7418#define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
7419#define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
7420#define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
7421
7422#define FMC_BTR3_ACCMOD_Pos (28U)
7423#define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
7424#define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7425#define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
7426#define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
7427
7428/****************** Bit definition for FMC_BTR4 register *******************/
7429#define FMC_BTR4_ADDSET_Pos (0U)
7430#define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
7431#define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7432#define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
7433#define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
7434#define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
7435#define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
7436
7437#define FMC_BTR4_ADDHLD_Pos (4U)
7438#define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
7439#define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7440#define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
7441#define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
7442#define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
7443#define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
7444
7445#define FMC_BTR4_DATAST_Pos (8U)
7446#define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
7447#define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7448#define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
7449#define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
7450#define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
7451#define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
7452#define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
7453#define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
7454#define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
7455#define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
7456
7457#define FMC_BTR4_BUSTURN_Pos (16U)
7458#define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
7459#define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7460#define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
7461#define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
7462#define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
7463#define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
7464
7465#define FMC_BTR4_CLKDIV_Pos (20U)
7466#define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
7467#define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7468#define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
7469#define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
7470#define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
7471#define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
7472
7473#define FMC_BTR4_DATLAT_Pos (24U)
7474#define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
7475#define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
7476#define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
7477#define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
7478#define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
7479#define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
7480
7481#define FMC_BTR4_ACCMOD_Pos (28U)
7482#define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
7483#define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7484#define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
7485#define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
7486
7487/****************** Bit definition for FMC_BWTR1 register ******************/
7488#define FMC_BWTR1_ADDSET_Pos (0U)
7489#define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
7490#define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7491#define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
7492#define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
7493#define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
7494#define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
7495
7496#define FMC_BWTR1_ADDHLD_Pos (4U)
7497#define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
7498#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7499#define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
7500#define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
7501#define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
7502#define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
7503
7504#define FMC_BWTR1_DATAST_Pos (8U)
7505#define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
7506#define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7507#define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
7508#define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
7509#define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
7510#define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
7511#define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
7512#define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
7513#define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
7514#define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
7515
7516#define FMC_BWTR1_BUSTURN_Pos (16U)
7517#define FMC_BWTR1_BUSTURN_Msk (0xFU << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
7518#define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7519#define FMC_BWTR1_BUSTURN_0 (0x1U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
7520#define FMC_BWTR1_BUSTURN_1 (0x2U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
7521#define FMC_BWTR1_BUSTURN_2 (0x4U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
7522#define FMC_BWTR1_BUSTURN_3 (0x8U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
7523
7524#define FMC_BWTR1_ACCMOD_Pos (28U)
7525#define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
7526#define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7527#define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
7528#define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
7529
7530/****************** Bit definition for FMC_BWTR2 register ******************/
7531#define FMC_BWTR2_ADDSET_Pos (0U)
7532#define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
7533#define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7534#define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
7535#define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
7536#define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
7537#define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
7538
7539#define FMC_BWTR2_ADDHLD_Pos (4U)
7540#define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
7541#define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7542#define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
7543#define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
7544#define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
7545#define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
7546
7547#define FMC_BWTR2_DATAST_Pos (8U)
7548#define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
7549#define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7550#define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
7551#define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
7552#define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
7553#define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
7554#define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
7555#define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
7556#define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
7557#define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
7558
7559#define FMC_BWTR2_BUSTURN_Pos (16U)
7560#define FMC_BWTR2_BUSTURN_Msk (0xFU << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
7561#define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7562#define FMC_BWTR2_BUSTURN_0 (0x1U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
7563#define FMC_BWTR2_BUSTURN_1 (0x2U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
7564#define FMC_BWTR2_BUSTURN_2 (0x4U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
7565#define FMC_BWTR2_BUSTURN_3 (0x8U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
7566
7567#define FMC_BWTR2_ACCMOD_Pos (28U)
7568#define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
7569#define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7570#define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
7571#define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
7572
7573/****************** Bit definition for FMC_BWTR3 register ******************/
7574#define FMC_BWTR3_ADDSET_Pos (0U)
7575#define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
7576#define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7577#define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
7578#define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
7579#define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
7580#define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
7581
7582#define FMC_BWTR3_ADDHLD_Pos (4U)
7583#define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
7584#define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7585#define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
7586#define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
7587#define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
7588#define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
7589
7590#define FMC_BWTR3_DATAST_Pos (8U)
7591#define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
7592#define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7593#define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
7594#define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
7595#define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
7596#define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
7597#define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
7598#define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
7599#define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
7600#define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
7601
7602#define FMC_BWTR3_BUSTURN_Pos (16U)
7603#define FMC_BWTR3_BUSTURN_Msk (0xFU << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
7604#define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7605#define FMC_BWTR3_BUSTURN_0 (0x1U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
7606#define FMC_BWTR3_BUSTURN_1 (0x2U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
7607#define FMC_BWTR3_BUSTURN_2 (0x4U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
7608#define FMC_BWTR3_BUSTURN_3 (0x8U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
7609
7610#define FMC_BWTR3_ACCMOD_Pos (28U)
7611#define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
7612#define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7613#define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
7614#define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
7615
7616/****************** Bit definition for FMC_BWTR4 register ******************/
7617#define FMC_BWTR4_ADDSET_Pos (0U)
7618#define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
7619#define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
7620#define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
7621#define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
7622#define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
7623#define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
7624
7625#define FMC_BWTR4_ADDHLD_Pos (4U)
7626#define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
7627#define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7628#define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
7629#define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
7630#define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
7631#define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
7632
7633#define FMC_BWTR4_DATAST_Pos (8U)
7634#define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
7635#define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
7636#define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
7637#define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
7638#define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
7639#define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
7640#define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
7641#define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
7642#define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
7643#define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
7644
7645#define FMC_BWTR4_BUSTURN_Pos (16U)
7646#define FMC_BWTR4_BUSTURN_Msk (0xFU << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
7647#define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7648#define FMC_BWTR4_BUSTURN_0 (0x1U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
7649#define FMC_BWTR4_BUSTURN_1 (0x2U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
7650#define FMC_BWTR4_BUSTURN_2 (0x4U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
7651#define FMC_BWTR4_BUSTURN_3 (0x8U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
7652
7653#define FMC_BWTR4_ACCMOD_Pos (28U)
7654#define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
7655#define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
7656#define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
7657#define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
7658
7659/****************** Bit definition for FMC_PCR register *******************/
7660#define FMC_PCR_PWAITEN_Pos (1U)
7661#define FMC_PCR_PWAITEN_Msk (0x1U << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
7662#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
7663#define FMC_PCR_PBKEN_Pos (2U)
7664#define FMC_PCR_PBKEN_Msk (0x1U << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
7665#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
7666#define FMC_PCR_PTYP_Pos (3U)
7667#define FMC_PCR_PTYP_Msk (0x1U << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
7668#define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
7669
7670#define FMC_PCR_PWID_Pos (4U)
7671#define FMC_PCR_PWID_Msk (0x3U << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
7672#define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
7673#define FMC_PCR_PWID_0 (0x1U << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
7674#define FMC_PCR_PWID_1 (0x2U << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
7675
7676#define FMC_PCR_ECCEN_Pos (6U)
7677#define FMC_PCR_ECCEN_Msk (0x1U << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
7678#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
7679
7680#define FMC_PCR_TCLR_Pos (9U)
7681#define FMC_PCR_TCLR_Msk (0xFU << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
7682#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
7683#define FMC_PCR_TCLR_0 (0x1U << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
7684#define FMC_PCR_TCLR_1 (0x2U << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
7685#define FMC_PCR_TCLR_2 (0x4U << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
7686#define FMC_PCR_TCLR_3 (0x8U << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
7687
7688#define FMC_PCR_TAR_Pos (13U)
7689#define FMC_PCR_TAR_Msk (0xFU << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
7690#define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
7691#define FMC_PCR_TAR_0 (0x1U << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
7692#define FMC_PCR_TAR_1 (0x2U << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
7693#define FMC_PCR_TAR_2 (0x4U << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
7694#define FMC_PCR_TAR_3 (0x8U << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
7695
7696#define FMC_PCR_ECCPS_Pos (17U)
7697#define FMC_PCR_ECCPS_Msk (0x7U << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
7698#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
7699#define FMC_PCR_ECCPS_0 (0x1U << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
7700#define FMC_PCR_ECCPS_1 (0x2U << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
7701#define FMC_PCR_ECCPS_2 (0x4U << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
7702
7703/******************* Bit definition for FMC_SR register *******************/
7704#define FMC_SR_IRS_Pos (0U)
7705#define FMC_SR_IRS_Msk (0x1U << FMC_SR_IRS_Pos) /*!< 0x00000001 */
7706#define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
7707#define FMC_SR_ILS_Pos (1U)
7708#define FMC_SR_ILS_Msk (0x1U << FMC_SR_ILS_Pos) /*!< 0x00000002 */
7709#define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
7710#define FMC_SR_IFS_Pos (2U)
7711#define FMC_SR_IFS_Msk (0x1U << FMC_SR_IFS_Pos) /*!< 0x00000004 */
7712#define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
7713#define FMC_SR_IREN_Pos (3U)
7714#define FMC_SR_IREN_Msk (0x1U << FMC_SR_IREN_Pos) /*!< 0x00000008 */
7715#define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
7716#define FMC_SR_ILEN_Pos (4U)
7717#define FMC_SR_ILEN_Msk (0x1U << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
7718#define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
7719#define FMC_SR_IFEN_Pos (5U)
7720#define FMC_SR_IFEN_Msk (0x1U << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
7721#define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
7722#define FMC_SR_FEMPT_Pos (6U)
7723#define FMC_SR_FEMPT_Msk (0x1U << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
7724#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
7725
7726/****************** Bit definition for FMC_PMEM register ******************/
7727#define FMC_PMEM_MEMSET2_Pos (0U)
7728#define FMC_PMEM_MEMSET2_Msk (0xFFU << FMC_PMEM_MEMSET2_Pos) /*!< 0x000000FF */
7729#define FMC_PMEM_MEMSET2 FMC_PMEM_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
7730#define FMC_PMEM_MEMSET2_0 (0x01U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000001 */
7731#define FMC_PMEM_MEMSET2_1 (0x02U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000002 */
7732#define FMC_PMEM_MEMSET2_2 (0x04U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000004 */
7733#define FMC_PMEM_MEMSET2_3 (0x08U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000008 */
7734#define FMC_PMEM_MEMSET2_4 (0x10U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000010 */
7735#define FMC_PMEM_MEMSET2_5 (0x20U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000020 */
7736#define FMC_PMEM_MEMSET2_6 (0x40U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000040 */
7737#define FMC_PMEM_MEMSET2_7 (0x80U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000080 */
7738
7739#define FMC_PMEM_MEMWAIT2_Pos (8U)
7740#define FMC_PMEM_MEMWAIT2_Msk (0xFFU << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x0000FF00 */
7741#define FMC_PMEM_MEMWAIT2 FMC_PMEM_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
7742#define FMC_PMEM_MEMWAIT2_0 (0x01U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000100 */
7743#define FMC_PMEM_MEMWAIT2_1 (0x02U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000200 */
7744#define FMC_PMEM_MEMWAIT2_2 (0x04U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000400 */
7745#define FMC_PMEM_MEMWAIT2_3 (0x08U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000800 */
7746#define FMC_PMEM_MEMWAIT2_4 (0x10U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00001000 */
7747#define FMC_PMEM_MEMWAIT2_5 (0x20U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00002000 */
7748#define FMC_PMEM_MEMWAIT2_6 (0x40U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00004000 */
7749#define FMC_PMEM_MEMWAIT2_7 (0x80U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00008000 */
7750
7751#define FMC_PMEM_MEMHOLD2_Pos (16U)
7752#define FMC_PMEM_MEMHOLD2_Msk (0xFFU << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00FF0000 */
7753#define FMC_PMEM_MEMHOLD2 FMC_PMEM_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
7754#define FMC_PMEM_MEMHOLD2_0 (0x01U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00010000 */
7755#define FMC_PMEM_MEMHOLD2_1 (0x02U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00020000 */
7756#define FMC_PMEM_MEMHOLD2_2 (0x04U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00040000 */
7757#define FMC_PMEM_MEMHOLD2_3 (0x08U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00080000 */
7758#define FMC_PMEM_MEMHOLD2_4 (0x10U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00100000 */
7759#define FMC_PMEM_MEMHOLD2_5 (0x20U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00200000 */
7760#define FMC_PMEM_MEMHOLD2_6 (0x40U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00400000 */
7761#define FMC_PMEM_MEMHOLD2_7 (0x80U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00800000 */
7762
7763#define FMC_PMEM_MEMHIZ2_Pos (24U)
7764#define FMC_PMEM_MEMHIZ2_Msk (0xFFU << FMC_PMEM_MEMHIZ2_Pos) /*!< 0xFF000000 */
7765#define FMC_PMEM_MEMHIZ2 FMC_PMEM_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
7766#define FMC_PMEM_MEMHIZ2_0 (0x01U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x01000000 */
7767#define FMC_PMEM_MEMHIZ2_1 (0x02U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x02000000 */
7768#define FMC_PMEM_MEMHIZ2_2 (0x04U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x04000000 */
7769#define FMC_PMEM_MEMHIZ2_3 (0x08U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x08000000 */
7770#define FMC_PMEM_MEMHIZ2_4 (0x10U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x10000000 */
7771#define FMC_PMEM_MEMHIZ2_5 (0x20U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x20000000 */
7772#define FMC_PMEM_MEMHIZ2_6 (0x40U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x40000000 */
7773#define FMC_PMEM_MEMHIZ2_7 (0x80U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x80000000 */
7774
7775/****************** Bit definition for FMC_PATT register ******************/
7776#define FMC_PATT_ATTSET2_Pos (0U)
7777#define FMC_PATT_ATTSET2_Msk (0xFFU << FMC_PATT_ATTSET2_Pos) /*!< 0x000000FF */
7778#define FMC_PATT_ATTSET2 FMC_PATT_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
7779#define FMC_PATT_ATTSET2_0 (0x01U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000001 */
7780#define FMC_PATT_ATTSET2_1 (0x02U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000002 */
7781#define FMC_PATT_ATTSET2_2 (0x04U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000004 */
7782#define FMC_PATT_ATTSET2_3 (0x08U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000008 */
7783#define FMC_PATT_ATTSET2_4 (0x10U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000010 */
7784#define FMC_PATT_ATTSET2_5 (0x20U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000020 */
7785#define FMC_PATT_ATTSET2_6 (0x40U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000040 */
7786#define FMC_PATT_ATTSET2_7 (0x80U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000080 */
7787
7788#define FMC_PATT_ATTWAIT2_Pos (8U)
7789#define FMC_PATT_ATTWAIT2_Msk (0xFFU << FMC_PATT_ATTWAIT2_Pos) /*!< 0x0000FF00 */
7790#define FMC_PATT_ATTWAIT2 FMC_PATT_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
7791#define FMC_PATT_ATTWAIT2_0 (0x01U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000100 */
7792#define FMC_PATT_ATTWAIT2_1 (0x02U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000200 */
7793#define FMC_PATT_ATTWAIT2_2 (0x04U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000400 */
7794#define FMC_PATT_ATTWAIT2_3 (0x08U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000800 */
7795#define FMC_PATT_ATTWAIT2_4 (0x10U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00001000 */
7796#define FMC_PATT_ATTWAIT2_5 (0x20U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00002000 */
7797#define FMC_PATT_ATTWAIT2_6 (0x40U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00004000 */
7798#define FMC_PATT_ATTWAIT2_7 (0x80U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00008000 */
7799
7800#define FMC_PATT_ATTHOLD2_Pos (16U)
7801#define FMC_PATT_ATTHOLD2_Msk (0xFFU << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00FF0000 */
7802#define FMC_PATT_ATTHOLD2 FMC_PATT_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
7803#define FMC_PATT_ATTHOLD2_0 (0x01U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00010000 */
7804#define FMC_PATT_ATTHOLD2_1 (0x02U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00020000 */
7805#define FMC_PATT_ATTHOLD2_2 (0x04U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00040000 */
7806#define FMC_PATT_ATTHOLD2_3 (0x08U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00080000 */
7807#define FMC_PATT_ATTHOLD2_4 (0x10U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00100000 */
7808#define FMC_PATT_ATTHOLD2_5 (0x20U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00200000 */
7809#define FMC_PATT_ATTHOLD2_6 (0x40U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00400000 */
7810#define FMC_PATT_ATTHOLD2_7 (0x80U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00800000 */
7811
7812#define FMC_PATT_ATTHIZ2_Pos (24U)
7813#define FMC_PATT_ATTHIZ2_Msk (0xFFU << FMC_PATT_ATTHIZ2_Pos) /*!< 0xFF000000 */
7814#define FMC_PATT_ATTHIZ2 FMC_PATT_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
7815#define FMC_PATT_ATTHIZ2_0 (0x01U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x01000000 */
7816#define FMC_PATT_ATTHIZ2_1 (0x02U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x02000000 */
7817#define FMC_PATT_ATTHIZ2_2 (0x04U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x04000000 */
7818#define FMC_PATT_ATTHIZ2_3 (0x08U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x08000000 */
7819#define FMC_PATT_ATTHIZ2_4 (0x10U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x10000000 */
7820#define FMC_PATT_ATTHIZ2_5 (0x20U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x20000000 */
7821#define FMC_PATT_ATTHIZ2_6 (0x40U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x40000000 */
7822#define FMC_PATT_ATTHIZ2_7 (0x80U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x80000000 */
7823
7824/****************** Bit definition for FMC_ECCR register ******************/
7825#define FMC_ECCR_ECC2_Pos (0U)
7826#define FMC_ECCR_ECC2_Msk (0xFFFFFFFFU << FMC_ECCR_ECC2_Pos) /*!< 0xFFFFFFFF */
7827#define FMC_ECCR_ECC2 FMC_ECCR_ECC2_Msk /*!<ECC result */
7828
7829/****************** Bit definition for FMC_SDCR1 register ******************/
7830#define FMC_SDCR1_NC_Pos (0U)
7831#define FMC_SDCR1_NC_Msk (0x3U << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */
7832#define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
7833#define FMC_SDCR1_NC_0 (0x1U << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */
7834#define FMC_SDCR1_NC_1 (0x2U << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */
7835
7836#define FMC_SDCR1_NR_Pos (2U)
7837#define FMC_SDCR1_NR_Msk (0x3U << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */
7838#define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
7839#define FMC_SDCR1_NR_0 (0x1U << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */
7840#define FMC_SDCR1_NR_1 (0x2U << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */
7841
7842#define FMC_SDCR1_MWID_Pos (4U)
7843#define FMC_SDCR1_MWID_Msk (0x3U << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */
7844#define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
7845#define FMC_SDCR1_MWID_0 (0x1U << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */
7846#define FMC_SDCR1_MWID_1 (0x2U << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */
7847
7848#define FMC_SDCR1_NB_Pos (6U)
7849#define FMC_SDCR1_NB_Msk (0x1U << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */
7850#define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */
7851
7852#define FMC_SDCR1_CAS_Pos (7U)
7853#define FMC_SDCR1_CAS_Msk (0x3U << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */
7854#define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
7855#define FMC_SDCR1_CAS_0 (0x1U << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */
7856#define FMC_SDCR1_CAS_1 (0x2U << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */
7857
7858#define FMC_SDCR1_WP_Pos (9U)
7859#define FMC_SDCR1_WP_Msk (0x1U << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */
7860#define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */
7861
7862#define FMC_SDCR1_SDCLK_Pos (10U)
7863#define FMC_SDCR1_SDCLK_Msk (0x3U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
7864#define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */
7865#define FMC_SDCR1_SDCLK_0 (0x1U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
7866#define FMC_SDCR1_SDCLK_1 (0x2U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
7867
7868#define FMC_SDCR1_RBURST_Pos (12U)
7869#define FMC_SDCR1_RBURST_Msk (0x1U << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */
7870#define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */
7871
7872#define FMC_SDCR1_RPIPE_Pos (13U)
7873#define FMC_SDCR1_RPIPE_Msk (0x3U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */
7874#define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */
7875#define FMC_SDCR1_RPIPE_0 (0x1U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */
7876#define FMC_SDCR1_RPIPE_1 (0x2U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */
7877
7878/****************** Bit definition for FMC_SDCR2 register ******************/
7879#define FMC_SDCR2_NC_Pos (0U)
7880#define FMC_SDCR2_NC_Msk (0x3U << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */
7881#define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
7882#define FMC_SDCR2_NC_0 (0x1U << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */
7883#define FMC_SDCR2_NC_1 (0x2U << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */
7884
7885#define FMC_SDCR2_NR_Pos (2U)
7886#define FMC_SDCR2_NR_Msk (0x3U << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */
7887#define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
7888#define FMC_SDCR2_NR_0 (0x1U << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */
7889#define FMC_SDCR2_NR_1 (0x2U << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */
7890
7891#define FMC_SDCR2_MWID_Pos (4U)
7892#define FMC_SDCR2_MWID_Msk (0x3U << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */
7893#define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
7894#define FMC_SDCR2_MWID_0 (0x1U << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */
7895#define FMC_SDCR2_MWID_1 (0x2U << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */
7896
7897#define FMC_SDCR2_NB_Pos (6U)
7898#define FMC_SDCR2_NB_Msk (0x1U << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */
7899#define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */
7900
7901#define FMC_SDCR2_CAS_Pos (7U)
7902#define FMC_SDCR2_CAS_Msk (0x3U << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */
7903#define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
7904#define FMC_SDCR2_CAS_0 (0x1U << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */
7905#define FMC_SDCR2_CAS_1 (0x2U << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */
7906
7907#define FMC_SDCR2_WP_Pos (9U)
7908#define FMC_SDCR2_WP_Msk (0x1U << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */
7909#define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */
7910
7911#define FMC_SDCR2_SDCLK_Pos (10U)
7912#define FMC_SDCR2_SDCLK_Msk (0x3U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */
7913#define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */
7914#define FMC_SDCR2_SDCLK_0 (0x1U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */
7915#define FMC_SDCR2_SDCLK_1 (0x2U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */
7916
7917#define FMC_SDCR2_RBURST_Pos (12U)
7918#define FMC_SDCR2_RBURST_Msk (0x1U << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */
7919#define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */
7920
7921#define FMC_SDCR2_RPIPE_Pos (13U)
7922#define FMC_SDCR2_RPIPE_Msk (0x3U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */
7923#define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */
7924#define FMC_SDCR2_RPIPE_0 (0x1U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */
7925#define FMC_SDCR2_RPIPE_1 (0x2U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */
7926
7927/****************** Bit definition for FMC_SDTR1 register ******************/
7928#define FMC_SDTR1_TMRD_Pos (0U)
7929#define FMC_SDTR1_TMRD_Msk (0xFU << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */
7930#define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
7931#define FMC_SDTR1_TMRD_0 (0x1U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */
7932#define FMC_SDTR1_TMRD_1 (0x2U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */
7933#define FMC_SDTR1_TMRD_2 (0x4U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */
7934#define FMC_SDTR1_TMRD_3 (0x8U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */
7935
7936#define FMC_SDTR1_TXSR_Pos (4U)
7937#define FMC_SDTR1_TXSR_Msk (0xFU << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */
7938#define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
7939#define FMC_SDTR1_TXSR_0 (0x1U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */
7940#define FMC_SDTR1_TXSR_1 (0x2U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */
7941#define FMC_SDTR1_TXSR_2 (0x4U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */
7942#define FMC_SDTR1_TXSR_3 (0x8U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */
7943
7944#define FMC_SDTR1_TRAS_Pos (8U)
7945#define FMC_SDTR1_TRAS_Msk (0xFU << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */
7946#define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
7947#define FMC_SDTR1_TRAS_0 (0x1U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */
7948#define FMC_SDTR1_TRAS_1 (0x2U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */
7949#define FMC_SDTR1_TRAS_2 (0x4U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */
7950#define FMC_SDTR1_TRAS_3 (0x8U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */
7951
7952#define FMC_SDTR1_TRC_Pos (12U)
7953#define FMC_SDTR1_TRC_Msk (0xFU << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */
7954#define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
7955#define FMC_SDTR1_TRC_0 (0x1U << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */
7956#define FMC_SDTR1_TRC_1 (0x2U << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */
7957#define FMC_SDTR1_TRC_2 (0x4U << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */
7958
7959#define FMC_SDTR1_TWR_Pos (16U)
7960#define FMC_SDTR1_TWR_Msk (0xFU << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
7961#define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
7962#define FMC_SDTR1_TWR_0 (0x1U << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
7963#define FMC_SDTR1_TWR_1 (0x2U << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
7964#define FMC_SDTR1_TWR_2 (0x4U << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
7965
7966#define FMC_SDTR1_TRP_Pos (20U)
7967#define FMC_SDTR1_TRP_Msk (0xFU << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */
7968#define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
7969#define FMC_SDTR1_TRP_0 (0x1U << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */
7970#define FMC_SDTR1_TRP_1 (0x2U << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */
7971#define FMC_SDTR1_TRP_2 (0x4U << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */
7972
7973#define FMC_SDTR1_TRCD_Pos (24U)
7974#define FMC_SDTR1_TRCD_Msk (0xFU << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
7975#define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
7976#define FMC_SDTR1_TRCD_0 (0x1U << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
7977#define FMC_SDTR1_TRCD_1 (0x2U << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
7978#define FMC_SDTR1_TRCD_2 (0x4U << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
7979
7980/****************** Bit definition for FMC_SDTR2 register ******************/
7981#define FMC_SDTR2_TMRD_Pos (0U)
7982#define FMC_SDTR2_TMRD_Msk (0xFU << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */
7983#define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
7984#define FMC_SDTR2_TMRD_0 (0x1U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */
7985#define FMC_SDTR2_TMRD_1 (0x2U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */
7986#define FMC_SDTR2_TMRD_2 (0x4U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */
7987#define FMC_SDTR2_TMRD_3 (0x8U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */
7988
7989#define FMC_SDTR2_TXSR_Pos (4U)
7990#define FMC_SDTR2_TXSR_Msk (0xFU << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */
7991#define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
7992#define FMC_SDTR2_TXSR_0 (0x1U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */
7993#define FMC_SDTR2_TXSR_1 (0x2U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */
7994#define FMC_SDTR2_TXSR_2 (0x4U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */
7995#define FMC_SDTR2_TXSR_3 (0x8U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */
7996
7997#define FMC_SDTR2_TRAS_Pos (8U)
7998#define FMC_SDTR2_TRAS_Msk (0xFU << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
7999#define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
8000#define FMC_SDTR2_TRAS_0 (0x1U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
8001#define FMC_SDTR2_TRAS_1 (0x2U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
8002#define FMC_SDTR2_TRAS_2 (0x4U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
8003#define FMC_SDTR2_TRAS_3 (0x8U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
8004
8005#define FMC_SDTR2_TRC_Pos (12U)
8006#define FMC_SDTR2_TRC_Msk (0xFU << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
8007#define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
8008#define FMC_SDTR2_TRC_0 (0x1U << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
8009#define FMC_SDTR2_TRC_1 (0x2U << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
8010#define FMC_SDTR2_TRC_2 (0x4U << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
8011
8012#define FMC_SDTR2_TWR_Pos (16U)
8013#define FMC_SDTR2_TWR_Msk (0xFU << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
8014#define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
8015#define FMC_SDTR2_TWR_0 (0x1U << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
8016#define FMC_SDTR2_TWR_1 (0x2U << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
8017#define FMC_SDTR2_TWR_2 (0x4U << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
8018
8019#define FMC_SDTR2_TRP_Pos (20U)
8020#define FMC_SDTR2_TRP_Msk (0xFU << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */
8021#define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
8022#define FMC_SDTR2_TRP_0 (0x1U << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */
8023#define FMC_SDTR2_TRP_1 (0x2U << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */
8024#define FMC_SDTR2_TRP_2 (0x4U << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */
8025
8026#define FMC_SDTR2_TRCD_Pos (24U)
8027#define FMC_SDTR2_TRCD_Msk (0xFU << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */
8028#define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
8029#define FMC_SDTR2_TRCD_0 (0x1U << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */
8030#define FMC_SDTR2_TRCD_1 (0x2U << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */
8031#define FMC_SDTR2_TRCD_2 (0x4U << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */
8032
8033/****************** Bit definition for FMC_SDCMR register ******************/
8034#define FMC_SDCMR_MODE_Pos (0U)
8035#define FMC_SDCMR_MODE_Msk (0x7U << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
8036#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
8037#define FMC_SDCMR_MODE_0 (0x1U << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
8038#define FMC_SDCMR_MODE_1 (0x2U << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
8039#define FMC_SDCMR_MODE_2 (0x4U << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
8040
8041#define FMC_SDCMR_CTB2_Pos (3U)
8042#define FMC_SDCMR_CTB2_Msk (0x1U << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
8043#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
8044
8045#define FMC_SDCMR_CTB1_Pos (4U)
8046#define FMC_SDCMR_CTB1_Msk (0x1U << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
8047#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
8048
8049#define FMC_SDCMR_NRFS_Pos (5U)
8050#define FMC_SDCMR_NRFS_Msk (0xFU << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
8051#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
8052#define FMC_SDCMR_NRFS_0 (0x1U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
8053#define FMC_SDCMR_NRFS_1 (0x2U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
8054#define FMC_SDCMR_NRFS_2 (0x4U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
8055#define FMC_SDCMR_NRFS_3 (0x8U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
8056
8057#define FMC_SDCMR_MRD_Pos (9U)
8058#define FMC_SDCMR_MRD_Msk (0x1FFFU << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
8059#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
8060
8061/****************** Bit definition for FMC_SDRTR register ******************/
8062#define FMC_SDRTR_CRE_Pos (0U)
8063#define FMC_SDRTR_CRE_Msk (0x1U << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
8064#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
8065
8066#define FMC_SDRTR_COUNT_Pos (1U)
8067#define FMC_SDRTR_COUNT_Msk (0x1FFFU << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
8068#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
8069
8070#define FMC_SDRTR_REIE_Pos (14U)
8071#define FMC_SDRTR_REIE_Msk (0x1U << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
8072#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
8073
8074/****************** Bit definition for FMC_SDSR register ******************/
8075#define FMC_SDSR_RE_Pos (0U)
8076#define FMC_SDSR_RE_Msk (0x1U << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
8077#define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
8078
8079#define FMC_SDSR_MODES1_Pos (1U)
8080#define FMC_SDSR_MODES1_Msk (0x3U << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
8081#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
8082#define FMC_SDSR_MODES1_0 (0x1U << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
8083#define FMC_SDSR_MODES1_1 (0x2U << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
8084
8085#define FMC_SDSR_MODES2_Pos (3U)
8086#define FMC_SDSR_MODES2_Msk (0x3U << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
8087#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
8088#define FMC_SDSR_MODES2_0 (0x1U << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
8089#define FMC_SDSR_MODES2_1 (0x2U << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
8090#define FMC_SDSR_BUSY_Pos (5U)
8091#define FMC_SDSR_BUSY_Msk (0x1U << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */
8092#define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */
8093
8094/******************************************************************************/
8095/* */
8096/* General Purpose I/O */
8097/* */
8098/******************************************************************************/
8099/****************** Bits definition for GPIO_MODER register *****************/
8100#define GPIO_MODER_MODE0_Pos (0U)
8101#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
8102#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
8103#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
8104#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
8105#define GPIO_MODER_MODE1_Pos (2U)
8106#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
8107#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
8108#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
8109#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
8110#define GPIO_MODER_MODE2_Pos (4U)
8111#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
8112#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
8113#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
8114#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
8115#define GPIO_MODER_MODE3_Pos (6U)
8116#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
8117#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
8118#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
8119#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
8120#define GPIO_MODER_MODE4_Pos (8U)
8121#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
8122#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
8123#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
8124#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
8125#define GPIO_MODER_MODE5_Pos (10U)
8126#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
8127#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
8128#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
8129#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
8130#define GPIO_MODER_MODE6_Pos (12U)
8131#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
8132#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
8133#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
8134#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
8135#define GPIO_MODER_MODE7_Pos (14U)
8136#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
8137#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
8138#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
8139#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
8140#define GPIO_MODER_MODE8_Pos (16U)
8141#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
8142#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
8143#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
8144#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
8145#define GPIO_MODER_MODE9_Pos (18U)
8146#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
8147#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
8148#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
8149#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
8150#define GPIO_MODER_MODE10_Pos (20U)
8151#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
8152#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
8153#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
8154#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
8155#define GPIO_MODER_MODE11_Pos (22U)
8156#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
8157#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
8158#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
8159#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
8160#define GPIO_MODER_MODE12_Pos (24U)
8161#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
8162#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
8163#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
8164#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
8165#define GPIO_MODER_MODE13_Pos (26U)
8166#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
8167#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
8168#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
8169#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
8170#define GPIO_MODER_MODE14_Pos (28U)
8171#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
8172#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
8173#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
8174#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
8175#define GPIO_MODER_MODE15_Pos (30U)
8176#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
8177#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
8178#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
8179#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
8180
8181/* Legacy defines */
8182#define GPIO_MODER_MODER0_Pos (0U)
8183#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
8184#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
8185#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
8186#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
8187#define GPIO_MODER_MODER1_Pos (2U)
8188#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
8189#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
8190#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
8191#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
8192#define GPIO_MODER_MODER2_Pos (4U)
8193#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
8194#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
8195#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
8196#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
8197#define GPIO_MODER_MODER3_Pos (6U)
8198#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
8199#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
8200#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
8201#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
8202#define GPIO_MODER_MODER4_Pos (8U)
8203#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
8204#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
8205#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
8206#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
8207#define GPIO_MODER_MODER5_Pos (10U)
8208#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
8209#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
8210#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
8211#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
8212#define GPIO_MODER_MODER6_Pos (12U)
8213#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
8214#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
8215#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
8216#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
8217#define GPIO_MODER_MODER7_Pos (14U)
8218#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
8219#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
8220#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
8221#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
8222#define GPIO_MODER_MODER8_Pos (16U)
8223#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
8224#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
8225#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
8226#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
8227#define GPIO_MODER_MODER9_Pos (18U)
8228#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
8229#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
8230#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
8231#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
8232#define GPIO_MODER_MODER10_Pos (20U)
8233#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
8234#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
8235#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
8236#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
8237#define GPIO_MODER_MODER11_Pos (22U)
8238#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
8239#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
8240#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
8241#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
8242#define GPIO_MODER_MODER12_Pos (24U)
8243#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
8244#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
8245#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
8246#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
8247#define GPIO_MODER_MODER13_Pos (26U)
8248#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
8249#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
8250#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
8251#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
8252#define GPIO_MODER_MODER14_Pos (28U)
8253#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
8254#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
8255#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
8256#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
8257#define GPIO_MODER_MODER15_Pos (30U)
8258#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
8259#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
8260#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
8261#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
8262
8263/****************** Bits definition for GPIO_OTYPER register ****************/
8264#define GPIO_OTYPER_OT0_Pos (0U)
8265#define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
8266#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
8267#define GPIO_OTYPER_OT1_Pos (1U)
8268#define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
8269#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
8270#define GPIO_OTYPER_OT2_Pos (2U)
8271#define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
8272#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
8273#define GPIO_OTYPER_OT3_Pos (3U)
8274#define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
8275#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
8276#define GPIO_OTYPER_OT4_Pos (4U)
8277#define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
8278#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
8279#define GPIO_OTYPER_OT5_Pos (5U)
8280#define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
8281#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
8282#define GPIO_OTYPER_OT6_Pos (6U)
8283#define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
8284#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
8285#define GPIO_OTYPER_OT7_Pos (7U)
8286#define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
8287#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
8288#define GPIO_OTYPER_OT8_Pos (8U)
8289#define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
8290#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
8291#define GPIO_OTYPER_OT9_Pos (9U)
8292#define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
8293#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
8294#define GPIO_OTYPER_OT10_Pos (10U)
8295#define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
8296#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
8297#define GPIO_OTYPER_OT11_Pos (11U)
8298#define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
8299#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
8300#define GPIO_OTYPER_OT12_Pos (12U)
8301#define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
8302#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
8303#define GPIO_OTYPER_OT13_Pos (13U)
8304#define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
8305#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
8306#define GPIO_OTYPER_OT14_Pos (14U)
8307#define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
8308#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
8309#define GPIO_OTYPER_OT15_Pos (15U)
8310#define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
8311#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
8312
8313/* Legacy defines */
8314#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
8315#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
8316#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
8317#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
8318#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
8319#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
8320#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
8321#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
8322#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
8323#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
8324#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
8325#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
8326#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
8327#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
8328#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
8329#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
8330
8331/****************** Bits definition for GPIO_OSPEEDR register ***************/
8332#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
8333#define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
8334#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
8335#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
8336#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
8337#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
8338#define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
8339#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
8340#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
8341#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
8342#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
8343#define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
8344#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
8345#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
8346#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
8347#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
8348#define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
8349#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
8350#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
8351#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
8352#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
8353#define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
8354#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
8355#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
8356#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
8357#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
8358#define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
8359#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
8360#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
8361#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
8362#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
8363#define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
8364#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
8365#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
8366#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
8367#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
8368#define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
8369#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
8370#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
8371#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
8372#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
8373#define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
8374#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
8375#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
8376#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
8377#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
8378#define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
8379#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
8380#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
8381#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
8382#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
8383#define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
8384#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
8385#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
8386#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
8387#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
8388#define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
8389#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
8390#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
8391#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
8392#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
8393#define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
8394#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
8395#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
8396#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
8397#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
8398#define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
8399#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
8400#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
8401#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
8402#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
8403#define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
8404#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
8405#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
8406#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
8407#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
8408#define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
8409#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
8410#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
8411#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
8412
8413/* Legacy defines */
8414#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
8415#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
8416#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
8417#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
8418#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
8419#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
8420#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
8421#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
8422#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
8423#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
8424#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
8425#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
8426#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
8427#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
8428#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
8429#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
8430#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
8431#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
8432#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
8433#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
8434#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
8435#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
8436#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
8437#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
8438#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
8439#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
8440#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
8441#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
8442#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
8443#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
8444#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
8445#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
8446#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
8447#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
8448#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
8449#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
8450#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
8451#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
8452#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
8453#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
8454#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
8455#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
8456#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
8457#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
8458#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
8459#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
8460#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
8461#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
8462
8463/****************** Bits definition for GPIO_PUPDR register *****************/
8464#define GPIO_PUPDR_PUPD0_Pos (0U)
8465#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
8466#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
8467#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
8468#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
8469#define GPIO_PUPDR_PUPD1_Pos (2U)
8470#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
8471#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
8472#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
8473#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
8474#define GPIO_PUPDR_PUPD2_Pos (4U)
8475#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
8476#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
8477#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
8478#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
8479#define GPIO_PUPDR_PUPD3_Pos (6U)
8480#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
8481#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
8482#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
8483#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
8484#define GPIO_PUPDR_PUPD4_Pos (8U)
8485#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
8486#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
8487#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
8488#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
8489#define GPIO_PUPDR_PUPD5_Pos (10U)
8490#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
8491#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
8492#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
8493#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
8494#define GPIO_PUPDR_PUPD6_Pos (12U)
8495#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
8496#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
8497#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
8498#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
8499#define GPIO_PUPDR_PUPD7_Pos (14U)
8500#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
8501#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
8502#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
8503#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
8504#define GPIO_PUPDR_PUPD8_Pos (16U)
8505#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
8506#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
8507#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
8508#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
8509#define GPIO_PUPDR_PUPD9_Pos (18U)
8510#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
8511#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
8512#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
8513#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
8514#define GPIO_PUPDR_PUPD10_Pos (20U)
8515#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
8516#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
8517#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
8518#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
8519#define GPIO_PUPDR_PUPD11_Pos (22U)
8520#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
8521#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
8522#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
8523#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
8524#define GPIO_PUPDR_PUPD12_Pos (24U)
8525#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
8526#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
8527#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
8528#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
8529#define GPIO_PUPDR_PUPD13_Pos (26U)
8530#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
8531#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
8532#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
8533#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
8534#define GPIO_PUPDR_PUPD14_Pos (28U)
8535#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
8536#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
8537#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
8538#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
8539#define GPIO_PUPDR_PUPD15_Pos (30U)
8540#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
8541#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
8542#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
8543#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
8544
8545/* Legacy defines */
8546#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
8547#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
8548#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
8549#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
8550#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
8551#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
8552#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
8553#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
8554#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
8555#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
8556#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
8557#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
8558#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
8559#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
8560#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
8561#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
8562#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
8563#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
8564#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
8565#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
8566#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
8567#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
8568#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
8569#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
8570#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
8571#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
8572#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
8573#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
8574#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
8575#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
8576#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
8577#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
8578#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
8579#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
8580#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
8581#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
8582#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
8583#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
8584#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
8585#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
8586#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
8587#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
8588#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
8589#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
8590#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
8591#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
8592#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
8593#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
8594
8595/****************** Bits definition for GPIO_IDR register *******************/
8596#define GPIO_IDR_ID0_Pos (0U)
8597#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
8598#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
8599#define GPIO_IDR_ID1_Pos (1U)
8600#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
8601#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
8602#define GPIO_IDR_ID2_Pos (2U)
8603#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
8604#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
8605#define GPIO_IDR_ID3_Pos (3U)
8606#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
8607#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
8608#define GPIO_IDR_ID4_Pos (4U)
8609#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
8610#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
8611#define GPIO_IDR_ID5_Pos (5U)
8612#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
8613#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
8614#define GPIO_IDR_ID6_Pos (6U)
8615#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
8616#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
8617#define GPIO_IDR_ID7_Pos (7U)
8618#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
8619#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
8620#define GPIO_IDR_ID8_Pos (8U)
8621#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
8622#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
8623#define GPIO_IDR_ID9_Pos (9U)
8624#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
8625#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
8626#define GPIO_IDR_ID10_Pos (10U)
8627#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
8628#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
8629#define GPIO_IDR_ID11_Pos (11U)
8630#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
8631#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
8632#define GPIO_IDR_ID12_Pos (12U)
8633#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
8634#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
8635#define GPIO_IDR_ID13_Pos (13U)
8636#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
8637#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
8638#define GPIO_IDR_ID14_Pos (14U)
8639#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
8640#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
8641#define GPIO_IDR_ID15_Pos (15U)
8642#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
8643#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
8644
8645/* Legacy defines */
8646#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
8647#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
8648#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
8649#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
8650#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
8651#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
8652#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
8653#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
8654#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
8655#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
8656#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
8657#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
8658#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
8659#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
8660#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
8661#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
8662
8663/****************** Bits definition for GPIO_ODR register *******************/
8664#define GPIO_ODR_OD0_Pos (0U)
8665#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
8666#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
8667#define GPIO_ODR_OD1_Pos (1U)
8668#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
8669#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
8670#define GPIO_ODR_OD2_Pos (2U)
8671#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
8672#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
8673#define GPIO_ODR_OD3_Pos (3U)
8674#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
8675#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
8676#define GPIO_ODR_OD4_Pos (4U)
8677#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
8678#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
8679#define GPIO_ODR_OD5_Pos (5U)
8680#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
8681#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
8682#define GPIO_ODR_OD6_Pos (6U)
8683#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
8684#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
8685#define GPIO_ODR_OD7_Pos (7U)
8686#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
8687#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
8688#define GPIO_ODR_OD8_Pos (8U)
8689#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
8690#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
8691#define GPIO_ODR_OD9_Pos (9U)
8692#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
8693#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
8694#define GPIO_ODR_OD10_Pos (10U)
8695#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
8696#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
8697#define GPIO_ODR_OD11_Pos (11U)
8698#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
8699#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
8700#define GPIO_ODR_OD12_Pos (12U)
8701#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
8702#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
8703#define GPIO_ODR_OD13_Pos (13U)
8704#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
8705#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
8706#define GPIO_ODR_OD14_Pos (14U)
8707#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
8708#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
8709#define GPIO_ODR_OD15_Pos (15U)
8710#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
8711#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
8712/* Legacy defines */
8713#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
8714#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
8715#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
8716#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
8717#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
8718#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
8719#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
8720#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
8721#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
8722#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
8723#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
8724#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
8725#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
8726#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
8727#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
8728#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
8729
8730/****************** Bits definition for GPIO_BSRR register ******************/
8731#define GPIO_BSRR_BS0_Pos (0U)
8732#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
8733#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
8734#define GPIO_BSRR_BS1_Pos (1U)
8735#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
8736#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
8737#define GPIO_BSRR_BS2_Pos (2U)
8738#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
8739#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
8740#define GPIO_BSRR_BS3_Pos (3U)
8741#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
8742#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
8743#define GPIO_BSRR_BS4_Pos (4U)
8744#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
8745#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
8746#define GPIO_BSRR_BS5_Pos (5U)
8747#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
8748#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
8749#define GPIO_BSRR_BS6_Pos (6U)
8750#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
8751#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
8752#define GPIO_BSRR_BS7_Pos (7U)
8753#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
8754#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
8755#define GPIO_BSRR_BS8_Pos (8U)
8756#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
8757#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
8758#define GPIO_BSRR_BS9_Pos (9U)
8759#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
8760#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
8761#define GPIO_BSRR_BS10_Pos (10U)
8762#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
8763#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
8764#define GPIO_BSRR_BS11_Pos (11U)
8765#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
8766#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
8767#define GPIO_BSRR_BS12_Pos (12U)
8768#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
8769#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
8770#define GPIO_BSRR_BS13_Pos (13U)
8771#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
8772#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
8773#define GPIO_BSRR_BS14_Pos (14U)
8774#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
8775#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
8776#define GPIO_BSRR_BS15_Pos (15U)
8777#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
8778#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
8779#define GPIO_BSRR_BR0_Pos (16U)
8780#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
8781#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
8782#define GPIO_BSRR_BR1_Pos (17U)
8783#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
8784#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
8785#define GPIO_BSRR_BR2_Pos (18U)
8786#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
8787#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
8788#define GPIO_BSRR_BR3_Pos (19U)
8789#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
8790#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
8791#define GPIO_BSRR_BR4_Pos (20U)
8792#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
8793#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
8794#define GPIO_BSRR_BR5_Pos (21U)
8795#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
8796#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
8797#define GPIO_BSRR_BR6_Pos (22U)
8798#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
8799#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
8800#define GPIO_BSRR_BR7_Pos (23U)
8801#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
8802#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
8803#define GPIO_BSRR_BR8_Pos (24U)
8804#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
8805#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
8806#define GPIO_BSRR_BR9_Pos (25U)
8807#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
8808#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
8809#define GPIO_BSRR_BR10_Pos (26U)
8810#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
8811#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
8812#define GPIO_BSRR_BR11_Pos (27U)
8813#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
8814#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
8815#define GPIO_BSRR_BR12_Pos (28U)
8816#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
8817#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
8818#define GPIO_BSRR_BR13_Pos (29U)
8819#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
8820#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
8821#define GPIO_BSRR_BR14_Pos (30U)
8822#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
8823#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
8824#define GPIO_BSRR_BR15_Pos (31U)
8825#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
8826#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
8827
8828/* Legacy defines */
8829#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
8830#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
8831#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
8832#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
8833#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
8834#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
8835#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
8836#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
8837#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
8838#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
8839#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
8840#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
8841#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
8842#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
8843#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
8844#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
8845#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
8846#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
8847#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
8848#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
8849#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
8850#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
8851#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
8852#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
8853#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
8854#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
8855#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
8856#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
8857#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
8858#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
8859#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
8860#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
8861/****************** Bit definition for GPIO_LCKR register *********************/
8862#define GPIO_LCKR_LCK0_Pos (0U)
8863#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
8864#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
8865#define GPIO_LCKR_LCK1_Pos (1U)
8866#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
8867#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
8868#define GPIO_LCKR_LCK2_Pos (2U)
8869#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
8870#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
8871#define GPIO_LCKR_LCK3_Pos (3U)
8872#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
8873#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
8874#define GPIO_LCKR_LCK4_Pos (4U)
8875#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
8876#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
8877#define GPIO_LCKR_LCK5_Pos (5U)
8878#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
8879#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
8880#define GPIO_LCKR_LCK6_Pos (6U)
8881#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
8882#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
8883#define GPIO_LCKR_LCK7_Pos (7U)
8884#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
8885#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
8886#define GPIO_LCKR_LCK8_Pos (8U)
8887#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
8888#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
8889#define GPIO_LCKR_LCK9_Pos (9U)
8890#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
8891#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
8892#define GPIO_LCKR_LCK10_Pos (10U)
8893#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
8894#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
8895#define GPIO_LCKR_LCK11_Pos (11U)
8896#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
8897#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
8898#define GPIO_LCKR_LCK12_Pos (12U)
8899#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
8900#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
8901#define GPIO_LCKR_LCK13_Pos (13U)
8902#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
8903#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
8904#define GPIO_LCKR_LCK14_Pos (14U)
8905#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
8906#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
8907#define GPIO_LCKR_LCK15_Pos (15U)
8908#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
8909#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
8910#define GPIO_LCKR_LCKK_Pos (16U)
8911#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
8912#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
8913/****************** Bit definition for GPIO_AFRL register *********************/
8914#define GPIO_AFRL_AFSEL0_Pos (0U)
8915#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
8916#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
8917#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
8918#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
8919#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
8920#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
8921#define GPIO_AFRL_AFSEL1_Pos (4U)
8922#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
8923#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
8924#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
8925#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
8926#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
8927#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
8928#define GPIO_AFRL_AFSEL2_Pos (8U)
8929#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
8930#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
8931#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
8932#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
8933#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
8934#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
8935#define GPIO_AFRL_AFSEL3_Pos (12U)
8936#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
8937#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
8938#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
8939#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
8940#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
8941#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
8942#define GPIO_AFRL_AFSEL4_Pos (16U)
8943#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
8944#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
8945#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
8946#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
8947#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
8948#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
8949#define GPIO_AFRL_AFSEL5_Pos (20U)
8950#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
8951#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
8952#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
8953#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
8954#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
8955#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
8956#define GPIO_AFRL_AFSEL6_Pos (24U)
8957#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
8958#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
8959#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
8960#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
8961#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
8962#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
8963#define GPIO_AFRL_AFSEL7_Pos (28U)
8964#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
8965#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
8966#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
8967#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
8968#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
8969#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
8970
8971/* Legacy defines */
8972#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
8973#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
8974#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
8975#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
8976#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
8977#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
8978#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
8979#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
8980#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
8981#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
8982#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
8983#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
8984#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
8985#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
8986#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
8987#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
8988#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
8989#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
8990#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
8991#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
8992#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
8993#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
8994#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
8995#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
8996#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
8997#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
8998#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
8999#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
9000#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
9001#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
9002#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
9003#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
9004#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
9005#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
9006#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
9007#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
9008#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
9009#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
9010#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
9011#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
9012
9013/****************** Bit definition for GPIO_AFRH register *********************/
9014#define GPIO_AFRH_AFSEL8_Pos (0U)
9015#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
9016#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
9017#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
9018#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
9019#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
9020#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
9021#define GPIO_AFRH_AFSEL9_Pos (4U)
9022#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
9023#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
9024#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
9025#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
9026#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
9027#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
9028#define GPIO_AFRH_AFSEL10_Pos (8U)
9029#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
9030#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
9031#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
9032#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
9033#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
9034#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
9035#define GPIO_AFRH_AFSEL11_Pos (12U)
9036#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
9037#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
9038#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
9039#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
9040#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
9041#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
9042#define GPIO_AFRH_AFSEL12_Pos (16U)
9043#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
9044#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
9045#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
9046#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
9047#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
9048#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
9049#define GPIO_AFRH_AFSEL13_Pos (20U)
9050#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
9051#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
9052#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
9053#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
9054#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
9055#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
9056#define GPIO_AFRH_AFSEL14_Pos (24U)
9057#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
9058#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
9059#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
9060#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
9061#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
9062#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
9063#define GPIO_AFRH_AFSEL15_Pos (28U)
9064#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
9065#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
9066#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
9067#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
9068#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
9069#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
9070
9071/* Legacy defines */
9072#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
9073#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
9074#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
9075#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
9076#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
9077#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
9078#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
9079#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
9080#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
9081#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
9082#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
9083#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
9084#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
9085#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
9086#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
9087#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
9088#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
9089#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
9090#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
9091#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
9092#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
9093#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
9094#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
9095#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
9096#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
9097#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
9098#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
9099#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
9100#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
9101#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
9102#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
9103#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
9104#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
9105#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
9106#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
9107#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
9108#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
9109#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
9110#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
9111#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
9112
9113/****************** Bits definition for GPIO_BRR register ******************/
9114#define GPIO_BRR_BR0_Pos (0U)
9115#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
9116#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
9117#define GPIO_BRR_BR1_Pos (1U)
9118#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
9119#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
9120#define GPIO_BRR_BR2_Pos (2U)
9121#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
9122#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
9123#define GPIO_BRR_BR3_Pos (3U)
9124#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
9125#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
9126#define GPIO_BRR_BR4_Pos (4U)
9127#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
9128#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
9129#define GPIO_BRR_BR5_Pos (5U)
9130#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
9131#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
9132#define GPIO_BRR_BR6_Pos (6U)
9133#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
9134#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
9135#define GPIO_BRR_BR7_Pos (7U)
9136#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
9137#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
9138#define GPIO_BRR_BR8_Pos (8U)
9139#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
9140#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
9141#define GPIO_BRR_BR9_Pos (9U)
9142#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
9143#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
9144#define GPIO_BRR_BR10_Pos (10U)
9145#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
9146#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
9147#define GPIO_BRR_BR11_Pos (11U)
9148#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
9149#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
9150#define GPIO_BRR_BR12_Pos (12U)
9151#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
9152#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
9153#define GPIO_BRR_BR13_Pos (13U)
9154#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
9155#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
9156#define GPIO_BRR_BR14_Pos (14U)
9157#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
9158#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
9159#define GPIO_BRR_BR15_Pos (15U)
9160#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
9161#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
9162
9163
9164/******************************************************************************/
9165/* */
9166/* Inter-integrated Circuit Interface */
9167/* */
9168/******************************************************************************/
9169/******************* Bit definition for I2C_CR1 register ********************/
9170#define I2C_CR1_PE_Pos (0U)
9171#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
9172#define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
9173#define I2C_CR1_SMBUS_Pos (1U)
9174#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
9175#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
9176#define I2C_CR1_SMBTYPE_Pos (3U)
9177#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
9178#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
9179#define I2C_CR1_ENARP_Pos (4U)
9180#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
9181#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
9182#define I2C_CR1_ENPEC_Pos (5U)
9183#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
9184#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
9185#define I2C_CR1_ENGC_Pos (6U)
9186#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
9187#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
9188#define I2C_CR1_NOSTRETCH_Pos (7U)
9189#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
9190#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
9191#define I2C_CR1_START_Pos (8U)
9192#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
9193#define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
9194#define I2C_CR1_STOP_Pos (9U)
9195#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
9196#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
9197#define I2C_CR1_ACK_Pos (10U)
9198#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
9199#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
9200#define I2C_CR1_POS_Pos (11U)
9201#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
9202#define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
9203#define I2C_CR1_PEC_Pos (12U)
9204#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
9205#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
9206#define I2C_CR1_ALERT_Pos (13U)
9207#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
9208#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
9209#define I2C_CR1_SWRST_Pos (15U)
9210#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
9211#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
9212
9213/******************* Bit definition for I2C_CR2 register ********************/
9214#define I2C_CR2_FREQ_Pos (0U)
9215#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
9216#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
9217#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
9218#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
9219#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
9220#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
9221#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
9222#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
9223
9224#define I2C_CR2_ITERREN_Pos (8U)
9225#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
9226#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
9227#define I2C_CR2_ITEVTEN_Pos (9U)
9228#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
9229#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
9230#define I2C_CR2_ITBUFEN_Pos (10U)
9231#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
9232#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
9233#define I2C_CR2_DMAEN_Pos (11U)
9234#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
9235#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
9236#define I2C_CR2_LAST_Pos (12U)
9237#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
9238#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
9239
9240/******************* Bit definition for I2C_OAR1 register *******************/
9241#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
9242#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
9243
9244#define I2C_OAR1_ADD0_Pos (0U)
9245#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
9246#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
9247#define I2C_OAR1_ADD1_Pos (1U)
9248#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
9249#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
9250#define I2C_OAR1_ADD2_Pos (2U)
9251#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
9252#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
9253#define I2C_OAR1_ADD3_Pos (3U)
9254#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
9255#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
9256#define I2C_OAR1_ADD4_Pos (4U)
9257#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
9258#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
9259#define I2C_OAR1_ADD5_Pos (5U)
9260#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
9261#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
9262#define I2C_OAR1_ADD6_Pos (6U)
9263#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
9264#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
9265#define I2C_OAR1_ADD7_Pos (7U)
9266#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
9267#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
9268#define I2C_OAR1_ADD8_Pos (8U)
9269#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
9270#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
9271#define I2C_OAR1_ADD9_Pos (9U)
9272#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
9273#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
9274
9275#define I2C_OAR1_ADDMODE_Pos (15U)
9276#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
9277#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
9278
9279/******************* Bit definition for I2C_OAR2 register *******************/
9280#define I2C_OAR2_ENDUAL_Pos (0U)
9281#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
9282#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
9283#define I2C_OAR2_ADD2_Pos (1U)
9284#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
9285#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
9286
9287/******************** Bit definition for I2C_DR register ********************/
9288#define I2C_DR_DR_Pos (0U)
9289#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
9290#define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
9291
9292/******************* Bit definition for I2C_SR1 register ********************/
9293#define I2C_SR1_SB_Pos (0U)
9294#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
9295#define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
9296#define I2C_SR1_ADDR_Pos (1U)
9297#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
9298#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
9299#define I2C_SR1_BTF_Pos (2U)
9300#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
9301#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
9302#define I2C_SR1_ADD10_Pos (3U)
9303#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
9304#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
9305#define I2C_SR1_STOPF_Pos (4U)
9306#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
9307#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
9308#define I2C_SR1_RXNE_Pos (6U)
9309#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
9310#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
9311#define I2C_SR1_TXE_Pos (7U)
9312#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
9313#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
9314#define I2C_SR1_BERR_Pos (8U)
9315#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
9316#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
9317#define I2C_SR1_ARLO_Pos (9U)
9318#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
9319#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
9320#define I2C_SR1_AF_Pos (10U)
9321#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
9322#define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
9323#define I2C_SR1_OVR_Pos (11U)
9324#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
9325#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
9326#define I2C_SR1_PECERR_Pos (12U)
9327#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
9328#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
9329#define I2C_SR1_TIMEOUT_Pos (14U)
9330#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
9331#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
9332#define I2C_SR1_SMBALERT_Pos (15U)
9333#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
9334#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
9335
9336/******************* Bit definition for I2C_SR2 register ********************/
9337#define I2C_SR2_MSL_Pos (0U)
9338#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
9339#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
9340#define I2C_SR2_BUSY_Pos (1U)
9341#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
9342#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
9343#define I2C_SR2_TRA_Pos (2U)
9344#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
9345#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
9346#define I2C_SR2_GENCALL_Pos (4U)
9347#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
9348#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
9349#define I2C_SR2_SMBDEFAULT_Pos (5U)
9350#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
9351#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
9352#define I2C_SR2_SMBHOST_Pos (6U)
9353#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
9354#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
9355#define I2C_SR2_DUALF_Pos (7U)
9356#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
9357#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
9358#define I2C_SR2_PEC_Pos (8U)
9359#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
9360#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
9361
9362/******************* Bit definition for I2C_CCR register ********************/
9363#define I2C_CCR_CCR_Pos (0U)
9364#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
9365#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
9366#define I2C_CCR_DUTY_Pos (14U)
9367#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
9368#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
9369#define I2C_CCR_FS_Pos (15U)
9370#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
9371#define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
9372
9373/****************** Bit definition for I2C_TRISE register *******************/
9374#define I2C_TRISE_TRISE_Pos (0U)
9375#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
9376#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
9377
9378/****************** Bit definition for I2C_FLTR register *******************/
9379#define I2C_FLTR_DNF_Pos (0U)
9380#define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
9381#define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
9382#define I2C_FLTR_ANOFF_Pos (4U)
9383#define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
9384#define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
9385
9386/******************************************************************************/
9387/* */
9388/* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
9389/* */
9390/******************************************************************************/
9391/******************* Bit definition for I2C_CR1 register *******************/
9392#define FMPI2C_CR1_PE_Pos (0U)
9393#define FMPI2C_CR1_PE_Msk (0x1U << FMPI2C_CR1_PE_Pos) /*!< 0x00000001 */
9394#define FMPI2C_CR1_PE FMPI2C_CR1_PE_Msk /*!< Peripheral enable */
9395#define FMPI2C_CR1_TXIE_Pos (1U)
9396#define FMPI2C_CR1_TXIE_Msk (0x1U << FMPI2C_CR1_TXIE_Pos) /*!< 0x00000002 */
9397#define FMPI2C_CR1_TXIE FMPI2C_CR1_TXIE_Msk /*!< TX interrupt enable */
9398#define FMPI2C_CR1_RXIE_Pos (2U)
9399#define FMPI2C_CR1_RXIE_Msk (0x1U << FMPI2C_CR1_RXIE_Pos) /*!< 0x00000004 */
9400#define FMPI2C_CR1_RXIE FMPI2C_CR1_RXIE_Msk /*!< RX interrupt enable */
9401#define FMPI2C_CR1_ADDRIE_Pos (3U)
9402#define FMPI2C_CR1_ADDRIE_Msk (0x1U << FMPI2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
9403#define FMPI2C_CR1_ADDRIE FMPI2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
9404#define FMPI2C_CR1_NACKIE_Pos (4U)
9405#define FMPI2C_CR1_NACKIE_Msk (0x1U << FMPI2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
9406#define FMPI2C_CR1_NACKIE FMPI2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
9407#define FMPI2C_CR1_STOPIE_Pos (5U)
9408#define FMPI2C_CR1_STOPIE_Msk (0x1U << FMPI2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
9409#define FMPI2C_CR1_STOPIE FMPI2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
9410#define FMPI2C_CR1_TCIE_Pos (6U)
9411#define FMPI2C_CR1_TCIE_Msk (0x1U << FMPI2C_CR1_TCIE_Pos) /*!< 0x00000040 */
9412#define FMPI2C_CR1_TCIE FMPI2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
9413#define FMPI2C_CR1_ERRIE_Pos (7U)
9414#define FMPI2C_CR1_ERRIE_Msk (0x1U << FMPI2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
9415#define FMPI2C_CR1_ERRIE FMPI2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
9416#define FMPI2C_CR1_DFN_Pos (8U)
9417#define FMPI2C_CR1_DFN_Msk (0xFU << FMPI2C_CR1_DFN_Pos) /*!< 0x00000F00 */
9418#define FMPI2C_CR1_DFN FMPI2C_CR1_DFN_Msk /*!< Digital noise filter */
9419#define FMPI2C_CR1_ANFOFF_Pos (12U)
9420#define FMPI2C_CR1_ANFOFF_Msk (0x1U << FMPI2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
9421#define FMPI2C_CR1_ANFOFF FMPI2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
9422#define FMPI2C_CR1_TXDMAEN_Pos (14U)
9423#define FMPI2C_CR1_TXDMAEN_Msk (0x1U << FMPI2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
9424#define FMPI2C_CR1_TXDMAEN FMPI2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
9425#define FMPI2C_CR1_RXDMAEN_Pos (15U)
9426#define FMPI2C_CR1_RXDMAEN_Msk (0x1U << FMPI2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
9427#define FMPI2C_CR1_RXDMAEN FMPI2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
9428#define FMPI2C_CR1_SBC_Pos (16U)
9429#define FMPI2C_CR1_SBC_Msk (0x1U << FMPI2C_CR1_SBC_Pos) /*!< 0x00010000 */
9430#define FMPI2C_CR1_SBC FMPI2C_CR1_SBC_Msk /*!< Slave byte control */
9431#define FMPI2C_CR1_NOSTRETCH_Pos (17U)
9432#define FMPI2C_CR1_NOSTRETCH_Msk (0x1U << FMPI2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
9433#define FMPI2C_CR1_NOSTRETCH FMPI2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
9434#define FMPI2C_CR1_GCEN_Pos (19U)
9435#define FMPI2C_CR1_GCEN_Msk (0x1U << FMPI2C_CR1_GCEN_Pos) /*!< 0x00080000 */
9436#define FMPI2C_CR1_GCEN FMPI2C_CR1_GCEN_Msk /*!< General call enable */
9437#define FMPI2C_CR1_SMBHEN_Pos (20U)
9438#define FMPI2C_CR1_SMBHEN_Msk (0x1U << FMPI2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
9439#define FMPI2C_CR1_SMBHEN FMPI2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
9440#define FMPI2C_CR1_SMBDEN_Pos (21U)
9441#define FMPI2C_CR1_SMBDEN_Msk (0x1U << FMPI2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
9442#define FMPI2C_CR1_SMBDEN FMPI2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
9443#define FMPI2C_CR1_ALERTEN_Pos (22U)
9444#define FMPI2C_CR1_ALERTEN_Msk (0x1U << FMPI2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
9445#define FMPI2C_CR1_ALERTEN FMPI2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
9446#define FMPI2C_CR1_PECEN_Pos (23U)
9447#define FMPI2C_CR1_PECEN_Msk (0x1U << FMPI2C_CR1_PECEN_Pos) /*!< 0x00800000 */
9448#define FMPI2C_CR1_PECEN FMPI2C_CR1_PECEN_Msk /*!< PEC enable */
9449
9450/****************** Bit definition for I2C_CR2 register ********************/
9451#define FMPI2C_CR2_SADD_Pos (0U)
9452#define FMPI2C_CR2_SADD_Msk (0x3FFU << FMPI2C_CR2_SADD_Pos) /*!< 0x000003FF */
9453#define FMPI2C_CR2_SADD FMPI2C_CR2_SADD_Msk /*!< Slave address (master mode) */
9454#define FMPI2C_CR2_RD_WRN_Pos (10U)
9455#define FMPI2C_CR2_RD_WRN_Msk (0x1U << FMPI2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
9456#define FMPI2C_CR2_RD_WRN FMPI2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
9457#define FMPI2C_CR2_ADD10_Pos (11U)
9458#define FMPI2C_CR2_ADD10_Msk (0x1U << FMPI2C_CR2_ADD10_Pos) /*!< 0x00000800 */
9459#define FMPI2C_CR2_ADD10 FMPI2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
9460#define FMPI2C_CR2_HEAD10R_Pos (12U)
9461#define FMPI2C_CR2_HEAD10R_Msk (0x1U << FMPI2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
9462#define FMPI2C_CR2_HEAD10R FMPI2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
9463#define FMPI2C_CR2_START_Pos (13U)
9464#define FMPI2C_CR2_START_Msk (0x1U << FMPI2C_CR2_START_Pos) /*!< 0x00002000 */
9465#define FMPI2C_CR2_START FMPI2C_CR2_START_Msk /*!< START generation */
9466#define FMPI2C_CR2_STOP_Pos (14U)
9467#define FMPI2C_CR2_STOP_Msk (0x1U << FMPI2C_CR2_STOP_Pos) /*!< 0x00004000 */
9468#define FMPI2C_CR2_STOP FMPI2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
9469#define FMPI2C_CR2_NACK_Pos (15U)
9470#define FMPI2C_CR2_NACK_Msk (0x1U << FMPI2C_CR2_NACK_Pos) /*!< 0x00008000 */
9471#define FMPI2C_CR2_NACK FMPI2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
9472#define FMPI2C_CR2_NBYTES_Pos (16U)
9473#define FMPI2C_CR2_NBYTES_Msk (0xFFU << FMPI2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
9474#define FMPI2C_CR2_NBYTES FMPI2C_CR2_NBYTES_Msk /*!< Number of bytes */
9475#define FMPI2C_CR2_RELOAD_Pos (24U)
9476#define FMPI2C_CR2_RELOAD_Msk (0x1U << FMPI2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
9477#define FMPI2C_CR2_RELOAD FMPI2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
9478#define FMPI2C_CR2_AUTOEND_Pos (25U)
9479#define FMPI2C_CR2_AUTOEND_Msk (0x1U << FMPI2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
9480#define FMPI2C_CR2_AUTOEND FMPI2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
9481#define FMPI2C_CR2_PECBYTE_Pos (26U)
9482#define FMPI2C_CR2_PECBYTE_Msk (0x1U << FMPI2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
9483#define FMPI2C_CR2_PECBYTE FMPI2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
9484
9485/******************* Bit definition for I2C_OAR1 register ******************/
9486#define FMPI2C_OAR1_OA1_Pos (0U)
9487#define FMPI2C_OAR1_OA1_Msk (0x3FFU << FMPI2C_OAR1_OA1_Pos) /*!< 0x000003FF */
9488#define FMPI2C_OAR1_OA1 FMPI2C_OAR1_OA1_Msk /*!< Interface own address 1 */
9489#define FMPI2C_OAR1_OA1MODE_Pos (10U)
9490#define FMPI2C_OAR1_OA1MODE_Msk (0x1U << FMPI2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
9491#define FMPI2C_OAR1_OA1MODE FMPI2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
9492#define FMPI2C_OAR1_OA1EN_Pos (15U)
9493#define FMPI2C_OAR1_OA1EN_Msk (0x1U << FMPI2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
9494#define FMPI2C_OAR1_OA1EN FMPI2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
9495
9496/******************* Bit definition for I2C_OAR2 register ******************/
9497#define FMPI2C_OAR2_OA2_Pos (1U)
9498#define FMPI2C_OAR2_OA2_Msk (0x7FU << FMPI2C_OAR2_OA2_Pos) /*!< 0x000000FE */
9499#define FMPI2C_OAR2_OA2 FMPI2C_OAR2_OA2_Msk /*!< Interface own address 2 */
9500#define FMPI2C_OAR2_OA2MSK_Pos (8U)
9501#define FMPI2C_OAR2_OA2MSK_Msk (0x7U << FMPI2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
9502#define FMPI2C_OAR2_OA2MSK FMPI2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
9503#define FMPI2C_OAR2_OA2EN_Pos (15U)
9504#define FMPI2C_OAR2_OA2EN_Msk (0x1U << FMPI2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
9505#define FMPI2C_OAR2_OA2EN FMPI2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
9506
9507/******************* Bit definition for I2C_TIMINGR register *******************/
9508#define FMPI2C_TIMINGR_SCLL_Pos (0U)
9509#define FMPI2C_TIMINGR_SCLL_Msk (0xFFU << FMPI2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
9510#define FMPI2C_TIMINGR_SCLL FMPI2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
9511#define FMPI2C_TIMINGR_SCLH_Pos (8U)
9512#define FMPI2C_TIMINGR_SCLH_Msk (0xFFU << FMPI2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
9513#define FMPI2C_TIMINGR_SCLH FMPI2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
9514#define FMPI2C_TIMINGR_SDADEL_Pos (16U)
9515#define FMPI2C_TIMINGR_SDADEL_Msk (0xFU << FMPI2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
9516#define FMPI2C_TIMINGR_SDADEL FMPI2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
9517#define FMPI2C_TIMINGR_SCLDEL_Pos (20U)
9518#define FMPI2C_TIMINGR_SCLDEL_Msk (0xFU << FMPI2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
9519#define FMPI2C_TIMINGR_SCLDEL FMPI2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
9520#define FMPI2C_TIMINGR_PRESC_Pos (28U)
9521#define FMPI2C_TIMINGR_PRESC_Msk (0xFU << FMPI2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
9522#define FMPI2C_TIMINGR_PRESC FMPI2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
9523
9524/******************* Bit definition for I2C_TIMEOUTR register *******************/
9525#define FMPI2C_TIMEOUTR_TIMEOUTA_Pos (0U)
9526#define FMPI2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << FMPI2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
9527#define FMPI2C_TIMEOUTR_TIMEOUTA FMPI2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
9528#define FMPI2C_TIMEOUTR_TIDLE_Pos (12U)
9529#define FMPI2C_TIMEOUTR_TIDLE_Msk (0x1U << FMPI2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
9530#define FMPI2C_TIMEOUTR_TIDLE FMPI2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
9531#define FMPI2C_TIMEOUTR_TIMOUTEN_Pos (15U)
9532#define FMPI2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << FMPI2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
9533#define FMPI2C_TIMEOUTR_TIMOUTEN FMPI2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
9534#define FMPI2C_TIMEOUTR_TIMEOUTB_Pos (16U)
9535#define FMPI2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << FMPI2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
9536#define FMPI2C_TIMEOUTR_TIMEOUTB FMPI2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
9537#define FMPI2C_TIMEOUTR_TEXTEN_Pos (31U)
9538#define FMPI2C_TIMEOUTR_TEXTEN_Msk (0x1U << FMPI2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
9539#define FMPI2C_TIMEOUTR_TEXTEN FMPI2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
9540
9541/****************** Bit definition for I2C_ISR register *********************/
9542#define FMPI2C_ISR_TXE_Pos (0U)
9543#define FMPI2C_ISR_TXE_Msk (0x1U << FMPI2C_ISR_TXE_Pos) /*!< 0x00000001 */
9544#define FMPI2C_ISR_TXE FMPI2C_ISR_TXE_Msk /*!< Transmit data register empty */
9545#define FMPI2C_ISR_TXIS_Pos (1U)
9546#define FMPI2C_ISR_TXIS_Msk (0x1U << FMPI2C_ISR_TXIS_Pos) /*!< 0x00000002 */
9547#define FMPI2C_ISR_TXIS FMPI2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
9548#define FMPI2C_ISR_RXNE_Pos (2U)
9549#define FMPI2C_ISR_RXNE_Msk (0x1U << FMPI2C_ISR_RXNE_Pos) /*!< 0x00000004 */
9550#define FMPI2C_ISR_RXNE FMPI2C_ISR_RXNE_Msk /*!< Receive data register not empty */
9551#define FMPI2C_ISR_ADDR_Pos (3U)
9552#define FMPI2C_ISR_ADDR_Msk (0x1U << FMPI2C_ISR_ADDR_Pos) /*!< 0x00000008 */
9553#define FMPI2C_ISR_ADDR FMPI2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
9554#define FMPI2C_ISR_NACKF_Pos (4U)
9555#define FMPI2C_ISR_NACKF_Msk (0x1U << FMPI2C_ISR_NACKF_Pos) /*!< 0x00000010 */
9556#define FMPI2C_ISR_NACKF FMPI2C_ISR_NACKF_Msk /*!< NACK received flag */
9557#define FMPI2C_ISR_STOPF_Pos (5U)
9558#define FMPI2C_ISR_STOPF_Msk (0x1U << FMPI2C_ISR_STOPF_Pos) /*!< 0x00000020 */
9559#define FMPI2C_ISR_STOPF FMPI2C_ISR_STOPF_Msk /*!< STOP detection flag */
9560#define FMPI2C_ISR_TC_Pos (6U)
9561#define FMPI2C_ISR_TC_Msk (0x1U << FMPI2C_ISR_TC_Pos) /*!< 0x00000040 */
9562#define FMPI2C_ISR_TC FMPI2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
9563#define FMPI2C_ISR_TCR_Pos (7U)
9564#define FMPI2C_ISR_TCR_Msk (0x1U << FMPI2C_ISR_TCR_Pos) /*!< 0x00000080 */
9565#define FMPI2C_ISR_TCR FMPI2C_ISR_TCR_Msk /*!< Transfer complete reload */
9566#define FMPI2C_ISR_BERR_Pos (8U)
9567#define FMPI2C_ISR_BERR_Msk (0x1U << FMPI2C_ISR_BERR_Pos) /*!< 0x00000100 */
9568#define FMPI2C_ISR_BERR FMPI2C_ISR_BERR_Msk /*!< Bus error */
9569#define FMPI2C_ISR_ARLO_Pos (9U)
9570#define FMPI2C_ISR_ARLO_Msk (0x1U << FMPI2C_ISR_ARLO_Pos) /*!< 0x00000200 */
9571#define FMPI2C_ISR_ARLO FMPI2C_ISR_ARLO_Msk /*!< Arbitration lost */
9572#define FMPI2C_ISR_OVR_Pos (10U)
9573#define FMPI2C_ISR_OVR_Msk (0x1U << FMPI2C_ISR_OVR_Pos) /*!< 0x00000400 */
9574#define FMPI2C_ISR_OVR FMPI2C_ISR_OVR_Msk /*!< Overrun/Underrun */
9575#define FMPI2C_ISR_PECERR_Pos (11U)
9576#define FMPI2C_ISR_PECERR_Msk (0x1U << FMPI2C_ISR_PECERR_Pos) /*!< 0x00000800 */
9577#define FMPI2C_ISR_PECERR FMPI2C_ISR_PECERR_Msk /*!< PEC error in reception */
9578#define FMPI2C_ISR_TIMEOUT_Pos (12U)
9579#define FMPI2C_ISR_TIMEOUT_Msk (0x1U << FMPI2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
9580#define FMPI2C_ISR_TIMEOUT FMPI2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
9581#define FMPI2C_ISR_ALERT_Pos (13U)
9582#define FMPI2C_ISR_ALERT_Msk (0x1U << FMPI2C_ISR_ALERT_Pos) /*!< 0x00002000 */
9583#define FMPI2C_ISR_ALERT FMPI2C_ISR_ALERT_Msk /*!< SMBus alert */
9584#define FMPI2C_ISR_BUSY_Pos (15U)
9585#define FMPI2C_ISR_BUSY_Msk (0x1U << FMPI2C_ISR_BUSY_Pos) /*!< 0x00008000 */
9586#define FMPI2C_ISR_BUSY FMPI2C_ISR_BUSY_Msk /*!< Bus busy */
9587#define FMPI2C_ISR_DIR_Pos (16U)
9588#define FMPI2C_ISR_DIR_Msk (0x1U << FMPI2C_ISR_DIR_Pos) /*!< 0x00010000 */
9589#define FMPI2C_ISR_DIR FMPI2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
9590#define FMPI2C_ISR_ADDCODE_Pos (17U)
9591#define FMPI2C_ISR_ADDCODE_Msk (0x7FU << FMPI2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
9592#define FMPI2C_ISR_ADDCODE FMPI2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
9593
9594/****************** Bit definition for I2C_ICR register *********************/
9595#define FMPI2C_ICR_ADDRCF_Pos (3U)
9596#define FMPI2C_ICR_ADDRCF_Msk (0x1U << FMPI2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
9597#define FMPI2C_ICR_ADDRCF FMPI2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
9598#define FMPI2C_ICR_NACKCF_Pos (4U)
9599#define FMPI2C_ICR_NACKCF_Msk (0x1U << FMPI2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
9600#define FMPI2C_ICR_NACKCF FMPI2C_ICR_NACKCF_Msk /*!< NACK clear flag */
9601#define FMPI2C_ICR_STOPCF_Pos (5U)
9602#define FMPI2C_ICR_STOPCF_Msk (0x1U << FMPI2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
9603#define FMPI2C_ICR_STOPCF FMPI2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
9604#define FMPI2C_ICR_BERRCF_Pos (8U)
9605#define FMPI2C_ICR_BERRCF_Msk (0x1U << FMPI2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
9606#define FMPI2C_ICR_BERRCF FMPI2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
9607#define FMPI2C_ICR_ARLOCF_Pos (9U)
9608#define FMPI2C_ICR_ARLOCF_Msk (0x1U << FMPI2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
9609#define FMPI2C_ICR_ARLOCF FMPI2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
9610#define FMPI2C_ICR_OVRCF_Pos (10U)
9611#define FMPI2C_ICR_OVRCF_Msk (0x1U << FMPI2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
9612#define FMPI2C_ICR_OVRCF FMPI2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
9613#define FMPI2C_ICR_PECCF_Pos (11U)
9614#define FMPI2C_ICR_PECCF_Msk (0x1U << FMPI2C_ICR_PECCF_Pos) /*!< 0x00000800 */
9615#define FMPI2C_ICR_PECCF FMPI2C_ICR_PECCF_Msk /*!< PAC error clear flag */
9616#define FMPI2C_ICR_TIMOUTCF_Pos (12U)
9617#define FMPI2C_ICR_TIMOUTCF_Msk (0x1U << FMPI2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
9618#define FMPI2C_ICR_TIMOUTCF FMPI2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
9619#define FMPI2C_ICR_ALERTCF_Pos (13U)
9620#define FMPI2C_ICR_ALERTCF_Msk (0x1U << FMPI2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
9621#define FMPI2C_ICR_ALERTCF FMPI2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
9622
9623/****************** Bit definition for I2C_PECR register *********************/
9624#define FMPI2C_PECR_PEC_Pos (0U)
9625#define FMPI2C_PECR_PEC_Msk (0xFFU << FMPI2C_PECR_PEC_Pos) /*!< 0x000000FF */
9626#define FMPI2C_PECR_PEC FMPI2C_PECR_PEC_Msk /*!< PEC register */
9627
9628/****************** Bit definition for I2C_RXDR register *********************/
9629#define FMPI2C_RXDR_RXDATA_Pos (0U)
9630#define FMPI2C_RXDR_RXDATA_Msk (0xFFU << FMPI2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
9631#define FMPI2C_RXDR_RXDATA FMPI2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
9632
9633/****************** Bit definition for I2C_TXDR register *********************/
9634#define FMPI2C_TXDR_TXDATA_Pos (0U)
9635#define FMPI2C_TXDR_TXDATA_Msk (0xFFU << FMPI2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
9636#define FMPI2C_TXDR_TXDATA FMPI2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
9637
9638
9639
9640/******************************************************************************/
9641/* */
9642/* Independent WATCHDOG */
9643/* */
9644/******************************************************************************/
9645/******************* Bit definition for IWDG_KR register ********************/
9646#define IWDG_KR_KEY_Pos (0U)
9647#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
9648#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
9649
9650/******************* Bit definition for IWDG_PR register ********************/
9651#define IWDG_PR_PR_Pos (0U)
9652#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
9653#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
9654#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
9655#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
9656#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
9657
9658/******************* Bit definition for IWDG_RLR register *******************/
9659#define IWDG_RLR_RL_Pos (0U)
9660#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
9661#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
9662
9663/******************* Bit definition for IWDG_SR register ********************/
9664#define IWDG_SR_PVU_Pos (0U)
9665#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
9666#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
9667#define IWDG_SR_RVU_Pos (1U)
9668#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
9669#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
9670
9671
9672
9673/******************************************************************************/
9674/* */
9675/* Power Control */
9676/* */
9677/******************************************************************************/
9678/******************** Bit definition for PWR_CR register ********************/
9679#define PWR_CR_LPDS_Pos (0U)
9680#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
9681#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
9682#define PWR_CR_PDDS_Pos (1U)
9683#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
9684#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
9685#define PWR_CR_CWUF_Pos (2U)
9686#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
9687#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
9688#define PWR_CR_CSBF_Pos (3U)
9689#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
9690#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
9691#define PWR_CR_PVDE_Pos (4U)
9692#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
9693#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
9694
9695#define PWR_CR_PLS_Pos (5U)
9696#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
9697#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
9698#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
9699#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
9700#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
9701
9702/*!< PVD level configuration */
9703#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
9704#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
9705#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
9706#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
9707#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
9708#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
9709#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
9710#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
9711#define PWR_CR_DBP_Pos (8U)
9712#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
9713#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
9714#define PWR_CR_FPDS_Pos (9U)
9715#define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
9716#define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
9717#define PWR_CR_LPLVDS_Pos (10U)
9718#define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
9719#define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
9720#define PWR_CR_MRLVDS_Pos (11U)
9721#define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
9722#define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main regulator Low Voltage Scaling in Stop mode */
9723#define PWR_CR_ADCDC1_Pos (13U)
9724#define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
9725#define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
9726#define PWR_CR_VOS_Pos (14U)
9727#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
9728#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
9729#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
9730#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
9731#define PWR_CR_ODEN_Pos (16U)
9732#define PWR_CR_ODEN_Msk (0x1U << PWR_CR_ODEN_Pos) /*!< 0x00010000 */
9733#define PWR_CR_ODEN PWR_CR_ODEN_Msk /*!< Over Drive enable */
9734#define PWR_CR_ODSWEN_Pos (17U)
9735#define PWR_CR_ODSWEN_Msk (0x1U << PWR_CR_ODSWEN_Pos) /*!< 0x00020000 */
9736#define PWR_CR_ODSWEN PWR_CR_ODSWEN_Msk /*!< Over Drive switch enabled */
9737#define PWR_CR_UDEN_Pos (18U)
9738#define PWR_CR_UDEN_Msk (0x3U << PWR_CR_UDEN_Pos) /*!< 0x000C0000 */
9739#define PWR_CR_UDEN PWR_CR_UDEN_Msk /*!< Under Drive enable in stop mode */
9740#define PWR_CR_UDEN_0 (0x1U << PWR_CR_UDEN_Pos) /*!< 0x00040000 */
9741#define PWR_CR_UDEN_1 (0x2U << PWR_CR_UDEN_Pos) /*!< 0x00080000 */
9742#define PWR_CR_FMSSR_Pos (20U)
9743#define PWR_CR_FMSSR_Msk (0x1U << PWR_CR_FMSSR_Pos) /*!< 0x00100000 */
9744#define PWR_CR_FMSSR PWR_CR_FMSSR_Msk /*!< Flash Memory Sleep System Run */
9745#define PWR_CR_FISSR_Pos (21U)
9746#define PWR_CR_FISSR_Msk (0x1U << PWR_CR_FISSR_Pos) /*!< 0x00200000 */
9747#define PWR_CR_FISSR PWR_CR_FISSR_Msk /*!< Flash Interface Stop while System Run */
9748
9749/* Legacy define */
9750#define PWR_CR_PMODE PWR_CR_VOS
9751#define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
9752#define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
9753
9754/******************* Bit definition for PWR_CSR register ********************/
9755#define PWR_CSR_WUF_Pos (0U)
9756#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
9757#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
9758#define PWR_CSR_SBF_Pos (1U)
9759#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
9760#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
9761#define PWR_CSR_PVDO_Pos (2U)
9762#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
9763#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
9764#define PWR_CSR_BRR_Pos (3U)
9765#define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
9766#define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
9767#define PWR_CSR_EWUP2_Pos (7U)
9768#define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000080 */
9769#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
9770#define PWR_CSR_EWUP1_Pos (8U)
9771#define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
9772#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
9773#define PWR_CSR_BRE_Pos (9U)
9774#define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
9775#define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
9776#define PWR_CSR_VOSRDY_Pos (14U)
9777#define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
9778#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
9779#define PWR_CSR_ODRDY_Pos (16U)
9780#define PWR_CSR_ODRDY_Msk (0x1U << PWR_CSR_ODRDY_Pos) /*!< 0x00010000 */
9781#define PWR_CSR_ODRDY PWR_CSR_ODRDY_Msk /*!< Over Drive generator ready */
9782#define PWR_CSR_ODSWRDY_Pos (17U)
9783#define PWR_CSR_ODSWRDY_Msk (0x1U << PWR_CSR_ODSWRDY_Pos) /*!< 0x00020000 */
9784#define PWR_CSR_ODSWRDY PWR_CSR_ODSWRDY_Msk /*!< Over Drive Switch ready */
9785#define PWR_CSR_UDRDY_Pos (18U)
9786#define PWR_CSR_UDRDY_Msk (0x3U << PWR_CSR_UDRDY_Pos) /*!< 0x000C0000 */
9787#define PWR_CSR_UDRDY PWR_CSR_UDRDY_Msk /*!< Under Drive ready */
9788/* Legacy define */
9789#define PWR_CSR_UDSWRDY PWR_CSR_UDRDY
9790
9791/* Legacy define */
9792#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
9793
9794/******************************************************************************/
9795/* */
9796/* QUADSPI */
9797/* */
9798/******************************************************************************/
9799/***************** Bit definition for QUADSPI_CR register *******************/
9800#define QUADSPI_CR_EN_Pos (0U)
9801#define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
9802#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
9803#define QUADSPI_CR_ABORT_Pos (1U)
9804#define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
9805#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
9806#define QUADSPI_CR_DMAEN_Pos (2U)
9807#define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
9808#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
9809#define QUADSPI_CR_TCEN_Pos (3U)
9810#define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
9811#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
9812#define QUADSPI_CR_SSHIFT_Pos (4U)
9813#define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
9814#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< SSHIFT Sample Shift */
9815#define QUADSPI_CR_DFM_Pos (6U)
9816#define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
9817#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
9818#define QUADSPI_CR_FSEL_Pos (7U)
9819#define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
9820#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
9821#define QUADSPI_CR_FTHRES_Pos (8U)
9822#define QUADSPI_CR_FTHRES_Msk (0x1FU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
9823#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
9824#define QUADSPI_CR_FTHRES_0 (0x01U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
9825#define QUADSPI_CR_FTHRES_1 (0x02U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
9826#define QUADSPI_CR_FTHRES_2 (0x04U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
9827#define QUADSPI_CR_FTHRES_3 (0x08U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
9828#define QUADSPI_CR_FTHRES_4 (0x10U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
9829#define QUADSPI_CR_TEIE_Pos (16U)
9830#define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
9831#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
9832#define QUADSPI_CR_TCIE_Pos (17U)
9833#define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
9834#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
9835#define QUADSPI_CR_FTIE_Pos (18U)
9836#define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
9837#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
9838#define QUADSPI_CR_SMIE_Pos (19U)
9839#define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
9840#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
9841#define QUADSPI_CR_TOIE_Pos (20U)
9842#define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
9843#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
9844#define QUADSPI_CR_APMS_Pos (22U)
9845#define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
9846#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
9847#define QUADSPI_CR_PMM_Pos (23U)
9848#define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
9849#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
9850#define QUADSPI_CR_PRESCALER_Pos (24U)
9851#define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
9852#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
9853#define QUADSPI_CR_PRESCALER_0 (0x01U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
9854#define QUADSPI_CR_PRESCALER_1 (0x02U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
9855#define QUADSPI_CR_PRESCALER_2 (0x04U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
9856#define QUADSPI_CR_PRESCALER_3 (0x08U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
9857#define QUADSPI_CR_PRESCALER_4 (0x10U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
9858#define QUADSPI_CR_PRESCALER_5 (0x20U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
9859#define QUADSPI_CR_PRESCALER_6 (0x40U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
9860#define QUADSPI_CR_PRESCALER_7 (0x80U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
9861
9862/***************** Bit definition for QUADSPI_DCR register ******************/
9863#define QUADSPI_DCR_CKMODE_Pos (0U)
9864#define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
9865#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
9866#define QUADSPI_DCR_CSHT_Pos (8U)
9867#define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
9868#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
9869#define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
9870#define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
9871#define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
9872#define QUADSPI_DCR_FSIZE_Pos (16U)
9873#define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
9874#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
9875#define QUADSPI_DCR_FSIZE_0 (0x01U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
9876#define QUADSPI_DCR_FSIZE_1 (0x02U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
9877#define QUADSPI_DCR_FSIZE_2 (0x04U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
9878#define QUADSPI_DCR_FSIZE_3 (0x08U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
9879#define QUADSPI_DCR_FSIZE_4 (0x10U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
9880
9881/****************** Bit definition for QUADSPI_SR register *******************/
9882#define QUADSPI_SR_TEF_Pos (0U)
9883#define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
9884#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
9885#define QUADSPI_SR_TCF_Pos (1U)
9886#define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
9887#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
9888#define QUADSPI_SR_FTF_Pos (2U)
9889#define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
9890#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
9891#define QUADSPI_SR_SMF_Pos (3U)
9892#define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
9893#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
9894#define QUADSPI_SR_TOF_Pos (4U)
9895#define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
9896#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
9897#define QUADSPI_SR_BUSY_Pos (5U)
9898#define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
9899#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
9900#define QUADSPI_SR_FLEVEL_Pos (8U)
9901#define QUADSPI_SR_FLEVEL_Msk (0x3FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
9902#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
9903#define QUADSPI_SR_FLEVEL_0 (0x01U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
9904#define QUADSPI_SR_FLEVEL_1 (0x02U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
9905#define QUADSPI_SR_FLEVEL_2 (0x04U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
9906#define QUADSPI_SR_FLEVEL_3 (0x08U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
9907#define QUADSPI_SR_FLEVEL_4 (0x10U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
9908#define QUADSPI_SR_FLEVEL_5 (0x20U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */
9909
9910/****************** Bit definition for QUADSPI_FCR register ******************/
9911#define QUADSPI_FCR_CTEF_Pos (0U)
9912#define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
9913#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
9914#define QUADSPI_FCR_CTCF_Pos (1U)
9915#define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
9916#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
9917#define QUADSPI_FCR_CSMF_Pos (3U)
9918#define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
9919#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
9920#define QUADSPI_FCR_CTOF_Pos (4U)
9921#define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
9922#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
9923
9924/****************** Bit definition for QUADSPI_DLR register ******************/
9925#define QUADSPI_DLR_DL_Pos (0U)
9926#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
9927#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
9928
9929/****************** Bit definition for QUADSPI_CCR register ******************/
9930#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
9931#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
9932#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
9933#define QUADSPI_CCR_INSTRUCTION_0 (0x01U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
9934#define QUADSPI_CCR_INSTRUCTION_1 (0x02U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
9935#define QUADSPI_CCR_INSTRUCTION_2 (0x04U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
9936#define QUADSPI_CCR_INSTRUCTION_3 (0x08U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
9937#define QUADSPI_CCR_INSTRUCTION_4 (0x10U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
9938#define QUADSPI_CCR_INSTRUCTION_5 (0x20U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
9939#define QUADSPI_CCR_INSTRUCTION_6 (0x40U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
9940#define QUADSPI_CCR_INSTRUCTION_7 (0x80U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
9941#define QUADSPI_CCR_IMODE_Pos (8U)
9942#define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
9943#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
9944#define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
9945#define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
9946#define QUADSPI_CCR_ADMODE_Pos (10U)
9947#define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
9948#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
9949#define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
9950#define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
9951#define QUADSPI_CCR_ADSIZE_Pos (12U)
9952#define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
9953#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
9954#define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
9955#define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
9956#define QUADSPI_CCR_ABMODE_Pos (14U)
9957#define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
9958#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
9959#define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
9960#define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
9961#define QUADSPI_CCR_ABSIZE_Pos (16U)
9962#define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
9963#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
9964#define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
9965#define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
9966#define QUADSPI_CCR_DCYC_Pos (18U)
9967#define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
9968#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
9969#define QUADSPI_CCR_DCYC_0 (0x01U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
9970#define QUADSPI_CCR_DCYC_1 (0x02U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
9971#define QUADSPI_CCR_DCYC_2 (0x04U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
9972#define QUADSPI_CCR_DCYC_3 (0x08U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
9973#define QUADSPI_CCR_DCYC_4 (0x10U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
9974#define QUADSPI_CCR_DMODE_Pos (24U)
9975#define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
9976#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
9977#define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
9978#define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
9979#define QUADSPI_CCR_FMODE_Pos (26U)
9980#define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
9981#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
9982#define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
9983#define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
9984#define QUADSPI_CCR_SIOO_Pos (28U)
9985#define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
9986#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
9987#define QUADSPI_CCR_DHHC_Pos (30U)
9988#define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
9989#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: Delay Half Hclk Cycle */
9990#define QUADSPI_CCR_DDRM_Pos (31U)
9991#define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
9992#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
9993/****************** Bit definition for QUADSPI_AR register *******************/
9994#define QUADSPI_AR_ADDRESS_Pos (0U)
9995#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
9996#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
9997
9998/****************** Bit definition for QUADSPI_ABR register ******************/
9999#define QUADSPI_ABR_ALTERNATE_Pos (0U)
10000#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
10001#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
10002
10003/****************** Bit definition for QUADSPI_DR register *******************/
10004#define QUADSPI_DR_DATA_Pos (0U)
10005#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
10006#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
10007
10008/****************** Bit definition for QUADSPI_PSMKR register ****************/
10009#define QUADSPI_PSMKR_MASK_Pos (0U)
10010#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
10011#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
10012
10013/****************** Bit definition for QUADSPI_PSMAR register ****************/
10014#define QUADSPI_PSMAR_MATCH_Pos (0U)
10015#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
10016#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
10017
10018/****************** Bit definition for QUADSPI_PIR register *****************/
10019#define QUADSPI_PIR_INTERVAL_Pos (0U)
10020#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
10021#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
10022
10023/****************** Bit definition for QUADSPI_LPTR register *****************/
10024#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
10025#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
10026#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
10027
10028/******************************************************************************/
10029/* */
10030/* Reset and Clock Control */
10031/* */
10032/******************************************************************************/
10033/******************** Bit definition for RCC_CR register ********************/
10034#define RCC_CR_HSION_Pos (0U)
10035#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
10036#define RCC_CR_HSION RCC_CR_HSION_Msk
10037#define RCC_CR_HSIRDY_Pos (1U)
10038#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
10039#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
10040
10041#define RCC_CR_HSITRIM_Pos (3U)
10042#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
10043#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
10044#define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
10045#define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
10046#define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
10047#define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
10048#define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
10049
10050#define RCC_CR_HSICAL_Pos (8U)
10051#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
10052#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
10053#define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
10054#define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
10055#define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
10056#define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
10057#define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
10058#define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
10059#define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
10060#define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
10061
10062#define RCC_CR_HSEON_Pos (16U)
10063#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
10064#define RCC_CR_HSEON RCC_CR_HSEON_Msk
10065#define RCC_CR_HSERDY_Pos (17U)
10066#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
10067#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
10068#define RCC_CR_HSEBYP_Pos (18U)
10069#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
10070#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
10071#define RCC_CR_CSSON_Pos (19U)
10072#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
10073#define RCC_CR_CSSON RCC_CR_CSSON_Msk
10074#define RCC_CR_PLLON_Pos (24U)
10075#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
10076#define RCC_CR_PLLON RCC_CR_PLLON_Msk
10077#define RCC_CR_PLLRDY_Pos (25U)
10078#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
10079#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
10080/*
10081 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10082 */
10083#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
10084
10085#define RCC_CR_PLLI2SON_Pos (26U)
10086#define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
10087#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
10088#define RCC_CR_PLLI2SRDY_Pos (27U)
10089#define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
10090#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
10091/*
10092 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10093 */
10094#define RCC_PLLSAI_SUPPORT /*!< Support PLLSAI oscillator */
10095
10096#define RCC_CR_PLLSAION_Pos (28U)
10097#define RCC_CR_PLLSAION_Msk (0x1U << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */
10098#define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
10099#define RCC_CR_PLLSAIRDY_Pos (29U)
10100#define RCC_CR_PLLSAIRDY_Msk (0x1U << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */
10101#define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
10102
10103/******************** Bit definition for RCC_PLLCFGR register ***************/
10104#define RCC_PLLCFGR_PLLM_Pos (0U)
10105#define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
10106#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
10107#define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
10108#define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
10109#define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
10110#define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
10111#define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
10112#define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
10113
10114#define RCC_PLLCFGR_PLLN_Pos (6U)
10115#define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
10116#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
10117#define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
10118#define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
10119#define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
10120#define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
10121#define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
10122#define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
10123#define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
10124#define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
10125#define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
10126
10127#define RCC_PLLCFGR_PLLP_Pos (16U)
10128#define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
10129#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
10130#define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
10131#define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
10132
10133#define RCC_PLLCFGR_PLLSRC_Pos (22U)
10134#define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
10135#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
10136#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
10137#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
10138#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
10139#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
10140
10141#define RCC_PLLCFGR_PLLQ_Pos (24U)
10142#define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
10143#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
10144#define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
10145#define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
10146#define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
10147#define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
10148/*
10149 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10150 */
10151#define RCC_PLLR_SYSCLK_SUPPORT /*!< Support PLLR as system clock */
10152#define RCC_PLLR_I2S_CLKSOURCE_SUPPORT /*!< Support PLLR clock as I2S clock source */
10153
10154#define RCC_PLLCFGR_PLLR_Pos (28U)
10155#define RCC_PLLCFGR_PLLR_Msk (0x7U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x70000000 */
10156#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
10157#define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x10000000 */
10158#define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
10159#define RCC_PLLCFGR_PLLR_2 (0x4U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
10160
10161/******************** Bit definition for RCC_CFGR register ******************/
10162/*!< SW configuration */
10163#define RCC_CFGR_SW_Pos (0U)
10164#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
10165#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
10166#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
10167#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
10168
10169#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
10170#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
10171#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
10172#define RCC_CFGR_SW_PLLR 0x00000003U /*!< PLL/PLLR selected as system clock */
10173
10174/*!< SWS configuration */
10175#define RCC_CFGR_SWS_Pos (2U)
10176#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
10177#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
10178#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
10179#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
10180
10181#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
10182#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
10183#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
10184#define RCC_CFGR_SWS_PLLR 0x0000000CU /*!< PLL/PLLR used as system clock */
10185
10186/*!< HPRE configuration */
10187#define RCC_CFGR_HPRE_Pos (4U)
10188#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
10189#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
10190#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
10191#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
10192#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
10193#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
10194
10195#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
10196#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
10197#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
10198#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
10199#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
10200#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
10201#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
10202#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
10203#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
10204
10205/*!< PPRE1 configuration */
10206#define RCC_CFGR_PPRE1_Pos (10U)
10207#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
10208#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
10209#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
10210#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
10211#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
10212
10213#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
10214#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
10215#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
10216#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
10217#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
10218
10219/*!< PPRE2 configuration */
10220#define RCC_CFGR_PPRE2_Pos (13U)
10221#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
10222#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
10223#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
10224#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
10225#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
10226
10227#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
10228#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
10229#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
10230#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
10231#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
10232
10233/*!< RTCPRE configuration */
10234#define RCC_CFGR_RTCPRE_Pos (16U)
10235#define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
10236#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
10237#define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
10238#define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
10239#define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
10240#define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
10241#define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
10242
10243/*!< MCO1 configuration */
10244#define RCC_CFGR_MCO1_Pos (21U)
10245#define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
10246#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
10247#define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
10248#define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
10249
10250
10251#define RCC_CFGR_MCO1PRE_Pos (24U)
10252#define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
10253#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
10254#define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
10255#define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
10256#define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
10257
10258#define RCC_CFGR_MCO2PRE_Pos (27U)
10259#define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
10260#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
10261#define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
10262#define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
10263#define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
10264
10265#define RCC_CFGR_MCO2_Pos (30U)
10266#define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
10267#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
10268#define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
10269#define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
10270
10271/******************** Bit definition for RCC_CIR register *******************/
10272#define RCC_CIR_LSIRDYF_Pos (0U)
10273#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
10274#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
10275#define RCC_CIR_LSERDYF_Pos (1U)
10276#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
10277#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
10278#define RCC_CIR_HSIRDYF_Pos (2U)
10279#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
10280#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
10281#define RCC_CIR_HSERDYF_Pos (3U)
10282#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
10283#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
10284#define RCC_CIR_PLLRDYF_Pos (4U)
10285#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
10286#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
10287#define RCC_CIR_PLLI2SRDYF_Pos (5U)
10288#define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
10289#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
10290
10291#define RCC_CIR_PLLSAIRDYF_Pos (6U)
10292#define RCC_CIR_PLLSAIRDYF_Msk (0x1U << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */
10293#define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
10294#define RCC_CIR_CSSF_Pos (7U)
10295#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
10296#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
10297#define RCC_CIR_LSIRDYIE_Pos (8U)
10298#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
10299#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
10300#define RCC_CIR_LSERDYIE_Pos (9U)
10301#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
10302#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
10303#define RCC_CIR_HSIRDYIE_Pos (10U)
10304#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
10305#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
10306#define RCC_CIR_HSERDYIE_Pos (11U)
10307#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
10308#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
10309#define RCC_CIR_PLLRDYIE_Pos (12U)
10310#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
10311#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
10312#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
10313#define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
10314#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
10315
10316#define RCC_CIR_PLLSAIRDYIE_Pos (14U)
10317#define RCC_CIR_PLLSAIRDYIE_Msk (0x1U << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */
10318#define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
10319#define RCC_CIR_LSIRDYC_Pos (16U)
10320#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
10321#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
10322#define RCC_CIR_LSERDYC_Pos (17U)
10323#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
10324#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
10325#define RCC_CIR_HSIRDYC_Pos (18U)
10326#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
10327#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
10328#define RCC_CIR_HSERDYC_Pos (19U)
10329#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
10330#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
10331#define RCC_CIR_PLLRDYC_Pos (20U)
10332#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
10333#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
10334#define RCC_CIR_PLLI2SRDYC_Pos (21U)
10335#define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
10336#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
10337#define RCC_CIR_PLLSAIRDYC_Pos (22U)
10338#define RCC_CIR_PLLSAIRDYC_Msk (0x1U << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */
10339#define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
10340
10341#define RCC_CIR_CSSC_Pos (23U)
10342#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
10343#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
10344
10345/******************** Bit definition for RCC_AHB1RSTR register **************/
10346#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
10347#define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
10348#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
10349#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
10350#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
10351#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
10352#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
10353#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
10354#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
10355#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
10356#define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
10357#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
10358#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
10359#define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
10360#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
10361#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
10362#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
10363#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
10364#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
10365#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
10366#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
10367#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
10368#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
10369#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
10370#define RCC_AHB1RSTR_CRCRST_Pos (12U)
10371#define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
10372#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
10373#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
10374#define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
10375#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
10376#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
10377#define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
10378#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
10379#define RCC_AHB1RSTR_OTGHRST_Pos (29U)
10380#define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
10381#define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
10382
10383/******************** Bit definition for RCC_AHB2RSTR register **************/
10384#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
10385#define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
10386#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
10387#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
10388#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
10389#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
10390/******************** Bit definition for RCC_AHB3RSTR register **************/
10391#define RCC_AHB3RSTR_FMCRST_Pos (0U)
10392#define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
10393#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
10394#define RCC_AHB3RSTR_QSPIRST_Pos (1U)
10395#define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000002 */
10396#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
10397
10398
10399/******************** Bit definition for RCC_APB1RSTR register **************/
10400#define RCC_APB1RSTR_TIM2RST_Pos (0U)
10401#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
10402#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
10403#define RCC_APB1RSTR_TIM3RST_Pos (1U)
10404#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
10405#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
10406#define RCC_APB1RSTR_TIM4RST_Pos (2U)
10407#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
10408#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
10409#define RCC_APB1RSTR_TIM5RST_Pos (3U)
10410#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
10411#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
10412#define RCC_APB1RSTR_TIM6RST_Pos (4U)
10413#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
10414#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
10415#define RCC_APB1RSTR_TIM7RST_Pos (5U)
10416#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
10417#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
10418#define RCC_APB1RSTR_TIM12RST_Pos (6U)
10419#define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
10420#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
10421#define RCC_APB1RSTR_TIM13RST_Pos (7U)
10422#define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
10423#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
10424#define RCC_APB1RSTR_TIM14RST_Pos (8U)
10425#define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
10426#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
10427#define RCC_APB1RSTR_WWDGRST_Pos (11U)
10428#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
10429#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
10430#define RCC_APB1RSTR_SPI2RST_Pos (14U)
10431#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
10432#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
10433#define RCC_APB1RSTR_SPI3RST_Pos (15U)
10434#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
10435#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
10436#define RCC_APB1RSTR_SPDIFRXRST_Pos (16U)
10437#define RCC_APB1RSTR_SPDIFRXRST_Msk (0x1U << RCC_APB1RSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */
10438#define RCC_APB1RSTR_SPDIFRXRST RCC_APB1RSTR_SPDIFRXRST_Msk
10439#define RCC_APB1RSTR_USART2RST_Pos (17U)
10440#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
10441#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
10442#define RCC_APB1RSTR_USART3RST_Pos (18U)
10443#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
10444#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
10445#define RCC_APB1RSTR_UART4RST_Pos (19U)
10446#define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
10447#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
10448#define RCC_APB1RSTR_UART5RST_Pos (20U)
10449#define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
10450#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
10451#define RCC_APB1RSTR_I2C1RST_Pos (21U)
10452#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
10453#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
10454#define RCC_APB1RSTR_I2C2RST_Pos (22U)
10455#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
10456#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
10457#define RCC_APB1RSTR_I2C3RST_Pos (23U)
10458#define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
10459#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
10460#define RCC_APB1RSTR_FMPI2C1RST_Pos (24U)
10461#define RCC_APB1RSTR_FMPI2C1RST_Msk (0x1U << RCC_APB1RSTR_FMPI2C1RST_Pos) /*!< 0x01000000 */
10462#define RCC_APB1RSTR_FMPI2C1RST RCC_APB1RSTR_FMPI2C1RST_Msk
10463#define RCC_APB1RSTR_CAN1RST_Pos (25U)
10464#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
10465#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
10466#define RCC_APB1RSTR_CAN2RST_Pos (26U)
10467#define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
10468#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
10469#define RCC_APB1RSTR_CECRST_Pos (27U)
10470#define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) /*!< 0x08000000 */
10471#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk
10472#define RCC_APB1RSTR_PWRRST_Pos (28U)
10473#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
10474#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
10475#define RCC_APB1RSTR_DACRST_Pos (29U)
10476#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
10477#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
10478
10479/******************** Bit definition for RCC_APB2RSTR register **************/
10480#define RCC_APB2RSTR_TIM1RST_Pos (0U)
10481#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
10482#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
10483#define RCC_APB2RSTR_TIM8RST_Pos (1U)
10484#define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
10485#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
10486#define RCC_APB2RSTR_USART1RST_Pos (4U)
10487#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
10488#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
10489#define RCC_APB2RSTR_USART6RST_Pos (5U)
10490#define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
10491#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
10492#define RCC_APB2RSTR_ADCRST_Pos (8U)
10493#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
10494#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
10495#define RCC_APB2RSTR_SDIORST_Pos (11U)
10496#define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
10497#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
10498#define RCC_APB2RSTR_SPI1RST_Pos (12U)
10499#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
10500#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
10501#define RCC_APB2RSTR_SPI4RST_Pos (13U)
10502#define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
10503#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
10504#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
10505#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
10506#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
10507#define RCC_APB2RSTR_TIM9RST_Pos (16U)
10508#define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
10509#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
10510#define RCC_APB2RSTR_TIM10RST_Pos (17U)
10511#define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
10512#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
10513#define RCC_APB2RSTR_TIM11RST_Pos (18U)
10514#define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
10515#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
10516#define RCC_APB2RSTR_SAI1RST_Pos (22U)
10517#define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
10518#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
10519#define RCC_APB2RSTR_SAI2RST_Pos (23U)
10520#define RCC_APB2RSTR_SAI2RST_Msk (0x1U << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */
10521#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
10522
10523/* Old SPI1RST bit definition, maintained for legacy purpose */
10524#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
10525
10526/******************** Bit definition for RCC_AHB1ENR register ***************/
10527#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
10528#define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
10529#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
10530#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
10531#define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
10532#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
10533#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
10534#define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
10535#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
10536#define RCC_AHB1ENR_GPIODEN_Pos (3U)
10537#define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
10538#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
10539#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
10540#define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
10541#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
10542#define RCC_AHB1ENR_GPIOFEN_Pos (5U)
10543#define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
10544#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
10545#define RCC_AHB1ENR_GPIOGEN_Pos (6U)
10546#define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
10547#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
10548#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
10549#define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
10550#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
10551#define RCC_AHB1ENR_CRCEN_Pos (12U)
10552#define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
10553#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
10554#define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
10555#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
10556#define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
10557#define RCC_AHB1ENR_DMA1EN_Pos (21U)
10558#define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
10559#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
10560#define RCC_AHB1ENR_DMA2EN_Pos (22U)
10561#define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
10562#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
10563#define RCC_AHB1ENR_OTGHSEN_Pos (29U)
10564#define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
10565#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
10566#define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
10567#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
10568#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
10569/******************** Bit definition for RCC_AHB2ENR register ***************/
10570/*
10571 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10572 */
10573#define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
10574
10575#define RCC_AHB2ENR_DCMIEN_Pos (0U)
10576#define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
10577#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
10578#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
10579#define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
10580#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
10581
10582/******************** Bit definition for RCC_AHB3ENR register ***************/
10583/*
10584 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10585 */
10586#define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
10587
10588#define RCC_AHB3ENR_FMCEN_Pos (0U)
10589#define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
10590#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
10591#define RCC_AHB3ENR_QSPIEN_Pos (1U)
10592#define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000002 */
10593#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
10594
10595/******************** Bit definition for RCC_APB1ENR register ***************/
10596#define RCC_APB1ENR_TIM2EN_Pos (0U)
10597#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
10598#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
10599#define RCC_APB1ENR_TIM3EN_Pos (1U)
10600#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
10601#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
10602#define RCC_APB1ENR_TIM4EN_Pos (2U)
10603#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
10604#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
10605#define RCC_APB1ENR_TIM5EN_Pos (3U)
10606#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
10607#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
10608#define RCC_APB1ENR_TIM6EN_Pos (4U)
10609#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
10610#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
10611#define RCC_APB1ENR_TIM7EN_Pos (5U)
10612#define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
10613#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
10614#define RCC_APB1ENR_TIM12EN_Pos (6U)
10615#define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
10616#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
10617#define RCC_APB1ENR_TIM13EN_Pos (7U)
10618#define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
10619#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
10620#define RCC_APB1ENR_TIM14EN_Pos (8U)
10621#define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
10622#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
10623#define RCC_APB1ENR_WWDGEN_Pos (11U)
10624#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
10625#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
10626#define RCC_APB1ENR_SPI2EN_Pos (14U)
10627#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
10628#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
10629#define RCC_APB1ENR_SPI3EN_Pos (15U)
10630#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
10631#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
10632#define RCC_APB1ENR_SPDIFRXEN_Pos (16U)
10633#define RCC_APB1ENR_SPDIFRXEN_Msk (0x1U << RCC_APB1ENR_SPDIFRXEN_Pos) /*!< 0x00010000 */
10634#define RCC_APB1ENR_SPDIFRXEN RCC_APB1ENR_SPDIFRXEN_Msk
10635#define RCC_APB1ENR_USART2EN_Pos (17U)
10636#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
10637#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
10638#define RCC_APB1ENR_USART3EN_Pos (18U)
10639#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
10640#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
10641#define RCC_APB1ENR_UART4EN_Pos (19U)
10642#define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
10643#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
10644#define RCC_APB1ENR_UART5EN_Pos (20U)
10645#define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
10646#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
10647#define RCC_APB1ENR_I2C1EN_Pos (21U)
10648#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
10649#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
10650#define RCC_APB1ENR_I2C2EN_Pos (22U)
10651#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
10652#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
10653#define RCC_APB1ENR_I2C3EN_Pos (23U)
10654#define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
10655#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
10656#define RCC_APB1ENR_FMPI2C1EN_Pos (24U)
10657#define RCC_APB1ENR_FMPI2C1EN_Msk (0x1U << RCC_APB1ENR_FMPI2C1EN_Pos) /*!< 0x01000000 */
10658#define RCC_APB1ENR_FMPI2C1EN RCC_APB1ENR_FMPI2C1EN_Msk
10659#define RCC_APB1ENR_CAN1EN_Pos (25U)
10660#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
10661#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
10662#define RCC_APB1ENR_CAN2EN_Pos (26U)
10663#define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
10664#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
10665#define RCC_APB1ENR_CECEN_Pos (27U)
10666#define RCC_APB1ENR_CECEN_Msk (0x1U << RCC_APB1ENR_CECEN_Pos) /*!< 0x08000000 */
10667#define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk
10668#define RCC_APB1ENR_PWREN_Pos (28U)
10669#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
10670#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
10671#define RCC_APB1ENR_DACEN_Pos (29U)
10672#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
10673#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
10674
10675/******************** Bit definition for RCC_APB2ENR register ***************/
10676#define RCC_APB2ENR_TIM1EN_Pos (0U)
10677#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
10678#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
10679#define RCC_APB2ENR_TIM8EN_Pos (1U)
10680#define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
10681#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
10682#define RCC_APB2ENR_USART1EN_Pos (4U)
10683#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
10684#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
10685#define RCC_APB2ENR_USART6EN_Pos (5U)
10686#define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
10687#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
10688#define RCC_APB2ENR_ADC1EN_Pos (8U)
10689#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
10690#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
10691#define RCC_APB2ENR_ADC2EN_Pos (9U)
10692#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
10693#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
10694#define RCC_APB2ENR_ADC3EN_Pos (10U)
10695#define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
10696#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
10697#define RCC_APB2ENR_SDIOEN_Pos (11U)
10698#define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
10699#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
10700#define RCC_APB2ENR_SPI1EN_Pos (12U)
10701#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
10702#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
10703#define RCC_APB2ENR_SPI4EN_Pos (13U)
10704#define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
10705#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
10706#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
10707#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
10708#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
10709#define RCC_APB2ENR_TIM9EN_Pos (16U)
10710#define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
10711#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
10712#define RCC_APB2ENR_TIM10EN_Pos (17U)
10713#define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
10714#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
10715#define RCC_APB2ENR_TIM11EN_Pos (18U)
10716#define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
10717#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
10718#define RCC_APB2ENR_SAI1EN_Pos (22U)
10719#define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
10720#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
10721#define RCC_APB2ENR_SAI2EN_Pos (23U)
10722#define RCC_APB2ENR_SAI2EN_Msk (0x1U << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */
10723#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
10724
10725/******************** Bit definition for RCC_AHB1LPENR register *************/
10726#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
10727#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
10728#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
10729#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
10730#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
10731#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
10732#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
10733#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
10734#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
10735#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
10736#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
10737#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
10738#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
10739#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
10740#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
10741#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
10742#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
10743#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
10744#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
10745#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
10746#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
10747#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
10748#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
10749#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
10750#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
10751#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
10752#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
10753#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
10754#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
10755#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
10756#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
10757#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
10758#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
10759#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
10760#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
10761#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
10762#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
10763#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
10764#define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
10765#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
10766#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
10767#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
10768#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
10769#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
10770#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
10771
10772#define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
10773#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
10774#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
10775#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
10776#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
10777#define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
10778
10779/******************** Bit definition for RCC_AHB2LPENR register *************/
10780#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
10781#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
10782#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
10783#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
10784#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
10785#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
10786
10787/******************** Bit definition for RCC_AHB3LPENR register *************/
10788#define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
10789#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
10790#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
10791#define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
10792#define RCC_AHB3LPENR_QSPILPEN_Msk (0x1U << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */
10793#define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
10794
10795/******************** Bit definition for RCC_APB1LPENR register *************/
10796#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
10797#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
10798#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
10799#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
10800#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
10801#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
10802#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
10803#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
10804#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
10805#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
10806#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
10807#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
10808#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
10809#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
10810#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
10811#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
10812#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
10813#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
10814#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
10815#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
10816#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
10817#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
10818#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
10819#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
10820#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
10821#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
10822#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
10823#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
10824#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
10825#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
10826#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
10827#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
10828#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
10829#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
10830#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
10831#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
10832#define RCC_APB1LPENR_SPDIFRXLPEN_Pos (16U)
10833#define RCC_APB1LPENR_SPDIFRXLPEN_Msk (0x1U << RCC_APB1LPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */
10834#define RCC_APB1LPENR_SPDIFRXLPEN RCC_APB1LPENR_SPDIFRXLPEN_Msk
10835#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
10836#define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
10837#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
10838#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
10839#define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
10840#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
10841#define RCC_APB1LPENR_UART4LPEN_Pos (19U)
10842#define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
10843#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
10844#define RCC_APB1LPENR_UART5LPEN_Pos (20U)
10845#define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
10846#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
10847#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
10848#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
10849#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
10850#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
10851#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
10852#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
10853#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
10854#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
10855#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
10856#define RCC_APB1LPENR_FMPI2C1LPEN_Pos (24U)
10857#define RCC_APB1LPENR_FMPI2C1LPEN_Msk (0x1U << RCC_APB1LPENR_FMPI2C1LPEN_Pos) /*!< 0x01000000 */
10858#define RCC_APB1LPENR_FMPI2C1LPEN RCC_APB1LPENR_FMPI2C1LPEN_Msk
10859#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
10860#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
10861#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
10862#define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
10863#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
10864#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
10865#define RCC_APB1LPENR_CECLPEN_Pos (27U)
10866#define RCC_APB1LPENR_CECLPEN_Msk (0x1U << RCC_APB1LPENR_CECLPEN_Pos) /*!< 0x08000000 */
10867#define RCC_APB1LPENR_CECLPEN RCC_APB1LPENR_CECLPEN_Msk
10868#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
10869#define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
10870#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
10871#define RCC_APB1LPENR_DACLPEN_Pos (29U)
10872#define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
10873#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
10874
10875/******************** Bit definition for RCC_APB2LPENR register *************/
10876#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
10877#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
10878#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
10879#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
10880#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
10881#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
10882#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
10883#define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
10884#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
10885#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
10886#define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
10887#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
10888#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
10889#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
10890#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
10891#define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
10892#define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
10893#define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
10894#define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
10895#define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
10896#define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
10897#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
10898#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
10899#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
10900#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
10901#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
10902#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
10903#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
10904#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
10905#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
10906#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
10907#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
10908#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
10909#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
10910#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
10911#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
10912#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
10913#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
10914#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
10915#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
10916#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
10917#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
10918#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
10919#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
10920#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
10921#define RCC_APB2LPENR_SAI2LPEN_Pos (23U)
10922#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1U << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */
10923#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk
10924
10925/******************** Bit definition for RCC_BDCR register ******************/
10926#define RCC_BDCR_LSEON_Pos (0U)
10927#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
10928#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
10929#define RCC_BDCR_LSERDY_Pos (1U)
10930#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
10931#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
10932#define RCC_BDCR_LSEBYP_Pos (2U)
10933#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
10934#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
10935#define RCC_BDCR_LSEMOD_Pos (3U)
10936#define RCC_BDCR_LSEMOD_Msk (0x1U << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */
10937#define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
10938
10939#define RCC_BDCR_RTCSEL_Pos (8U)
10940#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
10941#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
10942#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
10943#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
10944
10945#define RCC_BDCR_RTCEN_Pos (15U)
10946#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
10947#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
10948#define RCC_BDCR_BDRST_Pos (16U)
10949#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
10950#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
10951
10952/******************** Bit definition for RCC_CSR register *******************/
10953#define RCC_CSR_LSION_Pos (0U)
10954#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
10955#define RCC_CSR_LSION RCC_CSR_LSION_Msk
10956#define RCC_CSR_LSIRDY_Pos (1U)
10957#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
10958#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
10959#define RCC_CSR_RMVF_Pos (24U)
10960#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
10961#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
10962#define RCC_CSR_BORRSTF_Pos (25U)
10963#define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
10964#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
10965#define RCC_CSR_PINRSTF_Pos (26U)
10966#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
10967#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
10968#define RCC_CSR_PORRSTF_Pos (27U)
10969#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
10970#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
10971#define RCC_CSR_SFTRSTF_Pos (28U)
10972#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
10973#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
10974#define RCC_CSR_IWDGRSTF_Pos (29U)
10975#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
10976#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
10977#define RCC_CSR_WWDGRSTF_Pos (30U)
10978#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
10979#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
10980#define RCC_CSR_LPWRRSTF_Pos (31U)
10981#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
10982#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
10983/* Legacy defines */
10984#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
10985#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
10986
10987/******************** Bit definition for RCC_SSCGR register *****************/
10988#define RCC_SSCGR_MODPER_Pos (0U)
10989#define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
10990#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
10991#define RCC_SSCGR_INCSTEP_Pos (13U)
10992#define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
10993#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
10994#define RCC_SSCGR_SPREADSEL_Pos (30U)
10995#define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
10996#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
10997#define RCC_SSCGR_SSCGEN_Pos (31U)
10998#define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
10999#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
11000
11001/******************** Bit definition for RCC_PLLI2SCFGR register ************/
11002#define RCC_PLLI2SCFGR_PLLI2SM_Pos (0U)
11003#define RCC_PLLI2SCFGR_PLLI2SM_Msk (0x3FU << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x0000003F */
11004#define RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM_Msk
11005#define RCC_PLLI2SCFGR_PLLI2SM_0 (0x01U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000001 */
11006#define RCC_PLLI2SCFGR_PLLI2SM_1 (0x02U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000002 */
11007#define RCC_PLLI2SCFGR_PLLI2SM_2 (0x04U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000004 */
11008#define RCC_PLLI2SCFGR_PLLI2SM_3 (0x08U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000008 */
11009#define RCC_PLLI2SCFGR_PLLI2SM_4 (0x10U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000010 */
11010#define RCC_PLLI2SCFGR_PLLI2SM_5 (0x20U << RCC_PLLI2SCFGR_PLLI2SM_Pos) /*!< 0x00000020 */
11011
11012#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
11013#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
11014#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
11015#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
11016#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
11017#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
11018#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
11019#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
11020#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
11021#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
11022#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
11023#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
11024
11025#define RCC_PLLI2SCFGR_PLLI2SP_Pos (16U)
11026#define RCC_PLLI2SCFGR_PLLI2SP_Msk (0x3U << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00030000 */
11027#define RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP_Msk
11028#define RCC_PLLI2SCFGR_PLLI2SP_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00010000 */
11029#define RCC_PLLI2SCFGR_PLLI2SP_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SP_Pos) /*!< 0x00020000 */
11030#define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
11031#define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
11032#define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
11033#define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
11034#define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
11035#define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
11036#define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
11037#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
11038#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
11039#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
11040#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
11041#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
11042#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
11043
11044/******************** Bit definition for RCC_PLLSAICFGR register ************/
11045#define RCC_PLLSAICFGR_PLLSAIM_Pos (0U)
11046#define RCC_PLLSAICFGR_PLLSAIM_Msk (0x3FU << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x0000003F */
11047#define RCC_PLLSAICFGR_PLLSAIM RCC_PLLSAICFGR_PLLSAIM_Msk
11048#define RCC_PLLSAICFGR_PLLSAIM_0 (0x01U << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000001 */
11049#define RCC_PLLSAICFGR_PLLSAIM_1 (0x02U << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000002 */
11050#define RCC_PLLSAICFGR_PLLSAIM_2 (0x04U << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000004 */
11051#define RCC_PLLSAICFGR_PLLSAIM_3 (0x08U << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000008 */
11052#define RCC_PLLSAICFGR_PLLSAIM_4 (0x10U << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000010 */
11053#define RCC_PLLSAICFGR_PLLSAIM_5 (0x20U << RCC_PLLSAICFGR_PLLSAIM_Pos) /*!< 0x00000020 */
11054#define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
11055#define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
11056#define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
11057#define RCC_PLLSAICFGR_PLLSAIN_0 (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
11058#define RCC_PLLSAICFGR_PLLSAIN_1 (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
11059#define RCC_PLLSAICFGR_PLLSAIN_2 (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
11060#define RCC_PLLSAICFGR_PLLSAIN_3 (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
11061#define RCC_PLLSAICFGR_PLLSAIN_4 (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
11062#define RCC_PLLSAICFGR_PLLSAIN_5 (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
11063#define RCC_PLLSAICFGR_PLLSAIN_6 (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
11064#define RCC_PLLSAICFGR_PLLSAIN_7 (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
11065#define RCC_PLLSAICFGR_PLLSAIN_8 (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
11066
11067#define RCC_PLLSAICFGR_PLLSAIP_Pos (16U)
11068#define RCC_PLLSAICFGR_PLLSAIP_Msk (0x3U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00030000 */
11069#define RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP_Msk
11070#define RCC_PLLSAICFGR_PLLSAIP_0 (0x1U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00010000 */
11071#define RCC_PLLSAICFGR_PLLSAIP_1 (0x2U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00020000 */
11072
11073#define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
11074#define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
11075#define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
11076#define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
11077#define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
11078#define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
11079#define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
11080
11081
11082/******************** Bit definition for RCC_DCKCFGR register ***************/
11083#define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U)
11084#define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
11085#define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk
11086#define RCC_DCKCFGR_PLLI2SDIVQ_0 (0x01U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
11087#define RCC_DCKCFGR_PLLI2SDIVQ_1 (0x02U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
11088#define RCC_DCKCFGR_PLLI2SDIVQ_2 (0x04U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
11089#define RCC_DCKCFGR_PLLI2SDIVQ_3 (0x08U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
11090#define RCC_DCKCFGR_PLLI2SDIVQ_4 (0x10U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
11091
11092#define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U)
11093#define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
11094#define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk
11095#define RCC_DCKCFGR_PLLSAIDIVQ_0 (0x01U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
11096#define RCC_DCKCFGR_PLLSAIDIVQ_1 (0x02U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
11097#define RCC_DCKCFGR_PLLSAIDIVQ_2 (0x04U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
11098#define RCC_DCKCFGR_PLLSAIDIVQ_3 (0x08U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
11099#define RCC_DCKCFGR_PLLSAIDIVQ_4 (0x10U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
11100#define RCC_DCKCFGR_SAI1SRC_Pos (20U)
11101#define RCC_DCKCFGR_SAI1SRC_Msk (0x3U << RCC_DCKCFGR_SAI1SRC_Pos) /*!< 0x00300000 */
11102#define RCC_DCKCFGR_SAI1SRC RCC_DCKCFGR_SAI1SRC_Msk
11103#define RCC_DCKCFGR_SAI1SRC_0 (0x1U << RCC_DCKCFGR_SAI1SRC_Pos) /*!< 0x00100000 */
11104#define RCC_DCKCFGR_SAI1SRC_1 (0x2U << RCC_DCKCFGR_SAI1SRC_Pos) /*!< 0x00200000 */
11105#define RCC_DCKCFGR_SAI2SRC_Pos (22U)
11106#define RCC_DCKCFGR_SAI2SRC_Msk (0x3U << RCC_DCKCFGR_SAI2SRC_Pos) /*!< 0x00C00000 */
11107#define RCC_DCKCFGR_SAI2SRC RCC_DCKCFGR_SAI2SRC_Msk
11108#define RCC_DCKCFGR_SAI2SRC_0 (0x1U << RCC_DCKCFGR_SAI2SRC_Pos) /*!< 0x00400000 */
11109#define RCC_DCKCFGR_SAI2SRC_1 (0x2U << RCC_DCKCFGR_SAI2SRC_Pos) /*!< 0x00800000 */
11110
11111#define RCC_DCKCFGR_TIMPRE_Pos (24U)
11112#define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
11113#define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
11114#define RCC_DCKCFGR_I2S1SRC_Pos (25U)
11115#define RCC_DCKCFGR_I2S1SRC_Msk (0x3U << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x06000000 */
11116#define RCC_DCKCFGR_I2S1SRC RCC_DCKCFGR_I2S1SRC_Msk
11117#define RCC_DCKCFGR_I2S1SRC_0 (0x1U << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x02000000 */
11118#define RCC_DCKCFGR_I2S1SRC_1 (0x2U << RCC_DCKCFGR_I2S1SRC_Pos) /*!< 0x04000000 */
11119
11120#define RCC_DCKCFGR_I2S2SRC_Pos (27U)
11121#define RCC_DCKCFGR_I2S2SRC_Msk (0x3U << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x18000000 */
11122#define RCC_DCKCFGR_I2S2SRC RCC_DCKCFGR_I2S2SRC_Msk
11123#define RCC_DCKCFGR_I2S2SRC_0 (0x1U << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x08000000 */
11124#define RCC_DCKCFGR_I2S2SRC_1 (0x2U << RCC_DCKCFGR_I2S2SRC_Pos) /*!< 0x10000000 */
11125
11126/******************** Bit definition for RCC_CKGATENR register ***************/
11127#define RCC_CKGATENR_AHB2APB1_CKEN_Pos (0U)
11128#define RCC_CKGATENR_AHB2APB1_CKEN_Msk (0x1U << RCC_CKGATENR_AHB2APB1_CKEN_Pos) /*!< 0x00000001 */
11129#define RCC_CKGATENR_AHB2APB1_CKEN RCC_CKGATENR_AHB2APB1_CKEN_Msk
11130#define RCC_CKGATENR_AHB2APB2_CKEN_Pos (1U)
11131#define RCC_CKGATENR_AHB2APB2_CKEN_Msk (0x1U << RCC_CKGATENR_AHB2APB2_CKEN_Pos) /*!< 0x00000002 */
11132#define RCC_CKGATENR_AHB2APB2_CKEN RCC_CKGATENR_AHB2APB2_CKEN_Msk
11133#define RCC_CKGATENR_CM4DBG_CKEN_Pos (2U)
11134#define RCC_CKGATENR_CM4DBG_CKEN_Msk (0x1U << RCC_CKGATENR_CM4DBG_CKEN_Pos) /*!< 0x00000004 */
11135#define RCC_CKGATENR_CM4DBG_CKEN RCC_CKGATENR_CM4DBG_CKEN_Msk
11136#define RCC_CKGATENR_SPARE_CKEN_Pos (3U)
11137#define RCC_CKGATENR_SPARE_CKEN_Msk (0x1U << RCC_CKGATENR_SPARE_CKEN_Pos) /*!< 0x00000008 */
11138#define RCC_CKGATENR_SPARE_CKEN RCC_CKGATENR_SPARE_CKEN_Msk
11139#define RCC_CKGATENR_SRAM_CKEN_Pos (4U)
11140#define RCC_CKGATENR_SRAM_CKEN_Msk (0x1U << RCC_CKGATENR_SRAM_CKEN_Pos) /*!< 0x00000010 */
11141#define RCC_CKGATENR_SRAM_CKEN RCC_CKGATENR_SRAM_CKEN_Msk
11142#define RCC_CKGATENR_FLITF_CKEN_Pos (5U)
11143#define RCC_CKGATENR_FLITF_CKEN_Msk (0x1U << RCC_CKGATENR_FLITF_CKEN_Pos) /*!< 0x00000020 */
11144#define RCC_CKGATENR_FLITF_CKEN RCC_CKGATENR_FLITF_CKEN_Msk
11145#define RCC_CKGATENR_RCC_CKEN_Pos (6U)
11146#define RCC_CKGATENR_RCC_CKEN_Msk (0x1U << RCC_CKGATENR_RCC_CKEN_Pos) /*!< 0x00000040 */
11147#define RCC_CKGATENR_RCC_CKEN RCC_CKGATENR_RCC_CKEN_Msk
11148
11149/******************** Bit definition for RCC_DCKCFGR2 register ***************/
11150#define RCC_DCKCFGR2_FMPI2C1SEL_Pos (22U)
11151#define RCC_DCKCFGR2_FMPI2C1SEL_Msk (0x3U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00C00000 */
11152#define RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_Msk
11153#define RCC_DCKCFGR2_FMPI2C1SEL_0 (0x1U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00400000 */
11154#define RCC_DCKCFGR2_FMPI2C1SEL_1 (0x2U << RCC_DCKCFGR2_FMPI2C1SEL_Pos) /*!< 0x00800000 */
11155#define RCC_DCKCFGR2_CECSEL_Pos (26U)
11156#define RCC_DCKCFGR2_CECSEL_Msk (0x1U << RCC_DCKCFGR2_CECSEL_Pos) /*!< 0x04000000 */
11157#define RCC_DCKCFGR2_CECSEL RCC_DCKCFGR2_CECSEL_Msk
11158#define RCC_DCKCFGR2_CK48MSEL_Pos (27U)
11159#define RCC_DCKCFGR2_CK48MSEL_Msk (0x1U << RCC_DCKCFGR2_CK48MSEL_Pos) /*!< 0x08000000 */
11160#define RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_Msk
11161#define RCC_DCKCFGR2_SDIOSEL_Pos (28U)
11162#define RCC_DCKCFGR2_SDIOSEL_Msk (0x1U << RCC_DCKCFGR2_SDIOSEL_Pos) /*!< 0x10000000 */
11163#define RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_Msk
11164#define RCC_DCKCFGR2_SPDIFRXSEL_Pos (29U)
11165#define RCC_DCKCFGR2_SPDIFRXSEL_Msk (0x1U << RCC_DCKCFGR2_SPDIFRXSEL_Pos) /*!< 0x20000000 */
11166#define RCC_DCKCFGR2_SPDIFRXSEL RCC_DCKCFGR2_SPDIFRXSEL_Msk
11167
11168
11169/******************************************************************************/
11170/* */
11171/* Real-Time Clock (RTC) */
11172/* */
11173/******************************************************************************/
11174/*
11175 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
11176 */
11177#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
11178#define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
11179/******************** Bits definition for RTC_TR register *******************/
11180#define RTC_TR_PM_Pos (22U)
11181#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
11182#define RTC_TR_PM RTC_TR_PM_Msk
11183#define RTC_TR_HT_Pos (20U)
11184#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
11185#define RTC_TR_HT RTC_TR_HT_Msk
11186#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
11187#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
11188#define RTC_TR_HU_Pos (16U)
11189#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
11190#define RTC_TR_HU RTC_TR_HU_Msk
11191#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
11192#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
11193#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
11194#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
11195#define RTC_TR_MNT_Pos (12U)
11196#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
11197#define RTC_TR_MNT RTC_TR_MNT_Msk
11198#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
11199#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
11200#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
11201#define RTC_TR_MNU_Pos (8U)
11202#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
11203#define RTC_TR_MNU RTC_TR_MNU_Msk
11204#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
11205#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
11206#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
11207#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
11208#define RTC_TR_ST_Pos (4U)
11209#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
11210#define RTC_TR_ST RTC_TR_ST_Msk
11211#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
11212#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
11213#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
11214#define RTC_TR_SU_Pos (0U)
11215#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
11216#define RTC_TR_SU RTC_TR_SU_Msk
11217#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
11218#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
11219#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
11220#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
11221
11222/******************** Bits definition for RTC_DR register *******************/
11223#define RTC_DR_YT_Pos (20U)
11224#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
11225#define RTC_DR_YT RTC_DR_YT_Msk
11226#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
11227#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
11228#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
11229#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
11230#define RTC_DR_YU_Pos (16U)
11231#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
11232#define RTC_DR_YU RTC_DR_YU_Msk
11233#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
11234#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
11235#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
11236#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
11237#define RTC_DR_WDU_Pos (13U)
11238#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
11239#define RTC_DR_WDU RTC_DR_WDU_Msk
11240#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
11241#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
11242#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
11243#define RTC_DR_MT_Pos (12U)
11244#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
11245#define RTC_DR_MT RTC_DR_MT_Msk
11246#define RTC_DR_MU_Pos (8U)
11247#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
11248#define RTC_DR_MU RTC_DR_MU_Msk
11249#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
11250#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
11251#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
11252#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
11253#define RTC_DR_DT_Pos (4U)
11254#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
11255#define RTC_DR_DT RTC_DR_DT_Msk
11256#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
11257#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
11258#define RTC_DR_DU_Pos (0U)
11259#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
11260#define RTC_DR_DU RTC_DR_DU_Msk
11261#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
11262#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
11263#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
11264#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
11265
11266/******************** Bits definition for RTC_CR register *******************/
11267#define RTC_CR_COE_Pos (23U)
11268#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
11269#define RTC_CR_COE RTC_CR_COE_Msk
11270#define RTC_CR_OSEL_Pos (21U)
11271#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
11272#define RTC_CR_OSEL RTC_CR_OSEL_Msk
11273#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
11274#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
11275#define RTC_CR_POL_Pos (20U)
11276#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
11277#define RTC_CR_POL RTC_CR_POL_Msk
11278#define RTC_CR_COSEL_Pos (19U)
11279#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
11280#define RTC_CR_COSEL RTC_CR_COSEL_Msk
11281#define RTC_CR_BKP_Pos (18U)
11282#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
11283#define RTC_CR_BKP RTC_CR_BKP_Msk
11284#define RTC_CR_SUB1H_Pos (17U)
11285#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
11286#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
11287#define RTC_CR_ADD1H_Pos (16U)
11288#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
11289#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
11290#define RTC_CR_TSIE_Pos (15U)
11291#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
11292#define RTC_CR_TSIE RTC_CR_TSIE_Msk
11293#define RTC_CR_WUTIE_Pos (14U)
11294#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
11295#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
11296#define RTC_CR_ALRBIE_Pos (13U)
11297#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
11298#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
11299#define RTC_CR_ALRAIE_Pos (12U)
11300#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
11301#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
11302#define RTC_CR_TSE_Pos (11U)
11303#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
11304#define RTC_CR_TSE RTC_CR_TSE_Msk
11305#define RTC_CR_WUTE_Pos (10U)
11306#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
11307#define RTC_CR_WUTE RTC_CR_WUTE_Msk
11308#define RTC_CR_ALRBE_Pos (9U)
11309#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
11310#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
11311#define RTC_CR_ALRAE_Pos (8U)
11312#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
11313#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
11314#define RTC_CR_DCE_Pos (7U)
11315#define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
11316#define RTC_CR_DCE RTC_CR_DCE_Msk
11317#define RTC_CR_FMT_Pos (6U)
11318#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
11319#define RTC_CR_FMT RTC_CR_FMT_Msk
11320#define RTC_CR_BYPSHAD_Pos (5U)
11321#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
11322#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
11323#define RTC_CR_REFCKON_Pos (4U)
11324#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
11325#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
11326#define RTC_CR_TSEDGE_Pos (3U)
11327#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
11328#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
11329#define RTC_CR_WUCKSEL_Pos (0U)
11330#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
11331#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
11332#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
11333#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
11334#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
11335
11336/* Legacy defines */
11337#define RTC_CR_BCK RTC_CR_BKP
11338
11339/******************** Bits definition for RTC_ISR register ******************/
11340#define RTC_ISR_RECALPF_Pos (16U)
11341#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
11342#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
11343#define RTC_ISR_TAMP1F_Pos (13U)
11344#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
11345#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
11346#define RTC_ISR_TAMP2F_Pos (14U)
11347#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
11348#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
11349#define RTC_ISR_TSOVF_Pos (12U)
11350#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
11351#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
11352#define RTC_ISR_TSF_Pos (11U)
11353#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
11354#define RTC_ISR_TSF RTC_ISR_TSF_Msk
11355#define RTC_ISR_WUTF_Pos (10U)
11356#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
11357#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
11358#define RTC_ISR_ALRBF_Pos (9U)
11359#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
11360#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
11361#define RTC_ISR_ALRAF_Pos (8U)
11362#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
11363#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
11364#define RTC_ISR_INIT_Pos (7U)
11365#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
11366#define RTC_ISR_INIT RTC_ISR_INIT_Msk
11367#define RTC_ISR_INITF_Pos (6U)
11368#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
11369#define RTC_ISR_INITF RTC_ISR_INITF_Msk
11370#define RTC_ISR_RSF_Pos (5U)
11371#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
11372#define RTC_ISR_RSF RTC_ISR_RSF_Msk
11373#define RTC_ISR_INITS_Pos (4U)
11374#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
11375#define RTC_ISR_INITS RTC_ISR_INITS_Msk
11376#define RTC_ISR_SHPF_Pos (3U)
11377#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
11378#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
11379#define RTC_ISR_WUTWF_Pos (2U)
11380#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
11381#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
11382#define RTC_ISR_ALRBWF_Pos (1U)
11383#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
11384#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
11385#define RTC_ISR_ALRAWF_Pos (0U)
11386#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
11387#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
11388
11389/******************** Bits definition for RTC_PRER register *****************/
11390#define RTC_PRER_PREDIV_A_Pos (16U)
11391#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
11392#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
11393#define RTC_PRER_PREDIV_S_Pos (0U)
11394#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
11395#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
11396
11397/******************** Bits definition for RTC_WUTR register *****************/
11398#define RTC_WUTR_WUT_Pos (0U)
11399#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
11400#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
11401
11402/******************** Bits definition for RTC_CALIBR register ***************/
11403#define RTC_CALIBR_DCS_Pos (7U)
11404#define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
11405#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
11406#define RTC_CALIBR_DC_Pos (0U)
11407#define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
11408#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
11409
11410/******************** Bits definition for RTC_ALRMAR register ***************/
11411#define RTC_ALRMAR_MSK4_Pos (31U)
11412#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
11413#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
11414#define RTC_ALRMAR_WDSEL_Pos (30U)
11415#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
11416#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
11417#define RTC_ALRMAR_DT_Pos (28U)
11418#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
11419#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
11420#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
11421#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
11422#define RTC_ALRMAR_DU_Pos (24U)
11423#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
11424#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
11425#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
11426#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
11427#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
11428#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
11429#define RTC_ALRMAR_MSK3_Pos (23U)
11430#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
11431#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
11432#define RTC_ALRMAR_PM_Pos (22U)
11433#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
11434#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
11435#define RTC_ALRMAR_HT_Pos (20U)
11436#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
11437#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
11438#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
11439#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
11440#define RTC_ALRMAR_HU_Pos (16U)
11441#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
11442#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
11443#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
11444#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
11445#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
11446#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
11447#define RTC_ALRMAR_MSK2_Pos (15U)
11448#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
11449#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
11450#define RTC_ALRMAR_MNT_Pos (12U)
11451#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
11452#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
11453#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
11454#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
11455#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
11456#define RTC_ALRMAR_MNU_Pos (8U)
11457#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
11458#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
11459#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
11460#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
11461#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
11462#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
11463#define RTC_ALRMAR_MSK1_Pos (7U)
11464#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
11465#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
11466#define RTC_ALRMAR_ST_Pos (4U)
11467#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
11468#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
11469#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
11470#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
11471#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
11472#define RTC_ALRMAR_SU_Pos (0U)
11473#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
11474#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
11475#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
11476#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
11477#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
11478#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
11479
11480/******************** Bits definition for RTC_ALRMBR register ***************/
11481#define RTC_ALRMBR_MSK4_Pos (31U)
11482#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
11483#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
11484#define RTC_ALRMBR_WDSEL_Pos (30U)
11485#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
11486#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
11487#define RTC_ALRMBR_DT_Pos (28U)
11488#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
11489#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
11490#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
11491#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
11492#define RTC_ALRMBR_DU_Pos (24U)
11493#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
11494#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
11495#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
11496#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
11497#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
11498#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
11499#define RTC_ALRMBR_MSK3_Pos (23U)
11500#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
11501#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
11502#define RTC_ALRMBR_PM_Pos (22U)
11503#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
11504#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
11505#define RTC_ALRMBR_HT_Pos (20U)
11506#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
11507#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
11508#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
11509#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
11510#define RTC_ALRMBR_HU_Pos (16U)
11511#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
11512#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
11513#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
11514#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
11515#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
11516#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
11517#define RTC_ALRMBR_MSK2_Pos (15U)
11518#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
11519#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
11520#define RTC_ALRMBR_MNT_Pos (12U)
11521#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
11522#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
11523#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
11524#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
11525#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
11526#define RTC_ALRMBR_MNU_Pos (8U)
11527#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
11528#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
11529#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
11530#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
11531#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
11532#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
11533#define RTC_ALRMBR_MSK1_Pos (7U)
11534#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
11535#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
11536#define RTC_ALRMBR_ST_Pos (4U)
11537#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
11538#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
11539#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
11540#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
11541#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
11542#define RTC_ALRMBR_SU_Pos (0U)
11543#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
11544#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
11545#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
11546#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
11547#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
11548#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
11549
11550/******************** Bits definition for RTC_WPR register ******************/
11551#define RTC_WPR_KEY_Pos (0U)
11552#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
11553#define RTC_WPR_KEY RTC_WPR_KEY_Msk
11554
11555/******************** Bits definition for RTC_SSR register ******************/
11556#define RTC_SSR_SS_Pos (0U)
11557#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
11558#define RTC_SSR_SS RTC_SSR_SS_Msk
11559
11560/******************** Bits definition for RTC_SHIFTR register ***************/
11561#define RTC_SHIFTR_SUBFS_Pos (0U)
11562#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
11563#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
11564#define RTC_SHIFTR_ADD1S_Pos (31U)
11565#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
11566#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
11567
11568/******************** Bits definition for RTC_TSTR register *****************/
11569#define RTC_TSTR_PM_Pos (22U)
11570#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
11571#define RTC_TSTR_PM RTC_TSTR_PM_Msk
11572#define RTC_TSTR_HT_Pos (20U)
11573#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
11574#define RTC_TSTR_HT RTC_TSTR_HT_Msk
11575#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
11576#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
11577#define RTC_TSTR_HU_Pos (16U)
11578#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
11579#define RTC_TSTR_HU RTC_TSTR_HU_Msk
11580#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
11581#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
11582#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
11583#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
11584#define RTC_TSTR_MNT_Pos (12U)
11585#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
11586#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
11587#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
11588#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
11589#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
11590#define RTC_TSTR_MNU_Pos (8U)
11591#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
11592#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
11593#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
11594#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
11595#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
11596#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
11597#define RTC_TSTR_ST_Pos (4U)
11598#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
11599#define RTC_TSTR_ST RTC_TSTR_ST_Msk
11600#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
11601#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
11602#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
11603#define RTC_TSTR_SU_Pos (0U)
11604#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
11605#define RTC_TSTR_SU RTC_TSTR_SU_Msk
11606#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
11607#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
11608#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
11609#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
11610
11611/******************** Bits definition for RTC_TSDR register *****************/
11612#define RTC_TSDR_WDU_Pos (13U)
11613#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
11614#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
11615#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
11616#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
11617#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
11618#define RTC_TSDR_MT_Pos (12U)
11619#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
11620#define RTC_TSDR_MT RTC_TSDR_MT_Msk
11621#define RTC_TSDR_MU_Pos (8U)
11622#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
11623#define RTC_TSDR_MU RTC_TSDR_MU_Msk
11624#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
11625#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
11626#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
11627#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
11628#define RTC_TSDR_DT_Pos (4U)
11629#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
11630#define RTC_TSDR_DT RTC_TSDR_DT_Msk
11631#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
11632#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
11633#define RTC_TSDR_DU_Pos (0U)
11634#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
11635#define RTC_TSDR_DU RTC_TSDR_DU_Msk
11636#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
11637#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
11638#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
11639#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
11640
11641/******************** Bits definition for RTC_TSSSR register ****************/
11642#define RTC_TSSSR_SS_Pos (0U)
11643#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
11644#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
11645
11646/******************** Bits definition for RTC_CAL register *****************/
11647#define RTC_CALR_CALP_Pos (15U)
11648#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
11649#define RTC_CALR_CALP RTC_CALR_CALP_Msk
11650#define RTC_CALR_CALW8_Pos (14U)
11651#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
11652#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
11653#define RTC_CALR_CALW16_Pos (13U)
11654#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
11655#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
11656#define RTC_CALR_CALM_Pos (0U)
11657#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
11658#define RTC_CALR_CALM RTC_CALR_CALM_Msk
11659#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
11660#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
11661#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
11662#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
11663#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
11664#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
11665#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
11666#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
11667#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
11668
11669/******************** Bits definition for RTC_TAFCR register ****************/
11670#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
11671#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
11672#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
11673#define RTC_TAFCR_TSINSEL_Pos (17U)
11674#define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
11675#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
11676#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
11677#define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
11678#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
11679#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
11680#define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
11681#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
11682#define RTC_TAFCR_TAMPPRCH_Pos (13U)
11683#define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
11684#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
11685#define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
11686#define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
11687#define RTC_TAFCR_TAMPFLT_Pos (11U)
11688#define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
11689#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
11690#define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
11691#define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
11692#define RTC_TAFCR_TAMPFREQ_Pos (8U)
11693#define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
11694#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
11695#define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
11696#define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
11697#define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
11698#define RTC_TAFCR_TAMPTS_Pos (7U)
11699#define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
11700#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
11701#define RTC_TAFCR_TAMP2TRG_Pos (4U)
11702#define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
11703#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
11704#define RTC_TAFCR_TAMP2E_Pos (3U)
11705#define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
11706#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
11707#define RTC_TAFCR_TAMPIE_Pos (2U)
11708#define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
11709#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
11710#define RTC_TAFCR_TAMP1TRG_Pos (1U)
11711#define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
11712#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
11713#define RTC_TAFCR_TAMP1E_Pos (0U)
11714#define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
11715#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
11716
11717/* Legacy defines */
11718#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
11719
11720/******************** Bits definition for RTC_ALRMASSR register *************/
11721#define RTC_ALRMASSR_MASKSS_Pos (24U)
11722#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
11723#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
11724#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
11725#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
11726#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
11727#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
11728#define RTC_ALRMASSR_SS_Pos (0U)
11729#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
11730#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
11731
11732/******************** Bits definition for RTC_ALRMBSSR register *************/
11733#define RTC_ALRMBSSR_MASKSS_Pos (24U)
11734#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
11735#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
11736#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
11737#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
11738#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
11739#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
11740#define RTC_ALRMBSSR_SS_Pos (0U)
11741#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
11742#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
11743
11744/******************** Bits definition for RTC_BKP0R register ****************/
11745#define RTC_BKP0R_Pos (0U)
11746#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
11747#define RTC_BKP0R RTC_BKP0R_Msk
11748
11749/******************** Bits definition for RTC_BKP1R register ****************/
11750#define RTC_BKP1R_Pos (0U)
11751#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
11752#define RTC_BKP1R RTC_BKP1R_Msk
11753
11754/******************** Bits definition for RTC_BKP2R register ****************/
11755#define RTC_BKP2R_Pos (0U)
11756#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
11757#define RTC_BKP2R RTC_BKP2R_Msk
11758
11759/******************** Bits definition for RTC_BKP3R register ****************/
11760#define RTC_BKP3R_Pos (0U)
11761#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
11762#define RTC_BKP3R RTC_BKP3R_Msk
11763
11764/******************** Bits definition for RTC_BKP4R register ****************/
11765#define RTC_BKP4R_Pos (0U)
11766#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
11767#define RTC_BKP4R RTC_BKP4R_Msk
11768
11769/******************** Bits definition for RTC_BKP5R register ****************/
11770#define RTC_BKP5R_Pos (0U)
11771#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
11772#define RTC_BKP5R RTC_BKP5R_Msk
11773
11774/******************** Bits definition for RTC_BKP6R register ****************/
11775#define RTC_BKP6R_Pos (0U)
11776#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
11777#define RTC_BKP6R RTC_BKP6R_Msk
11778
11779/******************** Bits definition for RTC_BKP7R register ****************/
11780#define RTC_BKP7R_Pos (0U)
11781#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
11782#define RTC_BKP7R RTC_BKP7R_Msk
11783
11784/******************** Bits definition for RTC_BKP8R register ****************/
11785#define RTC_BKP8R_Pos (0U)
11786#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
11787#define RTC_BKP8R RTC_BKP8R_Msk
11788
11789/******************** Bits definition for RTC_BKP9R register ****************/
11790#define RTC_BKP9R_Pos (0U)
11791#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
11792#define RTC_BKP9R RTC_BKP9R_Msk
11793
11794/******************** Bits definition for RTC_BKP10R register ***************/
11795#define RTC_BKP10R_Pos (0U)
11796#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
11797#define RTC_BKP10R RTC_BKP10R_Msk
11798
11799/******************** Bits definition for RTC_BKP11R register ***************/
11800#define RTC_BKP11R_Pos (0U)
11801#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
11802#define RTC_BKP11R RTC_BKP11R_Msk
11803
11804/******************** Bits definition for RTC_BKP12R register ***************/
11805#define RTC_BKP12R_Pos (0U)
11806#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
11807#define RTC_BKP12R RTC_BKP12R_Msk
11808
11809/******************** Bits definition for RTC_BKP13R register ***************/
11810#define RTC_BKP13R_Pos (0U)
11811#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
11812#define RTC_BKP13R RTC_BKP13R_Msk
11813
11814/******************** Bits definition for RTC_BKP14R register ***************/
11815#define RTC_BKP14R_Pos (0U)
11816#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
11817#define RTC_BKP14R RTC_BKP14R_Msk
11818
11819/******************** Bits definition for RTC_BKP15R register ***************/
11820#define RTC_BKP15R_Pos (0U)
11821#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
11822#define RTC_BKP15R RTC_BKP15R_Msk
11823
11824/******************** Bits definition for RTC_BKP16R register ***************/
11825#define RTC_BKP16R_Pos (0U)
11826#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
11827#define RTC_BKP16R RTC_BKP16R_Msk
11828
11829/******************** Bits definition for RTC_BKP17R register ***************/
11830#define RTC_BKP17R_Pos (0U)
11831#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
11832#define RTC_BKP17R RTC_BKP17R_Msk
11833
11834/******************** Bits definition for RTC_BKP18R register ***************/
11835#define RTC_BKP18R_Pos (0U)
11836#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
11837#define RTC_BKP18R RTC_BKP18R_Msk
11838
11839/******************** Bits definition for RTC_BKP19R register ***************/
11840#define RTC_BKP19R_Pos (0U)
11841#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
11842#define RTC_BKP19R RTC_BKP19R_Msk
11843
11844/******************** Number of backup registers ******************************/
11845#define RTC_BKP_NUMBER 0x000000014U
11846
11847/******************************************************************************/
11848/* */
11849/* Serial Audio Interface */
11850/* */
11851/******************************************************************************/
11852/******************** Bit definition for SAI_GCR register *******************/
11853#define SAI_GCR_SYNCIN_Pos (0U)
11854#define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
11855#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
11856#define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
11857#define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
11858
11859#define SAI_GCR_SYNCOUT_Pos (4U)
11860#define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
11861#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
11862#define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
11863#define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
11864
11865/******************* Bit definition for SAI_xCR1 register *******************/
11866#define SAI_xCR1_MODE_Pos (0U)
11867#define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
11868#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
11869#define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
11870#define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
11871
11872#define SAI_xCR1_PRTCFG_Pos (2U)
11873#define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
11874#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
11875#define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
11876#define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
11877
11878#define SAI_xCR1_DS_Pos (5U)
11879#define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
11880#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
11881#define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
11882#define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
11883#define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
11884
11885#define SAI_xCR1_LSBFIRST_Pos (8U)
11886#define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
11887#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
11888#define SAI_xCR1_CKSTR_Pos (9U)
11889#define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
11890#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
11891
11892#define SAI_xCR1_SYNCEN_Pos (10U)
11893#define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
11894#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
11895#define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
11896#define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
11897
11898#define SAI_xCR1_MONO_Pos (12U)
11899#define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
11900#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
11901#define SAI_xCR1_OUTDRIV_Pos (13U)
11902#define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
11903#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
11904#define SAI_xCR1_SAIEN_Pos (16U)
11905#define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
11906#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
11907#define SAI_xCR1_DMAEN_Pos (17U)
11908#define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
11909#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
11910#define SAI_xCR1_NODIV_Pos (19U)
11911#define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
11912#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
11913
11914#define SAI_xCR1_MCKDIV_Pos (20U)
11915#define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
11916#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
11917#define SAI_xCR1_MCKDIV_0 (0x1U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
11918#define SAI_xCR1_MCKDIV_1 (0x2U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
11919#define SAI_xCR1_MCKDIV_2 (0x4U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
11920#define SAI_xCR1_MCKDIV_3 (0x8U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
11921
11922/******************* Bit definition for SAI_xCR2 register *******************/
11923#define SAI_xCR2_FTH_Pos (0U)
11924#define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
11925#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
11926#define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
11927#define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
11928#define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
11929
11930#define SAI_xCR2_FFLUSH_Pos (3U)
11931#define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
11932#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
11933#define SAI_xCR2_TRIS_Pos (4U)
11934#define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
11935#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
11936#define SAI_xCR2_MUTE_Pos (5U)
11937#define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
11938#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
11939#define SAI_xCR2_MUTEVAL_Pos (6U)
11940#define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
11941#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
11942
11943#define SAI_xCR2_MUTECNT_Pos (7U)
11944#define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
11945#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
11946#define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
11947#define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
11948#define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
11949#define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
11950#define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
11951#define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
11952
11953#define SAI_xCR2_CPL_Pos (13U)
11954#define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
11955#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
11956
11957#define SAI_xCR2_COMP_Pos (14U)
11958#define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
11959#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
11960#define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
11961#define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
11962
11963/****************** Bit definition for SAI_xFRCR register *******************/
11964#define SAI_xFRCR_FRL_Pos (0U)
11965#define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
11966#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[1:0](Frame length) */
11967#define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
11968#define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
11969#define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
11970#define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
11971#define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
11972#define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
11973#define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
11974#define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
11975
11976#define SAI_xFRCR_FSALL_Pos (8U)
11977#define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
11978#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[1:0] (Frame synchronization active level length) */
11979#define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
11980#define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
11981#define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
11982#define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
11983#define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
11984#define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
11985#define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
11986
11987#define SAI_xFRCR_FSDEF_Pos (16U)
11988#define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
11989#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
11990#define SAI_xFRCR_FSPOL_Pos (17U)
11991#define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
11992#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
11993#define SAI_xFRCR_FSOFF_Pos (18U)
11994#define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
11995#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
11996/* Legacy defines */
11997#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
11998
11999/****************** Bit definition for SAI_xSLOTR register *******************/
12000#define SAI_xSLOTR_FBOFF_Pos (0U)
12001#define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
12002#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
12003#define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
12004#define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
12005#define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
12006#define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
12007#define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
12008
12009#define SAI_xSLOTR_SLOTSZ_Pos (6U)
12010#define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
12011#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
12012#define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
12013#define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
12014
12015#define SAI_xSLOTR_NBSLOT_Pos (8U)
12016#define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
12017#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
12018#define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
12019#define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
12020#define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
12021#define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
12022
12023#define SAI_xSLOTR_SLOTEN_Pos (16U)
12024#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
12025#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
12026
12027/******************* Bit definition for SAI_xIMR register *******************/
12028#define SAI_xIMR_OVRUDRIE_Pos (0U)
12029#define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
12030#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
12031#define SAI_xIMR_MUTEDETIE_Pos (1U)
12032#define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
12033#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
12034#define SAI_xIMR_WCKCFGIE_Pos (2U)
12035#define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
12036#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
12037#define SAI_xIMR_FREQIE_Pos (3U)
12038#define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
12039#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
12040#define SAI_xIMR_CNRDYIE_Pos (4U)
12041#define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
12042#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
12043#define SAI_xIMR_AFSDETIE_Pos (5U)
12044#define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
12045#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
12046#define SAI_xIMR_LFSDETIE_Pos (6U)
12047#define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
12048#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
12049
12050/******************** Bit definition for SAI_xSR register *******************/
12051#define SAI_xSR_OVRUDR_Pos (0U)
12052#define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
12053#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
12054#define SAI_xSR_MUTEDET_Pos (1U)
12055#define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
12056#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
12057#define SAI_xSR_WCKCFG_Pos (2U)
12058#define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
12059#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
12060#define SAI_xSR_FREQ_Pos (3U)
12061#define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
12062#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
12063#define SAI_xSR_CNRDY_Pos (4U)
12064#define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
12065#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
12066#define SAI_xSR_AFSDET_Pos (5U)
12067#define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
12068#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
12069#define SAI_xSR_LFSDET_Pos (6U)
12070#define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
12071#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
12072
12073#define SAI_xSR_FLVL_Pos (16U)
12074#define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
12075#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
12076#define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
12077#define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
12078#define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
12079
12080/****************** Bit definition for SAI_xCLRFR register ******************/
12081#define SAI_xCLRFR_COVRUDR_Pos (0U)
12082#define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
12083#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
12084#define SAI_xCLRFR_CMUTEDET_Pos (1U)
12085#define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
12086#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
12087#define SAI_xCLRFR_CWCKCFG_Pos (2U)
12088#define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
12089#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
12090#define SAI_xCLRFR_CFREQ_Pos (3U)
12091#define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
12092#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
12093#define SAI_xCLRFR_CCNRDY_Pos (4U)
12094#define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
12095#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
12096#define SAI_xCLRFR_CAFSDET_Pos (5U)
12097#define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
12098#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
12099#define SAI_xCLRFR_CLFSDET_Pos (6U)
12100#define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
12101#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
12102
12103/****************** Bit definition for SAI_xDR register ******************/
12104#define SAI_xDR_DATA_Pos (0U)
12105#define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
12106#define SAI_xDR_DATA SAI_xDR_DATA_Msk
12107
12108/******************************************************************************/
12109/* */
12110/* SPDIF-RX Interface */
12111/* */
12112/******************************************************************************/
12113/******************** Bit definition for SPDIFRX_CR register *******************/
12114#define SPDIFRX_CR_SPDIFEN_Pos (0U)
12115#define SPDIFRX_CR_SPDIFEN_Msk (0x3U << SPDIFRX_CR_SPDIFEN_Pos) /*!< 0x00000003 */
12116#define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk /*!<Peripheral Block Enable */
12117#define SPDIFRX_CR_RXDMAEN_Pos (2U)
12118#define SPDIFRX_CR_RXDMAEN_Msk (0x1U << SPDIFRX_CR_RXDMAEN_Pos) /*!< 0x00000004 */
12119#define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk /*!<Receiver DMA Enable for data flow */
12120#define SPDIFRX_CR_RXSTEO_Pos (3U)
12121#define SPDIFRX_CR_RXSTEO_Msk (0x1U << SPDIFRX_CR_RXSTEO_Pos) /*!< 0x00000008 */
12122#define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk /*!<Stereo Mode */
12123#define SPDIFRX_CR_DRFMT_Pos (4U)
12124#define SPDIFRX_CR_DRFMT_Msk (0x3U << SPDIFRX_CR_DRFMT_Pos) /*!< 0x00000030 */
12125#define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk /*!<RX Data format */
12126#define SPDIFRX_CR_PMSK_Pos (6U)
12127#define SPDIFRX_CR_PMSK_Msk (0x1U << SPDIFRX_CR_PMSK_Pos) /*!< 0x00000040 */
12128#define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk /*!<Mask Parity error bit */
12129#define SPDIFRX_CR_VMSK_Pos (7U)
12130#define SPDIFRX_CR_VMSK_Msk (0x1U << SPDIFRX_CR_VMSK_Pos) /*!< 0x00000080 */
12131#define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk /*!<Mask of Validity bit */
12132#define SPDIFRX_CR_CUMSK_Pos (8U)
12133#define SPDIFRX_CR_CUMSK_Msk (0x1U << SPDIFRX_CR_CUMSK_Pos) /*!< 0x00000100 */
12134#define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk /*!<Mask of channel status and user bits */
12135#define SPDIFRX_CR_PTMSK_Pos (9U)
12136#define SPDIFRX_CR_PTMSK_Msk (0x1U << SPDIFRX_CR_PTMSK_Pos) /*!< 0x00000200 */
12137#define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk /*!<Mask of Preamble Type bits */
12138#define SPDIFRX_CR_CBDMAEN_Pos (10U)
12139#define SPDIFRX_CR_CBDMAEN_Msk (0x1U << SPDIFRX_CR_CBDMAEN_Pos) /*!< 0x00000400 */
12140#define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk /*!<Control Buffer DMA ENable for control flow */
12141#define SPDIFRX_CR_CHSEL_Pos (11U)
12142#define SPDIFRX_CR_CHSEL_Msk (0x1U << SPDIFRX_CR_CHSEL_Pos) /*!< 0x00000800 */
12143#define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk /*!<Channel Selection */
12144#define SPDIFRX_CR_NBTR_Pos (12U)
12145#define SPDIFRX_CR_NBTR_Msk (0x3U << SPDIFRX_CR_NBTR_Pos) /*!< 0x00003000 */
12146#define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchronization phase */
12147#define SPDIFRX_CR_WFA_Pos (14U)
12148#define SPDIFRX_CR_WFA_Msk (0x1U << SPDIFRX_CR_WFA_Pos) /*!< 0x00004000 */
12149#define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk /*!<Wait For Activity */
12150#define SPDIFRX_CR_INSEL_Pos (16U)
12151#define SPDIFRX_CR_INSEL_Msk (0x7U << SPDIFRX_CR_INSEL_Pos) /*!< 0x00070000 */
12152#define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk /*!<SPDIFRX input selection */
12153
12154/******************* Bit definition for SPDIFRX_IMR register *******************/
12155#define SPDIFRX_IMR_RXNEIE_Pos (0U)
12156#define SPDIFRX_IMR_RXNEIE_Msk (0x1U << SPDIFRX_IMR_RXNEIE_Pos) /*!< 0x00000001 */
12157#define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk /*!<RXNE interrupt enable */
12158#define SPDIFRX_IMR_CSRNEIE_Pos (1U)
12159#define SPDIFRX_IMR_CSRNEIE_Msk (0x1U << SPDIFRX_IMR_CSRNEIE_Pos) /*!< 0x00000002 */
12160#define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk /*!<Control Buffer Ready Interrupt Enable */
12161#define SPDIFRX_IMR_PERRIE_Pos (2U)
12162#define SPDIFRX_IMR_PERRIE_Msk (0x1U << SPDIFRX_IMR_PERRIE_Pos) /*!< 0x00000004 */
12163#define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk /*!<Parity error interrupt enable */
12164#define SPDIFRX_IMR_OVRIE_Pos (3U)
12165#define SPDIFRX_IMR_OVRIE_Msk (0x1U << SPDIFRX_IMR_OVRIE_Pos) /*!< 0x00000008 */
12166#define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk /*!<Overrun error Interrupt Enable */
12167#define SPDIFRX_IMR_SBLKIE_Pos (4U)
12168#define SPDIFRX_IMR_SBLKIE_Msk (0x1U << SPDIFRX_IMR_SBLKIE_Pos) /*!< 0x00000010 */
12169#define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk /*!<Synchronization Block Detected Interrupt Enable */
12170#define SPDIFRX_IMR_SYNCDIE_Pos (5U)
12171#define SPDIFRX_IMR_SYNCDIE_Msk (0x1U << SPDIFRX_IMR_SYNCDIE_Pos) /*!< 0x00000020 */
12172#define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk /*!<Synchronization Done */
12173#define SPDIFRX_IMR_IFEIE_Pos (6U)
12174#define SPDIFRX_IMR_IFEIE_Msk (0x1U << SPDIFRX_IMR_IFEIE_Pos) /*!< 0x00000040 */
12175#define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk /*!<Serial Interface Error Interrupt Enable */
12176
12177/******************* Bit definition for SPDIFRX_SR register *******************/
12178#define SPDIFRX_SR_RXNE_Pos (0U)
12179#define SPDIFRX_SR_RXNE_Msk (0x1U << SPDIFRX_SR_RXNE_Pos) /*!< 0x00000001 */
12180#define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk /*!<Read data register not empty */
12181#define SPDIFRX_SR_CSRNE_Pos (1U)
12182#define SPDIFRX_SR_CSRNE_Msk (0x1U << SPDIFRX_SR_CSRNE_Pos) /*!< 0x00000002 */
12183#define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk /*!<The Control Buffer register is not empty */
12184#define SPDIFRX_SR_PERR_Pos (2U)
12185#define SPDIFRX_SR_PERR_Msk (0x1U << SPDIFRX_SR_PERR_Pos) /*!< 0x00000004 */
12186#define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk /*!<Parity error */
12187#define SPDIFRX_SR_OVR_Pos (3U)
12188#define SPDIFRX_SR_OVR_Msk (0x1U << SPDIFRX_SR_OVR_Pos) /*!< 0x00000008 */
12189#define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk /*!<Overrun error */
12190#define SPDIFRX_SR_SBD_Pos (4U)
12191#define SPDIFRX_SR_SBD_Msk (0x1U << SPDIFRX_SR_SBD_Pos) /*!< 0x00000010 */
12192#define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk /*!<Synchronization Block Detected */
12193#define SPDIFRX_SR_SYNCD_Pos (5U)
12194#define SPDIFRX_SR_SYNCD_Msk (0x1U << SPDIFRX_SR_SYNCD_Pos) /*!< 0x00000020 */
12195#define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk /*!<Synchronization Done */
12196#define SPDIFRX_SR_FERR_Pos (6U)
12197#define SPDIFRX_SR_FERR_Msk (0x1U << SPDIFRX_SR_FERR_Pos) /*!< 0x00000040 */
12198#define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk /*!<Framing error */
12199#define SPDIFRX_SR_SERR_Pos (7U)
12200#define SPDIFRX_SR_SERR_Msk (0x1U << SPDIFRX_SR_SERR_Pos) /*!< 0x00000080 */
12201#define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk /*!<Synchronization error */
12202#define SPDIFRX_SR_TERR_Pos (8U)
12203#define SPDIFRX_SR_TERR_Msk (0x1U << SPDIFRX_SR_TERR_Pos) /*!< 0x00000100 */
12204#define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error */
12205#define SPDIFRX_SR_WIDTH5_Pos (16U)
12206#define SPDIFRX_SR_WIDTH5_Msk (0x7FFFU << SPDIFRX_SR_WIDTH5_Pos) /*!< 0x7FFF0000 */
12207#define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk /*!<Duration of 5 symbols counted with SPDIFRX_clk */
12208
12209/******************* Bit definition for SPDIFRX_IFCR register *******************/
12210#define SPDIFRX_IFCR_PERRCF_Pos (2U)
12211#define SPDIFRX_IFCR_PERRCF_Msk (0x1U << SPDIFRX_IFCR_PERRCF_Pos) /*!< 0x00000004 */
12212#define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk /*!<Clears the Parity error flag */
12213#define SPDIFRX_IFCR_OVRCF_Pos (3U)
12214#define SPDIFRX_IFCR_OVRCF_Msk (0x1U << SPDIFRX_IFCR_OVRCF_Pos) /*!< 0x00000008 */
12215#define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk /*!<Clears the Overrun error flag */
12216#define SPDIFRX_IFCR_SBDCF_Pos (4U)
12217#define SPDIFRX_IFCR_SBDCF_Msk (0x1U << SPDIFRX_IFCR_SBDCF_Pos) /*!< 0x00000010 */
12218#define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk /*!<Clears the Synchronization Block Detected flag */
12219#define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
12220#define SPDIFRX_IFCR_SYNCDCF_Msk (0x1U << SPDIFRX_IFCR_SYNCDCF_Pos) /*!< 0x00000020 */
12221#define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk /*!<Clears the Synchronization Done flag */
12222
12223/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
12224#define SPDIFRX_DR0_DR_Pos (0U)
12225#define SPDIFRX_DR0_DR_Msk (0xFFFFFFU << SPDIFRX_DR0_DR_Pos) /*!< 0x00FFFFFF */
12226#define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk /*!<Data value */
12227#define SPDIFRX_DR0_PE_Pos (24U)
12228#define SPDIFRX_DR0_PE_Msk (0x1U << SPDIFRX_DR0_PE_Pos) /*!< 0x01000000 */
12229#define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk /*!<Parity Error bit */
12230#define SPDIFRX_DR0_V_Pos (25U)
12231#define SPDIFRX_DR0_V_Msk (0x1U << SPDIFRX_DR0_V_Pos) /*!< 0x02000000 */
12232#define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk /*!<Validity bit */
12233#define SPDIFRX_DR0_U_Pos (26U)
12234#define SPDIFRX_DR0_U_Msk (0x1U << SPDIFRX_DR0_U_Pos) /*!< 0x04000000 */
12235#define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk /*!<User bit */
12236#define SPDIFRX_DR0_C_Pos (27U)
12237#define SPDIFRX_DR0_C_Msk (0x1U << SPDIFRX_DR0_C_Pos) /*!< 0x08000000 */
12238#define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk /*!<Channel Status bit */
12239#define SPDIFRX_DR0_PT_Pos (28U)
12240#define SPDIFRX_DR0_PT_Msk (0x3U << SPDIFRX_DR0_PT_Pos) /*!< 0x30000000 */
12241#define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk /*!<Preamble Type */
12242
12243/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
12244#define SPDIFRX_DR1_DR_Pos (8U)
12245#define SPDIFRX_DR1_DR_Msk (0xFFFFFFU << SPDIFRX_DR1_DR_Pos) /*!< 0xFFFFFF00 */
12246#define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk /*!<Data value */
12247#define SPDIFRX_DR1_PT_Pos (4U)
12248#define SPDIFRX_DR1_PT_Msk (0x3U << SPDIFRX_DR1_PT_Pos) /*!< 0x00000030 */
12249#define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk /*!<Preamble Type */
12250#define SPDIFRX_DR1_C_Pos (3U)
12251#define SPDIFRX_DR1_C_Msk (0x1U << SPDIFRX_DR1_C_Pos) /*!< 0x00000008 */
12252#define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk /*!<Channel Status bit */
12253#define SPDIFRX_DR1_U_Pos (2U)
12254#define SPDIFRX_DR1_U_Msk (0x1U << SPDIFRX_DR1_U_Pos) /*!< 0x00000004 */
12255#define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk /*!<User bit */
12256#define SPDIFRX_DR1_V_Pos (1U)
12257#define SPDIFRX_DR1_V_Msk (0x1U << SPDIFRX_DR1_V_Pos) /*!< 0x00000002 */
12258#define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk /*!<Validity bit */
12259#define SPDIFRX_DR1_PE_Pos (0U)
12260#define SPDIFRX_DR1_PE_Msk (0x1U << SPDIFRX_DR1_PE_Pos) /*!< 0x00000001 */
12261#define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk /*!<Parity Error bit */
12262
12263/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
12264#define SPDIFRX_DR1_DRNL1_Pos (16U)
12265#define SPDIFRX_DR1_DRNL1_Msk (0xFFFFU << SPDIFRX_DR1_DRNL1_Pos) /*!< 0xFFFF0000 */
12266#define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk /*!<Data value Channel B */
12267#define SPDIFRX_DR1_DRNL2_Pos (0U)
12268#define SPDIFRX_DR1_DRNL2_Msk (0xFFFFU << SPDIFRX_DR1_DRNL2_Pos) /*!< 0x0000FFFF */
12269#define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk /*!<Data value Channel A */
12270
12271/******************* Bit definition for SPDIFRX_CSR register *******************/
12272#define SPDIFRX_CSR_USR_Pos (0U)
12273#define SPDIFRX_CSR_USR_Msk (0xFFFFU << SPDIFRX_CSR_USR_Pos) /*!< 0x0000FFFF */
12274#define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk /*!<User data information */
12275#define SPDIFRX_CSR_CS_Pos (16U)
12276#define SPDIFRX_CSR_CS_Msk (0xFFU << SPDIFRX_CSR_CS_Pos) /*!< 0x00FF0000 */
12277#define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk /*!<Channel A status information */
12278#define SPDIFRX_CSR_SOB_Pos (24U)
12279#define SPDIFRX_CSR_SOB_Msk (0x1U << SPDIFRX_CSR_SOB_Pos) /*!< 0x01000000 */
12280#define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk /*!<Start Of Block */
12281
12282/******************* Bit definition for SPDIFRX_DIR register *******************/
12283#define SPDIFRX_DIR_THI_Pos (0U)
12284#define SPDIFRX_DIR_THI_Msk (0x13FFU << SPDIFRX_DIR_THI_Pos) /*!< 0x000013FF */
12285#define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk /*!<Threshold LOW */
12286#define SPDIFRX_DIR_TLO_Pos (16U)
12287#define SPDIFRX_DIR_TLO_Msk (0x1FFFU << SPDIFRX_DIR_TLO_Pos) /*!< 0x1FFF0000 */
12288#define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk /*!<Threshold HIGH */
12289
12290
12291/******************************************************************************/
12292/* */
12293/* SD host Interface */
12294/* */
12295/******************************************************************************/
12296/****************** Bit definition for SDIO_POWER register ******************/
12297#define SDIO_POWER_PWRCTRL_Pos (0U)
12298#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
12299#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
12300#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
12301#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
12302
12303/****************** Bit definition for SDIO_CLKCR register ******************/
12304#define SDIO_CLKCR_CLKDIV_Pos (0U)
12305#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
12306#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
12307#define SDIO_CLKCR_CLKEN_Pos (8U)
12308#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
12309#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
12310#define SDIO_CLKCR_PWRSAV_Pos (9U)
12311#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
12312#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
12313#define SDIO_CLKCR_BYPASS_Pos (10U)
12314#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
12315#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
12316
12317#define SDIO_CLKCR_WIDBUS_Pos (11U)
12318#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
12319#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
12320#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
12321#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
12322
12323#define SDIO_CLKCR_NEGEDGE_Pos (13U)
12324#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
12325#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
12326#define SDIO_CLKCR_HWFC_EN_Pos (14U)
12327#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
12328#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
12329
12330/******************* Bit definition for SDIO_ARG register *******************/
12331#define SDIO_ARG_CMDARG_Pos (0U)
12332#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
12333#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
12334
12335/******************* Bit definition for SDIO_CMD register *******************/
12336#define SDIO_CMD_CMDINDEX_Pos (0U)
12337#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
12338#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
12339
12340#define SDIO_CMD_WAITRESP_Pos (6U)
12341#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
12342#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
12343#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
12344#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
12345
12346#define SDIO_CMD_WAITINT_Pos (8U)
12347#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
12348#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
12349#define SDIO_CMD_WAITPEND_Pos (9U)
12350#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
12351#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
12352#define SDIO_CMD_CPSMEN_Pos (10U)
12353#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
12354#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
12355#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
12356#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
12357#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
12358
12359/***************** Bit definition for SDIO_RESPCMD register *****************/
12360#define SDIO_RESPCMD_RESPCMD_Pos (0U)
12361#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
12362#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
12363
12364/****************** Bit definition for SDIO_RESP0 register ******************/
12365#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
12366#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
12367#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
12368
12369/****************** Bit definition for SDIO_RESP1 register ******************/
12370#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
12371#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
12372#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
12373
12374/****************** Bit definition for SDIO_RESP2 register ******************/
12375#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
12376#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
12377#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
12378
12379/****************** Bit definition for SDIO_RESP3 register ******************/
12380#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
12381#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
12382#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
12383
12384/****************** Bit definition for SDIO_RESP4 register ******************/
12385#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
12386#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
12387#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
12388
12389/****************** Bit definition for SDIO_DTIMER register *****************/
12390#define SDIO_DTIMER_DATATIME_Pos (0U)
12391#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
12392#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
12393
12394/****************** Bit definition for SDIO_DLEN register *******************/
12395#define SDIO_DLEN_DATALENGTH_Pos (0U)
12396#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
12397#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
12398
12399/****************** Bit definition for SDIO_DCTRL register ******************/
12400#define SDIO_DCTRL_DTEN_Pos (0U)
12401#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
12402#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
12403#define SDIO_DCTRL_DTDIR_Pos (1U)
12404#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
12405#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
12406#define SDIO_DCTRL_DTMODE_Pos (2U)
12407#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
12408#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
12409#define SDIO_DCTRL_DMAEN_Pos (3U)
12410#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
12411#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
12412
12413#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
12414#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
12415#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
12416#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
12417#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
12418#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
12419#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
12420
12421#define SDIO_DCTRL_RWSTART_Pos (8U)
12422#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
12423#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
12424#define SDIO_DCTRL_RWSTOP_Pos (9U)
12425#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
12426#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
12427#define SDIO_DCTRL_RWMOD_Pos (10U)
12428#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
12429#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
12430#define SDIO_DCTRL_SDIOEN_Pos (11U)
12431#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
12432#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
12433
12434/****************** Bit definition for SDIO_DCOUNT register *****************/
12435#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
12436#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
12437#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
12438
12439/****************** Bit definition for SDIO_STA register ********************/
12440#define SDIO_STA_CCRCFAIL_Pos (0U)
12441#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
12442#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
12443#define SDIO_STA_DCRCFAIL_Pos (1U)
12444#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
12445#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
12446#define SDIO_STA_CTIMEOUT_Pos (2U)
12447#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
12448#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
12449#define SDIO_STA_DTIMEOUT_Pos (3U)
12450#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
12451#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
12452#define SDIO_STA_TXUNDERR_Pos (4U)
12453#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
12454#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
12455#define SDIO_STA_RXOVERR_Pos (5U)
12456#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
12457#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
12458#define SDIO_STA_CMDREND_Pos (6U)
12459#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
12460#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
12461#define SDIO_STA_CMDSENT_Pos (7U)
12462#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
12463#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
12464#define SDIO_STA_DATAEND_Pos (8U)
12465#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
12466#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
12467#define SDIO_STA_DBCKEND_Pos (10U)
12468#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
12469#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
12470#define SDIO_STA_CMDACT_Pos (11U)
12471#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
12472#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
12473#define SDIO_STA_TXACT_Pos (12U)
12474#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
12475#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
12476#define SDIO_STA_RXACT_Pos (13U)
12477#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
12478#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
12479#define SDIO_STA_TXFIFOHE_Pos (14U)
12480#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
12481#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
12482#define SDIO_STA_RXFIFOHF_Pos (15U)
12483#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
12484#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
12485#define SDIO_STA_TXFIFOF_Pos (16U)
12486#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
12487#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
12488#define SDIO_STA_RXFIFOF_Pos (17U)
12489#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
12490#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
12491#define SDIO_STA_TXFIFOE_Pos (18U)
12492#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
12493#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
12494#define SDIO_STA_RXFIFOE_Pos (19U)
12495#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
12496#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
12497#define SDIO_STA_TXDAVL_Pos (20U)
12498#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
12499#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
12500#define SDIO_STA_RXDAVL_Pos (21U)
12501#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
12502#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
12503#define SDIO_STA_SDIOIT_Pos (22U)
12504#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
12505#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
12506
12507/******************* Bit definition for SDIO_ICR register *******************/
12508#define SDIO_ICR_CCRCFAILC_Pos (0U)
12509#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
12510#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
12511#define SDIO_ICR_DCRCFAILC_Pos (1U)
12512#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
12513#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
12514#define SDIO_ICR_CTIMEOUTC_Pos (2U)
12515#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
12516#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
12517#define SDIO_ICR_DTIMEOUTC_Pos (3U)
12518#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
12519#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
12520#define SDIO_ICR_TXUNDERRC_Pos (4U)
12521#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
12522#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
12523#define SDIO_ICR_RXOVERRC_Pos (5U)
12524#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
12525#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
12526#define SDIO_ICR_CMDRENDC_Pos (6U)
12527#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
12528#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
12529#define SDIO_ICR_CMDSENTC_Pos (7U)
12530#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
12531#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
12532#define SDIO_ICR_DATAENDC_Pos (8U)
12533#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
12534#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
12535#define SDIO_ICR_DBCKENDC_Pos (10U)
12536#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
12537#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
12538#define SDIO_ICR_SDIOITC_Pos (22U)
12539#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
12540#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
12541
12542/****************** Bit definition for SDIO_MASK register *******************/
12543#define SDIO_MASK_CCRCFAILIE_Pos (0U)
12544#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
12545#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
12546#define SDIO_MASK_DCRCFAILIE_Pos (1U)
12547#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
12548#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
12549#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
12550#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
12551#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
12552#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
12553#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
12554#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
12555#define SDIO_MASK_TXUNDERRIE_Pos (4U)
12556#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
12557#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
12558#define SDIO_MASK_RXOVERRIE_Pos (5U)
12559#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
12560#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
12561#define SDIO_MASK_CMDRENDIE_Pos (6U)
12562#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
12563#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
12564#define SDIO_MASK_CMDSENTIE_Pos (7U)
12565#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
12566#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
12567#define SDIO_MASK_DATAENDIE_Pos (8U)
12568#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
12569#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
12570#define SDIO_MASK_DBCKENDIE_Pos (10U)
12571#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
12572#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
12573#define SDIO_MASK_CMDACTIE_Pos (11U)
12574#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
12575#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
12576#define SDIO_MASK_TXACTIE_Pos (12U)
12577#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
12578#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
12579#define SDIO_MASK_RXACTIE_Pos (13U)
12580#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
12581#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
12582#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
12583#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
12584#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
12585#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
12586#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
12587#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
12588#define SDIO_MASK_TXFIFOFIE_Pos (16U)
12589#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
12590#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
12591#define SDIO_MASK_RXFIFOFIE_Pos (17U)
12592#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
12593#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
12594#define SDIO_MASK_TXFIFOEIE_Pos (18U)
12595#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
12596#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
12597#define SDIO_MASK_RXFIFOEIE_Pos (19U)
12598#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
12599#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
12600#define SDIO_MASK_TXDAVLIE_Pos (20U)
12601#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
12602#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
12603#define SDIO_MASK_RXDAVLIE_Pos (21U)
12604#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
12605#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
12606#define SDIO_MASK_SDIOITIE_Pos (22U)
12607#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
12608#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
12609
12610/***************** Bit definition for SDIO_FIFOCNT register *****************/
12611#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
12612#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
12613#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
12614
12615/****************** Bit definition for SDIO_FIFO register *******************/
12616#define SDIO_FIFO_FIFODATA_Pos (0U)
12617#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
12618#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
12619
12620/******************************************************************************/
12621/* */
12622/* Serial Peripheral Interface */
12623/* */
12624/******************************************************************************/
12625#define I2S_APB1_APB2_FEATURE /*!< I2S IP's are splited between RCC APB1 and APB2 interfaces */
12626
12627/******************* Bit definition for SPI_CR1 register ********************/
12628#define SPI_CR1_CPHA_Pos (0U)
12629#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
12630#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
12631#define SPI_CR1_CPOL_Pos (1U)
12632#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
12633#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
12634#define SPI_CR1_MSTR_Pos (2U)
12635#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
12636#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
12637
12638#define SPI_CR1_BR_Pos (3U)
12639#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
12640#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
12641#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
12642#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
12643#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
12644
12645#define SPI_CR1_SPE_Pos (6U)
12646#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
12647#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
12648#define SPI_CR1_LSBFIRST_Pos (7U)
12649#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
12650#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
12651#define SPI_CR1_SSI_Pos (8U)
12652#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
12653#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
12654#define SPI_CR1_SSM_Pos (9U)
12655#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
12656#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
12657#define SPI_CR1_RXONLY_Pos (10U)
12658#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
12659#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
12660#define SPI_CR1_DFF_Pos (11U)
12661#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
12662#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
12663#define SPI_CR1_CRCNEXT_Pos (12U)
12664#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
12665#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
12666#define SPI_CR1_CRCEN_Pos (13U)
12667#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
12668#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
12669#define SPI_CR1_BIDIOE_Pos (14U)
12670#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
12671#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
12672#define SPI_CR1_BIDIMODE_Pos (15U)
12673#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
12674#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
12675
12676/******************* Bit definition for SPI_CR2 register ********************/
12677#define SPI_CR2_RXDMAEN_Pos (0U)
12678#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
12679#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
12680#define SPI_CR2_TXDMAEN_Pos (1U)
12681#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
12682#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
12683#define SPI_CR2_SSOE_Pos (2U)
12684#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
12685#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
12686#define SPI_CR2_FRF_Pos (4U)
12687#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
12688#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
12689#define SPI_CR2_ERRIE_Pos (5U)
12690#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
12691#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
12692#define SPI_CR2_RXNEIE_Pos (6U)
12693#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
12694#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
12695#define SPI_CR2_TXEIE_Pos (7U)
12696#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
12697#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
12698
12699/******************** Bit definition for SPI_SR register ********************/
12700#define SPI_SR_RXNE_Pos (0U)
12701#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
12702#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
12703#define SPI_SR_TXE_Pos (1U)
12704#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
12705#define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
12706#define SPI_SR_CHSIDE_Pos (2U)
12707#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
12708#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
12709#define SPI_SR_UDR_Pos (3U)
12710#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
12711#define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
12712#define SPI_SR_CRCERR_Pos (4U)
12713#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
12714#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
12715#define SPI_SR_MODF_Pos (5U)
12716#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
12717#define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
12718#define SPI_SR_OVR_Pos (6U)
12719#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
12720#define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
12721#define SPI_SR_BSY_Pos (7U)
12722#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
12723#define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
12724#define SPI_SR_FRE_Pos (8U)
12725#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
12726#define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
12727
12728/******************** Bit definition for SPI_DR register ********************/
12729#define SPI_DR_DR_Pos (0U)
12730#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
12731#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
12732
12733/******************* Bit definition for SPI_CRCPR register ******************/
12734#define SPI_CRCPR_CRCPOLY_Pos (0U)
12735#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
12736#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
12737
12738/****************** Bit definition for SPI_RXCRCR register ******************/
12739#define SPI_RXCRCR_RXCRC_Pos (0U)
12740#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
12741#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
12742
12743/****************** Bit definition for SPI_TXCRCR register ******************/
12744#define SPI_TXCRCR_TXCRC_Pos (0U)
12745#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
12746#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
12747
12748/****************** Bit definition for SPI_I2SCFGR register *****************/
12749#define SPI_I2SCFGR_CHLEN_Pos (0U)
12750#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
12751#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
12752
12753#define SPI_I2SCFGR_DATLEN_Pos (1U)
12754#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
12755#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
12756#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
12757#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
12758
12759#define SPI_I2SCFGR_CKPOL_Pos (3U)
12760#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
12761#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
12762
12763#define SPI_I2SCFGR_I2SSTD_Pos (4U)
12764#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
12765#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
12766#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
12767#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
12768
12769#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
12770#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
12771#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
12772
12773#define SPI_I2SCFGR_I2SCFG_Pos (8U)
12774#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
12775#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
12776#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
12777#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
12778
12779#define SPI_I2SCFGR_I2SE_Pos (10U)
12780#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
12781#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
12782#define SPI_I2SCFGR_I2SMOD_Pos (11U)
12783#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
12784#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
12785#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
12786#define SPI_I2SCFGR_ASTRTEN_Msk (0x1U << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
12787#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
12788
12789/****************** Bit definition for SPI_I2SPR register *******************/
12790#define SPI_I2SPR_I2SDIV_Pos (0U)
12791#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
12792#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
12793#define SPI_I2SPR_ODD_Pos (8U)
12794#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
12795#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
12796#define SPI_I2SPR_MCKOE_Pos (9U)
12797#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
12798#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
12799
12800/******************************************************************************/
12801/* */
12802/* SYSCFG */
12803/* */
12804/******************************************************************************/
12805/****************** Bit definition for SYSCFG_MEMRMP register ***************/
12806#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
12807#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
12808#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
12809#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
12810#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
12811#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
12812#define SYSCFG_MEMRMP_UFB_MODE_Pos (8U)
12813#define SYSCFG_MEMRMP_UFB_MODE_Msk (0x1U << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */
12814#define SYSCFG_MEMRMP_UFB_MODE SYSCFG_MEMRMP_UFB_MODE_Msk /*!< User Flash Bank mode */
12815#define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
12816#define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
12817#define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC memory mapping swap */
12818#define SYSCFG_MEMRMP_SWP_FMC_0 (0x1U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
12819/* Legacy Defines */
12820#define SYSCFG_SWP_FMC SYSCFG_MEMRMP_SWP_FMC
12821/****************** Bit definition for SYSCFG_PMC register ******************/
12822#define SYSCFG_PMC_ADCxDC2_Pos (16U)
12823#define SYSCFG_PMC_ADCxDC2_Msk (0x7U << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
12824#define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */
12825#define SYSCFG_PMC_ADC1DC2_Pos (16U)
12826#define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
12827#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
12828#define SYSCFG_PMC_ADC2DC2_Pos (17U)
12829#define SYSCFG_PMC_ADC2DC2_Msk (0x1U << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */
12830#define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */
12831#define SYSCFG_PMC_ADC3DC2_Pos (18U)
12832#define SYSCFG_PMC_ADC3DC2_Msk (0x1U << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */
12833#define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */
12834
12835/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
12836#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
12837#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
12838#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
12839#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
12840#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
12841#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
12842#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
12843#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
12844#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
12845#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
12846#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
12847#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
12848/**
12849 * @brief EXTI0 configuration
12850 */
12851#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
12852#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
12853#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
12854#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
12855#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
12856#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
12857#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
12858#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
12859#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
12860#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
12861#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
12862
12863/**
12864 * @brief EXTI1 configuration
12865 */
12866#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
12867#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
12868#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
12869#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
12870#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
12871#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
12872#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
12873#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
12874#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
12875#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
12876#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
12877
12878/**
12879 * @brief EXTI2 configuration
12880 */
12881#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
12882#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
12883#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
12884#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
12885#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
12886#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
12887#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
12888#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
12889#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
12890#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
12891#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
12892
12893/**
12894 * @brief EXTI3 configuration
12895 */
12896#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
12897#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
12898#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
12899#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
12900#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
12901#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
12902#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
12903#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
12904#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
12905#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
12906#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
12907
12908/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
12909#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
12910#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
12911#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
12912#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
12913#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
12914#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
12915#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
12916#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
12917#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
12918#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
12919#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
12920#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
12921
12922/**
12923 * @brief EXTI4 configuration
12924 */
12925#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
12926#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
12927#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
12928#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
12929#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
12930#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
12931#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
12932#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
12933#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
12934#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
12935#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
12936
12937/**
12938 * @brief EXTI5 configuration
12939 */
12940#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
12941#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
12942#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
12943#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
12944#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
12945#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
12946#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
12947#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
12948#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
12949#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
12950#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
12951
12952/**
12953 * @brief EXTI6 configuration
12954 */
12955#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
12956#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
12957#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
12958#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
12959#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
12960#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
12961#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
12962#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
12963#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
12964#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
12965#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
12966
12967/**
12968 * @brief EXTI7 configuration
12969 */
12970#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
12971#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
12972#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
12973#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
12974#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
12975#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
12976#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
12977#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
12978#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
12979#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
12980#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
12981
12982/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
12983#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
12984#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
12985#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
12986#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
12987#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
12988#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
12989#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
12990#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
12991#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
12992#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
12993#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
12994#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
12995
12996/**
12997 * @brief EXTI8 configuration
12998 */
12999#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
13000#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
13001#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
13002#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
13003#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
13004#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
13005#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
13006#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
13007#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
13008#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
13009
13010/**
13011 * @brief EXTI9 configuration
13012 */
13013#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
13014#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
13015#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
13016#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
13017#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
13018#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
13019#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
13020#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
13021#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
13022#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
13023
13024/**
13025 * @brief EXTI10 configuration
13026 */
13027#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
13028#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
13029#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
13030#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
13031#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
13032#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
13033#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
13034#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
13035#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
13036#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
13037
13038/**
13039 * @brief EXTI11 configuration
13040 */
13041#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
13042#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
13043#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
13044#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
13045#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
13046#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
13047#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
13048#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
13049#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
13050#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
13051
13052
13053/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
13054#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
13055#define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
13056#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
13057#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
13058#define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
13059#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
13060#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
13061#define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
13062#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
13063#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
13064#define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
13065#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
13066
13067/**
13068 * @brief EXTI12 configuration
13069 */
13070#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
13071#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
13072#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
13073#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
13074#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
13075#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
13076#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
13077#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
13078#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
13079#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
13080
13081/**
13082 * @brief EXTI13 configuration
13083 */
13084#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
13085#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
13086#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
13087#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
13088#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
13089#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
13090#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
13091#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
13092#define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */
13093#define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */
13094
13095/**
13096 * @brief EXTI14 configuration
13097 */
13098#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
13099#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
13100#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
13101#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
13102#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
13103#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
13104#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
13105#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
13106#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
13107#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
13108
13109/**
13110 * @brief EXTI15 configuration
13111 */
13112#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
13113#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
13114#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
13115#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
13116#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
13117#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
13118#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
13119#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
13120#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
13121#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
13122
13123/****************** Bit definition for SYSCFG_CMPCR register ****************/
13124#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
13125#define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
13126#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
13127#define SYSCFG_CMPCR_READY_Pos (8U)
13128#define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
13129#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
13130/****************** Bit definition for SYSCFG_CFGR register ****************/
13131#define SYSCFG_CFGR_FMPI2C1_SCL_Pos (0U)
13132#define SYSCFG_CFGR_FMPI2C1_SCL_Msk (0x1U << SYSCFG_CFGR_FMPI2C1_SCL_Pos) /*!< 0x00000001 */
13133#define SYSCFG_CFGR_FMPI2C1_SCL SYSCFG_CFGR_FMPI2C1_SCL_Msk /*!<FM+ drive capability for FMPI2C1_SCL pin */
13134#define SYSCFG_CFGR_FMPI2C1_SDA_Pos (1U)
13135#define SYSCFG_CFGR_FMPI2C1_SDA_Msk (0x1U << SYSCFG_CFGR_FMPI2C1_SDA_Pos) /*!< 0x00000002 */
13136#define SYSCFG_CFGR_FMPI2C1_SDA SYSCFG_CFGR_FMPI2C1_SDA_Msk /*!<FM+ drive capability for FMPI2C1_SDA pin */
13137
13138
13139/******************************************************************************/
13140/* */
13141/* TIM */
13142/* */
13143/******************************************************************************/
13144/******************* Bit definition for TIM_CR1 register ********************/
13145#define TIM_CR1_CEN_Pos (0U)
13146#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
13147#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
13148#define TIM_CR1_UDIS_Pos (1U)
13149#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
13150#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
13151#define TIM_CR1_URS_Pos (2U)
13152#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
13153#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
13154#define TIM_CR1_OPM_Pos (3U)
13155#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
13156#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
13157#define TIM_CR1_DIR_Pos (4U)
13158#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
13159#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
13160
13161#define TIM_CR1_CMS_Pos (5U)
13162#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
13163#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
13164#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
13165#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
13166
13167#define TIM_CR1_ARPE_Pos (7U)
13168#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
13169#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
13170
13171#define TIM_CR1_CKD_Pos (8U)
13172#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
13173#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
13174#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
13175#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
13176
13177/******************* Bit definition for TIM_CR2 register ********************/
13178#define TIM_CR2_CCPC_Pos (0U)
13179#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
13180#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
13181#define TIM_CR2_CCUS_Pos (2U)
13182#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
13183#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
13184#define TIM_CR2_CCDS_Pos (3U)
13185#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
13186#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
13187
13188#define TIM_CR2_MMS_Pos (4U)
13189#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
13190#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
13191#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
13192#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
13193#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
13194
13195#define TIM_CR2_TI1S_Pos (7U)
13196#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
13197#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
13198#define TIM_CR2_OIS1_Pos (8U)
13199#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
13200#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
13201#define TIM_CR2_OIS1N_Pos (9U)
13202#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
13203#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
13204#define TIM_CR2_OIS2_Pos (10U)
13205#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
13206#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
13207#define TIM_CR2_OIS2N_Pos (11U)
13208#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
13209#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
13210#define TIM_CR2_OIS3_Pos (12U)
13211#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
13212#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
13213#define TIM_CR2_OIS3N_Pos (13U)
13214#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
13215#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
13216#define TIM_CR2_OIS4_Pos (14U)
13217#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
13218#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
13219
13220/******************* Bit definition for TIM_SMCR register *******************/
13221#define TIM_SMCR_SMS_Pos (0U)
13222#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
13223#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
13224#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
13225#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
13226#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
13227
13228#define TIM_SMCR_TS_Pos (4U)
13229#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
13230#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
13231#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
13232#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
13233#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
13234
13235#define TIM_SMCR_MSM_Pos (7U)
13236#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
13237#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
13238
13239#define TIM_SMCR_ETF_Pos (8U)
13240#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
13241#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
13242#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
13243#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
13244#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
13245#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
13246
13247#define TIM_SMCR_ETPS_Pos (12U)
13248#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
13249#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
13250#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
13251#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
13252
13253#define TIM_SMCR_ECE_Pos (14U)
13254#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
13255#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
13256#define TIM_SMCR_ETP_Pos (15U)
13257#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
13258#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
13259
13260/******************* Bit definition for TIM_DIER register *******************/
13261#define TIM_DIER_UIE_Pos (0U)
13262#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
13263#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
13264#define TIM_DIER_CC1IE_Pos (1U)
13265#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
13266#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
13267#define TIM_DIER_CC2IE_Pos (2U)
13268#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
13269#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
13270#define TIM_DIER_CC3IE_Pos (3U)
13271#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
13272#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
13273#define TIM_DIER_CC4IE_Pos (4U)
13274#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
13275#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
13276#define TIM_DIER_COMIE_Pos (5U)
13277#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
13278#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
13279#define TIM_DIER_TIE_Pos (6U)
13280#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
13281#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
13282#define TIM_DIER_BIE_Pos (7U)
13283#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
13284#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
13285#define TIM_DIER_UDE_Pos (8U)
13286#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
13287#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
13288#define TIM_DIER_CC1DE_Pos (9U)
13289#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
13290#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
13291#define TIM_DIER_CC2DE_Pos (10U)
13292#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
13293#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
13294#define TIM_DIER_CC3DE_Pos (11U)
13295#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
13296#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
13297#define TIM_DIER_CC4DE_Pos (12U)
13298#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
13299#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
13300#define TIM_DIER_COMDE_Pos (13U)
13301#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
13302#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
13303#define TIM_DIER_TDE_Pos (14U)
13304#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
13305#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
13306
13307/******************** Bit definition for TIM_SR register ********************/
13308#define TIM_SR_UIF_Pos (0U)
13309#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
13310#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
13311#define TIM_SR_CC1IF_Pos (1U)
13312#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
13313#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
13314#define TIM_SR_CC2IF_Pos (2U)
13315#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
13316#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
13317#define TIM_SR_CC3IF_Pos (3U)
13318#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
13319#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
13320#define TIM_SR_CC4IF_Pos (4U)
13321#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
13322#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
13323#define TIM_SR_COMIF_Pos (5U)
13324#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
13325#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
13326#define TIM_SR_TIF_Pos (6U)
13327#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
13328#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
13329#define TIM_SR_BIF_Pos (7U)
13330#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
13331#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
13332#define TIM_SR_CC1OF_Pos (9U)
13333#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
13334#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
13335#define TIM_SR_CC2OF_Pos (10U)
13336#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
13337#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
13338#define TIM_SR_CC3OF_Pos (11U)
13339#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
13340#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
13341#define TIM_SR_CC4OF_Pos (12U)
13342#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
13343#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
13344
13345/******************* Bit definition for TIM_EGR register ********************/
13346#define TIM_EGR_UG_Pos (0U)
13347#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
13348#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
13349#define TIM_EGR_CC1G_Pos (1U)
13350#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
13351#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
13352#define TIM_EGR_CC2G_Pos (2U)
13353#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
13354#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
13355#define TIM_EGR_CC3G_Pos (3U)
13356#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
13357#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
13358#define TIM_EGR_CC4G_Pos (4U)
13359#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
13360#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
13361#define TIM_EGR_COMG_Pos (5U)
13362#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
13363#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
13364#define TIM_EGR_TG_Pos (6U)
13365#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
13366#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
13367#define TIM_EGR_BG_Pos (7U)
13368#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
13369#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
13370
13371/****************** Bit definition for TIM_CCMR1 register *******************/
13372#define TIM_CCMR1_CC1S_Pos (0U)
13373#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
13374#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
13375#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
13376#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
13377
13378#define TIM_CCMR1_OC1FE_Pos (2U)
13379#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
13380#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
13381#define TIM_CCMR1_OC1PE_Pos (3U)
13382#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
13383#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
13384
13385#define TIM_CCMR1_OC1M_Pos (4U)
13386#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
13387#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
13388#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
13389#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
13390#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
13391
13392#define TIM_CCMR1_OC1CE_Pos (7U)
13393#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
13394#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
13395
13396#define TIM_CCMR1_CC2S_Pos (8U)
13397#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
13398#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
13399#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
13400#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
13401
13402#define TIM_CCMR1_OC2FE_Pos (10U)
13403#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
13404#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
13405#define TIM_CCMR1_OC2PE_Pos (11U)
13406#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
13407#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
13408
13409#define TIM_CCMR1_OC2M_Pos (12U)
13410#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
13411#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
13412#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
13413#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
13414#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
13415
13416#define TIM_CCMR1_OC2CE_Pos (15U)
13417#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
13418#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
13419
13420/*----------------------------------------------------------------------------*/
13421
13422#define TIM_CCMR1_IC1PSC_Pos (2U)
13423#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
13424#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
13425#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
13426#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
13427
13428#define TIM_CCMR1_IC1F_Pos (4U)
13429#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
13430#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
13431#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
13432#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
13433#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
13434#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
13435
13436#define TIM_CCMR1_IC2PSC_Pos (10U)
13437#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
13438#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
13439#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
13440#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
13441
13442#define TIM_CCMR1_IC2F_Pos (12U)
13443#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
13444#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
13445#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
13446#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
13447#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
13448#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
13449
13450/****************** Bit definition for TIM_CCMR2 register *******************/
13451#define TIM_CCMR2_CC3S_Pos (0U)
13452#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
13453#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
13454#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
13455#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
13456
13457#define TIM_CCMR2_OC3FE_Pos (2U)
13458#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
13459#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
13460#define TIM_CCMR2_OC3PE_Pos (3U)
13461#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
13462#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
13463
13464#define TIM_CCMR2_OC3M_Pos (4U)
13465#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
13466#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
13467#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
13468#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
13469#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
13470
13471#define TIM_CCMR2_OC3CE_Pos (7U)
13472#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
13473#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
13474
13475#define TIM_CCMR2_CC4S_Pos (8U)
13476#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
13477#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
13478#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
13479#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
13480
13481#define TIM_CCMR2_OC4FE_Pos (10U)
13482#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
13483#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
13484#define TIM_CCMR2_OC4PE_Pos (11U)
13485#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
13486#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
13487
13488#define TIM_CCMR2_OC4M_Pos (12U)
13489#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
13490#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
13491#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
13492#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
13493#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
13494
13495#define TIM_CCMR2_OC4CE_Pos (15U)
13496#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
13497#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
13498
13499/*----------------------------------------------------------------------------*/
13500
13501#define TIM_CCMR2_IC3PSC_Pos (2U)
13502#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
13503#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
13504#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
13505#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
13506
13507#define TIM_CCMR2_IC3F_Pos (4U)
13508#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
13509#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
13510#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
13511#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
13512#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
13513#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
13514
13515#define TIM_CCMR2_IC4PSC_Pos (10U)
13516#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
13517#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
13518#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
13519#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
13520
13521#define TIM_CCMR2_IC4F_Pos (12U)
13522#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
13523#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
13524#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
13525#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
13526#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
13527#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
13528
13529/******************* Bit definition for TIM_CCER register *******************/
13530#define TIM_CCER_CC1E_Pos (0U)
13531#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
13532#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
13533#define TIM_CCER_CC1P_Pos (1U)
13534#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
13535#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
13536#define TIM_CCER_CC1NE_Pos (2U)
13537#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
13538#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
13539#define TIM_CCER_CC1NP_Pos (3U)
13540#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
13541#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
13542#define TIM_CCER_CC2E_Pos (4U)
13543#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
13544#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
13545#define TIM_CCER_CC2P_Pos (5U)
13546#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
13547#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
13548#define TIM_CCER_CC2NE_Pos (6U)
13549#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
13550#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
13551#define TIM_CCER_CC2NP_Pos (7U)
13552#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
13553#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
13554#define TIM_CCER_CC3E_Pos (8U)
13555#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
13556#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
13557#define TIM_CCER_CC3P_Pos (9U)
13558#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
13559#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
13560#define TIM_CCER_CC3NE_Pos (10U)
13561#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
13562#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
13563#define TIM_CCER_CC3NP_Pos (11U)
13564#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
13565#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
13566#define TIM_CCER_CC4E_Pos (12U)
13567#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
13568#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
13569#define TIM_CCER_CC4P_Pos (13U)
13570#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
13571#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
13572#define TIM_CCER_CC4NP_Pos (15U)
13573#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
13574#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
13575
13576/******************* Bit definition for TIM_CNT register ********************/
13577#define TIM_CNT_CNT_Pos (0U)
13578#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
13579#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
13580
13581/******************* Bit definition for TIM_PSC register ********************/
13582#define TIM_PSC_PSC_Pos (0U)
13583#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
13584#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
13585
13586/******************* Bit definition for TIM_ARR register ********************/
13587#define TIM_ARR_ARR_Pos (0U)
13588#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
13589#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
13590
13591/******************* Bit definition for TIM_RCR register ********************/
13592#define TIM_RCR_REP_Pos (0U)
13593#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
13594#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
13595
13596/******************* Bit definition for TIM_CCR1 register *******************/
13597#define TIM_CCR1_CCR1_Pos (0U)
13598#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
13599#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
13600
13601/******************* Bit definition for TIM_CCR2 register *******************/
13602#define TIM_CCR2_CCR2_Pos (0U)
13603#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
13604#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
13605
13606/******************* Bit definition for TIM_CCR3 register *******************/
13607#define TIM_CCR3_CCR3_Pos (0U)
13608#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
13609#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
13610
13611/******************* Bit definition for TIM_CCR4 register *******************/
13612#define TIM_CCR4_CCR4_Pos (0U)
13613#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
13614#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
13615
13616/******************* Bit definition for TIM_BDTR register *******************/
13617#define TIM_BDTR_DTG_Pos (0U)
13618#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
13619#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
13620#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
13621#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
13622#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
13623#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
13624#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
13625#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
13626#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
13627#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
13628
13629#define TIM_BDTR_LOCK_Pos (8U)
13630#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
13631#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
13632#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
13633#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
13634
13635#define TIM_BDTR_OSSI_Pos (10U)
13636#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
13637#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
13638#define TIM_BDTR_OSSR_Pos (11U)
13639#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
13640#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
13641#define TIM_BDTR_BKE_Pos (12U)
13642#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
13643#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
13644#define TIM_BDTR_BKP_Pos (13U)
13645#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
13646#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
13647#define TIM_BDTR_AOE_Pos (14U)
13648#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
13649#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
13650#define TIM_BDTR_MOE_Pos (15U)
13651#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
13652#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
13653
13654/******************* Bit definition for TIM_DCR register ********************/
13655#define TIM_DCR_DBA_Pos (0U)
13656#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
13657#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
13658#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
13659#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
13660#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
13661#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
13662#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
13663
13664#define TIM_DCR_DBL_Pos (8U)
13665#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
13666#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
13667#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
13668#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
13669#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
13670#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
13671#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
13672
13673/******************* Bit definition for TIM_DMAR register *******************/
13674#define TIM_DMAR_DMAB_Pos (0U)
13675#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
13676#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
13677
13678/******************* Bit definition for TIM_OR register *********************/
13679#define TIM_OR_TI1_RMP_Pos (0U)
13680#define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
13681#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
13682#define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
13683#define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
13684
13685#define TIM_OR_TI4_RMP_Pos (6U)
13686#define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
13687#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
13688#define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
13689#define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
13690#define TIM_OR_ITR1_RMP_Pos (10U)
13691#define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
13692#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
13693#define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
13694#define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
13695
13696
13697/******************************************************************************/
13698/* */
13699/* Universal Synchronous Asynchronous Receiver Transmitter */
13700/* */
13701/******************************************************************************/
13702/******************* Bit definition for USART_SR register *******************/
13703#define USART_SR_PE_Pos (0U)
13704#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
13705#define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
13706#define USART_SR_FE_Pos (1U)
13707#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
13708#define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
13709#define USART_SR_NE_Pos (2U)
13710#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
13711#define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
13712#define USART_SR_ORE_Pos (3U)
13713#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
13714#define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
13715#define USART_SR_IDLE_Pos (4U)
13716#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
13717#define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
13718#define USART_SR_RXNE_Pos (5U)
13719#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
13720#define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
13721#define USART_SR_TC_Pos (6U)
13722#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
13723#define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
13724#define USART_SR_TXE_Pos (7U)
13725#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
13726#define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
13727#define USART_SR_LBD_Pos (8U)
13728#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
13729#define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
13730#define USART_SR_CTS_Pos (9U)
13731#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
13732#define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
13733
13734/******************* Bit definition for USART_DR register *******************/
13735#define USART_DR_DR_Pos (0U)
13736#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
13737#define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
13738
13739/****************** Bit definition for USART_BRR register *******************/
13740#define USART_BRR_DIV_Fraction_Pos (0U)
13741#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
13742#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
13743#define USART_BRR_DIV_Mantissa_Pos (4U)
13744#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
13745#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
13746
13747/****************** Bit definition for USART_CR1 register *******************/
13748#define USART_CR1_SBK_Pos (0U)
13749#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
13750#define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
13751#define USART_CR1_RWU_Pos (1U)
13752#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
13753#define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
13754#define USART_CR1_RE_Pos (2U)
13755#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
13756#define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
13757#define USART_CR1_TE_Pos (3U)
13758#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
13759#define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
13760#define USART_CR1_IDLEIE_Pos (4U)
13761#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
13762#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
13763#define USART_CR1_RXNEIE_Pos (5U)
13764#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
13765#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
13766#define USART_CR1_TCIE_Pos (6U)
13767#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
13768#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
13769#define USART_CR1_TXEIE_Pos (7U)
13770#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
13771#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */
13772#define USART_CR1_PEIE_Pos (8U)
13773#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
13774#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
13775#define USART_CR1_PS_Pos (9U)
13776#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
13777#define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
13778#define USART_CR1_PCE_Pos (10U)
13779#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
13780#define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
13781#define USART_CR1_WAKE_Pos (11U)
13782#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
13783#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
13784#define USART_CR1_M_Pos (12U)
13785#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
13786#define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
13787#define USART_CR1_UE_Pos (13U)
13788#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
13789#define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
13790#define USART_CR1_OVER8_Pos (15U)
13791#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
13792#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
13793
13794/****************** Bit definition for USART_CR2 register *******************/
13795#define USART_CR2_ADD_Pos (0U)
13796#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
13797#define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
13798#define USART_CR2_LBDL_Pos (5U)
13799#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
13800#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
13801#define USART_CR2_LBDIE_Pos (6U)
13802#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
13803#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
13804#define USART_CR2_LBCL_Pos (8U)
13805#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
13806#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
13807#define USART_CR2_CPHA_Pos (9U)
13808#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
13809#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
13810#define USART_CR2_CPOL_Pos (10U)
13811#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
13812#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
13813#define USART_CR2_CLKEN_Pos (11U)
13814#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
13815#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
13816
13817#define USART_CR2_STOP_Pos (12U)
13818#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
13819#define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
13820#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
13821#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
13822
13823#define USART_CR2_LINEN_Pos (14U)
13824#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
13825#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
13826
13827/****************** Bit definition for USART_CR3 register *******************/
13828#define USART_CR3_EIE_Pos (0U)
13829#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
13830#define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
13831#define USART_CR3_IREN_Pos (1U)
13832#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
13833#define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
13834#define USART_CR3_IRLP_Pos (2U)
13835#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
13836#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
13837#define USART_CR3_HDSEL_Pos (3U)
13838#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
13839#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
13840#define USART_CR3_NACK_Pos (4U)
13841#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
13842#define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
13843#define USART_CR3_SCEN_Pos (5U)
13844#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
13845#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
13846#define USART_CR3_DMAR_Pos (6U)
13847#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
13848#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
13849#define USART_CR3_DMAT_Pos (7U)
13850#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
13851#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
13852#define USART_CR3_RTSE_Pos (8U)
13853#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
13854#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
13855#define USART_CR3_CTSE_Pos (9U)
13856#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
13857#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
13858#define USART_CR3_CTSIE_Pos (10U)
13859#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
13860#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
13861#define USART_CR3_ONEBIT_Pos (11U)
13862#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
13863#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
13864
13865/****************** Bit definition for USART_GTPR register ******************/
13866#define USART_GTPR_PSC_Pos (0U)
13867#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
13868#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
13869#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
13870#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
13871#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
13872#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
13873#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
13874#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
13875#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
13876#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
13877
13878#define USART_GTPR_GT_Pos (8U)
13879#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
13880#define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
13881
13882/******************************************************************************/
13883/* */
13884/* Window WATCHDOG */
13885/* */
13886/******************************************************************************/
13887/******************* Bit definition for WWDG_CR register ********************/
13888#define WWDG_CR_T_Pos (0U)
13889#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
13890#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
13891#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
13892#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
13893#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
13894#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
13895#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
13896#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
13897#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
13898/* Legacy defines */
13899#define WWDG_CR_T0 WWDG_CR_T_0
13900#define WWDG_CR_T1 WWDG_CR_T_1
13901#define WWDG_CR_T2 WWDG_CR_T_2
13902#define WWDG_CR_T3 WWDG_CR_T_3
13903#define WWDG_CR_T4 WWDG_CR_T_4
13904#define WWDG_CR_T5 WWDG_CR_T_5
13905#define WWDG_CR_T6 WWDG_CR_T_6
13906
13907#define WWDG_CR_WDGA_Pos (7U)
13908#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
13909#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
13910
13911/******************* Bit definition for WWDG_CFR register *******************/
13912#define WWDG_CFR_W_Pos (0U)
13913#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
13914#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
13915#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
13916#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
13917#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
13918#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
13919#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
13920#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
13921#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
13922/* Legacy defines */
13923#define WWDG_CFR_W0 WWDG_CFR_W_0
13924#define WWDG_CFR_W1 WWDG_CFR_W_1
13925#define WWDG_CFR_W2 WWDG_CFR_W_2
13926#define WWDG_CFR_W3 WWDG_CFR_W_3
13927#define WWDG_CFR_W4 WWDG_CFR_W_4
13928#define WWDG_CFR_W5 WWDG_CFR_W_5
13929#define WWDG_CFR_W6 WWDG_CFR_W_6
13930
13931#define WWDG_CFR_WDGTB_Pos (7U)
13932#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
13933#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
13934#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
13935#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
13936/* Legacy defines */
13937#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
13938#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
13939
13940#define WWDG_CFR_EWI_Pos (9U)
13941#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
13942#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
13943
13944/******************* Bit definition for WWDG_SR register ********************/
13945#define WWDG_SR_EWIF_Pos (0U)
13946#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
13947#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
13948
13949
13950/******************************************************************************/
13951/* */
13952/* DBG */
13953/* */
13954/******************************************************************************/
13955/******************** Bit definition for DBGMCU_IDCODE register *************/
13956#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
13957#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
13958#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
13959#define DBGMCU_IDCODE_REV_ID_Pos (16U)
13960#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
13961#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
13962
13963/******************** Bit definition for DBGMCU_CR register *****************/
13964#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
13965#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
13966#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
13967#define DBGMCU_CR_DBG_STOP_Pos (1U)
13968#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
13969#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
13970#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
13971#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
13972#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
13973#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
13974#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
13975#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
13976
13977#define DBGMCU_CR_TRACE_MODE_Pos (6U)
13978#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
13979#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
13980#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
13981#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
13982
13983/******************** Bit definition for DBGMCU_APB1_FZ register ************/
13984#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
13985#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
13986#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
13987#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
13988#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
13989#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
13990#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
13991#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
13992#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
13993#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
13994#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
13995#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
13996#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
13997#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
13998#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
13999#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
14000#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
14001#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
14002#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
14003#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
14004#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
14005#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
14006#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
14007#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
14008#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
14009#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
14010#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
14011#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
14012#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
14013#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
14014#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
14015#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
14016#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
14017#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
14018#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
14019#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
14020#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
14021#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
14022#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
14023#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
14024#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
14025#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
14026#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
14027#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
14028#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
14029#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
14030#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
14031#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
14032#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
14033#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
14034#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
14035#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
14036#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
14037#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
14038/* Old IWDGSTOP bit definition, maintained for legacy purpose */
14039#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
14040
14041/******************** Bit definition for DBGMCU_APB2_FZ register ************/
14042#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
14043#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
14044#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
14045#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
14046#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
14047#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
14048#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
14049#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
14050#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
14051#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
14052#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
14053#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
14054#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
14055#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
14056#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
14057
14058/******************************************************************************/
14059/* */
14060/* USB_OTG */
14061/* */
14062/******************************************************************************/
14063/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
14064#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
14065#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
14066#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
14067#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
14068#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
14069#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
14070#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
14071#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
14072#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
14073#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
14074#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
14075#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
14076#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
14077#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
14078#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
14079#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
14080#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
14081#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
14082#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
14083#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
14084#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
14085#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
14086#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
14087#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
14088#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
14089#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
14090#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
14091#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
14092#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
14093#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
14094#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
14095#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
14096#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
14097#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
14098#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
14099#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
14100#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
14101#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
14102#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
14103#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
14104#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
14105#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
14106#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
14107#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
14108#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
14109#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
14110#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
14111#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
14112#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
14113#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
14114#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
14115#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
14116#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
14117#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
14118
14119/******************** Bit definition forUSB_OTG_HCFG register ********************/
14120
14121#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
14122#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
14123#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
14124#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
14125#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
14126#define USB_OTG_HCFG_FSLSS_Pos (2U)
14127#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
14128#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
14129
14130/******************** Bit definition for USB_OTG_DCFG register ********************/
14131
14132#define USB_OTG_DCFG_DSPD_Pos (0U)
14133#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
14134#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
14135#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
14136#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
14137#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
14138#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
14139#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
14140
14141#define USB_OTG_DCFG_DAD_Pos (4U)
14142#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
14143#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
14144#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
14145#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
14146#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
14147#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
14148#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
14149#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
14150#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
14151
14152#define USB_OTG_DCFG_PFIVL_Pos (11U)
14153#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
14154#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
14155#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
14156#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
14157
14158#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
14159#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
14160#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
14161#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
14162#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
14163
14164/******************** Bit definition for USB_OTG_PCGCR register ********************/
14165#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
14166#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
14167#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
14168#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
14169#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
14170#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
14171#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
14172#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
14173#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
14174
14175/******************** Bit definition for USB_OTG_GOTGINT register ********************/
14176#define USB_OTG_GOTGINT_SEDET_Pos (2U)
14177#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
14178#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
14179#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
14180#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
14181#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
14182#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
14183#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
14184#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
14185#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
14186#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
14187#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
14188#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
14189#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
14190#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
14191#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
14192#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
14193#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
14194#define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
14195#define USB_OTG_GOTGINT_IDCHNG_Msk (0x1U << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
14196#define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */
14197
14198/******************** Bit definition for USB_OTG_DCTL register ********************/
14199#define USB_OTG_DCTL_RWUSIG_Pos (0U)
14200#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
14201#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
14202#define USB_OTG_DCTL_SDIS_Pos (1U)
14203#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
14204#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
14205#define USB_OTG_DCTL_GINSTS_Pos (2U)
14206#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
14207#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
14208#define USB_OTG_DCTL_GONSTS_Pos (3U)
14209#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
14210#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
14211
14212#define USB_OTG_DCTL_TCTL_Pos (4U)
14213#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
14214#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
14215#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
14216#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
14217#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
14218#define USB_OTG_DCTL_SGINAK_Pos (7U)
14219#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
14220#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
14221#define USB_OTG_DCTL_CGINAK_Pos (8U)
14222#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
14223#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
14224#define USB_OTG_DCTL_SGONAK_Pos (9U)
14225#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
14226#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
14227#define USB_OTG_DCTL_CGONAK_Pos (10U)
14228#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
14229#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
14230#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
14231#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
14232#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
14233
14234/******************** Bit definition for USB_OTG_HFIR register ********************/
14235#define USB_OTG_HFIR_FRIVL_Pos (0U)
14236#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
14237#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
14238
14239/******************** Bit definition for USB_OTG_HFNUM register ********************/
14240#define USB_OTG_HFNUM_FRNUM_Pos (0U)
14241#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
14242#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
14243#define USB_OTG_HFNUM_FTREM_Pos (16U)
14244#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
14245#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
14246
14247/******************** Bit definition for USB_OTG_DSTS register ********************/
14248#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
14249#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
14250#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
14251
14252#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
14253#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
14254#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
14255#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
14256#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
14257#define USB_OTG_DSTS_EERR_Pos (3U)
14258#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
14259#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
14260#define USB_OTG_DSTS_FNSOF_Pos (8U)
14261#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
14262#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
14263
14264/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
14265#define USB_OTG_GAHBCFG_GINT_Pos (0U)
14266#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
14267#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
14268#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
14269#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
14270#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
14271#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
14272#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
14273#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
14274#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
14275#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
14276#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
14277#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
14278#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
14279#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
14280#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
14281#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
14282#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
14283#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
14284#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
14285
14286/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
14287
14288#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
14289#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
14290#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
14291#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
14292#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
14293#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
14294#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
14295#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
14296#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
14297#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
14298#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
14299#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
14300#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
14301#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
14302#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
14303#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
14304#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
14305#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
14306#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
14307#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
14308#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
14309#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
14310#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
14311#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
14312#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
14313#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
14314#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
14315#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
14316#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
14317#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
14318#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
14319#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
14320#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
14321#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
14322#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
14323#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
14324#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
14325#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
14326#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
14327#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
14328#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
14329#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
14330#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
14331#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
14332#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
14333#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
14334#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
14335#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
14336#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
14337#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
14338#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
14339#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
14340#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
14341#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
14342#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
14343#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
14344#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
14345#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
14346#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
14347#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
14348#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
14349
14350/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
14351#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
14352#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
14353#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
14354#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
14355#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
14356#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
14357#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
14358#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
14359#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
14360#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
14361#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
14362#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
14363#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
14364#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
14365#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
14366
14367
14368#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
14369#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
14370#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
14371#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
14372#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
14373#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
14374#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
14375#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
14376#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
14377#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
14378#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
14379#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
14380#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
14381#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
14382
14383/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
14384#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
14385#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
14386#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
14387#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
14388#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
14389#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
14390#define USB_OTG_DIEPMSK_TOM_Pos (3U)
14391#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
14392#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
14393#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
14394#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
14395#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
14396#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
14397#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
14398#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
14399#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
14400#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
14401#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
14402#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
14403#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
14404#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
14405#define USB_OTG_DIEPMSK_BIM_Pos (9U)
14406#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
14407#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
14408
14409/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
14410#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
14411#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
14412#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
14413#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
14414#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
14415#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
14416#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
14417#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
14418#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
14419#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
14420#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
14421#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
14422#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
14423#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
14424
14425#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
14426#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
14427#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
14428#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
14429#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
14430#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
14431#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
14432#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
14433#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
14434#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
14435#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
14436
14437/******************** Bit definition for USB_OTG_HAINT register ********************/
14438#define USB_OTG_HAINT_HAINT_Pos (0U)
14439#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
14440#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
14441
14442/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
14443#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
14444#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
14445#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
14446#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
14447#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
14448#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
14449#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
14450#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
14451#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
14452#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
14453#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
14454#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
14455#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
14456#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
14457#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
14458#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
14459#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
14460#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
14461#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
14462#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
14463#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
14464#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
14465#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
14466#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
14467
14468/******************** Bit definition for USB_OTG_GINTSTS register ********************/
14469#define USB_OTG_GINTSTS_CMOD_Pos (0U)
14470#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
14471#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
14472#define USB_OTG_GINTSTS_MMIS_Pos (1U)
14473#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
14474#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
14475#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
14476#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
14477#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
14478#define USB_OTG_GINTSTS_SOF_Pos (3U)
14479#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
14480#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
14481#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
14482#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
14483#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
14484#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
14485#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
14486#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
14487#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
14488#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
14489#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
14490#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
14491#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
14492#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
14493#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
14494#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
14495#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
14496#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
14497#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
14498#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
14499#define USB_OTG_GINTSTS_USBRST_Pos (12U)
14500#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
14501#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
14502#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
14503#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
14504#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
14505#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
14506#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
14507#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
14508#define USB_OTG_GINTSTS_EOPF_Pos (15U)
14509#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
14510#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
14511#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
14512#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
14513#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
14514#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
14515#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
14516#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
14517#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
14518#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
14519#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
14520#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
14521#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
14522#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
14523#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
14524#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
14525#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
14526#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
14527#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
14528#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
14529#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
14530#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
14531#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
14532#define USB_OTG_GINTSTS_HCINT_Pos (25U)
14533#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
14534#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
14535#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
14536#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
14537#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
14538#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
14539#define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
14540#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
14541#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
14542#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
14543#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
14544#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
14545#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
14546#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
14547#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
14548#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
14549#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
14550#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
14551#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
14552#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
14553
14554/******************** Bit definition for USB_OTG_GINTMSK register ********************/
14555#define USB_OTG_GINTMSK_MMISM_Pos (1U)
14556#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
14557#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
14558#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
14559#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
14560#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
14561#define USB_OTG_GINTMSK_SOFM_Pos (3U)
14562#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
14563#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
14564#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
14565#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
14566#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
14567#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
14568#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
14569#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
14570#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
14571#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
14572#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
14573#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
14574#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
14575#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
14576#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
14577#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
14578#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
14579#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
14580#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
14581#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
14582#define USB_OTG_GINTMSK_USBRST_Pos (12U)
14583#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
14584#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
14585#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
14586#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
14587#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
14588#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
14589#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
14590#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
14591#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
14592#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
14593#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
14594#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
14595#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
14596#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
14597#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
14598#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
14599#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
14600#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
14601#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
14602#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
14603#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
14604#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
14605#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
14606#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
14607#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
14608#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
14609#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
14610#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
14611#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
14612#define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
14613#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1U << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
14614#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */
14615#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
14616#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
14617#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
14618#define USB_OTG_GINTMSK_HCIM_Pos (25U)
14619#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
14620#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
14621#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
14622#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
14623#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
14624#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
14625#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
14626#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
14627#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
14628#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
14629#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
14630#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
14631#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
14632#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
14633#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
14634#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
14635#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
14636#define USB_OTG_GINTMSK_WUIM_Pos (31U)
14637#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
14638#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
14639
14640/******************** Bit definition for USB_OTG_DAINT register ********************/
14641#define USB_OTG_DAINT_IEPINT_Pos (0U)
14642#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
14643#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
14644#define USB_OTG_DAINT_OEPINT_Pos (16U)
14645#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
14646#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
14647
14648/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
14649#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
14650#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
14651#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
14652
14653/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
14654#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
14655#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
14656#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
14657#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
14658#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
14659#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
14660#define USB_OTG_GRXSTSP_DPID_Pos (15U)
14661#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
14662#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
14663#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
14664#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
14665#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
14666
14667/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
14668#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
14669#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
14670#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
14671#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
14672#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
14673#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
14674
14675/******************** Bit definition for OTG register ********************/
14676
14677#define USB_OTG_CHNUM_Pos (0U)
14678#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
14679#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
14680#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
14681#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
14682#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
14683#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
14684#define USB_OTG_BCNT_Pos (4U)
14685#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
14686#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
14687
14688#define USB_OTG_DPID_Pos (15U)
14689#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
14690#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
14691#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
14692#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
14693
14694#define USB_OTG_PKTSTS_Pos (17U)
14695#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
14696#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
14697#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
14698#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
14699#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
14700#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
14701
14702#define USB_OTG_EPNUM_Pos (0U)
14703#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
14704#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
14705#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
14706#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
14707#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
14708#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
14709
14710#define USB_OTG_FRMNUM_Pos (21U)
14711#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
14712#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
14713#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
14714#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
14715#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
14716#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
14717
14718/******************** Bit definition for OTG register ********************/
14719
14720#define USB_OTG_CHNUM_Pos (0U)
14721#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
14722#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
14723#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
14724#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
14725#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
14726#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
14727#define USB_OTG_BCNT_Pos (4U)
14728#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
14729#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
14730
14731#define USB_OTG_DPID_Pos (15U)
14732#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
14733#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
14734#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
14735#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
14736
14737#define USB_OTG_PKTSTS_Pos (17U)
14738#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
14739#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
14740#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
14741#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
14742#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
14743#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
14744
14745#define USB_OTG_EPNUM_Pos (0U)
14746#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
14747#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
14748#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
14749#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
14750#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
14751#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
14752
14753#define USB_OTG_FRMNUM_Pos (21U)
14754#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
14755#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
14756#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
14757#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
14758#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
14759#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
14760
14761/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
14762#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
14763#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
14764#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
14765
14766/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
14767#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
14768#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
14769#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
14770
14771/******************** Bit definition for OTG register ********************/
14772#define USB_OTG_NPTXFSA_Pos (0U)
14773#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
14774#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
14775#define USB_OTG_NPTXFD_Pos (16U)
14776#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
14777#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
14778#define USB_OTG_TX0FSA_Pos (0U)
14779#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
14780#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
14781#define USB_OTG_TX0FD_Pos (16U)
14782#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
14783#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
14784
14785/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
14786#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
14787#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
14788#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
14789
14790/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
14791#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
14792#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
14793#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
14794
14795#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
14796#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
14797#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
14798#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
14799#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
14800#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
14801#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
14802#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
14803#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
14804#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
14805#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
14806
14807#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
14808#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
14809#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
14810#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
14811#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
14812#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
14813#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
14814#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
14815#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
14816#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
14817
14818/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
14819#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
14820#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
14821#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
14822#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
14823#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
14824#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
14825
14826#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
14827#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
14828#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
14829#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
14830#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
14831#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
14832#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
14833#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
14834#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
14835#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
14836#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
14837#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
14838#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
14839#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
14840#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
14841
14842#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
14843#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
14844#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
14845#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
14846#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
14847#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
14848#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
14849#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
14850#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
14851#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
14852#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
14853#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
14854#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
14855#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
14856#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
14857
14858/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
14859#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
14860#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
14861#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
14862
14863/******************** Bit definition for USB_OTG_DEACHINT register ********************/
14864#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
14865#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
14866#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
14867#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
14868#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
14869#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
14870
14871/******************** Bit definition for USB_OTG_GCCFG register ********************/
14872#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
14873#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
14874#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
14875#define USB_OTG_GCCFG_VBDEN_Pos (21U)
14876#define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
14877#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< USB VBUS Detection Enable */
14878
14879/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
14880#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
14881#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
14882#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
14883#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
14884#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
14885#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
14886
14887/******************** Bit definition for USB_OTG_CID register ********************/
14888#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
14889#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
14890#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
14891
14892/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
14893#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
14894#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
14895#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
14896#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
14897#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
14898#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
14899#define USB_OTG_GLPMCFG_BESL_Pos (2U)
14900#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
14901#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
14902#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
14903#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
14904#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
14905#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
14906#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
14907#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
14908#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
14909#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
14910#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
14911#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
14912#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
14913#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
14914#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
14915#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
14916#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
14917#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
14918#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
14919#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
14920#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
14921#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
14922#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
14923#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
14924#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
14925#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
14926#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
14927#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
14928#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
14929#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
14930#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
14931#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
14932#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
14933#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
14934#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
14935#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
14936#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
14937#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
14938
14939/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
14940#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
14941#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
14942#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
14943#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
14944#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
14945#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
14946#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
14947#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
14948#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
14949#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
14950#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
14951#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
14952#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
14953#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
14954#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
14955#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
14956#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
14957#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
14958#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
14959#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
14960#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
14961#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
14962#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
14963#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
14964#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
14965#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
14966#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
14967
14968/******************** Bit definition for USB_OTG_HPRT register ********************/
14969#define USB_OTG_HPRT_PCSTS_Pos (0U)
14970#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
14971#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
14972#define USB_OTG_HPRT_PCDET_Pos (1U)
14973#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
14974#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
14975#define USB_OTG_HPRT_PENA_Pos (2U)
14976#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
14977#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
14978#define USB_OTG_HPRT_PENCHNG_Pos (3U)
14979#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
14980#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
14981#define USB_OTG_HPRT_POCA_Pos (4U)
14982#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
14983#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
14984#define USB_OTG_HPRT_POCCHNG_Pos (5U)
14985#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
14986#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
14987#define USB_OTG_HPRT_PRES_Pos (6U)
14988#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
14989#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
14990#define USB_OTG_HPRT_PSUSP_Pos (7U)
14991#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
14992#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
14993#define USB_OTG_HPRT_PRST_Pos (8U)
14994#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
14995#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
14996
14997#define USB_OTG_HPRT_PLSTS_Pos (10U)
14998#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
14999#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
15000#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
15001#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
15002#define USB_OTG_HPRT_PPWR_Pos (12U)
15003#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
15004#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
15005
15006#define USB_OTG_HPRT_PTCTL_Pos (13U)
15007#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
15008#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
15009#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
15010#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
15011#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
15012#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
15013
15014#define USB_OTG_HPRT_PSPD_Pos (17U)
15015#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
15016#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
15017#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
15018#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
15019
15020/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
15021#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
15022#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
15023#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
15024#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
15025#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
15026#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
15027#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
15028#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
15029#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
15030#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
15031#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
15032#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
15033#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
15034#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
15035#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
15036#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
15037#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
15038#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
15039#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
15040#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
15041#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
15042#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
15043#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
15044#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
15045#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
15046#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
15047#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
15048#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
15049#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
15050#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
15051#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
15052#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
15053#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
15054
15055/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
15056#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
15057#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
15058#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
15059#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
15060#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
15061#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
15062
15063/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
15064#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
15065#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
15066#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
15067#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
15068#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
15069#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
15070#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
15071#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
15072#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
15073#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
15074#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
15075#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
15076
15077#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
15078#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
15079#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
15080#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
15081#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
15082#define USB_OTG_DIEPCTL_STALL_Pos (21U)
15083#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
15084#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
15085
15086#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
15087#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
15088#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
15089#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
15090#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
15091#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
15092#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
15093#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
15094#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
15095#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
15096#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
15097#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
15098#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
15099#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
15100#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
15101#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
15102#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
15103#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
15104#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
15105#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
15106#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
15107#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
15108#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
15109#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
15110#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
15111
15112/******************** Bit definition for USB_OTG_HCCHAR register ********************/
15113#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
15114#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
15115#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
15116
15117#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
15118#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
15119#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
15120#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
15121#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
15122#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
15123#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
15124#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
15125#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
15126#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
15127#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
15128#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
15129#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
15130
15131#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
15132#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
15133#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
15134#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
15135#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
15136
15137#define USB_OTG_HCCHAR_MC_Pos (20U)
15138#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
15139#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
15140#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
15141#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
15142
15143#define USB_OTG_HCCHAR_DAD_Pos (22U)
15144#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
15145#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
15146#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
15147#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
15148#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
15149#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
15150#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
15151#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
15152#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
15153#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
15154#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
15155#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
15156#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
15157#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
15158#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
15159#define USB_OTG_HCCHAR_CHENA_Pos (31U)
15160#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
15161#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
15162
15163/******************** Bit definition for USB_OTG_HCSPLT register ********************/
15164
15165#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
15166#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
15167#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
15168#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
15169#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
15170#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
15171#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
15172#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
15173#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
15174#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
15175
15176#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
15177#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
15178#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
15179#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
15180#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
15181#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
15182#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
15183#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
15184#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
15185#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
15186
15187#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
15188#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
15189#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
15190#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
15191#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
15192#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
15193#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
15194#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
15195#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
15196#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
15197#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
15198
15199/******************** Bit definition for USB_OTG_HCINT register ********************/
15200#define USB_OTG_HCINT_XFRC_Pos (0U)
15201#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
15202#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
15203#define USB_OTG_HCINT_CHH_Pos (1U)
15204#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
15205#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
15206#define USB_OTG_HCINT_AHBERR_Pos (2U)
15207#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
15208#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
15209#define USB_OTG_HCINT_STALL_Pos (3U)
15210#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
15211#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
15212#define USB_OTG_HCINT_NAK_Pos (4U)
15213#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
15214#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
15215#define USB_OTG_HCINT_ACK_Pos (5U)
15216#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
15217#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
15218#define USB_OTG_HCINT_NYET_Pos (6U)
15219#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
15220#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
15221#define USB_OTG_HCINT_TXERR_Pos (7U)
15222#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
15223#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
15224#define USB_OTG_HCINT_BBERR_Pos (8U)
15225#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
15226#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
15227#define USB_OTG_HCINT_FRMOR_Pos (9U)
15228#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
15229#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
15230#define USB_OTG_HCINT_DTERR_Pos (10U)
15231#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
15232#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
15233
15234/******************** Bit definition for USB_OTG_DIEPINT register ********************/
15235#define USB_OTG_DIEPINT_XFRC_Pos (0U)
15236#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
15237#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
15238#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
15239#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
15240#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
15241#define USB_OTG_DIEPINT_TOC_Pos (3U)
15242#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
15243#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
15244#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
15245#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
15246#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
15247#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
15248#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
15249#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
15250#define USB_OTG_DIEPINT_TXFE_Pos (7U)
15251#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
15252#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
15253#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
15254#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
15255#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
15256#define USB_OTG_DIEPINT_BNA_Pos (9U)
15257#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
15258#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
15259#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
15260#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
15261#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
15262#define USB_OTG_DIEPINT_BERR_Pos (12U)
15263#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
15264#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
15265#define USB_OTG_DIEPINT_NAK_Pos (13U)
15266#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
15267#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
15268
15269/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
15270#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
15271#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
15272#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
15273#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
15274#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
15275#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
15276#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
15277#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
15278#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
15279#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
15280#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
15281#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
15282#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
15283#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
15284#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
15285#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
15286#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
15287#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
15288#define USB_OTG_HCINTMSK_NYET_Pos (6U)
15289#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
15290#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
15291#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
15292#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
15293#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
15294#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
15295#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
15296#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
15297#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
15298#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
15299#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
15300#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
15301#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
15302#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
15303
15304/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
15305
15306#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
15307#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
15308#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
15309#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
15310#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
15311#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
15312#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
15313#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
15314#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
15315/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
15316#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
15317#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
15318#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
15319#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
15320#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
15321#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
15322#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
15323#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
15324#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
15325#define USB_OTG_HCTSIZ_DPID_Pos (29U)
15326#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
15327#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
15328#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
15329#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
15330
15331/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
15332#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
15333#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
15334#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
15335
15336/******************** Bit definition for USB_OTG_HCDMA register ********************/
15337#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
15338#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
15339#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
15340
15341/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
15342#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
15343#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
15344#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
15345
15346/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
15347#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
15348#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
15349#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
15350#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
15351#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
15352#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
15353
15354/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
15355
15356#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
15357#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
15358#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
15359#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
15360#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
15361#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
15362#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
15363#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
15364#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
15365#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
15366#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
15367#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
15368#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
15369#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
15370#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
15371#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
15372#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
15373#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
15374#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
15375#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
15376#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
15377#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
15378#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
15379#define USB_OTG_DOEPCTL_STALL_Pos (21U)
15380#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
15381#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
15382#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
15383#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
15384#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
15385#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
15386#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
15387#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
15388#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
15389#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
15390#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
15391#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
15392#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
15393#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
15394
15395/******************** Bit definition for USB_OTG_DOEPINT register ********************/
15396#define USB_OTG_DOEPINT_XFRC_Pos (0U)
15397#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
15398#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
15399#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
15400#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
15401#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
15402#define USB_OTG_DOEPINT_STUP_Pos (3U)
15403#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
15404#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
15405#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
15406#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
15407#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
15408#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
15409#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
15410#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */
15411#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
15412#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
15413#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
15414#define USB_OTG_DOEPINT_NYET_Pos (14U)
15415#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
15416#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
15417
15418/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
15419
15420#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
15421#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
15422#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
15423#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
15424#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
15425#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
15426
15427#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
15428#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
15429#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
15430#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
15431#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
15432
15433/******************** Bit definition for PCGCCTL register ********************/
15434#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
15435#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
15436#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
15437#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
15438#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
15439#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
15440#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
15441#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
15442#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
15443
15444/**
15445 * @}
15446 */
15447
15448/**
15449 * @}
15450 */
15451
15452/** @addtogroup Exported_macros
15453 * @{
15454 */
15455
15456/******************************* ADC Instances ********************************/
15457#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
15458 ((INSTANCE) == ADC2) || \
15459 ((INSTANCE) == ADC3))
15460
15461#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
15462
15463#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
15464
15465/******************************* CAN Instances ********************************/
15466#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
15467 ((INSTANCE) == CAN2))
15468/******************************* CRC Instances ********************************/
15469#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
15470
15471/******************************* DAC Instances ********************************/
15472#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
15473
15474/******************************* DCMI Instances *******************************/
15475#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
15476
15477/******************************** DMA Instances *******************************/
15478#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
15479 ((INSTANCE) == DMA1_Stream1) || \
15480 ((INSTANCE) == DMA1_Stream2) || \
15481 ((INSTANCE) == DMA1_Stream3) || \
15482 ((INSTANCE) == DMA1_Stream4) || \
15483 ((INSTANCE) == DMA1_Stream5) || \
15484 ((INSTANCE) == DMA1_Stream6) || \
15485 ((INSTANCE) == DMA1_Stream7) || \
15486 ((INSTANCE) == DMA2_Stream0) || \
15487 ((INSTANCE) == DMA2_Stream1) || \
15488 ((INSTANCE) == DMA2_Stream2) || \
15489 ((INSTANCE) == DMA2_Stream3) || \
15490 ((INSTANCE) == DMA2_Stream4) || \
15491 ((INSTANCE) == DMA2_Stream5) || \
15492 ((INSTANCE) == DMA2_Stream6) || \
15493 ((INSTANCE) == DMA2_Stream7))
15494
15495/******************************* GPIO Instances *******************************/
15496#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
15497 ((INSTANCE) == GPIOB) || \
15498 ((INSTANCE) == GPIOC) || \
15499 ((INSTANCE) == GPIOD) || \
15500 ((INSTANCE) == GPIOE) || \
15501 ((INSTANCE) == GPIOF) || \
15502 ((INSTANCE) == GPIOG) || \
15503 ((INSTANCE) == GPIOH))
15504
15505/******************************** I2C Instances *******************************/
15506#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
15507 ((INSTANCE) == I2C2) || \
15508 ((INSTANCE) == I2C3))
15509
15510/******************************* SMBUS Instances ******************************/
15511#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
15512
15513/******************************** I2S Instances *******************************/
15514#define IS_I2S_APB1_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
15515 ((INSTANCE) == SPI3))
15516
15517#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
15518 ((INSTANCE) == SPI2) || \
15519 ((INSTANCE) == SPI3))
15520
15521
15522
15523/****************************** RTC Instances *********************************/
15524#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
15525
15526/******************************* SAI Instances ********************************/
15527#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
15528 ((PERIPH) == SAI1_Block_B) || \
15529 ((PERIPH) == SAI2_Block_A) || \
15530 ((PERIPH) == SAI2_Block_B))
15531/* Legacy define */
15532
15533#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
15534
15535/******************************** SPI Instances *******************************/
15536#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
15537 ((INSTANCE) == SPI2) || \
15538 ((INSTANCE) == SPI3) || \
15539 ((INSTANCE) == SPI4))
15540
15541
15542/****************** TIM Instances : All supported instances *******************/
15543#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15544 ((INSTANCE) == TIM2) || \
15545 ((INSTANCE) == TIM3) || \
15546 ((INSTANCE) == TIM4) || \
15547 ((INSTANCE) == TIM5) || \
15548 ((INSTANCE) == TIM6) || \
15549 ((INSTANCE) == TIM7) || \
15550 ((INSTANCE) == TIM8) || \
15551 ((INSTANCE) == TIM9) || \
15552 ((INSTANCE) == TIM10)|| \
15553 ((INSTANCE) == TIM11)|| \
15554 ((INSTANCE) == TIM12)|| \
15555 ((INSTANCE) == TIM13)|| \
15556 ((INSTANCE) == TIM14))
15557
15558/************* TIM Instances : at least 1 capture/compare channel *************/
15559#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15560 ((INSTANCE) == TIM2) || \
15561 ((INSTANCE) == TIM3) || \
15562 ((INSTANCE) == TIM4) || \
15563 ((INSTANCE) == TIM5) || \
15564 ((INSTANCE) == TIM8) || \
15565 ((INSTANCE) == TIM9) || \
15566 ((INSTANCE) == TIM10) || \
15567 ((INSTANCE) == TIM11) || \
15568 ((INSTANCE) == TIM12) || \
15569 ((INSTANCE) == TIM13) || \
15570 ((INSTANCE) == TIM14))
15571
15572/************ TIM Instances : at least 2 capture/compare channels *************/
15573#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15574 ((INSTANCE) == TIM2) || \
15575 ((INSTANCE) == TIM3) || \
15576 ((INSTANCE) == TIM4) || \
15577 ((INSTANCE) == TIM5) || \
15578 ((INSTANCE) == TIM8) || \
15579 ((INSTANCE) == TIM9) || \
15580 ((INSTANCE) == TIM12))
15581
15582/************ TIM Instances : at least 3 capture/compare channels *************/
15583#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15584 ((INSTANCE) == TIM2) || \
15585 ((INSTANCE) == TIM3) || \
15586 ((INSTANCE) == TIM4) || \
15587 ((INSTANCE) == TIM5) || \
15588 ((INSTANCE) == TIM8))
15589
15590/************ TIM Instances : at least 4 capture/compare channels *************/
15591#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15592 ((INSTANCE) == TIM2) || \
15593 ((INSTANCE) == TIM3) || \
15594 ((INSTANCE) == TIM4) || \
15595 ((INSTANCE) == TIM5) || \
15596 ((INSTANCE) == TIM8))
15597
15598/******************** TIM Instances : Advanced-control timers *****************/
15599#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15600 ((INSTANCE) == TIM8))
15601
15602/******************* TIM Instances : Timer input XOR function *****************/
15603#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15604 ((INSTANCE) == TIM2) || \
15605 ((INSTANCE) == TIM3) || \
15606 ((INSTANCE) == TIM4) || \
15607 ((INSTANCE) == TIM5) || \
15608 ((INSTANCE) == TIM8))
15609
15610/****************** TIM Instances : DMA requests generation (UDE) *************/
15611#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15612 ((INSTANCE) == TIM2) || \
15613 ((INSTANCE) == TIM3) || \
15614 ((INSTANCE) == TIM4) || \
15615 ((INSTANCE) == TIM5) || \
15616 ((INSTANCE) == TIM6) || \
15617 ((INSTANCE) == TIM7) || \
15618 ((INSTANCE) == TIM8))
15619
15620/************ TIM Instances : DMA requests generation (CCxDE) *****************/
15621#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15622 ((INSTANCE) == TIM2) || \
15623 ((INSTANCE) == TIM3) || \
15624 ((INSTANCE) == TIM4) || \
15625 ((INSTANCE) == TIM5) || \
15626 ((INSTANCE) == TIM8))
15627
15628/************ TIM Instances : DMA requests generation (COMDE) *****************/
15629#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15630 ((INSTANCE) == TIM2) || \
15631 ((INSTANCE) == TIM3) || \
15632 ((INSTANCE) == TIM4) || \
15633 ((INSTANCE) == TIM5) || \
15634 ((INSTANCE) == TIM8))
15635
15636/******************** TIM Instances : DMA burst feature ***********************/
15637#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15638 ((INSTANCE) == TIM2) || \
15639 ((INSTANCE) == TIM3) || \
15640 ((INSTANCE) == TIM4) || \
15641 ((INSTANCE) == TIM5) || \
15642 ((INSTANCE) == TIM8))
15643
15644/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
15645#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15646 ((INSTANCE) == TIM2) || \
15647 ((INSTANCE) == TIM3) || \
15648 ((INSTANCE) == TIM4) || \
15649 ((INSTANCE) == TIM5) || \
15650 ((INSTANCE) == TIM6) || \
15651 ((INSTANCE) == TIM7) || \
15652 ((INSTANCE) == TIM8))
15653
15654/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
15655#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15656 ((INSTANCE) == TIM2) || \
15657 ((INSTANCE) == TIM3) || \
15658 ((INSTANCE) == TIM4) || \
15659 ((INSTANCE) == TIM5) || \
15660 ((INSTANCE) == TIM8) || \
15661 ((INSTANCE) == TIM9) || \
15662 ((INSTANCE) == TIM12))
15663
15664/********************** TIM Instances : 32 bit Counter ************************/
15665#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
15666 ((INSTANCE) == TIM5))
15667
15668/***************** TIM Instances : external trigger input availabe ************/
15669#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15670 ((INSTANCE) == TIM2) || \
15671 ((INSTANCE) == TIM3) || \
15672 ((INSTANCE) == TIM4) || \
15673 ((INSTANCE) == TIM5) || \
15674 ((INSTANCE) == TIM8))
15675
15676/****************** TIM Instances : remapping capability **********************/
15677#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
15678 ((INSTANCE) == TIM5) || \
15679 ((INSTANCE) == TIM11))
15680
15681/******************* TIM Instances : output(s) available **********************/
15682#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
15683 ((((INSTANCE) == TIM1) && \
15684 (((CHANNEL) == TIM_CHANNEL_1) || \
15685 ((CHANNEL) == TIM_CHANNEL_2) || \
15686 ((CHANNEL) == TIM_CHANNEL_3) || \
15687 ((CHANNEL) == TIM_CHANNEL_4))) \
15688 || \
15689 (((INSTANCE) == TIM2) && \
15690 (((CHANNEL) == TIM_CHANNEL_1) || \
15691 ((CHANNEL) == TIM_CHANNEL_2) || \
15692 ((CHANNEL) == TIM_CHANNEL_3) || \
15693 ((CHANNEL) == TIM_CHANNEL_4))) \
15694 || \
15695 (((INSTANCE) == TIM3) && \
15696 (((CHANNEL) == TIM_CHANNEL_1) || \
15697 ((CHANNEL) == TIM_CHANNEL_2) || \
15698 ((CHANNEL) == TIM_CHANNEL_3) || \
15699 ((CHANNEL) == TIM_CHANNEL_4))) \
15700 || \
15701 (((INSTANCE) == TIM4) && \
15702 (((CHANNEL) == TIM_CHANNEL_1) || \
15703 ((CHANNEL) == TIM_CHANNEL_2) || \
15704 ((CHANNEL) == TIM_CHANNEL_3) || \
15705 ((CHANNEL) == TIM_CHANNEL_4))) \
15706 || \
15707 (((INSTANCE) == TIM5) && \
15708 (((CHANNEL) == TIM_CHANNEL_1) || \
15709 ((CHANNEL) == TIM_CHANNEL_2) || \
15710 ((CHANNEL) == TIM_CHANNEL_3) || \
15711 ((CHANNEL) == TIM_CHANNEL_4))) \
15712 || \
15713 (((INSTANCE) == TIM8) && \
15714 (((CHANNEL) == TIM_CHANNEL_1) || \
15715 ((CHANNEL) == TIM_CHANNEL_2) || \
15716 ((CHANNEL) == TIM_CHANNEL_3) || \
15717 ((CHANNEL) == TIM_CHANNEL_4))) \
15718 || \
15719 (((INSTANCE) == TIM9) && \
15720 (((CHANNEL) == TIM_CHANNEL_1) || \
15721 ((CHANNEL) == TIM_CHANNEL_2))) \
15722 || \
15723 (((INSTANCE) == TIM10) && \
15724 (((CHANNEL) == TIM_CHANNEL_1))) \
15725 || \
15726 (((INSTANCE) == TIM11) && \
15727 (((CHANNEL) == TIM_CHANNEL_1))) \
15728 || \
15729 (((INSTANCE) == TIM12) && \
15730 (((CHANNEL) == TIM_CHANNEL_1) || \
15731 ((CHANNEL) == TIM_CHANNEL_2))) \
15732 || \
15733 (((INSTANCE) == TIM13) && \
15734 (((CHANNEL) == TIM_CHANNEL_1))) \
15735 || \
15736 (((INSTANCE) == TIM14) && \
15737 (((CHANNEL) == TIM_CHANNEL_1))))
15738
15739/************ TIM Instances : complementary output(s) available ***************/
15740#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
15741 ((((INSTANCE) == TIM1) && \
15742 (((CHANNEL) == TIM_CHANNEL_1) || \
15743 ((CHANNEL) == TIM_CHANNEL_2) || \
15744 ((CHANNEL) == TIM_CHANNEL_3))) \
15745 || \
15746 (((INSTANCE) == TIM8) && \
15747 (((CHANNEL) == TIM_CHANNEL_1) || \
15748 ((CHANNEL) == TIM_CHANNEL_2) || \
15749 ((CHANNEL) == TIM_CHANNEL_3))))
15750
15751/****************** TIM Instances : supporting counting mode selection ********/
15752#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15753 ((INSTANCE) == TIM2) || \
15754 ((INSTANCE) == TIM3) || \
15755 ((INSTANCE) == TIM4) || \
15756 ((INSTANCE) == TIM5) || \
15757 ((INSTANCE) == TIM8))
15758
15759/****************** TIM Instances : supporting clock division *****************/
15760#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15761 ((INSTANCE) == TIM2) || \
15762 ((INSTANCE) == TIM3) || \
15763 ((INSTANCE) == TIM4) || \
15764 ((INSTANCE) == TIM5) || \
15765 ((INSTANCE) == TIM8) || \
15766 ((INSTANCE) == TIM9) || \
15767 ((INSTANCE) == TIM10)|| \
15768 ((INSTANCE) == TIM11)|| \
15769 ((INSTANCE) == TIM12)|| \
15770 ((INSTANCE) == TIM13)|| \
15771 ((INSTANCE) == TIM14))
15772
15773/****************** TIM Instances : supporting commutation event generation ***/
15774#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
15775 ((INSTANCE) == TIM8))
15776
15777
15778/****************** TIM Instances : supporting OCxREF clear *******************/
15779#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15780 ((INSTANCE) == TIM2) || \
15781 ((INSTANCE) == TIM3) || \
15782 ((INSTANCE) == TIM4) || \
15783 ((INSTANCE) == TIM5) || \
15784 ((INSTANCE) == TIM8))
15785
15786/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
15787#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15788 ((INSTANCE) == TIM2) || \
15789 ((INSTANCE) == TIM3) || \
15790 ((INSTANCE) == TIM4) || \
15791 ((INSTANCE) == TIM5) || \
15792 ((INSTANCE) == TIM8) || \
15793 ((INSTANCE) == TIM9) || \
15794 ((INSTANCE) == TIM12))
15795
15796/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
15797#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15798 ((INSTANCE) == TIM2) || \
15799 ((INSTANCE) == TIM3) || \
15800 ((INSTANCE) == TIM4) || \
15801 ((INSTANCE) == TIM5) || \
15802 ((INSTANCE) == TIM8))
15803
15804/****************** TIM Instances : supporting repetition counter *************/
15805#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15806 ((INSTANCE) == TIM8))
15807
15808/****************** TIM Instances : supporting encoder interface **************/
15809#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15810 ((INSTANCE) == TIM2) || \
15811 ((INSTANCE) == TIM3) || \
15812 ((INSTANCE) == TIM4) || \
15813 ((INSTANCE) == TIM5) || \
15814 ((INSTANCE) == TIM8) || \
15815 ((INSTANCE) == TIM9) || \
15816 ((INSTANCE) == TIM12))
15817/****************** TIM Instances : supporting Hall sensor interface **********/
15818#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15819 ((INSTANCE) == TIM2) || \
15820 ((INSTANCE) == TIM3) || \
15821 ((INSTANCE) == TIM4) || \
15822 ((INSTANCE) == TIM5) || \
15823 ((INSTANCE) == TIM8))
15824/****************** TIM Instances : supporting the break function *************/
15825#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15826 ((INSTANCE) == TIM8))
15827
15828/******************** USART Instances : Synchronous mode **********************/
15829#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15830 ((INSTANCE) == USART2) || \
15831 ((INSTANCE) == USART3) || \
15832 ((INSTANCE) == USART6))
15833
15834/******************** UART Instances : Half-Duplex mode **********************/
15835#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15836 ((INSTANCE) == USART2) || \
15837 ((INSTANCE) == USART3) || \
15838 ((INSTANCE) == UART4) || \
15839 ((INSTANCE) == UART5) || \
15840 ((INSTANCE) == USART6))
15841
15842/* Legacy defines */
15843#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
15844
15845/****************** UART Instances : Hardware Flow control ********************/
15846#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15847 ((INSTANCE) == USART2) || \
15848 ((INSTANCE) == USART3) || \
15849 ((INSTANCE) == USART6))
15850/******************** UART Instances : LIN mode **********************/
15851#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
15852
15853/********************* UART Instances : Smart card mode ***********************/
15854#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15855 ((INSTANCE) == USART2) || \
15856 ((INSTANCE) == USART3) || \
15857 ((INSTANCE) == USART6))
15858
15859/*********************** UART Instances : IRDA mode ***************************/
15860#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15861 ((INSTANCE) == USART2) || \
15862 ((INSTANCE) == USART3) || \
15863 ((INSTANCE) == UART4) || \
15864 ((INSTANCE) == UART5) || \
15865 ((INSTANCE) == USART6))
15866
15867
15868/*********************** PCD Instances ****************************************/
15869#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
15870 ((INSTANCE) == USB_OTG_HS))
15871
15872/*********************** HCD Instances ****************************************/
15873#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
15874 ((INSTANCE) == USB_OTG_HS))
15875
15876/****************************** SDIO Instances ********************************/
15877#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
15878
15879/****************************** IWDG Instances ********************************/
15880#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
15881
15882/****************************** WWDG Instances ********************************/
15883#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
15884
15885
15886/****************************** QSPI Instances ********************************/
15887#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
15888
15889/******************************* CEC Instances ********************************/
15890#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
15891
15892/***************************** FMPI2C Instances *******************************/
15893#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
15894
15895/******************************* SPDIFRX Instances ********************************/
15896#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
15897/****************************** USB Exported Constants ************************/
15898#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
15899#define USB_OTG_FS_MAX_IN_ENDPOINTS 5U /* Including EP0 */
15900#define USB_OTG_FS_MAX_OUT_ENDPOINTS 5U /* Including EP0 */
15901#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
15902#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16U
15903#define USB_OTG_HS_MAX_IN_ENDPOINTS 8U /* Including EP0 */
15904#define USB_OTG_HS_MAX_OUT_ENDPOINTS 8U /* Including EP0 */
15905#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
15906
15907/*
15908 * @brief Specific devices reset values definitions
15909 */
15910#define RCC_PLLCFGR_RST_VALUE 0x24003010U
15911#define RCC_PLLI2SCFGR_RST_VALUE 0x24003010U
15912#define RCC_PLLSAICFGR_RST_VALUE 0x04003010U
15913
15914#define RCC_MAX_FREQUENCY 180000000U /*!< Max frequency of family in Hz*/
15915#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
15916#define RCC_MAX_FREQUENCY_SCALE2 168000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
15917#define RCC_MAX_FREQUENCY_SCALE3 120000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
15918#define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
15919#define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
15920#define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
15921#define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
15922
15923#define RCC_PLLN_MIN_VALUE 50U
15924#define RCC_PLLN_MAX_VALUE 432U
15925
15926#define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
15927#define FLASH_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
15928#define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
15929#define FLASH_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
15930#define FLASH_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
15931
15932#define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
15933#define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
15934#define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
15935#define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
15936#define FLASH_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
15937
15938#define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
15939#define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
15940#define FLASH_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
15941
15942/******************************************************************************/
15943/* For a painless codes migration between the STM32F4xx device product */
15944/* lines, the aliases defined below are put in place to overcome the */
15945/* differences in the interrupt handlers and IRQn definitions. */
15946/* No need to update developed interrupt code when moving across */
15947/* product lines within the same STM32F4 Family */
15948/******************************************************************************/
15949/* Aliases for __IRQn */
15950#define FSMC_IRQn FMC_IRQn
15951
15952/* Aliases for __IRQHandler */
15953#define FSMC_IRQHandler FMC_IRQHandler
15954#define QuadSPI_IRQHandler QUADSPI_IRQHandler
15955
15956/**
15957 * @}
15958 */
15959
15960/**
15961 * @}
15962 */
15963
15964/**
15965 * @}
15966 */
15967
15968#ifdef __cplusplus
15969}
15970#endif /* __cplusplus */
15971
15972#endif /* __STM32F446xx_H */
15973
15974
15975
15976/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 17:01:56 +0100