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1/**
2 ******************************************************************************
3 * @file stm32f479xx.h
4 * @author MCD Application Team
5 * @version V2.6.1
6 * @date 14-February-2017
7 * @brief CMSIS STM32F479xx Device Peripheral Access Layer Header File.
8 *
9 * This file contains:
10 * - Data structures and the address mapping for all peripherals
11 * - peripherals registers declarations and bits definition
12 * - Macros to access peripheral’s registers hardware
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
18 *
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ******************************************************************************
42 */
43
44/** @addtogroup CMSIS_Device
45 * @{
46 */
47
48/** @addtogroup stm32f479xx
49 * @{
50 */
51
52#ifndef __STM32F479xx_H
53#define __STM32F479xx_H
54
55#ifdef __cplusplus
56 extern "C" {
57#endif /* __cplusplus */
58
59/** @addtogroup Configuration_section_for_CMSIS
60 * @{
61 */
62
63/**
64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
65 */
66#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
67#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
68#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
69#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
70#define __FPU_PRESENT 1U /*!< FPU present */
71
72/**
73 * @}
74 */
75
76/** @addtogroup Peripheral_interrupt_number_definition
77 * @{
78 */
79
80/**
81 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
82 * in @ref Library_configuration_section
83 */
84typedef enum
85{
86/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
87 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
88 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
89 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
90 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
91 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
92 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
93 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
94 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
95/****** STM32 specific Interrupt Numbers **********************************************************************/
96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
97 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
98 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
99 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
100 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
101 RCC_IRQn = 5, /*!< RCC global Interrupt */
102 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
103 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
104 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
105 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
106 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
107 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
108 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
109 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
110 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
111 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
112 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
113 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
114 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
115 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
116 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
117 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
118 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
119 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
120 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
121 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
122 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
123 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
124 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
125 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
126 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
127 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
128 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
129 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
130 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
131 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
132 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
133 USART1_IRQn = 37, /*!< USART1 global Interrupt */
134 USART2_IRQn = 38, /*!< USART2 global Interrupt */
135 USART3_IRQn = 39, /*!< USART3 global Interrupt */
136 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
137 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
138 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
139 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
140 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
141 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
142 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
143 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
144 FMC_IRQn = 48, /*!< FMC global Interrupt */
145 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
146 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
147 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
148 UART4_IRQn = 52, /*!< UART4 global Interrupt */
149 UART5_IRQn = 53, /*!< UART5 global Interrupt */
150 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
151 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
152 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
153 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
154 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
155 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
156 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
157 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
158 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
159 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
160 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
161 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
162 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
163 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
164 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
165 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
166 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
167 USART6_IRQn = 71, /*!< USART6 global interrupt */
168 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
169 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
170 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
171 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
172 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
173 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
174 DCMI_IRQn = 78, /*!< DCMI global interrupt */
175 CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
176 HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
177 FPU_IRQn = 81, /*!< FPU global interrupt */
178 UART7_IRQn = 82, /*!< UART7 global interrupt */
179 UART8_IRQn = 83, /*!< UART8 global interrupt */
180 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
181 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
182 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
183 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
184 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
185 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
186 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
187 QUADSPI_IRQn = 91, /*!< QUADSPI global Interrupt */
188 DSI_IRQn = 92 /*!< DSI global Interrupt */
189} IRQn_Type;
190
191/**
192 * @}
193 */
194
195#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
196#include "system_stm32f4xx.h"
197#include <stdint.h>
198
199/** @addtogroup Peripheral_registers_structures
200 * @{
201 */
202
203/**
204 * @brief Analog to Digital Converter
205 */
206
207typedef struct
208{
209 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
210 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
211 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
212 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
213 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
214 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
215 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
216 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
217 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
218 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
219 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
220 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
221 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
222 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
223 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
224 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
225 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
226 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
227 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
228 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
229} ADC_TypeDef;
230
231typedef struct
232{
233 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
234 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
235 __IO uint32_t CDR; /*!< ADC common regular data register for dual
236 AND triple modes, Address offset: ADC1 base address + 0x308 */
237} ADC_Common_TypeDef;
238
239
240/**
241 * @brief Controller Area Network TxMailBox
242 */
243
244typedef struct
245{
246 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
247 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
248 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
249 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
250} CAN_TxMailBox_TypeDef;
251
252/**
253 * @brief Controller Area Network FIFOMailBox
254 */
255
256typedef struct
257{
258 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
259 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
260 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
261 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
262} CAN_FIFOMailBox_TypeDef;
263
264/**
265 * @brief Controller Area Network FilterRegister
266 */
267
268typedef struct
269{
270 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
271 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
272} CAN_FilterRegister_TypeDef;
273
274/**
275 * @brief Controller Area Network
276 */
277
278typedef struct
279{
280 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
281 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
282 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
283 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
284 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
285 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
286 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
287 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
288 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
289 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
290 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
291 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
292 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
293 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
294 uint32_t RESERVED2; /*!< Reserved, 0x208 */
295 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
296 uint32_t RESERVED3; /*!< Reserved, 0x210 */
297 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
298 uint32_t RESERVED4; /*!< Reserved, 0x218 */
299 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
300 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
301 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
302} CAN_TypeDef;
303
304/**
305 * @brief CRC calculation unit
306 */
307
308typedef struct
309{
310 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
311 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
312 uint8_t RESERVED0; /*!< Reserved, 0x05 */
313 uint16_t RESERVED1; /*!< Reserved, 0x06 */
314 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
315} CRC_TypeDef;
316
317/**
318 * @brief Digital to Analog Converter
319 */
320
321typedef struct
322{
323 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
324 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
325 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
326 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
327 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
328 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
329 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
330 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
331 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
332 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
333 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
334 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
335 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
336 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
337} DAC_TypeDef;
338
339/**
340 * @brief Debug MCU
341 */
342
343typedef struct
344{
345 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
346 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
347 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
348 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
349}DBGMCU_TypeDef;
350
351/**
352 * @brief DCMI
353 */
354
355typedef struct
356{
357 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
358 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
359 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
360 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
361 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
362 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
363 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
364 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
365 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
366 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
367 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
368} DCMI_TypeDef;
369
370/**
371 * @brief DMA Controller
372 */
373
374typedef struct
375{
376 __IO uint32_t CR; /*!< DMA stream x configuration register */
377 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
378 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
379 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
380 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
381 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
382} DMA_Stream_TypeDef;
383
384typedef struct
385{
386 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
387 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
388 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
389 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
390} DMA_TypeDef;
391
392/**
393 * @brief DMA2D Controller
394 */
395
396typedef struct
397{
398 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
399 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
400 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
401 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
402 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
403 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
404 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
405 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
406 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
407 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
408 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
409 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
410 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
411 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
412 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
413 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
414 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
415 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
416 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
417 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
418 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
419 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
420 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
421} DMA2D_TypeDef;
422
423/**
424 * @brief DSI Controller
425 */
426
427typedef struct
428{
429 __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */
430 __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */
431 __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */
432 __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */
433 __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */
434 __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */
435 __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */
436 uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */
437 __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */
438 __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */
439 __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */
440 __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */
441 __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */
442 __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */
443 __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */
444 __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */
445 __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */
446 __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */
447 __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */
448 __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */
449 __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */
450 __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */
451 __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */
452 __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */
453 __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */
454 __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */
455 __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */
456 __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
457 __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */
458 __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */
459 __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */
460 __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */
461 __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */
462 __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */
463 __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */
464 __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */
465 __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */
466 uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */
467 __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
468 __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
469 uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */
470 __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
471 uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */
472 __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */
473 uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */
474 __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */
475 __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */
476 uint32_t RESERVED5; /*!< Reserved, 0x114 */
477 __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */
478 uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
479 __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
480 __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
481 __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
482 __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
483 __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
484 __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
485 __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */
486 __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */
487 __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */
488 __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */
489 __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */
490 uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */
491 __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */
492 uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */
493 __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */
494 __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */
495 __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */
496 __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */
497 __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */
498 uint32_t RESERVED9; /*!< Reserved, 0x414 */
499 __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */
500 uint32_t RESERVED10; /*!< Reserved, 0x42C */
501 __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */
502} DSI_TypeDef;
503
504/**
505 * @brief Ethernet MAC
506 */
507
508typedef struct
509{
510 __IO uint32_t MACCR;
511 __IO uint32_t MACFFR;
512 __IO uint32_t MACHTHR;
513 __IO uint32_t MACHTLR;
514 __IO uint32_t MACMIIAR;
515 __IO uint32_t MACMIIDR;
516 __IO uint32_t MACFCR;
517 __IO uint32_t MACVLANTR; /* 8 */
518 uint32_t RESERVED0[2];
519 __IO uint32_t MACRWUFFR; /* 11 */
520 __IO uint32_t MACPMTCSR;
521 uint32_t RESERVED1;
522 __IO uint32_t MACDBGR;
523 __IO uint32_t MACSR; /* 15 */
524 __IO uint32_t MACIMR;
525 __IO uint32_t MACA0HR;
526 __IO uint32_t MACA0LR;
527 __IO uint32_t MACA1HR;
528 __IO uint32_t MACA1LR;
529 __IO uint32_t MACA2HR;
530 __IO uint32_t MACA2LR;
531 __IO uint32_t MACA3HR;
532 __IO uint32_t MACA3LR; /* 24 */
533 uint32_t RESERVED2[40];
534 __IO uint32_t MMCCR; /* 65 */
535 __IO uint32_t MMCRIR;
536 __IO uint32_t MMCTIR;
537 __IO uint32_t MMCRIMR;
538 __IO uint32_t MMCTIMR; /* 69 */
539 uint32_t RESERVED3[14];
540 __IO uint32_t MMCTGFSCCR; /* 84 */
541 __IO uint32_t MMCTGFMSCCR;
542 uint32_t RESERVED4[5];
543 __IO uint32_t MMCTGFCR;
544 uint32_t RESERVED5[10];
545 __IO uint32_t MMCRFCECR;
546 __IO uint32_t MMCRFAECR;
547 uint32_t RESERVED6[10];
548 __IO uint32_t MMCRGUFCR;
549 uint32_t RESERVED7[334];
550 __IO uint32_t PTPTSCR;
551 __IO uint32_t PTPSSIR;
552 __IO uint32_t PTPTSHR;
553 __IO uint32_t PTPTSLR;
554 __IO uint32_t PTPTSHUR;
555 __IO uint32_t PTPTSLUR;
556 __IO uint32_t PTPTSAR;
557 __IO uint32_t PTPTTHR;
558 __IO uint32_t PTPTTLR;
559 __IO uint32_t RESERVED8;
560 __IO uint32_t PTPTSSR;
561 uint32_t RESERVED9[565];
562 __IO uint32_t DMABMR;
563 __IO uint32_t DMATPDR;
564 __IO uint32_t DMARPDR;
565 __IO uint32_t DMARDLAR;
566 __IO uint32_t DMATDLAR;
567 __IO uint32_t DMASR;
568 __IO uint32_t DMAOMR;
569 __IO uint32_t DMAIER;
570 __IO uint32_t DMAMFBOCR;
571 __IO uint32_t DMARSWTR;
572 uint32_t RESERVED10[8];
573 __IO uint32_t DMACHTDR;
574 __IO uint32_t DMACHRDR;
575 __IO uint32_t DMACHTBAR;
576 __IO uint32_t DMACHRBAR;
577} ETH_TypeDef;
578
579/**
580 * @brief External Interrupt/Event Controller
581 */
582
583typedef struct
584{
585 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
586 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
587 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
588 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
589 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
590 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
591} EXTI_TypeDef;
592
593/**
594 * @brief FLASH Registers
595 */
596
597typedef struct
598{
599 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
600 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
601 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
602 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
603 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
604 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
605 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
606} FLASH_TypeDef;
607
608/**
609 * @brief Flexible Memory Controller
610 */
611
612typedef struct
613{
614 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
615} FMC_Bank1_TypeDef;
616
617/**
618 * @brief Flexible Memory Controller Bank1E
619 */
620
621typedef struct
622{
623 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
624} FMC_Bank1E_TypeDef;
625
626/**
627 * @brief Flexible Memory Controller Bank3
628 */
629
630typedef struct
631{
632 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
633 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
634 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
635 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
636 uint32_t RESERVED; /*!< Reserved, 0x90 */
637 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
638} FMC_Bank3_TypeDef;
639
640/**
641 * @brief Flexible Memory Controller Bank5_6
642 */
643
644typedef struct
645{
646 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
647 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
648 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
649 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
650 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
651} FMC_Bank5_6_TypeDef;
652
653/**
654 * @brief General Purpose I/O
655 */
656
657typedef struct
658{
659 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
660 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
661 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
662 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
663 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
664 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
665 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
666 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
667 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
668} GPIO_TypeDef;
669
670/**
671 * @brief System configuration controller
672 */
673
674typedef struct
675{
676 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
677 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
678 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
679 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
680 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
681} SYSCFG_TypeDef;
682
683/**
684 * @brief Inter-integrated Circuit Interface
685 */
686
687typedef struct
688{
689 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
690 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
691 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
692 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
693 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
694 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
695 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
696 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
697 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
698 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
699} I2C_TypeDef;
700
701/**
702 * @brief Independent WATCHDOG
703 */
704
705typedef struct
706{
707 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
708 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
709 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
710 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
711} IWDG_TypeDef;
712
713/**
714 * @brief LCD-TFT Display Controller
715 */
716
717typedef struct
718{
719 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
720 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
721 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
722 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
723 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
724 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
725 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
726 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
727 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
728 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
729 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
730 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
731 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
732 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
733 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
734 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
735 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
736} LTDC_TypeDef;
737
738/**
739 * @brief LCD-TFT Display layer x Controller
740 */
741
742typedef struct
743{
744 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
745 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
746 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
747 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
748 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
749 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
750 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
751 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
752 uint32_t RESERVED0[2]; /*!< Reserved */
753 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
754 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
755 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
756 uint32_t RESERVED1[3]; /*!< Reserved */
757 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144*/
758} LTDC_Layer_TypeDef;
759
760/**
761 * @brief Power Control
762 */
763
764typedef struct
765{
766 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
767 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
768} PWR_TypeDef;
769
770/**
771 * @brief Reset and Clock Control
772 */
773
774typedef struct
775{
776 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
777 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
778 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
779 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
780 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
781 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
782 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
783 uint32_t RESERVED0; /*!< Reserved, 0x1C */
784 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
785 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
786 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
787 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
788 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
789 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
790 uint32_t RESERVED2; /*!< Reserved, 0x3C */
791 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
792 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
793 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
794 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
795 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
796 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
797 uint32_t RESERVED4; /*!< Reserved, 0x5C */
798 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
799 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
800 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
801 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
802 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
803 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
804 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
805 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
806 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
807 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
808} RCC_TypeDef;
809
810/**
811 * @brief Real-Time Clock
812 */
813
814typedef struct
815{
816 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
817 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
818 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
819 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
820 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
821 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
822 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
823 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
824 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
825 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
826 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
827 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
828 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
829 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
830 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
831 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
832 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
833 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
834 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
835 uint32_t RESERVED7; /*!< Reserved, 0x4C */
836 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
837 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
838 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
839 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
840 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
841 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
842 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
843 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
844 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
845 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
846 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
847 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
848 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
849 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
850 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
851 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
852 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
853 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
854 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
855 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
856} RTC_TypeDef;
857
858/**
859 * @brief Serial Audio Interface
860 */
861
862typedef struct
863{
864 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
865} SAI_TypeDef;
866
867typedef struct
868{
869 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
870 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
871 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
872 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
873 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
874 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
875 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
876 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
877} SAI_Block_TypeDef;
878
879/**
880 * @brief SD host Interface
881 */
882
883typedef struct
884{
885 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
886 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
887 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
888 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
889 __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
890 __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
891 __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
892 __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
893 __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
894 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
895 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
896 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
897 __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
898 __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
899 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
900 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
901 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
902 __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
903 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
904 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
905} SDIO_TypeDef;
906
907/**
908 * @brief Serial Peripheral Interface
909 */
910
911typedef struct
912{
913 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
914 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
915 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
916 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
917 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
918 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
919 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
920 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
921 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
922} SPI_TypeDef;
923
924/**
925 * @brief QUAD Serial Peripheral Interface
926 */
927
928typedef struct
929{
930 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
931 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
932 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
933 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
934 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
935 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
936 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
937 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
938 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
939 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
940 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
941 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
942 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
943} QUADSPI_TypeDef;
944
945/**
946 * @brief TIM
947 */
948
949typedef struct
950{
951 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
952 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
953 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
954 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
955 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
956 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
957 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
958 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
959 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
960 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
961 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
962 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
963 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
964 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
965 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
966 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
967 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
968 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
969 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
970 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
971 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
972} TIM_TypeDef;
973
974/**
975 * @brief Universal Synchronous Asynchronous Receiver Transmitter
976 */
977
978typedef struct
979{
980 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
981 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
982 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
983 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
984 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
985 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
986 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
987} USART_TypeDef;
988
989/**
990 * @brief Window WATCHDOG
991 */
992
993typedef struct
994{
995 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
996 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
997 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
998} WWDG_TypeDef;
999
1000/**
1001 * @brief Crypto Processor
1002 */
1003
1004typedef struct
1005{
1006 __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
1007 __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
1008 __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
1009 __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
1010 __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
1011 __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
1012 __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
1013 __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
1014 __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
1015 __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
1016 __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
1017 __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
1018 __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
1019 __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
1020 __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
1021 __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
1022 __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
1023 __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
1024 __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
1025 __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
1026 __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
1027 __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
1028 __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
1029 __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
1030 __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
1031 __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
1032 __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
1033 __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
1034 __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
1035 __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
1036 __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
1037 __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
1038 __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
1039 __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
1040 __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
1041 __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
1042} CRYP_TypeDef;
1043
1044/**
1045 * @brief HASH
1046 */
1047
1048typedef struct
1049{
1050 __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
1051 __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
1052 __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
1053 __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
1054 __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
1055 __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
1056 uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
1057 __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
1058} HASH_TypeDef;
1059
1060/**
1061 * @brief HASH_DIGEST
1062 */
1063
1064typedef struct
1065{
1066 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
1067} HASH_DIGEST_TypeDef;
1068
1069/**
1070 * @brief RNG
1071 */
1072
1073typedef struct
1074{
1075 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
1076 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
1077 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
1078} RNG_TypeDef;
1079
1080/**
1081 * @brief USB_OTG_Core_Registers
1082 */
1083typedef struct
1084{
1085 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
1086 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
1087 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
1088 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
1089 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
1090 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
1091 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
1092 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
1093 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
1094 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
1095 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
1096 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
1097 uint32_t Reserved30[2]; /*!< Reserved 030h */
1098 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
1099 __IO uint32_t CID; /*!< User ID Register 03Ch */
1100 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
1101 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
1102 uint32_t Reserved6; /*!< Reserved 050h */
1103 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
1104 uint32_t Reserved; /*!< Reserved 058h */
1105 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
1106 uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh */
1107 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
1108 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
1109} USB_OTG_GlobalTypeDef;
1110
1111/**
1112 * @brief USB_OTG_device_Registers
1113 */
1114typedef struct
1115{
1116 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
1117 __IO uint32_t DCTL; /*!< dev Control Register 804h */
1118 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
1119 uint32_t Reserved0C; /*!< Reserved 80Ch */
1120 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
1121 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
1122 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
1123 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
1124 uint32_t Reserved20; /*!< Reserved 820h */
1125 uint32_t Reserved9; /*!< Reserved 824h */
1126 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
1127 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
1128 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
1129 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
1130 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
1131 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
1132 uint32_t Reserved40; /*!< dedicated EP mask 840h */
1133 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
1134 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
1135 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
1136} USB_OTG_DeviceTypeDef;
1137
1138/**
1139 * @brief USB_OTG_IN_Endpoint-Specific_Register
1140 */
1141typedef struct
1142{
1143 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
1144 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
1145 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
1146 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
1147 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
1148 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
1149 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
1150 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
1151} USB_OTG_INEndpointTypeDef;
1152
1153/**
1154 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1155 */
1156typedef struct
1157{
1158 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
1159 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
1160 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
1161 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
1162 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
1163 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
1164 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
1165} USB_OTG_OUTEndpointTypeDef;
1166
1167/**
1168 * @brief USB_OTG_Host_Mode_Register_Structures
1169 */
1170typedef struct
1171{
1172 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
1173 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
1174 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
1175 uint32_t Reserved40C; /*!< Reserved 40Ch */
1176 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
1177 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
1178 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
1179} USB_OTG_HostTypeDef;
1180
1181/**
1182 * @brief USB_OTG_Host_Channel_Specific_Registers
1183 */
1184typedef struct
1185{
1186 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
1187 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
1188 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
1189 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
1190 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
1191 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
1192 uint32_t Reserved[2]; /*!< Reserved */
1193} USB_OTG_HostChannelTypeDef;
1194
1195/**
1196 * @}
1197 */
1198
1199/** @addtogroup Peripheral_memory_map
1200 * @{
1201 */
1202#define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
1203#define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
1204#define SRAM1_BASE 0x20000000U /*!< SRAM1(160 KB) base address in the alias region */
1205#define SRAM2_BASE 0x20028000U /*!< SRAM2(32 KB) base address in the alias region */
1206#define SRAM3_BASE 0x20030000U /*!< SRAM3(128 KB) base address in the alias region */
1207#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
1208#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
1209#define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */
1210#define QSPI_R_BASE 0xA0001000U /*!< QuadSPI registers base address */
1211#define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
1212#define SRAM2_BB_BASE 0x22500000U /*!< SRAM2(16 KB) base address in the bit-band region */
1213#define SRAM3_BB_BASE 0x22600000U /*!< SRAM3(64 KB) base address in the bit-band region */
1214#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
1215#define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
1216#define FLASH_END 0x081FFFFFU /*!< FLASH end address */
1217#define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
1218#define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
1219#define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
1220
1221/* Legacy defines */
1222#define SRAM_BASE SRAM1_BASE
1223#define SRAM_BB_BASE SRAM1_BB_BASE
1224
1225/*!< Peripheral memory map */
1226#define APB1PERIPH_BASE PERIPH_BASE
1227#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1228#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1229#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
1230
1231/*!< APB1 peripherals */
1232#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1233#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1234#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1235#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1236#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1237#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1238#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
1239#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
1240#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
1241#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1242#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1243#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1244#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
1245#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1246#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1247#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
1248#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1249#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1250#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1251#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1252#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1253#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1254#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1255#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1256#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
1257#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1258#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1259#define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
1260#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
1261
1262/*!< APB2 peripherals */
1263#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
1264#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
1265#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
1266#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
1267#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
1268#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
1269#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
1270#define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
1271/* Legacy define */
1272#define ADC_BASE ADC123_COMMON_BASE
1273#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
1274#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1275#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
1276#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
1277#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
1278#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
1279#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
1280#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
1281#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
1282#define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
1283#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
1284#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
1285#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
1286#define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
1287#define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
1288#define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
1289#define DSI_BASE (APB2PERIPH_BASE + 0x6C00U)
1290
1291/*!< AHB1 peripherals */
1292#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
1293#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1294#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1295#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1296#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1297#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1298#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1299#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1300#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
1301#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
1302#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
1303#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1304#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1305#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1306#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1307#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1308#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1309#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1310#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1311#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1312#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1313#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1314#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1315#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1316#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1317#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1318#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1319#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1320#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1321#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1322#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1323#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1324#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
1325#define ETH_MAC_BASE (ETH_BASE)
1326#define ETH_MMC_BASE (ETH_BASE + 0x0100U)
1327#define ETH_PTP_BASE (ETH_BASE + 0x0700U)
1328#define ETH_DMA_BASE (ETH_BASE + 0x1000U)
1329#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
1330
1331/*!< AHB2 peripherals */
1332#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
1333#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000U)
1334#define HASH_BASE (AHB2PERIPH_BASE + 0x60400U)
1335#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710U)
1336#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1337
1338/*!< FMC Bankx registers base address */
1339#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1340#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1341#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
1342#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
1343
1344
1345/*!< Debug MCU registers base address */
1346#define DBGMCU_BASE 0xE0042000U
1347/*!< USB registers base address */
1348#define USB_OTG_HS_PERIPH_BASE 0x40040000U
1349#define USB_OTG_FS_PERIPH_BASE 0x50000000U
1350
1351#define USB_OTG_GLOBAL_BASE 0x000U
1352#define USB_OTG_DEVICE_BASE 0x800U
1353#define USB_OTG_IN_ENDPOINT_BASE 0x900U
1354#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1355#define USB_OTG_EP_REG_SIZE 0x20U
1356#define USB_OTG_HOST_BASE 0x400U
1357#define USB_OTG_HOST_PORT_BASE 0x440U
1358#define USB_OTG_HOST_CHANNEL_BASE 0x500U
1359#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1360#define USB_OTG_PCGCCTL_BASE 0xE00U
1361#define USB_OTG_FIFO_BASE 0x1000U
1362#define USB_OTG_FIFO_SIZE 0x1000U
1363
1364#define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
1365#define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
1366#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
1367/**
1368 * @}
1369 */
1370
1371/** @addtogroup Peripheral_declaration
1372 * @{
1373 */
1374#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1375#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1376#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1377#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1378#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1379#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1380#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1381#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1382#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1383#define RTC ((RTC_TypeDef *) RTC_BASE)
1384#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1385#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1386#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1387#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1388#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1389#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1390#define USART2 ((USART_TypeDef *) USART2_BASE)
1391#define USART3 ((USART_TypeDef *) USART3_BASE)
1392#define UART4 ((USART_TypeDef *) UART4_BASE)
1393#define UART5 ((USART_TypeDef *) UART5_BASE)
1394#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1395#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1396#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1397#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1398#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1399#define PWR ((PWR_TypeDef *) PWR_BASE)
1400#define DAC1 ((DAC_TypeDef *) DAC_BASE)
1401#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1402#define UART7 ((USART_TypeDef *) UART7_BASE)
1403#define UART8 ((USART_TypeDef *) UART8_BASE)
1404#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1405#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1406#define USART1 ((USART_TypeDef *) USART1_BASE)
1407#define USART6 ((USART_TypeDef *) USART6_BASE)
1408#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1409#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1410#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1411#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1412/* Legacy define */
1413#define ADC ADC123_COMMON
1414#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1415#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1416#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1417#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1418#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1419#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1420#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1421#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1422#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1423#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1424#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1425#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1426#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1427#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
1428#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1429#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1430#define DSI ((DSI_TypeDef *)DSI_BASE)
1431#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1432#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1433#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1434#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1435#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1436#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1437#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1438#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1439#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1440#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1441#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1442#define CRC ((CRC_TypeDef *) CRC_BASE)
1443#define RCC ((RCC_TypeDef *) RCC_BASE)
1444#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1445#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1446#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1447#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1448#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1449#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1450#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1451#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1452#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1453#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1454#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1455#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1456#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1457#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1458#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1459#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1460#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1461#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1462#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1463#define ETH ((ETH_TypeDef *) ETH_BASE)
1464#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1465#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1466#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
1467#define HASH ((HASH_TypeDef *) HASH_BASE)
1468#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
1469#define RNG ((RNG_TypeDef *) RNG_BASE)
1470#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1471#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1472#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1473#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1474#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1475#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1476#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1477#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1478
1479/**
1480 * @}
1481 */
1482
1483/** @addtogroup Exported_constants
1484 * @{
1485 */
1486
1487 /** @addtogroup Peripheral_Registers_Bits_Definition
1488 * @{
1489 */
1490
1491/******************************************************************************/
1492/* Peripheral Registers_Bits_Definition */
1493/******************************************************************************/
1494
1495/******************************************************************************/
1496/* */
1497/* Analog to Digital Converter */
1498/* */
1499/******************************************************************************/
1500/*
1501 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
1502 */
1503#define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */
1504
1505/******************** Bit definition for ADC_SR register ********************/
1506#define ADC_SR_AWD_Pos (0U)
1507#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
1508#define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
1509#define ADC_SR_EOC_Pos (1U)
1510#define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
1511#define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
1512#define ADC_SR_JEOC_Pos (2U)
1513#define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
1514#define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
1515#define ADC_SR_JSTRT_Pos (3U)
1516#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
1517#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
1518#define ADC_SR_STRT_Pos (4U)
1519#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
1520#define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
1521#define ADC_SR_OVR_Pos (5U)
1522#define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
1523#define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
1524
1525/******************* Bit definition for ADC_CR1 register ********************/
1526#define ADC_CR1_AWDCH_Pos (0U)
1527#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
1528#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1529#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
1530#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
1531#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
1532#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
1533#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
1534#define ADC_CR1_EOCIE_Pos (5U)
1535#define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
1536#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
1537#define ADC_CR1_AWDIE_Pos (6U)
1538#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
1539#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
1540#define ADC_CR1_JEOCIE_Pos (7U)
1541#define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
1542#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
1543#define ADC_CR1_SCAN_Pos (8U)
1544#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
1545#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
1546#define ADC_CR1_AWDSGL_Pos (9U)
1547#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
1548#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
1549#define ADC_CR1_JAUTO_Pos (10U)
1550#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
1551#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
1552#define ADC_CR1_DISCEN_Pos (11U)
1553#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
1554#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
1555#define ADC_CR1_JDISCEN_Pos (12U)
1556#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
1557#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
1558#define ADC_CR1_DISCNUM_Pos (13U)
1559#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
1560#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1561#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
1562#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
1563#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
1564#define ADC_CR1_JAWDEN_Pos (22U)
1565#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
1566#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
1567#define ADC_CR1_AWDEN_Pos (23U)
1568#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
1569#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
1570#define ADC_CR1_RES_Pos (24U)
1571#define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
1572#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
1573#define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
1574#define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
1575#define ADC_CR1_OVRIE_Pos (26U)
1576#define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
1577#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
1578
1579/******************* Bit definition for ADC_CR2 register ********************/
1580#define ADC_CR2_ADON_Pos (0U)
1581#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
1582#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
1583#define ADC_CR2_CONT_Pos (1U)
1584#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
1585#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
1586#define ADC_CR2_DMA_Pos (8U)
1587#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
1588#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
1589#define ADC_CR2_DDS_Pos (9U)
1590#define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
1591#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
1592#define ADC_CR2_EOCS_Pos (10U)
1593#define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
1594#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
1595#define ADC_CR2_ALIGN_Pos (11U)
1596#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
1597#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
1598#define ADC_CR2_JEXTSEL_Pos (16U)
1599#define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
1600#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1601#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
1602#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
1603#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
1604#define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
1605#define ADC_CR2_JEXTEN_Pos (20U)
1606#define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
1607#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1608#define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
1609#define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
1610#define ADC_CR2_JSWSTART_Pos (22U)
1611#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
1612#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
1613#define ADC_CR2_EXTSEL_Pos (24U)
1614#define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
1615#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1616#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
1617#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
1618#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
1619#define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
1620#define ADC_CR2_EXTEN_Pos (28U)
1621#define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
1622#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1623#define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
1624#define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
1625#define ADC_CR2_SWSTART_Pos (30U)
1626#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
1627#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
1628
1629/****************** Bit definition for ADC_SMPR1 register *******************/
1630#define ADC_SMPR1_SMP10_Pos (0U)
1631#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
1632#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1633#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
1634#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
1635#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
1636#define ADC_SMPR1_SMP11_Pos (3U)
1637#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
1638#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1639#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
1640#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
1641#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
1642#define ADC_SMPR1_SMP12_Pos (6U)
1643#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
1644#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1645#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
1646#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
1647#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
1648#define ADC_SMPR1_SMP13_Pos (9U)
1649#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
1650#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1651#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
1652#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
1653#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
1654#define ADC_SMPR1_SMP14_Pos (12U)
1655#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
1656#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1657#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
1658#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
1659#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
1660#define ADC_SMPR1_SMP15_Pos (15U)
1661#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
1662#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1663#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
1664#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
1665#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
1666#define ADC_SMPR1_SMP16_Pos (18U)
1667#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
1668#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1669#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
1670#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
1671#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
1672#define ADC_SMPR1_SMP17_Pos (21U)
1673#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
1674#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1675#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
1676#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
1677#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
1678#define ADC_SMPR1_SMP18_Pos (24U)
1679#define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
1680#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1681#define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
1682#define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
1683#define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
1684
1685/****************** Bit definition for ADC_SMPR2 register *******************/
1686#define ADC_SMPR2_SMP0_Pos (0U)
1687#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
1688#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1689#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
1690#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
1691#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
1692#define ADC_SMPR2_SMP1_Pos (3U)
1693#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
1694#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1695#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
1696#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
1697#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
1698#define ADC_SMPR2_SMP2_Pos (6U)
1699#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
1700#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1701#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
1702#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
1703#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
1704#define ADC_SMPR2_SMP3_Pos (9U)
1705#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
1706#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1707#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
1708#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
1709#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
1710#define ADC_SMPR2_SMP4_Pos (12U)
1711#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
1712#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1713#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
1714#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
1715#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
1716#define ADC_SMPR2_SMP5_Pos (15U)
1717#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
1718#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1719#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
1720#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
1721#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
1722#define ADC_SMPR2_SMP6_Pos (18U)
1723#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
1724#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1725#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
1726#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
1727#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
1728#define ADC_SMPR2_SMP7_Pos (21U)
1729#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
1730#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1731#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
1732#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
1733#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
1734#define ADC_SMPR2_SMP8_Pos (24U)
1735#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
1736#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1737#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
1738#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
1739#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
1740#define ADC_SMPR2_SMP9_Pos (27U)
1741#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
1742#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1743#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
1744#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
1745#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
1746
1747/****************** Bit definition for ADC_JOFR1 register *******************/
1748#define ADC_JOFR1_JOFFSET1_Pos (0U)
1749#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
1750#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
1751
1752/****************** Bit definition for ADC_JOFR2 register *******************/
1753#define ADC_JOFR2_JOFFSET2_Pos (0U)
1754#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
1755#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
1756
1757/****************** Bit definition for ADC_JOFR3 register *******************/
1758#define ADC_JOFR3_JOFFSET3_Pos (0U)
1759#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
1760#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
1761
1762/****************** Bit definition for ADC_JOFR4 register *******************/
1763#define ADC_JOFR4_JOFFSET4_Pos (0U)
1764#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
1765#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
1766
1767/******************* Bit definition for ADC_HTR register ********************/
1768#define ADC_HTR_HT_Pos (0U)
1769#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
1770#define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
1771
1772/******************* Bit definition for ADC_LTR register ********************/
1773#define ADC_LTR_LT_Pos (0U)
1774#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
1775#define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
1776
1777/******************* Bit definition for ADC_SQR1 register *******************/
1778#define ADC_SQR1_SQ13_Pos (0U)
1779#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
1780#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1781#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
1782#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
1783#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
1784#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
1785#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
1786#define ADC_SQR1_SQ14_Pos (5U)
1787#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
1788#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1789#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
1790#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
1791#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
1792#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
1793#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
1794#define ADC_SQR1_SQ15_Pos (10U)
1795#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
1796#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1797#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
1798#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
1799#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
1800#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
1801#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
1802#define ADC_SQR1_SQ16_Pos (15U)
1803#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
1804#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1805#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
1806#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
1807#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
1808#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
1809#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
1810#define ADC_SQR1_L_Pos (20U)
1811#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
1812#define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
1813#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
1814#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
1815#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
1816#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
1817
1818/******************* Bit definition for ADC_SQR2 register *******************/
1819#define ADC_SQR2_SQ7_Pos (0U)
1820#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
1821#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1822#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
1823#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
1824#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
1825#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
1826#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
1827#define ADC_SQR2_SQ8_Pos (5U)
1828#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
1829#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1830#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
1831#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
1832#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
1833#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
1834#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
1835#define ADC_SQR2_SQ9_Pos (10U)
1836#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
1837#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1838#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
1839#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
1840#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
1841#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
1842#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
1843#define ADC_SQR2_SQ10_Pos (15U)
1844#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
1845#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1846#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
1847#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
1848#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
1849#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
1850#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
1851#define ADC_SQR2_SQ11_Pos (20U)
1852#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
1853#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1854#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
1855#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
1856#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
1857#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
1858#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
1859#define ADC_SQR2_SQ12_Pos (25U)
1860#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
1861#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1862#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
1863#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
1864#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
1865#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
1866#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
1867
1868/******************* Bit definition for ADC_SQR3 register *******************/
1869#define ADC_SQR3_SQ1_Pos (0U)
1870#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
1871#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1872#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
1873#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
1874#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
1875#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
1876#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
1877#define ADC_SQR3_SQ2_Pos (5U)
1878#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
1879#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1880#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
1881#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
1882#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
1883#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
1884#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
1885#define ADC_SQR3_SQ3_Pos (10U)
1886#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
1887#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1888#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
1889#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
1890#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
1891#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
1892#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
1893#define ADC_SQR3_SQ4_Pos (15U)
1894#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
1895#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1896#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
1897#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
1898#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
1899#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
1900#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
1901#define ADC_SQR3_SQ5_Pos (20U)
1902#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
1903#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1904#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
1905#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
1906#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
1907#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
1908#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
1909#define ADC_SQR3_SQ6_Pos (25U)
1910#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
1911#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1912#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
1913#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
1914#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
1915#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
1916#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
1917
1918/******************* Bit definition for ADC_JSQR register *******************/
1919#define ADC_JSQR_JSQ1_Pos (0U)
1920#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
1921#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1922#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
1923#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
1924#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
1925#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
1926#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
1927#define ADC_JSQR_JSQ2_Pos (5U)
1928#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
1929#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1930#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
1931#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
1932#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
1933#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
1934#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
1935#define ADC_JSQR_JSQ3_Pos (10U)
1936#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
1937#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1938#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
1939#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
1940#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
1941#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
1942#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
1943#define ADC_JSQR_JSQ4_Pos (15U)
1944#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
1945#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1946#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
1947#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
1948#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
1949#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
1950#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
1951#define ADC_JSQR_JL_Pos (20U)
1952#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
1953#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
1954#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
1955#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
1956
1957/******************* Bit definition for ADC_JDR1 register *******************/
1958#define ADC_JDR1_JDATA_Pos (0U)
1959#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
1960#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
1961
1962/******************* Bit definition for ADC_JDR2 register *******************/
1963#define ADC_JDR2_JDATA_Pos (0U)
1964#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
1965#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
1966
1967/******************* Bit definition for ADC_JDR3 register *******************/
1968#define ADC_JDR3_JDATA_Pos (0U)
1969#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
1970#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
1971
1972/******************* Bit definition for ADC_JDR4 register *******************/
1973#define ADC_JDR4_JDATA_Pos (0U)
1974#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
1975#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
1976
1977/******************** Bit definition for ADC_DR register ********************/
1978#define ADC_DR_DATA_Pos (0U)
1979#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
1980#define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
1981#define ADC_DR_ADC2DATA_Pos (16U)
1982#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
1983#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
1984
1985/******************* Bit definition for ADC_CSR register ********************/
1986#define ADC_CSR_AWD1_Pos (0U)
1987#define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
1988#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
1989#define ADC_CSR_EOC1_Pos (1U)
1990#define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
1991#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
1992#define ADC_CSR_JEOC1_Pos (2U)
1993#define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
1994#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
1995#define ADC_CSR_JSTRT1_Pos (3U)
1996#define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
1997#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
1998#define ADC_CSR_STRT1_Pos (4U)
1999#define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
2000#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
2001#define ADC_CSR_OVR1_Pos (5U)
2002#define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
2003#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
2004#define ADC_CSR_AWD2_Pos (8U)
2005#define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
2006#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
2007#define ADC_CSR_EOC2_Pos (9U)
2008#define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
2009#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
2010#define ADC_CSR_JEOC2_Pos (10U)
2011#define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
2012#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
2013#define ADC_CSR_JSTRT2_Pos (11U)
2014#define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
2015#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
2016#define ADC_CSR_STRT2_Pos (12U)
2017#define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
2018#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
2019#define ADC_CSR_OVR2_Pos (13U)
2020#define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
2021#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */
2022#define ADC_CSR_AWD3_Pos (16U)
2023#define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
2024#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
2025#define ADC_CSR_EOC3_Pos (17U)
2026#define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
2027#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
2028#define ADC_CSR_JEOC3_Pos (18U)
2029#define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
2030#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
2031#define ADC_CSR_JSTRT3_Pos (19U)
2032#define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
2033#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
2034#define ADC_CSR_STRT3_Pos (20U)
2035#define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
2036#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
2037#define ADC_CSR_OVR3_Pos (21U)
2038#define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
2039#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */
2040
2041/* Legacy defines */
2042#define ADC_CSR_DOVR1 ADC_CSR_OVR1
2043#define ADC_CSR_DOVR2 ADC_CSR_OVR2
2044#define ADC_CSR_DOVR3 ADC_CSR_OVR3
2045
2046/******************* Bit definition for ADC_CCR register ********************/
2047#define ADC_CCR_MULTI_Pos (0U)
2048#define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
2049#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
2050#define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
2051#define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
2052#define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
2053#define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
2054#define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
2055#define ADC_CCR_DELAY_Pos (8U)
2056#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
2057#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
2058#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
2059#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
2060#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
2061#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
2062#define ADC_CCR_DDS_Pos (13U)
2063#define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
2064#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
2065#define ADC_CCR_DMA_Pos (14U)
2066#define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
2067#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
2068#define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
2069#define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
2070#define ADC_CCR_ADCPRE_Pos (16U)
2071#define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
2072#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
2073#define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
2074#define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
2075#define ADC_CCR_VBATE_Pos (22U)
2076#define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
2077#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
2078#define ADC_CCR_TSVREFE_Pos (23U)
2079#define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
2080#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
2081
2082/******************* Bit definition for ADC_CDR register ********************/
2083#define ADC_CDR_DATA1_Pos (0U)
2084#define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
2085#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
2086#define ADC_CDR_DATA2_Pos (16U)
2087#define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
2088#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
2089
2090/* Legacy defines */
2091#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
2092#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
2093
2094/******************************************************************************/
2095/* */
2096/* Controller Area Network */
2097/* */
2098/******************************************************************************/
2099/*!<CAN control and status registers */
2100/******************* Bit definition for CAN_MCR register ********************/
2101#define CAN_MCR_INRQ_Pos (0U)
2102#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
2103#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
2104#define CAN_MCR_SLEEP_Pos (1U)
2105#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
2106#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
2107#define CAN_MCR_TXFP_Pos (2U)
2108#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
2109#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
2110#define CAN_MCR_RFLM_Pos (3U)
2111#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
2112#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
2113#define CAN_MCR_NART_Pos (4U)
2114#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
2115#define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
2116#define CAN_MCR_AWUM_Pos (5U)
2117#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
2118#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
2119#define CAN_MCR_ABOM_Pos (6U)
2120#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
2121#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
2122#define CAN_MCR_TTCM_Pos (7U)
2123#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
2124#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
2125#define CAN_MCR_RESET_Pos (15U)
2126#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
2127#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
2128#define CAN_MCR_DBF_Pos (16U)
2129#define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
2130#define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
2131/******************* Bit definition for CAN_MSR register ********************/
2132#define CAN_MSR_INAK_Pos (0U)
2133#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
2134#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
2135#define CAN_MSR_SLAK_Pos (1U)
2136#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
2137#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
2138#define CAN_MSR_ERRI_Pos (2U)
2139#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
2140#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
2141#define CAN_MSR_WKUI_Pos (3U)
2142#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
2143#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
2144#define CAN_MSR_SLAKI_Pos (4U)
2145#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
2146#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
2147#define CAN_MSR_TXM_Pos (8U)
2148#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
2149#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
2150#define CAN_MSR_RXM_Pos (9U)
2151#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
2152#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
2153#define CAN_MSR_SAMP_Pos (10U)
2154#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
2155#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
2156#define CAN_MSR_RX_Pos (11U)
2157#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
2158#define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
2159
2160/******************* Bit definition for CAN_TSR register ********************/
2161#define CAN_TSR_RQCP0_Pos (0U)
2162#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
2163#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
2164#define CAN_TSR_TXOK0_Pos (1U)
2165#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
2166#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
2167#define CAN_TSR_ALST0_Pos (2U)
2168#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
2169#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
2170#define CAN_TSR_TERR0_Pos (3U)
2171#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
2172#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
2173#define CAN_TSR_ABRQ0_Pos (7U)
2174#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
2175#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
2176#define CAN_TSR_RQCP1_Pos (8U)
2177#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
2178#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
2179#define CAN_TSR_TXOK1_Pos (9U)
2180#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
2181#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
2182#define CAN_TSR_ALST1_Pos (10U)
2183#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
2184#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
2185#define CAN_TSR_TERR1_Pos (11U)
2186#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
2187#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
2188#define CAN_TSR_ABRQ1_Pos (15U)
2189#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
2190#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
2191#define CAN_TSR_RQCP2_Pos (16U)
2192#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
2193#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
2194#define CAN_TSR_TXOK2_Pos (17U)
2195#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
2196#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
2197#define CAN_TSR_ALST2_Pos (18U)
2198#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
2199#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
2200#define CAN_TSR_TERR2_Pos (19U)
2201#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
2202#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
2203#define CAN_TSR_ABRQ2_Pos (23U)
2204#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
2205#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
2206#define CAN_TSR_CODE_Pos (24U)
2207#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
2208#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
2209
2210#define CAN_TSR_TME_Pos (26U)
2211#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
2212#define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
2213#define CAN_TSR_TME0_Pos (26U)
2214#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
2215#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
2216#define CAN_TSR_TME1_Pos (27U)
2217#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
2218#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
2219#define CAN_TSR_TME2_Pos (28U)
2220#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
2221#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
2222
2223#define CAN_TSR_LOW_Pos (29U)
2224#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
2225#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
2226#define CAN_TSR_LOW0_Pos (29U)
2227#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
2228#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
2229#define CAN_TSR_LOW1_Pos (30U)
2230#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
2231#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
2232#define CAN_TSR_LOW2_Pos (31U)
2233#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
2234#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
2235
2236/******************* Bit definition for CAN_RF0R register *******************/
2237#define CAN_RF0R_FMP0_Pos (0U)
2238#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
2239#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
2240#define CAN_RF0R_FULL0_Pos (3U)
2241#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
2242#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
2243#define CAN_RF0R_FOVR0_Pos (4U)
2244#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
2245#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
2246#define CAN_RF0R_RFOM0_Pos (5U)
2247#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
2248#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
2249
2250/******************* Bit definition for CAN_RF1R register *******************/
2251#define CAN_RF1R_FMP1_Pos (0U)
2252#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
2253#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
2254#define CAN_RF1R_FULL1_Pos (3U)
2255#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
2256#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
2257#define CAN_RF1R_FOVR1_Pos (4U)
2258#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
2259#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
2260#define CAN_RF1R_RFOM1_Pos (5U)
2261#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
2262#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
2263
2264/******************** Bit definition for CAN_IER register *******************/
2265#define CAN_IER_TMEIE_Pos (0U)
2266#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
2267#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
2268#define CAN_IER_FMPIE0_Pos (1U)
2269#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
2270#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
2271#define CAN_IER_FFIE0_Pos (2U)
2272#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
2273#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
2274#define CAN_IER_FOVIE0_Pos (3U)
2275#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
2276#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
2277#define CAN_IER_FMPIE1_Pos (4U)
2278#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
2279#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
2280#define CAN_IER_FFIE1_Pos (5U)
2281#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
2282#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
2283#define CAN_IER_FOVIE1_Pos (6U)
2284#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
2285#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
2286#define CAN_IER_EWGIE_Pos (8U)
2287#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
2288#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
2289#define CAN_IER_EPVIE_Pos (9U)
2290#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
2291#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
2292#define CAN_IER_BOFIE_Pos (10U)
2293#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
2294#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
2295#define CAN_IER_LECIE_Pos (11U)
2296#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
2297#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
2298#define CAN_IER_ERRIE_Pos (15U)
2299#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
2300#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
2301#define CAN_IER_WKUIE_Pos (16U)
2302#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
2303#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
2304#define CAN_IER_SLKIE_Pos (17U)
2305#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
2306#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
2307#define CAN_IER_EWGIE_Pos (8U)
2308
2309/******************** Bit definition for CAN_ESR register *******************/
2310#define CAN_ESR_EWGF_Pos (0U)
2311#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
2312#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
2313#define CAN_ESR_EPVF_Pos (1U)
2314#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
2315#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
2316#define CAN_ESR_BOFF_Pos (2U)
2317#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
2318#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
2319
2320#define CAN_ESR_LEC_Pos (4U)
2321#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
2322#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
2323#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
2324#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
2325#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
2326
2327#define CAN_ESR_TEC_Pos (16U)
2328#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
2329#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
2330#define CAN_ESR_REC_Pos (24U)
2331#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
2332#define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
2333
2334/******************* Bit definition for CAN_BTR register ********************/
2335#define CAN_BTR_BRP_Pos (0U)
2336#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
2337#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
2338#define CAN_BTR_TS1_Pos (16U)
2339#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
2340#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
2341#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
2342#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
2343#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
2344#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
2345#define CAN_BTR_TS2_Pos (20U)
2346#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
2347#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
2348#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
2349#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
2350#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
2351#define CAN_BTR_SJW_Pos (24U)
2352#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
2353#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
2354#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
2355#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
2356#define CAN_BTR_LBKM_Pos (30U)
2357#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
2358#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
2359#define CAN_BTR_SILM_Pos (31U)
2360#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
2361#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
2362
2363
2364/*!<Mailbox registers */
2365/****************** Bit definition for CAN_TI0R register ********************/
2366#define CAN_TI0R_TXRQ_Pos (0U)
2367#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
2368#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
2369#define CAN_TI0R_RTR_Pos (1U)
2370#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
2371#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
2372#define CAN_TI0R_IDE_Pos (2U)
2373#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
2374#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
2375#define CAN_TI0R_EXID_Pos (3U)
2376#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
2377#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
2378#define CAN_TI0R_STID_Pos (21U)
2379#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
2380#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2381
2382/****************** Bit definition for CAN_TDT0R register *******************/
2383#define CAN_TDT0R_DLC_Pos (0U)
2384#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
2385#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
2386#define CAN_TDT0R_TGT_Pos (8U)
2387#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
2388#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
2389#define CAN_TDT0R_TIME_Pos (16U)
2390#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2391#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
2392
2393/****************** Bit definition for CAN_TDL0R register *******************/
2394#define CAN_TDL0R_DATA0_Pos (0U)
2395#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
2396#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
2397#define CAN_TDL0R_DATA1_Pos (8U)
2398#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2399#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
2400#define CAN_TDL0R_DATA2_Pos (16U)
2401#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2402#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
2403#define CAN_TDL0R_DATA3_Pos (24U)
2404#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
2405#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
2406
2407/****************** Bit definition for CAN_TDH0R register *******************/
2408#define CAN_TDH0R_DATA4_Pos (0U)
2409#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
2410#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
2411#define CAN_TDH0R_DATA5_Pos (8U)
2412#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2413#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
2414#define CAN_TDH0R_DATA6_Pos (16U)
2415#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2416#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
2417#define CAN_TDH0R_DATA7_Pos (24U)
2418#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
2419#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
2420
2421/******************* Bit definition for CAN_TI1R register *******************/
2422#define CAN_TI1R_TXRQ_Pos (0U)
2423#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
2424#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
2425#define CAN_TI1R_RTR_Pos (1U)
2426#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
2427#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
2428#define CAN_TI1R_IDE_Pos (2U)
2429#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
2430#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
2431#define CAN_TI1R_EXID_Pos (3U)
2432#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
2433#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
2434#define CAN_TI1R_STID_Pos (21U)
2435#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
2436#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2437
2438/******************* Bit definition for CAN_TDT1R register ******************/
2439#define CAN_TDT1R_DLC_Pos (0U)
2440#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
2441#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
2442#define CAN_TDT1R_TGT_Pos (8U)
2443#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
2444#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
2445#define CAN_TDT1R_TIME_Pos (16U)
2446#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2447#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
2448
2449/******************* Bit definition for CAN_TDL1R register ******************/
2450#define CAN_TDL1R_DATA0_Pos (0U)
2451#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
2452#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
2453#define CAN_TDL1R_DATA1_Pos (8U)
2454#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2455#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
2456#define CAN_TDL1R_DATA2_Pos (16U)
2457#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2458#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
2459#define CAN_TDL1R_DATA3_Pos (24U)
2460#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
2461#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
2462
2463/******************* Bit definition for CAN_TDH1R register ******************/
2464#define CAN_TDH1R_DATA4_Pos (0U)
2465#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
2466#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
2467#define CAN_TDH1R_DATA5_Pos (8U)
2468#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2469#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
2470#define CAN_TDH1R_DATA6_Pos (16U)
2471#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2472#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
2473#define CAN_TDH1R_DATA7_Pos (24U)
2474#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
2475#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
2476
2477/******************* Bit definition for CAN_TI2R register *******************/
2478#define CAN_TI2R_TXRQ_Pos (0U)
2479#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
2480#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
2481#define CAN_TI2R_RTR_Pos (1U)
2482#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
2483#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
2484#define CAN_TI2R_IDE_Pos (2U)
2485#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
2486#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
2487#define CAN_TI2R_EXID_Pos (3U)
2488#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
2489#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
2490#define CAN_TI2R_STID_Pos (21U)
2491#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
2492#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2493
2494/******************* Bit definition for CAN_TDT2R register ******************/
2495#define CAN_TDT2R_DLC_Pos (0U)
2496#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
2497#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
2498#define CAN_TDT2R_TGT_Pos (8U)
2499#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
2500#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
2501#define CAN_TDT2R_TIME_Pos (16U)
2502#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
2503#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
2504
2505/******************* Bit definition for CAN_TDL2R register ******************/
2506#define CAN_TDL2R_DATA0_Pos (0U)
2507#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
2508#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
2509#define CAN_TDL2R_DATA1_Pos (8U)
2510#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
2511#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
2512#define CAN_TDL2R_DATA2_Pos (16U)
2513#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
2514#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
2515#define CAN_TDL2R_DATA3_Pos (24U)
2516#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
2517#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
2518
2519/******************* Bit definition for CAN_TDH2R register ******************/
2520#define CAN_TDH2R_DATA4_Pos (0U)
2521#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
2522#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
2523#define CAN_TDH2R_DATA5_Pos (8U)
2524#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
2525#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
2526#define CAN_TDH2R_DATA6_Pos (16U)
2527#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
2528#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
2529#define CAN_TDH2R_DATA7_Pos (24U)
2530#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
2531#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
2532
2533/******************* Bit definition for CAN_RI0R register *******************/
2534#define CAN_RI0R_RTR_Pos (1U)
2535#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
2536#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
2537#define CAN_RI0R_IDE_Pos (2U)
2538#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
2539#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
2540#define CAN_RI0R_EXID_Pos (3U)
2541#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
2542#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
2543#define CAN_RI0R_STID_Pos (21U)
2544#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
2545#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2546
2547/******************* Bit definition for CAN_RDT0R register ******************/
2548#define CAN_RDT0R_DLC_Pos (0U)
2549#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
2550#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
2551#define CAN_RDT0R_FMI_Pos (8U)
2552#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
2553#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
2554#define CAN_RDT0R_TIME_Pos (16U)
2555#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2556#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
2557
2558/******************* Bit definition for CAN_RDL0R register ******************/
2559#define CAN_RDL0R_DATA0_Pos (0U)
2560#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
2561#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
2562#define CAN_RDL0R_DATA1_Pos (8U)
2563#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2564#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
2565#define CAN_RDL0R_DATA2_Pos (16U)
2566#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2567#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
2568#define CAN_RDL0R_DATA3_Pos (24U)
2569#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
2570#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
2571
2572/******************* Bit definition for CAN_RDH0R register ******************/
2573#define CAN_RDH0R_DATA4_Pos (0U)
2574#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
2575#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
2576#define CAN_RDH0R_DATA5_Pos (8U)
2577#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2578#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
2579#define CAN_RDH0R_DATA6_Pos (16U)
2580#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2581#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
2582#define CAN_RDH0R_DATA7_Pos (24U)
2583#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
2584#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
2585
2586/******************* Bit definition for CAN_RI1R register *******************/
2587#define CAN_RI1R_RTR_Pos (1U)
2588#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
2589#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
2590#define CAN_RI1R_IDE_Pos (2U)
2591#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
2592#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
2593#define CAN_RI1R_EXID_Pos (3U)
2594#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
2595#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
2596#define CAN_RI1R_STID_Pos (21U)
2597#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
2598#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2599
2600/******************* Bit definition for CAN_RDT1R register ******************/
2601#define CAN_RDT1R_DLC_Pos (0U)
2602#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
2603#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
2604#define CAN_RDT1R_FMI_Pos (8U)
2605#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
2606#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
2607#define CAN_RDT1R_TIME_Pos (16U)
2608#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2609#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
2610
2611/******************* Bit definition for CAN_RDL1R register ******************/
2612#define CAN_RDL1R_DATA0_Pos (0U)
2613#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
2614#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
2615#define CAN_RDL1R_DATA1_Pos (8U)
2616#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2617#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
2618#define CAN_RDL1R_DATA2_Pos (16U)
2619#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2620#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
2621#define CAN_RDL1R_DATA3_Pos (24U)
2622#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
2623#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
2624
2625/******************* Bit definition for CAN_RDH1R register ******************/
2626#define CAN_RDH1R_DATA4_Pos (0U)
2627#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
2628#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
2629#define CAN_RDH1R_DATA5_Pos (8U)
2630#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2631#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
2632#define CAN_RDH1R_DATA6_Pos (16U)
2633#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2634#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
2635#define CAN_RDH1R_DATA7_Pos (24U)
2636#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
2637#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
2638
2639/*!<CAN filter registers */
2640/******************* Bit definition for CAN_FMR register ********************/
2641#define CAN_FMR_FINIT_Pos (0U)
2642#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
2643#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
2644#define CAN_FMR_CAN2SB_Pos (8U)
2645#define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
2646#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
2647
2648/******************* Bit definition for CAN_FM1R register *******************/
2649#define CAN_FM1R_FBM_Pos (0U)
2650#define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
2651#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
2652#define CAN_FM1R_FBM0_Pos (0U)
2653#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
2654#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
2655#define CAN_FM1R_FBM1_Pos (1U)
2656#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
2657#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
2658#define CAN_FM1R_FBM2_Pos (2U)
2659#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
2660#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
2661#define CAN_FM1R_FBM3_Pos (3U)
2662#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
2663#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
2664#define CAN_FM1R_FBM4_Pos (4U)
2665#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
2666#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
2667#define CAN_FM1R_FBM5_Pos (5U)
2668#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
2669#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
2670#define CAN_FM1R_FBM6_Pos (6U)
2671#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
2672#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
2673#define CAN_FM1R_FBM7_Pos (7U)
2674#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
2675#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
2676#define CAN_FM1R_FBM8_Pos (8U)
2677#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
2678#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
2679#define CAN_FM1R_FBM9_Pos (9U)
2680#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
2681#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
2682#define CAN_FM1R_FBM10_Pos (10U)
2683#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
2684#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
2685#define CAN_FM1R_FBM11_Pos (11U)
2686#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
2687#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
2688#define CAN_FM1R_FBM12_Pos (12U)
2689#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
2690#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
2691#define CAN_FM1R_FBM13_Pos (13U)
2692#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
2693#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
2694#define CAN_FM1R_FBM14_Pos (14U)
2695#define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
2696#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
2697#define CAN_FM1R_FBM15_Pos (15U)
2698#define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
2699#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
2700#define CAN_FM1R_FBM16_Pos (16U)
2701#define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
2702#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
2703#define CAN_FM1R_FBM17_Pos (17U)
2704#define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
2705#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
2706#define CAN_FM1R_FBM18_Pos (18U)
2707#define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
2708#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
2709#define CAN_FM1R_FBM19_Pos (19U)
2710#define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
2711#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
2712#define CAN_FM1R_FBM20_Pos (20U)
2713#define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
2714#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
2715#define CAN_FM1R_FBM21_Pos (21U)
2716#define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
2717#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
2718#define CAN_FM1R_FBM22_Pos (22U)
2719#define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
2720#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
2721#define CAN_FM1R_FBM23_Pos (23U)
2722#define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
2723#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
2724#define CAN_FM1R_FBM24_Pos (24U)
2725#define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
2726#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
2727#define CAN_FM1R_FBM25_Pos (25U)
2728#define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
2729#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
2730#define CAN_FM1R_FBM26_Pos (26U)
2731#define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
2732#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
2733#define CAN_FM1R_FBM27_Pos (27U)
2734#define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
2735#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
2736
2737/******************* Bit definition for CAN_FS1R register *******************/
2738#define CAN_FS1R_FSC_Pos (0U)
2739#define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
2740#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
2741#define CAN_FS1R_FSC0_Pos (0U)
2742#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
2743#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
2744#define CAN_FS1R_FSC1_Pos (1U)
2745#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
2746#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
2747#define CAN_FS1R_FSC2_Pos (2U)
2748#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
2749#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
2750#define CAN_FS1R_FSC3_Pos (3U)
2751#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
2752#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
2753#define CAN_FS1R_FSC4_Pos (4U)
2754#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
2755#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
2756#define CAN_FS1R_FSC5_Pos (5U)
2757#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
2758#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
2759#define CAN_FS1R_FSC6_Pos (6U)
2760#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
2761#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
2762#define CAN_FS1R_FSC7_Pos (7U)
2763#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
2764#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
2765#define CAN_FS1R_FSC8_Pos (8U)
2766#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
2767#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
2768#define CAN_FS1R_FSC9_Pos (9U)
2769#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
2770#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
2771#define CAN_FS1R_FSC10_Pos (10U)
2772#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
2773#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
2774#define CAN_FS1R_FSC11_Pos (11U)
2775#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
2776#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
2777#define CAN_FS1R_FSC12_Pos (12U)
2778#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
2779#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
2780#define CAN_FS1R_FSC13_Pos (13U)
2781#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
2782#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
2783#define CAN_FS1R_FSC14_Pos (14U)
2784#define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
2785#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
2786#define CAN_FS1R_FSC15_Pos (15U)
2787#define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
2788#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
2789#define CAN_FS1R_FSC16_Pos (16U)
2790#define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
2791#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
2792#define CAN_FS1R_FSC17_Pos (17U)
2793#define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
2794#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
2795#define CAN_FS1R_FSC18_Pos (18U)
2796#define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
2797#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
2798#define CAN_FS1R_FSC19_Pos (19U)
2799#define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
2800#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
2801#define CAN_FS1R_FSC20_Pos (20U)
2802#define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
2803#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
2804#define CAN_FS1R_FSC21_Pos (21U)
2805#define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
2806#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
2807#define CAN_FS1R_FSC22_Pos (22U)
2808#define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
2809#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
2810#define CAN_FS1R_FSC23_Pos (23U)
2811#define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
2812#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
2813#define CAN_FS1R_FSC24_Pos (24U)
2814#define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
2815#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
2816#define CAN_FS1R_FSC25_Pos (25U)
2817#define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
2818#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
2819#define CAN_FS1R_FSC26_Pos (26U)
2820#define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
2821#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
2822#define CAN_FS1R_FSC27_Pos (27U)
2823#define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
2824#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
2825
2826/****************** Bit definition for CAN_FFA1R register *******************/
2827#define CAN_FFA1R_FFA_Pos (0U)
2828#define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
2829#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
2830#define CAN_FFA1R_FFA0_Pos (0U)
2831#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
2832#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
2833#define CAN_FFA1R_FFA1_Pos (1U)
2834#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
2835#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
2836#define CAN_FFA1R_FFA2_Pos (2U)
2837#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
2838#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
2839#define CAN_FFA1R_FFA3_Pos (3U)
2840#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
2841#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
2842#define CAN_FFA1R_FFA4_Pos (4U)
2843#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
2844#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
2845#define CAN_FFA1R_FFA5_Pos (5U)
2846#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
2847#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
2848#define CAN_FFA1R_FFA6_Pos (6U)
2849#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
2850#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
2851#define CAN_FFA1R_FFA7_Pos (7U)
2852#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
2853#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
2854#define CAN_FFA1R_FFA8_Pos (8U)
2855#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
2856#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
2857#define CAN_FFA1R_FFA9_Pos (9U)
2858#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
2859#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
2860#define CAN_FFA1R_FFA10_Pos (10U)
2861#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
2862#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
2863#define CAN_FFA1R_FFA11_Pos (11U)
2864#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
2865#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
2866#define CAN_FFA1R_FFA12_Pos (12U)
2867#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
2868#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
2869#define CAN_FFA1R_FFA13_Pos (13U)
2870#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
2871#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
2872#define CAN_FFA1R_FFA14_Pos (14U)
2873#define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
2874#define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
2875#define CAN_FFA1R_FFA15_Pos (15U)
2876#define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
2877#define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
2878#define CAN_FFA1R_FFA16_Pos (16U)
2879#define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
2880#define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
2881#define CAN_FFA1R_FFA17_Pos (17U)
2882#define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
2883#define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
2884#define CAN_FFA1R_FFA18_Pos (18U)
2885#define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
2886#define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
2887#define CAN_FFA1R_FFA19_Pos (19U)
2888#define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
2889#define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
2890#define CAN_FFA1R_FFA20_Pos (20U)
2891#define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
2892#define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
2893#define CAN_FFA1R_FFA21_Pos (21U)
2894#define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
2895#define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
2896#define CAN_FFA1R_FFA22_Pos (22U)
2897#define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
2898#define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
2899#define CAN_FFA1R_FFA23_Pos (23U)
2900#define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
2901#define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
2902#define CAN_FFA1R_FFA24_Pos (24U)
2903#define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
2904#define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
2905#define CAN_FFA1R_FFA25_Pos (25U)
2906#define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
2907#define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
2908#define CAN_FFA1R_FFA26_Pos (26U)
2909#define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
2910#define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
2911#define CAN_FFA1R_FFA27_Pos (27U)
2912#define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
2913#define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
2914
2915/******************* Bit definition for CAN_FA1R register *******************/
2916#define CAN_FA1R_FACT_Pos (0U)
2917#define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
2918#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
2919#define CAN_FA1R_FACT0_Pos (0U)
2920#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
2921#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
2922#define CAN_FA1R_FACT1_Pos (1U)
2923#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
2924#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
2925#define CAN_FA1R_FACT2_Pos (2U)
2926#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
2927#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
2928#define CAN_FA1R_FACT3_Pos (3U)
2929#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
2930#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
2931#define CAN_FA1R_FACT4_Pos (4U)
2932#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
2933#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
2934#define CAN_FA1R_FACT5_Pos (5U)
2935#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
2936#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
2937#define CAN_FA1R_FACT6_Pos (6U)
2938#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
2939#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
2940#define CAN_FA1R_FACT7_Pos (7U)
2941#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
2942#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
2943#define CAN_FA1R_FACT8_Pos (8U)
2944#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
2945#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
2946#define CAN_FA1R_FACT9_Pos (9U)
2947#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
2948#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
2949#define CAN_FA1R_FACT10_Pos (10U)
2950#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
2951#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
2952#define CAN_FA1R_FACT11_Pos (11U)
2953#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
2954#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
2955#define CAN_FA1R_FACT12_Pos (12U)
2956#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
2957#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
2958#define CAN_FA1R_FACT13_Pos (13U)
2959#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
2960#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
2961#define CAN_FA1R_FACT14_Pos (14U)
2962#define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
2963#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
2964#define CAN_FA1R_FACT15_Pos (15U)
2965#define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
2966#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
2967#define CAN_FA1R_FACT16_Pos (16U)
2968#define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
2969#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
2970#define CAN_FA1R_FACT17_Pos (17U)
2971#define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
2972#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
2973#define CAN_FA1R_FACT18_Pos (18U)
2974#define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
2975#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
2976#define CAN_FA1R_FACT19_Pos (19U)
2977#define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
2978#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
2979#define CAN_FA1R_FACT20_Pos (20U)
2980#define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
2981#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
2982#define CAN_FA1R_FACT21_Pos (21U)
2983#define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
2984#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
2985#define CAN_FA1R_FACT22_Pos (22U)
2986#define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
2987#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
2988#define CAN_FA1R_FACT23_Pos (23U)
2989#define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
2990#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
2991#define CAN_FA1R_FACT24_Pos (24U)
2992#define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
2993#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
2994#define CAN_FA1R_FACT25_Pos (25U)
2995#define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
2996#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
2997#define CAN_FA1R_FACT26_Pos (26U)
2998#define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
2999#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
3000#define CAN_FA1R_FACT27_Pos (27U)
3001#define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
3002#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
3003
3004
3005/******************* Bit definition for CAN_F0R1 register *******************/
3006#define CAN_F0R1_FB0_Pos (0U)
3007#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
3008#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
3009#define CAN_F0R1_FB1_Pos (1U)
3010#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
3011#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
3012#define CAN_F0R1_FB2_Pos (2U)
3013#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
3014#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
3015#define CAN_F0R1_FB3_Pos (3U)
3016#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
3017#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
3018#define CAN_F0R1_FB4_Pos (4U)
3019#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
3020#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
3021#define CAN_F0R1_FB5_Pos (5U)
3022#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
3023#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
3024#define CAN_F0R1_FB6_Pos (6U)
3025#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
3026#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
3027#define CAN_F0R1_FB7_Pos (7U)
3028#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
3029#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
3030#define CAN_F0R1_FB8_Pos (8U)
3031#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
3032#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
3033#define CAN_F0R1_FB9_Pos (9U)
3034#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
3035#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
3036#define CAN_F0R1_FB10_Pos (10U)
3037#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
3038#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
3039#define CAN_F0R1_FB11_Pos (11U)
3040#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
3041#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
3042#define CAN_F0R1_FB12_Pos (12U)
3043#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
3044#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
3045#define CAN_F0R1_FB13_Pos (13U)
3046#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
3047#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
3048#define CAN_F0R1_FB14_Pos (14U)
3049#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
3050#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
3051#define CAN_F0R1_FB15_Pos (15U)
3052#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
3053#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
3054#define CAN_F0R1_FB16_Pos (16U)
3055#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
3056#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
3057#define CAN_F0R1_FB17_Pos (17U)
3058#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
3059#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
3060#define CAN_F0R1_FB18_Pos (18U)
3061#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
3062#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
3063#define CAN_F0R1_FB19_Pos (19U)
3064#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
3065#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
3066#define CAN_F0R1_FB20_Pos (20U)
3067#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
3068#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
3069#define CAN_F0R1_FB21_Pos (21U)
3070#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
3071#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
3072#define CAN_F0R1_FB22_Pos (22U)
3073#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
3074#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
3075#define CAN_F0R1_FB23_Pos (23U)
3076#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
3077#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
3078#define CAN_F0R1_FB24_Pos (24U)
3079#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
3080#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
3081#define CAN_F0R1_FB25_Pos (25U)
3082#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
3083#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
3084#define CAN_F0R1_FB26_Pos (26U)
3085#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
3086#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
3087#define CAN_F0R1_FB27_Pos (27U)
3088#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
3089#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
3090#define CAN_F0R1_FB28_Pos (28U)
3091#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
3092#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
3093#define CAN_F0R1_FB29_Pos (29U)
3094#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
3095#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
3096#define CAN_F0R1_FB30_Pos (30U)
3097#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
3098#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
3099#define CAN_F0R1_FB31_Pos (31U)
3100#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
3101#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
3102
3103/******************* Bit definition for CAN_F1R1 register *******************/
3104#define CAN_F1R1_FB0_Pos (0U)
3105#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
3106#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
3107#define CAN_F1R1_FB1_Pos (1U)
3108#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
3109#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
3110#define CAN_F1R1_FB2_Pos (2U)
3111#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
3112#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
3113#define CAN_F1R1_FB3_Pos (3U)
3114#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
3115#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
3116#define CAN_F1R1_FB4_Pos (4U)
3117#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
3118#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
3119#define CAN_F1R1_FB5_Pos (5U)
3120#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
3121#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
3122#define CAN_F1R1_FB6_Pos (6U)
3123#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
3124#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
3125#define CAN_F1R1_FB7_Pos (7U)
3126#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
3127#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
3128#define CAN_F1R1_FB8_Pos (8U)
3129#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
3130#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
3131#define CAN_F1R1_FB9_Pos (9U)
3132#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
3133#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
3134#define CAN_F1R1_FB10_Pos (10U)
3135#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
3136#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
3137#define CAN_F1R1_FB11_Pos (11U)
3138#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
3139#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
3140#define CAN_F1R1_FB12_Pos (12U)
3141#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
3142#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
3143#define CAN_F1R1_FB13_Pos (13U)
3144#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
3145#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
3146#define CAN_F1R1_FB14_Pos (14U)
3147#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
3148#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
3149#define CAN_F1R1_FB15_Pos (15U)
3150#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
3151#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
3152#define CAN_F1R1_FB16_Pos (16U)
3153#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
3154#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
3155#define CAN_F1R1_FB17_Pos (17U)
3156#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
3157#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
3158#define CAN_F1R1_FB18_Pos (18U)
3159#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
3160#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
3161#define CAN_F1R1_FB19_Pos (19U)
3162#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
3163#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
3164#define CAN_F1R1_FB20_Pos (20U)
3165#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
3166#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
3167#define CAN_F1R1_FB21_Pos (21U)
3168#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
3169#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
3170#define CAN_F1R1_FB22_Pos (22U)
3171#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
3172#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
3173#define CAN_F1R1_FB23_Pos (23U)
3174#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
3175#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
3176#define CAN_F1R1_FB24_Pos (24U)
3177#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
3178#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
3179#define CAN_F1R1_FB25_Pos (25U)
3180#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
3181#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
3182#define CAN_F1R1_FB26_Pos (26U)
3183#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
3184#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
3185#define CAN_F1R1_FB27_Pos (27U)
3186#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
3187#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
3188#define CAN_F1R1_FB28_Pos (28U)
3189#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
3190#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
3191#define CAN_F1R1_FB29_Pos (29U)
3192#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
3193#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
3194#define CAN_F1R1_FB30_Pos (30U)
3195#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
3196#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
3197#define CAN_F1R1_FB31_Pos (31U)
3198#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
3199#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
3200
3201/******************* Bit definition for CAN_F2R1 register *******************/
3202#define CAN_F2R1_FB0_Pos (0U)
3203#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
3204#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
3205#define CAN_F2R1_FB1_Pos (1U)
3206#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
3207#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
3208#define CAN_F2R1_FB2_Pos (2U)
3209#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
3210#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
3211#define CAN_F2R1_FB3_Pos (3U)
3212#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
3213#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
3214#define CAN_F2R1_FB4_Pos (4U)
3215#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
3216#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
3217#define CAN_F2R1_FB5_Pos (5U)
3218#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
3219#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
3220#define CAN_F2R1_FB6_Pos (6U)
3221#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
3222#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
3223#define CAN_F2R1_FB7_Pos (7U)
3224#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
3225#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
3226#define CAN_F2R1_FB8_Pos (8U)
3227#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
3228#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
3229#define CAN_F2R1_FB9_Pos (9U)
3230#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
3231#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
3232#define CAN_F2R1_FB10_Pos (10U)
3233#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
3234#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
3235#define CAN_F2R1_FB11_Pos (11U)
3236#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
3237#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
3238#define CAN_F2R1_FB12_Pos (12U)
3239#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
3240#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
3241#define CAN_F2R1_FB13_Pos (13U)
3242#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
3243#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
3244#define CAN_F2R1_FB14_Pos (14U)
3245#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
3246#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
3247#define CAN_F2R1_FB15_Pos (15U)
3248#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
3249#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
3250#define CAN_F2R1_FB16_Pos (16U)
3251#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
3252#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
3253#define CAN_F2R1_FB17_Pos (17U)
3254#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
3255#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
3256#define CAN_F2R1_FB18_Pos (18U)
3257#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
3258#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
3259#define CAN_F2R1_FB19_Pos (19U)
3260#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
3261#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
3262#define CAN_F2R1_FB20_Pos (20U)
3263#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
3264#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
3265#define CAN_F2R1_FB21_Pos (21U)
3266#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
3267#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
3268#define CAN_F2R1_FB22_Pos (22U)
3269#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
3270#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
3271#define CAN_F2R1_FB23_Pos (23U)
3272#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
3273#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
3274#define CAN_F2R1_FB24_Pos (24U)
3275#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
3276#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
3277#define CAN_F2R1_FB25_Pos (25U)
3278#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
3279#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
3280#define CAN_F2R1_FB26_Pos (26U)
3281#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
3282#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
3283#define CAN_F2R1_FB27_Pos (27U)
3284#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
3285#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
3286#define CAN_F2R1_FB28_Pos (28U)
3287#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
3288#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
3289#define CAN_F2R1_FB29_Pos (29U)
3290#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
3291#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
3292#define CAN_F2R1_FB30_Pos (30U)
3293#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
3294#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
3295#define CAN_F2R1_FB31_Pos (31U)
3296#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
3297#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
3298
3299/******************* Bit definition for CAN_F3R1 register *******************/
3300#define CAN_F3R1_FB0_Pos (0U)
3301#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
3302#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
3303#define CAN_F3R1_FB1_Pos (1U)
3304#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
3305#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
3306#define CAN_F3R1_FB2_Pos (2U)
3307#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
3308#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
3309#define CAN_F3R1_FB3_Pos (3U)
3310#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
3311#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
3312#define CAN_F3R1_FB4_Pos (4U)
3313#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
3314#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
3315#define CAN_F3R1_FB5_Pos (5U)
3316#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
3317#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
3318#define CAN_F3R1_FB6_Pos (6U)
3319#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
3320#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
3321#define CAN_F3R1_FB7_Pos (7U)
3322#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
3323#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
3324#define CAN_F3R1_FB8_Pos (8U)
3325#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
3326#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
3327#define CAN_F3R1_FB9_Pos (9U)
3328#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
3329#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
3330#define CAN_F3R1_FB10_Pos (10U)
3331#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
3332#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
3333#define CAN_F3R1_FB11_Pos (11U)
3334#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
3335#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
3336#define CAN_F3R1_FB12_Pos (12U)
3337#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
3338#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
3339#define CAN_F3R1_FB13_Pos (13U)
3340#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
3341#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
3342#define CAN_F3R1_FB14_Pos (14U)
3343#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
3344#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
3345#define CAN_F3R1_FB15_Pos (15U)
3346#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
3347#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
3348#define CAN_F3R1_FB16_Pos (16U)
3349#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
3350#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
3351#define CAN_F3R1_FB17_Pos (17U)
3352#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
3353#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
3354#define CAN_F3R1_FB18_Pos (18U)
3355#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
3356#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
3357#define CAN_F3R1_FB19_Pos (19U)
3358#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
3359#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
3360#define CAN_F3R1_FB20_Pos (20U)
3361#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
3362#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
3363#define CAN_F3R1_FB21_Pos (21U)
3364#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
3365#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
3366#define CAN_F3R1_FB22_Pos (22U)
3367#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
3368#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
3369#define CAN_F3R1_FB23_Pos (23U)
3370#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
3371#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
3372#define CAN_F3R1_FB24_Pos (24U)
3373#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
3374#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
3375#define CAN_F3R1_FB25_Pos (25U)
3376#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
3377#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
3378#define CAN_F3R1_FB26_Pos (26U)
3379#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
3380#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
3381#define CAN_F3R1_FB27_Pos (27U)
3382#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
3383#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
3384#define CAN_F3R1_FB28_Pos (28U)
3385#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
3386#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
3387#define CAN_F3R1_FB29_Pos (29U)
3388#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
3389#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
3390#define CAN_F3R1_FB30_Pos (30U)
3391#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
3392#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
3393#define CAN_F3R1_FB31_Pos (31U)
3394#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
3395#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
3396
3397/******************* Bit definition for CAN_F4R1 register *******************/
3398#define CAN_F4R1_FB0_Pos (0U)
3399#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
3400#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
3401#define CAN_F4R1_FB1_Pos (1U)
3402#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
3403#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
3404#define CAN_F4R1_FB2_Pos (2U)
3405#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
3406#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
3407#define CAN_F4R1_FB3_Pos (3U)
3408#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
3409#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
3410#define CAN_F4R1_FB4_Pos (4U)
3411#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
3412#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
3413#define CAN_F4R1_FB5_Pos (5U)
3414#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
3415#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
3416#define CAN_F4R1_FB6_Pos (6U)
3417#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
3418#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
3419#define CAN_F4R1_FB7_Pos (7U)
3420#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
3421#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
3422#define CAN_F4R1_FB8_Pos (8U)
3423#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
3424#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
3425#define CAN_F4R1_FB9_Pos (9U)
3426#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
3427#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
3428#define CAN_F4R1_FB10_Pos (10U)
3429#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
3430#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
3431#define CAN_F4R1_FB11_Pos (11U)
3432#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
3433#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
3434#define CAN_F4R1_FB12_Pos (12U)
3435#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
3436#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
3437#define CAN_F4R1_FB13_Pos (13U)
3438#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
3439#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
3440#define CAN_F4R1_FB14_Pos (14U)
3441#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
3442#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
3443#define CAN_F4R1_FB15_Pos (15U)
3444#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
3445#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
3446#define CAN_F4R1_FB16_Pos (16U)
3447#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
3448#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
3449#define CAN_F4R1_FB17_Pos (17U)
3450#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
3451#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
3452#define CAN_F4R1_FB18_Pos (18U)
3453#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
3454#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
3455#define CAN_F4R1_FB19_Pos (19U)
3456#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
3457#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
3458#define CAN_F4R1_FB20_Pos (20U)
3459#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
3460#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
3461#define CAN_F4R1_FB21_Pos (21U)
3462#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
3463#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
3464#define CAN_F4R1_FB22_Pos (22U)
3465#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
3466#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
3467#define CAN_F4R1_FB23_Pos (23U)
3468#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
3469#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
3470#define CAN_F4R1_FB24_Pos (24U)
3471#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
3472#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
3473#define CAN_F4R1_FB25_Pos (25U)
3474#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
3475#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
3476#define CAN_F4R1_FB26_Pos (26U)
3477#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
3478#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
3479#define CAN_F4R1_FB27_Pos (27U)
3480#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
3481#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
3482#define CAN_F4R1_FB28_Pos (28U)
3483#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
3484#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
3485#define CAN_F4R1_FB29_Pos (29U)
3486#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
3487#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
3488#define CAN_F4R1_FB30_Pos (30U)
3489#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
3490#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
3491#define CAN_F4R1_FB31_Pos (31U)
3492#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
3493#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
3494
3495/******************* Bit definition for CAN_F5R1 register *******************/
3496#define CAN_F5R1_FB0_Pos (0U)
3497#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
3498#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
3499#define CAN_F5R1_FB1_Pos (1U)
3500#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
3501#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
3502#define CAN_F5R1_FB2_Pos (2U)
3503#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
3504#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
3505#define CAN_F5R1_FB3_Pos (3U)
3506#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
3507#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
3508#define CAN_F5R1_FB4_Pos (4U)
3509#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
3510#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
3511#define CAN_F5R1_FB5_Pos (5U)
3512#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
3513#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
3514#define CAN_F5R1_FB6_Pos (6U)
3515#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
3516#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
3517#define CAN_F5R1_FB7_Pos (7U)
3518#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
3519#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
3520#define CAN_F5R1_FB8_Pos (8U)
3521#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
3522#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
3523#define CAN_F5R1_FB9_Pos (9U)
3524#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
3525#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
3526#define CAN_F5R1_FB10_Pos (10U)
3527#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
3528#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
3529#define CAN_F5R1_FB11_Pos (11U)
3530#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
3531#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
3532#define CAN_F5R1_FB12_Pos (12U)
3533#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
3534#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
3535#define CAN_F5R1_FB13_Pos (13U)
3536#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
3537#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
3538#define CAN_F5R1_FB14_Pos (14U)
3539#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
3540#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
3541#define CAN_F5R1_FB15_Pos (15U)
3542#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
3543#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
3544#define CAN_F5R1_FB16_Pos (16U)
3545#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
3546#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
3547#define CAN_F5R1_FB17_Pos (17U)
3548#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
3549#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
3550#define CAN_F5R1_FB18_Pos (18U)
3551#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
3552#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
3553#define CAN_F5R1_FB19_Pos (19U)
3554#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
3555#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
3556#define CAN_F5R1_FB20_Pos (20U)
3557#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
3558#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
3559#define CAN_F5R1_FB21_Pos (21U)
3560#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
3561#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
3562#define CAN_F5R1_FB22_Pos (22U)
3563#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
3564#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
3565#define CAN_F5R1_FB23_Pos (23U)
3566#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
3567#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
3568#define CAN_F5R1_FB24_Pos (24U)
3569#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
3570#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
3571#define CAN_F5R1_FB25_Pos (25U)
3572#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
3573#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
3574#define CAN_F5R1_FB26_Pos (26U)
3575#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
3576#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
3577#define CAN_F5R1_FB27_Pos (27U)
3578#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
3579#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
3580#define CAN_F5R1_FB28_Pos (28U)
3581#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
3582#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
3583#define CAN_F5R1_FB29_Pos (29U)
3584#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
3585#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
3586#define CAN_F5R1_FB30_Pos (30U)
3587#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
3588#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
3589#define CAN_F5R1_FB31_Pos (31U)
3590#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
3591#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
3592
3593/******************* Bit definition for CAN_F6R1 register *******************/
3594#define CAN_F6R1_FB0_Pos (0U)
3595#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
3596#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
3597#define CAN_F6R1_FB1_Pos (1U)
3598#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
3599#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
3600#define CAN_F6R1_FB2_Pos (2U)
3601#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
3602#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
3603#define CAN_F6R1_FB3_Pos (3U)
3604#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
3605#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
3606#define CAN_F6R1_FB4_Pos (4U)
3607#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
3608#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
3609#define CAN_F6R1_FB5_Pos (5U)
3610#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
3611#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
3612#define CAN_F6R1_FB6_Pos (6U)
3613#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
3614#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
3615#define CAN_F6R1_FB7_Pos (7U)
3616#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
3617#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
3618#define CAN_F6R1_FB8_Pos (8U)
3619#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
3620#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
3621#define CAN_F6R1_FB9_Pos (9U)
3622#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
3623#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
3624#define CAN_F6R1_FB10_Pos (10U)
3625#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
3626#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
3627#define CAN_F6R1_FB11_Pos (11U)
3628#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
3629#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
3630#define CAN_F6R1_FB12_Pos (12U)
3631#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
3632#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
3633#define CAN_F6R1_FB13_Pos (13U)
3634#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
3635#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
3636#define CAN_F6R1_FB14_Pos (14U)
3637#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
3638#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
3639#define CAN_F6R1_FB15_Pos (15U)
3640#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
3641#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
3642#define CAN_F6R1_FB16_Pos (16U)
3643#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
3644#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
3645#define CAN_F6R1_FB17_Pos (17U)
3646#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
3647#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
3648#define CAN_F6R1_FB18_Pos (18U)
3649#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
3650#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
3651#define CAN_F6R1_FB19_Pos (19U)
3652#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
3653#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
3654#define CAN_F6R1_FB20_Pos (20U)
3655#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
3656#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
3657#define CAN_F6R1_FB21_Pos (21U)
3658#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
3659#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
3660#define CAN_F6R1_FB22_Pos (22U)
3661#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
3662#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
3663#define CAN_F6R1_FB23_Pos (23U)
3664#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
3665#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
3666#define CAN_F6R1_FB24_Pos (24U)
3667#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
3668#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
3669#define CAN_F6R1_FB25_Pos (25U)
3670#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
3671#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
3672#define CAN_F6R1_FB26_Pos (26U)
3673#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
3674#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
3675#define CAN_F6R1_FB27_Pos (27U)
3676#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
3677#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
3678#define CAN_F6R1_FB28_Pos (28U)
3679#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
3680#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
3681#define CAN_F6R1_FB29_Pos (29U)
3682#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
3683#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
3684#define CAN_F6R1_FB30_Pos (30U)
3685#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
3686#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
3687#define CAN_F6R1_FB31_Pos (31U)
3688#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
3689#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
3690
3691/******************* Bit definition for CAN_F7R1 register *******************/
3692#define CAN_F7R1_FB0_Pos (0U)
3693#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
3694#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
3695#define CAN_F7R1_FB1_Pos (1U)
3696#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
3697#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
3698#define CAN_F7R1_FB2_Pos (2U)
3699#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
3700#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
3701#define CAN_F7R1_FB3_Pos (3U)
3702#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
3703#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
3704#define CAN_F7R1_FB4_Pos (4U)
3705#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
3706#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
3707#define CAN_F7R1_FB5_Pos (5U)
3708#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
3709#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
3710#define CAN_F7R1_FB6_Pos (6U)
3711#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
3712#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
3713#define CAN_F7R1_FB7_Pos (7U)
3714#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
3715#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
3716#define CAN_F7R1_FB8_Pos (8U)
3717#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
3718#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
3719#define CAN_F7R1_FB9_Pos (9U)
3720#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
3721#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
3722#define CAN_F7R1_FB10_Pos (10U)
3723#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
3724#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
3725#define CAN_F7R1_FB11_Pos (11U)
3726#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
3727#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
3728#define CAN_F7R1_FB12_Pos (12U)
3729#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
3730#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
3731#define CAN_F7R1_FB13_Pos (13U)
3732#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
3733#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
3734#define CAN_F7R1_FB14_Pos (14U)
3735#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
3736#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
3737#define CAN_F7R1_FB15_Pos (15U)
3738#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
3739#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
3740#define CAN_F7R1_FB16_Pos (16U)
3741#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
3742#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
3743#define CAN_F7R1_FB17_Pos (17U)
3744#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
3745#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
3746#define CAN_F7R1_FB18_Pos (18U)
3747#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
3748#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
3749#define CAN_F7R1_FB19_Pos (19U)
3750#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
3751#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
3752#define CAN_F7R1_FB20_Pos (20U)
3753#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
3754#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
3755#define CAN_F7R1_FB21_Pos (21U)
3756#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
3757#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
3758#define CAN_F7R1_FB22_Pos (22U)
3759#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
3760#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
3761#define CAN_F7R1_FB23_Pos (23U)
3762#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
3763#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
3764#define CAN_F7R1_FB24_Pos (24U)
3765#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
3766#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
3767#define CAN_F7R1_FB25_Pos (25U)
3768#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
3769#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
3770#define CAN_F7R1_FB26_Pos (26U)
3771#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
3772#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
3773#define CAN_F7R1_FB27_Pos (27U)
3774#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
3775#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
3776#define CAN_F7R1_FB28_Pos (28U)
3777#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
3778#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
3779#define CAN_F7R1_FB29_Pos (29U)
3780#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
3781#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
3782#define CAN_F7R1_FB30_Pos (30U)
3783#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
3784#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
3785#define CAN_F7R1_FB31_Pos (31U)
3786#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
3787#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
3788
3789/******************* Bit definition for CAN_F8R1 register *******************/
3790#define CAN_F8R1_FB0_Pos (0U)
3791#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
3792#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
3793#define CAN_F8R1_FB1_Pos (1U)
3794#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
3795#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
3796#define CAN_F8R1_FB2_Pos (2U)
3797#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
3798#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
3799#define CAN_F8R1_FB3_Pos (3U)
3800#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
3801#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
3802#define CAN_F8R1_FB4_Pos (4U)
3803#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
3804#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
3805#define CAN_F8R1_FB5_Pos (5U)
3806#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
3807#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
3808#define CAN_F8R1_FB6_Pos (6U)
3809#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
3810#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
3811#define CAN_F8R1_FB7_Pos (7U)
3812#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
3813#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
3814#define CAN_F8R1_FB8_Pos (8U)
3815#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
3816#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
3817#define CAN_F8R1_FB9_Pos (9U)
3818#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
3819#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
3820#define CAN_F8R1_FB10_Pos (10U)
3821#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
3822#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
3823#define CAN_F8R1_FB11_Pos (11U)
3824#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
3825#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
3826#define CAN_F8R1_FB12_Pos (12U)
3827#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
3828#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
3829#define CAN_F8R1_FB13_Pos (13U)
3830#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
3831#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
3832#define CAN_F8R1_FB14_Pos (14U)
3833#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
3834#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
3835#define CAN_F8R1_FB15_Pos (15U)
3836#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
3837#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
3838#define CAN_F8R1_FB16_Pos (16U)
3839#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
3840#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
3841#define CAN_F8R1_FB17_Pos (17U)
3842#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
3843#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
3844#define CAN_F8R1_FB18_Pos (18U)
3845#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
3846#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
3847#define CAN_F8R1_FB19_Pos (19U)
3848#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
3849#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
3850#define CAN_F8R1_FB20_Pos (20U)
3851#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
3852#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
3853#define CAN_F8R1_FB21_Pos (21U)
3854#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
3855#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
3856#define CAN_F8R1_FB22_Pos (22U)
3857#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
3858#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
3859#define CAN_F8R1_FB23_Pos (23U)
3860#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
3861#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
3862#define CAN_F8R1_FB24_Pos (24U)
3863#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
3864#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
3865#define CAN_F8R1_FB25_Pos (25U)
3866#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
3867#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
3868#define CAN_F8R1_FB26_Pos (26U)
3869#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
3870#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
3871#define CAN_F8R1_FB27_Pos (27U)
3872#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
3873#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
3874#define CAN_F8R1_FB28_Pos (28U)
3875#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
3876#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
3877#define CAN_F8R1_FB29_Pos (29U)
3878#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
3879#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
3880#define CAN_F8R1_FB30_Pos (30U)
3881#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
3882#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
3883#define CAN_F8R1_FB31_Pos (31U)
3884#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
3885#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
3886
3887/******************* Bit definition for CAN_F9R1 register *******************/
3888#define CAN_F9R1_FB0_Pos (0U)
3889#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
3890#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
3891#define CAN_F9R1_FB1_Pos (1U)
3892#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
3893#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
3894#define CAN_F9R1_FB2_Pos (2U)
3895#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
3896#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
3897#define CAN_F9R1_FB3_Pos (3U)
3898#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
3899#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
3900#define CAN_F9R1_FB4_Pos (4U)
3901#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
3902#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
3903#define CAN_F9R1_FB5_Pos (5U)
3904#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
3905#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
3906#define CAN_F9R1_FB6_Pos (6U)
3907#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
3908#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
3909#define CAN_F9R1_FB7_Pos (7U)
3910#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
3911#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
3912#define CAN_F9R1_FB8_Pos (8U)
3913#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
3914#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
3915#define CAN_F9R1_FB9_Pos (9U)
3916#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
3917#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
3918#define CAN_F9R1_FB10_Pos (10U)
3919#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
3920#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
3921#define CAN_F9R1_FB11_Pos (11U)
3922#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
3923#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
3924#define CAN_F9R1_FB12_Pos (12U)
3925#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
3926#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
3927#define CAN_F9R1_FB13_Pos (13U)
3928#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
3929#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
3930#define CAN_F9R1_FB14_Pos (14U)
3931#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
3932#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
3933#define CAN_F9R1_FB15_Pos (15U)
3934#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
3935#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
3936#define CAN_F9R1_FB16_Pos (16U)
3937#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
3938#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
3939#define CAN_F9R1_FB17_Pos (17U)
3940#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
3941#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
3942#define CAN_F9R1_FB18_Pos (18U)
3943#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
3944#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
3945#define CAN_F9R1_FB19_Pos (19U)
3946#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
3947#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
3948#define CAN_F9R1_FB20_Pos (20U)
3949#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
3950#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
3951#define CAN_F9R1_FB21_Pos (21U)
3952#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
3953#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
3954#define CAN_F9R1_FB22_Pos (22U)
3955#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
3956#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
3957#define CAN_F9R1_FB23_Pos (23U)
3958#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
3959#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
3960#define CAN_F9R1_FB24_Pos (24U)
3961#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
3962#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
3963#define CAN_F9R1_FB25_Pos (25U)
3964#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
3965#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
3966#define CAN_F9R1_FB26_Pos (26U)
3967#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
3968#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
3969#define CAN_F9R1_FB27_Pos (27U)
3970#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
3971#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
3972#define CAN_F9R1_FB28_Pos (28U)
3973#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
3974#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
3975#define CAN_F9R1_FB29_Pos (29U)
3976#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
3977#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
3978#define CAN_F9R1_FB30_Pos (30U)
3979#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
3980#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
3981#define CAN_F9R1_FB31_Pos (31U)
3982#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
3983#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
3984
3985/******************* Bit definition for CAN_F10R1 register ******************/
3986#define CAN_F10R1_FB0_Pos (0U)
3987#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
3988#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
3989#define CAN_F10R1_FB1_Pos (1U)
3990#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
3991#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
3992#define CAN_F10R1_FB2_Pos (2U)
3993#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
3994#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
3995#define CAN_F10R1_FB3_Pos (3U)
3996#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
3997#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
3998#define CAN_F10R1_FB4_Pos (4U)
3999#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
4000#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
4001#define CAN_F10R1_FB5_Pos (5U)
4002#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
4003#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
4004#define CAN_F10R1_FB6_Pos (6U)
4005#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
4006#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
4007#define CAN_F10R1_FB7_Pos (7U)
4008#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
4009#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
4010#define CAN_F10R1_FB8_Pos (8U)
4011#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
4012#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
4013#define CAN_F10R1_FB9_Pos (9U)
4014#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
4015#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
4016#define CAN_F10R1_FB10_Pos (10U)
4017#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
4018#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
4019#define CAN_F10R1_FB11_Pos (11U)
4020#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
4021#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
4022#define CAN_F10R1_FB12_Pos (12U)
4023#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
4024#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
4025#define CAN_F10R1_FB13_Pos (13U)
4026#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
4027#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
4028#define CAN_F10R1_FB14_Pos (14U)
4029#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
4030#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
4031#define CAN_F10R1_FB15_Pos (15U)
4032#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
4033#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
4034#define CAN_F10R1_FB16_Pos (16U)
4035#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
4036#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
4037#define CAN_F10R1_FB17_Pos (17U)
4038#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
4039#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
4040#define CAN_F10R1_FB18_Pos (18U)
4041#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
4042#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
4043#define CAN_F10R1_FB19_Pos (19U)
4044#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
4045#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
4046#define CAN_F10R1_FB20_Pos (20U)
4047#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
4048#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
4049#define CAN_F10R1_FB21_Pos (21U)
4050#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
4051#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
4052#define CAN_F10R1_FB22_Pos (22U)
4053#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
4054#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
4055#define CAN_F10R1_FB23_Pos (23U)
4056#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
4057#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
4058#define CAN_F10R1_FB24_Pos (24U)
4059#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
4060#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
4061#define CAN_F10R1_FB25_Pos (25U)
4062#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
4063#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
4064#define CAN_F10R1_FB26_Pos (26U)
4065#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
4066#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
4067#define CAN_F10R1_FB27_Pos (27U)
4068#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
4069#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
4070#define CAN_F10R1_FB28_Pos (28U)
4071#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
4072#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
4073#define CAN_F10R1_FB29_Pos (29U)
4074#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
4075#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
4076#define CAN_F10R1_FB30_Pos (30U)
4077#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
4078#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
4079#define CAN_F10R1_FB31_Pos (31U)
4080#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
4081#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
4082
4083/******************* Bit definition for CAN_F11R1 register ******************/
4084#define CAN_F11R1_FB0_Pos (0U)
4085#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
4086#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
4087#define CAN_F11R1_FB1_Pos (1U)
4088#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
4089#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
4090#define CAN_F11R1_FB2_Pos (2U)
4091#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
4092#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
4093#define CAN_F11R1_FB3_Pos (3U)
4094#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
4095#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
4096#define CAN_F11R1_FB4_Pos (4U)
4097#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
4098#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
4099#define CAN_F11R1_FB5_Pos (5U)
4100#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
4101#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
4102#define CAN_F11R1_FB6_Pos (6U)
4103#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
4104#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
4105#define CAN_F11R1_FB7_Pos (7U)
4106#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
4107#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
4108#define CAN_F11R1_FB8_Pos (8U)
4109#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
4110#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
4111#define CAN_F11R1_FB9_Pos (9U)
4112#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
4113#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
4114#define CAN_F11R1_FB10_Pos (10U)
4115#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
4116#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
4117#define CAN_F11R1_FB11_Pos (11U)
4118#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
4119#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
4120#define CAN_F11R1_FB12_Pos (12U)
4121#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
4122#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
4123#define CAN_F11R1_FB13_Pos (13U)
4124#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
4125#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
4126#define CAN_F11R1_FB14_Pos (14U)
4127#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
4128#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
4129#define CAN_F11R1_FB15_Pos (15U)
4130#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
4131#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
4132#define CAN_F11R1_FB16_Pos (16U)
4133#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
4134#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
4135#define CAN_F11R1_FB17_Pos (17U)
4136#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
4137#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
4138#define CAN_F11R1_FB18_Pos (18U)
4139#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
4140#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
4141#define CAN_F11R1_FB19_Pos (19U)
4142#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
4143#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
4144#define CAN_F11R1_FB20_Pos (20U)
4145#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
4146#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
4147#define CAN_F11R1_FB21_Pos (21U)
4148#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
4149#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
4150#define CAN_F11R1_FB22_Pos (22U)
4151#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
4152#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
4153#define CAN_F11R1_FB23_Pos (23U)
4154#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
4155#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
4156#define CAN_F11R1_FB24_Pos (24U)
4157#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
4158#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
4159#define CAN_F11R1_FB25_Pos (25U)
4160#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
4161#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
4162#define CAN_F11R1_FB26_Pos (26U)
4163#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
4164#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
4165#define CAN_F11R1_FB27_Pos (27U)
4166#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
4167#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
4168#define CAN_F11R1_FB28_Pos (28U)
4169#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
4170#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
4171#define CAN_F11R1_FB29_Pos (29U)
4172#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
4173#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
4174#define CAN_F11R1_FB30_Pos (30U)
4175#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
4176#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
4177#define CAN_F11R1_FB31_Pos (31U)
4178#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
4179#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
4180
4181/******************* Bit definition for CAN_F12R1 register ******************/
4182#define CAN_F12R1_FB0_Pos (0U)
4183#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
4184#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
4185#define CAN_F12R1_FB1_Pos (1U)
4186#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
4187#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
4188#define CAN_F12R1_FB2_Pos (2U)
4189#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
4190#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
4191#define CAN_F12R1_FB3_Pos (3U)
4192#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
4193#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
4194#define CAN_F12R1_FB4_Pos (4U)
4195#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
4196#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
4197#define CAN_F12R1_FB5_Pos (5U)
4198#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
4199#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
4200#define CAN_F12R1_FB6_Pos (6U)
4201#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
4202#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
4203#define CAN_F12R1_FB7_Pos (7U)
4204#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
4205#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
4206#define CAN_F12R1_FB8_Pos (8U)
4207#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
4208#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
4209#define CAN_F12R1_FB9_Pos (9U)
4210#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
4211#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
4212#define CAN_F12R1_FB10_Pos (10U)
4213#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
4214#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
4215#define CAN_F12R1_FB11_Pos (11U)
4216#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
4217#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
4218#define CAN_F12R1_FB12_Pos (12U)
4219#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
4220#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
4221#define CAN_F12R1_FB13_Pos (13U)
4222#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
4223#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
4224#define CAN_F12R1_FB14_Pos (14U)
4225#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
4226#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
4227#define CAN_F12R1_FB15_Pos (15U)
4228#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
4229#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
4230#define CAN_F12R1_FB16_Pos (16U)
4231#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
4232#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
4233#define CAN_F12R1_FB17_Pos (17U)
4234#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
4235#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
4236#define CAN_F12R1_FB18_Pos (18U)
4237#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
4238#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
4239#define CAN_F12R1_FB19_Pos (19U)
4240#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
4241#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
4242#define CAN_F12R1_FB20_Pos (20U)
4243#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
4244#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
4245#define CAN_F12R1_FB21_Pos (21U)
4246#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
4247#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
4248#define CAN_F12R1_FB22_Pos (22U)
4249#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
4250#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
4251#define CAN_F12R1_FB23_Pos (23U)
4252#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
4253#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
4254#define CAN_F12R1_FB24_Pos (24U)
4255#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
4256#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
4257#define CAN_F12R1_FB25_Pos (25U)
4258#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
4259#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
4260#define CAN_F12R1_FB26_Pos (26U)
4261#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
4262#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
4263#define CAN_F12R1_FB27_Pos (27U)
4264#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
4265#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
4266#define CAN_F12R1_FB28_Pos (28U)
4267#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
4268#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
4269#define CAN_F12R1_FB29_Pos (29U)
4270#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
4271#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
4272#define CAN_F12R1_FB30_Pos (30U)
4273#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
4274#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
4275#define CAN_F12R1_FB31_Pos (31U)
4276#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
4277#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
4278
4279/******************* Bit definition for CAN_F13R1 register ******************/
4280#define CAN_F13R1_FB0_Pos (0U)
4281#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
4282#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
4283#define CAN_F13R1_FB1_Pos (1U)
4284#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
4285#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
4286#define CAN_F13R1_FB2_Pos (2U)
4287#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
4288#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
4289#define CAN_F13R1_FB3_Pos (3U)
4290#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
4291#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
4292#define CAN_F13R1_FB4_Pos (4U)
4293#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
4294#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
4295#define CAN_F13R1_FB5_Pos (5U)
4296#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
4297#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
4298#define CAN_F13R1_FB6_Pos (6U)
4299#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
4300#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
4301#define CAN_F13R1_FB7_Pos (7U)
4302#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
4303#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
4304#define CAN_F13R1_FB8_Pos (8U)
4305#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
4306#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
4307#define CAN_F13R1_FB9_Pos (9U)
4308#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
4309#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
4310#define CAN_F13R1_FB10_Pos (10U)
4311#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
4312#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
4313#define CAN_F13R1_FB11_Pos (11U)
4314#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
4315#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
4316#define CAN_F13R1_FB12_Pos (12U)
4317#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
4318#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
4319#define CAN_F13R1_FB13_Pos (13U)
4320#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
4321#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
4322#define CAN_F13R1_FB14_Pos (14U)
4323#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
4324#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
4325#define CAN_F13R1_FB15_Pos (15U)
4326#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
4327#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
4328#define CAN_F13R1_FB16_Pos (16U)
4329#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
4330#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
4331#define CAN_F13R1_FB17_Pos (17U)
4332#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
4333#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
4334#define CAN_F13R1_FB18_Pos (18U)
4335#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
4336#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
4337#define CAN_F13R1_FB19_Pos (19U)
4338#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
4339#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
4340#define CAN_F13R1_FB20_Pos (20U)
4341#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
4342#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
4343#define CAN_F13R1_FB21_Pos (21U)
4344#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
4345#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
4346#define CAN_F13R1_FB22_Pos (22U)
4347#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
4348#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
4349#define CAN_F13R1_FB23_Pos (23U)
4350#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
4351#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
4352#define CAN_F13R1_FB24_Pos (24U)
4353#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
4354#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
4355#define CAN_F13R1_FB25_Pos (25U)
4356#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
4357#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
4358#define CAN_F13R1_FB26_Pos (26U)
4359#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
4360#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
4361#define CAN_F13R1_FB27_Pos (27U)
4362#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
4363#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
4364#define CAN_F13R1_FB28_Pos (28U)
4365#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
4366#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
4367#define CAN_F13R1_FB29_Pos (29U)
4368#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
4369#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
4370#define CAN_F13R1_FB30_Pos (30U)
4371#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
4372#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
4373#define CAN_F13R1_FB31_Pos (31U)
4374#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
4375#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
4376
4377/******************* Bit definition for CAN_F0R2 register *******************/
4378#define CAN_F0R2_FB0_Pos (0U)
4379#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
4380#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
4381#define CAN_F0R2_FB1_Pos (1U)
4382#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
4383#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
4384#define CAN_F0R2_FB2_Pos (2U)
4385#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
4386#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
4387#define CAN_F0R2_FB3_Pos (3U)
4388#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
4389#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
4390#define CAN_F0R2_FB4_Pos (4U)
4391#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
4392#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
4393#define CAN_F0R2_FB5_Pos (5U)
4394#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
4395#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
4396#define CAN_F0R2_FB6_Pos (6U)
4397#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
4398#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
4399#define CAN_F0R2_FB7_Pos (7U)
4400#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
4401#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
4402#define CAN_F0R2_FB8_Pos (8U)
4403#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
4404#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
4405#define CAN_F0R2_FB9_Pos (9U)
4406#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
4407#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
4408#define CAN_F0R2_FB10_Pos (10U)
4409#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
4410#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
4411#define CAN_F0R2_FB11_Pos (11U)
4412#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
4413#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
4414#define CAN_F0R2_FB12_Pos (12U)
4415#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
4416#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
4417#define CAN_F0R2_FB13_Pos (13U)
4418#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
4419#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
4420#define CAN_F0R2_FB14_Pos (14U)
4421#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
4422#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
4423#define CAN_F0R2_FB15_Pos (15U)
4424#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
4425#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
4426#define CAN_F0R2_FB16_Pos (16U)
4427#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
4428#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
4429#define CAN_F0R2_FB17_Pos (17U)
4430#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
4431#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
4432#define CAN_F0R2_FB18_Pos (18U)
4433#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
4434#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
4435#define CAN_F0R2_FB19_Pos (19U)
4436#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
4437#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
4438#define CAN_F0R2_FB20_Pos (20U)
4439#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
4440#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
4441#define CAN_F0R2_FB21_Pos (21U)
4442#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
4443#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
4444#define CAN_F0R2_FB22_Pos (22U)
4445#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
4446#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
4447#define CAN_F0R2_FB23_Pos (23U)
4448#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
4449#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
4450#define CAN_F0R2_FB24_Pos (24U)
4451#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
4452#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
4453#define CAN_F0R2_FB25_Pos (25U)
4454#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
4455#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
4456#define CAN_F0R2_FB26_Pos (26U)
4457#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
4458#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
4459#define CAN_F0R2_FB27_Pos (27U)
4460#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
4461#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
4462#define CAN_F0R2_FB28_Pos (28U)
4463#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
4464#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
4465#define CAN_F0R2_FB29_Pos (29U)
4466#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
4467#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
4468#define CAN_F0R2_FB30_Pos (30U)
4469#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
4470#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
4471#define CAN_F0R2_FB31_Pos (31U)
4472#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
4473#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
4474
4475/******************* Bit definition for CAN_F1R2 register *******************/
4476#define CAN_F1R2_FB0_Pos (0U)
4477#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
4478#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
4479#define CAN_F1R2_FB1_Pos (1U)
4480#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
4481#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
4482#define CAN_F1R2_FB2_Pos (2U)
4483#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
4484#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
4485#define CAN_F1R2_FB3_Pos (3U)
4486#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
4487#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
4488#define CAN_F1R2_FB4_Pos (4U)
4489#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
4490#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
4491#define CAN_F1R2_FB5_Pos (5U)
4492#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
4493#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
4494#define CAN_F1R2_FB6_Pos (6U)
4495#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
4496#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
4497#define CAN_F1R2_FB7_Pos (7U)
4498#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
4499#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
4500#define CAN_F1R2_FB8_Pos (8U)
4501#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
4502#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
4503#define CAN_F1R2_FB9_Pos (9U)
4504#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
4505#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
4506#define CAN_F1R2_FB10_Pos (10U)
4507#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
4508#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
4509#define CAN_F1R2_FB11_Pos (11U)
4510#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
4511#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
4512#define CAN_F1R2_FB12_Pos (12U)
4513#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
4514#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
4515#define CAN_F1R2_FB13_Pos (13U)
4516#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
4517#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
4518#define CAN_F1R2_FB14_Pos (14U)
4519#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
4520#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
4521#define CAN_F1R2_FB15_Pos (15U)
4522#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
4523#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
4524#define CAN_F1R2_FB16_Pos (16U)
4525#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
4526#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
4527#define CAN_F1R2_FB17_Pos (17U)
4528#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
4529#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
4530#define CAN_F1R2_FB18_Pos (18U)
4531#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
4532#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
4533#define CAN_F1R2_FB19_Pos (19U)
4534#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
4535#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
4536#define CAN_F1R2_FB20_Pos (20U)
4537#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
4538#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
4539#define CAN_F1R2_FB21_Pos (21U)
4540#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
4541#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
4542#define CAN_F1R2_FB22_Pos (22U)
4543#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
4544#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
4545#define CAN_F1R2_FB23_Pos (23U)
4546#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
4547#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
4548#define CAN_F1R2_FB24_Pos (24U)
4549#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
4550#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
4551#define CAN_F1R2_FB25_Pos (25U)
4552#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
4553#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
4554#define CAN_F1R2_FB26_Pos (26U)
4555#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
4556#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
4557#define CAN_F1R2_FB27_Pos (27U)
4558#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
4559#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
4560#define CAN_F1R2_FB28_Pos (28U)
4561#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
4562#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
4563#define CAN_F1R2_FB29_Pos (29U)
4564#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
4565#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
4566#define CAN_F1R2_FB30_Pos (30U)
4567#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
4568#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
4569#define CAN_F1R2_FB31_Pos (31U)
4570#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
4571#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
4572
4573/******************* Bit definition for CAN_F2R2 register *******************/
4574#define CAN_F2R2_FB0_Pos (0U)
4575#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
4576#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
4577#define CAN_F2R2_FB1_Pos (1U)
4578#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
4579#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
4580#define CAN_F2R2_FB2_Pos (2U)
4581#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
4582#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
4583#define CAN_F2R2_FB3_Pos (3U)
4584#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
4585#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
4586#define CAN_F2R2_FB4_Pos (4U)
4587#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
4588#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
4589#define CAN_F2R2_FB5_Pos (5U)
4590#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
4591#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
4592#define CAN_F2R2_FB6_Pos (6U)
4593#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
4594#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
4595#define CAN_F2R2_FB7_Pos (7U)
4596#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
4597#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
4598#define CAN_F2R2_FB8_Pos (8U)
4599#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
4600#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
4601#define CAN_F2R2_FB9_Pos (9U)
4602#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
4603#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
4604#define CAN_F2R2_FB10_Pos (10U)
4605#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
4606#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
4607#define CAN_F2R2_FB11_Pos (11U)
4608#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
4609#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
4610#define CAN_F2R2_FB12_Pos (12U)
4611#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
4612#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
4613#define CAN_F2R2_FB13_Pos (13U)
4614#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
4615#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
4616#define CAN_F2R2_FB14_Pos (14U)
4617#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
4618#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
4619#define CAN_F2R2_FB15_Pos (15U)
4620#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
4621#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
4622#define CAN_F2R2_FB16_Pos (16U)
4623#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
4624#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
4625#define CAN_F2R2_FB17_Pos (17U)
4626#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
4627#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
4628#define CAN_F2R2_FB18_Pos (18U)
4629#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
4630#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
4631#define CAN_F2R2_FB19_Pos (19U)
4632#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
4633#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
4634#define CAN_F2R2_FB20_Pos (20U)
4635#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
4636#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
4637#define CAN_F2R2_FB21_Pos (21U)
4638#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
4639#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
4640#define CAN_F2R2_FB22_Pos (22U)
4641#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
4642#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
4643#define CAN_F2R2_FB23_Pos (23U)
4644#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
4645#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
4646#define CAN_F2R2_FB24_Pos (24U)
4647#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
4648#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
4649#define CAN_F2R2_FB25_Pos (25U)
4650#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
4651#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
4652#define CAN_F2R2_FB26_Pos (26U)
4653#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
4654#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
4655#define CAN_F2R2_FB27_Pos (27U)
4656#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
4657#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
4658#define CAN_F2R2_FB28_Pos (28U)
4659#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
4660#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
4661#define CAN_F2R2_FB29_Pos (29U)
4662#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
4663#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
4664#define CAN_F2R2_FB30_Pos (30U)
4665#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
4666#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
4667#define CAN_F2R2_FB31_Pos (31U)
4668#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
4669#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
4670
4671/******************* Bit definition for CAN_F3R2 register *******************/
4672#define CAN_F3R2_FB0_Pos (0U)
4673#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
4674#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
4675#define CAN_F3R2_FB1_Pos (1U)
4676#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
4677#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
4678#define CAN_F3R2_FB2_Pos (2U)
4679#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
4680#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
4681#define CAN_F3R2_FB3_Pos (3U)
4682#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
4683#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
4684#define CAN_F3R2_FB4_Pos (4U)
4685#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
4686#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
4687#define CAN_F3R2_FB5_Pos (5U)
4688#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
4689#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
4690#define CAN_F3R2_FB6_Pos (6U)
4691#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
4692#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
4693#define CAN_F3R2_FB7_Pos (7U)
4694#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
4695#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
4696#define CAN_F3R2_FB8_Pos (8U)
4697#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
4698#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
4699#define CAN_F3R2_FB9_Pos (9U)
4700#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
4701#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
4702#define CAN_F3R2_FB10_Pos (10U)
4703#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
4704#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
4705#define CAN_F3R2_FB11_Pos (11U)
4706#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
4707#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
4708#define CAN_F3R2_FB12_Pos (12U)
4709#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
4710#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
4711#define CAN_F3R2_FB13_Pos (13U)
4712#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
4713#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
4714#define CAN_F3R2_FB14_Pos (14U)
4715#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
4716#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
4717#define CAN_F3R2_FB15_Pos (15U)
4718#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
4719#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
4720#define CAN_F3R2_FB16_Pos (16U)
4721#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
4722#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
4723#define CAN_F3R2_FB17_Pos (17U)
4724#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
4725#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
4726#define CAN_F3R2_FB18_Pos (18U)
4727#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
4728#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
4729#define CAN_F3R2_FB19_Pos (19U)
4730#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
4731#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
4732#define CAN_F3R2_FB20_Pos (20U)
4733#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
4734#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
4735#define CAN_F3R2_FB21_Pos (21U)
4736#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
4737#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
4738#define CAN_F3R2_FB22_Pos (22U)
4739#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
4740#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
4741#define CAN_F3R2_FB23_Pos (23U)
4742#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
4743#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
4744#define CAN_F3R2_FB24_Pos (24U)
4745#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
4746#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
4747#define CAN_F3R2_FB25_Pos (25U)
4748#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
4749#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
4750#define CAN_F3R2_FB26_Pos (26U)
4751#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
4752#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
4753#define CAN_F3R2_FB27_Pos (27U)
4754#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
4755#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
4756#define CAN_F3R2_FB28_Pos (28U)
4757#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
4758#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
4759#define CAN_F3R2_FB29_Pos (29U)
4760#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
4761#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
4762#define CAN_F3R2_FB30_Pos (30U)
4763#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
4764#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
4765#define CAN_F3R2_FB31_Pos (31U)
4766#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
4767#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
4768
4769/******************* Bit definition for CAN_F4R2 register *******************/
4770#define CAN_F4R2_FB0_Pos (0U)
4771#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
4772#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
4773#define CAN_F4R2_FB1_Pos (1U)
4774#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
4775#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
4776#define CAN_F4R2_FB2_Pos (2U)
4777#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
4778#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
4779#define CAN_F4R2_FB3_Pos (3U)
4780#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
4781#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
4782#define CAN_F4R2_FB4_Pos (4U)
4783#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
4784#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
4785#define CAN_F4R2_FB5_Pos (5U)
4786#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
4787#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
4788#define CAN_F4R2_FB6_Pos (6U)
4789#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
4790#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
4791#define CAN_F4R2_FB7_Pos (7U)
4792#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
4793#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
4794#define CAN_F4R2_FB8_Pos (8U)
4795#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
4796#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
4797#define CAN_F4R2_FB9_Pos (9U)
4798#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
4799#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
4800#define CAN_F4R2_FB10_Pos (10U)
4801#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
4802#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
4803#define CAN_F4R2_FB11_Pos (11U)
4804#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
4805#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
4806#define CAN_F4R2_FB12_Pos (12U)
4807#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
4808#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
4809#define CAN_F4R2_FB13_Pos (13U)
4810#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
4811#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
4812#define CAN_F4R2_FB14_Pos (14U)
4813#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
4814#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
4815#define CAN_F4R2_FB15_Pos (15U)
4816#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
4817#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
4818#define CAN_F4R2_FB16_Pos (16U)
4819#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
4820#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
4821#define CAN_F4R2_FB17_Pos (17U)
4822#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
4823#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
4824#define CAN_F4R2_FB18_Pos (18U)
4825#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
4826#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
4827#define CAN_F4R2_FB19_Pos (19U)
4828#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
4829#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
4830#define CAN_F4R2_FB20_Pos (20U)
4831#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
4832#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
4833#define CAN_F4R2_FB21_Pos (21U)
4834#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
4835#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
4836#define CAN_F4R2_FB22_Pos (22U)
4837#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
4838#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
4839#define CAN_F4R2_FB23_Pos (23U)
4840#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
4841#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
4842#define CAN_F4R2_FB24_Pos (24U)
4843#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
4844#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
4845#define CAN_F4R2_FB25_Pos (25U)
4846#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
4847#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
4848#define CAN_F4R2_FB26_Pos (26U)
4849#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
4850#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
4851#define CAN_F4R2_FB27_Pos (27U)
4852#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
4853#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
4854#define CAN_F4R2_FB28_Pos (28U)
4855#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
4856#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
4857#define CAN_F4R2_FB29_Pos (29U)
4858#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
4859#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
4860#define CAN_F4R2_FB30_Pos (30U)
4861#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
4862#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
4863#define CAN_F4R2_FB31_Pos (31U)
4864#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
4865#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
4866
4867/******************* Bit definition for CAN_F5R2 register *******************/
4868#define CAN_F5R2_FB0_Pos (0U)
4869#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
4870#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
4871#define CAN_F5R2_FB1_Pos (1U)
4872#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
4873#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
4874#define CAN_F5R2_FB2_Pos (2U)
4875#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
4876#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
4877#define CAN_F5R2_FB3_Pos (3U)
4878#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
4879#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
4880#define CAN_F5R2_FB4_Pos (4U)
4881#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
4882#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
4883#define CAN_F5R2_FB5_Pos (5U)
4884#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
4885#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
4886#define CAN_F5R2_FB6_Pos (6U)
4887#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
4888#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
4889#define CAN_F5R2_FB7_Pos (7U)
4890#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
4891#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
4892#define CAN_F5R2_FB8_Pos (8U)
4893#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
4894#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
4895#define CAN_F5R2_FB9_Pos (9U)
4896#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
4897#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
4898#define CAN_F5R2_FB10_Pos (10U)
4899#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
4900#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
4901#define CAN_F5R2_FB11_Pos (11U)
4902#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
4903#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
4904#define CAN_F5R2_FB12_Pos (12U)
4905#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
4906#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
4907#define CAN_F5R2_FB13_Pos (13U)
4908#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
4909#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
4910#define CAN_F5R2_FB14_Pos (14U)
4911#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
4912#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
4913#define CAN_F5R2_FB15_Pos (15U)
4914#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
4915#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
4916#define CAN_F5R2_FB16_Pos (16U)
4917#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
4918#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
4919#define CAN_F5R2_FB17_Pos (17U)
4920#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
4921#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
4922#define CAN_F5R2_FB18_Pos (18U)
4923#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
4924#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
4925#define CAN_F5R2_FB19_Pos (19U)
4926#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
4927#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
4928#define CAN_F5R2_FB20_Pos (20U)
4929#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
4930#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
4931#define CAN_F5R2_FB21_Pos (21U)
4932#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
4933#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
4934#define CAN_F5R2_FB22_Pos (22U)
4935#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
4936#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
4937#define CAN_F5R2_FB23_Pos (23U)
4938#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
4939#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
4940#define CAN_F5R2_FB24_Pos (24U)
4941#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
4942#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
4943#define CAN_F5R2_FB25_Pos (25U)
4944#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
4945#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
4946#define CAN_F5R2_FB26_Pos (26U)
4947#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
4948#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
4949#define CAN_F5R2_FB27_Pos (27U)
4950#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
4951#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
4952#define CAN_F5R2_FB28_Pos (28U)
4953#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
4954#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
4955#define CAN_F5R2_FB29_Pos (29U)
4956#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
4957#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
4958#define CAN_F5R2_FB30_Pos (30U)
4959#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
4960#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
4961#define CAN_F5R2_FB31_Pos (31U)
4962#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
4963#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
4964
4965/******************* Bit definition for CAN_F6R2 register *******************/
4966#define CAN_F6R2_FB0_Pos (0U)
4967#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
4968#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
4969#define CAN_F6R2_FB1_Pos (1U)
4970#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
4971#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
4972#define CAN_F6R2_FB2_Pos (2U)
4973#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
4974#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
4975#define CAN_F6R2_FB3_Pos (3U)
4976#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
4977#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
4978#define CAN_F6R2_FB4_Pos (4U)
4979#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
4980#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
4981#define CAN_F6R2_FB5_Pos (5U)
4982#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
4983#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
4984#define CAN_F6R2_FB6_Pos (6U)
4985#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
4986#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
4987#define CAN_F6R2_FB7_Pos (7U)
4988#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
4989#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
4990#define CAN_F6R2_FB8_Pos (8U)
4991#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
4992#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
4993#define CAN_F6R2_FB9_Pos (9U)
4994#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
4995#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
4996#define CAN_F6R2_FB10_Pos (10U)
4997#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
4998#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
4999#define CAN_F6R2_FB11_Pos (11U)
5000#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
5001#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
5002#define CAN_F6R2_FB12_Pos (12U)
5003#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
5004#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
5005#define CAN_F6R2_FB13_Pos (13U)
5006#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
5007#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
5008#define CAN_F6R2_FB14_Pos (14U)
5009#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
5010#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
5011#define CAN_F6R2_FB15_Pos (15U)
5012#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
5013#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
5014#define CAN_F6R2_FB16_Pos (16U)
5015#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
5016#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
5017#define CAN_F6R2_FB17_Pos (17U)
5018#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
5019#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
5020#define CAN_F6R2_FB18_Pos (18U)
5021#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
5022#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
5023#define CAN_F6R2_FB19_Pos (19U)
5024#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
5025#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
5026#define CAN_F6R2_FB20_Pos (20U)
5027#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
5028#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
5029#define CAN_F6R2_FB21_Pos (21U)
5030#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
5031#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
5032#define CAN_F6R2_FB22_Pos (22U)
5033#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
5034#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
5035#define CAN_F6R2_FB23_Pos (23U)
5036#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
5037#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
5038#define CAN_F6R2_FB24_Pos (24U)
5039#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
5040#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
5041#define CAN_F6R2_FB25_Pos (25U)
5042#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
5043#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
5044#define CAN_F6R2_FB26_Pos (26U)
5045#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
5046#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
5047#define CAN_F6R2_FB27_Pos (27U)
5048#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
5049#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
5050#define CAN_F6R2_FB28_Pos (28U)
5051#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
5052#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
5053#define CAN_F6R2_FB29_Pos (29U)
5054#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
5055#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
5056#define CAN_F6R2_FB30_Pos (30U)
5057#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
5058#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
5059#define CAN_F6R2_FB31_Pos (31U)
5060#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
5061#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
5062
5063/******************* Bit definition for CAN_F7R2 register *******************/
5064#define CAN_F7R2_FB0_Pos (0U)
5065#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
5066#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
5067#define CAN_F7R2_FB1_Pos (1U)
5068#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
5069#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
5070#define CAN_F7R2_FB2_Pos (2U)
5071#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
5072#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
5073#define CAN_F7R2_FB3_Pos (3U)
5074#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
5075#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
5076#define CAN_F7R2_FB4_Pos (4U)
5077#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
5078#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
5079#define CAN_F7R2_FB5_Pos (5U)
5080#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
5081#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
5082#define CAN_F7R2_FB6_Pos (6U)
5083#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
5084#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
5085#define CAN_F7R2_FB7_Pos (7U)
5086#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
5087#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
5088#define CAN_F7R2_FB8_Pos (8U)
5089#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
5090#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
5091#define CAN_F7R2_FB9_Pos (9U)
5092#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
5093#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
5094#define CAN_F7R2_FB10_Pos (10U)
5095#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
5096#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
5097#define CAN_F7R2_FB11_Pos (11U)
5098#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
5099#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
5100#define CAN_F7R2_FB12_Pos (12U)
5101#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
5102#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
5103#define CAN_F7R2_FB13_Pos (13U)
5104#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
5105#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
5106#define CAN_F7R2_FB14_Pos (14U)
5107#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
5108#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
5109#define CAN_F7R2_FB15_Pos (15U)
5110#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
5111#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
5112#define CAN_F7R2_FB16_Pos (16U)
5113#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
5114#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
5115#define CAN_F7R2_FB17_Pos (17U)
5116#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
5117#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
5118#define CAN_F7R2_FB18_Pos (18U)
5119#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
5120#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
5121#define CAN_F7R2_FB19_Pos (19U)
5122#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
5123#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
5124#define CAN_F7R2_FB20_Pos (20U)
5125#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
5126#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
5127#define CAN_F7R2_FB21_Pos (21U)
5128#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
5129#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
5130#define CAN_F7R2_FB22_Pos (22U)
5131#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
5132#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
5133#define CAN_F7R2_FB23_Pos (23U)
5134#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
5135#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
5136#define CAN_F7R2_FB24_Pos (24U)
5137#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
5138#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
5139#define CAN_F7R2_FB25_Pos (25U)
5140#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
5141#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
5142#define CAN_F7R2_FB26_Pos (26U)
5143#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
5144#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
5145#define CAN_F7R2_FB27_Pos (27U)
5146#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
5147#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
5148#define CAN_F7R2_FB28_Pos (28U)
5149#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
5150#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
5151#define CAN_F7R2_FB29_Pos (29U)
5152#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
5153#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
5154#define CAN_F7R2_FB30_Pos (30U)
5155#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
5156#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
5157#define CAN_F7R2_FB31_Pos (31U)
5158#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
5159#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
5160
5161/******************* Bit definition for CAN_F8R2 register *******************/
5162#define CAN_F8R2_FB0_Pos (0U)
5163#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
5164#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
5165#define CAN_F8R2_FB1_Pos (1U)
5166#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
5167#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
5168#define CAN_F8R2_FB2_Pos (2U)
5169#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
5170#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
5171#define CAN_F8R2_FB3_Pos (3U)
5172#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
5173#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
5174#define CAN_F8R2_FB4_Pos (4U)
5175#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
5176#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
5177#define CAN_F8R2_FB5_Pos (5U)
5178#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
5179#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
5180#define CAN_F8R2_FB6_Pos (6U)
5181#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
5182#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
5183#define CAN_F8R2_FB7_Pos (7U)
5184#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
5185#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
5186#define CAN_F8R2_FB8_Pos (8U)
5187#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
5188#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
5189#define CAN_F8R2_FB9_Pos (9U)
5190#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
5191#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
5192#define CAN_F8R2_FB10_Pos (10U)
5193#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
5194#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
5195#define CAN_F8R2_FB11_Pos (11U)
5196#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
5197#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
5198#define CAN_F8R2_FB12_Pos (12U)
5199#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
5200#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
5201#define CAN_F8R2_FB13_Pos (13U)
5202#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
5203#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
5204#define CAN_F8R2_FB14_Pos (14U)
5205#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
5206#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
5207#define CAN_F8R2_FB15_Pos (15U)
5208#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
5209#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
5210#define CAN_F8R2_FB16_Pos (16U)
5211#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
5212#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
5213#define CAN_F8R2_FB17_Pos (17U)
5214#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
5215#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
5216#define CAN_F8R2_FB18_Pos (18U)
5217#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
5218#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
5219#define CAN_F8R2_FB19_Pos (19U)
5220#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
5221#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
5222#define CAN_F8R2_FB20_Pos (20U)
5223#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
5224#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
5225#define CAN_F8R2_FB21_Pos (21U)
5226#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
5227#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
5228#define CAN_F8R2_FB22_Pos (22U)
5229#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
5230#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
5231#define CAN_F8R2_FB23_Pos (23U)
5232#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
5233#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
5234#define CAN_F8R2_FB24_Pos (24U)
5235#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
5236#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
5237#define CAN_F8R2_FB25_Pos (25U)
5238#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
5239#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
5240#define CAN_F8R2_FB26_Pos (26U)
5241#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
5242#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
5243#define CAN_F8R2_FB27_Pos (27U)
5244#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
5245#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
5246#define CAN_F8R2_FB28_Pos (28U)
5247#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
5248#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
5249#define CAN_F8R2_FB29_Pos (29U)
5250#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
5251#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
5252#define CAN_F8R2_FB30_Pos (30U)
5253#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
5254#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
5255#define CAN_F8R2_FB31_Pos (31U)
5256#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
5257#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
5258
5259/******************* Bit definition for CAN_F9R2 register *******************/
5260#define CAN_F9R2_FB0_Pos (0U)
5261#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
5262#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
5263#define CAN_F9R2_FB1_Pos (1U)
5264#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
5265#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
5266#define CAN_F9R2_FB2_Pos (2U)
5267#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
5268#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
5269#define CAN_F9R2_FB3_Pos (3U)
5270#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
5271#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
5272#define CAN_F9R2_FB4_Pos (4U)
5273#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
5274#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
5275#define CAN_F9R2_FB5_Pos (5U)
5276#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
5277#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
5278#define CAN_F9R2_FB6_Pos (6U)
5279#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
5280#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
5281#define CAN_F9R2_FB7_Pos (7U)
5282#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
5283#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
5284#define CAN_F9R2_FB8_Pos (8U)
5285#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
5286#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
5287#define CAN_F9R2_FB9_Pos (9U)
5288#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
5289#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
5290#define CAN_F9R2_FB10_Pos (10U)
5291#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
5292#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
5293#define CAN_F9R2_FB11_Pos (11U)
5294#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
5295#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
5296#define CAN_F9R2_FB12_Pos (12U)
5297#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
5298#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
5299#define CAN_F9R2_FB13_Pos (13U)
5300#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
5301#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
5302#define CAN_F9R2_FB14_Pos (14U)
5303#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
5304#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
5305#define CAN_F9R2_FB15_Pos (15U)
5306#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
5307#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
5308#define CAN_F9R2_FB16_Pos (16U)
5309#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
5310#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
5311#define CAN_F9R2_FB17_Pos (17U)
5312#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
5313#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
5314#define CAN_F9R2_FB18_Pos (18U)
5315#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
5316#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
5317#define CAN_F9R2_FB19_Pos (19U)
5318#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
5319#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
5320#define CAN_F9R2_FB20_Pos (20U)
5321#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
5322#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
5323#define CAN_F9R2_FB21_Pos (21U)
5324#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
5325#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
5326#define CAN_F9R2_FB22_Pos (22U)
5327#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
5328#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
5329#define CAN_F9R2_FB23_Pos (23U)
5330#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
5331#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
5332#define CAN_F9R2_FB24_Pos (24U)
5333#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
5334#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
5335#define CAN_F9R2_FB25_Pos (25U)
5336#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
5337#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
5338#define CAN_F9R2_FB26_Pos (26U)
5339#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
5340#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
5341#define CAN_F9R2_FB27_Pos (27U)
5342#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
5343#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
5344#define CAN_F9R2_FB28_Pos (28U)
5345#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
5346#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
5347#define CAN_F9R2_FB29_Pos (29U)
5348#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
5349#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
5350#define CAN_F9R2_FB30_Pos (30U)
5351#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
5352#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
5353#define CAN_F9R2_FB31_Pos (31U)
5354#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
5355#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
5356
5357/******************* Bit definition for CAN_F10R2 register ******************/
5358#define CAN_F10R2_FB0_Pos (0U)
5359#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
5360#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
5361#define CAN_F10R2_FB1_Pos (1U)
5362#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
5363#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
5364#define CAN_F10R2_FB2_Pos (2U)
5365#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
5366#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
5367#define CAN_F10R2_FB3_Pos (3U)
5368#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
5369#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
5370#define CAN_F10R2_FB4_Pos (4U)
5371#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
5372#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
5373#define CAN_F10R2_FB5_Pos (5U)
5374#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
5375#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
5376#define CAN_F10R2_FB6_Pos (6U)
5377#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
5378#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
5379#define CAN_F10R2_FB7_Pos (7U)
5380#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
5381#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
5382#define CAN_F10R2_FB8_Pos (8U)
5383#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
5384#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
5385#define CAN_F10R2_FB9_Pos (9U)
5386#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
5387#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
5388#define CAN_F10R2_FB10_Pos (10U)
5389#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
5390#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
5391#define CAN_F10R2_FB11_Pos (11U)
5392#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
5393#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
5394#define CAN_F10R2_FB12_Pos (12U)
5395#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
5396#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
5397#define CAN_F10R2_FB13_Pos (13U)
5398#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
5399#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
5400#define CAN_F10R2_FB14_Pos (14U)
5401#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
5402#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
5403#define CAN_F10R2_FB15_Pos (15U)
5404#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
5405#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
5406#define CAN_F10R2_FB16_Pos (16U)
5407#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
5408#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
5409#define CAN_F10R2_FB17_Pos (17U)
5410#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
5411#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
5412#define CAN_F10R2_FB18_Pos (18U)
5413#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
5414#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
5415#define CAN_F10R2_FB19_Pos (19U)
5416#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
5417#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
5418#define CAN_F10R2_FB20_Pos (20U)
5419#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
5420#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
5421#define CAN_F10R2_FB21_Pos (21U)
5422#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
5423#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
5424#define CAN_F10R2_FB22_Pos (22U)
5425#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
5426#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
5427#define CAN_F10R2_FB23_Pos (23U)
5428#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
5429#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
5430#define CAN_F10R2_FB24_Pos (24U)
5431#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
5432#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
5433#define CAN_F10R2_FB25_Pos (25U)
5434#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
5435#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
5436#define CAN_F10R2_FB26_Pos (26U)
5437#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
5438#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
5439#define CAN_F10R2_FB27_Pos (27U)
5440#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
5441#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
5442#define CAN_F10R2_FB28_Pos (28U)
5443#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
5444#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
5445#define CAN_F10R2_FB29_Pos (29U)
5446#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
5447#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
5448#define CAN_F10R2_FB30_Pos (30U)
5449#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
5450#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
5451#define CAN_F10R2_FB31_Pos (31U)
5452#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
5453#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
5454
5455/******************* Bit definition for CAN_F11R2 register ******************/
5456#define CAN_F11R2_FB0_Pos (0U)
5457#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
5458#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
5459#define CAN_F11R2_FB1_Pos (1U)
5460#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
5461#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
5462#define CAN_F11R2_FB2_Pos (2U)
5463#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
5464#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
5465#define CAN_F11R2_FB3_Pos (3U)
5466#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
5467#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
5468#define CAN_F11R2_FB4_Pos (4U)
5469#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
5470#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
5471#define CAN_F11R2_FB5_Pos (5U)
5472#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
5473#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
5474#define CAN_F11R2_FB6_Pos (6U)
5475#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
5476#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
5477#define CAN_F11R2_FB7_Pos (7U)
5478#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
5479#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
5480#define CAN_F11R2_FB8_Pos (8U)
5481#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
5482#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
5483#define CAN_F11R2_FB9_Pos (9U)
5484#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
5485#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
5486#define CAN_F11R2_FB10_Pos (10U)
5487#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
5488#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
5489#define CAN_F11R2_FB11_Pos (11U)
5490#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
5491#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
5492#define CAN_F11R2_FB12_Pos (12U)
5493#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
5494#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
5495#define CAN_F11R2_FB13_Pos (13U)
5496#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
5497#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
5498#define CAN_F11R2_FB14_Pos (14U)
5499#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
5500#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
5501#define CAN_F11R2_FB15_Pos (15U)
5502#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
5503#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
5504#define CAN_F11R2_FB16_Pos (16U)
5505#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
5506#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
5507#define CAN_F11R2_FB17_Pos (17U)
5508#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
5509#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
5510#define CAN_F11R2_FB18_Pos (18U)
5511#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
5512#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
5513#define CAN_F11R2_FB19_Pos (19U)
5514#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
5515#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
5516#define CAN_F11R2_FB20_Pos (20U)
5517#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
5518#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
5519#define CAN_F11R2_FB21_Pos (21U)
5520#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
5521#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
5522#define CAN_F11R2_FB22_Pos (22U)
5523#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
5524#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
5525#define CAN_F11R2_FB23_Pos (23U)
5526#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
5527#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
5528#define CAN_F11R2_FB24_Pos (24U)
5529#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
5530#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
5531#define CAN_F11R2_FB25_Pos (25U)
5532#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
5533#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
5534#define CAN_F11R2_FB26_Pos (26U)
5535#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
5536#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
5537#define CAN_F11R2_FB27_Pos (27U)
5538#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
5539#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
5540#define CAN_F11R2_FB28_Pos (28U)
5541#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
5542#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
5543#define CAN_F11R2_FB29_Pos (29U)
5544#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
5545#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
5546#define CAN_F11R2_FB30_Pos (30U)
5547#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
5548#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
5549#define CAN_F11R2_FB31_Pos (31U)
5550#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
5551#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
5552
5553/******************* Bit definition for CAN_F12R2 register ******************/
5554#define CAN_F12R2_FB0_Pos (0U)
5555#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
5556#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
5557#define CAN_F12R2_FB1_Pos (1U)
5558#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
5559#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
5560#define CAN_F12R2_FB2_Pos (2U)
5561#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
5562#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
5563#define CAN_F12R2_FB3_Pos (3U)
5564#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
5565#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
5566#define CAN_F12R2_FB4_Pos (4U)
5567#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
5568#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
5569#define CAN_F12R2_FB5_Pos (5U)
5570#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
5571#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
5572#define CAN_F12R2_FB6_Pos (6U)
5573#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
5574#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
5575#define CAN_F12R2_FB7_Pos (7U)
5576#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
5577#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
5578#define CAN_F12R2_FB8_Pos (8U)
5579#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
5580#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
5581#define CAN_F12R2_FB9_Pos (9U)
5582#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
5583#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
5584#define CAN_F12R2_FB10_Pos (10U)
5585#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
5586#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
5587#define CAN_F12R2_FB11_Pos (11U)
5588#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
5589#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
5590#define CAN_F12R2_FB12_Pos (12U)
5591#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
5592#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
5593#define CAN_F12R2_FB13_Pos (13U)
5594#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
5595#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
5596#define CAN_F12R2_FB14_Pos (14U)
5597#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
5598#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
5599#define CAN_F12R2_FB15_Pos (15U)
5600#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
5601#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
5602#define CAN_F12R2_FB16_Pos (16U)
5603#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
5604#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
5605#define CAN_F12R2_FB17_Pos (17U)
5606#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
5607#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
5608#define CAN_F12R2_FB18_Pos (18U)
5609#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
5610#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
5611#define CAN_F12R2_FB19_Pos (19U)
5612#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
5613#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
5614#define CAN_F12R2_FB20_Pos (20U)
5615#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
5616#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
5617#define CAN_F12R2_FB21_Pos (21U)
5618#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
5619#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
5620#define CAN_F12R2_FB22_Pos (22U)
5621#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
5622#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
5623#define CAN_F12R2_FB23_Pos (23U)
5624#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
5625#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
5626#define CAN_F12R2_FB24_Pos (24U)
5627#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
5628#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
5629#define CAN_F12R2_FB25_Pos (25U)
5630#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
5631#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
5632#define CAN_F12R2_FB26_Pos (26U)
5633#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
5634#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
5635#define CAN_F12R2_FB27_Pos (27U)
5636#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
5637#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
5638#define CAN_F12R2_FB28_Pos (28U)
5639#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
5640#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
5641#define CAN_F12R2_FB29_Pos (29U)
5642#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
5643#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
5644#define CAN_F12R2_FB30_Pos (30U)
5645#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
5646#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
5647#define CAN_F12R2_FB31_Pos (31U)
5648#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
5649#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
5650
5651/******************* Bit definition for CAN_F13R2 register ******************/
5652#define CAN_F13R2_FB0_Pos (0U)
5653#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
5654#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
5655#define CAN_F13R2_FB1_Pos (1U)
5656#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
5657#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
5658#define CAN_F13R2_FB2_Pos (2U)
5659#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
5660#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
5661#define CAN_F13R2_FB3_Pos (3U)
5662#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
5663#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
5664#define CAN_F13R2_FB4_Pos (4U)
5665#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
5666#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
5667#define CAN_F13R2_FB5_Pos (5U)
5668#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
5669#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
5670#define CAN_F13R2_FB6_Pos (6U)
5671#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
5672#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
5673#define CAN_F13R2_FB7_Pos (7U)
5674#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
5675#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
5676#define CAN_F13R2_FB8_Pos (8U)
5677#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
5678#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
5679#define CAN_F13R2_FB9_Pos (9U)
5680#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
5681#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
5682#define CAN_F13R2_FB10_Pos (10U)
5683#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
5684#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
5685#define CAN_F13R2_FB11_Pos (11U)
5686#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
5687#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
5688#define CAN_F13R2_FB12_Pos (12U)
5689#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
5690#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
5691#define CAN_F13R2_FB13_Pos (13U)
5692#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
5693#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
5694#define CAN_F13R2_FB14_Pos (14U)
5695#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
5696#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
5697#define CAN_F13R2_FB15_Pos (15U)
5698#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
5699#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
5700#define CAN_F13R2_FB16_Pos (16U)
5701#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
5702#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
5703#define CAN_F13R2_FB17_Pos (17U)
5704#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
5705#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
5706#define CAN_F13R2_FB18_Pos (18U)
5707#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
5708#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
5709#define CAN_F13R2_FB19_Pos (19U)
5710#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
5711#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
5712#define CAN_F13R2_FB20_Pos (20U)
5713#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
5714#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
5715#define CAN_F13R2_FB21_Pos (21U)
5716#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
5717#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
5718#define CAN_F13R2_FB22_Pos (22U)
5719#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
5720#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
5721#define CAN_F13R2_FB23_Pos (23U)
5722#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
5723#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
5724#define CAN_F13R2_FB24_Pos (24U)
5725#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
5726#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
5727#define CAN_F13R2_FB25_Pos (25U)
5728#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
5729#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
5730#define CAN_F13R2_FB26_Pos (26U)
5731#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
5732#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
5733#define CAN_F13R2_FB27_Pos (27U)
5734#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
5735#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
5736#define CAN_F13R2_FB28_Pos (28U)
5737#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
5738#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
5739#define CAN_F13R2_FB29_Pos (29U)
5740#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
5741#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
5742#define CAN_F13R2_FB30_Pos (30U)
5743#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
5744#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
5745#define CAN_F13R2_FB31_Pos (31U)
5746#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
5747#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
5748
5749/******************************************************************************/
5750/* */
5751/* CRC calculation unit */
5752/* */
5753/******************************************************************************/
5754/******************* Bit definition for CRC_DR register *********************/
5755#define CRC_DR_DR_Pos (0U)
5756#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
5757#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
5758
5759
5760/******************* Bit definition for CRC_IDR register ********************/
5761#define CRC_IDR_IDR_Pos (0U)
5762#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
5763#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
5764
5765
5766/******************** Bit definition for CRC_CR register ********************/
5767#define CRC_CR_RESET_Pos (0U)
5768#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
5769#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
5770
5771/******************************************************************************/
5772/* */
5773/* Crypto Processor */
5774/* */
5775/******************************************************************************/
5776/******************* Bits definition for CRYP_CR register ********************/
5777#define CRYP_CR_ALGODIR_Pos (2U)
5778#define CRYP_CR_ALGODIR_Msk (0x1U << CRYP_CR_ALGODIR_Pos) /*!< 0x00000004 */
5779#define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk
5780
5781#define CRYP_CR_ALGOMODE_Pos (3U)
5782#define CRYP_CR_ALGOMODE_Msk (0x10007U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00080038 */
5783#define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk
5784#define CRYP_CR_ALGOMODE_0 (0x00001U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
5785#define CRYP_CR_ALGOMODE_1 (0x00002U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
5786#define CRYP_CR_ALGOMODE_2 (0x00004U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
5787#define CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U
5788#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
5789#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1U << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
5790#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
5791#define CRYP_CR_ALGOMODE_DES_ECB_Pos (4U)
5792#define CRYP_CR_ALGOMODE_DES_ECB_Msk (0x1U << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */
5793#define CRYP_CR_ALGOMODE_DES_ECB CRYP_CR_ALGOMODE_DES_ECB_Msk
5794#define CRYP_CR_ALGOMODE_DES_CBC_Pos (3U)
5795#define CRYP_CR_ALGOMODE_DES_CBC_Msk (0x3U << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */
5796#define CRYP_CR_ALGOMODE_DES_CBC CRYP_CR_ALGOMODE_DES_CBC_Msk
5797#define CRYP_CR_ALGOMODE_AES_ECB_Pos (5U)
5798#define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1U << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */
5799#define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk
5800#define CRYP_CR_ALGOMODE_AES_CBC_Pos (3U)
5801#define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5U << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */
5802#define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk
5803#define CRYP_CR_ALGOMODE_AES_CTR_Pos (4U)
5804#define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3U << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */
5805#define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk
5806#define CRYP_CR_ALGOMODE_AES_KEY_Pos (3U)
5807#define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7U << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */
5808#define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk
5809
5810#define CRYP_CR_DATATYPE_Pos (6U)
5811#define CRYP_CR_DATATYPE_Msk (0x3U << CRYP_CR_DATATYPE_Pos) /*!< 0x000000C0 */
5812#define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk
5813#define CRYP_CR_DATATYPE_0 (0x1U << CRYP_CR_DATATYPE_Pos) /*!< 0x00000040 */
5814#define CRYP_CR_DATATYPE_1 (0x2U << CRYP_CR_DATATYPE_Pos) /*!< 0x00000080 */
5815#define CRYP_CR_KEYSIZE_Pos (8U)
5816#define CRYP_CR_KEYSIZE_Msk (0x3U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000300 */
5817#define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk
5818#define CRYP_CR_KEYSIZE_0 (0x1U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000100 */
5819#define CRYP_CR_KEYSIZE_1 (0x2U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000200 */
5820#define CRYP_CR_FFLUSH_Pos (14U)
5821#define CRYP_CR_FFLUSH_Msk (0x1U << CRYP_CR_FFLUSH_Pos) /*!< 0x00004000 */
5822#define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk
5823#define CRYP_CR_CRYPEN_Pos (15U)
5824#define CRYP_CR_CRYPEN_Msk (0x1U << CRYP_CR_CRYPEN_Pos) /*!< 0x00008000 */
5825#define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk
5826
5827#define CRYP_CR_GCM_CCMPH_Pos (16U)
5828#define CRYP_CR_GCM_CCMPH_Msk (0x3U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00030000 */
5829#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
5830#define CRYP_CR_GCM_CCMPH_0 (0x1U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
5831#define CRYP_CR_GCM_CCMPH_1 (0x2U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
5832#define CRYP_CR_ALGOMODE_3 0x00080000U
5833
5834/****************** Bits definition for CRYP_SR register *********************/
5835#define CRYP_SR_IFEM_Pos (0U)
5836#define CRYP_SR_IFEM_Msk (0x1U << CRYP_SR_IFEM_Pos) /*!< 0x00000001 */
5837#define CRYP_SR_IFEM CRYP_SR_IFEM_Msk
5838#define CRYP_SR_IFNF_Pos (1U)
5839#define CRYP_SR_IFNF_Msk (0x1U << CRYP_SR_IFNF_Pos) /*!< 0x00000002 */
5840#define CRYP_SR_IFNF CRYP_SR_IFNF_Msk
5841#define CRYP_SR_OFNE_Pos (2U)
5842#define CRYP_SR_OFNE_Msk (0x1U << CRYP_SR_OFNE_Pos) /*!< 0x00000004 */
5843#define CRYP_SR_OFNE CRYP_SR_OFNE_Msk
5844#define CRYP_SR_OFFU_Pos (3U)
5845#define CRYP_SR_OFFU_Msk (0x1U << CRYP_SR_OFFU_Pos) /*!< 0x00000008 */
5846#define CRYP_SR_OFFU CRYP_SR_OFFU_Msk
5847#define CRYP_SR_BUSY_Pos (4U)
5848#define CRYP_SR_BUSY_Msk (0x1U << CRYP_SR_BUSY_Pos) /*!< 0x00000010 */
5849#define CRYP_SR_BUSY CRYP_SR_BUSY_Msk
5850/****************** Bits definition for CRYP_DMACR register ******************/
5851#define CRYP_DMACR_DIEN_Pos (0U)
5852#define CRYP_DMACR_DIEN_Msk (0x1U << CRYP_DMACR_DIEN_Pos) /*!< 0x00000001 */
5853#define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk
5854#define CRYP_DMACR_DOEN_Pos (1U)
5855#define CRYP_DMACR_DOEN_Msk (0x1U << CRYP_DMACR_DOEN_Pos) /*!< 0x00000002 */
5856#define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk
5857/***************** Bits definition for CRYP_IMSCR register ******************/
5858#define CRYP_IMSCR_INIM_Pos (0U)
5859#define CRYP_IMSCR_INIM_Msk (0x1U << CRYP_IMSCR_INIM_Pos) /*!< 0x00000001 */
5860#define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk
5861#define CRYP_IMSCR_OUTIM_Pos (1U)
5862#define CRYP_IMSCR_OUTIM_Msk (0x1U << CRYP_IMSCR_OUTIM_Pos) /*!< 0x00000002 */
5863#define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk
5864/****************** Bits definition for CRYP_RISR register *******************/
5865#define CRYP_RISR_OUTRIS_Pos (0U)
5866#define CRYP_RISR_OUTRIS_Msk (0x1U << CRYP_RISR_OUTRIS_Pos) /*!< 0x00000001 */
5867#define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk
5868#define CRYP_RISR_INRIS_Pos (1U)
5869#define CRYP_RISR_INRIS_Msk (0x1U << CRYP_RISR_INRIS_Pos) /*!< 0x00000002 */
5870#define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk
5871/****************** Bits definition for CRYP_MISR register *******************/
5872#define CRYP_MISR_INMIS_Pos (0U)
5873#define CRYP_MISR_INMIS_Msk (0x1U << CRYP_MISR_INMIS_Pos) /*!< 0x00000001 */
5874#define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk
5875#define CRYP_MISR_OUTMIS_Pos (1U)
5876#define CRYP_MISR_OUTMIS_Msk (0x1U << CRYP_MISR_OUTMIS_Pos) /*!< 0x00000002 */
5877#define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk
5878
5879/******************************************************************************/
5880/* */
5881/* Digital to Analog Converter */
5882/* */
5883/******************************************************************************/
5884/*
5885 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
5886 */
5887#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
5888/******************** Bit definition for DAC_CR register ********************/
5889#define DAC_CR_EN1_Pos (0U)
5890#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
5891#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
5892#define DAC_CR_BOFF1_Pos (1U)
5893#define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
5894#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
5895#define DAC_CR_TEN1_Pos (2U)
5896#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
5897#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
5898
5899#define DAC_CR_TSEL1_Pos (3U)
5900#define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
5901#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5902#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
5903#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
5904#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
5905
5906#define DAC_CR_WAVE1_Pos (6U)
5907#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
5908#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5909#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
5910#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
5911
5912#define DAC_CR_MAMP1_Pos (8U)
5913#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
5914#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5915#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
5916#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
5917#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
5918#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
5919
5920#define DAC_CR_DMAEN1_Pos (12U)
5921#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
5922#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
5923#define DAC_CR_DMAUDRIE1_Pos (13U)
5924#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
5925#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
5926#define DAC_CR_EN2_Pos (16U)
5927#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
5928#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
5929#define DAC_CR_BOFF2_Pos (17U)
5930#define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
5931#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
5932#define DAC_CR_TEN2_Pos (18U)
5933#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
5934#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
5935
5936#define DAC_CR_TSEL2_Pos (19U)
5937#define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
5938#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5939#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
5940#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
5941#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
5942
5943#define DAC_CR_WAVE2_Pos (22U)
5944#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
5945#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5946#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
5947#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
5948
5949#define DAC_CR_MAMP2_Pos (24U)
5950#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
5951#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5952#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
5953#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
5954#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
5955#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
5956
5957#define DAC_CR_DMAEN2_Pos (28U)
5958#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
5959#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
5960#define DAC_CR_DMAUDRIE2_Pos (29U)
5961#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
5962#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
5963
5964/***************** Bit definition for DAC_SWTRIGR register ******************/
5965#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5966#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
5967#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
5968#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5969#define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
5970#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
5971
5972/***************** Bit definition for DAC_DHR12R1 register ******************/
5973#define DAC_DHR12R1_DACC1DHR_Pos (0U)
5974#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
5975#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5976
5977/***************** Bit definition for DAC_DHR12L1 register ******************/
5978#define DAC_DHR12L1_DACC1DHR_Pos (4U)
5979#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5980#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5981
5982/****************** Bit definition for DAC_DHR8R1 register ******************/
5983#define DAC_DHR8R1_DACC1DHR_Pos (0U)
5984#define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
5985#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5986
5987/***************** Bit definition for DAC_DHR12R2 register ******************/
5988#define DAC_DHR12R2_DACC2DHR_Pos (0U)
5989#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
5990#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5991
5992/***************** Bit definition for DAC_DHR12L2 register ******************/
5993#define DAC_DHR12L2_DACC2DHR_Pos (4U)
5994#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
5995#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5996
5997/****************** Bit definition for DAC_DHR8R2 register ******************/
5998#define DAC_DHR8R2_DACC2DHR_Pos (0U)
5999#define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
6000#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
6001
6002/***************** Bit definition for DAC_DHR12RD register ******************/
6003#define DAC_DHR12RD_DACC1DHR_Pos (0U)
6004#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
6005#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
6006#define DAC_DHR12RD_DACC2DHR_Pos (16U)
6007#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
6008#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
6009
6010/***************** Bit definition for DAC_DHR12LD register ******************/
6011#define DAC_DHR12LD_DACC1DHR_Pos (4U)
6012#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
6013#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
6014#define DAC_DHR12LD_DACC2DHR_Pos (20U)
6015#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
6016#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
6017
6018/****************** Bit definition for DAC_DHR8RD register ******************/
6019#define DAC_DHR8RD_DACC1DHR_Pos (0U)
6020#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
6021#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
6022#define DAC_DHR8RD_DACC2DHR_Pos (8U)
6023#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
6024#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
6025
6026/******************* Bit definition for DAC_DOR1 register *******************/
6027#define DAC_DOR1_DACC1DOR_Pos (0U)
6028#define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
6029#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
6030
6031/******************* Bit definition for DAC_DOR2 register *******************/
6032#define DAC_DOR2_DACC2DOR_Pos (0U)
6033#define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
6034#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
6035
6036/******************** Bit definition for DAC_SR register ********************/
6037#define DAC_SR_DMAUDR1_Pos (13U)
6038#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
6039#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
6040#define DAC_SR_DMAUDR2_Pos (29U)
6041#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
6042#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
6043
6044/******************************************************************************/
6045/* */
6046/* DCMI */
6047/* */
6048/******************************************************************************/
6049/******************** Bits definition for DCMI_CR register ******************/
6050#define DCMI_CR_CAPTURE_Pos (0U)
6051#define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
6052#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
6053#define DCMI_CR_CM_Pos (1U)
6054#define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
6055#define DCMI_CR_CM DCMI_CR_CM_Msk
6056#define DCMI_CR_CROP_Pos (2U)
6057#define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
6058#define DCMI_CR_CROP DCMI_CR_CROP_Msk
6059#define DCMI_CR_JPEG_Pos (3U)
6060#define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
6061#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
6062#define DCMI_CR_ESS_Pos (4U)
6063#define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
6064#define DCMI_CR_ESS DCMI_CR_ESS_Msk
6065#define DCMI_CR_PCKPOL_Pos (5U)
6066#define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
6067#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
6068#define DCMI_CR_HSPOL_Pos (6U)
6069#define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
6070#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
6071#define DCMI_CR_VSPOL_Pos (7U)
6072#define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
6073#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
6074#define DCMI_CR_FCRC_0 0x00000100U
6075#define DCMI_CR_FCRC_1 0x00000200U
6076#define DCMI_CR_EDM_0 0x00000400U
6077#define DCMI_CR_EDM_1 0x00000800U
6078#define DCMI_CR_OUTEN_Pos (13U)
6079#define DCMI_CR_OUTEN_Msk (0x1U << DCMI_CR_OUTEN_Pos) /*!< 0x00002000 */
6080#define DCMI_CR_OUTEN DCMI_CR_OUTEN_Msk
6081#define DCMI_CR_ENABLE_Pos (14U)
6082#define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
6083#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
6084#define DCMI_CR_BSM_0 0x00010000U
6085#define DCMI_CR_BSM_1 0x00020000U
6086#define DCMI_CR_OEBS_Pos (18U)
6087#define DCMI_CR_OEBS_Msk (0x1U << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
6088#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
6089#define DCMI_CR_LSM_Pos (19U)
6090#define DCMI_CR_LSM_Msk (0x1U << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
6091#define DCMI_CR_LSM DCMI_CR_LSM_Msk
6092#define DCMI_CR_OELS_Pos (20U)
6093#define DCMI_CR_OELS_Msk (0x1U << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
6094#define DCMI_CR_OELS DCMI_CR_OELS_Msk
6095
6096/******************** Bits definition for DCMI_SR register ******************/
6097#define DCMI_SR_HSYNC_Pos (0U)
6098#define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
6099#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
6100#define DCMI_SR_VSYNC_Pos (1U)
6101#define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
6102#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
6103#define DCMI_SR_FNE_Pos (2U)
6104#define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
6105#define DCMI_SR_FNE DCMI_SR_FNE_Msk
6106
6107/******************** Bits definition for DCMI_RIS register *****************/
6108#define DCMI_RIS_FRAME_RIS_Pos (0U)
6109#define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
6110#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
6111#define DCMI_RIS_OVR_RIS_Pos (1U)
6112#define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
6113#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
6114#define DCMI_RIS_ERR_RIS_Pos (2U)
6115#define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
6116#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
6117#define DCMI_RIS_VSYNC_RIS_Pos (3U)
6118#define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
6119#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
6120#define DCMI_RIS_LINE_RIS_Pos (4U)
6121#define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
6122#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
6123/* Legacy defines */
6124#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
6125#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
6126#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
6127#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
6128#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
6129#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
6130
6131/******************** Bits definition for DCMI_IER register *****************/
6132#define DCMI_IER_FRAME_IE_Pos (0U)
6133#define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
6134#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
6135#define DCMI_IER_OVR_IE_Pos (1U)
6136#define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
6137#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
6138#define DCMI_IER_ERR_IE_Pos (2U)
6139#define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
6140#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
6141#define DCMI_IER_VSYNC_IE_Pos (3U)
6142#define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
6143#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
6144#define DCMI_IER_LINE_IE_Pos (4U)
6145#define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
6146#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
6147/* Legacy defines */
6148#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
6149
6150/******************** Bits definition for DCMI_MIS register *****************/
6151#define DCMI_MIS_FRAME_MIS_Pos (0U)
6152#define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
6153#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
6154#define DCMI_MIS_OVR_MIS_Pos (1U)
6155#define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
6156#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
6157#define DCMI_MIS_ERR_MIS_Pos (2U)
6158#define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
6159#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
6160#define DCMI_MIS_VSYNC_MIS_Pos (3U)
6161#define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
6162#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
6163#define DCMI_MIS_LINE_MIS_Pos (4U)
6164#define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
6165#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
6166
6167/* Legacy defines */
6168#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
6169#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
6170#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
6171#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
6172#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
6173
6174/******************** Bits definition for DCMI_ICR register *****************/
6175#define DCMI_ICR_FRAME_ISC_Pos (0U)
6176#define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
6177#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
6178#define DCMI_ICR_OVR_ISC_Pos (1U)
6179#define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
6180#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
6181#define DCMI_ICR_ERR_ISC_Pos (2U)
6182#define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
6183#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
6184#define DCMI_ICR_VSYNC_ISC_Pos (3U)
6185#define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
6186#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
6187#define DCMI_ICR_LINE_ISC_Pos (4U)
6188#define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
6189#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
6190
6191/* Legacy defines */
6192#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
6193
6194/******************** Bits definition for DCMI_ESCR register ******************/
6195#define DCMI_ESCR_FSC_Pos (0U)
6196#define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
6197#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
6198#define DCMI_ESCR_LSC_Pos (8U)
6199#define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
6200#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
6201#define DCMI_ESCR_LEC_Pos (16U)
6202#define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
6203#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
6204#define DCMI_ESCR_FEC_Pos (24U)
6205#define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
6206#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
6207
6208/******************** Bits definition for DCMI_ESUR register ******************/
6209#define DCMI_ESUR_FSU_Pos (0U)
6210#define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
6211#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
6212#define DCMI_ESUR_LSU_Pos (8U)
6213#define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
6214#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
6215#define DCMI_ESUR_LEU_Pos (16U)
6216#define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
6217#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
6218#define DCMI_ESUR_FEU_Pos (24U)
6219#define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
6220#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
6221
6222/******************** Bits definition for DCMI_CWSTRT register ******************/
6223#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
6224#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
6225#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
6226#define DCMI_CWSTRT_VST_Pos (16U)
6227#define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
6228#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
6229
6230/******************** Bits definition for DCMI_CWSIZE register ******************/
6231#define DCMI_CWSIZE_CAPCNT_Pos (0U)
6232#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
6233#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
6234#define DCMI_CWSIZE_VLINE_Pos (16U)
6235#define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
6236#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
6237
6238/******************** Bits definition for DCMI_DR register *********************/
6239#define DCMI_DR_BYTE0_Pos (0U)
6240#define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
6241#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
6242#define DCMI_DR_BYTE1_Pos (8U)
6243#define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
6244#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
6245#define DCMI_DR_BYTE2_Pos (16U)
6246#define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
6247#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
6248#define DCMI_DR_BYTE3_Pos (24U)
6249#define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
6250#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
6251
6252/******************************************************************************/
6253/* */
6254/* DMA Controller */
6255/* */
6256/******************************************************************************/
6257/******************** Bits definition for DMA_SxCR register *****************/
6258#define DMA_SxCR_CHSEL_Pos (25U)
6259#define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
6260#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
6261#define DMA_SxCR_CHSEL_0 0x02000000U
6262#define DMA_SxCR_CHSEL_1 0x04000000U
6263#define DMA_SxCR_CHSEL_2 0x08000000U
6264#define DMA_SxCR_MBURST_Pos (23U)
6265#define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
6266#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
6267#define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
6268#define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
6269#define DMA_SxCR_PBURST_Pos (21U)
6270#define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
6271#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
6272#define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
6273#define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
6274#define DMA_SxCR_CT_Pos (19U)
6275#define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
6276#define DMA_SxCR_CT DMA_SxCR_CT_Msk
6277#define DMA_SxCR_DBM_Pos (18U)
6278#define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
6279#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
6280#define DMA_SxCR_PL_Pos (16U)
6281#define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
6282#define DMA_SxCR_PL DMA_SxCR_PL_Msk
6283#define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
6284#define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
6285#define DMA_SxCR_PINCOS_Pos (15U)
6286#define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
6287#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
6288#define DMA_SxCR_MSIZE_Pos (13U)
6289#define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
6290#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
6291#define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
6292#define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
6293#define DMA_SxCR_PSIZE_Pos (11U)
6294#define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
6295#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
6296#define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
6297#define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
6298#define DMA_SxCR_MINC_Pos (10U)
6299#define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
6300#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
6301#define DMA_SxCR_PINC_Pos (9U)
6302#define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
6303#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
6304#define DMA_SxCR_CIRC_Pos (8U)
6305#define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
6306#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
6307#define DMA_SxCR_DIR_Pos (6U)
6308#define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
6309#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
6310#define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
6311#define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
6312#define DMA_SxCR_PFCTRL_Pos (5U)
6313#define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
6314#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
6315#define DMA_SxCR_TCIE_Pos (4U)
6316#define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
6317#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
6318#define DMA_SxCR_HTIE_Pos (3U)
6319#define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
6320#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
6321#define DMA_SxCR_TEIE_Pos (2U)
6322#define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
6323#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
6324#define DMA_SxCR_DMEIE_Pos (1U)
6325#define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
6326#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
6327#define DMA_SxCR_EN_Pos (0U)
6328#define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
6329#define DMA_SxCR_EN DMA_SxCR_EN_Msk
6330
6331/* Legacy defines */
6332#define DMA_SxCR_ACK_Pos (20U)
6333#define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
6334#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
6335
6336/******************** Bits definition for DMA_SxCNDTR register **************/
6337#define DMA_SxNDT_Pos (0U)
6338#define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
6339#define DMA_SxNDT DMA_SxNDT_Msk
6340#define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
6341#define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
6342#define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
6343#define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
6344#define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
6345#define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
6346#define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
6347#define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
6348#define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
6349#define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
6350#define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
6351#define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
6352#define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
6353#define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
6354#define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
6355#define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
6356
6357/******************** Bits definition for DMA_SxFCR register ****************/
6358#define DMA_SxFCR_FEIE_Pos (7U)
6359#define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
6360#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
6361#define DMA_SxFCR_FS_Pos (3U)
6362#define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
6363#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
6364#define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
6365#define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
6366#define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
6367#define DMA_SxFCR_DMDIS_Pos (2U)
6368#define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
6369#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
6370#define DMA_SxFCR_FTH_Pos (0U)
6371#define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
6372#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
6373#define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
6374#define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
6375
6376/******************** Bits definition for DMA_LISR register *****************/
6377#define DMA_LISR_TCIF3_Pos (27U)
6378#define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
6379#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
6380#define DMA_LISR_HTIF3_Pos (26U)
6381#define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
6382#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
6383#define DMA_LISR_TEIF3_Pos (25U)
6384#define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
6385#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
6386#define DMA_LISR_DMEIF3_Pos (24U)
6387#define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
6388#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
6389#define DMA_LISR_FEIF3_Pos (22U)
6390#define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
6391#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
6392#define DMA_LISR_TCIF2_Pos (21U)
6393#define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
6394#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
6395#define DMA_LISR_HTIF2_Pos (20U)
6396#define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
6397#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
6398#define DMA_LISR_TEIF2_Pos (19U)
6399#define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
6400#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
6401#define DMA_LISR_DMEIF2_Pos (18U)
6402#define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
6403#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
6404#define DMA_LISR_FEIF2_Pos (16U)
6405#define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
6406#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
6407#define DMA_LISR_TCIF1_Pos (11U)
6408#define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
6409#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
6410#define DMA_LISR_HTIF1_Pos (10U)
6411#define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
6412#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
6413#define DMA_LISR_TEIF1_Pos (9U)
6414#define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
6415#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
6416#define DMA_LISR_DMEIF1_Pos (8U)
6417#define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
6418#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
6419#define DMA_LISR_FEIF1_Pos (6U)
6420#define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
6421#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
6422#define DMA_LISR_TCIF0_Pos (5U)
6423#define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
6424#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
6425#define DMA_LISR_HTIF0_Pos (4U)
6426#define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
6427#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
6428#define DMA_LISR_TEIF0_Pos (3U)
6429#define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
6430#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
6431#define DMA_LISR_DMEIF0_Pos (2U)
6432#define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
6433#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
6434#define DMA_LISR_FEIF0_Pos (0U)
6435#define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
6436#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
6437
6438/******************** Bits definition for DMA_HISR register *****************/
6439#define DMA_HISR_TCIF7_Pos (27U)
6440#define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
6441#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
6442#define DMA_HISR_HTIF7_Pos (26U)
6443#define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
6444#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
6445#define DMA_HISR_TEIF7_Pos (25U)
6446#define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
6447#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
6448#define DMA_HISR_DMEIF7_Pos (24U)
6449#define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
6450#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
6451#define DMA_HISR_FEIF7_Pos (22U)
6452#define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
6453#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
6454#define DMA_HISR_TCIF6_Pos (21U)
6455#define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
6456#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
6457#define DMA_HISR_HTIF6_Pos (20U)
6458#define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
6459#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
6460#define DMA_HISR_TEIF6_Pos (19U)
6461#define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
6462#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
6463#define DMA_HISR_DMEIF6_Pos (18U)
6464#define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
6465#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
6466#define DMA_HISR_FEIF6_Pos (16U)
6467#define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
6468#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
6469#define DMA_HISR_TCIF5_Pos (11U)
6470#define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
6471#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
6472#define DMA_HISR_HTIF5_Pos (10U)
6473#define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
6474#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
6475#define DMA_HISR_TEIF5_Pos (9U)
6476#define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
6477#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
6478#define DMA_HISR_DMEIF5_Pos (8U)
6479#define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
6480#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
6481#define DMA_HISR_FEIF5_Pos (6U)
6482#define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
6483#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
6484#define DMA_HISR_TCIF4_Pos (5U)
6485#define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
6486#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
6487#define DMA_HISR_HTIF4_Pos (4U)
6488#define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
6489#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
6490#define DMA_HISR_TEIF4_Pos (3U)
6491#define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
6492#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
6493#define DMA_HISR_DMEIF4_Pos (2U)
6494#define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
6495#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
6496#define DMA_HISR_FEIF4_Pos (0U)
6497#define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
6498#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
6499
6500/******************** Bits definition for DMA_LIFCR register ****************/
6501#define DMA_LIFCR_CTCIF3_Pos (27U)
6502#define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
6503#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
6504#define DMA_LIFCR_CHTIF3_Pos (26U)
6505#define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
6506#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
6507#define DMA_LIFCR_CTEIF3_Pos (25U)
6508#define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
6509#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
6510#define DMA_LIFCR_CDMEIF3_Pos (24U)
6511#define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
6512#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
6513#define DMA_LIFCR_CFEIF3_Pos (22U)
6514#define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
6515#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
6516#define DMA_LIFCR_CTCIF2_Pos (21U)
6517#define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
6518#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
6519#define DMA_LIFCR_CHTIF2_Pos (20U)
6520#define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
6521#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
6522#define DMA_LIFCR_CTEIF2_Pos (19U)
6523#define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
6524#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
6525#define DMA_LIFCR_CDMEIF2_Pos (18U)
6526#define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
6527#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
6528#define DMA_LIFCR_CFEIF2_Pos (16U)
6529#define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
6530#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
6531#define DMA_LIFCR_CTCIF1_Pos (11U)
6532#define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
6533#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
6534#define DMA_LIFCR_CHTIF1_Pos (10U)
6535#define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
6536#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
6537#define DMA_LIFCR_CTEIF1_Pos (9U)
6538#define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
6539#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
6540#define DMA_LIFCR_CDMEIF1_Pos (8U)
6541#define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
6542#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
6543#define DMA_LIFCR_CFEIF1_Pos (6U)
6544#define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
6545#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
6546#define DMA_LIFCR_CTCIF0_Pos (5U)
6547#define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
6548#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
6549#define DMA_LIFCR_CHTIF0_Pos (4U)
6550#define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
6551#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
6552#define DMA_LIFCR_CTEIF0_Pos (3U)
6553#define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
6554#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
6555#define DMA_LIFCR_CDMEIF0_Pos (2U)
6556#define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
6557#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
6558#define DMA_LIFCR_CFEIF0_Pos (0U)
6559#define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
6560#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
6561
6562/******************** Bits definition for DMA_HIFCR register ****************/
6563#define DMA_HIFCR_CTCIF7_Pos (27U)
6564#define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
6565#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
6566#define DMA_HIFCR_CHTIF7_Pos (26U)
6567#define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
6568#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
6569#define DMA_HIFCR_CTEIF7_Pos (25U)
6570#define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
6571#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
6572#define DMA_HIFCR_CDMEIF7_Pos (24U)
6573#define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
6574#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
6575#define DMA_HIFCR_CFEIF7_Pos (22U)
6576#define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
6577#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
6578#define DMA_HIFCR_CTCIF6_Pos (21U)
6579#define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
6580#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
6581#define DMA_HIFCR_CHTIF6_Pos (20U)
6582#define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
6583#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
6584#define DMA_HIFCR_CTEIF6_Pos (19U)
6585#define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
6586#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
6587#define DMA_HIFCR_CDMEIF6_Pos (18U)
6588#define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
6589#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
6590#define DMA_HIFCR_CFEIF6_Pos (16U)
6591#define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
6592#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
6593#define DMA_HIFCR_CTCIF5_Pos (11U)
6594#define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
6595#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
6596#define DMA_HIFCR_CHTIF5_Pos (10U)
6597#define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
6598#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
6599#define DMA_HIFCR_CTEIF5_Pos (9U)
6600#define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
6601#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
6602#define DMA_HIFCR_CDMEIF5_Pos (8U)
6603#define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
6604#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
6605#define DMA_HIFCR_CFEIF5_Pos (6U)
6606#define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
6607#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
6608#define DMA_HIFCR_CTCIF4_Pos (5U)
6609#define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
6610#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
6611#define DMA_HIFCR_CHTIF4_Pos (4U)
6612#define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
6613#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
6614#define DMA_HIFCR_CTEIF4_Pos (3U)
6615#define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
6616#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
6617#define DMA_HIFCR_CDMEIF4_Pos (2U)
6618#define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
6619#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
6620#define DMA_HIFCR_CFEIF4_Pos (0U)
6621#define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
6622#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
6623
6624/****************** Bit definition for DMA_SxPAR register ********************/
6625#define DMA_SxPAR_PA_Pos (0U)
6626#define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
6627#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
6628
6629/****************** Bit definition for DMA_SxM0AR register ********************/
6630#define DMA_SxM0AR_M0A_Pos (0U)
6631#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
6632#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
6633
6634/****************** Bit definition for DMA_SxM1AR register ********************/
6635#define DMA_SxM1AR_M1A_Pos (0U)
6636#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
6637#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
6638
6639
6640/******************************************************************************/
6641/* */
6642/* AHB Master DMA2D Controller (DMA2D) */
6643/* */
6644/******************************************************************************/
6645
6646/******************** Bit definition for DMA2D_CR register ******************/
6647
6648#define DMA2D_CR_START_Pos (0U)
6649#define DMA2D_CR_START_Msk (0x1U << DMA2D_CR_START_Pos) /*!< 0x00000001 */
6650#define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
6651#define DMA2D_CR_SUSP_Pos (1U)
6652#define DMA2D_CR_SUSP_Msk (0x1U << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
6653#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
6654#define DMA2D_CR_ABORT_Pos (2U)
6655#define DMA2D_CR_ABORT_Msk (0x1U << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
6656#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
6657#define DMA2D_CR_TEIE_Pos (8U)
6658#define DMA2D_CR_TEIE_Msk (0x1U << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
6659#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
6660#define DMA2D_CR_TCIE_Pos (9U)
6661#define DMA2D_CR_TCIE_Msk (0x1U << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
6662#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
6663#define DMA2D_CR_TWIE_Pos (10U)
6664#define DMA2D_CR_TWIE_Msk (0x1U << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
6665#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
6666#define DMA2D_CR_CAEIE_Pos (11U)
6667#define DMA2D_CR_CAEIE_Msk (0x1U << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
6668#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
6669#define DMA2D_CR_CTCIE_Pos (12U)
6670#define DMA2D_CR_CTCIE_Msk (0x1U << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
6671#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
6672#define DMA2D_CR_CEIE_Pos (13U)
6673#define DMA2D_CR_CEIE_Msk (0x1U << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
6674#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
6675#define DMA2D_CR_MODE_Pos (16U)
6676#define DMA2D_CR_MODE_Msk (0x3U << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */
6677#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */
6678#define DMA2D_CR_MODE_0 (0x1U << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
6679#define DMA2D_CR_MODE_1 (0x2U << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
6680
6681/******************** Bit definition for DMA2D_ISR register *****************/
6682
6683#define DMA2D_ISR_TEIF_Pos (0U)
6684#define DMA2D_ISR_TEIF_Msk (0x1U << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
6685#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
6686#define DMA2D_ISR_TCIF_Pos (1U)
6687#define DMA2D_ISR_TCIF_Msk (0x1U << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
6688#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
6689#define DMA2D_ISR_TWIF_Pos (2U)
6690#define DMA2D_ISR_TWIF_Msk (0x1U << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
6691#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
6692#define DMA2D_ISR_CAEIF_Pos (3U)
6693#define DMA2D_ISR_CAEIF_Msk (0x1U << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
6694#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
6695#define DMA2D_ISR_CTCIF_Pos (4U)
6696#define DMA2D_ISR_CTCIF_Msk (0x1U << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
6697#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
6698#define DMA2D_ISR_CEIF_Pos (5U)
6699#define DMA2D_ISR_CEIF_Msk (0x1U << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
6700#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
6701
6702/******************** Bit definition for DMA2D_IFCR register ****************/
6703
6704#define DMA2D_IFCR_CTEIF_Pos (0U)
6705#define DMA2D_IFCR_CTEIF_Msk (0x1U << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
6706#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
6707#define DMA2D_IFCR_CTCIF_Pos (1U)
6708#define DMA2D_IFCR_CTCIF_Msk (0x1U << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
6709#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
6710#define DMA2D_IFCR_CTWIF_Pos (2U)
6711#define DMA2D_IFCR_CTWIF_Msk (0x1U << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
6712#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
6713#define DMA2D_IFCR_CAECIF_Pos (3U)
6714#define DMA2D_IFCR_CAECIF_Msk (0x1U << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
6715#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
6716#define DMA2D_IFCR_CCTCIF_Pos (4U)
6717#define DMA2D_IFCR_CCTCIF_Msk (0x1U << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
6718#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
6719#define DMA2D_IFCR_CCEIF_Pos (5U)
6720#define DMA2D_IFCR_CCEIF_Msk (0x1U << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
6721#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
6722
6723/* Legacy defines */
6724#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
6725#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
6726#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
6727#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
6728#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
6729#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
6730
6731/******************** Bit definition for DMA2D_FGMAR register ***************/
6732
6733#define DMA2D_FGMAR_MA_Pos (0U)
6734#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
6735#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */
6736
6737/******************** Bit definition for DMA2D_FGOR register ****************/
6738
6739#define DMA2D_FGOR_LO_Pos (0U)
6740#define DMA2D_FGOR_LO_Msk (0x3FFFU << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */
6741#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
6742
6743/******************** Bit definition for DMA2D_BGMAR register ***************/
6744
6745#define DMA2D_BGMAR_MA_Pos (0U)
6746#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
6747#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */
6748
6749/******************** Bit definition for DMA2D_BGOR register ****************/
6750
6751#define DMA2D_BGOR_LO_Pos (0U)
6752#define DMA2D_BGOR_LO_Msk (0x3FFFU << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */
6753#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
6754
6755/******************** Bit definition for DMA2D_FGPFCCR register *************/
6756
6757#define DMA2D_FGPFCCR_CM_Pos (0U)
6758#define DMA2D_FGPFCCR_CM_Msk (0xFU << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
6759#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
6760#define DMA2D_FGPFCCR_CM_0 (0x1U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
6761#define DMA2D_FGPFCCR_CM_1 (0x2U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
6762#define DMA2D_FGPFCCR_CM_2 (0x4U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
6763#define DMA2D_FGPFCCR_CM_3 (0x8U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
6764#define DMA2D_FGPFCCR_CCM_Pos (4U)
6765#define DMA2D_FGPFCCR_CCM_Msk (0x1U << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
6766#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
6767#define DMA2D_FGPFCCR_START_Pos (5U)
6768#define DMA2D_FGPFCCR_START_Msk (0x1U << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
6769#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
6770#define DMA2D_FGPFCCR_CS_Pos (8U)
6771#define DMA2D_FGPFCCR_CS_Msk (0xFFU << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
6772#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
6773#define DMA2D_FGPFCCR_AM_Pos (16U)
6774#define DMA2D_FGPFCCR_AM_Msk (0x3U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
6775#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
6776#define DMA2D_FGPFCCR_AM_0 (0x1U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
6777#define DMA2D_FGPFCCR_AM_1 (0x2U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
6778#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
6779#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
6780#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
6781
6782/******************** Bit definition for DMA2D_FGCOLR register **************/
6783
6784#define DMA2D_FGCOLR_BLUE_Pos (0U)
6785#define DMA2D_FGCOLR_BLUE_Msk (0xFFU << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
6786#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */
6787#define DMA2D_FGCOLR_GREEN_Pos (8U)
6788#define DMA2D_FGCOLR_GREEN_Msk (0xFFU << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
6789#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */
6790#define DMA2D_FGCOLR_RED_Pos (16U)
6791#define DMA2D_FGCOLR_RED_Msk (0xFFU << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
6792#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */
6793
6794/******************** Bit definition for DMA2D_BGPFCCR register *************/
6795
6796#define DMA2D_BGPFCCR_CM_Pos (0U)
6797#define DMA2D_BGPFCCR_CM_Msk (0xFU << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
6798#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
6799#define DMA2D_BGPFCCR_CM_0 (0x1U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
6800#define DMA2D_BGPFCCR_CM_1 (0x2U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
6801#define DMA2D_BGPFCCR_CM_2 (0x4U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
6802#define DMA2D_BGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
6803#define DMA2D_BGPFCCR_CCM_Pos (4U)
6804#define DMA2D_BGPFCCR_CCM_Msk (0x1U << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
6805#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
6806#define DMA2D_BGPFCCR_START_Pos (5U)
6807#define DMA2D_BGPFCCR_START_Msk (0x1U << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
6808#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
6809#define DMA2D_BGPFCCR_CS_Pos (8U)
6810#define DMA2D_BGPFCCR_CS_Msk (0xFFU << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
6811#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
6812#define DMA2D_BGPFCCR_AM_Pos (16U)
6813#define DMA2D_BGPFCCR_AM_Msk (0x3U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
6814#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
6815#define DMA2D_BGPFCCR_AM_0 (0x1U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
6816#define DMA2D_BGPFCCR_AM_1 (0x2U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
6817#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
6818#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
6819#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
6820
6821/******************** Bit definition for DMA2D_BGCOLR register **************/
6822
6823#define DMA2D_BGCOLR_BLUE_Pos (0U)
6824#define DMA2D_BGCOLR_BLUE_Msk (0xFFU << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
6825#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */
6826#define DMA2D_BGCOLR_GREEN_Pos (8U)
6827#define DMA2D_BGCOLR_GREEN_Msk (0xFFU << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
6828#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */
6829#define DMA2D_BGCOLR_RED_Pos (16U)
6830#define DMA2D_BGCOLR_RED_Msk (0xFFU << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
6831#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */
6832
6833/******************** Bit definition for DMA2D_FGCMAR register **************/
6834
6835#define DMA2D_FGCMAR_MA_Pos (0U)
6836#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
6837#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */
6838
6839/******************** Bit definition for DMA2D_BGCMAR register **************/
6840
6841#define DMA2D_BGCMAR_MA_Pos (0U)
6842#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
6843#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */
6844
6845/******************** Bit definition for DMA2D_OPFCCR register **************/
6846
6847#define DMA2D_OPFCCR_CM_Pos (0U)
6848#define DMA2D_OPFCCR_CM_Msk (0x7U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
6849#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */
6850#define DMA2D_OPFCCR_CM_0 (0x1U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
6851#define DMA2D_OPFCCR_CM_1 (0x2U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
6852#define DMA2D_OPFCCR_CM_2 (0x4U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
6853
6854/******************** Bit definition for DMA2D_OCOLR register ***************/
6855
6856/*!<Mode_ARGB8888/RGB888 */
6857
6858#define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
6859#define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
6860#define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
6861#define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
6862
6863/*!<Mode_RGB565 */
6864#define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
6865#define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
6866#define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
6867
6868/*!<Mode_ARGB1555 */
6869#define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
6870#define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
6871#define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
6872#define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
6873
6874/*!<Mode_ARGB4444 */
6875#define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
6876#define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
6877#define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
6878#define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
6879
6880/******************** Bit definition for DMA2D_OMAR register ****************/
6881
6882#define DMA2D_OMAR_MA_Pos (0U)
6883#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
6884#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */
6885
6886/******************** Bit definition for DMA2D_OOR register *****************/
6887
6888#define DMA2D_OOR_LO_Pos (0U)
6889#define DMA2D_OOR_LO_Msk (0x3FFFU << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */
6890#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */
6891
6892/******************** Bit definition for DMA2D_NLR register *****************/
6893
6894#define DMA2D_NLR_NL_Pos (0U)
6895#define DMA2D_NLR_NL_Msk (0xFFFFU << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
6896#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
6897#define DMA2D_NLR_PL_Pos (16U)
6898#define DMA2D_NLR_PL_Msk (0x3FFFU << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
6899#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
6900
6901/******************** Bit definition for DMA2D_LWR register *****************/
6902
6903#define DMA2D_LWR_LW_Pos (0U)
6904#define DMA2D_LWR_LW_Msk (0xFFFFU << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
6905#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
6906
6907/******************** Bit definition for DMA2D_AMTCR register ***************/
6908
6909#define DMA2D_AMTCR_EN_Pos (0U)
6910#define DMA2D_AMTCR_EN_Msk (0x1U << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
6911#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
6912#define DMA2D_AMTCR_DT_Pos (8U)
6913#define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
6914#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
6915
6916/******************** Bit definition for DMA2D_FGCLUT register **************/
6917
6918/******************** Bit definition for DMA2D_BGCLUT register **************/
6919
6920
6921/******************************************************************************/
6922/* */
6923/* Display Serial Interface (DSI) */
6924/* */
6925/******************************************************************************/
6926/******************* Bit definition for DSI_VR register *****************/
6927#define DSI_VR_Pos (1U)
6928#define DSI_VR_Msk (0x18999815U << DSI_VR_Pos) /*!< 0x3133302A */
6929#define DSI_VR DSI_VR_Msk /*!< DSI Host Version */
6930
6931/******************* Bit definition for DSI_CR register *****************/
6932#define DSI_CR_EN_Pos (0U)
6933#define DSI_CR_EN_Msk (0x1U << DSI_CR_EN_Pos) /*!< 0x00000001 */
6934#define DSI_CR_EN DSI_CR_EN_Msk /*!< DSI Host power up and reset */
6935
6936/******************* Bit definition for DSI_CCR register ****************/
6937#define DSI_CCR_TXECKDIV_Pos (0U)
6938#define DSI_CCR_TXECKDIV_Msk (0xFFU << DSI_CCR_TXECKDIV_Pos) /*!< 0x000000FF */
6939#define DSI_CCR_TXECKDIV DSI_CCR_TXECKDIV_Msk /*!< TX Escape Clock Division */
6940#define DSI_CCR_TXECKDIV0_Pos (0U)
6941#define DSI_CCR_TXECKDIV0_Msk (0x1U << DSI_CCR_TXECKDIV0_Pos) /*!< 0x00000001 */
6942#define DSI_CCR_TXECKDIV0 DSI_CCR_TXECKDIV0_Msk
6943#define DSI_CCR_TXECKDIV1_Pos (1U)
6944#define DSI_CCR_TXECKDIV1_Msk (0x1U << DSI_CCR_TXECKDIV1_Pos) /*!< 0x00000002 */
6945#define DSI_CCR_TXECKDIV1 DSI_CCR_TXECKDIV1_Msk
6946#define DSI_CCR_TXECKDIV2_Pos (2U)
6947#define DSI_CCR_TXECKDIV2_Msk (0x1U << DSI_CCR_TXECKDIV2_Pos) /*!< 0x00000004 */
6948#define DSI_CCR_TXECKDIV2 DSI_CCR_TXECKDIV2_Msk
6949#define DSI_CCR_TXECKDIV3_Pos (3U)
6950#define DSI_CCR_TXECKDIV3_Msk (0x1U << DSI_CCR_TXECKDIV3_Pos) /*!< 0x00000008 */
6951#define DSI_CCR_TXECKDIV3 DSI_CCR_TXECKDIV3_Msk
6952#define DSI_CCR_TXECKDIV4_Pos (4U)
6953#define DSI_CCR_TXECKDIV4_Msk (0x1U << DSI_CCR_TXECKDIV4_Pos) /*!< 0x00000010 */
6954#define DSI_CCR_TXECKDIV4 DSI_CCR_TXECKDIV4_Msk
6955#define DSI_CCR_TXECKDIV5_Pos (5U)
6956#define DSI_CCR_TXECKDIV5_Msk (0x1U << DSI_CCR_TXECKDIV5_Pos) /*!< 0x00000020 */
6957#define DSI_CCR_TXECKDIV5 DSI_CCR_TXECKDIV5_Msk
6958#define DSI_CCR_TXECKDIV6_Pos (6U)
6959#define DSI_CCR_TXECKDIV6_Msk (0x1U << DSI_CCR_TXECKDIV6_Pos) /*!< 0x00000040 */
6960#define DSI_CCR_TXECKDIV6 DSI_CCR_TXECKDIV6_Msk
6961#define DSI_CCR_TXECKDIV7_Pos (7U)
6962#define DSI_CCR_TXECKDIV7_Msk (0x1U << DSI_CCR_TXECKDIV7_Pos) /*!< 0x00000080 */
6963#define DSI_CCR_TXECKDIV7 DSI_CCR_TXECKDIV7_Msk
6964
6965#define DSI_CCR_TOCKDIV_Pos (8U)
6966#define DSI_CCR_TOCKDIV_Msk (0xFFU << DSI_CCR_TOCKDIV_Pos) /*!< 0x0000FF00 */
6967#define DSI_CCR_TOCKDIV DSI_CCR_TOCKDIV_Msk /*!< Timeout Clock Division */
6968#define DSI_CCR_TOCKDIV0_Pos (8U)
6969#define DSI_CCR_TOCKDIV0_Msk (0x1U << DSI_CCR_TOCKDIV0_Pos) /*!< 0x00000100 */
6970#define DSI_CCR_TOCKDIV0 DSI_CCR_TOCKDIV0_Msk
6971#define DSI_CCR_TOCKDIV1_Pos (9U)
6972#define DSI_CCR_TOCKDIV1_Msk (0x1U << DSI_CCR_TOCKDIV1_Pos) /*!< 0x00000200 */
6973#define DSI_CCR_TOCKDIV1 DSI_CCR_TOCKDIV1_Msk
6974#define DSI_CCR_TOCKDIV2_Pos (10U)
6975#define DSI_CCR_TOCKDIV2_Msk (0x1U << DSI_CCR_TOCKDIV2_Pos) /*!< 0x00000400 */
6976#define DSI_CCR_TOCKDIV2 DSI_CCR_TOCKDIV2_Msk
6977#define DSI_CCR_TOCKDIV3_Pos (11U)
6978#define DSI_CCR_TOCKDIV3_Msk (0x1U << DSI_CCR_TOCKDIV3_Pos) /*!< 0x00000800 */
6979#define DSI_CCR_TOCKDIV3 DSI_CCR_TOCKDIV3_Msk
6980#define DSI_CCR_TOCKDIV4_Pos (12U)
6981#define DSI_CCR_TOCKDIV4_Msk (0x1U << DSI_CCR_TOCKDIV4_Pos) /*!< 0x00001000 */
6982#define DSI_CCR_TOCKDIV4 DSI_CCR_TOCKDIV4_Msk
6983#define DSI_CCR_TOCKDIV5_Pos (13U)
6984#define DSI_CCR_TOCKDIV5_Msk (0x1U << DSI_CCR_TOCKDIV5_Pos) /*!< 0x00002000 */
6985#define DSI_CCR_TOCKDIV5 DSI_CCR_TOCKDIV5_Msk
6986#define DSI_CCR_TOCKDIV6_Pos (14U)
6987#define DSI_CCR_TOCKDIV6_Msk (0x1U << DSI_CCR_TOCKDIV6_Pos) /*!< 0x00004000 */
6988#define DSI_CCR_TOCKDIV6 DSI_CCR_TOCKDIV6_Msk
6989#define DSI_CCR_TOCKDIV7_Pos (15U)
6990#define DSI_CCR_TOCKDIV7_Msk (0x1U << DSI_CCR_TOCKDIV7_Pos) /*!< 0x00008000 */
6991#define DSI_CCR_TOCKDIV7 DSI_CCR_TOCKDIV7_Msk
6992
6993/******************* Bit definition for DSI_LVCIDR register *************/
6994#define DSI_LVCIDR_VCID_Pos (0U)
6995#define DSI_LVCIDR_VCID_Msk (0x3U << DSI_LVCIDR_VCID_Pos) /*!< 0x00000003 */
6996#define DSI_LVCIDR_VCID DSI_LVCIDR_VCID_Msk /*!< Virtual Channel ID */
6997#define DSI_LVCIDR_VCID0_Pos (0U)
6998#define DSI_LVCIDR_VCID0_Msk (0x1U << DSI_LVCIDR_VCID0_Pos) /*!< 0x00000001 */
6999#define DSI_LVCIDR_VCID0 DSI_LVCIDR_VCID0_Msk
7000#define DSI_LVCIDR_VCID1_Pos (1U)
7001#define DSI_LVCIDR_VCID1_Msk (0x1U << DSI_LVCIDR_VCID1_Pos) /*!< 0x00000002 */
7002#define DSI_LVCIDR_VCID1 DSI_LVCIDR_VCID1_Msk
7003
7004/******************* Bit definition for DSI_LCOLCR register *************/
7005#define DSI_LCOLCR_COLC_Pos (0U)
7006#define DSI_LCOLCR_COLC_Msk (0xFU << DSI_LCOLCR_COLC_Pos) /*!< 0x0000000F */
7007#define DSI_LCOLCR_COLC DSI_LCOLCR_COLC_Msk /*!< Color Coding */
7008#define DSI_LCOLCR_COLC0_Pos (0U)
7009#define DSI_LCOLCR_COLC0_Msk (0x1U << DSI_LCOLCR_COLC0_Pos) /*!< 0x00000001 */
7010#define DSI_LCOLCR_COLC0 DSI_LCOLCR_COLC0_Msk
7011#define DSI_LCOLCR_COLC1_Pos (5U)
7012#define DSI_LCOLCR_COLC1_Msk (0x1U << DSI_LCOLCR_COLC1_Pos) /*!< 0x00000020 */
7013#define DSI_LCOLCR_COLC1 DSI_LCOLCR_COLC1_Msk
7014#define DSI_LCOLCR_COLC2_Pos (6U)
7015#define DSI_LCOLCR_COLC2_Msk (0x1U << DSI_LCOLCR_COLC2_Pos) /*!< 0x00000040 */
7016#define DSI_LCOLCR_COLC2 DSI_LCOLCR_COLC2_Msk
7017#define DSI_LCOLCR_COLC3_Pos (7U)
7018#define DSI_LCOLCR_COLC3_Msk (0x1U << DSI_LCOLCR_COLC3_Pos) /*!< 0x00000080 */
7019#define DSI_LCOLCR_COLC3 DSI_LCOLCR_COLC3_Msk
7020
7021#define DSI_LCOLCR_LPE_Pos (8U)
7022#define DSI_LCOLCR_LPE_Msk (0x1U << DSI_LCOLCR_LPE_Pos) /*!< 0x00000100 */
7023#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosly Packet Enable */
7024
7025/******************* Bit definition for DSI_LPCR register ***************/
7026#define DSI_LPCR_DEP_Pos (0U)
7027#define DSI_LPCR_DEP_Msk (0x1U << DSI_LPCR_DEP_Pos) /*!< 0x00000001 */
7028#define DSI_LPCR_DEP DSI_LPCR_DEP_Msk /*!< Data Enable Polarity */
7029#define DSI_LPCR_VSP_Pos (1U)
7030#define DSI_LPCR_VSP_Msk (0x1U << DSI_LPCR_VSP_Pos) /*!< 0x00000002 */
7031#define DSI_LPCR_VSP DSI_LPCR_VSP_Msk /*!< VSYNC Polarity */
7032#define DSI_LPCR_HSP_Pos (2U)
7033#define DSI_LPCR_HSP_Msk (0x1U << DSI_LPCR_HSP_Pos) /*!< 0x00000004 */
7034#define DSI_LPCR_HSP DSI_LPCR_HSP_Msk /*!< HSYNC Polarity */
7035
7036/******************* Bit definition for DSI_LPMCR register **************/
7037#define DSI_LPMCR_VLPSIZE_Pos (0U)
7038#define DSI_LPMCR_VLPSIZE_Msk (0xFFU << DSI_LPMCR_VLPSIZE_Pos) /*!< 0x000000FF */
7039#define DSI_LPMCR_VLPSIZE DSI_LPMCR_VLPSIZE_Msk /*!< VACT Largest Packet Size */
7040#define DSI_LPMCR_VLPSIZE0_Pos (0U)
7041#define DSI_LPMCR_VLPSIZE0_Msk (0x1U << DSI_LPMCR_VLPSIZE0_Pos) /*!< 0x00000001 */
7042#define DSI_LPMCR_VLPSIZE0 DSI_LPMCR_VLPSIZE0_Msk
7043#define DSI_LPMCR_VLPSIZE1_Pos (1U)
7044#define DSI_LPMCR_VLPSIZE1_Msk (0x1U << DSI_LPMCR_VLPSIZE1_Pos) /*!< 0x00000002 */
7045#define DSI_LPMCR_VLPSIZE1 DSI_LPMCR_VLPSIZE1_Msk
7046#define DSI_LPMCR_VLPSIZE2_Pos (2U)
7047#define DSI_LPMCR_VLPSIZE2_Msk (0x1U << DSI_LPMCR_VLPSIZE2_Pos) /*!< 0x00000004 */
7048#define DSI_LPMCR_VLPSIZE2 DSI_LPMCR_VLPSIZE2_Msk
7049#define DSI_LPMCR_VLPSIZE3_Pos (3U)
7050#define DSI_LPMCR_VLPSIZE3_Msk (0x1U << DSI_LPMCR_VLPSIZE3_Pos) /*!< 0x00000008 */
7051#define DSI_LPMCR_VLPSIZE3 DSI_LPMCR_VLPSIZE3_Msk
7052#define DSI_LPMCR_VLPSIZE4_Pos (4U)
7053#define DSI_LPMCR_VLPSIZE4_Msk (0x1U << DSI_LPMCR_VLPSIZE4_Pos) /*!< 0x00000010 */
7054#define DSI_LPMCR_VLPSIZE4 DSI_LPMCR_VLPSIZE4_Msk
7055#define DSI_LPMCR_VLPSIZE5_Pos (5U)
7056#define DSI_LPMCR_VLPSIZE5_Msk (0x1U << DSI_LPMCR_VLPSIZE5_Pos) /*!< 0x00000020 */
7057#define DSI_LPMCR_VLPSIZE5 DSI_LPMCR_VLPSIZE5_Msk
7058#define DSI_LPMCR_VLPSIZE6_Pos (6U)
7059#define DSI_LPMCR_VLPSIZE6_Msk (0x1U << DSI_LPMCR_VLPSIZE6_Pos) /*!< 0x00000040 */
7060#define DSI_LPMCR_VLPSIZE6 DSI_LPMCR_VLPSIZE6_Msk
7061#define DSI_LPMCR_VLPSIZE7_Pos (7U)
7062#define DSI_LPMCR_VLPSIZE7_Msk (0x1U << DSI_LPMCR_VLPSIZE7_Pos) /*!< 0x00000080 */
7063#define DSI_LPMCR_VLPSIZE7 DSI_LPMCR_VLPSIZE7_Msk
7064
7065#define DSI_LPMCR_LPSIZE_Pos (16U)
7066#define DSI_LPMCR_LPSIZE_Msk (0xFFU << DSI_LPMCR_LPSIZE_Pos) /*!< 0x00FF0000 */
7067#define DSI_LPMCR_LPSIZE DSI_LPMCR_LPSIZE_Msk /*!< Largest Packet Size */
7068#define DSI_LPMCR_LPSIZE0_Pos (16U)
7069#define DSI_LPMCR_LPSIZE0_Msk (0x1U << DSI_LPMCR_LPSIZE0_Pos) /*!< 0x00010000 */
7070#define DSI_LPMCR_LPSIZE0 DSI_LPMCR_LPSIZE0_Msk
7071#define DSI_LPMCR_LPSIZE1_Pos (17U)
7072#define DSI_LPMCR_LPSIZE1_Msk (0x1U << DSI_LPMCR_LPSIZE1_Pos) /*!< 0x00020000 */
7073#define DSI_LPMCR_LPSIZE1 DSI_LPMCR_LPSIZE1_Msk
7074#define DSI_LPMCR_LPSIZE2_Pos (18U)
7075#define DSI_LPMCR_LPSIZE2_Msk (0x1U << DSI_LPMCR_LPSIZE2_Pos) /*!< 0x00040000 */
7076#define DSI_LPMCR_LPSIZE2 DSI_LPMCR_LPSIZE2_Msk
7077#define DSI_LPMCR_LPSIZE3_Pos (19U)
7078#define DSI_LPMCR_LPSIZE3_Msk (0x1U << DSI_LPMCR_LPSIZE3_Pos) /*!< 0x00080000 */
7079#define DSI_LPMCR_LPSIZE3 DSI_LPMCR_LPSIZE3_Msk
7080#define DSI_LPMCR_LPSIZE4_Pos (20U)
7081#define DSI_LPMCR_LPSIZE4_Msk (0x1U << DSI_LPMCR_LPSIZE4_Pos) /*!< 0x00100000 */
7082#define DSI_LPMCR_LPSIZE4 DSI_LPMCR_LPSIZE4_Msk
7083#define DSI_LPMCR_LPSIZE5_Pos (21U)
7084#define DSI_LPMCR_LPSIZE5_Msk (0x1U << DSI_LPMCR_LPSIZE5_Pos) /*!< 0x00200000 */
7085#define DSI_LPMCR_LPSIZE5 DSI_LPMCR_LPSIZE5_Msk
7086#define DSI_LPMCR_LPSIZE6_Pos (22U)
7087#define DSI_LPMCR_LPSIZE6_Msk (0x1U << DSI_LPMCR_LPSIZE6_Pos) /*!< 0x00400000 */
7088#define DSI_LPMCR_LPSIZE6 DSI_LPMCR_LPSIZE6_Msk
7089#define DSI_LPMCR_LPSIZE7_Pos (23U)
7090#define DSI_LPMCR_LPSIZE7_Msk (0x1U << DSI_LPMCR_LPSIZE7_Pos) /*!< 0x00800000 */
7091#define DSI_LPMCR_LPSIZE7 DSI_LPMCR_LPSIZE7_Msk
7092
7093/******************* Bit definition for DSI_PCR register ****************/
7094#define DSI_PCR_ETTXE_Pos (0U)
7095#define DSI_PCR_ETTXE_Msk (0x1U << DSI_PCR_ETTXE_Pos) /*!< 0x00000001 */
7096#define DSI_PCR_ETTXE DSI_PCR_ETTXE_Msk /*!< EoTp Transmission Enable */
7097#define DSI_PCR_ETRXE_Pos (1U)
7098#define DSI_PCR_ETRXE_Msk (0x1U << DSI_PCR_ETRXE_Pos) /*!< 0x00000002 */
7099#define DSI_PCR_ETRXE DSI_PCR_ETRXE_Msk /*!< EoTp Reception Enable */
7100#define DSI_PCR_BTAE_Pos (2U)
7101#define DSI_PCR_BTAE_Msk (0x1U << DSI_PCR_BTAE_Pos) /*!< 0x00000004 */
7102#define DSI_PCR_BTAE DSI_PCR_BTAE_Msk /*!< Bus Turn Around Enable */
7103#define DSI_PCR_ECCRXE_Pos (3U)
7104#define DSI_PCR_ECCRXE_Msk (0x1U << DSI_PCR_ECCRXE_Pos) /*!< 0x00000008 */
7105#define DSI_PCR_ECCRXE DSI_PCR_ECCRXE_Msk /*!< ECC Reception Enable */
7106#define DSI_PCR_CRCRXE_Pos (4U)
7107#define DSI_PCR_CRCRXE_Msk (0x1U << DSI_PCR_CRCRXE_Pos) /*!< 0x00000010 */
7108#define DSI_PCR_CRCRXE DSI_PCR_CRCRXE_Msk /*!< CRC Reception Enable */
7109
7110/******************* Bit definition for DSI_GVCIDR register *************/
7111#define DSI_GVCIDR_VCID_Pos (0U)
7112#define DSI_GVCIDR_VCID_Msk (0x3U << DSI_GVCIDR_VCID_Pos) /*!< 0x00000003 */
7113#define DSI_GVCIDR_VCID DSI_GVCIDR_VCID_Msk /*!< Virtual Channel ID */
7114#define DSI_GVCIDR_VCID0_Pos (0U)
7115#define DSI_GVCIDR_VCID0_Msk (0x1U << DSI_GVCIDR_VCID0_Pos) /*!< 0x00000001 */
7116#define DSI_GVCIDR_VCID0 DSI_GVCIDR_VCID0_Msk
7117#define DSI_GVCIDR_VCID1_Pos (1U)
7118#define DSI_GVCIDR_VCID1_Msk (0x1U << DSI_GVCIDR_VCID1_Pos) /*!< 0x00000002 */
7119#define DSI_GVCIDR_VCID1 DSI_GVCIDR_VCID1_Msk
7120
7121/******************* Bit definition for DSI_MCR register ****************/
7122#define DSI_MCR_CMDM_Pos (0U)
7123#define DSI_MCR_CMDM_Msk (0x1U << DSI_MCR_CMDM_Pos) /*!< 0x00000001 */
7124#define DSI_MCR_CMDM DSI_MCR_CMDM_Msk /*!< Command Mode */
7125
7126/******************* Bit definition for DSI_VMCR register ***************/
7127#define DSI_VMCR_VMT_Pos (0U)
7128#define DSI_VMCR_VMT_Msk (0x3U << DSI_VMCR_VMT_Pos) /*!< 0x00000003 */
7129#define DSI_VMCR_VMT DSI_VMCR_VMT_Msk /*!< Video Mode Type */
7130#define DSI_VMCR_VMT0_Pos (0U)
7131#define DSI_VMCR_VMT0_Msk (0x1U << DSI_VMCR_VMT0_Pos) /*!< 0x00000001 */
7132#define DSI_VMCR_VMT0 DSI_VMCR_VMT0_Msk
7133#define DSI_VMCR_VMT1_Pos (1U)
7134#define DSI_VMCR_VMT1_Msk (0x1U << DSI_VMCR_VMT1_Pos) /*!< 0x00000002 */
7135#define DSI_VMCR_VMT1 DSI_VMCR_VMT1_Msk
7136
7137#define DSI_VMCR_LPVSAE_Pos (8U)
7138#define DSI_VMCR_LPVSAE_Msk (0x1U << DSI_VMCR_LPVSAE_Pos) /*!< 0x00000100 */
7139#define DSI_VMCR_LPVSAE DSI_VMCR_LPVSAE_Msk /*!< Low-Power Vertical Sync Active Enable */
7140#define DSI_VMCR_LPVBPE_Pos (9U)
7141#define DSI_VMCR_LPVBPE_Msk (0x1U << DSI_VMCR_LPVBPE_Pos) /*!< 0x00000200 */
7142#define DSI_VMCR_LPVBPE DSI_VMCR_LPVBPE_Msk /*!< Low-power Vertical Back-Porch Enable */
7143#define DSI_VMCR_LPVFPE_Pos (10U)
7144#define DSI_VMCR_LPVFPE_Msk (0x1U << DSI_VMCR_LPVFPE_Pos) /*!< 0x00000400 */
7145#define DSI_VMCR_LPVFPE DSI_VMCR_LPVFPE_Msk /*!< Low-power Vertical Front-porch Enable */
7146#define DSI_VMCR_LPVAE_Pos (11U)
7147#define DSI_VMCR_LPVAE_Msk (0x1U << DSI_VMCR_LPVAE_Pos) /*!< 0x00000800 */
7148#define DSI_VMCR_LPVAE DSI_VMCR_LPVAE_Msk /*!< Low-Power Vertical Active Enable */
7149#define DSI_VMCR_LPHBPE_Pos (12U)
7150#define DSI_VMCR_LPHBPE_Msk (0x1U << DSI_VMCR_LPHBPE_Pos) /*!< 0x00001000 */
7151#define DSI_VMCR_LPHBPE DSI_VMCR_LPHBPE_Msk /*!< Low-Power Horizontal Back-Porch Enable */
7152#define DSI_VMCR_LPHFPE_Pos (13U)
7153#define DSI_VMCR_LPHFPE_Msk (0x1U << DSI_VMCR_LPHFPE_Pos) /*!< 0x00002000 */
7154#define DSI_VMCR_LPHFPE DSI_VMCR_LPHFPE_Msk /*!< Low-Power Horizontal Front-Porch Enable */
7155#define DSI_VMCR_FBTAAE_Pos (14U)
7156#define DSI_VMCR_FBTAAE_Msk (0x1U << DSI_VMCR_FBTAAE_Pos) /*!< 0x00004000 */
7157#define DSI_VMCR_FBTAAE DSI_VMCR_FBTAAE_Msk /*!< Frame Bus-Turn-Around Acknowledge Enable */
7158#define DSI_VMCR_LPCE_Pos (15U)
7159#define DSI_VMCR_LPCE_Msk (0x1U << DSI_VMCR_LPCE_Pos) /*!< 0x00008000 */
7160#define DSI_VMCR_LPCE DSI_VMCR_LPCE_Msk /*!< Low-Power Command Enable */
7161#define DSI_VMCR_PGE_Pos (16U)
7162#define DSI_VMCR_PGE_Msk (0x1U << DSI_VMCR_PGE_Pos) /*!< 0x00010000 */
7163#define DSI_VMCR_PGE DSI_VMCR_PGE_Msk /*!< Pattern Generator Enable */
7164#define DSI_VMCR_PGM_Pos (20U)
7165#define DSI_VMCR_PGM_Msk (0x1U << DSI_VMCR_PGM_Pos) /*!< 0x00100000 */
7166#define DSI_VMCR_PGM DSI_VMCR_PGM_Msk /*!< Pattern Generator Mode */
7167#define DSI_VMCR_PGO_Pos (24U)
7168#define DSI_VMCR_PGO_Msk (0x1U << DSI_VMCR_PGO_Pos) /*!< 0x01000000 */
7169#define DSI_VMCR_PGO DSI_VMCR_PGO_Msk /*!< Pattern Generator Orientation */
7170
7171/******************* Bit definition for DSI_VPCR register ***************/
7172#define DSI_VPCR_VPSIZE_Pos (0U)
7173#define DSI_VPCR_VPSIZE_Msk (0x3FFFU << DSI_VPCR_VPSIZE_Pos) /*!< 0x00003FFF */
7174#define DSI_VPCR_VPSIZE DSI_VPCR_VPSIZE_Msk /*!< Video Packet Size */
7175#define DSI_VPCR_VPSIZE0_Pos (0U)
7176#define DSI_VPCR_VPSIZE0_Msk (0x1U << DSI_VPCR_VPSIZE0_Pos) /*!< 0x00000001 */
7177#define DSI_VPCR_VPSIZE0 DSI_VPCR_VPSIZE0_Msk
7178#define DSI_VPCR_VPSIZE1_Pos (1U)
7179#define DSI_VPCR_VPSIZE1_Msk (0x1U << DSI_VPCR_VPSIZE1_Pos) /*!< 0x00000002 */
7180#define DSI_VPCR_VPSIZE1 DSI_VPCR_VPSIZE1_Msk
7181#define DSI_VPCR_VPSIZE2_Pos (2U)
7182#define DSI_VPCR_VPSIZE2_Msk (0x1U << DSI_VPCR_VPSIZE2_Pos) /*!< 0x00000004 */
7183#define DSI_VPCR_VPSIZE2 DSI_VPCR_VPSIZE2_Msk
7184#define DSI_VPCR_VPSIZE3_Pos (3U)
7185#define DSI_VPCR_VPSIZE3_Msk (0x1U << DSI_VPCR_VPSIZE3_Pos) /*!< 0x00000008 */
7186#define DSI_VPCR_VPSIZE3 DSI_VPCR_VPSIZE3_Msk
7187#define DSI_VPCR_VPSIZE4_Pos (4U)
7188#define DSI_VPCR_VPSIZE4_Msk (0x1U << DSI_VPCR_VPSIZE4_Pos) /*!< 0x00000010 */
7189#define DSI_VPCR_VPSIZE4 DSI_VPCR_VPSIZE4_Msk
7190#define DSI_VPCR_VPSIZE5_Pos (5U)
7191#define DSI_VPCR_VPSIZE5_Msk (0x1U << DSI_VPCR_VPSIZE5_Pos) /*!< 0x00000020 */
7192#define DSI_VPCR_VPSIZE5 DSI_VPCR_VPSIZE5_Msk
7193#define DSI_VPCR_VPSIZE6_Pos (6U)
7194#define DSI_VPCR_VPSIZE6_Msk (0x1U << DSI_VPCR_VPSIZE6_Pos) /*!< 0x00000040 */
7195#define DSI_VPCR_VPSIZE6 DSI_VPCR_VPSIZE6_Msk
7196#define DSI_VPCR_VPSIZE7_Pos (7U)
7197#define DSI_VPCR_VPSIZE7_Msk (0x1U << DSI_VPCR_VPSIZE7_Pos) /*!< 0x00000080 */
7198#define DSI_VPCR_VPSIZE7 DSI_VPCR_VPSIZE7_Msk
7199#define DSI_VPCR_VPSIZE8_Pos (8U)
7200#define DSI_VPCR_VPSIZE8_Msk (0x1U << DSI_VPCR_VPSIZE8_Pos) /*!< 0x00000100 */
7201#define DSI_VPCR_VPSIZE8 DSI_VPCR_VPSIZE8_Msk
7202#define DSI_VPCR_VPSIZE9_Pos (9U)
7203#define DSI_VPCR_VPSIZE9_Msk (0x1U << DSI_VPCR_VPSIZE9_Pos) /*!< 0x00000200 */
7204#define DSI_VPCR_VPSIZE9 DSI_VPCR_VPSIZE9_Msk
7205#define DSI_VPCR_VPSIZE10_Pos (10U)
7206#define DSI_VPCR_VPSIZE10_Msk (0x1U << DSI_VPCR_VPSIZE10_Pos) /*!< 0x00000400 */
7207#define DSI_VPCR_VPSIZE10 DSI_VPCR_VPSIZE10_Msk
7208#define DSI_VPCR_VPSIZE11_Pos (11U)
7209#define DSI_VPCR_VPSIZE11_Msk (0x1U << DSI_VPCR_VPSIZE11_Pos) /*!< 0x00000800 */
7210#define DSI_VPCR_VPSIZE11 DSI_VPCR_VPSIZE11_Msk
7211#define DSI_VPCR_VPSIZE12_Pos (12U)
7212#define DSI_VPCR_VPSIZE12_Msk (0x1U << DSI_VPCR_VPSIZE12_Pos) /*!< 0x00001000 */
7213#define DSI_VPCR_VPSIZE12 DSI_VPCR_VPSIZE12_Msk
7214#define DSI_VPCR_VPSIZE13_Pos (13U)
7215#define DSI_VPCR_VPSIZE13_Msk (0x1U << DSI_VPCR_VPSIZE13_Pos) /*!< 0x00002000 */
7216#define DSI_VPCR_VPSIZE13 DSI_VPCR_VPSIZE13_Msk
7217
7218/******************* Bit definition for DSI_VCCR register ***************/
7219#define DSI_VCCR_NUMC_Pos (0U)
7220#define DSI_VCCR_NUMC_Msk (0x1FFFU << DSI_VCCR_NUMC_Pos) /*!< 0x00001FFF */
7221#define DSI_VCCR_NUMC DSI_VCCR_NUMC_Msk /*!< Number of Chunks */
7222#define DSI_VCCR_NUMC0_Pos (0U)
7223#define DSI_VCCR_NUMC0_Msk (0x1U << DSI_VCCR_NUMC0_Pos) /*!< 0x00000001 */
7224#define DSI_VCCR_NUMC0 DSI_VCCR_NUMC0_Msk
7225#define DSI_VCCR_NUMC1_Pos (1U)
7226#define DSI_VCCR_NUMC1_Msk (0x1U << DSI_VCCR_NUMC1_Pos) /*!< 0x00000002 */
7227#define DSI_VCCR_NUMC1 DSI_VCCR_NUMC1_Msk
7228#define DSI_VCCR_NUMC2_Pos (2U)
7229#define DSI_VCCR_NUMC2_Msk (0x1U << DSI_VCCR_NUMC2_Pos) /*!< 0x00000004 */
7230#define DSI_VCCR_NUMC2 DSI_VCCR_NUMC2_Msk
7231#define DSI_VCCR_NUMC3_Pos (3U)
7232#define DSI_VCCR_NUMC3_Msk (0x1U << DSI_VCCR_NUMC3_Pos) /*!< 0x00000008 */
7233#define DSI_VCCR_NUMC3 DSI_VCCR_NUMC3_Msk
7234#define DSI_VCCR_NUMC4_Pos (4U)
7235#define DSI_VCCR_NUMC4_Msk (0x1U << DSI_VCCR_NUMC4_Pos) /*!< 0x00000010 */
7236#define DSI_VCCR_NUMC4 DSI_VCCR_NUMC4_Msk
7237#define DSI_VCCR_NUMC5_Pos (5U)
7238#define DSI_VCCR_NUMC5_Msk (0x1U << DSI_VCCR_NUMC5_Pos) /*!< 0x00000020 */
7239#define DSI_VCCR_NUMC5 DSI_VCCR_NUMC5_Msk
7240#define DSI_VCCR_NUMC6_Pos (6U)
7241#define DSI_VCCR_NUMC6_Msk (0x1U << DSI_VCCR_NUMC6_Pos) /*!< 0x00000040 */
7242#define DSI_VCCR_NUMC6 DSI_VCCR_NUMC6_Msk
7243#define DSI_VCCR_NUMC7_Pos (7U)
7244#define DSI_VCCR_NUMC7_Msk (0x1U << DSI_VCCR_NUMC7_Pos) /*!< 0x00000080 */
7245#define DSI_VCCR_NUMC7 DSI_VCCR_NUMC7_Msk
7246#define DSI_VCCR_NUMC8_Pos (8U)
7247#define DSI_VCCR_NUMC8_Msk (0x1U << DSI_VCCR_NUMC8_Pos) /*!< 0x00000100 */
7248#define DSI_VCCR_NUMC8 DSI_VCCR_NUMC8_Msk
7249#define DSI_VCCR_NUMC9_Pos (9U)
7250#define DSI_VCCR_NUMC9_Msk (0x1U << DSI_VCCR_NUMC9_Pos) /*!< 0x00000200 */
7251#define DSI_VCCR_NUMC9 DSI_VCCR_NUMC9_Msk
7252#define DSI_VCCR_NUMC10_Pos (10U)
7253#define DSI_VCCR_NUMC10_Msk (0x1U << DSI_VCCR_NUMC10_Pos) /*!< 0x00000400 */
7254#define DSI_VCCR_NUMC10 DSI_VCCR_NUMC10_Msk
7255#define DSI_VCCR_NUMC11_Pos (11U)
7256#define DSI_VCCR_NUMC11_Msk (0x1U << DSI_VCCR_NUMC11_Pos) /*!< 0x00000800 */
7257#define DSI_VCCR_NUMC11 DSI_VCCR_NUMC11_Msk
7258#define DSI_VCCR_NUMC12_Pos (12U)
7259#define DSI_VCCR_NUMC12_Msk (0x1U << DSI_VCCR_NUMC12_Pos) /*!< 0x00001000 */
7260#define DSI_VCCR_NUMC12 DSI_VCCR_NUMC12_Msk
7261
7262/******************* Bit definition for DSI_VNPCR register **************/
7263#define DSI_VNPCR_NPSIZE_Pos (0U)
7264#define DSI_VNPCR_NPSIZE_Msk (0x1FFFU << DSI_VNPCR_NPSIZE_Pos) /*!< 0x00001FFF */
7265#define DSI_VNPCR_NPSIZE DSI_VNPCR_NPSIZE_Msk /*!< Null Packet Size */
7266#define DSI_VNPCR_NPSIZE0_Pos (0U)
7267#define DSI_VNPCR_NPSIZE0_Msk (0x1U << DSI_VNPCR_NPSIZE0_Pos) /*!< 0x00000001 */
7268#define DSI_VNPCR_NPSIZE0 DSI_VNPCR_NPSIZE0_Msk
7269#define DSI_VNPCR_NPSIZE1_Pos (1U)
7270#define DSI_VNPCR_NPSIZE1_Msk (0x1U << DSI_VNPCR_NPSIZE1_Pos) /*!< 0x00000002 */
7271#define DSI_VNPCR_NPSIZE1 DSI_VNPCR_NPSIZE1_Msk
7272#define DSI_VNPCR_NPSIZE2_Pos (2U)
7273#define DSI_VNPCR_NPSIZE2_Msk (0x1U << DSI_VNPCR_NPSIZE2_Pos) /*!< 0x00000004 */
7274#define DSI_VNPCR_NPSIZE2 DSI_VNPCR_NPSIZE2_Msk
7275#define DSI_VNPCR_NPSIZE3_Pos (3U)
7276#define DSI_VNPCR_NPSIZE3_Msk (0x1U << DSI_VNPCR_NPSIZE3_Pos) /*!< 0x00000008 */
7277#define DSI_VNPCR_NPSIZE3 DSI_VNPCR_NPSIZE3_Msk
7278#define DSI_VNPCR_NPSIZE4_Pos (4U)
7279#define DSI_VNPCR_NPSIZE4_Msk (0x1U << DSI_VNPCR_NPSIZE4_Pos) /*!< 0x00000010 */
7280#define DSI_VNPCR_NPSIZE4 DSI_VNPCR_NPSIZE4_Msk
7281#define DSI_VNPCR_NPSIZE5_Pos (5U)
7282#define DSI_VNPCR_NPSIZE5_Msk (0x1U << DSI_VNPCR_NPSIZE5_Pos) /*!< 0x00000020 */
7283#define DSI_VNPCR_NPSIZE5 DSI_VNPCR_NPSIZE5_Msk
7284#define DSI_VNPCR_NPSIZE6_Pos (6U)
7285#define DSI_VNPCR_NPSIZE6_Msk (0x1U << DSI_VNPCR_NPSIZE6_Pos) /*!< 0x00000040 */
7286#define DSI_VNPCR_NPSIZE6 DSI_VNPCR_NPSIZE6_Msk
7287#define DSI_VNPCR_NPSIZE7_Pos (7U)
7288#define DSI_VNPCR_NPSIZE7_Msk (0x1U << DSI_VNPCR_NPSIZE7_Pos) /*!< 0x00000080 */
7289#define DSI_VNPCR_NPSIZE7 DSI_VNPCR_NPSIZE7_Msk
7290#define DSI_VNPCR_NPSIZE8_Pos (8U)
7291#define DSI_VNPCR_NPSIZE8_Msk (0x1U << DSI_VNPCR_NPSIZE8_Pos) /*!< 0x00000100 */
7292#define DSI_VNPCR_NPSIZE8 DSI_VNPCR_NPSIZE8_Msk
7293#define DSI_VNPCR_NPSIZE9_Pos (9U)
7294#define DSI_VNPCR_NPSIZE9_Msk (0x1U << DSI_VNPCR_NPSIZE9_Pos) /*!< 0x00000200 */
7295#define DSI_VNPCR_NPSIZE9 DSI_VNPCR_NPSIZE9_Msk
7296#define DSI_VNPCR_NPSIZE10_Pos (10U)
7297#define DSI_VNPCR_NPSIZE10_Msk (0x1U << DSI_VNPCR_NPSIZE10_Pos) /*!< 0x00000400 */
7298#define DSI_VNPCR_NPSIZE10 DSI_VNPCR_NPSIZE10_Msk
7299#define DSI_VNPCR_NPSIZE11_Pos (11U)
7300#define DSI_VNPCR_NPSIZE11_Msk (0x1U << DSI_VNPCR_NPSIZE11_Pos) /*!< 0x00000800 */
7301#define DSI_VNPCR_NPSIZE11 DSI_VNPCR_NPSIZE11_Msk
7302#define DSI_VNPCR_NPSIZE12_Pos (12U)
7303#define DSI_VNPCR_NPSIZE12_Msk (0x1U << DSI_VNPCR_NPSIZE12_Pos) /*!< 0x00001000 */
7304#define DSI_VNPCR_NPSIZE12 DSI_VNPCR_NPSIZE12_Msk
7305
7306/******************* Bit definition for DSI_VHSACR register *************/
7307#define DSI_VHSACR_HSA_Pos (0U)
7308#define DSI_VHSACR_HSA_Msk (0xFFFU << DSI_VHSACR_HSA_Pos) /*!< 0x00000FFF */
7309#define DSI_VHSACR_HSA DSI_VHSACR_HSA_Msk /*!< Horizontal Synchronism Active duration */
7310#define DSI_VHSACR_HSA0_Pos (0U)
7311#define DSI_VHSACR_HSA0_Msk (0x1U << DSI_VHSACR_HSA0_Pos) /*!< 0x00000001 */
7312#define DSI_VHSACR_HSA0 DSI_VHSACR_HSA0_Msk
7313#define DSI_VHSACR_HSA1_Pos (1U)
7314#define DSI_VHSACR_HSA1_Msk (0x1U << DSI_VHSACR_HSA1_Pos) /*!< 0x00000002 */
7315#define DSI_VHSACR_HSA1 DSI_VHSACR_HSA1_Msk
7316#define DSI_VHSACR_HSA2_Pos (2U)
7317#define DSI_VHSACR_HSA2_Msk (0x1U << DSI_VHSACR_HSA2_Pos) /*!< 0x00000004 */
7318#define DSI_VHSACR_HSA2 DSI_VHSACR_HSA2_Msk
7319#define DSI_VHSACR_HSA3_Pos (3U)
7320#define DSI_VHSACR_HSA3_Msk (0x1U << DSI_VHSACR_HSA3_Pos) /*!< 0x00000008 */
7321#define DSI_VHSACR_HSA3 DSI_VHSACR_HSA3_Msk
7322#define DSI_VHSACR_HSA4_Pos (4U)
7323#define DSI_VHSACR_HSA4_Msk (0x1U << DSI_VHSACR_HSA4_Pos) /*!< 0x00000010 */
7324#define DSI_VHSACR_HSA4 DSI_VHSACR_HSA4_Msk
7325#define DSI_VHSACR_HSA5_Pos (5U)
7326#define DSI_VHSACR_HSA5_Msk (0x1U << DSI_VHSACR_HSA5_Pos) /*!< 0x00000020 */
7327#define DSI_VHSACR_HSA5 DSI_VHSACR_HSA5_Msk
7328#define DSI_VHSACR_HSA6_Pos (6U)
7329#define DSI_VHSACR_HSA6_Msk (0x1U << DSI_VHSACR_HSA6_Pos) /*!< 0x00000040 */
7330#define DSI_VHSACR_HSA6 DSI_VHSACR_HSA6_Msk
7331#define DSI_VHSACR_HSA7_Pos (7U)
7332#define DSI_VHSACR_HSA7_Msk (0x1U << DSI_VHSACR_HSA7_Pos) /*!< 0x00000080 */
7333#define DSI_VHSACR_HSA7 DSI_VHSACR_HSA7_Msk
7334#define DSI_VHSACR_HSA8_Pos (8U)
7335#define DSI_VHSACR_HSA8_Msk (0x1U << DSI_VHSACR_HSA8_Pos) /*!< 0x00000100 */
7336#define DSI_VHSACR_HSA8 DSI_VHSACR_HSA8_Msk
7337#define DSI_VHSACR_HSA9_Pos (9U)
7338#define DSI_VHSACR_HSA9_Msk (0x1U << DSI_VHSACR_HSA9_Pos) /*!< 0x00000200 */
7339#define DSI_VHSACR_HSA9 DSI_VHSACR_HSA9_Msk
7340#define DSI_VHSACR_HSA10_Pos (10U)
7341#define DSI_VHSACR_HSA10_Msk (0x1U << DSI_VHSACR_HSA10_Pos) /*!< 0x00000400 */
7342#define DSI_VHSACR_HSA10 DSI_VHSACR_HSA10_Msk
7343#define DSI_VHSACR_HSA11_Pos (11U)
7344#define DSI_VHSACR_HSA11_Msk (0x1U << DSI_VHSACR_HSA11_Pos) /*!< 0x00000800 */
7345#define DSI_VHSACR_HSA11 DSI_VHSACR_HSA11_Msk
7346
7347/******************* Bit definition for DSI_VHBPCR register *************/
7348#define DSI_VHBPCR_HBP_Pos (0U)
7349#define DSI_VHBPCR_HBP_Msk (0xFFFU << DSI_VHBPCR_HBP_Pos) /*!< 0x00000FFF */
7350#define DSI_VHBPCR_HBP DSI_VHBPCR_HBP_Msk /*!< Horizontal Back-Porch duration */
7351#define DSI_VHBPCR_HBP0_Pos (0U)
7352#define DSI_VHBPCR_HBP0_Msk (0x1U << DSI_VHBPCR_HBP0_Pos) /*!< 0x00000001 */
7353#define DSI_VHBPCR_HBP0 DSI_VHBPCR_HBP0_Msk
7354#define DSI_VHBPCR_HBP1_Pos (1U)
7355#define DSI_VHBPCR_HBP1_Msk (0x1U << DSI_VHBPCR_HBP1_Pos) /*!< 0x00000002 */
7356#define DSI_VHBPCR_HBP1 DSI_VHBPCR_HBP1_Msk
7357#define DSI_VHBPCR_HBP2_Pos (2U)
7358#define DSI_VHBPCR_HBP2_Msk (0x1U << DSI_VHBPCR_HBP2_Pos) /*!< 0x00000004 */
7359#define DSI_VHBPCR_HBP2 DSI_VHBPCR_HBP2_Msk
7360#define DSI_VHBPCR_HBP3_Pos (3U)
7361#define DSI_VHBPCR_HBP3_Msk (0x1U << DSI_VHBPCR_HBP3_Pos) /*!< 0x00000008 */
7362#define DSI_VHBPCR_HBP3 DSI_VHBPCR_HBP3_Msk
7363#define DSI_VHBPCR_HBP4_Pos (4U)
7364#define DSI_VHBPCR_HBP4_Msk (0x1U << DSI_VHBPCR_HBP4_Pos) /*!< 0x00000010 */
7365#define DSI_VHBPCR_HBP4 DSI_VHBPCR_HBP4_Msk
7366#define DSI_VHBPCR_HBP5_Pos (5U)
7367#define DSI_VHBPCR_HBP5_Msk (0x1U << DSI_VHBPCR_HBP5_Pos) /*!< 0x00000020 */
7368#define DSI_VHBPCR_HBP5 DSI_VHBPCR_HBP5_Msk
7369#define DSI_VHBPCR_HBP6_Pos (6U)
7370#define DSI_VHBPCR_HBP6_Msk (0x1U << DSI_VHBPCR_HBP6_Pos) /*!< 0x00000040 */
7371#define DSI_VHBPCR_HBP6 DSI_VHBPCR_HBP6_Msk
7372#define DSI_VHBPCR_HBP7_Pos (7U)
7373#define DSI_VHBPCR_HBP7_Msk (0x1U << DSI_VHBPCR_HBP7_Pos) /*!< 0x00000080 */
7374#define DSI_VHBPCR_HBP7 DSI_VHBPCR_HBP7_Msk
7375#define DSI_VHBPCR_HBP8_Pos (8U)
7376#define DSI_VHBPCR_HBP8_Msk (0x1U << DSI_VHBPCR_HBP8_Pos) /*!< 0x00000100 */
7377#define DSI_VHBPCR_HBP8 DSI_VHBPCR_HBP8_Msk
7378#define DSI_VHBPCR_HBP9_Pos (9U)
7379#define DSI_VHBPCR_HBP9_Msk (0x1U << DSI_VHBPCR_HBP9_Pos) /*!< 0x00000200 */
7380#define DSI_VHBPCR_HBP9 DSI_VHBPCR_HBP9_Msk
7381#define DSI_VHBPCR_HBP10_Pos (10U)
7382#define DSI_VHBPCR_HBP10_Msk (0x1U << DSI_VHBPCR_HBP10_Pos) /*!< 0x00000400 */
7383#define DSI_VHBPCR_HBP10 DSI_VHBPCR_HBP10_Msk
7384#define DSI_VHBPCR_HBP11_Pos (11U)
7385#define DSI_VHBPCR_HBP11_Msk (0x1U << DSI_VHBPCR_HBP11_Pos) /*!< 0x00000800 */
7386#define DSI_VHBPCR_HBP11 DSI_VHBPCR_HBP11_Msk
7387
7388/******************* Bit definition for DSI_VLCR register ***************/
7389#define DSI_VLCR_HLINE_Pos (0U)
7390#define DSI_VLCR_HLINE_Msk (0x7FFFU << DSI_VLCR_HLINE_Pos) /*!< 0x00007FFF */
7391#define DSI_VLCR_HLINE DSI_VLCR_HLINE_Msk /*!< Horizontal Line duration */
7392#define DSI_VLCR_HLINE0_Pos (0U)
7393#define DSI_VLCR_HLINE0_Msk (0x1U << DSI_VLCR_HLINE0_Pos) /*!< 0x00000001 */
7394#define DSI_VLCR_HLINE0 DSI_VLCR_HLINE0_Msk
7395#define DSI_VLCR_HLINE1_Pos (1U)
7396#define DSI_VLCR_HLINE1_Msk (0x1U << DSI_VLCR_HLINE1_Pos) /*!< 0x00000002 */
7397#define DSI_VLCR_HLINE1 DSI_VLCR_HLINE1_Msk
7398#define DSI_VLCR_HLINE2_Pos (2U)
7399#define DSI_VLCR_HLINE2_Msk (0x1U << DSI_VLCR_HLINE2_Pos) /*!< 0x00000004 */
7400#define DSI_VLCR_HLINE2 DSI_VLCR_HLINE2_Msk
7401#define DSI_VLCR_HLINE3_Pos (3U)
7402#define DSI_VLCR_HLINE3_Msk (0x1U << DSI_VLCR_HLINE3_Pos) /*!< 0x00000008 */
7403#define DSI_VLCR_HLINE3 DSI_VLCR_HLINE3_Msk
7404#define DSI_VLCR_HLINE4_Pos (4U)
7405#define DSI_VLCR_HLINE4_Msk (0x1U << DSI_VLCR_HLINE4_Pos) /*!< 0x00000010 */
7406#define DSI_VLCR_HLINE4 DSI_VLCR_HLINE4_Msk
7407#define DSI_VLCR_HLINE5_Pos (5U)
7408#define DSI_VLCR_HLINE5_Msk (0x1U << DSI_VLCR_HLINE5_Pos) /*!< 0x00000020 */
7409#define DSI_VLCR_HLINE5 DSI_VLCR_HLINE5_Msk
7410#define DSI_VLCR_HLINE6_Pos (6U)
7411#define DSI_VLCR_HLINE6_Msk (0x1U << DSI_VLCR_HLINE6_Pos) /*!< 0x00000040 */
7412#define DSI_VLCR_HLINE6 DSI_VLCR_HLINE6_Msk
7413#define DSI_VLCR_HLINE7_Pos (7U)
7414#define DSI_VLCR_HLINE7_Msk (0x1U << DSI_VLCR_HLINE7_Pos) /*!< 0x00000080 */
7415#define DSI_VLCR_HLINE7 DSI_VLCR_HLINE7_Msk
7416#define DSI_VLCR_HLINE8_Pos (8U)
7417#define DSI_VLCR_HLINE8_Msk (0x1U << DSI_VLCR_HLINE8_Pos) /*!< 0x00000100 */
7418#define DSI_VLCR_HLINE8 DSI_VLCR_HLINE8_Msk
7419#define DSI_VLCR_HLINE9_Pos (9U)
7420#define DSI_VLCR_HLINE9_Msk (0x1U << DSI_VLCR_HLINE9_Pos) /*!< 0x00000200 */
7421#define DSI_VLCR_HLINE9 DSI_VLCR_HLINE9_Msk
7422#define DSI_VLCR_HLINE10_Pos (10U)
7423#define DSI_VLCR_HLINE10_Msk (0x1U << DSI_VLCR_HLINE10_Pos) /*!< 0x00000400 */
7424#define DSI_VLCR_HLINE10 DSI_VLCR_HLINE10_Msk
7425#define DSI_VLCR_HLINE11_Pos (11U)
7426#define DSI_VLCR_HLINE11_Msk (0x1U << DSI_VLCR_HLINE11_Pos) /*!< 0x00000800 */
7427#define DSI_VLCR_HLINE11 DSI_VLCR_HLINE11_Msk
7428#define DSI_VLCR_HLINE12_Pos (12U)
7429#define DSI_VLCR_HLINE12_Msk (0x1U << DSI_VLCR_HLINE12_Pos) /*!< 0x00001000 */
7430#define DSI_VLCR_HLINE12 DSI_VLCR_HLINE12_Msk
7431#define DSI_VLCR_HLINE13_Pos (13U)
7432#define DSI_VLCR_HLINE13_Msk (0x1U << DSI_VLCR_HLINE13_Pos) /*!< 0x00002000 */
7433#define DSI_VLCR_HLINE13 DSI_VLCR_HLINE13_Msk
7434#define DSI_VLCR_HLINE14_Pos (14U)
7435#define DSI_VLCR_HLINE14_Msk (0x1U << DSI_VLCR_HLINE14_Pos) /*!< 0x00004000 */
7436#define DSI_VLCR_HLINE14 DSI_VLCR_HLINE14_Msk
7437
7438/******************* Bit definition for DSI_VVSACR register *************/
7439#define DSI_VVSACR_VSA_Pos (0U)
7440#define DSI_VVSACR_VSA_Msk (0x3FFU << DSI_VVSACR_VSA_Pos) /*!< 0x000003FF */
7441#define DSI_VVSACR_VSA DSI_VVSACR_VSA_Msk /*!< Vertical Synchronism Active duration */
7442#define DSI_VVSACR_VSA0_Pos (0U)
7443#define DSI_VVSACR_VSA0_Msk (0x1U << DSI_VVSACR_VSA0_Pos) /*!< 0x00000001 */
7444#define DSI_VVSACR_VSA0 DSI_VVSACR_VSA0_Msk
7445#define DSI_VVSACR_VSA1_Pos (1U)
7446#define DSI_VVSACR_VSA1_Msk (0x1U << DSI_VVSACR_VSA1_Pos) /*!< 0x00000002 */
7447#define DSI_VVSACR_VSA1 DSI_VVSACR_VSA1_Msk
7448#define DSI_VVSACR_VSA2_Pos (2U)
7449#define DSI_VVSACR_VSA2_Msk (0x1U << DSI_VVSACR_VSA2_Pos) /*!< 0x00000004 */
7450#define DSI_VVSACR_VSA2 DSI_VVSACR_VSA2_Msk
7451#define DSI_VVSACR_VSA3_Pos (3U)
7452#define DSI_VVSACR_VSA3_Msk (0x1U << DSI_VVSACR_VSA3_Pos) /*!< 0x00000008 */
7453#define DSI_VVSACR_VSA3 DSI_VVSACR_VSA3_Msk
7454#define DSI_VVSACR_VSA4_Pos (4U)
7455#define DSI_VVSACR_VSA4_Msk (0x1U << DSI_VVSACR_VSA4_Pos) /*!< 0x00000010 */
7456#define DSI_VVSACR_VSA4 DSI_VVSACR_VSA4_Msk
7457#define DSI_VVSACR_VSA5_Pos (5U)
7458#define DSI_VVSACR_VSA5_Msk (0x1U << DSI_VVSACR_VSA5_Pos) /*!< 0x00000020 */
7459#define DSI_VVSACR_VSA5 DSI_VVSACR_VSA5_Msk
7460#define DSI_VVSACR_VSA6_Pos (6U)
7461#define DSI_VVSACR_VSA6_Msk (0x1U << DSI_VVSACR_VSA6_Pos) /*!< 0x00000040 */
7462#define DSI_VVSACR_VSA6 DSI_VVSACR_VSA6_Msk
7463#define DSI_VVSACR_VSA7_Pos (7U)
7464#define DSI_VVSACR_VSA7_Msk (0x1U << DSI_VVSACR_VSA7_Pos) /*!< 0x00000080 */
7465#define DSI_VVSACR_VSA7 DSI_VVSACR_VSA7_Msk
7466#define DSI_VVSACR_VSA8_Pos (8U)
7467#define DSI_VVSACR_VSA8_Msk (0x1U << DSI_VVSACR_VSA8_Pos) /*!< 0x00000100 */
7468#define DSI_VVSACR_VSA8 DSI_VVSACR_VSA8_Msk
7469#define DSI_VVSACR_VSA9_Pos (9U)
7470#define DSI_VVSACR_VSA9_Msk (0x1U << DSI_VVSACR_VSA9_Pos) /*!< 0x00000200 */
7471#define DSI_VVSACR_VSA9 DSI_VVSACR_VSA9_Msk
7472
7473/******************* Bit definition for DSI_VVBPCR register *************/
7474#define DSI_VVBPCR_VBP_Pos (0U)
7475#define DSI_VVBPCR_VBP_Msk (0x3FFU << DSI_VVBPCR_VBP_Pos) /*!< 0x000003FF */
7476#define DSI_VVBPCR_VBP DSI_VVBPCR_VBP_Msk /*!< Vertical Back-Porch duration */
7477#define DSI_VVBPCR_VBP0_Pos (0U)
7478#define DSI_VVBPCR_VBP0_Msk (0x1U << DSI_VVBPCR_VBP0_Pos) /*!< 0x00000001 */
7479#define DSI_VVBPCR_VBP0 DSI_VVBPCR_VBP0_Msk
7480#define DSI_VVBPCR_VBP1_Pos (1U)
7481#define DSI_VVBPCR_VBP1_Msk (0x1U << DSI_VVBPCR_VBP1_Pos) /*!< 0x00000002 */
7482#define DSI_VVBPCR_VBP1 DSI_VVBPCR_VBP1_Msk
7483#define DSI_VVBPCR_VBP2_Pos (2U)
7484#define DSI_VVBPCR_VBP2_Msk (0x1U << DSI_VVBPCR_VBP2_Pos) /*!< 0x00000004 */
7485#define DSI_VVBPCR_VBP2 DSI_VVBPCR_VBP2_Msk
7486#define DSI_VVBPCR_VBP3_Pos (3U)
7487#define DSI_VVBPCR_VBP3_Msk (0x1U << DSI_VVBPCR_VBP3_Pos) /*!< 0x00000008 */
7488#define DSI_VVBPCR_VBP3 DSI_VVBPCR_VBP3_Msk
7489#define DSI_VVBPCR_VBP4_Pos (4U)
7490#define DSI_VVBPCR_VBP4_Msk (0x1U << DSI_VVBPCR_VBP4_Pos) /*!< 0x00000010 */
7491#define DSI_VVBPCR_VBP4 DSI_VVBPCR_VBP4_Msk
7492#define DSI_VVBPCR_VBP5_Pos (5U)
7493#define DSI_VVBPCR_VBP5_Msk (0x1U << DSI_VVBPCR_VBP5_Pos) /*!< 0x00000020 */
7494#define DSI_VVBPCR_VBP5 DSI_VVBPCR_VBP5_Msk
7495#define DSI_VVBPCR_VBP6_Pos (6U)
7496#define DSI_VVBPCR_VBP6_Msk (0x1U << DSI_VVBPCR_VBP6_Pos) /*!< 0x00000040 */
7497#define DSI_VVBPCR_VBP6 DSI_VVBPCR_VBP6_Msk
7498#define DSI_VVBPCR_VBP7_Pos (7U)
7499#define DSI_VVBPCR_VBP7_Msk (0x1U << DSI_VVBPCR_VBP7_Pos) /*!< 0x00000080 */
7500#define DSI_VVBPCR_VBP7 DSI_VVBPCR_VBP7_Msk
7501#define DSI_VVBPCR_VBP8_Pos (8U)
7502#define DSI_VVBPCR_VBP8_Msk (0x1U << DSI_VVBPCR_VBP8_Pos) /*!< 0x00000100 */
7503#define DSI_VVBPCR_VBP8 DSI_VVBPCR_VBP8_Msk
7504#define DSI_VVBPCR_VBP9_Pos (9U)
7505#define DSI_VVBPCR_VBP9_Msk (0x1U << DSI_VVBPCR_VBP9_Pos) /*!< 0x00000200 */
7506#define DSI_VVBPCR_VBP9 DSI_VVBPCR_VBP9_Msk
7507
7508/******************* Bit definition for DSI_VVFPCR register *************/
7509#define DSI_VVFPCR_VFP_Pos (0U)
7510#define DSI_VVFPCR_VFP_Msk (0x3FFU << DSI_VVFPCR_VFP_Pos) /*!< 0x000003FF */
7511#define DSI_VVFPCR_VFP DSI_VVFPCR_VFP_Msk /*!< Vertical Front-Porch duration */
7512#define DSI_VVFPCR_VFP0_Pos (0U)
7513#define DSI_VVFPCR_VFP0_Msk (0x1U << DSI_VVFPCR_VFP0_Pos) /*!< 0x00000001 */
7514#define DSI_VVFPCR_VFP0 DSI_VVFPCR_VFP0_Msk
7515#define DSI_VVFPCR_VFP1_Pos (1U)
7516#define DSI_VVFPCR_VFP1_Msk (0x1U << DSI_VVFPCR_VFP1_Pos) /*!< 0x00000002 */
7517#define DSI_VVFPCR_VFP1 DSI_VVFPCR_VFP1_Msk
7518#define DSI_VVFPCR_VFP2_Pos (2U)
7519#define DSI_VVFPCR_VFP2_Msk (0x1U << DSI_VVFPCR_VFP2_Pos) /*!< 0x00000004 */
7520#define DSI_VVFPCR_VFP2 DSI_VVFPCR_VFP2_Msk
7521#define DSI_VVFPCR_VFP3_Pos (3U)
7522#define DSI_VVFPCR_VFP3_Msk (0x1U << DSI_VVFPCR_VFP3_Pos) /*!< 0x00000008 */
7523#define DSI_VVFPCR_VFP3 DSI_VVFPCR_VFP3_Msk
7524#define DSI_VVFPCR_VFP4_Pos (4U)
7525#define DSI_VVFPCR_VFP4_Msk (0x1U << DSI_VVFPCR_VFP4_Pos) /*!< 0x00000010 */
7526#define DSI_VVFPCR_VFP4 DSI_VVFPCR_VFP4_Msk
7527#define DSI_VVFPCR_VFP5_Pos (5U)
7528#define DSI_VVFPCR_VFP5_Msk (0x1U << DSI_VVFPCR_VFP5_Pos) /*!< 0x00000020 */
7529#define DSI_VVFPCR_VFP5 DSI_VVFPCR_VFP5_Msk
7530#define DSI_VVFPCR_VFP6_Pos (6U)
7531#define DSI_VVFPCR_VFP6_Msk (0x1U << DSI_VVFPCR_VFP6_Pos) /*!< 0x00000040 */
7532#define DSI_VVFPCR_VFP6 DSI_VVFPCR_VFP6_Msk
7533#define DSI_VVFPCR_VFP7_Pos (7U)
7534#define DSI_VVFPCR_VFP7_Msk (0x1U << DSI_VVFPCR_VFP7_Pos) /*!< 0x00000080 */
7535#define DSI_VVFPCR_VFP7 DSI_VVFPCR_VFP7_Msk
7536#define DSI_VVFPCR_VFP8_Pos (8U)
7537#define DSI_VVFPCR_VFP8_Msk (0x1U << DSI_VVFPCR_VFP8_Pos) /*!< 0x00000100 */
7538#define DSI_VVFPCR_VFP8 DSI_VVFPCR_VFP8_Msk
7539#define DSI_VVFPCR_VFP9_Pos (9U)
7540#define DSI_VVFPCR_VFP9_Msk (0x1U << DSI_VVFPCR_VFP9_Pos) /*!< 0x00000200 */
7541#define DSI_VVFPCR_VFP9 DSI_VVFPCR_VFP9_Msk
7542
7543/******************* Bit definition for DSI_VVACR register **************/
7544#define DSI_VVACR_VA_Pos (0U)
7545#define DSI_VVACR_VA_Msk (0x3FFFU << DSI_VVACR_VA_Pos) /*!< 0x00003FFF */
7546#define DSI_VVACR_VA DSI_VVACR_VA_Msk /*!< Vertical Active duration */
7547#define DSI_VVACR_VA0_Pos (0U)
7548#define DSI_VVACR_VA0_Msk (0x1U << DSI_VVACR_VA0_Pos) /*!< 0x00000001 */
7549#define DSI_VVACR_VA0 DSI_VVACR_VA0_Msk
7550#define DSI_VVACR_VA1_Pos (1U)
7551#define DSI_VVACR_VA1_Msk (0x1U << DSI_VVACR_VA1_Pos) /*!< 0x00000002 */
7552#define DSI_VVACR_VA1 DSI_VVACR_VA1_Msk
7553#define DSI_VVACR_VA2_Pos (2U)
7554#define DSI_VVACR_VA2_Msk (0x1U << DSI_VVACR_VA2_Pos) /*!< 0x00000004 */
7555#define DSI_VVACR_VA2 DSI_VVACR_VA2_Msk
7556#define DSI_VVACR_VA3_Pos (3U)
7557#define DSI_VVACR_VA3_Msk (0x1U << DSI_VVACR_VA3_Pos) /*!< 0x00000008 */
7558#define DSI_VVACR_VA3 DSI_VVACR_VA3_Msk
7559#define DSI_VVACR_VA4_Pos (4U)
7560#define DSI_VVACR_VA4_Msk (0x1U << DSI_VVACR_VA4_Pos) /*!< 0x00000010 */
7561#define DSI_VVACR_VA4 DSI_VVACR_VA4_Msk
7562#define DSI_VVACR_VA5_Pos (5U)
7563#define DSI_VVACR_VA5_Msk (0x1U << DSI_VVACR_VA5_Pos) /*!< 0x00000020 */
7564#define DSI_VVACR_VA5 DSI_VVACR_VA5_Msk
7565#define DSI_VVACR_VA6_Pos (6U)
7566#define DSI_VVACR_VA6_Msk (0x1U << DSI_VVACR_VA6_Pos) /*!< 0x00000040 */
7567#define DSI_VVACR_VA6 DSI_VVACR_VA6_Msk
7568#define DSI_VVACR_VA7_Pos (7U)
7569#define DSI_VVACR_VA7_Msk (0x1U << DSI_VVACR_VA7_Pos) /*!< 0x00000080 */
7570#define DSI_VVACR_VA7 DSI_VVACR_VA7_Msk
7571#define DSI_VVACR_VA8_Pos (8U)
7572#define DSI_VVACR_VA8_Msk (0x1U << DSI_VVACR_VA8_Pos) /*!< 0x00000100 */
7573#define DSI_VVACR_VA8 DSI_VVACR_VA8_Msk
7574#define DSI_VVACR_VA9_Pos (9U)
7575#define DSI_VVACR_VA9_Msk (0x1U << DSI_VVACR_VA9_Pos) /*!< 0x00000200 */
7576#define DSI_VVACR_VA9 DSI_VVACR_VA9_Msk
7577#define DSI_VVACR_VA10_Pos (10U)
7578#define DSI_VVACR_VA10_Msk (0x1U << DSI_VVACR_VA10_Pos) /*!< 0x00000400 */
7579#define DSI_VVACR_VA10 DSI_VVACR_VA10_Msk
7580#define DSI_VVACR_VA11_Pos (11U)
7581#define DSI_VVACR_VA11_Msk (0x1U << DSI_VVACR_VA11_Pos) /*!< 0x00000800 */
7582#define DSI_VVACR_VA11 DSI_VVACR_VA11_Msk
7583#define DSI_VVACR_VA12_Pos (12U)
7584#define DSI_VVACR_VA12_Msk (0x1U << DSI_VVACR_VA12_Pos) /*!< 0x00001000 */
7585#define DSI_VVACR_VA12 DSI_VVACR_VA12_Msk
7586#define DSI_VVACR_VA13_Pos (13U)
7587#define DSI_VVACR_VA13_Msk (0x1U << DSI_VVACR_VA13_Pos) /*!< 0x00002000 */
7588#define DSI_VVACR_VA13 DSI_VVACR_VA13_Msk
7589
7590/******************* Bit definition for DSI_LCCR register ***************/
7591#define DSI_LCCR_CMDSIZE_Pos (0U)
7592#define DSI_LCCR_CMDSIZE_Msk (0xFFFFU << DSI_LCCR_CMDSIZE_Pos) /*!< 0x0000FFFF */
7593#define DSI_LCCR_CMDSIZE DSI_LCCR_CMDSIZE_Msk /*!< Command Size */
7594#define DSI_LCCR_CMDSIZE0_Pos (0U)
7595#define DSI_LCCR_CMDSIZE0_Msk (0x1U << DSI_LCCR_CMDSIZE0_Pos) /*!< 0x00000001 */
7596#define DSI_LCCR_CMDSIZE0 DSI_LCCR_CMDSIZE0_Msk
7597#define DSI_LCCR_CMDSIZE1_Pos (1U)
7598#define DSI_LCCR_CMDSIZE1_Msk (0x1U << DSI_LCCR_CMDSIZE1_Pos) /*!< 0x00000002 */
7599#define DSI_LCCR_CMDSIZE1 DSI_LCCR_CMDSIZE1_Msk
7600#define DSI_LCCR_CMDSIZE2_Pos (2U)
7601#define DSI_LCCR_CMDSIZE2_Msk (0x1U << DSI_LCCR_CMDSIZE2_Pos) /*!< 0x00000004 */
7602#define DSI_LCCR_CMDSIZE2 DSI_LCCR_CMDSIZE2_Msk
7603#define DSI_LCCR_CMDSIZE3_Pos (3U)
7604#define DSI_LCCR_CMDSIZE3_Msk (0x1U << DSI_LCCR_CMDSIZE3_Pos) /*!< 0x00000008 */
7605#define DSI_LCCR_CMDSIZE3 DSI_LCCR_CMDSIZE3_Msk
7606#define DSI_LCCR_CMDSIZE4_Pos (4U)
7607#define DSI_LCCR_CMDSIZE4_Msk (0x1U << DSI_LCCR_CMDSIZE4_Pos) /*!< 0x00000010 */
7608#define DSI_LCCR_CMDSIZE4 DSI_LCCR_CMDSIZE4_Msk
7609#define DSI_LCCR_CMDSIZE5_Pos (5U)
7610#define DSI_LCCR_CMDSIZE5_Msk (0x1U << DSI_LCCR_CMDSIZE5_Pos) /*!< 0x00000020 */
7611#define DSI_LCCR_CMDSIZE5 DSI_LCCR_CMDSIZE5_Msk
7612#define DSI_LCCR_CMDSIZE6_Pos (6U)
7613#define DSI_LCCR_CMDSIZE6_Msk (0x1U << DSI_LCCR_CMDSIZE6_Pos) /*!< 0x00000040 */
7614#define DSI_LCCR_CMDSIZE6 DSI_LCCR_CMDSIZE6_Msk
7615#define DSI_LCCR_CMDSIZE7_Pos (7U)
7616#define DSI_LCCR_CMDSIZE7_Msk (0x1U << DSI_LCCR_CMDSIZE7_Pos) /*!< 0x00000080 */
7617#define DSI_LCCR_CMDSIZE7 DSI_LCCR_CMDSIZE7_Msk
7618#define DSI_LCCR_CMDSIZE8_Pos (8U)
7619#define DSI_LCCR_CMDSIZE8_Msk (0x1U << DSI_LCCR_CMDSIZE8_Pos) /*!< 0x00000100 */
7620#define DSI_LCCR_CMDSIZE8 DSI_LCCR_CMDSIZE8_Msk
7621#define DSI_LCCR_CMDSIZE9_Pos (9U)
7622#define DSI_LCCR_CMDSIZE9_Msk (0x1U << DSI_LCCR_CMDSIZE9_Pos) /*!< 0x00000200 */
7623#define DSI_LCCR_CMDSIZE9 DSI_LCCR_CMDSIZE9_Msk
7624#define DSI_LCCR_CMDSIZE10_Pos (10U)
7625#define DSI_LCCR_CMDSIZE10_Msk (0x1U << DSI_LCCR_CMDSIZE10_Pos) /*!< 0x00000400 */
7626#define DSI_LCCR_CMDSIZE10 DSI_LCCR_CMDSIZE10_Msk
7627#define DSI_LCCR_CMDSIZE11_Pos (11U)
7628#define DSI_LCCR_CMDSIZE11_Msk (0x1U << DSI_LCCR_CMDSIZE11_Pos) /*!< 0x00000800 */
7629#define DSI_LCCR_CMDSIZE11 DSI_LCCR_CMDSIZE11_Msk
7630#define DSI_LCCR_CMDSIZE12_Pos (12U)
7631#define DSI_LCCR_CMDSIZE12_Msk (0x1U << DSI_LCCR_CMDSIZE12_Pos) /*!< 0x00001000 */
7632#define DSI_LCCR_CMDSIZE12 DSI_LCCR_CMDSIZE12_Msk
7633#define DSI_LCCR_CMDSIZE13_Pos (13U)
7634#define DSI_LCCR_CMDSIZE13_Msk (0x1U << DSI_LCCR_CMDSIZE13_Pos) /*!< 0x00002000 */
7635#define DSI_LCCR_CMDSIZE13 DSI_LCCR_CMDSIZE13_Msk
7636#define DSI_LCCR_CMDSIZE14_Pos (14U)
7637#define DSI_LCCR_CMDSIZE14_Msk (0x1U << DSI_LCCR_CMDSIZE14_Pos) /*!< 0x00004000 */
7638#define DSI_LCCR_CMDSIZE14 DSI_LCCR_CMDSIZE14_Msk
7639#define DSI_LCCR_CMDSIZE15_Pos (15U)
7640#define DSI_LCCR_CMDSIZE15_Msk (0x1U << DSI_LCCR_CMDSIZE15_Pos) /*!< 0x00008000 */
7641#define DSI_LCCR_CMDSIZE15 DSI_LCCR_CMDSIZE15_Msk
7642
7643/******************* Bit definition for DSI_CMCR register ***************/
7644#define DSI_CMCR_TEARE_Pos (0U)
7645#define DSI_CMCR_TEARE_Msk (0x1U << DSI_CMCR_TEARE_Pos) /*!< 0x00000001 */
7646#define DSI_CMCR_TEARE DSI_CMCR_TEARE_Msk /*!< Tearing Effect Acknowledge Request Enable */
7647#define DSI_CMCR_ARE_Pos (1U)
7648#define DSI_CMCR_ARE_Msk (0x1U << DSI_CMCR_ARE_Pos) /*!< 0x00000002 */
7649#define DSI_CMCR_ARE DSI_CMCR_ARE_Msk /*!< Acknowledge Request Enable */
7650#define DSI_CMCR_GSW0TX_Pos (8U)
7651#define DSI_CMCR_GSW0TX_Msk (0x1U << DSI_CMCR_GSW0TX_Pos) /*!< 0x00000100 */
7652#define DSI_CMCR_GSW0TX DSI_CMCR_GSW0TX_Msk /*!< Generic Short Write Zero parameters Transmission */
7653#define DSI_CMCR_GSW1TX_Pos (9U)
7654#define DSI_CMCR_GSW1TX_Msk (0x1U << DSI_CMCR_GSW1TX_Pos) /*!< 0x00000200 */
7655#define DSI_CMCR_GSW1TX DSI_CMCR_GSW1TX_Msk /*!< Generic Short Write One parameters Transmission */
7656#define DSI_CMCR_GSW2TX_Pos (10U)
7657#define DSI_CMCR_GSW2TX_Msk (0x1U << DSI_CMCR_GSW2TX_Pos) /*!< 0x00000400 */
7658#define DSI_CMCR_GSW2TX DSI_CMCR_GSW2TX_Msk /*!< Generic Short Write Two parameters Transmission */
7659#define DSI_CMCR_GSR0TX_Pos (11U)
7660#define DSI_CMCR_GSR0TX_Msk (0x1U << DSI_CMCR_GSR0TX_Pos) /*!< 0x00000800 */
7661#define DSI_CMCR_GSR0TX DSI_CMCR_GSR0TX_Msk /*!< Generic Short Read Zero parameters Transmission */
7662#define DSI_CMCR_GSR1TX_Pos (12U)
7663#define DSI_CMCR_GSR1TX_Msk (0x1U << DSI_CMCR_GSR1TX_Pos) /*!< 0x00001000 */
7664#define DSI_CMCR_GSR1TX DSI_CMCR_GSR1TX_Msk /*!< Generic Short Read One parameters Transmission */
7665#define DSI_CMCR_GSR2TX_Pos (13U)
7666#define DSI_CMCR_GSR2TX_Msk (0x1U << DSI_CMCR_GSR2TX_Pos) /*!< 0x00002000 */
7667#define DSI_CMCR_GSR2TX DSI_CMCR_GSR2TX_Msk /*!< Generic Short Read Two parameters Transmission */
7668#define DSI_CMCR_GLWTX_Pos (14U)
7669#define DSI_CMCR_GLWTX_Msk (0x1U << DSI_CMCR_GLWTX_Pos) /*!< 0x00004000 */
7670#define DSI_CMCR_GLWTX DSI_CMCR_GLWTX_Msk /*!< Generic Long Write Transmission */
7671#define DSI_CMCR_DSW0TX_Pos (16U)
7672#define DSI_CMCR_DSW0TX_Msk (0x1U << DSI_CMCR_DSW0TX_Pos) /*!< 0x00010000 */
7673#define DSI_CMCR_DSW0TX DSI_CMCR_DSW0TX_Msk /*!< DCS Short Write Zero parameter Transmission */
7674#define DSI_CMCR_DSW1TX_Pos (17U)
7675#define DSI_CMCR_DSW1TX_Msk (0x1U << DSI_CMCR_DSW1TX_Pos) /*!< 0x00020000 */
7676#define DSI_CMCR_DSW1TX DSI_CMCR_DSW1TX_Msk /*!< DCS Short Read One parameter Transmission */
7677#define DSI_CMCR_DSR0TX_Pos (18U)
7678#define DSI_CMCR_DSR0TX_Msk (0x1U << DSI_CMCR_DSR0TX_Pos) /*!< 0x00040000 */
7679#define DSI_CMCR_DSR0TX DSI_CMCR_DSR0TX_Msk /*!< DCS Short Read Zero parameter Transmission */
7680#define DSI_CMCR_DLWTX_Pos (19U)
7681#define DSI_CMCR_DLWTX_Msk (0x1U << DSI_CMCR_DLWTX_Pos) /*!< 0x00080000 */
7682#define DSI_CMCR_DLWTX DSI_CMCR_DLWTX_Msk /*!< DCS Long Write Transmission */
7683#define DSI_CMCR_MRDPS_Pos (24U)
7684#define DSI_CMCR_MRDPS_Msk (0x1U << DSI_CMCR_MRDPS_Pos) /*!< 0x01000000 */
7685#define DSI_CMCR_MRDPS DSI_CMCR_MRDPS_Msk /*!< Maximum Read Packet Size */
7686
7687/******************* Bit definition for DSI_GHCR register ***************/
7688#define DSI_GHCR_DT_Pos (0U)
7689#define DSI_GHCR_DT_Msk (0x3FU << DSI_GHCR_DT_Pos) /*!< 0x0000003F */
7690#define DSI_GHCR_DT DSI_GHCR_DT_Msk /*!< Type */
7691#define DSI_GHCR_DT0_Pos (0U)
7692#define DSI_GHCR_DT0_Msk (0x1U << DSI_GHCR_DT0_Pos) /*!< 0x00000001 */
7693#define DSI_GHCR_DT0 DSI_GHCR_DT0_Msk
7694#define DSI_GHCR_DT1_Pos (1U)
7695#define DSI_GHCR_DT1_Msk (0x1U << DSI_GHCR_DT1_Pos) /*!< 0x00000002 */
7696#define DSI_GHCR_DT1 DSI_GHCR_DT1_Msk
7697#define DSI_GHCR_DT2_Pos (2U)
7698#define DSI_GHCR_DT2_Msk (0x1U << DSI_GHCR_DT2_Pos) /*!< 0x00000004 */
7699#define DSI_GHCR_DT2 DSI_GHCR_DT2_Msk
7700#define DSI_GHCR_DT3_Pos (3U)
7701#define DSI_GHCR_DT3_Msk (0x1U << DSI_GHCR_DT3_Pos) /*!< 0x00000008 */
7702#define DSI_GHCR_DT3 DSI_GHCR_DT3_Msk
7703#define DSI_GHCR_DT4_Pos (4U)
7704#define DSI_GHCR_DT4_Msk (0x1U << DSI_GHCR_DT4_Pos) /*!< 0x00000010 */
7705#define DSI_GHCR_DT4 DSI_GHCR_DT4_Msk
7706#define DSI_GHCR_DT5_Pos (5U)
7707#define DSI_GHCR_DT5_Msk (0x1U << DSI_GHCR_DT5_Pos) /*!< 0x00000020 */
7708#define DSI_GHCR_DT5 DSI_GHCR_DT5_Msk
7709
7710#define DSI_GHCR_VCID_Pos (6U)
7711#define DSI_GHCR_VCID_Msk (0x3U << DSI_GHCR_VCID_Pos) /*!< 0x000000C0 */
7712#define DSI_GHCR_VCID DSI_GHCR_VCID_Msk /*!< Channel */
7713#define DSI_GHCR_VCID0_Pos (6U)
7714#define DSI_GHCR_VCID0_Msk (0x1U << DSI_GHCR_VCID0_Pos) /*!< 0x00000040 */
7715#define DSI_GHCR_VCID0 DSI_GHCR_VCID0_Msk
7716#define DSI_GHCR_VCID1_Pos (7U)
7717#define DSI_GHCR_VCID1_Msk (0x1U << DSI_GHCR_VCID1_Pos) /*!< 0x00000080 */
7718#define DSI_GHCR_VCID1 DSI_GHCR_VCID1_Msk
7719
7720#define DSI_GHCR_WCLSB_Pos (8U)
7721#define DSI_GHCR_WCLSB_Msk (0xFFU << DSI_GHCR_WCLSB_Pos) /*!< 0x0000FF00 */
7722#define DSI_GHCR_WCLSB DSI_GHCR_WCLSB_Msk /*!< WordCount LSB */
7723#define DSI_GHCR_WCLSB0_Pos (8U)
7724#define DSI_GHCR_WCLSB0_Msk (0x1U << DSI_GHCR_WCLSB0_Pos) /*!< 0x00000100 */
7725#define DSI_GHCR_WCLSB0 DSI_GHCR_WCLSB0_Msk
7726#define DSI_GHCR_WCLSB1_Pos (9U)
7727#define DSI_GHCR_WCLSB1_Msk (0x1U << DSI_GHCR_WCLSB1_Pos) /*!< 0x00000200 */
7728#define DSI_GHCR_WCLSB1 DSI_GHCR_WCLSB1_Msk
7729#define DSI_GHCR_WCLSB2_Pos (10U)
7730#define DSI_GHCR_WCLSB2_Msk (0x1U << DSI_GHCR_WCLSB2_Pos) /*!< 0x00000400 */
7731#define DSI_GHCR_WCLSB2 DSI_GHCR_WCLSB2_Msk
7732#define DSI_GHCR_WCLSB3_Pos (11U)
7733#define DSI_GHCR_WCLSB3_Msk (0x1U << DSI_GHCR_WCLSB3_Pos) /*!< 0x00000800 */
7734#define DSI_GHCR_WCLSB3 DSI_GHCR_WCLSB3_Msk
7735#define DSI_GHCR_WCLSB4_Pos (12U)
7736#define DSI_GHCR_WCLSB4_Msk (0x1U << DSI_GHCR_WCLSB4_Pos) /*!< 0x00001000 */
7737#define DSI_GHCR_WCLSB4 DSI_GHCR_WCLSB4_Msk
7738#define DSI_GHCR_WCLSB5_Pos (13U)
7739#define DSI_GHCR_WCLSB5_Msk (0x1U << DSI_GHCR_WCLSB5_Pos) /*!< 0x00002000 */
7740#define DSI_GHCR_WCLSB5 DSI_GHCR_WCLSB5_Msk
7741#define DSI_GHCR_WCLSB6_Pos (14U)
7742#define DSI_GHCR_WCLSB6_Msk (0x1U << DSI_GHCR_WCLSB6_Pos) /*!< 0x00004000 */
7743#define DSI_GHCR_WCLSB6 DSI_GHCR_WCLSB6_Msk
7744#define DSI_GHCR_WCLSB7_Pos (15U)
7745#define DSI_GHCR_WCLSB7_Msk (0x1U << DSI_GHCR_WCLSB7_Pos) /*!< 0x00008000 */
7746#define DSI_GHCR_WCLSB7 DSI_GHCR_WCLSB7_Msk
7747
7748#define DSI_GHCR_WCMSB_Pos (16U)
7749#define DSI_GHCR_WCMSB_Msk (0xFFU << DSI_GHCR_WCMSB_Pos) /*!< 0x00FF0000 */
7750#define DSI_GHCR_WCMSB DSI_GHCR_WCMSB_Msk /*!< WordCount MSB */
7751#define DSI_GHCR_WCMSB0_Pos (16U)
7752#define DSI_GHCR_WCMSB0_Msk (0x1U << DSI_GHCR_WCMSB0_Pos) /*!< 0x00010000 */
7753#define DSI_GHCR_WCMSB0 DSI_GHCR_WCMSB0_Msk
7754#define DSI_GHCR_WCMSB1_Pos (17U)
7755#define DSI_GHCR_WCMSB1_Msk (0x1U << DSI_GHCR_WCMSB1_Pos) /*!< 0x00020000 */
7756#define DSI_GHCR_WCMSB1 DSI_GHCR_WCMSB1_Msk
7757#define DSI_GHCR_WCMSB2_Pos (18U)
7758#define DSI_GHCR_WCMSB2_Msk (0x1U << DSI_GHCR_WCMSB2_Pos) /*!< 0x00040000 */
7759#define DSI_GHCR_WCMSB2 DSI_GHCR_WCMSB2_Msk
7760#define DSI_GHCR_WCMSB3_Pos (19U)
7761#define DSI_GHCR_WCMSB3_Msk (0x1U << DSI_GHCR_WCMSB3_Pos) /*!< 0x00080000 */
7762#define DSI_GHCR_WCMSB3 DSI_GHCR_WCMSB3_Msk
7763#define DSI_GHCR_WCMSB4_Pos (20U)
7764#define DSI_GHCR_WCMSB4_Msk (0x1U << DSI_GHCR_WCMSB4_Pos) /*!< 0x00100000 */
7765#define DSI_GHCR_WCMSB4 DSI_GHCR_WCMSB4_Msk
7766#define DSI_GHCR_WCMSB5_Pos (21U)
7767#define DSI_GHCR_WCMSB5_Msk (0x1U << DSI_GHCR_WCMSB5_Pos) /*!< 0x00200000 */
7768#define DSI_GHCR_WCMSB5 DSI_GHCR_WCMSB5_Msk
7769#define DSI_GHCR_WCMSB6_Pos (22U)
7770#define DSI_GHCR_WCMSB6_Msk (0x1U << DSI_GHCR_WCMSB6_Pos) /*!< 0x00400000 */
7771#define DSI_GHCR_WCMSB6 DSI_GHCR_WCMSB6_Msk
7772#define DSI_GHCR_WCMSB7_Pos (23U)
7773#define DSI_GHCR_WCMSB7_Msk (0x1U << DSI_GHCR_WCMSB7_Pos) /*!< 0x00800000 */
7774#define DSI_GHCR_WCMSB7 DSI_GHCR_WCMSB7_Msk
7775
7776/******************* Bit definition for DSI_GPDR register ***************/
7777#define DSI_GPDR_DATA1_Pos (0U)
7778#define DSI_GPDR_DATA1_Msk (0xFFU << DSI_GPDR_DATA1_Pos) /*!< 0x000000FF */
7779#define DSI_GPDR_DATA1 DSI_GPDR_DATA1_Msk /*!< Payload Byte 1 */
7780#define DSI_GPDR_DATA1_0 (0x01U << DSI_GPDR_DATA1_Pos) /*!< 0x00000001 */
7781#define DSI_GPDR_DATA1_1 (0x02U << DSI_GPDR_DATA1_Pos) /*!< 0x00000002 */
7782#define DSI_GPDR_DATA1_2 (0x04U << DSI_GPDR_DATA1_Pos) /*!< 0x00000004 */
7783#define DSI_GPDR_DATA1_3 (0x08U << DSI_GPDR_DATA1_Pos) /*!< 0x00000008 */
7784#define DSI_GPDR_DATA1_4 (0x10U << DSI_GPDR_DATA1_Pos) /*!< 0x00000010 */
7785#define DSI_GPDR_DATA1_5 (0x20U << DSI_GPDR_DATA1_Pos) /*!< 0x00000020 */
7786#define DSI_GPDR_DATA1_6 (0x40U << DSI_GPDR_DATA1_Pos) /*!< 0x00000040 */
7787#define DSI_GPDR_DATA1_7 (0x80U << DSI_GPDR_DATA1_Pos) /*!< 0x00000080 */
7788
7789#define DSI_GPDR_DATA2_Pos (8U)
7790#define DSI_GPDR_DATA2_Msk (0xFFU << DSI_GPDR_DATA2_Pos) /*!< 0x0000FF00 */
7791#define DSI_GPDR_DATA2 DSI_GPDR_DATA2_Msk /*!< Payload Byte 2 */
7792#define DSI_GPDR_DATA2_0 (0x01U << DSI_GPDR_DATA2_Pos) /*!< 0x00000100 */
7793#define DSI_GPDR_DATA2_1 (0x02U << DSI_GPDR_DATA2_Pos) /*!< 0x00000200 */
7794#define DSI_GPDR_DATA2_2 (0x04U << DSI_GPDR_DATA2_Pos) /*!< 0x00000400 */
7795#define DSI_GPDR_DATA2_3 (0x08U << DSI_GPDR_DATA2_Pos) /*!< 0x00000800 */
7796#define DSI_GPDR_DATA2_4 (0x10U << DSI_GPDR_DATA2_Pos) /*!< 0x00001000 */
7797#define DSI_GPDR_DATA2_5 (0x20U << DSI_GPDR_DATA2_Pos) /*!< 0x00002000 */
7798#define DSI_GPDR_DATA2_6 (0x40U << DSI_GPDR_DATA2_Pos) /*!< 0x00004000 */
7799#define DSI_GPDR_DATA2_7 (0x80U << DSI_GPDR_DATA2_Pos) /*!< 0x00008000 */
7800
7801#define DSI_GPDR_DATA3_Pos (16U)
7802#define DSI_GPDR_DATA3_Msk (0xFFU << DSI_GPDR_DATA3_Pos) /*!< 0x00FF0000 */
7803#define DSI_GPDR_DATA3 DSI_GPDR_DATA3_Msk /*!< Payload Byte 3 */
7804#define DSI_GPDR_DATA3_0 (0x01U << DSI_GPDR_DATA3_Pos) /*!< 0x00010000 */
7805#define DSI_GPDR_DATA3_1 (0x02U << DSI_GPDR_DATA3_Pos) /*!< 0x00020000 */
7806#define DSI_GPDR_DATA3_2 (0x04U << DSI_GPDR_DATA3_Pos) /*!< 0x00040000 */
7807#define DSI_GPDR_DATA3_3 (0x08U << DSI_GPDR_DATA3_Pos) /*!< 0x00080000 */
7808#define DSI_GPDR_DATA3_4 (0x10U << DSI_GPDR_DATA3_Pos) /*!< 0x00100000 */
7809#define DSI_GPDR_DATA3_5 (0x20U << DSI_GPDR_DATA3_Pos) /*!< 0x00200000 */
7810#define DSI_GPDR_DATA3_6 (0x40U << DSI_GPDR_DATA3_Pos) /*!< 0x00400000 */
7811#define DSI_GPDR_DATA3_7 (0x80U << DSI_GPDR_DATA3_Pos) /*!< 0x00800000 */
7812
7813#define DSI_GPDR_DATA4_Pos (24U)
7814#define DSI_GPDR_DATA4_Msk (0xFFU << DSI_GPDR_DATA4_Pos) /*!< 0xFF000000 */
7815#define DSI_GPDR_DATA4 DSI_GPDR_DATA4_Msk /*!< Payload Byte 4 */
7816#define DSI_GPDR_DATA4_0 (0x01U << DSI_GPDR_DATA4_Pos) /*!< 0x01000000 */
7817#define DSI_GPDR_DATA4_1 (0x02U << DSI_GPDR_DATA4_Pos) /*!< 0x02000000 */
7818#define DSI_GPDR_DATA4_2 (0x04U << DSI_GPDR_DATA4_Pos) /*!< 0x04000000 */
7819#define DSI_GPDR_DATA4_3 (0x08U << DSI_GPDR_DATA4_Pos) /*!< 0x08000000 */
7820#define DSI_GPDR_DATA4_4 (0x10U << DSI_GPDR_DATA4_Pos) /*!< 0x10000000 */
7821#define DSI_GPDR_DATA4_5 (0x20U << DSI_GPDR_DATA4_Pos) /*!< 0x20000000 */
7822#define DSI_GPDR_DATA4_6 (0x40U << DSI_GPDR_DATA4_Pos) /*!< 0x40000000 */
7823#define DSI_GPDR_DATA4_7 (0x80U << DSI_GPDR_DATA4_Pos) /*!< 0x80000000 */
7824
7825/******************* Bit definition for DSI_GPSR register ***************/
7826#define DSI_GPSR_CMDFE_Pos (0U)
7827#define DSI_GPSR_CMDFE_Msk (0x1U << DSI_GPSR_CMDFE_Pos) /*!< 0x00000001 */
7828#define DSI_GPSR_CMDFE DSI_GPSR_CMDFE_Msk /*!< Command FIFO Empty */
7829#define DSI_GPSR_CMDFF_Pos (1U)
7830#define DSI_GPSR_CMDFF_Msk (0x1U << DSI_GPSR_CMDFF_Pos) /*!< 0x00000002 */
7831#define DSI_GPSR_CMDFF DSI_GPSR_CMDFF_Msk /*!< Command FIFO Full */
7832#define DSI_GPSR_PWRFE_Pos (2U)
7833#define DSI_GPSR_PWRFE_Msk (0x1U << DSI_GPSR_PWRFE_Pos) /*!< 0x00000004 */
7834#define DSI_GPSR_PWRFE DSI_GPSR_PWRFE_Msk /*!< Payload Write FIFO Empty */
7835#define DSI_GPSR_PWRFF_Pos (3U)
7836#define DSI_GPSR_PWRFF_Msk (0x1U << DSI_GPSR_PWRFF_Pos) /*!< 0x00000008 */
7837#define DSI_GPSR_PWRFF DSI_GPSR_PWRFF_Msk /*!< Payload Write FIFO Full */
7838#define DSI_GPSR_PRDFE_Pos (4U)
7839#define DSI_GPSR_PRDFE_Msk (0x1U << DSI_GPSR_PRDFE_Pos) /*!< 0x00000010 */
7840#define DSI_GPSR_PRDFE DSI_GPSR_PRDFE_Msk /*!< Payload Read FIFO Empty */
7841#define DSI_GPSR_PRDFF_Pos (5U)
7842#define DSI_GPSR_PRDFF_Msk (0x1U << DSI_GPSR_PRDFF_Pos) /*!< 0x00000020 */
7843#define DSI_GPSR_PRDFF DSI_GPSR_PRDFF_Msk /*!< Payload Read FIFO Full */
7844#define DSI_GPSR_RCB_Pos (6U)
7845#define DSI_GPSR_RCB_Msk (0x1U << DSI_GPSR_RCB_Pos) /*!< 0x00000040 */
7846#define DSI_GPSR_RCB DSI_GPSR_RCB_Msk /*!< Read Command Busy */
7847
7848/******************* Bit definition for DSI_TCCR0 register **************/
7849#define DSI_TCCR0_LPRX_TOCNT_Pos (0U)
7850#define DSI_TCCR0_LPRX_TOCNT_Msk (0xFFFFU << DSI_TCCR0_LPRX_TOCNT_Pos) /*!< 0x0000FFFF */
7851#define DSI_TCCR0_LPRX_TOCNT DSI_TCCR0_LPRX_TOCNT_Msk /*!< Low-power Reception Timeout Counter */
7852#define DSI_TCCR0_LPRX_TOCNT0_Pos (0U)
7853#define DSI_TCCR0_LPRX_TOCNT0_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT0_Pos) /*!< 0x00000001 */
7854#define DSI_TCCR0_LPRX_TOCNT0 DSI_TCCR0_LPRX_TOCNT0_Msk
7855#define DSI_TCCR0_LPRX_TOCNT1_Pos (1U)
7856#define DSI_TCCR0_LPRX_TOCNT1_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT1_Pos) /*!< 0x00000002 */
7857#define DSI_TCCR0_LPRX_TOCNT1 DSI_TCCR0_LPRX_TOCNT1_Msk
7858#define DSI_TCCR0_LPRX_TOCNT2_Pos (2U)
7859#define DSI_TCCR0_LPRX_TOCNT2_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT2_Pos) /*!< 0x00000004 */
7860#define DSI_TCCR0_LPRX_TOCNT2 DSI_TCCR0_LPRX_TOCNT2_Msk
7861#define DSI_TCCR0_LPRX_TOCNT3_Pos (3U)
7862#define DSI_TCCR0_LPRX_TOCNT3_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT3_Pos) /*!< 0x00000008 */
7863#define DSI_TCCR0_LPRX_TOCNT3 DSI_TCCR0_LPRX_TOCNT3_Msk
7864#define DSI_TCCR0_LPRX_TOCNT4_Pos (4U)
7865#define DSI_TCCR0_LPRX_TOCNT4_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT4_Pos) /*!< 0x00000010 */
7866#define DSI_TCCR0_LPRX_TOCNT4 DSI_TCCR0_LPRX_TOCNT4_Msk
7867#define DSI_TCCR0_LPRX_TOCNT5_Pos (5U)
7868#define DSI_TCCR0_LPRX_TOCNT5_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT5_Pos) /*!< 0x00000020 */
7869#define DSI_TCCR0_LPRX_TOCNT5 DSI_TCCR0_LPRX_TOCNT5_Msk
7870#define DSI_TCCR0_LPRX_TOCNT6_Pos (6U)
7871#define DSI_TCCR0_LPRX_TOCNT6_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT6_Pos) /*!< 0x00000040 */
7872#define DSI_TCCR0_LPRX_TOCNT6 DSI_TCCR0_LPRX_TOCNT6_Msk
7873#define DSI_TCCR0_LPRX_TOCNT7_Pos (7U)
7874#define DSI_TCCR0_LPRX_TOCNT7_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT7_Pos) /*!< 0x00000080 */
7875#define DSI_TCCR0_LPRX_TOCNT7 DSI_TCCR0_LPRX_TOCNT7_Msk
7876#define DSI_TCCR0_LPRX_TOCNT8_Pos (8U)
7877#define DSI_TCCR0_LPRX_TOCNT8_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT8_Pos) /*!< 0x00000100 */
7878#define DSI_TCCR0_LPRX_TOCNT8 DSI_TCCR0_LPRX_TOCNT8_Msk
7879#define DSI_TCCR0_LPRX_TOCNT9_Pos (9U)
7880#define DSI_TCCR0_LPRX_TOCNT9_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT9_Pos) /*!< 0x00000200 */
7881#define DSI_TCCR0_LPRX_TOCNT9 DSI_TCCR0_LPRX_TOCNT9_Msk
7882#define DSI_TCCR0_LPRX_TOCNT10_Pos (10U)
7883#define DSI_TCCR0_LPRX_TOCNT10_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT10_Pos) /*!< 0x00000400 */
7884#define DSI_TCCR0_LPRX_TOCNT10 DSI_TCCR0_LPRX_TOCNT10_Msk
7885#define DSI_TCCR0_LPRX_TOCNT11_Pos (11U)
7886#define DSI_TCCR0_LPRX_TOCNT11_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT11_Pos) /*!< 0x00000800 */
7887#define DSI_TCCR0_LPRX_TOCNT11 DSI_TCCR0_LPRX_TOCNT11_Msk
7888#define DSI_TCCR0_LPRX_TOCNT12_Pos (12U)
7889#define DSI_TCCR0_LPRX_TOCNT12_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT12_Pos) /*!< 0x00001000 */
7890#define DSI_TCCR0_LPRX_TOCNT12 DSI_TCCR0_LPRX_TOCNT12_Msk
7891#define DSI_TCCR0_LPRX_TOCNT13_Pos (13U)
7892#define DSI_TCCR0_LPRX_TOCNT13_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT13_Pos) /*!< 0x00002000 */
7893#define DSI_TCCR0_LPRX_TOCNT13 DSI_TCCR0_LPRX_TOCNT13_Msk
7894#define DSI_TCCR0_LPRX_TOCNT14_Pos (14U)
7895#define DSI_TCCR0_LPRX_TOCNT14_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT14_Pos) /*!< 0x00004000 */
7896#define DSI_TCCR0_LPRX_TOCNT14 DSI_TCCR0_LPRX_TOCNT14_Msk
7897#define DSI_TCCR0_LPRX_TOCNT15_Pos (15U)
7898#define DSI_TCCR0_LPRX_TOCNT15_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT15_Pos) /*!< 0x00008000 */
7899#define DSI_TCCR0_LPRX_TOCNT15 DSI_TCCR0_LPRX_TOCNT15_Msk
7900
7901#define DSI_TCCR0_HSTX_TOCNT_Pos (16U)
7902#define DSI_TCCR0_HSTX_TOCNT_Msk (0xFFFFU << DSI_TCCR0_HSTX_TOCNT_Pos) /*!< 0xFFFF0000 */
7903#define DSI_TCCR0_HSTX_TOCNT DSI_TCCR0_HSTX_TOCNT_Msk /*!< High-Speed Transmission Timeout Counter */
7904#define DSI_TCCR0_HSTX_TOCNT0_Pos (16U)
7905#define DSI_TCCR0_HSTX_TOCNT0_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT0_Pos) /*!< 0x00010000 */
7906#define DSI_TCCR0_HSTX_TOCNT0 DSI_TCCR0_HSTX_TOCNT0_Msk
7907#define DSI_TCCR0_HSTX_TOCNT1_Pos (17U)
7908#define DSI_TCCR0_HSTX_TOCNT1_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT1_Pos) /*!< 0x00020000 */
7909#define DSI_TCCR0_HSTX_TOCNT1 DSI_TCCR0_HSTX_TOCNT1_Msk
7910#define DSI_TCCR0_HSTX_TOCNT2_Pos (18U)
7911#define DSI_TCCR0_HSTX_TOCNT2_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT2_Pos) /*!< 0x00040000 */
7912#define DSI_TCCR0_HSTX_TOCNT2 DSI_TCCR0_HSTX_TOCNT2_Msk
7913#define DSI_TCCR0_HSTX_TOCNT3_Pos (19U)
7914#define DSI_TCCR0_HSTX_TOCNT3_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT3_Pos) /*!< 0x00080000 */
7915#define DSI_TCCR0_HSTX_TOCNT3 DSI_TCCR0_HSTX_TOCNT3_Msk
7916#define DSI_TCCR0_HSTX_TOCNT4_Pos (20U)
7917#define DSI_TCCR0_HSTX_TOCNT4_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT4_Pos) /*!< 0x00100000 */
7918#define DSI_TCCR0_HSTX_TOCNT4 DSI_TCCR0_HSTX_TOCNT4_Msk
7919#define DSI_TCCR0_HSTX_TOCNT5_Pos (21U)
7920#define DSI_TCCR0_HSTX_TOCNT5_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT5_Pos) /*!< 0x00200000 */
7921#define DSI_TCCR0_HSTX_TOCNT5 DSI_TCCR0_HSTX_TOCNT5_Msk
7922#define DSI_TCCR0_HSTX_TOCNT6_Pos (22U)
7923#define DSI_TCCR0_HSTX_TOCNT6_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT6_Pos) /*!< 0x00400000 */
7924#define DSI_TCCR0_HSTX_TOCNT6 DSI_TCCR0_HSTX_TOCNT6_Msk
7925#define DSI_TCCR0_HSTX_TOCNT7_Pos (23U)
7926#define DSI_TCCR0_HSTX_TOCNT7_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT7_Pos) /*!< 0x00800000 */
7927#define DSI_TCCR0_HSTX_TOCNT7 DSI_TCCR0_HSTX_TOCNT7_Msk
7928#define DSI_TCCR0_HSTX_TOCNT8_Pos (24U)
7929#define DSI_TCCR0_HSTX_TOCNT8_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT8_Pos) /*!< 0x01000000 */
7930#define DSI_TCCR0_HSTX_TOCNT8 DSI_TCCR0_HSTX_TOCNT8_Msk
7931#define DSI_TCCR0_HSTX_TOCNT9_Pos (25U)
7932#define DSI_TCCR0_HSTX_TOCNT9_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT9_Pos) /*!< 0x02000000 */
7933#define DSI_TCCR0_HSTX_TOCNT9 DSI_TCCR0_HSTX_TOCNT9_Msk
7934#define DSI_TCCR0_HSTX_TOCNT10_Pos (26U)
7935#define DSI_TCCR0_HSTX_TOCNT10_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT10_Pos) /*!< 0x04000000 */
7936#define DSI_TCCR0_HSTX_TOCNT10 DSI_TCCR0_HSTX_TOCNT10_Msk
7937#define DSI_TCCR0_HSTX_TOCNT11_Pos (27U)
7938#define DSI_TCCR0_HSTX_TOCNT11_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT11_Pos) /*!< 0x08000000 */
7939#define DSI_TCCR0_HSTX_TOCNT11 DSI_TCCR0_HSTX_TOCNT11_Msk
7940#define DSI_TCCR0_HSTX_TOCNT12_Pos (28U)
7941#define DSI_TCCR0_HSTX_TOCNT12_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT12_Pos) /*!< 0x10000000 */
7942#define DSI_TCCR0_HSTX_TOCNT12 DSI_TCCR0_HSTX_TOCNT12_Msk
7943#define DSI_TCCR0_HSTX_TOCNT13_Pos (29U)
7944#define DSI_TCCR0_HSTX_TOCNT13_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT13_Pos) /*!< 0x20000000 */
7945#define DSI_TCCR0_HSTX_TOCNT13 DSI_TCCR0_HSTX_TOCNT13_Msk
7946#define DSI_TCCR0_HSTX_TOCNT14_Pos (30U)
7947#define DSI_TCCR0_HSTX_TOCNT14_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT14_Pos) /*!< 0x40000000 */
7948#define DSI_TCCR0_HSTX_TOCNT14 DSI_TCCR0_HSTX_TOCNT14_Msk
7949#define DSI_TCCR0_HSTX_TOCNT15_Pos (31U)
7950#define DSI_TCCR0_HSTX_TOCNT15_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT15_Pos) /*!< 0x80000000 */
7951#define DSI_TCCR0_HSTX_TOCNT15 DSI_TCCR0_HSTX_TOCNT15_Msk
7952
7953/******************* Bit definition for DSI_TCCR1 register **************/
7954#define DSI_TCCR1_HSRD_TOCNT_Pos (0U)
7955#define DSI_TCCR1_HSRD_TOCNT_Msk (0xFFFFU << DSI_TCCR1_HSRD_TOCNT_Pos) /*!< 0x0000FFFF */
7956#define DSI_TCCR1_HSRD_TOCNT DSI_TCCR1_HSRD_TOCNT_Msk /*!< High-Speed Read Timeout Counter */
7957#define DSI_TCCR1_HSRD_TOCNT0_Pos (0U)
7958#define DSI_TCCR1_HSRD_TOCNT0_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT0_Pos) /*!< 0x00000001 */
7959#define DSI_TCCR1_HSRD_TOCNT0 DSI_TCCR1_HSRD_TOCNT0_Msk
7960#define DSI_TCCR1_HSRD_TOCNT1_Pos (1U)
7961#define DSI_TCCR1_HSRD_TOCNT1_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT1_Pos) /*!< 0x00000002 */
7962#define DSI_TCCR1_HSRD_TOCNT1 DSI_TCCR1_HSRD_TOCNT1_Msk
7963#define DSI_TCCR1_HSRD_TOCNT2_Pos (2U)
7964#define DSI_TCCR1_HSRD_TOCNT2_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT2_Pos) /*!< 0x00000004 */
7965#define DSI_TCCR1_HSRD_TOCNT2 DSI_TCCR1_HSRD_TOCNT2_Msk
7966#define DSI_TCCR1_HSRD_TOCNT3_Pos (3U)
7967#define DSI_TCCR1_HSRD_TOCNT3_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT3_Pos) /*!< 0x00000008 */
7968#define DSI_TCCR1_HSRD_TOCNT3 DSI_TCCR1_HSRD_TOCNT3_Msk
7969#define DSI_TCCR1_HSRD_TOCNT4_Pos (4U)
7970#define DSI_TCCR1_HSRD_TOCNT4_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT4_Pos) /*!< 0x00000010 */
7971#define DSI_TCCR1_HSRD_TOCNT4 DSI_TCCR1_HSRD_TOCNT4_Msk
7972#define DSI_TCCR1_HSRD_TOCNT5_Pos (5U)
7973#define DSI_TCCR1_HSRD_TOCNT5_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT5_Pos) /*!< 0x00000020 */
7974#define DSI_TCCR1_HSRD_TOCNT5 DSI_TCCR1_HSRD_TOCNT5_Msk
7975#define DSI_TCCR1_HSRD_TOCNT6_Pos (6U)
7976#define DSI_TCCR1_HSRD_TOCNT6_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT6_Pos) /*!< 0x00000040 */
7977#define DSI_TCCR1_HSRD_TOCNT6 DSI_TCCR1_HSRD_TOCNT6_Msk
7978#define DSI_TCCR1_HSRD_TOCNT7_Pos (7U)
7979#define DSI_TCCR1_HSRD_TOCNT7_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT7_Pos) /*!< 0x00000080 */
7980#define DSI_TCCR1_HSRD_TOCNT7 DSI_TCCR1_HSRD_TOCNT7_Msk
7981#define DSI_TCCR1_HSRD_TOCNT8_Pos (8U)
7982#define DSI_TCCR1_HSRD_TOCNT8_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT8_Pos) /*!< 0x00000100 */
7983#define DSI_TCCR1_HSRD_TOCNT8 DSI_TCCR1_HSRD_TOCNT8_Msk
7984#define DSI_TCCR1_HSRD_TOCNT9_Pos (9U)
7985#define DSI_TCCR1_HSRD_TOCNT9_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT9_Pos) /*!< 0x00000200 */
7986#define DSI_TCCR1_HSRD_TOCNT9 DSI_TCCR1_HSRD_TOCNT9_Msk
7987#define DSI_TCCR1_HSRD_TOCNT10_Pos (10U)
7988#define DSI_TCCR1_HSRD_TOCNT10_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT10_Pos) /*!< 0x00000400 */
7989#define DSI_TCCR1_HSRD_TOCNT10 DSI_TCCR1_HSRD_TOCNT10_Msk
7990#define DSI_TCCR1_HSRD_TOCNT11_Pos (11U)
7991#define DSI_TCCR1_HSRD_TOCNT11_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT11_Pos) /*!< 0x00000800 */
7992#define DSI_TCCR1_HSRD_TOCNT11 DSI_TCCR1_HSRD_TOCNT11_Msk
7993#define DSI_TCCR1_HSRD_TOCNT12_Pos (12U)
7994#define DSI_TCCR1_HSRD_TOCNT12_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT12_Pos) /*!< 0x00001000 */
7995#define DSI_TCCR1_HSRD_TOCNT12 DSI_TCCR1_HSRD_TOCNT12_Msk
7996#define DSI_TCCR1_HSRD_TOCNT13_Pos (13U)
7997#define DSI_TCCR1_HSRD_TOCNT13_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT13_Pos) /*!< 0x00002000 */
7998#define DSI_TCCR1_HSRD_TOCNT13 DSI_TCCR1_HSRD_TOCNT13_Msk
7999#define DSI_TCCR1_HSRD_TOCNT14_Pos (14U)
8000#define DSI_TCCR1_HSRD_TOCNT14_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT14_Pos) /*!< 0x00004000 */
8001#define DSI_TCCR1_HSRD_TOCNT14 DSI_TCCR1_HSRD_TOCNT14_Msk
8002#define DSI_TCCR1_HSRD_TOCNT15_Pos (15U)
8003#define DSI_TCCR1_HSRD_TOCNT15_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT15_Pos) /*!< 0x00008000 */
8004#define DSI_TCCR1_HSRD_TOCNT15 DSI_TCCR1_HSRD_TOCNT15_Msk
8005
8006/******************* Bit definition for DSI_TCCR2 register **************/
8007#define DSI_TCCR2_LPRD_TOCNT_Pos (0U)
8008#define DSI_TCCR2_LPRD_TOCNT_Msk (0xFFFFU << DSI_TCCR2_LPRD_TOCNT_Pos) /*!< 0x0000FFFF */
8009#define DSI_TCCR2_LPRD_TOCNT DSI_TCCR2_LPRD_TOCNT_Msk /*!< Low-Power Read Timeout Counter */
8010#define DSI_TCCR2_LPRD_TOCNT0_Pos (0U)
8011#define DSI_TCCR2_LPRD_TOCNT0_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT0_Pos) /*!< 0x00000001 */
8012#define DSI_TCCR2_LPRD_TOCNT0 DSI_TCCR2_LPRD_TOCNT0_Msk
8013#define DSI_TCCR2_LPRD_TOCNT1_Pos (1U)
8014#define DSI_TCCR2_LPRD_TOCNT1_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT1_Pos) /*!< 0x00000002 */
8015#define DSI_TCCR2_LPRD_TOCNT1 DSI_TCCR2_LPRD_TOCNT1_Msk
8016#define DSI_TCCR2_LPRD_TOCNT2_Pos (2U)
8017#define DSI_TCCR2_LPRD_TOCNT2_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT2_Pos) /*!< 0x00000004 */
8018#define DSI_TCCR2_LPRD_TOCNT2 DSI_TCCR2_LPRD_TOCNT2_Msk
8019#define DSI_TCCR2_LPRD_TOCNT3_Pos (3U)
8020#define DSI_TCCR2_LPRD_TOCNT3_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT3_Pos) /*!< 0x00000008 */
8021#define DSI_TCCR2_LPRD_TOCNT3 DSI_TCCR2_LPRD_TOCNT3_Msk
8022#define DSI_TCCR2_LPRD_TOCNT4_Pos (4U)
8023#define DSI_TCCR2_LPRD_TOCNT4_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT4_Pos) /*!< 0x00000010 */
8024#define DSI_TCCR2_LPRD_TOCNT4 DSI_TCCR2_LPRD_TOCNT4_Msk
8025#define DSI_TCCR2_LPRD_TOCNT5_Pos (5U)
8026#define DSI_TCCR2_LPRD_TOCNT5_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT5_Pos) /*!< 0x00000020 */
8027#define DSI_TCCR2_LPRD_TOCNT5 DSI_TCCR2_LPRD_TOCNT5_Msk
8028#define DSI_TCCR2_LPRD_TOCNT6_Pos (6U)
8029#define DSI_TCCR2_LPRD_TOCNT6_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT6_Pos) /*!< 0x00000040 */
8030#define DSI_TCCR2_LPRD_TOCNT6 DSI_TCCR2_LPRD_TOCNT6_Msk
8031#define DSI_TCCR2_LPRD_TOCNT7_Pos (7U)
8032#define DSI_TCCR2_LPRD_TOCNT7_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT7_Pos) /*!< 0x00000080 */
8033#define DSI_TCCR2_LPRD_TOCNT7 DSI_TCCR2_LPRD_TOCNT7_Msk
8034#define DSI_TCCR2_LPRD_TOCNT8_Pos (8U)
8035#define DSI_TCCR2_LPRD_TOCNT8_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT8_Pos) /*!< 0x00000100 */
8036#define DSI_TCCR2_LPRD_TOCNT8 DSI_TCCR2_LPRD_TOCNT8_Msk
8037#define DSI_TCCR2_LPRD_TOCNT9_Pos (9U)
8038#define DSI_TCCR2_LPRD_TOCNT9_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT9_Pos) /*!< 0x00000200 */
8039#define DSI_TCCR2_LPRD_TOCNT9 DSI_TCCR2_LPRD_TOCNT9_Msk
8040#define DSI_TCCR2_LPRD_TOCNT10_Pos (10U)
8041#define DSI_TCCR2_LPRD_TOCNT10_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT10_Pos) /*!< 0x00000400 */
8042#define DSI_TCCR2_LPRD_TOCNT10 DSI_TCCR2_LPRD_TOCNT10_Msk
8043#define DSI_TCCR2_LPRD_TOCNT11_Pos (11U)
8044#define DSI_TCCR2_LPRD_TOCNT11_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT11_Pos) /*!< 0x00000800 */
8045#define DSI_TCCR2_LPRD_TOCNT11 DSI_TCCR2_LPRD_TOCNT11_Msk
8046#define DSI_TCCR2_LPRD_TOCNT12_Pos (12U)
8047#define DSI_TCCR2_LPRD_TOCNT12_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT12_Pos) /*!< 0x00001000 */
8048#define DSI_TCCR2_LPRD_TOCNT12 DSI_TCCR2_LPRD_TOCNT12_Msk
8049#define DSI_TCCR2_LPRD_TOCNT13_Pos (13U)
8050#define DSI_TCCR2_LPRD_TOCNT13_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT13_Pos) /*!< 0x00002000 */
8051#define DSI_TCCR2_LPRD_TOCNT13 DSI_TCCR2_LPRD_TOCNT13_Msk
8052#define DSI_TCCR2_LPRD_TOCNT14_Pos (14U)
8053#define DSI_TCCR2_LPRD_TOCNT14_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT14_Pos) /*!< 0x00004000 */
8054#define DSI_TCCR2_LPRD_TOCNT14 DSI_TCCR2_LPRD_TOCNT14_Msk
8055#define DSI_TCCR2_LPRD_TOCNT15_Pos (15U)
8056#define DSI_TCCR2_LPRD_TOCNT15_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT15_Pos) /*!< 0x00008000 */
8057#define DSI_TCCR2_LPRD_TOCNT15 DSI_TCCR2_LPRD_TOCNT15_Msk
8058
8059/******************* Bit definition for DSI_TCCR3 register **************/
8060#define DSI_TCCR3_HSWR_TOCNT_Pos (0U)
8061#define DSI_TCCR3_HSWR_TOCNT_Msk (0xFFFFU << DSI_TCCR3_HSWR_TOCNT_Pos) /*!< 0x0000FFFF */
8062#define DSI_TCCR3_HSWR_TOCNT DSI_TCCR3_HSWR_TOCNT_Msk /*!< High-Speed Write Timeout Counter */
8063#define DSI_TCCR3_HSWR_TOCNT0_Pos (0U)
8064#define DSI_TCCR3_HSWR_TOCNT0_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT0_Pos) /*!< 0x00000001 */
8065#define DSI_TCCR3_HSWR_TOCNT0 DSI_TCCR3_HSWR_TOCNT0_Msk
8066#define DSI_TCCR3_HSWR_TOCNT1_Pos (1U)
8067#define DSI_TCCR3_HSWR_TOCNT1_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT1_Pos) /*!< 0x00000002 */
8068#define DSI_TCCR3_HSWR_TOCNT1 DSI_TCCR3_HSWR_TOCNT1_Msk
8069#define DSI_TCCR3_HSWR_TOCNT2_Pos (2U)
8070#define DSI_TCCR3_HSWR_TOCNT2_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT2_Pos) /*!< 0x00000004 */
8071#define DSI_TCCR3_HSWR_TOCNT2 DSI_TCCR3_HSWR_TOCNT2_Msk
8072#define DSI_TCCR3_HSWR_TOCNT3_Pos (3U)
8073#define DSI_TCCR3_HSWR_TOCNT3_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT3_Pos) /*!< 0x00000008 */
8074#define DSI_TCCR3_HSWR_TOCNT3 DSI_TCCR3_HSWR_TOCNT3_Msk
8075#define DSI_TCCR3_HSWR_TOCNT4_Pos (4U)
8076#define DSI_TCCR3_HSWR_TOCNT4_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT4_Pos) /*!< 0x00000010 */
8077#define DSI_TCCR3_HSWR_TOCNT4 DSI_TCCR3_HSWR_TOCNT4_Msk
8078#define DSI_TCCR3_HSWR_TOCNT5_Pos (5U)
8079#define DSI_TCCR3_HSWR_TOCNT5_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT5_Pos) /*!< 0x00000020 */
8080#define DSI_TCCR3_HSWR_TOCNT5 DSI_TCCR3_HSWR_TOCNT5_Msk
8081#define DSI_TCCR3_HSWR_TOCNT6_Pos (6U)
8082#define DSI_TCCR3_HSWR_TOCNT6_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT6_Pos) /*!< 0x00000040 */
8083#define DSI_TCCR3_HSWR_TOCNT6 DSI_TCCR3_HSWR_TOCNT6_Msk
8084#define DSI_TCCR3_HSWR_TOCNT7_Pos (7U)
8085#define DSI_TCCR3_HSWR_TOCNT7_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT7_Pos) /*!< 0x00000080 */
8086#define DSI_TCCR3_HSWR_TOCNT7 DSI_TCCR3_HSWR_TOCNT7_Msk
8087#define DSI_TCCR3_HSWR_TOCNT8_Pos (8U)
8088#define DSI_TCCR3_HSWR_TOCNT8_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT8_Pos) /*!< 0x00000100 */
8089#define DSI_TCCR3_HSWR_TOCNT8 DSI_TCCR3_HSWR_TOCNT8_Msk
8090#define DSI_TCCR3_HSWR_TOCNT9_Pos (9U)
8091#define DSI_TCCR3_HSWR_TOCNT9_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT9_Pos) /*!< 0x00000200 */
8092#define DSI_TCCR3_HSWR_TOCNT9 DSI_TCCR3_HSWR_TOCNT9_Msk
8093#define DSI_TCCR3_HSWR_TOCNT10_Pos (10U)
8094#define DSI_TCCR3_HSWR_TOCNT10_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT10_Pos) /*!< 0x00000400 */
8095#define DSI_TCCR3_HSWR_TOCNT10 DSI_TCCR3_HSWR_TOCNT10_Msk
8096#define DSI_TCCR3_HSWR_TOCNT11_Pos (11U)
8097#define DSI_TCCR3_HSWR_TOCNT11_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT11_Pos) /*!< 0x00000800 */
8098#define DSI_TCCR3_HSWR_TOCNT11 DSI_TCCR3_HSWR_TOCNT11_Msk
8099#define DSI_TCCR3_HSWR_TOCNT12_Pos (12U)
8100#define DSI_TCCR3_HSWR_TOCNT12_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT12_Pos) /*!< 0x00001000 */
8101#define DSI_TCCR3_HSWR_TOCNT12 DSI_TCCR3_HSWR_TOCNT12_Msk
8102#define DSI_TCCR3_HSWR_TOCNT13_Pos (13U)
8103#define DSI_TCCR3_HSWR_TOCNT13_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT13_Pos) /*!< 0x00002000 */
8104#define DSI_TCCR3_HSWR_TOCNT13 DSI_TCCR3_HSWR_TOCNT13_Msk
8105#define DSI_TCCR3_HSWR_TOCNT14_Pos (14U)
8106#define DSI_TCCR3_HSWR_TOCNT14_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT14_Pos) /*!< 0x00004000 */
8107#define DSI_TCCR3_HSWR_TOCNT14 DSI_TCCR3_HSWR_TOCNT14_Msk
8108#define DSI_TCCR3_HSWR_TOCNT15_Pos (15U)
8109#define DSI_TCCR3_HSWR_TOCNT15_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT15_Pos) /*!< 0x00008000 */
8110#define DSI_TCCR3_HSWR_TOCNT15 DSI_TCCR3_HSWR_TOCNT15_Msk
8111
8112#define DSI_TCCR3_PM_Pos (24U)
8113#define DSI_TCCR3_PM_Msk (0x1U << DSI_TCCR3_PM_Pos) /*!< 0x01000000 */
8114#define DSI_TCCR3_PM DSI_TCCR3_PM_Msk /*!< Presp Mode */
8115
8116/******************* Bit definition for DSI_TCCR4 register **************/
8117#define DSI_TCCR4_LPWR_TOCNT_Pos (0U)
8118#define DSI_TCCR4_LPWR_TOCNT_Msk (0xFFFFU << DSI_TCCR4_LPWR_TOCNT_Pos) /*!< 0x0000FFFF */
8119#define DSI_TCCR4_LPWR_TOCNT DSI_TCCR4_LPWR_TOCNT_Msk /*!< Low-Power Write Timeout Counter */
8120#define DSI_TCCR4_LPWR_TOCNT0_Pos (0U)
8121#define DSI_TCCR4_LPWR_TOCNT0_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT0_Pos) /*!< 0x00000001 */
8122#define DSI_TCCR4_LPWR_TOCNT0 DSI_TCCR4_LPWR_TOCNT0_Msk
8123#define DSI_TCCR4_LPWR_TOCNT1_Pos (1U)
8124#define DSI_TCCR4_LPWR_TOCNT1_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT1_Pos) /*!< 0x00000002 */
8125#define DSI_TCCR4_LPWR_TOCNT1 DSI_TCCR4_LPWR_TOCNT1_Msk
8126#define DSI_TCCR4_LPWR_TOCNT2_Pos (2U)
8127#define DSI_TCCR4_LPWR_TOCNT2_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT2_Pos) /*!< 0x00000004 */
8128#define DSI_TCCR4_LPWR_TOCNT2 DSI_TCCR4_LPWR_TOCNT2_Msk
8129#define DSI_TCCR4_LPWR_TOCNT3_Pos (3U)
8130#define DSI_TCCR4_LPWR_TOCNT3_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT3_Pos) /*!< 0x00000008 */
8131#define DSI_TCCR4_LPWR_TOCNT3 DSI_TCCR4_LPWR_TOCNT3_Msk
8132#define DSI_TCCR4_LPWR_TOCNT4_Pos (4U)
8133#define DSI_TCCR4_LPWR_TOCNT4_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT4_Pos) /*!< 0x00000010 */
8134#define DSI_TCCR4_LPWR_TOCNT4 DSI_TCCR4_LPWR_TOCNT4_Msk
8135#define DSI_TCCR4_LPWR_TOCNT5_Pos (5U)
8136#define DSI_TCCR4_LPWR_TOCNT5_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT5_Pos) /*!< 0x00000020 */
8137#define DSI_TCCR4_LPWR_TOCNT5 DSI_TCCR4_LPWR_TOCNT5_Msk
8138#define DSI_TCCR4_LPWR_TOCNT6_Pos (6U)
8139#define DSI_TCCR4_LPWR_TOCNT6_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT6_Pos) /*!< 0x00000040 */
8140#define DSI_TCCR4_LPWR_TOCNT6 DSI_TCCR4_LPWR_TOCNT6_Msk
8141#define DSI_TCCR4_LPWR_TOCNT7_Pos (7U)
8142#define DSI_TCCR4_LPWR_TOCNT7_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT7_Pos) /*!< 0x00000080 */
8143#define DSI_TCCR4_LPWR_TOCNT7 DSI_TCCR4_LPWR_TOCNT7_Msk
8144#define DSI_TCCR4_LPWR_TOCNT8_Pos (8U)
8145#define DSI_TCCR4_LPWR_TOCNT8_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT8_Pos) /*!< 0x00000100 */
8146#define DSI_TCCR4_LPWR_TOCNT8 DSI_TCCR4_LPWR_TOCNT8_Msk
8147#define DSI_TCCR4_LPWR_TOCNT9_Pos (9U)
8148#define DSI_TCCR4_LPWR_TOCNT9_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT9_Pos) /*!< 0x00000200 */
8149#define DSI_TCCR4_LPWR_TOCNT9 DSI_TCCR4_LPWR_TOCNT9_Msk
8150#define DSI_TCCR4_LPWR_TOCNT10_Pos (10U)
8151#define DSI_TCCR4_LPWR_TOCNT10_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT10_Pos) /*!< 0x00000400 */
8152#define DSI_TCCR4_LPWR_TOCNT10 DSI_TCCR4_LPWR_TOCNT10_Msk
8153#define DSI_TCCR4_LPWR_TOCNT11_Pos (11U)
8154#define DSI_TCCR4_LPWR_TOCNT11_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT11_Pos) /*!< 0x00000800 */
8155#define DSI_TCCR4_LPWR_TOCNT11 DSI_TCCR4_LPWR_TOCNT11_Msk
8156#define DSI_TCCR4_LPWR_TOCNT12_Pos (12U)
8157#define DSI_TCCR4_LPWR_TOCNT12_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT12_Pos) /*!< 0x00001000 */
8158#define DSI_TCCR4_LPWR_TOCNT12 DSI_TCCR4_LPWR_TOCNT12_Msk
8159#define DSI_TCCR4_LPWR_TOCNT13_Pos (13U)
8160#define DSI_TCCR4_LPWR_TOCNT13_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT13_Pos) /*!< 0x00002000 */
8161#define DSI_TCCR4_LPWR_TOCNT13 DSI_TCCR4_LPWR_TOCNT13_Msk
8162#define DSI_TCCR4_LPWR_TOCNT14_Pos (14U)
8163#define DSI_TCCR4_LPWR_TOCNT14_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT14_Pos) /*!< 0x00004000 */
8164#define DSI_TCCR4_LPWR_TOCNT14 DSI_TCCR4_LPWR_TOCNT14_Msk
8165#define DSI_TCCR4_LPWR_TOCNT15_Pos (15U)
8166#define DSI_TCCR4_LPWR_TOCNT15_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT15_Pos) /*!< 0x00008000 */
8167#define DSI_TCCR4_LPWR_TOCNT15 DSI_TCCR4_LPWR_TOCNT15_Msk
8168
8169/******************* Bit definition for DSI_TCCR5 register **************/
8170#define DSI_TCCR5_BTA_TOCNT_Pos (0U)
8171#define DSI_TCCR5_BTA_TOCNT_Msk (0xFFFFU << DSI_TCCR5_BTA_TOCNT_Pos) /*!< 0x0000FFFF */
8172#define DSI_TCCR5_BTA_TOCNT DSI_TCCR5_BTA_TOCNT_Msk /*!< Bus-Turn-Around Timeout Counter */
8173#define DSI_TCCR5_BTA_TOCNT0_Pos (0U)
8174#define DSI_TCCR5_BTA_TOCNT0_Msk (0x1U << DSI_TCCR5_BTA_TOCNT0_Pos) /*!< 0x00000001 */
8175#define DSI_TCCR5_BTA_TOCNT0 DSI_TCCR5_BTA_TOCNT0_Msk
8176#define DSI_TCCR5_BTA_TOCNT1_Pos (1U)
8177#define DSI_TCCR5_BTA_TOCNT1_Msk (0x1U << DSI_TCCR5_BTA_TOCNT1_Pos) /*!< 0x00000002 */
8178#define DSI_TCCR5_BTA_TOCNT1 DSI_TCCR5_BTA_TOCNT1_Msk
8179#define DSI_TCCR5_BTA_TOCNT2_Pos (2U)
8180#define DSI_TCCR5_BTA_TOCNT2_Msk (0x1U << DSI_TCCR5_BTA_TOCNT2_Pos) /*!< 0x00000004 */
8181#define DSI_TCCR5_BTA_TOCNT2 DSI_TCCR5_BTA_TOCNT2_Msk
8182#define DSI_TCCR5_BTA_TOCNT3_Pos (3U)
8183#define DSI_TCCR5_BTA_TOCNT3_Msk (0x1U << DSI_TCCR5_BTA_TOCNT3_Pos) /*!< 0x00000008 */
8184#define DSI_TCCR5_BTA_TOCNT3 DSI_TCCR5_BTA_TOCNT3_Msk
8185#define DSI_TCCR5_BTA_TOCNT4_Pos (4U)
8186#define DSI_TCCR5_BTA_TOCNT4_Msk (0x1U << DSI_TCCR5_BTA_TOCNT4_Pos) /*!< 0x00000010 */
8187#define DSI_TCCR5_BTA_TOCNT4 DSI_TCCR5_BTA_TOCNT4_Msk
8188#define DSI_TCCR5_BTA_TOCNT5_Pos (5U)
8189#define DSI_TCCR5_BTA_TOCNT5_Msk (0x1U << DSI_TCCR5_BTA_TOCNT5_Pos) /*!< 0x00000020 */
8190#define DSI_TCCR5_BTA_TOCNT5 DSI_TCCR5_BTA_TOCNT5_Msk
8191#define DSI_TCCR5_BTA_TOCNT6_Pos (6U)
8192#define DSI_TCCR5_BTA_TOCNT6_Msk (0x1U << DSI_TCCR5_BTA_TOCNT6_Pos) /*!< 0x00000040 */
8193#define DSI_TCCR5_BTA_TOCNT6 DSI_TCCR5_BTA_TOCNT6_Msk
8194#define DSI_TCCR5_BTA_TOCNT7_Pos (7U)
8195#define DSI_TCCR5_BTA_TOCNT7_Msk (0x1U << DSI_TCCR5_BTA_TOCNT7_Pos) /*!< 0x00000080 */
8196#define DSI_TCCR5_BTA_TOCNT7 DSI_TCCR5_BTA_TOCNT7_Msk
8197#define DSI_TCCR5_BTA_TOCNT8_Pos (8U)
8198#define DSI_TCCR5_BTA_TOCNT8_Msk (0x1U << DSI_TCCR5_BTA_TOCNT8_Pos) /*!< 0x00000100 */
8199#define DSI_TCCR5_BTA_TOCNT8 DSI_TCCR5_BTA_TOCNT8_Msk
8200#define DSI_TCCR5_BTA_TOCNT9_Pos (9U)
8201#define DSI_TCCR5_BTA_TOCNT9_Msk (0x1U << DSI_TCCR5_BTA_TOCNT9_Pos) /*!< 0x00000200 */
8202#define DSI_TCCR5_BTA_TOCNT9 DSI_TCCR5_BTA_TOCNT9_Msk
8203#define DSI_TCCR5_BTA_TOCNT10_Pos (10U)
8204#define DSI_TCCR5_BTA_TOCNT10_Msk (0x1U << DSI_TCCR5_BTA_TOCNT10_Pos) /*!< 0x00000400 */
8205#define DSI_TCCR5_BTA_TOCNT10 DSI_TCCR5_BTA_TOCNT10_Msk
8206#define DSI_TCCR5_BTA_TOCNT11_Pos (11U)
8207#define DSI_TCCR5_BTA_TOCNT11_Msk (0x1U << DSI_TCCR5_BTA_TOCNT11_Pos) /*!< 0x00000800 */
8208#define DSI_TCCR5_BTA_TOCNT11 DSI_TCCR5_BTA_TOCNT11_Msk
8209#define DSI_TCCR5_BTA_TOCNT12_Pos (12U)
8210#define DSI_TCCR5_BTA_TOCNT12_Msk (0x1U << DSI_TCCR5_BTA_TOCNT12_Pos) /*!< 0x00001000 */
8211#define DSI_TCCR5_BTA_TOCNT12 DSI_TCCR5_BTA_TOCNT12_Msk
8212#define DSI_TCCR5_BTA_TOCNT13_Pos (13U)
8213#define DSI_TCCR5_BTA_TOCNT13_Msk (0x1U << DSI_TCCR5_BTA_TOCNT13_Pos) /*!< 0x00002000 */
8214#define DSI_TCCR5_BTA_TOCNT13 DSI_TCCR5_BTA_TOCNT13_Msk
8215#define DSI_TCCR5_BTA_TOCNT14_Pos (14U)
8216#define DSI_TCCR5_BTA_TOCNT14_Msk (0x1U << DSI_TCCR5_BTA_TOCNT14_Pos) /*!< 0x00004000 */
8217#define DSI_TCCR5_BTA_TOCNT14 DSI_TCCR5_BTA_TOCNT14_Msk
8218#define DSI_TCCR5_BTA_TOCNT15_Pos (15U)
8219#define DSI_TCCR5_BTA_TOCNT15_Msk (0x1U << DSI_TCCR5_BTA_TOCNT15_Pos) /*!< 0x00008000 */
8220#define DSI_TCCR5_BTA_TOCNT15 DSI_TCCR5_BTA_TOCNT15_Msk
8221
8222/******************* Bit definition for DSI_TDCR register ***************/
8223#define DSI_TDCR_3DM 0x00000003U /*!< 3D Mode */
8224#define DSI_TDCR_3DM0 0x00000001U
8225#define DSI_TDCR_3DM1 0x00000002U
8226
8227#define DSI_TDCR_3DF 0x0000000CU /*!< 3D Format */
8228#define DSI_TDCR_3DF0 0x00000004U
8229#define DSI_TDCR_3DF1 0x00000008U
8230
8231#define DSI_TDCR_SVS_Pos (4U)
8232#define DSI_TDCR_SVS_Msk (0x1U << DSI_TDCR_SVS_Pos) /*!< 0x00000010 */
8233#define DSI_TDCR_SVS DSI_TDCR_SVS_Msk /*!< Second VSYNC */
8234#define DSI_TDCR_RF_Pos (5U)
8235#define DSI_TDCR_RF_Msk (0x1U << DSI_TDCR_RF_Pos) /*!< 0x00000020 */
8236#define DSI_TDCR_RF DSI_TDCR_RF_Msk /*!< Right First */
8237#define DSI_TDCR_S3DC_Pos (16U)
8238#define DSI_TDCR_S3DC_Msk (0x1U << DSI_TDCR_S3DC_Pos) /*!< 0x00010000 */
8239#define DSI_TDCR_S3DC DSI_TDCR_S3DC_Msk /*!< Send 3D Control */
8240
8241/******************* Bit definition for DSI_CLCR register ***************/
8242#define DSI_CLCR_DPCC_Pos (0U)
8243#define DSI_CLCR_DPCC_Msk (0x1U << DSI_CLCR_DPCC_Pos) /*!< 0x00000001 */
8244#define DSI_CLCR_DPCC DSI_CLCR_DPCC_Msk /*!< D-PHY Clock Control */
8245#define DSI_CLCR_ACR_Pos (1U)
8246#define DSI_CLCR_ACR_Msk (0x1U << DSI_CLCR_ACR_Pos) /*!< 0x00000002 */
8247#define DSI_CLCR_ACR DSI_CLCR_ACR_Msk /*!< Automatic Clocklane Control */
8248
8249/******************* Bit definition for DSI_CLTCR register **************/
8250#define DSI_CLTCR_LP2HS_TIME_Pos (0U)
8251#define DSI_CLTCR_LP2HS_TIME_Msk (0x3FFU << DSI_CLTCR_LP2HS_TIME_Pos) /*!< 0x000003FF */
8252#define DSI_CLTCR_LP2HS_TIME DSI_CLTCR_LP2HS_TIME_Msk /*!< Low-Power to High-Speed Time */
8253#define DSI_CLTCR_LP2HS_TIME0_Pos (0U)
8254#define DSI_CLTCR_LP2HS_TIME0_Msk (0x1U << DSI_CLTCR_LP2HS_TIME0_Pos) /*!< 0x00000001 */
8255#define DSI_CLTCR_LP2HS_TIME0 DSI_CLTCR_LP2HS_TIME0_Msk
8256#define DSI_CLTCR_LP2HS_TIME1_Pos (1U)
8257#define DSI_CLTCR_LP2HS_TIME1_Msk (0x1U << DSI_CLTCR_LP2HS_TIME1_Pos) /*!< 0x00000002 */
8258#define DSI_CLTCR_LP2HS_TIME1 DSI_CLTCR_LP2HS_TIME1_Msk
8259#define DSI_CLTCR_LP2HS_TIME2_Pos (2U)
8260#define DSI_CLTCR_LP2HS_TIME2_Msk (0x1U << DSI_CLTCR_LP2HS_TIME2_Pos) /*!< 0x00000004 */
8261#define DSI_CLTCR_LP2HS_TIME2 DSI_CLTCR_LP2HS_TIME2_Msk
8262#define DSI_CLTCR_LP2HS_TIME3_Pos (3U)
8263#define DSI_CLTCR_LP2HS_TIME3_Msk (0x1U << DSI_CLTCR_LP2HS_TIME3_Pos) /*!< 0x00000008 */
8264#define DSI_CLTCR_LP2HS_TIME3 DSI_CLTCR_LP2HS_TIME3_Msk
8265#define DSI_CLTCR_LP2HS_TIME4_Pos (4U)
8266#define DSI_CLTCR_LP2HS_TIME4_Msk (0x1U << DSI_CLTCR_LP2HS_TIME4_Pos) /*!< 0x00000010 */
8267#define DSI_CLTCR_LP2HS_TIME4 DSI_CLTCR_LP2HS_TIME4_Msk
8268#define DSI_CLTCR_LP2HS_TIME5_Pos (5U)
8269#define DSI_CLTCR_LP2HS_TIME5_Msk (0x1U << DSI_CLTCR_LP2HS_TIME5_Pos) /*!< 0x00000020 */
8270#define DSI_CLTCR_LP2HS_TIME5 DSI_CLTCR_LP2HS_TIME5_Msk
8271#define DSI_CLTCR_LP2HS_TIME6_Pos (6U)
8272#define DSI_CLTCR_LP2HS_TIME6_Msk (0x1U << DSI_CLTCR_LP2HS_TIME6_Pos) /*!< 0x00000040 */
8273#define DSI_CLTCR_LP2HS_TIME6 DSI_CLTCR_LP2HS_TIME6_Msk
8274#define DSI_CLTCR_LP2HS_TIME7_Pos (7U)
8275#define DSI_CLTCR_LP2HS_TIME7_Msk (0x1U << DSI_CLTCR_LP2HS_TIME7_Pos) /*!< 0x00000080 */
8276#define DSI_CLTCR_LP2HS_TIME7 DSI_CLTCR_LP2HS_TIME7_Msk
8277#define DSI_CLTCR_LP2HS_TIME8_Pos (8U)
8278#define DSI_CLTCR_LP2HS_TIME8_Msk (0x1U << DSI_CLTCR_LP2HS_TIME8_Pos) /*!< 0x00000100 */
8279#define DSI_CLTCR_LP2HS_TIME8 DSI_CLTCR_LP2HS_TIME8_Msk
8280#define DSI_CLTCR_LP2HS_TIME9_Pos (9U)
8281#define DSI_CLTCR_LP2HS_TIME9_Msk (0x1U << DSI_CLTCR_LP2HS_TIME9_Pos) /*!< 0x00000200 */
8282#define DSI_CLTCR_LP2HS_TIME9 DSI_CLTCR_LP2HS_TIME9_Msk
8283
8284#define DSI_CLTCR_HS2LP_TIME_Pos (16U)
8285#define DSI_CLTCR_HS2LP_TIME_Msk (0x3FFU << DSI_CLTCR_HS2LP_TIME_Pos) /*!< 0x03FF0000 */
8286#define DSI_CLTCR_HS2LP_TIME DSI_CLTCR_HS2LP_TIME_Msk /*!< High-Speed to Low-Power Time */
8287#define DSI_CLTCR_HS2LP_TIME0_Pos (16U)
8288#define DSI_CLTCR_HS2LP_TIME0_Msk (0x1U << DSI_CLTCR_HS2LP_TIME0_Pos) /*!< 0x00010000 */
8289#define DSI_CLTCR_HS2LP_TIME0 DSI_CLTCR_HS2LP_TIME0_Msk
8290#define DSI_CLTCR_HS2LP_TIME1_Pos (17U)
8291#define DSI_CLTCR_HS2LP_TIME1_Msk (0x1U << DSI_CLTCR_HS2LP_TIME1_Pos) /*!< 0x00020000 */
8292#define DSI_CLTCR_HS2LP_TIME1 DSI_CLTCR_HS2LP_TIME1_Msk
8293#define DSI_CLTCR_HS2LP_TIME2_Pos (18U)
8294#define DSI_CLTCR_HS2LP_TIME2_Msk (0x1U << DSI_CLTCR_HS2LP_TIME2_Pos) /*!< 0x00040000 */
8295#define DSI_CLTCR_HS2LP_TIME2 DSI_CLTCR_HS2LP_TIME2_Msk
8296#define DSI_CLTCR_HS2LP_TIME3_Pos (19U)
8297#define DSI_CLTCR_HS2LP_TIME3_Msk (0x1U << DSI_CLTCR_HS2LP_TIME3_Pos) /*!< 0x00080000 */
8298#define DSI_CLTCR_HS2LP_TIME3 DSI_CLTCR_HS2LP_TIME3_Msk
8299#define DSI_CLTCR_HS2LP_TIME4_Pos (20U)
8300#define DSI_CLTCR_HS2LP_TIME4_Msk (0x1U << DSI_CLTCR_HS2LP_TIME4_Pos) /*!< 0x00100000 */
8301#define DSI_CLTCR_HS2LP_TIME4 DSI_CLTCR_HS2LP_TIME4_Msk
8302#define DSI_CLTCR_HS2LP_TIME5_Pos (21U)
8303#define DSI_CLTCR_HS2LP_TIME5_Msk (0x1U << DSI_CLTCR_HS2LP_TIME5_Pos) /*!< 0x00200000 */
8304#define DSI_CLTCR_HS2LP_TIME5 DSI_CLTCR_HS2LP_TIME5_Msk
8305#define DSI_CLTCR_HS2LP_TIME6_Pos (22U)
8306#define DSI_CLTCR_HS2LP_TIME6_Msk (0x1U << DSI_CLTCR_HS2LP_TIME6_Pos) /*!< 0x00400000 */
8307#define DSI_CLTCR_HS2LP_TIME6 DSI_CLTCR_HS2LP_TIME6_Msk
8308#define DSI_CLTCR_HS2LP_TIME7_Pos (23U)
8309#define DSI_CLTCR_HS2LP_TIME7_Msk (0x1U << DSI_CLTCR_HS2LP_TIME7_Pos) /*!< 0x00800000 */
8310#define DSI_CLTCR_HS2LP_TIME7 DSI_CLTCR_HS2LP_TIME7_Msk
8311#define DSI_CLTCR_HS2LP_TIME8_Pos (24U)
8312#define DSI_CLTCR_HS2LP_TIME8_Msk (0x1U << DSI_CLTCR_HS2LP_TIME8_Pos) /*!< 0x01000000 */
8313#define DSI_CLTCR_HS2LP_TIME8 DSI_CLTCR_HS2LP_TIME8_Msk
8314#define DSI_CLTCR_HS2LP_TIME9_Pos (25U)
8315#define DSI_CLTCR_HS2LP_TIME9_Msk (0x1U << DSI_CLTCR_HS2LP_TIME9_Pos) /*!< 0x02000000 */
8316#define DSI_CLTCR_HS2LP_TIME9 DSI_CLTCR_HS2LP_TIME9_Msk
8317
8318/******************* Bit definition for DSI_DLTCR register **************/
8319#define DSI_DLTCR_MRD_TIME_Pos (0U)
8320#define DSI_DLTCR_MRD_TIME_Msk (0x7FFFU << DSI_DLTCR_MRD_TIME_Pos) /*!< 0x00007FFF */
8321#define DSI_DLTCR_MRD_TIME DSI_DLTCR_MRD_TIME_Msk /*!< Maximum Read Time */
8322#define DSI_DLTCR_MRD_TIME0_Pos (0U)
8323#define DSI_DLTCR_MRD_TIME0_Msk (0x1U << DSI_DLTCR_MRD_TIME0_Pos) /*!< 0x00000001 */
8324#define DSI_DLTCR_MRD_TIME0 DSI_DLTCR_MRD_TIME0_Msk
8325#define DSI_DLTCR_MRD_TIME1_Pos (1U)
8326#define DSI_DLTCR_MRD_TIME1_Msk (0x1U << DSI_DLTCR_MRD_TIME1_Pos) /*!< 0x00000002 */
8327#define DSI_DLTCR_MRD_TIME1 DSI_DLTCR_MRD_TIME1_Msk
8328#define DSI_DLTCR_MRD_TIME2_Pos (2U)
8329#define DSI_DLTCR_MRD_TIME2_Msk (0x1U << DSI_DLTCR_MRD_TIME2_Pos) /*!< 0x00000004 */
8330#define DSI_DLTCR_MRD_TIME2 DSI_DLTCR_MRD_TIME2_Msk
8331#define DSI_DLTCR_MRD_TIME3_Pos (3U)
8332#define DSI_DLTCR_MRD_TIME3_Msk (0x1U << DSI_DLTCR_MRD_TIME3_Pos) /*!< 0x00000008 */
8333#define DSI_DLTCR_MRD_TIME3 DSI_DLTCR_MRD_TIME3_Msk
8334#define DSI_DLTCR_MRD_TIME4_Pos (4U)
8335#define DSI_DLTCR_MRD_TIME4_Msk (0x1U << DSI_DLTCR_MRD_TIME4_Pos) /*!< 0x00000010 */
8336#define DSI_DLTCR_MRD_TIME4 DSI_DLTCR_MRD_TIME4_Msk
8337#define DSI_DLTCR_MRD_TIME5_Pos (5U)
8338#define DSI_DLTCR_MRD_TIME5_Msk (0x1U << DSI_DLTCR_MRD_TIME5_Pos) /*!< 0x00000020 */
8339#define DSI_DLTCR_MRD_TIME5 DSI_DLTCR_MRD_TIME5_Msk
8340#define DSI_DLTCR_MRD_TIME6_Pos (6U)
8341#define DSI_DLTCR_MRD_TIME6_Msk (0x1U << DSI_DLTCR_MRD_TIME6_Pos) /*!< 0x00000040 */
8342#define DSI_DLTCR_MRD_TIME6 DSI_DLTCR_MRD_TIME6_Msk
8343#define DSI_DLTCR_MRD_TIME7_Pos (7U)
8344#define DSI_DLTCR_MRD_TIME7_Msk (0x1U << DSI_DLTCR_MRD_TIME7_Pos) /*!< 0x00000080 */
8345#define DSI_DLTCR_MRD_TIME7 DSI_DLTCR_MRD_TIME7_Msk
8346#define DSI_DLTCR_MRD_TIME8_Pos (8U)
8347#define DSI_DLTCR_MRD_TIME8_Msk (0x1U << DSI_DLTCR_MRD_TIME8_Pos) /*!< 0x00000100 */
8348#define DSI_DLTCR_MRD_TIME8 DSI_DLTCR_MRD_TIME8_Msk
8349#define DSI_DLTCR_MRD_TIME9_Pos (9U)
8350#define DSI_DLTCR_MRD_TIME9_Msk (0x1U << DSI_DLTCR_MRD_TIME9_Pos) /*!< 0x00000200 */
8351#define DSI_DLTCR_MRD_TIME9 DSI_DLTCR_MRD_TIME9_Msk
8352#define DSI_DLTCR_MRD_TIME10_Pos (10U)
8353#define DSI_DLTCR_MRD_TIME10_Msk (0x1U << DSI_DLTCR_MRD_TIME10_Pos) /*!< 0x00000400 */
8354#define DSI_DLTCR_MRD_TIME10 DSI_DLTCR_MRD_TIME10_Msk
8355#define DSI_DLTCR_MRD_TIME11_Pos (11U)
8356#define DSI_DLTCR_MRD_TIME11_Msk (0x1U << DSI_DLTCR_MRD_TIME11_Pos) /*!< 0x00000800 */
8357#define DSI_DLTCR_MRD_TIME11 DSI_DLTCR_MRD_TIME11_Msk
8358#define DSI_DLTCR_MRD_TIME12_Pos (12U)
8359#define DSI_DLTCR_MRD_TIME12_Msk (0x1U << DSI_DLTCR_MRD_TIME12_Pos) /*!< 0x00001000 */
8360#define DSI_DLTCR_MRD_TIME12 DSI_DLTCR_MRD_TIME12_Msk
8361#define DSI_DLTCR_MRD_TIME13_Pos (13U)
8362#define DSI_DLTCR_MRD_TIME13_Msk (0x1U << DSI_DLTCR_MRD_TIME13_Pos) /*!< 0x00002000 */
8363#define DSI_DLTCR_MRD_TIME13 DSI_DLTCR_MRD_TIME13_Msk
8364#define DSI_DLTCR_MRD_TIME14_Pos (14U)
8365#define DSI_DLTCR_MRD_TIME14_Msk (0x1U << DSI_DLTCR_MRD_TIME14_Pos) /*!< 0x00004000 */
8366#define DSI_DLTCR_MRD_TIME14 DSI_DLTCR_MRD_TIME14_Msk
8367
8368#define DSI_DLTCR_LP2HS_TIME_Pos (16U)
8369#define DSI_DLTCR_LP2HS_TIME_Msk (0xFFU << DSI_DLTCR_LP2HS_TIME_Pos) /*!< 0x00FF0000 */
8370#define DSI_DLTCR_LP2HS_TIME DSI_DLTCR_LP2HS_TIME_Msk /*!< Low-Power To High-Speed Time */
8371#define DSI_DLTCR_LP2HS_TIME0_Pos (16U)
8372#define DSI_DLTCR_LP2HS_TIME0_Msk (0x1U << DSI_DLTCR_LP2HS_TIME0_Pos) /*!< 0x00010000 */
8373#define DSI_DLTCR_LP2HS_TIME0 DSI_DLTCR_LP2HS_TIME0_Msk
8374#define DSI_DLTCR_LP2HS_TIME1_Pos (17U)
8375#define DSI_DLTCR_LP2HS_TIME1_Msk (0x1U << DSI_DLTCR_LP2HS_TIME1_Pos) /*!< 0x00020000 */
8376#define DSI_DLTCR_LP2HS_TIME1 DSI_DLTCR_LP2HS_TIME1_Msk
8377#define DSI_DLTCR_LP2HS_TIME2_Pos (18U)
8378#define DSI_DLTCR_LP2HS_TIME2_Msk (0x1U << DSI_DLTCR_LP2HS_TIME2_Pos) /*!< 0x00040000 */
8379#define DSI_DLTCR_LP2HS_TIME2 DSI_DLTCR_LP2HS_TIME2_Msk
8380#define DSI_DLTCR_LP2HS_TIME3_Pos (19U)
8381#define DSI_DLTCR_LP2HS_TIME3_Msk (0x1U << DSI_DLTCR_LP2HS_TIME3_Pos) /*!< 0x00080000 */
8382#define DSI_DLTCR_LP2HS_TIME3 DSI_DLTCR_LP2HS_TIME3_Msk
8383#define DSI_DLTCR_LP2HS_TIME4_Pos (20U)
8384#define DSI_DLTCR_LP2HS_TIME4_Msk (0x1U << DSI_DLTCR_LP2HS_TIME4_Pos) /*!< 0x00100000 */
8385#define DSI_DLTCR_LP2HS_TIME4 DSI_DLTCR_LP2HS_TIME4_Msk
8386#define DSI_DLTCR_LP2HS_TIME5_Pos (21U)
8387#define DSI_DLTCR_LP2HS_TIME5_Msk (0x1U << DSI_DLTCR_LP2HS_TIME5_Pos) /*!< 0x00200000 */
8388#define DSI_DLTCR_LP2HS_TIME5 DSI_DLTCR_LP2HS_TIME5_Msk
8389#define DSI_DLTCR_LP2HS_TIME6_Pos (22U)
8390#define DSI_DLTCR_LP2HS_TIME6_Msk (0x1U << DSI_DLTCR_LP2HS_TIME6_Pos) /*!< 0x00400000 */
8391#define DSI_DLTCR_LP2HS_TIME6 DSI_DLTCR_LP2HS_TIME6_Msk
8392#define DSI_DLTCR_LP2HS_TIME7_Pos (23U)
8393#define DSI_DLTCR_LP2HS_TIME7_Msk (0x1U << DSI_DLTCR_LP2HS_TIME7_Pos) /*!< 0x00800000 */
8394#define DSI_DLTCR_LP2HS_TIME7 DSI_DLTCR_LP2HS_TIME7_Msk
8395
8396#define DSI_DLTCR_HS2LP_TIME_Pos (24U)
8397#define DSI_DLTCR_HS2LP_TIME_Msk (0xFFU << DSI_DLTCR_HS2LP_TIME_Pos) /*!< 0xFF000000 */
8398#define DSI_DLTCR_HS2LP_TIME DSI_DLTCR_HS2LP_TIME_Msk /*!< High-Speed To Low-Power Time */
8399#define DSI_DLTCR_HS2LP_TIME0_Pos (24U)
8400#define DSI_DLTCR_HS2LP_TIME0_Msk (0x1U << DSI_DLTCR_HS2LP_TIME0_Pos) /*!< 0x01000000 */
8401#define DSI_DLTCR_HS2LP_TIME0 DSI_DLTCR_HS2LP_TIME0_Msk
8402#define DSI_DLTCR_HS2LP_TIME1_Pos (25U)
8403#define DSI_DLTCR_HS2LP_TIME1_Msk (0x1U << DSI_DLTCR_HS2LP_TIME1_Pos) /*!< 0x02000000 */
8404#define DSI_DLTCR_HS2LP_TIME1 DSI_DLTCR_HS2LP_TIME1_Msk
8405#define DSI_DLTCR_HS2LP_TIME2_Pos (26U)
8406#define DSI_DLTCR_HS2LP_TIME2_Msk (0x1U << DSI_DLTCR_HS2LP_TIME2_Pos) /*!< 0x04000000 */
8407#define DSI_DLTCR_HS2LP_TIME2 DSI_DLTCR_HS2LP_TIME2_Msk
8408#define DSI_DLTCR_HS2LP_TIME3_Pos (27U)
8409#define DSI_DLTCR_HS2LP_TIME3_Msk (0x1U << DSI_DLTCR_HS2LP_TIME3_Pos) /*!< 0x08000000 */
8410#define DSI_DLTCR_HS2LP_TIME3 DSI_DLTCR_HS2LP_TIME3_Msk
8411#define DSI_DLTCR_HS2LP_TIME4_Pos (28U)
8412#define DSI_DLTCR_HS2LP_TIME4_Msk (0x1U << DSI_DLTCR_HS2LP_TIME4_Pos) /*!< 0x10000000 */
8413#define DSI_DLTCR_HS2LP_TIME4 DSI_DLTCR_HS2LP_TIME4_Msk
8414#define DSI_DLTCR_HS2LP_TIME5_Pos (29U)
8415#define DSI_DLTCR_HS2LP_TIME5_Msk (0x1U << DSI_DLTCR_HS2LP_TIME5_Pos) /*!< 0x20000000 */
8416#define DSI_DLTCR_HS2LP_TIME5 DSI_DLTCR_HS2LP_TIME5_Msk
8417#define DSI_DLTCR_HS2LP_TIME6_Pos (30U)
8418#define DSI_DLTCR_HS2LP_TIME6_Msk (0x1U << DSI_DLTCR_HS2LP_TIME6_Pos) /*!< 0x40000000 */
8419#define DSI_DLTCR_HS2LP_TIME6 DSI_DLTCR_HS2LP_TIME6_Msk
8420#define DSI_DLTCR_HS2LP_TIME7_Pos (31U)
8421#define DSI_DLTCR_HS2LP_TIME7_Msk (0x1U << DSI_DLTCR_HS2LP_TIME7_Pos) /*!< 0x80000000 */
8422#define DSI_DLTCR_HS2LP_TIME7 DSI_DLTCR_HS2LP_TIME7_Msk
8423
8424/******************* Bit definition for DSI_PCTLR register **************/
8425#define DSI_PCTLR_DEN_Pos (1U)
8426#define DSI_PCTLR_DEN_Msk (0x1U << DSI_PCTLR_DEN_Pos) /*!< 0x00000002 */
8427#define DSI_PCTLR_DEN DSI_PCTLR_DEN_Msk /*!< Digital Enable */
8428#define DSI_PCTLR_CKE_Pos (2U)
8429#define DSI_PCTLR_CKE_Msk (0x1U << DSI_PCTLR_CKE_Pos) /*!< 0x00000004 */
8430#define DSI_PCTLR_CKE DSI_PCTLR_CKE_Msk /*!< Clock Enable */
8431
8432/******************* Bit definition for DSI_PCONFR register *************/
8433#define DSI_PCONFR_NL_Pos (0U)
8434#define DSI_PCONFR_NL_Msk (0x3U << DSI_PCONFR_NL_Pos) /*!< 0x00000003 */
8435#define DSI_PCONFR_NL DSI_PCONFR_NL_Msk /*!< Number of Lanes */
8436#define DSI_PCONFR_NL0_Pos (0U)
8437#define DSI_PCONFR_NL0_Msk (0x1U << DSI_PCONFR_NL0_Pos) /*!< 0x00000001 */
8438#define DSI_PCONFR_NL0 DSI_PCONFR_NL0_Msk
8439#define DSI_PCONFR_NL1_Pos (1U)
8440#define DSI_PCONFR_NL1_Msk (0x1U << DSI_PCONFR_NL1_Pos) /*!< 0x00000002 */
8441#define DSI_PCONFR_NL1 DSI_PCONFR_NL1_Msk
8442
8443#define DSI_PCONFR_SW_TIME_Pos (8U)
8444#define DSI_PCONFR_SW_TIME_Msk (0xFFU << DSI_PCONFR_SW_TIME_Pos) /*!< 0x0000FF00 */
8445#define DSI_PCONFR_SW_TIME DSI_PCONFR_SW_TIME_Msk /*!< Stop Wait Time */
8446#define DSI_PCONFR_SW_TIME0_Pos (8U)
8447#define DSI_PCONFR_SW_TIME0_Msk (0x1U << DSI_PCONFR_SW_TIME0_Pos) /*!< 0x00000100 */
8448#define DSI_PCONFR_SW_TIME0 DSI_PCONFR_SW_TIME0_Msk
8449#define DSI_PCONFR_SW_TIME1_Pos (9U)
8450#define DSI_PCONFR_SW_TIME1_Msk (0x1U << DSI_PCONFR_SW_TIME1_Pos) /*!< 0x00000200 */
8451#define DSI_PCONFR_SW_TIME1 DSI_PCONFR_SW_TIME1_Msk
8452#define DSI_PCONFR_SW_TIME2_Pos (10U)
8453#define DSI_PCONFR_SW_TIME2_Msk (0x1U << DSI_PCONFR_SW_TIME2_Pos) /*!< 0x00000400 */
8454#define DSI_PCONFR_SW_TIME2 DSI_PCONFR_SW_TIME2_Msk
8455#define DSI_PCONFR_SW_TIME3_Pos (11U)
8456#define DSI_PCONFR_SW_TIME3_Msk (0x1U << DSI_PCONFR_SW_TIME3_Pos) /*!< 0x00000800 */
8457#define DSI_PCONFR_SW_TIME3 DSI_PCONFR_SW_TIME3_Msk
8458#define DSI_PCONFR_SW_TIME4_Pos (12U)
8459#define DSI_PCONFR_SW_TIME4_Msk (0x1U << DSI_PCONFR_SW_TIME4_Pos) /*!< 0x00001000 */
8460#define DSI_PCONFR_SW_TIME4 DSI_PCONFR_SW_TIME4_Msk
8461#define DSI_PCONFR_SW_TIME5_Pos (13U)
8462#define DSI_PCONFR_SW_TIME5_Msk (0x1U << DSI_PCONFR_SW_TIME5_Pos) /*!< 0x00002000 */
8463#define DSI_PCONFR_SW_TIME5 DSI_PCONFR_SW_TIME5_Msk
8464#define DSI_PCONFR_SW_TIME6_Pos (14U)
8465#define DSI_PCONFR_SW_TIME6_Msk (0x1U << DSI_PCONFR_SW_TIME6_Pos) /*!< 0x00004000 */
8466#define DSI_PCONFR_SW_TIME6 DSI_PCONFR_SW_TIME6_Msk
8467#define DSI_PCONFR_SW_TIME7_Pos (15U)
8468#define DSI_PCONFR_SW_TIME7_Msk (0x1U << DSI_PCONFR_SW_TIME7_Pos) /*!< 0x00008000 */
8469#define DSI_PCONFR_SW_TIME7 DSI_PCONFR_SW_TIME7_Msk
8470
8471/******************* Bit definition for DSI_PUCR register ***************/
8472#define DSI_PUCR_URCL_Pos (0U)
8473#define DSI_PUCR_URCL_Msk (0x1U << DSI_PUCR_URCL_Pos) /*!< 0x00000001 */
8474#define DSI_PUCR_URCL DSI_PUCR_URCL_Msk /*!< ULPS Request on Clock Lane */
8475#define DSI_PUCR_UECL_Pos (1U)
8476#define DSI_PUCR_UECL_Msk (0x1U << DSI_PUCR_UECL_Pos) /*!< 0x00000002 */
8477#define DSI_PUCR_UECL DSI_PUCR_UECL_Msk /*!< ULPS Exit on Clock Lane */
8478#define DSI_PUCR_URDL_Pos (2U)
8479#define DSI_PUCR_URDL_Msk (0x1U << DSI_PUCR_URDL_Pos) /*!< 0x00000004 */
8480#define DSI_PUCR_URDL DSI_PUCR_URDL_Msk /*!< ULPS Request on Data Lane */
8481#define DSI_PUCR_UEDL_Pos (3U)
8482#define DSI_PUCR_UEDL_Msk (0x1U << DSI_PUCR_UEDL_Pos) /*!< 0x00000008 */
8483#define DSI_PUCR_UEDL DSI_PUCR_UEDL_Msk /*!< ULPS Exit on Data Lane */
8484
8485/******************* Bit definition for DSI_PTTCR register **************/
8486#define DSI_PTTCR_TX_TRIG_Pos (0U)
8487#define DSI_PTTCR_TX_TRIG_Msk (0xFU << DSI_PTTCR_TX_TRIG_Pos) /*!< 0x0000000F */
8488#define DSI_PTTCR_TX_TRIG DSI_PTTCR_TX_TRIG_Msk /*!< Transmission Trigger */
8489#define DSI_PTTCR_TX_TRIG0_Pos (0U)
8490#define DSI_PTTCR_TX_TRIG0_Msk (0x1U << DSI_PTTCR_TX_TRIG0_Pos) /*!< 0x00000001 */
8491#define DSI_PTTCR_TX_TRIG0 DSI_PTTCR_TX_TRIG0_Msk
8492#define DSI_PTTCR_TX_TRIG1_Pos (1U)
8493#define DSI_PTTCR_TX_TRIG1_Msk (0x1U << DSI_PTTCR_TX_TRIG1_Pos) /*!< 0x00000002 */
8494#define DSI_PTTCR_TX_TRIG1 DSI_PTTCR_TX_TRIG1_Msk
8495#define DSI_PTTCR_TX_TRIG2_Pos (2U)
8496#define DSI_PTTCR_TX_TRIG2_Msk (0x1U << DSI_PTTCR_TX_TRIG2_Pos) /*!< 0x00000004 */
8497#define DSI_PTTCR_TX_TRIG2 DSI_PTTCR_TX_TRIG2_Msk
8498#define DSI_PTTCR_TX_TRIG3_Pos (3U)
8499#define DSI_PTTCR_TX_TRIG3_Msk (0x1U << DSI_PTTCR_TX_TRIG3_Pos) /*!< 0x00000008 */
8500#define DSI_PTTCR_TX_TRIG3 DSI_PTTCR_TX_TRIG3_Msk
8501
8502/******************* Bit definition for DSI_PSR register ****************/
8503#define DSI_PSR_PD_Pos (1U)
8504#define DSI_PSR_PD_Msk (0x1U << DSI_PSR_PD_Pos) /*!< 0x00000002 */
8505#define DSI_PSR_PD DSI_PSR_PD_Msk /*!< PHY Direction */
8506#define DSI_PSR_PSSC_Pos (2U)
8507#define DSI_PSR_PSSC_Msk (0x1U << DSI_PSR_PSSC_Pos) /*!< 0x00000004 */
8508#define DSI_PSR_PSSC DSI_PSR_PSSC_Msk /*!< PHY Stop State Clock lane */
8509#define DSI_PSR_UANC_Pos (3U)
8510#define DSI_PSR_UANC_Msk (0x1U << DSI_PSR_UANC_Pos) /*!< 0x00000008 */
8511#define DSI_PSR_UANC DSI_PSR_UANC_Msk /*!< ULPS Active Not Clock lane */
8512#define DSI_PSR_PSS0_Pos (4U)
8513#define DSI_PSR_PSS0_Msk (0x1U << DSI_PSR_PSS0_Pos) /*!< 0x00000010 */
8514#define DSI_PSR_PSS0 DSI_PSR_PSS0_Msk /*!< PHY Stop State lane 0 */
8515#define DSI_PSR_UAN0_Pos (5U)
8516#define DSI_PSR_UAN0_Msk (0x1U << DSI_PSR_UAN0_Pos) /*!< 0x00000020 */
8517#define DSI_PSR_UAN0 DSI_PSR_UAN0_Msk /*!< ULPS Active Not lane 0 */
8518#define DSI_PSR_RUE0_Pos (6U)
8519#define DSI_PSR_RUE0_Msk (0x1U << DSI_PSR_RUE0_Pos) /*!< 0x00000040 */
8520#define DSI_PSR_RUE0 DSI_PSR_RUE0_Msk /*!< RX ULPS Escape lane 0 */
8521#define DSI_PSR_PSS1_Pos (7U)
8522#define DSI_PSR_PSS1_Msk (0x1U << DSI_PSR_PSS1_Pos) /*!< 0x00000080 */
8523#define DSI_PSR_PSS1 DSI_PSR_PSS1_Msk /*!< PHY Stop State lane 1 */
8524#define DSI_PSR_UAN1_Pos (8U)
8525#define DSI_PSR_UAN1_Msk (0x1U << DSI_PSR_UAN1_Pos) /*!< 0x00000100 */
8526#define DSI_PSR_UAN1 DSI_PSR_UAN1_Msk /*!< ULPS Active Not lane 1 */
8527
8528/******************* Bit definition for DSI_ISR0 register ***************/
8529#define DSI_ISR0_AE0_Pos (0U)
8530#define DSI_ISR0_AE0_Msk (0x1U << DSI_ISR0_AE0_Pos) /*!< 0x00000001 */
8531#define DSI_ISR0_AE0 DSI_ISR0_AE0_Msk /*!< Acknowledge Error 0 */
8532#define DSI_ISR0_AE1_Pos (1U)
8533#define DSI_ISR0_AE1_Msk (0x1U << DSI_ISR0_AE1_Pos) /*!< 0x00000002 */
8534#define DSI_ISR0_AE1 DSI_ISR0_AE1_Msk /*!< Acknowledge Error 1 */
8535#define DSI_ISR0_AE2_Pos (2U)
8536#define DSI_ISR0_AE2_Msk (0x1U << DSI_ISR0_AE2_Pos) /*!< 0x00000004 */
8537#define DSI_ISR0_AE2 DSI_ISR0_AE2_Msk /*!< Acknowledge Error 2 */
8538#define DSI_ISR0_AE3_Pos (3U)
8539#define DSI_ISR0_AE3_Msk (0x1U << DSI_ISR0_AE3_Pos) /*!< 0x00000008 */
8540#define DSI_ISR0_AE3 DSI_ISR0_AE3_Msk /*!< Acknowledge Error 3 */
8541#define DSI_ISR0_AE4_Pos (4U)
8542#define DSI_ISR0_AE4_Msk (0x1U << DSI_ISR0_AE4_Pos) /*!< 0x00000010 */
8543#define DSI_ISR0_AE4 DSI_ISR0_AE4_Msk /*!< Acknowledge Error 4 */
8544#define DSI_ISR0_AE5_Pos (5U)
8545#define DSI_ISR0_AE5_Msk (0x1U << DSI_ISR0_AE5_Pos) /*!< 0x00000020 */
8546#define DSI_ISR0_AE5 DSI_ISR0_AE5_Msk /*!< Acknowledge Error 5 */
8547#define DSI_ISR0_AE6_Pos (6U)
8548#define DSI_ISR0_AE6_Msk (0x1U << DSI_ISR0_AE6_Pos) /*!< 0x00000040 */
8549#define DSI_ISR0_AE6 DSI_ISR0_AE6_Msk /*!< Acknowledge Error 6 */
8550#define DSI_ISR0_AE7_Pos (7U)
8551#define DSI_ISR0_AE7_Msk (0x1U << DSI_ISR0_AE7_Pos) /*!< 0x00000080 */
8552#define DSI_ISR0_AE7 DSI_ISR0_AE7_Msk /*!< Acknowledge Error 7 */
8553#define DSI_ISR0_AE8_Pos (8U)
8554#define DSI_ISR0_AE8_Msk (0x1U << DSI_ISR0_AE8_Pos) /*!< 0x00000100 */
8555#define DSI_ISR0_AE8 DSI_ISR0_AE8_Msk /*!< Acknowledge Error 8 */
8556#define DSI_ISR0_AE9_Pos (9U)
8557#define DSI_ISR0_AE9_Msk (0x1U << DSI_ISR0_AE9_Pos) /*!< 0x00000200 */
8558#define DSI_ISR0_AE9 DSI_ISR0_AE9_Msk /*!< Acknowledge Error 9 */
8559#define DSI_ISR0_AE10_Pos (10U)
8560#define DSI_ISR0_AE10_Msk (0x1U << DSI_ISR0_AE10_Pos) /*!< 0x00000400 */
8561#define DSI_ISR0_AE10 DSI_ISR0_AE10_Msk /*!< Acknowledge Error 10 */
8562#define DSI_ISR0_AE11_Pos (11U)
8563#define DSI_ISR0_AE11_Msk (0x1U << DSI_ISR0_AE11_Pos) /*!< 0x00000800 */
8564#define DSI_ISR0_AE11 DSI_ISR0_AE11_Msk /*!< Acknowledge Error 11 */
8565#define DSI_ISR0_AE12_Pos (12U)
8566#define DSI_ISR0_AE12_Msk (0x1U << DSI_ISR0_AE12_Pos) /*!< 0x00001000 */
8567#define DSI_ISR0_AE12 DSI_ISR0_AE12_Msk /*!< Acknowledge Error 12 */
8568#define DSI_ISR0_AE13_Pos (13U)
8569#define DSI_ISR0_AE13_Msk (0x1U << DSI_ISR0_AE13_Pos) /*!< 0x00002000 */
8570#define DSI_ISR0_AE13 DSI_ISR0_AE13_Msk /*!< Acknowledge Error 13 */
8571#define DSI_ISR0_AE14_Pos (14U)
8572#define DSI_ISR0_AE14_Msk (0x1U << DSI_ISR0_AE14_Pos) /*!< 0x00004000 */
8573#define DSI_ISR0_AE14 DSI_ISR0_AE14_Msk /*!< Acknowledge Error 14 */
8574#define DSI_ISR0_AE15_Pos (15U)
8575#define DSI_ISR0_AE15_Msk (0x1U << DSI_ISR0_AE15_Pos) /*!< 0x00008000 */
8576#define DSI_ISR0_AE15 DSI_ISR0_AE15_Msk /*!< Acknowledge Error 15 */
8577#define DSI_ISR0_PE0_Pos (16U)
8578#define DSI_ISR0_PE0_Msk (0x1U << DSI_ISR0_PE0_Pos) /*!< 0x00010000 */
8579#define DSI_ISR0_PE0 DSI_ISR0_PE0_Msk /*!< PHY Error 0 */
8580#define DSI_ISR0_PE1_Pos (17U)
8581#define DSI_ISR0_PE1_Msk (0x1U << DSI_ISR0_PE1_Pos) /*!< 0x00020000 */
8582#define DSI_ISR0_PE1 DSI_ISR0_PE1_Msk /*!< PHY Error 1 */
8583#define DSI_ISR0_PE2_Pos (18U)
8584#define DSI_ISR0_PE2_Msk (0x1U << DSI_ISR0_PE2_Pos) /*!< 0x00040000 */
8585#define DSI_ISR0_PE2 DSI_ISR0_PE2_Msk /*!< PHY Error 2 */
8586#define DSI_ISR0_PE3_Pos (19U)
8587#define DSI_ISR0_PE3_Msk (0x1U << DSI_ISR0_PE3_Pos) /*!< 0x00080000 */
8588#define DSI_ISR0_PE3 DSI_ISR0_PE3_Msk /*!< PHY Error 3 */
8589#define DSI_ISR0_PE4_Pos (20U)
8590#define DSI_ISR0_PE4_Msk (0x1U << DSI_ISR0_PE4_Pos) /*!< 0x00100000 */
8591#define DSI_ISR0_PE4 DSI_ISR0_PE4_Msk /*!< PHY Error 4 */
8592
8593/******************* Bit definition for DSI_ISR1 register ***************/
8594#define DSI_ISR1_TOHSTX_Pos (0U)
8595#define DSI_ISR1_TOHSTX_Msk (0x1U << DSI_ISR1_TOHSTX_Pos) /*!< 0x00000001 */
8596#define DSI_ISR1_TOHSTX DSI_ISR1_TOHSTX_Msk /*!< Timeout High-Speed Transmission */
8597#define DSI_ISR1_TOLPRX_Pos (1U)
8598#define DSI_ISR1_TOLPRX_Msk (0x1U << DSI_ISR1_TOLPRX_Pos) /*!< 0x00000002 */
8599#define DSI_ISR1_TOLPRX DSI_ISR1_TOLPRX_Msk /*!< Timeout Low-Power Reception */
8600#define DSI_ISR1_ECCSE_Pos (2U)
8601#define DSI_ISR1_ECCSE_Msk (0x1U << DSI_ISR1_ECCSE_Pos) /*!< 0x00000004 */
8602#define DSI_ISR1_ECCSE DSI_ISR1_ECCSE_Msk /*!< ECC Single-bit Error */
8603#define DSI_ISR1_ECCME_Pos (3U)
8604#define DSI_ISR1_ECCME_Msk (0x1U << DSI_ISR1_ECCME_Pos) /*!< 0x00000008 */
8605#define DSI_ISR1_ECCME DSI_ISR1_ECCME_Msk /*!< ECC Multi-bit Error */
8606#define DSI_ISR1_CRCE_Pos (4U)
8607#define DSI_ISR1_CRCE_Msk (0x1U << DSI_ISR1_CRCE_Pos) /*!< 0x00000010 */
8608#define DSI_ISR1_CRCE DSI_ISR1_CRCE_Msk /*!< CRC Error */
8609#define DSI_ISR1_PSE_Pos (5U)
8610#define DSI_ISR1_PSE_Msk (0x1U << DSI_ISR1_PSE_Pos) /*!< 0x00000020 */
8611#define DSI_ISR1_PSE DSI_ISR1_PSE_Msk /*!< Packet Size Error */
8612#define DSI_ISR1_EOTPE_Pos (6U)
8613#define DSI_ISR1_EOTPE_Msk (0x1U << DSI_ISR1_EOTPE_Pos) /*!< 0x00000040 */
8614#define DSI_ISR1_EOTPE DSI_ISR1_EOTPE_Msk /*!< EoTp Error */
8615#define DSI_ISR1_LPWRE_Pos (7U)
8616#define DSI_ISR1_LPWRE_Msk (0x1U << DSI_ISR1_LPWRE_Pos) /*!< 0x00000080 */
8617#define DSI_ISR1_LPWRE DSI_ISR1_LPWRE_Msk /*!< LTDC Payload Write Error */
8618#define DSI_ISR1_GCWRE_Pos (8U)
8619#define DSI_ISR1_GCWRE_Msk (0x1U << DSI_ISR1_GCWRE_Pos) /*!< 0x00000100 */
8620#define DSI_ISR1_GCWRE DSI_ISR1_GCWRE_Msk /*!< Generic Command Write Error */
8621#define DSI_ISR1_GPWRE_Pos (9U)
8622#define DSI_ISR1_GPWRE_Msk (0x1U << DSI_ISR1_GPWRE_Pos) /*!< 0x00000200 */
8623#define DSI_ISR1_GPWRE DSI_ISR1_GPWRE_Msk /*!< Generic Payload Write Error */
8624#define DSI_ISR1_GPTXE_Pos (10U)
8625#define DSI_ISR1_GPTXE_Msk (0x1U << DSI_ISR1_GPTXE_Pos) /*!< 0x00000400 */
8626#define DSI_ISR1_GPTXE DSI_ISR1_GPTXE_Msk /*!< Generic Payload Transmit Error */
8627#define DSI_ISR1_GPRDE_Pos (11U)
8628#define DSI_ISR1_GPRDE_Msk (0x1U << DSI_ISR1_GPRDE_Pos) /*!< 0x00000800 */
8629#define DSI_ISR1_GPRDE DSI_ISR1_GPRDE_Msk /*!< Generic Payload Read Error */
8630#define DSI_ISR1_GPRXE_Pos (12U)
8631#define DSI_ISR1_GPRXE_Msk (0x1U << DSI_ISR1_GPRXE_Pos) /*!< 0x00001000 */
8632#define DSI_ISR1_GPRXE DSI_ISR1_GPRXE_Msk /*!< Generic Payload Receive Error */
8633
8634/******************* Bit definition for DSI_IER0 register ***************/
8635#define DSI_IER0_AE0IE_Pos (0U)
8636#define DSI_IER0_AE0IE_Msk (0x1U << DSI_IER0_AE0IE_Pos) /*!< 0x00000001 */
8637#define DSI_IER0_AE0IE DSI_IER0_AE0IE_Msk /*!< Acknowledge Error 0 Interrupt Enable */
8638#define DSI_IER0_AE1IE_Pos (1U)
8639#define DSI_IER0_AE1IE_Msk (0x1U << DSI_IER0_AE1IE_Pos) /*!< 0x00000002 */
8640#define DSI_IER0_AE1IE DSI_IER0_AE1IE_Msk /*!< Acknowledge Error 1 Interrupt Enable */
8641#define DSI_IER0_AE2IE_Pos (2U)
8642#define DSI_IER0_AE2IE_Msk (0x1U << DSI_IER0_AE2IE_Pos) /*!< 0x00000004 */
8643#define DSI_IER0_AE2IE DSI_IER0_AE2IE_Msk /*!< Acknowledge Error 2 Interrupt Enable */
8644#define DSI_IER0_AE3IE_Pos (3U)
8645#define DSI_IER0_AE3IE_Msk (0x1U << DSI_IER0_AE3IE_Pos) /*!< 0x00000008 */
8646#define DSI_IER0_AE3IE DSI_IER0_AE3IE_Msk /*!< Acknowledge Error 3 Interrupt Enable */
8647#define DSI_IER0_AE4IE_Pos (4U)
8648#define DSI_IER0_AE4IE_Msk (0x1U << DSI_IER0_AE4IE_Pos) /*!< 0x00000010 */
8649#define DSI_IER0_AE4IE DSI_IER0_AE4IE_Msk /*!< Acknowledge Error 4 Interrupt Enable */
8650#define DSI_IER0_AE5IE_Pos (5U)
8651#define DSI_IER0_AE5IE_Msk (0x1U << DSI_IER0_AE5IE_Pos) /*!< 0x00000020 */
8652#define DSI_IER0_AE5IE DSI_IER0_AE5IE_Msk /*!< Acknowledge Error 5 Interrupt Enable */
8653#define DSI_IER0_AE6IE_Pos (6U)
8654#define DSI_IER0_AE6IE_Msk (0x1U << DSI_IER0_AE6IE_Pos) /*!< 0x00000040 */
8655#define DSI_IER0_AE6IE DSI_IER0_AE6IE_Msk /*!< Acknowledge Error 6 Interrupt Enable */
8656#define DSI_IER0_AE7IE_Pos (7U)
8657#define DSI_IER0_AE7IE_Msk (0x1U << DSI_IER0_AE7IE_Pos) /*!< 0x00000080 */
8658#define DSI_IER0_AE7IE DSI_IER0_AE7IE_Msk /*!< Acknowledge Error 7 Interrupt Enable */
8659#define DSI_IER0_AE8IE_Pos (8U)
8660#define DSI_IER0_AE8IE_Msk (0x1U << DSI_IER0_AE8IE_Pos) /*!< 0x00000100 */
8661#define DSI_IER0_AE8IE DSI_IER0_AE8IE_Msk /*!< Acknowledge Error 8 Interrupt Enable */
8662#define DSI_IER0_AE9IE_Pos (9U)
8663#define DSI_IER0_AE9IE_Msk (0x1U << DSI_IER0_AE9IE_Pos) /*!< 0x00000200 */
8664#define DSI_IER0_AE9IE DSI_IER0_AE9IE_Msk /*!< Acknowledge Error 9 Interrupt Enable */
8665#define DSI_IER0_AE10IE_Pos (10U)
8666#define DSI_IER0_AE10IE_Msk (0x1U << DSI_IER0_AE10IE_Pos) /*!< 0x00000400 */
8667#define DSI_IER0_AE10IE DSI_IER0_AE10IE_Msk /*!< Acknowledge Error 10 Interrupt Enable */
8668#define DSI_IER0_AE11IE_Pos (11U)
8669#define DSI_IER0_AE11IE_Msk (0x1U << DSI_IER0_AE11IE_Pos) /*!< 0x00000800 */
8670#define DSI_IER0_AE11IE DSI_IER0_AE11IE_Msk /*!< Acknowledge Error 11 Interrupt Enable */
8671#define DSI_IER0_AE12IE_Pos (12U)
8672#define DSI_IER0_AE12IE_Msk (0x1U << DSI_IER0_AE12IE_Pos) /*!< 0x00001000 */
8673#define DSI_IER0_AE12IE DSI_IER0_AE12IE_Msk /*!< Acknowledge Error 12 Interrupt Enable */
8674#define DSI_IER0_AE13IE_Pos (13U)
8675#define DSI_IER0_AE13IE_Msk (0x1U << DSI_IER0_AE13IE_Pos) /*!< 0x00002000 */
8676#define DSI_IER0_AE13IE DSI_IER0_AE13IE_Msk /*!< Acknowledge Error 13 Interrupt Enable */
8677#define DSI_IER0_AE14IE_Pos (14U)
8678#define DSI_IER0_AE14IE_Msk (0x1U << DSI_IER0_AE14IE_Pos) /*!< 0x00004000 */
8679#define DSI_IER0_AE14IE DSI_IER0_AE14IE_Msk /*!< Acknowledge Error 14 Interrupt Enable */
8680#define DSI_IER0_AE15IE_Pos (15U)
8681#define DSI_IER0_AE15IE_Msk (0x1U << DSI_IER0_AE15IE_Pos) /*!< 0x00008000 */
8682#define DSI_IER0_AE15IE DSI_IER0_AE15IE_Msk /*!< Acknowledge Error 15 Interrupt Enable */
8683#define DSI_IER0_PE0IE_Pos (16U)
8684#define DSI_IER0_PE0IE_Msk (0x1U << DSI_IER0_PE0IE_Pos) /*!< 0x00010000 */
8685#define DSI_IER0_PE0IE DSI_IER0_PE0IE_Msk /*!< PHY Error 0 Interrupt Enable */
8686#define DSI_IER0_PE1IE_Pos (17U)
8687#define DSI_IER0_PE1IE_Msk (0x1U << DSI_IER0_PE1IE_Pos) /*!< 0x00020000 */
8688#define DSI_IER0_PE1IE DSI_IER0_PE1IE_Msk /*!< PHY Error 1 Interrupt Enable */
8689#define DSI_IER0_PE2IE_Pos (18U)
8690#define DSI_IER0_PE2IE_Msk (0x1U << DSI_IER0_PE2IE_Pos) /*!< 0x00040000 */
8691#define DSI_IER0_PE2IE DSI_IER0_PE2IE_Msk /*!< PHY Error 2 Interrupt Enable */
8692#define DSI_IER0_PE3IE_Pos (19U)
8693#define DSI_IER0_PE3IE_Msk (0x1U << DSI_IER0_PE3IE_Pos) /*!< 0x00080000 */
8694#define DSI_IER0_PE3IE DSI_IER0_PE3IE_Msk /*!< PHY Error 3 Interrupt Enable */
8695#define DSI_IER0_PE4IE_Pos (20U)
8696#define DSI_IER0_PE4IE_Msk (0x1U << DSI_IER0_PE4IE_Pos) /*!< 0x00100000 */
8697#define DSI_IER0_PE4IE DSI_IER0_PE4IE_Msk /*!< PHY Error 4 Interrupt Enable */
8698
8699/******************* Bit definition for DSI_IER1 register ***************/
8700#define DSI_IER1_TOHSTXIE_Pos (0U)
8701#define DSI_IER1_TOHSTXIE_Msk (0x1U << DSI_IER1_TOHSTXIE_Pos) /*!< 0x00000001 */
8702#define DSI_IER1_TOHSTXIE DSI_IER1_TOHSTXIE_Msk /*!< Timeout High-Speed Transmission Interrupt Enable */
8703#define DSI_IER1_TOLPRXIE_Pos (1U)
8704#define DSI_IER1_TOLPRXIE_Msk (0x1U << DSI_IER1_TOLPRXIE_Pos) /*!< 0x00000002 */
8705#define DSI_IER1_TOLPRXIE DSI_IER1_TOLPRXIE_Msk /*!< Timeout Low-Power Reception Interrupt Enable */
8706#define DSI_IER1_ECCSEIE_Pos (2U)
8707#define DSI_IER1_ECCSEIE_Msk (0x1U << DSI_IER1_ECCSEIE_Pos) /*!< 0x00000004 */
8708#define DSI_IER1_ECCSEIE DSI_IER1_ECCSEIE_Msk /*!< ECC Single-bit Error Interrupt Enable */
8709#define DSI_IER1_ECCMEIE_Pos (3U)
8710#define DSI_IER1_ECCMEIE_Msk (0x1U << DSI_IER1_ECCMEIE_Pos) /*!< 0x00000008 */
8711#define DSI_IER1_ECCMEIE DSI_IER1_ECCMEIE_Msk /*!< ECC Multi-bit Error Interrupt Enable */
8712#define DSI_IER1_CRCEIE_Pos (4U)
8713#define DSI_IER1_CRCEIE_Msk (0x1U << DSI_IER1_CRCEIE_Pos) /*!< 0x00000010 */
8714#define DSI_IER1_CRCEIE DSI_IER1_CRCEIE_Msk /*!< CRC Error Interrupt Enable */
8715#define DSI_IER1_PSEIE_Pos (5U)
8716#define DSI_IER1_PSEIE_Msk (0x1U << DSI_IER1_PSEIE_Pos) /*!< 0x00000020 */
8717#define DSI_IER1_PSEIE DSI_IER1_PSEIE_Msk /*!< Packet Size Error Interrupt Enable */
8718#define DSI_IER1_EOTPEIE_Pos (6U)
8719#define DSI_IER1_EOTPEIE_Msk (0x1U << DSI_IER1_EOTPEIE_Pos) /*!< 0x00000040 */
8720#define DSI_IER1_EOTPEIE DSI_IER1_EOTPEIE_Msk /*!< EoTp Error Interrupt Enable */
8721#define DSI_IER1_LPWREIE_Pos (7U)
8722#define DSI_IER1_LPWREIE_Msk (0x1U << DSI_IER1_LPWREIE_Pos) /*!< 0x00000080 */
8723#define DSI_IER1_LPWREIE DSI_IER1_LPWREIE_Msk /*!< LTDC Payload Write Error Interrupt Enable */
8724#define DSI_IER1_GCWREIE_Pos (8U)
8725#define DSI_IER1_GCWREIE_Msk (0x1U << DSI_IER1_GCWREIE_Pos) /*!< 0x00000100 */
8726#define DSI_IER1_GCWREIE DSI_IER1_GCWREIE_Msk /*!< Generic Command Write Error Interrupt Enable */
8727#define DSI_IER1_GPWREIE_Pos (9U)
8728#define DSI_IER1_GPWREIE_Msk (0x1U << DSI_IER1_GPWREIE_Pos) /*!< 0x00000200 */
8729#define DSI_IER1_GPWREIE DSI_IER1_GPWREIE_Msk /*!< Generic Payload Write Error Interrupt Enable */
8730#define DSI_IER1_GPTXEIE_Pos (10U)
8731#define DSI_IER1_GPTXEIE_Msk (0x1U << DSI_IER1_GPTXEIE_Pos) /*!< 0x00000400 */
8732#define DSI_IER1_GPTXEIE DSI_IER1_GPTXEIE_Msk /*!< Generic Payload Transmit Error Interrupt Enable */
8733#define DSI_IER1_GPRDEIE_Pos (11U)
8734#define DSI_IER1_GPRDEIE_Msk (0x1U << DSI_IER1_GPRDEIE_Pos) /*!< 0x00000800 */
8735#define DSI_IER1_GPRDEIE DSI_IER1_GPRDEIE_Msk /*!< Generic Payload Read Error Interrupt Enable */
8736#define DSI_IER1_GPRXEIE_Pos (12U)
8737#define DSI_IER1_GPRXEIE_Msk (0x1U << DSI_IER1_GPRXEIE_Pos) /*!< 0x00001000 */
8738#define DSI_IER1_GPRXEIE DSI_IER1_GPRXEIE_Msk /*!< Generic Payload Receive Error Interrupt Enable */
8739
8740/******************* Bit definition for DSI_FIR0 register ***************/
8741#define DSI_FIR0_FAE0_Pos (0U)
8742#define DSI_FIR0_FAE0_Msk (0x1U << DSI_FIR0_FAE0_Pos) /*!< 0x00000001 */
8743#define DSI_FIR0_FAE0 DSI_FIR0_FAE0_Msk /*!< Force Acknowledge Error 0 */
8744#define DSI_FIR0_FAE1_Pos (1U)
8745#define DSI_FIR0_FAE1_Msk (0x1U << DSI_FIR0_FAE1_Pos) /*!< 0x00000002 */
8746#define DSI_FIR0_FAE1 DSI_FIR0_FAE1_Msk /*!< Force Acknowledge Error 1 */
8747#define DSI_FIR0_FAE2_Pos (2U)
8748#define DSI_FIR0_FAE2_Msk (0x1U << DSI_FIR0_FAE2_Pos) /*!< 0x00000004 */
8749#define DSI_FIR0_FAE2 DSI_FIR0_FAE2_Msk /*!< Force Acknowledge Error 2 */
8750#define DSI_FIR0_FAE3_Pos (3U)
8751#define DSI_FIR0_FAE3_Msk (0x1U << DSI_FIR0_FAE3_Pos) /*!< 0x00000008 */
8752#define DSI_FIR0_FAE3 DSI_FIR0_FAE3_Msk /*!< Force Acknowledge Error 3 */
8753#define DSI_FIR0_FAE4_Pos (4U)
8754#define DSI_FIR0_FAE4_Msk (0x1U << DSI_FIR0_FAE4_Pos) /*!< 0x00000010 */
8755#define DSI_FIR0_FAE4 DSI_FIR0_FAE4_Msk /*!< Force Acknowledge Error 4 */
8756#define DSI_FIR0_FAE5_Pos (5U)
8757#define DSI_FIR0_FAE5_Msk (0x1U << DSI_FIR0_FAE5_Pos) /*!< 0x00000020 */
8758#define DSI_FIR0_FAE5 DSI_FIR0_FAE5_Msk /*!< Force Acknowledge Error 5 */
8759#define DSI_FIR0_FAE6_Pos (6U)
8760#define DSI_FIR0_FAE6_Msk (0x1U << DSI_FIR0_FAE6_Pos) /*!< 0x00000040 */
8761#define DSI_FIR0_FAE6 DSI_FIR0_FAE6_Msk /*!< Force Acknowledge Error 6 */
8762#define DSI_FIR0_FAE7_Pos (7U)
8763#define DSI_FIR0_FAE7_Msk (0x1U << DSI_FIR0_FAE7_Pos) /*!< 0x00000080 */
8764#define DSI_FIR0_FAE7 DSI_FIR0_FAE7_Msk /*!< Force Acknowledge Error 7 */
8765#define DSI_FIR0_FAE8_Pos (8U)
8766#define DSI_FIR0_FAE8_Msk (0x1U << DSI_FIR0_FAE8_Pos) /*!< 0x00000100 */
8767#define DSI_FIR0_FAE8 DSI_FIR0_FAE8_Msk /*!< Force Acknowledge Error 8 */
8768#define DSI_FIR0_FAE9_Pos (9U)
8769#define DSI_FIR0_FAE9_Msk (0x1U << DSI_FIR0_FAE9_Pos) /*!< 0x00000200 */
8770#define DSI_FIR0_FAE9 DSI_FIR0_FAE9_Msk /*!< Force Acknowledge Error 9 */
8771#define DSI_FIR0_FAE10_Pos (10U)
8772#define DSI_FIR0_FAE10_Msk (0x1U << DSI_FIR0_FAE10_Pos) /*!< 0x00000400 */
8773#define DSI_FIR0_FAE10 DSI_FIR0_FAE10_Msk /*!< Force Acknowledge Error 10 */
8774#define DSI_FIR0_FAE11_Pos (11U)
8775#define DSI_FIR0_FAE11_Msk (0x1U << DSI_FIR0_FAE11_Pos) /*!< 0x00000800 */
8776#define DSI_FIR0_FAE11 DSI_FIR0_FAE11_Msk /*!< Force Acknowledge Error 11 */
8777#define DSI_FIR0_FAE12_Pos (12U)
8778#define DSI_FIR0_FAE12_Msk (0x1U << DSI_FIR0_FAE12_Pos) /*!< 0x00001000 */
8779#define DSI_FIR0_FAE12 DSI_FIR0_FAE12_Msk /*!< Force Acknowledge Error 12 */
8780#define DSI_FIR0_FAE13_Pos (13U)
8781#define DSI_FIR0_FAE13_Msk (0x1U << DSI_FIR0_FAE13_Pos) /*!< 0x00002000 */
8782#define DSI_FIR0_FAE13 DSI_FIR0_FAE13_Msk /*!< Force Acknowledge Error 13 */
8783#define DSI_FIR0_FAE14_Pos (14U)
8784#define DSI_FIR0_FAE14_Msk (0x1U << DSI_FIR0_FAE14_Pos) /*!< 0x00004000 */
8785#define DSI_FIR0_FAE14 DSI_FIR0_FAE14_Msk /*!< Force Acknowledge Error 14 */
8786#define DSI_FIR0_FAE15_Pos (15U)
8787#define DSI_FIR0_FAE15_Msk (0x1U << DSI_FIR0_FAE15_Pos) /*!< 0x00008000 */
8788#define DSI_FIR0_FAE15 DSI_FIR0_FAE15_Msk /*!< Force Acknowledge Error 15 */
8789#define DSI_FIR0_FPE0_Pos (16U)
8790#define DSI_FIR0_FPE0_Msk (0x1U << DSI_FIR0_FPE0_Pos) /*!< 0x00010000 */
8791#define DSI_FIR0_FPE0 DSI_FIR0_FPE0_Msk /*!< Force PHY Error 0 */
8792#define DSI_FIR0_FPE1_Pos (17U)
8793#define DSI_FIR0_FPE1_Msk (0x1U << DSI_FIR0_FPE1_Pos) /*!< 0x00020000 */
8794#define DSI_FIR0_FPE1 DSI_FIR0_FPE1_Msk /*!< Force PHY Error 1 */
8795#define DSI_FIR0_FPE2_Pos (18U)
8796#define DSI_FIR0_FPE2_Msk (0x1U << DSI_FIR0_FPE2_Pos) /*!< 0x00040000 */
8797#define DSI_FIR0_FPE2 DSI_FIR0_FPE2_Msk /*!< Force PHY Error 2 */
8798#define DSI_FIR0_FPE3_Pos (19U)
8799#define DSI_FIR0_FPE3_Msk (0x1U << DSI_FIR0_FPE3_Pos) /*!< 0x00080000 */
8800#define DSI_FIR0_FPE3 DSI_FIR0_FPE3_Msk /*!< Force PHY Error 3 */
8801#define DSI_FIR0_FPE4_Pos (20U)
8802#define DSI_FIR0_FPE4_Msk (0x1U << DSI_FIR0_FPE4_Pos) /*!< 0x00100000 */
8803#define DSI_FIR0_FPE4 DSI_FIR0_FPE4_Msk /*!< Force PHY Error 4 */
8804
8805/******************* Bit definition for DSI_FIR1 register ***************/
8806#define DSI_FIR1_FTOHSTX_Pos (0U)
8807#define DSI_FIR1_FTOHSTX_Msk (0x1U << DSI_FIR1_FTOHSTX_Pos) /*!< 0x00000001 */
8808#define DSI_FIR1_FTOHSTX DSI_FIR1_FTOHSTX_Msk /*!< Force Timeout High-Speed Transmission */
8809#define DSI_FIR1_FTOLPRX_Pos (1U)
8810#define DSI_FIR1_FTOLPRX_Msk (0x1U << DSI_FIR1_FTOLPRX_Pos) /*!< 0x00000002 */
8811#define DSI_FIR1_FTOLPRX DSI_FIR1_FTOLPRX_Msk /*!< Force Timeout Low-Power Reception */
8812#define DSI_FIR1_FECCSE_Pos (2U)
8813#define DSI_FIR1_FECCSE_Msk (0x1U << DSI_FIR1_FECCSE_Pos) /*!< 0x00000004 */
8814#define DSI_FIR1_FECCSE DSI_FIR1_FECCSE_Msk /*!< Force ECC Single-bit Error */
8815#define DSI_FIR1_FECCME_Pos (3U)
8816#define DSI_FIR1_FECCME_Msk (0x1U << DSI_FIR1_FECCME_Pos) /*!< 0x00000008 */
8817#define DSI_FIR1_FECCME DSI_FIR1_FECCME_Msk /*!< Force ECC Multi-bit Error */
8818#define DSI_FIR1_FCRCE_Pos (4U)
8819#define DSI_FIR1_FCRCE_Msk (0x1U << DSI_FIR1_FCRCE_Pos) /*!< 0x00000010 */
8820#define DSI_FIR1_FCRCE DSI_FIR1_FCRCE_Msk /*!< Force CRC Error */
8821#define DSI_FIR1_FPSE_Pos (5U)
8822#define DSI_FIR1_FPSE_Msk (0x1U << DSI_FIR1_FPSE_Pos) /*!< 0x00000020 */
8823#define DSI_FIR1_FPSE DSI_FIR1_FPSE_Msk /*!< Force Packet Size Error */
8824#define DSI_FIR1_FEOTPE_Pos (6U)
8825#define DSI_FIR1_FEOTPE_Msk (0x1U << DSI_FIR1_FEOTPE_Pos) /*!< 0x00000040 */
8826#define DSI_FIR1_FEOTPE DSI_FIR1_FEOTPE_Msk /*!< Force EoTp Error */
8827#define DSI_FIR1_FLPWRE_Pos (7U)
8828#define DSI_FIR1_FLPWRE_Msk (0x1U << DSI_FIR1_FLPWRE_Pos) /*!< 0x00000080 */
8829#define DSI_FIR1_FLPWRE DSI_FIR1_FLPWRE_Msk /*!< Force LTDC Payload Write Error */
8830#define DSI_FIR1_FGCWRE_Pos (8U)
8831#define DSI_FIR1_FGCWRE_Msk (0x1U << DSI_FIR1_FGCWRE_Pos) /*!< 0x00000100 */
8832#define DSI_FIR1_FGCWRE DSI_FIR1_FGCWRE_Msk /*!< Force Generic Command Write Error */
8833#define DSI_FIR1_FGPWRE_Pos (9U)
8834#define DSI_FIR1_FGPWRE_Msk (0x1U << DSI_FIR1_FGPWRE_Pos) /*!< 0x00000200 */
8835#define DSI_FIR1_FGPWRE DSI_FIR1_FGPWRE_Msk /*!< Force Generic Payload Write Error */
8836#define DSI_FIR1_FGPTXE_Pos (10U)
8837#define DSI_FIR1_FGPTXE_Msk (0x1U << DSI_FIR1_FGPTXE_Pos) /*!< 0x00000400 */
8838#define DSI_FIR1_FGPTXE DSI_FIR1_FGPTXE_Msk /*!< Force Generic Payload Transmit Error */
8839#define DSI_FIR1_FGPRDE_Pos (11U)
8840#define DSI_FIR1_FGPRDE_Msk (0x1U << DSI_FIR1_FGPRDE_Pos) /*!< 0x00000800 */
8841#define DSI_FIR1_FGPRDE DSI_FIR1_FGPRDE_Msk /*!< Force Generic Payload Read Error */
8842#define DSI_FIR1_FGPRXE_Pos (12U)
8843#define DSI_FIR1_FGPRXE_Msk (0x1U << DSI_FIR1_FGPRXE_Pos) /*!< 0x00001000 */
8844#define DSI_FIR1_FGPRXE DSI_FIR1_FGPRXE_Msk /*!< Force Generic Payload Receive Error */
8845
8846/******************* Bit definition for DSI_VSCR register ***************/
8847#define DSI_VSCR_EN_Pos (0U)
8848#define DSI_VSCR_EN_Msk (0x1U << DSI_VSCR_EN_Pos) /*!< 0x00000001 */
8849#define DSI_VSCR_EN DSI_VSCR_EN_Msk /*!< Enable */
8850#define DSI_VSCR_UR_Pos (8U)
8851#define DSI_VSCR_UR_Msk (0x1U << DSI_VSCR_UR_Pos) /*!< 0x00000100 */
8852#define DSI_VSCR_UR DSI_VSCR_UR_Msk /*!< Update Register */
8853
8854/******************* Bit definition for DSI_LCVCIDR register ************/
8855#define DSI_LCVCIDR_VCID_Pos (0U)
8856#define DSI_LCVCIDR_VCID_Msk (0x3U << DSI_LCVCIDR_VCID_Pos) /*!< 0x00000003 */
8857#define DSI_LCVCIDR_VCID DSI_LCVCIDR_VCID_Msk /*!< Virtual Channel ID */
8858#define DSI_LCVCIDR_VCID0_Pos (0U)
8859#define DSI_LCVCIDR_VCID0_Msk (0x1U << DSI_LCVCIDR_VCID0_Pos) /*!< 0x00000001 */
8860#define DSI_LCVCIDR_VCID0 DSI_LCVCIDR_VCID0_Msk
8861#define DSI_LCVCIDR_VCID1_Pos (1U)
8862#define DSI_LCVCIDR_VCID1_Msk (0x1U << DSI_LCVCIDR_VCID1_Pos) /*!< 0x00000002 */
8863#define DSI_LCVCIDR_VCID1 DSI_LCVCIDR_VCID1_Msk
8864
8865/******************* Bit definition for DSI_LCCCR register **************/
8866#define DSI_LCCCR_COLC_Pos (0U)
8867#define DSI_LCCCR_COLC_Msk (0xFU << DSI_LCCCR_COLC_Pos) /*!< 0x0000000F */
8868#define DSI_LCCCR_COLC DSI_LCCCR_COLC_Msk /*!< Color Coding */
8869#define DSI_LCCCR_COLC0_Pos (0U)
8870#define DSI_LCCCR_COLC0_Msk (0x1U << DSI_LCCCR_COLC0_Pos) /*!< 0x00000001 */
8871#define DSI_LCCCR_COLC0 DSI_LCCCR_COLC0_Msk
8872#define DSI_LCCCR_COLC1_Pos (1U)
8873#define DSI_LCCCR_COLC1_Msk (0x1U << DSI_LCCCR_COLC1_Pos) /*!< 0x00000002 */
8874#define DSI_LCCCR_COLC1 DSI_LCCCR_COLC1_Msk
8875#define DSI_LCCCR_COLC2_Pos (2U)
8876#define DSI_LCCCR_COLC2_Msk (0x1U << DSI_LCCCR_COLC2_Pos) /*!< 0x00000004 */
8877#define DSI_LCCCR_COLC2 DSI_LCCCR_COLC2_Msk
8878#define DSI_LCCCR_COLC3_Pos (3U)
8879#define DSI_LCCCR_COLC3_Msk (0x1U << DSI_LCCCR_COLC3_Pos) /*!< 0x00000008 */
8880#define DSI_LCCCR_COLC3 DSI_LCCCR_COLC3_Msk
8881
8882#define DSI_LCCCR_LPE_Pos (8U)
8883#define DSI_LCCCR_LPE_Msk (0x1U << DSI_LCCCR_LPE_Pos) /*!< 0x00000100 */
8884#define DSI_LCCCR_LPE DSI_LCCCR_LPE_Msk /*!< Loosely Packed Enable */
8885
8886/******************* Bit definition for DSI_LPMCCR register *************/
8887#define DSI_LPMCCR_VLPSIZE_Pos (0U)
8888#define DSI_LPMCCR_VLPSIZE_Msk (0xFFU << DSI_LPMCCR_VLPSIZE_Pos) /*!< 0x000000FF */
8889#define DSI_LPMCCR_VLPSIZE DSI_LPMCCR_VLPSIZE_Msk /*!< VACT Largest Packet Size */
8890#define DSI_LPMCCR_VLPSIZE0_Pos (0U)
8891#define DSI_LPMCCR_VLPSIZE0_Msk (0x1U << DSI_LPMCCR_VLPSIZE0_Pos) /*!< 0x00000001 */
8892#define DSI_LPMCCR_VLPSIZE0 DSI_LPMCCR_VLPSIZE0_Msk
8893#define DSI_LPMCCR_VLPSIZE1_Pos (1U)
8894#define DSI_LPMCCR_VLPSIZE1_Msk (0x1U << DSI_LPMCCR_VLPSIZE1_Pos) /*!< 0x00000002 */
8895#define DSI_LPMCCR_VLPSIZE1 DSI_LPMCCR_VLPSIZE1_Msk
8896#define DSI_LPMCCR_VLPSIZE2_Pos (2U)
8897#define DSI_LPMCCR_VLPSIZE2_Msk (0x1U << DSI_LPMCCR_VLPSIZE2_Pos) /*!< 0x00000004 */
8898#define DSI_LPMCCR_VLPSIZE2 DSI_LPMCCR_VLPSIZE2_Msk
8899#define DSI_LPMCCR_VLPSIZE3_Pos (3U)
8900#define DSI_LPMCCR_VLPSIZE3_Msk (0x1U << DSI_LPMCCR_VLPSIZE3_Pos) /*!< 0x00000008 */
8901#define DSI_LPMCCR_VLPSIZE3 DSI_LPMCCR_VLPSIZE3_Msk
8902#define DSI_LPMCCR_VLPSIZE4_Pos (4U)
8903#define DSI_LPMCCR_VLPSIZE4_Msk (0x1U << DSI_LPMCCR_VLPSIZE4_Pos) /*!< 0x00000010 */
8904#define DSI_LPMCCR_VLPSIZE4 DSI_LPMCCR_VLPSIZE4_Msk
8905#define DSI_LPMCCR_VLPSIZE5_Pos (5U)
8906#define DSI_LPMCCR_VLPSIZE5_Msk (0x1U << DSI_LPMCCR_VLPSIZE5_Pos) /*!< 0x00000020 */
8907#define DSI_LPMCCR_VLPSIZE5 DSI_LPMCCR_VLPSIZE5_Msk
8908#define DSI_LPMCCR_VLPSIZE6_Pos (6U)
8909#define DSI_LPMCCR_VLPSIZE6_Msk (0x1U << DSI_LPMCCR_VLPSIZE6_Pos) /*!< 0x00000040 */
8910#define DSI_LPMCCR_VLPSIZE6 DSI_LPMCCR_VLPSIZE6_Msk
8911#define DSI_LPMCCR_VLPSIZE7_Pos (7U)
8912#define DSI_LPMCCR_VLPSIZE7_Msk (0x1U << DSI_LPMCCR_VLPSIZE7_Pos) /*!< 0x00000080 */
8913#define DSI_LPMCCR_VLPSIZE7 DSI_LPMCCR_VLPSIZE7_Msk
8914
8915#define DSI_LPMCCR_LPSIZE_Pos (16U)
8916#define DSI_LPMCCR_LPSIZE_Msk (0xFFU << DSI_LPMCCR_LPSIZE_Pos) /*!< 0x00FF0000 */
8917#define DSI_LPMCCR_LPSIZE DSI_LPMCCR_LPSIZE_Msk /*!< Largest Packet Size */
8918#define DSI_LPMCCR_LPSIZE0_Pos (16U)
8919#define DSI_LPMCCR_LPSIZE0_Msk (0x1U << DSI_LPMCCR_LPSIZE0_Pos) /*!< 0x00010000 */
8920#define DSI_LPMCCR_LPSIZE0 DSI_LPMCCR_LPSIZE0_Msk
8921#define DSI_LPMCCR_LPSIZE1_Pos (17U)
8922#define DSI_LPMCCR_LPSIZE1_Msk (0x1U << DSI_LPMCCR_LPSIZE1_Pos) /*!< 0x00020000 */
8923#define DSI_LPMCCR_LPSIZE1 DSI_LPMCCR_LPSIZE1_Msk
8924#define DSI_LPMCCR_LPSIZE2_Pos (18U)
8925#define DSI_LPMCCR_LPSIZE2_Msk (0x1U << DSI_LPMCCR_LPSIZE2_Pos) /*!< 0x00040000 */
8926#define DSI_LPMCCR_LPSIZE2 DSI_LPMCCR_LPSIZE2_Msk
8927#define DSI_LPMCCR_LPSIZE3_Pos (19U)
8928#define DSI_LPMCCR_LPSIZE3_Msk (0x1U << DSI_LPMCCR_LPSIZE3_Pos) /*!< 0x00080000 */
8929#define DSI_LPMCCR_LPSIZE3 DSI_LPMCCR_LPSIZE3_Msk
8930#define DSI_LPMCCR_LPSIZE4_Pos (20U)
8931#define DSI_LPMCCR_LPSIZE4_Msk (0x1U << DSI_LPMCCR_LPSIZE4_Pos) /*!< 0x00100000 */
8932#define DSI_LPMCCR_LPSIZE4 DSI_LPMCCR_LPSIZE4_Msk
8933#define DSI_LPMCCR_LPSIZE5_Pos (21U)
8934#define DSI_LPMCCR_LPSIZE5_Msk (0x1U << DSI_LPMCCR_LPSIZE5_Pos) /*!< 0x00200000 */
8935#define DSI_LPMCCR_LPSIZE5 DSI_LPMCCR_LPSIZE5_Msk
8936#define DSI_LPMCCR_LPSIZE6_Pos (22U)
8937#define DSI_LPMCCR_LPSIZE6_Msk (0x1U << DSI_LPMCCR_LPSIZE6_Pos) /*!< 0x00400000 */
8938#define DSI_LPMCCR_LPSIZE6 DSI_LPMCCR_LPSIZE6_Msk
8939#define DSI_LPMCCR_LPSIZE7_Pos (23U)
8940#define DSI_LPMCCR_LPSIZE7_Msk (0x1U << DSI_LPMCCR_LPSIZE7_Pos) /*!< 0x00800000 */
8941#define DSI_LPMCCR_LPSIZE7 DSI_LPMCCR_LPSIZE7_Msk
8942
8943/******************* Bit definition for DSI_VMCCR register **************/
8944#define DSI_VMCCR_VMT_Pos (0U)
8945#define DSI_VMCCR_VMT_Msk (0x3U << DSI_VMCCR_VMT_Pos) /*!< 0x00000003 */
8946#define DSI_VMCCR_VMT DSI_VMCCR_VMT_Msk /*!< Video Mode Type */
8947#define DSI_VMCCR_VMT0_Pos (0U)
8948#define DSI_VMCCR_VMT0_Msk (0x1U << DSI_VMCCR_VMT0_Pos) /*!< 0x00000001 */
8949#define DSI_VMCCR_VMT0 DSI_VMCCR_VMT0_Msk
8950#define DSI_VMCCR_VMT1_Pos (1U)
8951#define DSI_VMCCR_VMT1_Msk (0x1U << DSI_VMCCR_VMT1_Pos) /*!< 0x00000002 */
8952#define DSI_VMCCR_VMT1 DSI_VMCCR_VMT1_Msk
8953
8954#define DSI_VMCCR_LPVSAE_Pos (8U)
8955#define DSI_VMCCR_LPVSAE_Msk (0x1U << DSI_VMCCR_LPVSAE_Pos) /*!< 0x00000100 */
8956#define DSI_VMCCR_LPVSAE DSI_VMCCR_LPVSAE_Msk /*!< Low-power Vertical Sync time Enable */
8957#define DSI_VMCCR_LPVBPE_Pos (9U)
8958#define DSI_VMCCR_LPVBPE_Msk (0x1U << DSI_VMCCR_LPVBPE_Pos) /*!< 0x00000200 */
8959#define DSI_VMCCR_LPVBPE DSI_VMCCR_LPVBPE_Msk /*!< Low-power Vertical Back-porch Enable */
8960#define DSI_VMCCR_LPVFPE_Pos (10U)
8961#define DSI_VMCCR_LPVFPE_Msk (0x1U << DSI_VMCCR_LPVFPE_Pos) /*!< 0x00000400 */
8962#define DSI_VMCCR_LPVFPE DSI_VMCCR_LPVFPE_Msk /*!< Low-power Vertical Front-porch Enable */
8963#define DSI_VMCCR_LPVAE_Pos (11U)
8964#define DSI_VMCCR_LPVAE_Msk (0x1U << DSI_VMCCR_LPVAE_Pos) /*!< 0x00000800 */
8965#define DSI_VMCCR_LPVAE DSI_VMCCR_LPVAE_Msk /*!< Low-power Vertical Active Enable */
8966#define DSI_VMCCR_LPHBPE_Pos (12U)
8967#define DSI_VMCCR_LPHBPE_Msk (0x1U << DSI_VMCCR_LPHBPE_Pos) /*!< 0x00001000 */
8968#define DSI_VMCCR_LPHBPE DSI_VMCCR_LPHBPE_Msk /*!< Low-power Horizontal Back-porch Enable */
8969#define DSI_VMCCR_LPHFE_Pos (13U)
8970#define DSI_VMCCR_LPHFE_Msk (0x1U << DSI_VMCCR_LPHFE_Pos) /*!< 0x00002000 */
8971#define DSI_VMCCR_LPHFE DSI_VMCCR_LPHFE_Msk /*!< Low-power Horizontal Front-porch Enable */
8972#define DSI_VMCCR_FBTAAE_Pos (14U)
8973#define DSI_VMCCR_FBTAAE_Msk (0x1U << DSI_VMCCR_FBTAAE_Pos) /*!< 0x00004000 */
8974#define DSI_VMCCR_FBTAAE DSI_VMCCR_FBTAAE_Msk /*!< Frame BTA Acknowledge Enable */
8975#define DSI_VMCCR_LPCE_Pos (15U)
8976#define DSI_VMCCR_LPCE_Msk (0x1U << DSI_VMCCR_LPCE_Pos) /*!< 0x00008000 */
8977#define DSI_VMCCR_LPCE DSI_VMCCR_LPCE_Msk /*!< Low-power Command Enable */
8978
8979/******************* Bit definition for DSI_VPCCR register **************/
8980#define DSI_VPCCR_VPSIZE_Pos (0U)
8981#define DSI_VPCCR_VPSIZE_Msk (0x3FFFU << DSI_VPCCR_VPSIZE_Pos) /*!< 0x00003FFF */
8982#define DSI_VPCCR_VPSIZE DSI_VPCCR_VPSIZE_Msk /*!< Video Packet Size */
8983#define DSI_VPCCR_VPSIZE0_Pos (0U)
8984#define DSI_VPCCR_VPSIZE0_Msk (0x1U << DSI_VPCCR_VPSIZE0_Pos) /*!< 0x00000001 */
8985#define DSI_VPCCR_VPSIZE0 DSI_VPCCR_VPSIZE0_Msk
8986#define DSI_VPCCR_VPSIZE1_Pos (1U)
8987#define DSI_VPCCR_VPSIZE1_Msk (0x1U << DSI_VPCCR_VPSIZE1_Pos) /*!< 0x00000002 */
8988#define DSI_VPCCR_VPSIZE1 DSI_VPCCR_VPSIZE1_Msk
8989#define DSI_VPCCR_VPSIZE2_Pos (2U)
8990#define DSI_VPCCR_VPSIZE2_Msk (0x1U << DSI_VPCCR_VPSIZE2_Pos) /*!< 0x00000004 */
8991#define DSI_VPCCR_VPSIZE2 DSI_VPCCR_VPSIZE2_Msk
8992#define DSI_VPCCR_VPSIZE3_Pos (3U)
8993#define DSI_VPCCR_VPSIZE3_Msk (0x1U << DSI_VPCCR_VPSIZE3_Pos) /*!< 0x00000008 */
8994#define DSI_VPCCR_VPSIZE3 DSI_VPCCR_VPSIZE3_Msk
8995#define DSI_VPCCR_VPSIZE4_Pos (4U)
8996#define DSI_VPCCR_VPSIZE4_Msk (0x1U << DSI_VPCCR_VPSIZE4_Pos) /*!< 0x00000010 */
8997#define DSI_VPCCR_VPSIZE4 DSI_VPCCR_VPSIZE4_Msk
8998#define DSI_VPCCR_VPSIZE5_Pos (5U)
8999#define DSI_VPCCR_VPSIZE5_Msk (0x1U << DSI_VPCCR_VPSIZE5_Pos) /*!< 0x00000020 */
9000#define DSI_VPCCR_VPSIZE5 DSI_VPCCR_VPSIZE5_Msk
9001#define DSI_VPCCR_VPSIZE6_Pos (6U)
9002#define DSI_VPCCR_VPSIZE6_Msk (0x1U << DSI_VPCCR_VPSIZE6_Pos) /*!< 0x00000040 */
9003#define DSI_VPCCR_VPSIZE6 DSI_VPCCR_VPSIZE6_Msk
9004#define DSI_VPCCR_VPSIZE7_Pos (7U)
9005#define DSI_VPCCR_VPSIZE7_Msk (0x1U << DSI_VPCCR_VPSIZE7_Pos) /*!< 0x00000080 */
9006#define DSI_VPCCR_VPSIZE7 DSI_VPCCR_VPSIZE7_Msk
9007#define DSI_VPCCR_VPSIZE8_Pos (8U)
9008#define DSI_VPCCR_VPSIZE8_Msk (0x1U << DSI_VPCCR_VPSIZE8_Pos) /*!< 0x00000100 */
9009#define DSI_VPCCR_VPSIZE8 DSI_VPCCR_VPSIZE8_Msk
9010#define DSI_VPCCR_VPSIZE9_Pos (9U)
9011#define DSI_VPCCR_VPSIZE9_Msk (0x1U << DSI_VPCCR_VPSIZE9_Pos) /*!< 0x00000200 */
9012#define DSI_VPCCR_VPSIZE9 DSI_VPCCR_VPSIZE9_Msk
9013#define DSI_VPCCR_VPSIZE10_Pos (10U)
9014#define DSI_VPCCR_VPSIZE10_Msk (0x1U << DSI_VPCCR_VPSIZE10_Pos) /*!< 0x00000400 */
9015#define DSI_VPCCR_VPSIZE10 DSI_VPCCR_VPSIZE10_Msk
9016#define DSI_VPCCR_VPSIZE11_Pos (11U)
9017#define DSI_VPCCR_VPSIZE11_Msk (0x1U << DSI_VPCCR_VPSIZE11_Pos) /*!< 0x00000800 */
9018#define DSI_VPCCR_VPSIZE11 DSI_VPCCR_VPSIZE11_Msk
9019#define DSI_VPCCR_VPSIZE12_Pos (12U)
9020#define DSI_VPCCR_VPSIZE12_Msk (0x1U << DSI_VPCCR_VPSIZE12_Pos) /*!< 0x00001000 */
9021#define DSI_VPCCR_VPSIZE12 DSI_VPCCR_VPSIZE12_Msk
9022#define DSI_VPCCR_VPSIZE13_Pos (13U)
9023#define DSI_VPCCR_VPSIZE13_Msk (0x1U << DSI_VPCCR_VPSIZE13_Pos) /*!< 0x00002000 */
9024#define DSI_VPCCR_VPSIZE13 DSI_VPCCR_VPSIZE13_Msk
9025
9026/******************* Bit definition for DSI_VCCCR register **************/
9027#define DSI_VCCCR_NUMC_Pos (0U)
9028#define DSI_VCCCR_NUMC_Msk (0x1FFFU << DSI_VCCCR_NUMC_Pos) /*!< 0x00001FFF */
9029#define DSI_VCCCR_NUMC DSI_VCCCR_NUMC_Msk /*!< Number of Chunks */
9030#define DSI_VCCCR_NUMC0_Pos (0U)
9031#define DSI_VCCCR_NUMC0_Msk (0x1U << DSI_VCCCR_NUMC0_Pos) /*!< 0x00000001 */
9032#define DSI_VCCCR_NUMC0 DSI_VCCCR_NUMC0_Msk
9033#define DSI_VCCCR_NUMC1_Pos (1U)
9034#define DSI_VCCCR_NUMC1_Msk (0x1U << DSI_VCCCR_NUMC1_Pos) /*!< 0x00000002 */
9035#define DSI_VCCCR_NUMC1 DSI_VCCCR_NUMC1_Msk
9036#define DSI_VCCCR_NUMC2_Pos (2U)
9037#define DSI_VCCCR_NUMC2_Msk (0x1U << DSI_VCCCR_NUMC2_Pos) /*!< 0x00000004 */
9038#define DSI_VCCCR_NUMC2 DSI_VCCCR_NUMC2_Msk
9039#define DSI_VCCCR_NUMC3_Pos (3U)
9040#define DSI_VCCCR_NUMC3_Msk (0x1U << DSI_VCCCR_NUMC3_Pos) /*!< 0x00000008 */
9041#define DSI_VCCCR_NUMC3 DSI_VCCCR_NUMC3_Msk
9042#define DSI_VCCCR_NUMC4_Pos (4U)
9043#define DSI_VCCCR_NUMC4_Msk (0x1U << DSI_VCCCR_NUMC4_Pos) /*!< 0x00000010 */
9044#define DSI_VCCCR_NUMC4 DSI_VCCCR_NUMC4_Msk
9045#define DSI_VCCCR_NUMC5_Pos (5U)
9046#define DSI_VCCCR_NUMC5_Msk (0x1U << DSI_VCCCR_NUMC5_Pos) /*!< 0x00000020 */
9047#define DSI_VCCCR_NUMC5 DSI_VCCCR_NUMC5_Msk
9048#define DSI_VCCCR_NUMC6_Pos (6U)
9049#define DSI_VCCCR_NUMC6_Msk (0x1U << DSI_VCCCR_NUMC6_Pos) /*!< 0x00000040 */
9050#define DSI_VCCCR_NUMC6 DSI_VCCCR_NUMC6_Msk
9051#define DSI_VCCCR_NUMC7_Pos (7U)
9052#define DSI_VCCCR_NUMC7_Msk (0x1U << DSI_VCCCR_NUMC7_Pos) /*!< 0x00000080 */
9053#define DSI_VCCCR_NUMC7 DSI_VCCCR_NUMC7_Msk
9054#define DSI_VCCCR_NUMC8_Pos (8U)
9055#define DSI_VCCCR_NUMC8_Msk (0x1U << DSI_VCCCR_NUMC8_Pos) /*!< 0x00000100 */
9056#define DSI_VCCCR_NUMC8 DSI_VCCCR_NUMC8_Msk
9057#define DSI_VCCCR_NUMC9_Pos (9U)
9058#define DSI_VCCCR_NUMC9_Msk (0x1U << DSI_VCCCR_NUMC9_Pos) /*!< 0x00000200 */
9059#define DSI_VCCCR_NUMC9 DSI_VCCCR_NUMC9_Msk
9060#define DSI_VCCCR_NUMC10_Pos (10U)
9061#define DSI_VCCCR_NUMC10_Msk (0x1U << DSI_VCCCR_NUMC10_Pos) /*!< 0x00000400 */
9062#define DSI_VCCCR_NUMC10 DSI_VCCCR_NUMC10_Msk
9063#define DSI_VCCCR_NUMC11_Pos (11U)
9064#define DSI_VCCCR_NUMC11_Msk (0x1U << DSI_VCCCR_NUMC11_Pos) /*!< 0x00000800 */
9065#define DSI_VCCCR_NUMC11 DSI_VCCCR_NUMC11_Msk
9066#define DSI_VCCCR_NUMC12_Pos (12U)
9067#define DSI_VCCCR_NUMC12_Msk (0x1U << DSI_VCCCR_NUMC12_Pos) /*!< 0x00001000 */
9068#define DSI_VCCCR_NUMC12 DSI_VCCCR_NUMC12_Msk
9069
9070/******************* Bit definition for DSI_VNPCCR register *************/
9071#define DSI_VNPCCR_NPSIZE_Pos (0U)
9072#define DSI_VNPCCR_NPSIZE_Msk (0x1FFFU << DSI_VNPCCR_NPSIZE_Pos) /*!< 0x00001FFF */
9073#define DSI_VNPCCR_NPSIZE DSI_VNPCCR_NPSIZE_Msk /*!< Number of Chunks */
9074#define DSI_VNPCCR_NPSIZE0_Pos (0U)
9075#define DSI_VNPCCR_NPSIZE0_Msk (0x1U << DSI_VNPCCR_NPSIZE0_Pos) /*!< 0x00000001 */
9076#define DSI_VNPCCR_NPSIZE0 DSI_VNPCCR_NPSIZE0_Msk
9077#define DSI_VNPCCR_NPSIZE1_Pos (1U)
9078#define DSI_VNPCCR_NPSIZE1_Msk (0x1U << DSI_VNPCCR_NPSIZE1_Pos) /*!< 0x00000002 */
9079#define DSI_VNPCCR_NPSIZE1 DSI_VNPCCR_NPSIZE1_Msk
9080#define DSI_VNPCCR_NPSIZE2_Pos (2U)
9081#define DSI_VNPCCR_NPSIZE2_Msk (0x1U << DSI_VNPCCR_NPSIZE2_Pos) /*!< 0x00000004 */
9082#define DSI_VNPCCR_NPSIZE2 DSI_VNPCCR_NPSIZE2_Msk
9083#define DSI_VNPCCR_NPSIZE3_Pos (3U)
9084#define DSI_VNPCCR_NPSIZE3_Msk (0x1U << DSI_VNPCCR_NPSIZE3_Pos) /*!< 0x00000008 */
9085#define DSI_VNPCCR_NPSIZE3 DSI_VNPCCR_NPSIZE3_Msk
9086#define DSI_VNPCCR_NPSIZE4_Pos (4U)
9087#define DSI_VNPCCR_NPSIZE4_Msk (0x1U << DSI_VNPCCR_NPSIZE4_Pos) /*!< 0x00000010 */
9088#define DSI_VNPCCR_NPSIZE4 DSI_VNPCCR_NPSIZE4_Msk
9089#define DSI_VNPCCR_NPSIZE5_Pos (5U)
9090#define DSI_VNPCCR_NPSIZE5_Msk (0x1U << DSI_VNPCCR_NPSIZE5_Pos) /*!< 0x00000020 */
9091#define DSI_VNPCCR_NPSIZE5 DSI_VNPCCR_NPSIZE5_Msk
9092#define DSI_VNPCCR_NPSIZE6_Pos (6U)
9093#define DSI_VNPCCR_NPSIZE6_Msk (0x1U << DSI_VNPCCR_NPSIZE6_Pos) /*!< 0x00000040 */
9094#define DSI_VNPCCR_NPSIZE6 DSI_VNPCCR_NPSIZE6_Msk
9095#define DSI_VNPCCR_NPSIZE7_Pos (7U)
9096#define DSI_VNPCCR_NPSIZE7_Msk (0x1U << DSI_VNPCCR_NPSIZE7_Pos) /*!< 0x00000080 */
9097#define DSI_VNPCCR_NPSIZE7 DSI_VNPCCR_NPSIZE7_Msk
9098#define DSI_VNPCCR_NPSIZE8_Pos (8U)
9099#define DSI_VNPCCR_NPSIZE8_Msk (0x1U << DSI_VNPCCR_NPSIZE8_Pos) /*!< 0x00000100 */
9100#define DSI_VNPCCR_NPSIZE8 DSI_VNPCCR_NPSIZE8_Msk
9101#define DSI_VNPCCR_NPSIZE9_Pos (9U)
9102#define DSI_VNPCCR_NPSIZE9_Msk (0x1U << DSI_VNPCCR_NPSIZE9_Pos) /*!< 0x00000200 */
9103#define DSI_VNPCCR_NPSIZE9 DSI_VNPCCR_NPSIZE9_Msk
9104#define DSI_VNPCCR_NPSIZE10_Pos (10U)
9105#define DSI_VNPCCR_NPSIZE10_Msk (0x1U << DSI_VNPCCR_NPSIZE10_Pos) /*!< 0x00000400 */
9106#define DSI_VNPCCR_NPSIZE10 DSI_VNPCCR_NPSIZE10_Msk
9107#define DSI_VNPCCR_NPSIZE11_Pos (11U)
9108#define DSI_VNPCCR_NPSIZE11_Msk (0x1U << DSI_VNPCCR_NPSIZE11_Pos) /*!< 0x00000800 */
9109#define DSI_VNPCCR_NPSIZE11 DSI_VNPCCR_NPSIZE11_Msk
9110#define DSI_VNPCCR_NPSIZE12_Pos (12U)
9111#define DSI_VNPCCR_NPSIZE12_Msk (0x1U << DSI_VNPCCR_NPSIZE12_Pos) /*!< 0x00001000 */
9112#define DSI_VNPCCR_NPSIZE12 DSI_VNPCCR_NPSIZE12_Msk
9113
9114/******************* Bit definition for DSI_VHSACCR register ************/
9115#define DSI_VHSACCR_HSA_Pos (0U)
9116#define DSI_VHSACCR_HSA_Msk (0xFFFU << DSI_VHSACCR_HSA_Pos) /*!< 0x00000FFF */
9117#define DSI_VHSACCR_HSA DSI_VHSACCR_HSA_Msk /*!< Horizontal Synchronism Active duration */
9118#define DSI_VHSACCR_HSA0_Pos (0U)
9119#define DSI_VHSACCR_HSA0_Msk (0x1U << DSI_VHSACCR_HSA0_Pos) /*!< 0x00000001 */
9120#define DSI_VHSACCR_HSA0 DSI_VHSACCR_HSA0_Msk
9121#define DSI_VHSACCR_HSA1_Pos (1U)
9122#define DSI_VHSACCR_HSA1_Msk (0x1U << DSI_VHSACCR_HSA1_Pos) /*!< 0x00000002 */
9123#define DSI_VHSACCR_HSA1 DSI_VHSACCR_HSA1_Msk
9124#define DSI_VHSACCR_HSA2_Pos (2U)
9125#define DSI_VHSACCR_HSA2_Msk (0x1U << DSI_VHSACCR_HSA2_Pos) /*!< 0x00000004 */
9126#define DSI_VHSACCR_HSA2 DSI_VHSACCR_HSA2_Msk
9127#define DSI_VHSACCR_HSA3_Pos (3U)
9128#define DSI_VHSACCR_HSA3_Msk (0x1U << DSI_VHSACCR_HSA3_Pos) /*!< 0x00000008 */
9129#define DSI_VHSACCR_HSA3 DSI_VHSACCR_HSA3_Msk
9130#define DSI_VHSACCR_HSA4_Pos (4U)
9131#define DSI_VHSACCR_HSA4_Msk (0x1U << DSI_VHSACCR_HSA4_Pos) /*!< 0x00000010 */
9132#define DSI_VHSACCR_HSA4 DSI_VHSACCR_HSA4_Msk
9133#define DSI_VHSACCR_HSA5_Pos (5U)
9134#define DSI_VHSACCR_HSA5_Msk (0x1U << DSI_VHSACCR_HSA5_Pos) /*!< 0x00000020 */
9135#define DSI_VHSACCR_HSA5 DSI_VHSACCR_HSA5_Msk
9136#define DSI_VHSACCR_HSA6_Pos (6U)
9137#define DSI_VHSACCR_HSA6_Msk (0x1U << DSI_VHSACCR_HSA6_Pos) /*!< 0x00000040 */
9138#define DSI_VHSACCR_HSA6 DSI_VHSACCR_HSA6_Msk
9139#define DSI_VHSACCR_HSA7_Pos (7U)
9140#define DSI_VHSACCR_HSA7_Msk (0x1U << DSI_VHSACCR_HSA7_Pos) /*!< 0x00000080 */
9141#define DSI_VHSACCR_HSA7 DSI_VHSACCR_HSA7_Msk
9142#define DSI_VHSACCR_HSA8_Pos (8U)
9143#define DSI_VHSACCR_HSA8_Msk (0x1U << DSI_VHSACCR_HSA8_Pos) /*!< 0x00000100 */
9144#define DSI_VHSACCR_HSA8 DSI_VHSACCR_HSA8_Msk
9145#define DSI_VHSACCR_HSA9_Pos (9U)
9146#define DSI_VHSACCR_HSA9_Msk (0x1U << DSI_VHSACCR_HSA9_Pos) /*!< 0x00000200 */
9147#define DSI_VHSACCR_HSA9 DSI_VHSACCR_HSA9_Msk
9148#define DSI_VHSACCR_HSA10_Pos (10U)
9149#define DSI_VHSACCR_HSA10_Msk (0x1U << DSI_VHSACCR_HSA10_Pos) /*!< 0x00000400 */
9150#define DSI_VHSACCR_HSA10 DSI_VHSACCR_HSA10_Msk
9151#define DSI_VHSACCR_HSA11_Pos (11U)
9152#define DSI_VHSACCR_HSA11_Msk (0x1U << DSI_VHSACCR_HSA11_Pos) /*!< 0x00000800 */
9153#define DSI_VHSACCR_HSA11 DSI_VHSACCR_HSA11_Msk
9154
9155/******************* Bit definition for DSI_VHBPCCR register ************/
9156#define DSI_VHBPCCR_HBP_Pos (0U)
9157#define DSI_VHBPCCR_HBP_Msk (0xFFFU << DSI_VHBPCCR_HBP_Pos) /*!< 0x00000FFF */
9158#define DSI_VHBPCCR_HBP DSI_VHBPCCR_HBP_Msk /*!< Horizontal Back-Porch duration */
9159#define DSI_VHBPCCR_HBP0_Pos (0U)
9160#define DSI_VHBPCCR_HBP0_Msk (0x1U << DSI_VHBPCCR_HBP0_Pos) /*!< 0x00000001 */
9161#define DSI_VHBPCCR_HBP0 DSI_VHBPCCR_HBP0_Msk
9162#define DSI_VHBPCCR_HBP1_Pos (1U)
9163#define DSI_VHBPCCR_HBP1_Msk (0x1U << DSI_VHBPCCR_HBP1_Pos) /*!< 0x00000002 */
9164#define DSI_VHBPCCR_HBP1 DSI_VHBPCCR_HBP1_Msk
9165#define DSI_VHBPCCR_HBP2_Pos (2U)
9166#define DSI_VHBPCCR_HBP2_Msk (0x1U << DSI_VHBPCCR_HBP2_Pos) /*!< 0x00000004 */
9167#define DSI_VHBPCCR_HBP2 DSI_VHBPCCR_HBP2_Msk
9168#define DSI_VHBPCCR_HBP3_Pos (3U)
9169#define DSI_VHBPCCR_HBP3_Msk (0x1U << DSI_VHBPCCR_HBP3_Pos) /*!< 0x00000008 */
9170#define DSI_VHBPCCR_HBP3 DSI_VHBPCCR_HBP3_Msk
9171#define DSI_VHBPCCR_HBP4_Pos (4U)
9172#define DSI_VHBPCCR_HBP4_Msk (0x1U << DSI_VHBPCCR_HBP4_Pos) /*!< 0x00000010 */
9173#define DSI_VHBPCCR_HBP4 DSI_VHBPCCR_HBP4_Msk
9174#define DSI_VHBPCCR_HBP5_Pos (5U)
9175#define DSI_VHBPCCR_HBP5_Msk (0x1U << DSI_VHBPCCR_HBP5_Pos) /*!< 0x00000020 */
9176#define DSI_VHBPCCR_HBP5 DSI_VHBPCCR_HBP5_Msk
9177#define DSI_VHBPCCR_HBP6_Pos (6U)
9178#define DSI_VHBPCCR_HBP6_Msk (0x1U << DSI_VHBPCCR_HBP6_Pos) /*!< 0x00000040 */
9179#define DSI_VHBPCCR_HBP6 DSI_VHBPCCR_HBP6_Msk
9180#define DSI_VHBPCCR_HBP7_Pos (7U)
9181#define DSI_VHBPCCR_HBP7_Msk (0x1U << DSI_VHBPCCR_HBP7_Pos) /*!< 0x00000080 */
9182#define DSI_VHBPCCR_HBP7 DSI_VHBPCCR_HBP7_Msk
9183#define DSI_VHBPCCR_HBP8_Pos (8U)
9184#define DSI_VHBPCCR_HBP8_Msk (0x1U << DSI_VHBPCCR_HBP8_Pos) /*!< 0x00000100 */
9185#define DSI_VHBPCCR_HBP8 DSI_VHBPCCR_HBP8_Msk
9186#define DSI_VHBPCCR_HBP9_Pos (9U)
9187#define DSI_VHBPCCR_HBP9_Msk (0x1U << DSI_VHBPCCR_HBP9_Pos) /*!< 0x00000200 */
9188#define DSI_VHBPCCR_HBP9 DSI_VHBPCCR_HBP9_Msk
9189#define DSI_VHBPCCR_HBP10_Pos (10U)
9190#define DSI_VHBPCCR_HBP10_Msk (0x1U << DSI_VHBPCCR_HBP10_Pos) /*!< 0x00000400 */
9191#define DSI_VHBPCCR_HBP10 DSI_VHBPCCR_HBP10_Msk
9192#define DSI_VHBPCCR_HBP11_Pos (11U)
9193#define DSI_VHBPCCR_HBP11_Msk (0x1U << DSI_VHBPCCR_HBP11_Pos) /*!< 0x00000800 */
9194#define DSI_VHBPCCR_HBP11 DSI_VHBPCCR_HBP11_Msk
9195
9196/******************* Bit definition for DSI_VLCCR register **************/
9197#define DSI_VLCCR_HLINE_Pos (0U)
9198#define DSI_VLCCR_HLINE_Msk (0x7FFFU << DSI_VLCCR_HLINE_Pos) /*!< 0x00007FFF */
9199#define DSI_VLCCR_HLINE DSI_VLCCR_HLINE_Msk /*!< Horizontal Line duration */
9200#define DSI_VLCCR_HLINE0_Pos (0U)
9201#define DSI_VLCCR_HLINE0_Msk (0x1U << DSI_VLCCR_HLINE0_Pos) /*!< 0x00000001 */
9202#define DSI_VLCCR_HLINE0 DSI_VLCCR_HLINE0_Msk
9203#define DSI_VLCCR_HLINE1_Pos (1U)
9204#define DSI_VLCCR_HLINE1_Msk (0x1U << DSI_VLCCR_HLINE1_Pos) /*!< 0x00000002 */
9205#define DSI_VLCCR_HLINE1 DSI_VLCCR_HLINE1_Msk
9206#define DSI_VLCCR_HLINE2_Pos (2U)
9207#define DSI_VLCCR_HLINE2_Msk (0x1U << DSI_VLCCR_HLINE2_Pos) /*!< 0x00000004 */
9208#define DSI_VLCCR_HLINE2 DSI_VLCCR_HLINE2_Msk
9209#define DSI_VLCCR_HLINE3_Pos (3U)
9210#define DSI_VLCCR_HLINE3_Msk (0x1U << DSI_VLCCR_HLINE3_Pos) /*!< 0x00000008 */
9211#define DSI_VLCCR_HLINE3 DSI_VLCCR_HLINE3_Msk
9212#define DSI_VLCCR_HLINE4_Pos (4U)
9213#define DSI_VLCCR_HLINE4_Msk (0x1U << DSI_VLCCR_HLINE4_Pos) /*!< 0x00000010 */
9214#define DSI_VLCCR_HLINE4 DSI_VLCCR_HLINE4_Msk
9215#define DSI_VLCCR_HLINE5_Pos (5U)
9216#define DSI_VLCCR_HLINE5_Msk (0x1U << DSI_VLCCR_HLINE5_Pos) /*!< 0x00000020 */
9217#define DSI_VLCCR_HLINE5 DSI_VLCCR_HLINE5_Msk
9218#define DSI_VLCCR_HLINE6_Pos (6U)
9219#define DSI_VLCCR_HLINE6_Msk (0x1U << DSI_VLCCR_HLINE6_Pos) /*!< 0x00000040 */
9220#define DSI_VLCCR_HLINE6 DSI_VLCCR_HLINE6_Msk
9221#define DSI_VLCCR_HLINE7_Pos (7U)
9222#define DSI_VLCCR_HLINE7_Msk (0x1U << DSI_VLCCR_HLINE7_Pos) /*!< 0x00000080 */
9223#define DSI_VLCCR_HLINE7 DSI_VLCCR_HLINE7_Msk
9224#define DSI_VLCCR_HLINE8_Pos (8U)
9225#define DSI_VLCCR_HLINE8_Msk (0x1U << DSI_VLCCR_HLINE8_Pos) /*!< 0x00000100 */
9226#define DSI_VLCCR_HLINE8 DSI_VLCCR_HLINE8_Msk
9227#define DSI_VLCCR_HLINE9_Pos (9U)
9228#define DSI_VLCCR_HLINE9_Msk (0x1U << DSI_VLCCR_HLINE9_Pos) /*!< 0x00000200 */
9229#define DSI_VLCCR_HLINE9 DSI_VLCCR_HLINE9_Msk
9230#define DSI_VLCCR_HLINE10_Pos (10U)
9231#define DSI_VLCCR_HLINE10_Msk (0x1U << DSI_VLCCR_HLINE10_Pos) /*!< 0x00000400 */
9232#define DSI_VLCCR_HLINE10 DSI_VLCCR_HLINE10_Msk
9233#define DSI_VLCCR_HLINE11_Pos (11U)
9234#define DSI_VLCCR_HLINE11_Msk (0x1U << DSI_VLCCR_HLINE11_Pos) /*!< 0x00000800 */
9235#define DSI_VLCCR_HLINE11 DSI_VLCCR_HLINE11_Msk
9236#define DSI_VLCCR_HLINE12_Pos (12U)
9237#define DSI_VLCCR_HLINE12_Msk (0x1U << DSI_VLCCR_HLINE12_Pos) /*!< 0x00001000 */
9238#define DSI_VLCCR_HLINE12 DSI_VLCCR_HLINE12_Msk
9239#define DSI_VLCCR_HLINE13_Pos (13U)
9240#define DSI_VLCCR_HLINE13_Msk (0x1U << DSI_VLCCR_HLINE13_Pos) /*!< 0x00002000 */
9241#define DSI_VLCCR_HLINE13 DSI_VLCCR_HLINE13_Msk
9242#define DSI_VLCCR_HLINE14_Pos (14U)
9243#define DSI_VLCCR_HLINE14_Msk (0x1U << DSI_VLCCR_HLINE14_Pos) /*!< 0x00004000 */
9244#define DSI_VLCCR_HLINE14 DSI_VLCCR_HLINE14_Msk
9245
9246/******************* Bit definition for DSI_VVSACCR register ***************/
9247#define DSI_VVSACCR_VSA_Pos (0U)
9248#define DSI_VVSACCR_VSA_Msk (0x3FFU << DSI_VVSACCR_VSA_Pos) /*!< 0x000003FF */
9249#define DSI_VVSACCR_VSA DSI_VVSACCR_VSA_Msk /*!< Vertical Synchronism Active duration */
9250#define DSI_VVSACCR_VSA0_Pos (0U)
9251#define DSI_VVSACCR_VSA0_Msk (0x1U << DSI_VVSACCR_VSA0_Pos) /*!< 0x00000001 */
9252#define DSI_VVSACCR_VSA0 DSI_VVSACCR_VSA0_Msk
9253#define DSI_VVSACCR_VSA1_Pos (1U)
9254#define DSI_VVSACCR_VSA1_Msk (0x1U << DSI_VVSACCR_VSA1_Pos) /*!< 0x00000002 */
9255#define DSI_VVSACCR_VSA1 DSI_VVSACCR_VSA1_Msk
9256#define DSI_VVSACCR_VSA2_Pos (2U)
9257#define DSI_VVSACCR_VSA2_Msk (0x1U << DSI_VVSACCR_VSA2_Pos) /*!< 0x00000004 */
9258#define DSI_VVSACCR_VSA2 DSI_VVSACCR_VSA2_Msk
9259#define DSI_VVSACCR_VSA3_Pos (3U)
9260#define DSI_VVSACCR_VSA3_Msk (0x1U << DSI_VVSACCR_VSA3_Pos) /*!< 0x00000008 */
9261#define DSI_VVSACCR_VSA3 DSI_VVSACCR_VSA3_Msk
9262#define DSI_VVSACCR_VSA4_Pos (4U)
9263#define DSI_VVSACCR_VSA4_Msk (0x1U << DSI_VVSACCR_VSA4_Pos) /*!< 0x00000010 */
9264#define DSI_VVSACCR_VSA4 DSI_VVSACCR_VSA4_Msk
9265#define DSI_VVSACCR_VSA5_Pos (5U)
9266#define DSI_VVSACCR_VSA5_Msk (0x1U << DSI_VVSACCR_VSA5_Pos) /*!< 0x00000020 */
9267#define DSI_VVSACCR_VSA5 DSI_VVSACCR_VSA5_Msk
9268#define DSI_VVSACCR_VSA6_Pos (6U)
9269#define DSI_VVSACCR_VSA6_Msk (0x1U << DSI_VVSACCR_VSA6_Pos) /*!< 0x00000040 */
9270#define DSI_VVSACCR_VSA6 DSI_VVSACCR_VSA6_Msk
9271#define DSI_VVSACCR_VSA7_Pos (7U)
9272#define DSI_VVSACCR_VSA7_Msk (0x1U << DSI_VVSACCR_VSA7_Pos) /*!< 0x00000080 */
9273#define DSI_VVSACCR_VSA7 DSI_VVSACCR_VSA7_Msk
9274#define DSI_VVSACCR_VSA8_Pos (8U)
9275#define DSI_VVSACCR_VSA8_Msk (0x1U << DSI_VVSACCR_VSA8_Pos) /*!< 0x00000100 */
9276#define DSI_VVSACCR_VSA8 DSI_VVSACCR_VSA8_Msk
9277#define DSI_VVSACCR_VSA9_Pos (9U)
9278#define DSI_VVSACCR_VSA9_Msk (0x1U << DSI_VVSACCR_VSA9_Pos) /*!< 0x00000200 */
9279#define DSI_VVSACCR_VSA9 DSI_VVSACCR_VSA9_Msk
9280
9281/******************* Bit definition for DSI_VVBPCCR register ************/
9282#define DSI_VVBPCCR_VBP_Pos (0U)
9283#define DSI_VVBPCCR_VBP_Msk (0x3FFU << DSI_VVBPCCR_VBP_Pos) /*!< 0x000003FF */
9284#define DSI_VVBPCCR_VBP DSI_VVBPCCR_VBP_Msk /*!< Vertical Back-Porch duration */
9285#define DSI_VVBPCCR_VBP0_Pos (0U)
9286#define DSI_VVBPCCR_VBP0_Msk (0x1U << DSI_VVBPCCR_VBP0_Pos) /*!< 0x00000001 */
9287#define DSI_VVBPCCR_VBP0 DSI_VVBPCCR_VBP0_Msk
9288#define DSI_VVBPCCR_VBP1_Pos (1U)
9289#define DSI_VVBPCCR_VBP1_Msk (0x1U << DSI_VVBPCCR_VBP1_Pos) /*!< 0x00000002 */
9290#define DSI_VVBPCCR_VBP1 DSI_VVBPCCR_VBP1_Msk
9291#define DSI_VVBPCCR_VBP2_Pos (2U)
9292#define DSI_VVBPCCR_VBP2_Msk (0x1U << DSI_VVBPCCR_VBP2_Pos) /*!< 0x00000004 */
9293#define DSI_VVBPCCR_VBP2 DSI_VVBPCCR_VBP2_Msk
9294#define DSI_VVBPCCR_VBP3_Pos (3U)
9295#define DSI_VVBPCCR_VBP3_Msk (0x1U << DSI_VVBPCCR_VBP3_Pos) /*!< 0x00000008 */
9296#define DSI_VVBPCCR_VBP3 DSI_VVBPCCR_VBP3_Msk
9297#define DSI_VVBPCCR_VBP4_Pos (4U)
9298#define DSI_VVBPCCR_VBP4_Msk (0x1U << DSI_VVBPCCR_VBP4_Pos) /*!< 0x00000010 */
9299#define DSI_VVBPCCR_VBP4 DSI_VVBPCCR_VBP4_Msk
9300#define DSI_VVBPCCR_VBP5_Pos (5U)
9301#define DSI_VVBPCCR_VBP5_Msk (0x1U << DSI_VVBPCCR_VBP5_Pos) /*!< 0x00000020 */
9302#define DSI_VVBPCCR_VBP5 DSI_VVBPCCR_VBP5_Msk
9303#define DSI_VVBPCCR_VBP6_Pos (6U)
9304#define DSI_VVBPCCR_VBP6_Msk (0x1U << DSI_VVBPCCR_VBP6_Pos) /*!< 0x00000040 */
9305#define DSI_VVBPCCR_VBP6 DSI_VVBPCCR_VBP6_Msk
9306#define DSI_VVBPCCR_VBP7_Pos (7U)
9307#define DSI_VVBPCCR_VBP7_Msk (0x1U << DSI_VVBPCCR_VBP7_Pos) /*!< 0x00000080 */
9308#define DSI_VVBPCCR_VBP7 DSI_VVBPCCR_VBP7_Msk
9309#define DSI_VVBPCCR_VBP8_Pos (8U)
9310#define DSI_VVBPCCR_VBP8_Msk (0x1U << DSI_VVBPCCR_VBP8_Pos) /*!< 0x00000100 */
9311#define DSI_VVBPCCR_VBP8 DSI_VVBPCCR_VBP8_Msk
9312#define DSI_VVBPCCR_VBP9_Pos (9U)
9313#define DSI_VVBPCCR_VBP9_Msk (0x1U << DSI_VVBPCCR_VBP9_Pos) /*!< 0x00000200 */
9314#define DSI_VVBPCCR_VBP9 DSI_VVBPCCR_VBP9_Msk
9315
9316/******************* Bit definition for DSI_VVFPCCR register ************/
9317#define DSI_VVFPCCR_VFP_Pos (0U)
9318#define DSI_VVFPCCR_VFP_Msk (0x3FFU << DSI_VVFPCCR_VFP_Pos) /*!< 0x000003FF */
9319#define DSI_VVFPCCR_VFP DSI_VVFPCCR_VFP_Msk /*!< Vertical Front-Porch duration */
9320#define DSI_VVFPCCR_VFP0_Pos (0U)
9321#define DSI_VVFPCCR_VFP0_Msk (0x1U << DSI_VVFPCCR_VFP0_Pos) /*!< 0x00000001 */
9322#define DSI_VVFPCCR_VFP0 DSI_VVFPCCR_VFP0_Msk
9323#define DSI_VVFPCCR_VFP1_Pos (1U)
9324#define DSI_VVFPCCR_VFP1_Msk (0x1U << DSI_VVFPCCR_VFP1_Pos) /*!< 0x00000002 */
9325#define DSI_VVFPCCR_VFP1 DSI_VVFPCCR_VFP1_Msk
9326#define DSI_VVFPCCR_VFP2_Pos (2U)
9327#define DSI_VVFPCCR_VFP2_Msk (0x1U << DSI_VVFPCCR_VFP2_Pos) /*!< 0x00000004 */
9328#define DSI_VVFPCCR_VFP2 DSI_VVFPCCR_VFP2_Msk
9329#define DSI_VVFPCCR_VFP3_Pos (3U)
9330#define DSI_VVFPCCR_VFP3_Msk (0x1U << DSI_VVFPCCR_VFP3_Pos) /*!< 0x00000008 */
9331#define DSI_VVFPCCR_VFP3 DSI_VVFPCCR_VFP3_Msk
9332#define DSI_VVFPCCR_VFP4_Pos (4U)
9333#define DSI_VVFPCCR_VFP4_Msk (0x1U << DSI_VVFPCCR_VFP4_Pos) /*!< 0x00000010 */
9334#define DSI_VVFPCCR_VFP4 DSI_VVFPCCR_VFP4_Msk
9335#define DSI_VVFPCCR_VFP5_Pos (5U)
9336#define DSI_VVFPCCR_VFP5_Msk (0x1U << DSI_VVFPCCR_VFP5_Pos) /*!< 0x00000020 */
9337#define DSI_VVFPCCR_VFP5 DSI_VVFPCCR_VFP5_Msk
9338#define DSI_VVFPCCR_VFP6_Pos (6U)
9339#define DSI_VVFPCCR_VFP6_Msk (0x1U << DSI_VVFPCCR_VFP6_Pos) /*!< 0x00000040 */
9340#define DSI_VVFPCCR_VFP6 DSI_VVFPCCR_VFP6_Msk
9341#define DSI_VVFPCCR_VFP7_Pos (7U)
9342#define DSI_VVFPCCR_VFP7_Msk (0x1U << DSI_VVFPCCR_VFP7_Pos) /*!< 0x00000080 */
9343#define DSI_VVFPCCR_VFP7 DSI_VVFPCCR_VFP7_Msk
9344#define DSI_VVFPCCR_VFP8_Pos (8U)
9345#define DSI_VVFPCCR_VFP8_Msk (0x1U << DSI_VVFPCCR_VFP8_Pos) /*!< 0x00000100 */
9346#define DSI_VVFPCCR_VFP8 DSI_VVFPCCR_VFP8_Msk
9347#define DSI_VVFPCCR_VFP9_Pos (9U)
9348#define DSI_VVFPCCR_VFP9_Msk (0x1U << DSI_VVFPCCR_VFP9_Pos) /*!< 0x00000200 */
9349#define DSI_VVFPCCR_VFP9 DSI_VVFPCCR_VFP9_Msk
9350
9351/******************* Bit definition for DSI_VVACCR register *************/
9352#define DSI_VVACCR_VA_Pos (0U)
9353#define DSI_VVACCR_VA_Msk (0x3FFFU << DSI_VVACCR_VA_Pos) /*!< 0x00003FFF */
9354#define DSI_VVACCR_VA DSI_VVACCR_VA_Msk /*!< Vertical Active duration */
9355#define DSI_VVACCR_VA0_Pos (0U)
9356#define DSI_VVACCR_VA0_Msk (0x1U << DSI_VVACCR_VA0_Pos) /*!< 0x00000001 */
9357#define DSI_VVACCR_VA0 DSI_VVACCR_VA0_Msk
9358#define DSI_VVACCR_VA1_Pos (1U)
9359#define DSI_VVACCR_VA1_Msk (0x1U << DSI_VVACCR_VA1_Pos) /*!< 0x00000002 */
9360#define DSI_VVACCR_VA1 DSI_VVACCR_VA1_Msk
9361#define DSI_VVACCR_VA2_Pos (2U)
9362#define DSI_VVACCR_VA2_Msk (0x1U << DSI_VVACCR_VA2_Pos) /*!< 0x00000004 */
9363#define DSI_VVACCR_VA2 DSI_VVACCR_VA2_Msk
9364#define DSI_VVACCR_VA3_Pos (3U)
9365#define DSI_VVACCR_VA3_Msk (0x1U << DSI_VVACCR_VA3_Pos) /*!< 0x00000008 */
9366#define DSI_VVACCR_VA3 DSI_VVACCR_VA3_Msk
9367#define DSI_VVACCR_VA4_Pos (4U)
9368#define DSI_VVACCR_VA4_Msk (0x1U << DSI_VVACCR_VA4_Pos) /*!< 0x00000010 */
9369#define DSI_VVACCR_VA4 DSI_VVACCR_VA4_Msk
9370#define DSI_VVACCR_VA5_Pos (5U)
9371#define DSI_VVACCR_VA5_Msk (0x1U << DSI_VVACCR_VA5_Pos) /*!< 0x00000020 */
9372#define DSI_VVACCR_VA5 DSI_VVACCR_VA5_Msk
9373#define DSI_VVACCR_VA6_Pos (6U)
9374#define DSI_VVACCR_VA6_Msk (0x1U << DSI_VVACCR_VA6_Pos) /*!< 0x00000040 */
9375#define DSI_VVACCR_VA6 DSI_VVACCR_VA6_Msk
9376#define DSI_VVACCR_VA7_Pos (7U)
9377#define DSI_VVACCR_VA7_Msk (0x1U << DSI_VVACCR_VA7_Pos) /*!< 0x00000080 */
9378#define DSI_VVACCR_VA7 DSI_VVACCR_VA7_Msk
9379#define DSI_VVACCR_VA8_Pos (8U)
9380#define DSI_VVACCR_VA8_Msk (0x1U << DSI_VVACCR_VA8_Pos) /*!< 0x00000100 */
9381#define DSI_VVACCR_VA8 DSI_VVACCR_VA8_Msk
9382#define DSI_VVACCR_VA9_Pos (9U)
9383#define DSI_VVACCR_VA9_Msk (0x1U << DSI_VVACCR_VA9_Pos) /*!< 0x00000200 */
9384#define DSI_VVACCR_VA9 DSI_VVACCR_VA9_Msk
9385#define DSI_VVACCR_VA10_Pos (10U)
9386#define DSI_VVACCR_VA10_Msk (0x1U << DSI_VVACCR_VA10_Pos) /*!< 0x00000400 */
9387#define DSI_VVACCR_VA10 DSI_VVACCR_VA10_Msk
9388#define DSI_VVACCR_VA11_Pos (11U)
9389#define DSI_VVACCR_VA11_Msk (0x1U << DSI_VVACCR_VA11_Pos) /*!< 0x00000800 */
9390#define DSI_VVACCR_VA11 DSI_VVACCR_VA11_Msk
9391#define DSI_VVACCR_VA12_Pos (12U)
9392#define DSI_VVACCR_VA12_Msk (0x1U << DSI_VVACCR_VA12_Pos) /*!< 0x00001000 */
9393#define DSI_VVACCR_VA12 DSI_VVACCR_VA12_Msk
9394#define DSI_VVACCR_VA13_Pos (13U)
9395#define DSI_VVACCR_VA13_Msk (0x1U << DSI_VVACCR_VA13_Pos) /*!< 0x00002000 */
9396#define DSI_VVACCR_VA13 DSI_VVACCR_VA13_Msk
9397
9398/******************* Bit definition for DSI_TDCCR register **************/
9399#define DSI_TDCCR_3DM 0x00000003U /*!< 3D Mode */
9400#define DSI_TDCCR_3DM0 0x00000001U
9401#define DSI_TDCCR_3DM1 0x00000002U
9402
9403#define DSI_TDCCR_3DF 0x0000000CU /*!< 3D Format */
9404#define DSI_TDCCR_3DF0 0x00000004U
9405#define DSI_TDCCR_3DF1 0x00000008U
9406
9407#define DSI_TDCCR_SVS_Pos (4U)
9408#define DSI_TDCCR_SVS_Msk (0x1U << DSI_TDCCR_SVS_Pos) /*!< 0x00000010 */
9409#define DSI_TDCCR_SVS DSI_TDCCR_SVS_Msk /*!< Second VSYNC */
9410#define DSI_TDCCR_RF_Pos (5U)
9411#define DSI_TDCCR_RF_Msk (0x1U << DSI_TDCCR_RF_Pos) /*!< 0x00000020 */
9412#define DSI_TDCCR_RF DSI_TDCCR_RF_Msk /*!< Right First */
9413#define DSI_TDCCR_S3DC_Pos (16U)
9414#define DSI_TDCCR_S3DC_Msk (0x1U << DSI_TDCCR_S3DC_Pos) /*!< 0x00010000 */
9415#define DSI_TDCCR_S3DC DSI_TDCCR_S3DC_Msk /*!< Send 3D Control */
9416
9417/******************* Bit definition for DSI_WCFGR register ***************/
9418#define DSI_WCFGR_DSIM_Pos (0U)
9419#define DSI_WCFGR_DSIM_Msk (0x1U << DSI_WCFGR_DSIM_Pos) /*!< 0x00000001 */
9420#define DSI_WCFGR_DSIM DSI_WCFGR_DSIM_Msk /*!< DSI Mode */
9421#define DSI_WCFGR_COLMUX_Pos (1U)
9422#define DSI_WCFGR_COLMUX_Msk (0x7U << DSI_WCFGR_COLMUX_Pos) /*!< 0x0000000E */
9423#define DSI_WCFGR_COLMUX DSI_WCFGR_COLMUX_Msk /*!< Color Multiplexing */
9424#define DSI_WCFGR_COLMUX0_Pos (1U)
9425#define DSI_WCFGR_COLMUX0_Msk (0x1U << DSI_WCFGR_COLMUX0_Pos) /*!< 0x00000002 */
9426#define DSI_WCFGR_COLMUX0 DSI_WCFGR_COLMUX0_Msk
9427#define DSI_WCFGR_COLMUX1_Pos (2U)
9428#define DSI_WCFGR_COLMUX1_Msk (0x1U << DSI_WCFGR_COLMUX1_Pos) /*!< 0x00000004 */
9429#define DSI_WCFGR_COLMUX1 DSI_WCFGR_COLMUX1_Msk
9430#define DSI_WCFGR_COLMUX2_Pos (3U)
9431#define DSI_WCFGR_COLMUX2_Msk (0x1U << DSI_WCFGR_COLMUX2_Pos) /*!< 0x00000008 */
9432#define DSI_WCFGR_COLMUX2 DSI_WCFGR_COLMUX2_Msk
9433
9434#define DSI_WCFGR_TESRC_Pos (4U)
9435#define DSI_WCFGR_TESRC_Msk (0x1U << DSI_WCFGR_TESRC_Pos) /*!< 0x00000010 */
9436#define DSI_WCFGR_TESRC DSI_WCFGR_TESRC_Msk /*!< Tearing Effect Source */
9437#define DSI_WCFGR_TEPOL_Pos (5U)
9438#define DSI_WCFGR_TEPOL_Msk (0x1U << DSI_WCFGR_TEPOL_Pos) /*!< 0x00000020 */
9439#define DSI_WCFGR_TEPOL DSI_WCFGR_TEPOL_Msk /*!< Tearing Effect Polarity */
9440#define DSI_WCFGR_AR_Pos (6U)
9441#define DSI_WCFGR_AR_Msk (0x1U << DSI_WCFGR_AR_Pos) /*!< 0x00000040 */
9442#define DSI_WCFGR_AR DSI_WCFGR_AR_Msk /*!< Automatic Refresh */
9443#define DSI_WCFGR_VSPOL_Pos (7U)
9444#define DSI_WCFGR_VSPOL_Msk (0x1U << DSI_WCFGR_VSPOL_Pos) /*!< 0x00000080 */
9445#define DSI_WCFGR_VSPOL DSI_WCFGR_VSPOL_Msk /*!< VSync Polarity */
9446
9447/******************* Bit definition for DSI_WCR register *****************/
9448#define DSI_WCR_COLM_Pos (0U)
9449#define DSI_WCR_COLM_Msk (0x1U << DSI_WCR_COLM_Pos) /*!< 0x00000001 */
9450#define DSI_WCR_COLM DSI_WCR_COLM_Msk /*!< Color Mode */
9451#define DSI_WCR_SHTDN_Pos (1U)
9452#define DSI_WCR_SHTDN_Msk (0x1U << DSI_WCR_SHTDN_Pos) /*!< 0x00000002 */
9453#define DSI_WCR_SHTDN DSI_WCR_SHTDN_Msk /*!< Shutdown */
9454#define DSI_WCR_LTDCEN_Pos (2U)
9455#define DSI_WCR_LTDCEN_Msk (0x1U << DSI_WCR_LTDCEN_Pos) /*!< 0x00000004 */
9456#define DSI_WCR_LTDCEN DSI_WCR_LTDCEN_Msk /*!< LTDC Enable */
9457#define DSI_WCR_DSIEN_Pos (3U)
9458#define DSI_WCR_DSIEN_Msk (0x1U << DSI_WCR_DSIEN_Pos) /*!< 0x00000008 */
9459#define DSI_WCR_DSIEN DSI_WCR_DSIEN_Msk /*!< DSI Enable */
9460
9461/******************* Bit definition for DSI_WIER register ****************/
9462#define DSI_WIER_TEIE_Pos (0U)
9463#define DSI_WIER_TEIE_Msk (0x1U << DSI_WIER_TEIE_Pos) /*!< 0x00000001 */
9464#define DSI_WIER_TEIE DSI_WIER_TEIE_Msk /*!< Tearing Effect Interrupt Enable */
9465#define DSI_WIER_ERIE_Pos (1U)
9466#define DSI_WIER_ERIE_Msk (0x1U << DSI_WIER_ERIE_Pos) /*!< 0x00000002 */
9467#define DSI_WIER_ERIE DSI_WIER_ERIE_Msk /*!< End of Refresh Interrupt Enable */
9468#define DSI_WIER_PLLLIE_Pos (9U)
9469#define DSI_WIER_PLLLIE_Msk (0x1U << DSI_WIER_PLLLIE_Pos) /*!< 0x00000200 */
9470#define DSI_WIER_PLLLIE DSI_WIER_PLLLIE_Msk /*!< PLL Lock Interrupt Enable */
9471#define DSI_WIER_PLLUIE_Pos (10U)
9472#define DSI_WIER_PLLUIE_Msk (0x1U << DSI_WIER_PLLUIE_Pos) /*!< 0x00000400 */
9473#define DSI_WIER_PLLUIE DSI_WIER_PLLUIE_Msk /*!< PLL Unlock Interrupt Enable */
9474#define DSI_WIER_RRIE_Pos (13U)
9475#define DSI_WIER_RRIE_Msk (0x1U << DSI_WIER_RRIE_Pos) /*!< 0x00002000 */
9476#define DSI_WIER_RRIE DSI_WIER_RRIE_Msk /*!< Regulator Ready Interrupt Enable */
9477
9478/******************* Bit definition for DSI_WISR register ****************/
9479#define DSI_WISR_TEIF_Pos (0U)
9480#define DSI_WISR_TEIF_Msk (0x1U << DSI_WISR_TEIF_Pos) /*!< 0x00000001 */
9481#define DSI_WISR_TEIF DSI_WISR_TEIF_Msk /*!< Tearing Effect Interrupt Flag */
9482#define DSI_WISR_ERIF_Pos (1U)
9483#define DSI_WISR_ERIF_Msk (0x1U << DSI_WISR_ERIF_Pos) /*!< 0x00000002 */
9484#define DSI_WISR_ERIF DSI_WISR_ERIF_Msk /*!< End of Refresh Interrupt Flag */
9485#define DSI_WISR_BUSY_Pos (2U)
9486#define DSI_WISR_BUSY_Msk (0x1U << DSI_WISR_BUSY_Pos) /*!< 0x00000004 */
9487#define DSI_WISR_BUSY DSI_WISR_BUSY_Msk /*!< Busy Flag */
9488#define DSI_WISR_PLLLS_Pos (8U)
9489#define DSI_WISR_PLLLS_Msk (0x1U << DSI_WISR_PLLLS_Pos) /*!< 0x00000100 */
9490#define DSI_WISR_PLLLS DSI_WISR_PLLLS_Msk /*!< PLL Lock Status */
9491#define DSI_WISR_PLLLIF_Pos (9U)
9492#define DSI_WISR_PLLLIF_Msk (0x1U << DSI_WISR_PLLLIF_Pos) /*!< 0x00000200 */
9493#define DSI_WISR_PLLLIF DSI_WISR_PLLLIF_Msk /*!< PLL Lock Interrupt Flag */
9494#define DSI_WISR_PLLUIF_Pos (10U)
9495#define DSI_WISR_PLLUIF_Msk (0x1U << DSI_WISR_PLLUIF_Pos) /*!< 0x00000400 */
9496#define DSI_WISR_PLLUIF DSI_WISR_PLLUIF_Msk /*!< PLL Unlock Interrupt Flag */
9497#define DSI_WISR_RRS_Pos (12U)
9498#define DSI_WISR_RRS_Msk (0x1U << DSI_WISR_RRS_Pos) /*!< 0x00001000 */
9499#define DSI_WISR_RRS DSI_WISR_RRS_Msk /*!< Regulator Ready Flag */
9500#define DSI_WISR_RRIF_Pos (13U)
9501#define DSI_WISR_RRIF_Msk (0x1U << DSI_WISR_RRIF_Pos) /*!< 0x00002000 */
9502#define DSI_WISR_RRIF DSI_WISR_RRIF_Msk /*!< Regulator Ready Interrupt Flag */
9503
9504/******************* Bit definition for DSI_WIFCR register ***************/
9505#define DSI_WIFCR_CTEIF_Pos (0U)
9506#define DSI_WIFCR_CTEIF_Msk (0x1U << DSI_WIFCR_CTEIF_Pos) /*!< 0x00000001 */
9507#define DSI_WIFCR_CTEIF DSI_WIFCR_CTEIF_Msk /*!< Clear Tearing Effect Interrupt Flag */
9508#define DSI_WIFCR_CERIF_Pos (1U)
9509#define DSI_WIFCR_CERIF_Msk (0x1U << DSI_WIFCR_CERIF_Pos) /*!< 0x00000002 */
9510#define DSI_WIFCR_CERIF DSI_WIFCR_CERIF_Msk /*!< Clear End of Refresh Interrupt Flag */
9511#define DSI_WIFCR_CPLLLIF_Pos (9U)
9512#define DSI_WIFCR_CPLLLIF_Msk (0x1U << DSI_WIFCR_CPLLLIF_Pos) /*!< 0x00000200 */
9513#define DSI_WIFCR_CPLLLIF DSI_WIFCR_CPLLLIF_Msk /*!< Clear PLL Lock Interrupt Flag */
9514#define DSI_WIFCR_CPLLUIF_Pos (10U)
9515#define DSI_WIFCR_CPLLUIF_Msk (0x1U << DSI_WIFCR_CPLLUIF_Pos) /*!< 0x00000400 */
9516#define DSI_WIFCR_CPLLUIF DSI_WIFCR_CPLLUIF_Msk /*!< Clear PLL Unlock Interrupt Flag */
9517#define DSI_WIFCR_CRRIF_Pos (13U)
9518#define DSI_WIFCR_CRRIF_Msk (0x1U << DSI_WIFCR_CRRIF_Pos) /*!< 0x00002000 */
9519#define DSI_WIFCR_CRRIF DSI_WIFCR_CRRIF_Msk /*!< Clear Regulator Ready Interrupt Flag */
9520
9521/******************* Bit definition for DSI_WPCR0 register ***************/
9522#define DSI_WPCR0_UIX4_Pos (0U)
9523#define DSI_WPCR0_UIX4_Msk (0x3FU << DSI_WPCR0_UIX4_Pos) /*!< 0x0000003F */
9524#define DSI_WPCR0_UIX4 DSI_WPCR0_UIX4_Msk /*!< Unit Interval multiplied by 4 */
9525#define DSI_WPCR0_UIX4_0 (0x01U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000001 */
9526#define DSI_WPCR0_UIX4_1 (0x02U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000002 */
9527#define DSI_WPCR0_UIX4_2 (0x04U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000004 */
9528#define DSI_WPCR0_UIX4_3 (0x08U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000008 */
9529#define DSI_WPCR0_UIX4_4 (0x10U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000010 */
9530#define DSI_WPCR0_UIX4_5 (0x20U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000020 */
9531
9532#define DSI_WPCR0_SWCL_Pos (6U)
9533#define DSI_WPCR0_SWCL_Msk (0x1U << DSI_WPCR0_SWCL_Pos) /*!< 0x00000040 */
9534#define DSI_WPCR0_SWCL DSI_WPCR0_SWCL_Msk /*!< Swap pins on clock lane */
9535#define DSI_WPCR0_SWDL0_Pos (7U)
9536#define DSI_WPCR0_SWDL0_Msk (0x1U << DSI_WPCR0_SWDL0_Pos) /*!< 0x00000080 */
9537#define DSI_WPCR0_SWDL0 DSI_WPCR0_SWDL0_Msk /*!< Swap pins on data lane 1 */
9538#define DSI_WPCR0_SWDL1_Pos (8U)
9539#define DSI_WPCR0_SWDL1_Msk (0x1U << DSI_WPCR0_SWDL1_Pos) /*!< 0x00000100 */
9540#define DSI_WPCR0_SWDL1 DSI_WPCR0_SWDL1_Msk /*!< Swap pins on data lane 2 */
9541#define DSI_WPCR0_HSICL_Pos (9U)
9542#define DSI_WPCR0_HSICL_Msk (0x1U << DSI_WPCR0_HSICL_Pos) /*!< 0x00000200 */
9543#define DSI_WPCR0_HSICL DSI_WPCR0_HSICL_Msk /*!< Invert the high-speed data signal on clock lane */
9544#define DSI_WPCR0_HSIDL0_Pos (10U)
9545#define DSI_WPCR0_HSIDL0_Msk (0x1U << DSI_WPCR0_HSIDL0_Pos) /*!< 0x00000400 */
9546#define DSI_WPCR0_HSIDL0 DSI_WPCR0_HSIDL0_Msk /*!< Invert the high-speed data signal on lane 1 */
9547#define DSI_WPCR0_HSIDL1_Pos (11U)
9548#define DSI_WPCR0_HSIDL1_Msk (0x1U << DSI_WPCR0_HSIDL1_Pos) /*!< 0x00000800 */
9549#define DSI_WPCR0_HSIDL1 DSI_WPCR0_HSIDL1_Msk /*!< Invert the high-speed data signal on lane 2 */
9550#define DSI_WPCR0_FTXSMCL_Pos (12U)
9551#define DSI_WPCR0_FTXSMCL_Msk (0x1U << DSI_WPCR0_FTXSMCL_Pos) /*!< 0x00001000 */
9552#define DSI_WPCR0_FTXSMCL DSI_WPCR0_FTXSMCL_Msk /*!< Force clock lane in TX stop mode */
9553#define DSI_WPCR0_FTXSMDL_Pos (13U)
9554#define DSI_WPCR0_FTXSMDL_Msk (0x1U << DSI_WPCR0_FTXSMDL_Pos) /*!< 0x00002000 */
9555#define DSI_WPCR0_FTXSMDL DSI_WPCR0_FTXSMDL_Msk /*!< Force data lanes in TX stop mode */
9556#define DSI_WPCR0_CDOFFDL_Pos (14U)
9557#define DSI_WPCR0_CDOFFDL_Msk (0x1U << DSI_WPCR0_CDOFFDL_Pos) /*!< 0x00004000 */
9558#define DSI_WPCR0_CDOFFDL DSI_WPCR0_CDOFFDL_Msk /*!< Contention detection OFF */
9559#define DSI_WPCR0_TDDL_Pos (16U)
9560#define DSI_WPCR0_TDDL_Msk (0x1U << DSI_WPCR0_TDDL_Pos) /*!< 0x00010000 */
9561#define DSI_WPCR0_TDDL DSI_WPCR0_TDDL_Msk /*!< Turn Disable Data Lanes */
9562#define DSI_WPCR0_PDEN_Pos (18U)
9563#define DSI_WPCR0_PDEN_Msk (0x1U << DSI_WPCR0_PDEN_Pos) /*!< 0x00040000 */
9564#define DSI_WPCR0_PDEN DSI_WPCR0_PDEN_Msk /*!< Pull-Down Enable */
9565#define DSI_WPCR0_TCLKPREPEN_Pos (19U)
9566#define DSI_WPCR0_TCLKPREPEN_Msk (0x1U << DSI_WPCR0_TCLKPREPEN_Pos) /*!< 0x00080000 */
9567#define DSI_WPCR0_TCLKPREPEN DSI_WPCR0_TCLKPREPEN_Msk /*!< Timer for t-CLKPREP Enable */
9568#define DSI_WPCR0_TCLKZEROEN_Pos (20U)
9569#define DSI_WPCR0_TCLKZEROEN_Msk (0x1U << DSI_WPCR0_TCLKZEROEN_Pos) /*!< 0x00100000 */
9570#define DSI_WPCR0_TCLKZEROEN DSI_WPCR0_TCLKZEROEN_Msk /*!< Timer for t-CLKZERO Enable */
9571#define DSI_WPCR0_THSPREPEN_Pos (21U)
9572#define DSI_WPCR0_THSPREPEN_Msk (0x1U << DSI_WPCR0_THSPREPEN_Pos) /*!< 0x00200000 */
9573#define DSI_WPCR0_THSPREPEN DSI_WPCR0_THSPREPEN_Msk /*!< Timer for t-HSPREP Enable */
9574#define DSI_WPCR0_THSTRAILEN_Pos (22U)
9575#define DSI_WPCR0_THSTRAILEN_Msk (0x1U << DSI_WPCR0_THSTRAILEN_Pos) /*!< 0x00400000 */
9576#define DSI_WPCR0_THSTRAILEN DSI_WPCR0_THSTRAILEN_Msk /*!< Timer for t-HSTRAIL Enable */
9577#define DSI_WPCR0_THSZEROEN_Pos (23U)
9578#define DSI_WPCR0_THSZEROEN_Msk (0x1U << DSI_WPCR0_THSZEROEN_Pos) /*!< 0x00800000 */
9579#define DSI_WPCR0_THSZEROEN DSI_WPCR0_THSZEROEN_Msk /*!< Timer for t-HSZERO Enable */
9580#define DSI_WPCR0_TLPXDEN_Pos (24U)
9581#define DSI_WPCR0_TLPXDEN_Msk (0x1U << DSI_WPCR0_TLPXDEN_Pos) /*!< 0x01000000 */
9582#define DSI_WPCR0_TLPXDEN DSI_WPCR0_TLPXDEN_Msk /*!< Timer for t-LPXD Enable */
9583#define DSI_WPCR0_THSEXITEN_Pos (25U)
9584#define DSI_WPCR0_THSEXITEN_Msk (0x1U << DSI_WPCR0_THSEXITEN_Pos) /*!< 0x02000000 */
9585#define DSI_WPCR0_THSEXITEN DSI_WPCR0_THSEXITEN_Msk /*!< Timer for t-HSEXIT Enable */
9586#define DSI_WPCR0_TLPXCEN_Pos (26U)
9587#define DSI_WPCR0_TLPXCEN_Msk (0x1U << DSI_WPCR0_TLPXCEN_Pos) /*!< 0x04000000 */
9588#define DSI_WPCR0_TLPXCEN DSI_WPCR0_TLPXCEN_Msk /*!< Timer for t-LPXC Enable */
9589#define DSI_WPCR0_TCLKPOSTEN_Pos (27U)
9590#define DSI_WPCR0_TCLKPOSTEN_Msk (0x1U << DSI_WPCR0_TCLKPOSTEN_Pos) /*!< 0x08000000 */
9591#define DSI_WPCR0_TCLKPOSTEN DSI_WPCR0_TCLKPOSTEN_Msk /*!< Timer for t-CLKPOST Enable */
9592
9593/******************* Bit definition for DSI_WPCR1 register ***************/
9594#define DSI_WPCR1_HSTXDCL_Pos (0U)
9595#define DSI_WPCR1_HSTXDCL_Msk (0x3U << DSI_WPCR1_HSTXDCL_Pos) /*!< 0x00000003 */
9596#define DSI_WPCR1_HSTXDCL DSI_WPCR1_HSTXDCL_Msk /*!< High-Speed Transmission Delay on Clock Lane */
9597#define DSI_WPCR1_HSTXDCL0_Pos (0U)
9598#define DSI_WPCR1_HSTXDCL0_Msk (0x1U << DSI_WPCR1_HSTXDCL0_Pos) /*!< 0x00000001 */
9599#define DSI_WPCR1_HSTXDCL0 DSI_WPCR1_HSTXDCL0_Msk
9600#define DSI_WPCR1_HSTXDCL1_Pos (1U)
9601#define DSI_WPCR1_HSTXDCL1_Msk (0x1U << DSI_WPCR1_HSTXDCL1_Pos) /*!< 0x00000002 */
9602#define DSI_WPCR1_HSTXDCL1 DSI_WPCR1_HSTXDCL1_Msk
9603
9604#define DSI_WPCR1_HSTXDDL_Pos (2U)
9605#define DSI_WPCR1_HSTXDDL_Msk (0x3U << DSI_WPCR1_HSTXDDL_Pos) /*!< 0x0000000C */
9606#define DSI_WPCR1_HSTXDDL DSI_WPCR1_HSTXDDL_Msk /*!< High-Speed Transmission Delay on Data Lane */
9607#define DSI_WPCR1_HSTXDDL0_Pos (2U)
9608#define DSI_WPCR1_HSTXDDL0_Msk (0x1U << DSI_WPCR1_HSTXDDL0_Pos) /*!< 0x00000004 */
9609#define DSI_WPCR1_HSTXDDL0 DSI_WPCR1_HSTXDDL0_Msk
9610#define DSI_WPCR1_HSTXDDL1_Pos (3U)
9611#define DSI_WPCR1_HSTXDDL1_Msk (0x1U << DSI_WPCR1_HSTXDDL1_Pos) /*!< 0x00000008 */
9612#define DSI_WPCR1_HSTXDDL1 DSI_WPCR1_HSTXDDL1_Msk
9613
9614#define DSI_WPCR1_LPSRCCL_Pos (6U)
9615#define DSI_WPCR1_LPSRCCL_Msk (0x3U << DSI_WPCR1_LPSRCCL_Pos) /*!< 0x000000C0 */
9616#define DSI_WPCR1_LPSRCCL DSI_WPCR1_LPSRCCL_Msk /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */
9617#define DSI_WPCR1_LPSRCCL0_Pos (6U)
9618#define DSI_WPCR1_LPSRCCL0_Msk (0x1U << DSI_WPCR1_LPSRCCL0_Pos) /*!< 0x00000040 */
9619#define DSI_WPCR1_LPSRCCL0 DSI_WPCR1_LPSRCCL0_Msk
9620#define DSI_WPCR1_LPSRCCL1_Pos (7U)
9621#define DSI_WPCR1_LPSRCCL1_Msk (0x1U << DSI_WPCR1_LPSRCCL1_Pos) /*!< 0x00000080 */
9622#define DSI_WPCR1_LPSRCCL1 DSI_WPCR1_LPSRCCL1_Msk
9623
9624#define DSI_WPCR1_LPSRCDL_Pos (8U)
9625#define DSI_WPCR1_LPSRCDL_Msk (0x3U << DSI_WPCR1_LPSRCDL_Pos) /*!< 0x00000300 */
9626#define DSI_WPCR1_LPSRCDL DSI_WPCR1_LPSRCDL_Msk /*!< Low-Power transmission Slew Rate Compensation on Data Lane */
9627#define DSI_WPCR1_LPSRCDL0_Pos (8U)
9628#define DSI_WPCR1_LPSRCDL0_Msk (0x1U << DSI_WPCR1_LPSRCDL0_Pos) /*!< 0x00000100 */
9629#define DSI_WPCR1_LPSRCDL0 DSI_WPCR1_LPSRCDL0_Msk
9630#define DSI_WPCR1_LPSRCDL1_Pos (9U)
9631#define DSI_WPCR1_LPSRCDL1_Msk (0x1U << DSI_WPCR1_LPSRCDL1_Pos) /*!< 0x00000200 */
9632#define DSI_WPCR1_LPSRCDL1 DSI_WPCR1_LPSRCDL1_Msk
9633
9634#define DSI_WPCR1_SDDC_Pos (12U)
9635#define DSI_WPCR1_SDDC_Msk (0x1U << DSI_WPCR1_SDDC_Pos) /*!< 0x00001000 */
9636#define DSI_WPCR1_SDDC DSI_WPCR1_SDDC_Msk /*!< SDD Control */
9637
9638#define DSI_WPCR1_LPRXVCDL_Pos (14U)
9639#define DSI_WPCR1_LPRXVCDL_Msk (0x3U << DSI_WPCR1_LPRXVCDL_Pos) /*!< 0x0000C000 */
9640#define DSI_WPCR1_LPRXVCDL DSI_WPCR1_LPRXVCDL_Msk /*!< Low-Power Reception V-IL Compensation on Data Lanes */
9641#define DSI_WPCR1_LPRXVCDL0_Pos (14U)
9642#define DSI_WPCR1_LPRXVCDL0_Msk (0x1U << DSI_WPCR1_LPRXVCDL0_Pos) /*!< 0x00004000 */
9643#define DSI_WPCR1_LPRXVCDL0 DSI_WPCR1_LPRXVCDL0_Msk
9644#define DSI_WPCR1_LPRXVCDL1_Pos (15U)
9645#define DSI_WPCR1_LPRXVCDL1_Msk (0x1U << DSI_WPCR1_LPRXVCDL1_Pos) /*!< 0x00008000 */
9646#define DSI_WPCR1_LPRXVCDL1 DSI_WPCR1_LPRXVCDL1_Msk
9647
9648#define DSI_WPCR1_HSTXSRCCL_Pos (16U)
9649#define DSI_WPCR1_HSTXSRCCL_Msk (0x3U << DSI_WPCR1_HSTXSRCCL_Pos) /*!< 0x00030000 */
9650#define DSI_WPCR1_HSTXSRCCL DSI_WPCR1_HSTXSRCCL_Msk /*!< High-Speed Transmission Delay on Clock Lane */
9651#define DSI_WPCR1_HSTXSRCCL0_Pos (16U)
9652#define DSI_WPCR1_HSTXSRCCL0_Msk (0x1U << DSI_WPCR1_HSTXSRCCL0_Pos) /*!< 0x00010000 */
9653#define DSI_WPCR1_HSTXSRCCL0 DSI_WPCR1_HSTXSRCCL0_Msk
9654#define DSI_WPCR1_HSTXSRCCL1_Pos (17U)
9655#define DSI_WPCR1_HSTXSRCCL1_Msk (0x1U << DSI_WPCR1_HSTXSRCCL1_Pos) /*!< 0x00020000 */
9656#define DSI_WPCR1_HSTXSRCCL1 DSI_WPCR1_HSTXSRCCL1_Msk
9657
9658#define DSI_WPCR1_HSTXSRCDL_Pos (18U)
9659#define DSI_WPCR1_HSTXSRCDL_Msk (0x3U << DSI_WPCR1_HSTXSRCDL_Pos) /*!< 0x000C0000 */
9660#define DSI_WPCR1_HSTXSRCDL DSI_WPCR1_HSTXSRCDL_Msk /*!< High-Speed Transmission Delay on Data Lane */
9661#define DSI_WPCR1_HSTXSRCDL0_Pos (18U)
9662#define DSI_WPCR1_HSTXSRCDL0_Msk (0x1U << DSI_WPCR1_HSTXSRCDL0_Pos) /*!< 0x00040000 */
9663#define DSI_WPCR1_HSTXSRCDL0 DSI_WPCR1_HSTXSRCDL0_Msk
9664#define DSI_WPCR1_HSTXSRCDL1_Pos (19U)
9665#define DSI_WPCR1_HSTXSRCDL1_Msk (0x1U << DSI_WPCR1_HSTXSRCDL1_Pos) /*!< 0x00080000 */
9666#define DSI_WPCR1_HSTXSRCDL1 DSI_WPCR1_HSTXSRCDL1_Msk
9667
9668#define DSI_WPCR1_FLPRXLPM_Pos (22U)
9669#define DSI_WPCR1_FLPRXLPM_Msk (0x1U << DSI_WPCR1_FLPRXLPM_Pos) /*!< 0x00400000 */
9670#define DSI_WPCR1_FLPRXLPM DSI_WPCR1_FLPRXLPM_Msk /*!< Forces LP Receiver in Low-Power Mode */
9671
9672#define DSI_WPCR1_LPRXFT_Pos (25U)
9673#define DSI_WPCR1_LPRXFT_Msk (0x3U << DSI_WPCR1_LPRXFT_Pos) /*!< 0x06000000 */
9674#define DSI_WPCR1_LPRXFT DSI_WPCR1_LPRXFT_Msk /*!< Low-Power RX low-pass Filtering Tuning */
9675#define DSI_WPCR1_LPRXFT0_Pos (25U)
9676#define DSI_WPCR1_LPRXFT0_Msk (0x1U << DSI_WPCR1_LPRXFT0_Pos) /*!< 0x02000000 */
9677#define DSI_WPCR1_LPRXFT0 DSI_WPCR1_LPRXFT0_Msk
9678#define DSI_WPCR1_LPRXFT1_Pos (26U)
9679#define DSI_WPCR1_LPRXFT1_Msk (0x1U << DSI_WPCR1_LPRXFT1_Pos) /*!< 0x04000000 */
9680#define DSI_WPCR1_LPRXFT1 DSI_WPCR1_LPRXFT1_Msk
9681
9682/******************* Bit definition for DSI_WPCR2 register ***************/
9683#define DSI_WPCR2_TCLKPREP_Pos (0U)
9684#define DSI_WPCR2_TCLKPREP_Msk (0xFFU << DSI_WPCR2_TCLKPREP_Pos) /*!< 0x000000FF */
9685#define DSI_WPCR2_TCLKPREP DSI_WPCR2_TCLKPREP_Msk /*!< t-CLKPREP */
9686#define DSI_WPCR2_TCLKPREP0_Pos (0U)
9687#define DSI_WPCR2_TCLKPREP0_Msk (0x1U << DSI_WPCR2_TCLKPREP0_Pos) /*!< 0x00000001 */
9688#define DSI_WPCR2_TCLKPREP0 DSI_WPCR2_TCLKPREP0_Msk
9689#define DSI_WPCR2_TCLKPREP1_Pos (1U)
9690#define DSI_WPCR2_TCLKPREP1_Msk (0x1U << DSI_WPCR2_TCLKPREP1_Pos) /*!< 0x00000002 */
9691#define DSI_WPCR2_TCLKPREP1 DSI_WPCR2_TCLKPREP1_Msk
9692#define DSI_WPCR2_TCLKPREP2_Pos (2U)
9693#define DSI_WPCR2_TCLKPREP2_Msk (0x1U << DSI_WPCR2_TCLKPREP2_Pos) /*!< 0x00000004 */
9694#define DSI_WPCR2_TCLKPREP2 DSI_WPCR2_TCLKPREP2_Msk
9695#define DSI_WPCR2_TCLKPREP3_Pos (3U)
9696#define DSI_WPCR2_TCLKPREP3_Msk (0x1U << DSI_WPCR2_TCLKPREP3_Pos) /*!< 0x00000008 */
9697#define DSI_WPCR2_TCLKPREP3 DSI_WPCR2_TCLKPREP3_Msk
9698#define DSI_WPCR2_TCLKPREP4_Pos (4U)
9699#define DSI_WPCR2_TCLKPREP4_Msk (0x1U << DSI_WPCR2_TCLKPREP4_Pos) /*!< 0x00000010 */
9700#define DSI_WPCR2_TCLKPREP4 DSI_WPCR2_TCLKPREP4_Msk
9701#define DSI_WPCR2_TCLKPREP5_Pos (5U)
9702#define DSI_WPCR2_TCLKPREP5_Msk (0x1U << DSI_WPCR2_TCLKPREP5_Pos) /*!< 0x00000020 */
9703#define DSI_WPCR2_TCLKPREP5 DSI_WPCR2_TCLKPREP5_Msk
9704#define DSI_WPCR2_TCLKPREP6_Pos (6U)
9705#define DSI_WPCR2_TCLKPREP6_Msk (0x1U << DSI_WPCR2_TCLKPREP6_Pos) /*!< 0x00000040 */
9706#define DSI_WPCR2_TCLKPREP6 DSI_WPCR2_TCLKPREP6_Msk
9707#define DSI_WPCR2_TCLKPREP7_Pos (7U)
9708#define DSI_WPCR2_TCLKPREP7_Msk (0x1U << DSI_WPCR2_TCLKPREP7_Pos) /*!< 0x00000080 */
9709#define DSI_WPCR2_TCLKPREP7 DSI_WPCR2_TCLKPREP7_Msk
9710
9711#define DSI_WPCR2_TCLKZERO_Pos (8U)
9712#define DSI_WPCR2_TCLKZERO_Msk (0xFFU << DSI_WPCR2_TCLKZERO_Pos) /*!< 0x0000FF00 */
9713#define DSI_WPCR2_TCLKZERO DSI_WPCR2_TCLKZERO_Msk /*!< t-CLKZERO */
9714#define DSI_WPCR2_TCLKZERO0_Pos (8U)
9715#define DSI_WPCR2_TCLKZERO0_Msk (0x1U << DSI_WPCR2_TCLKZERO0_Pos) /*!< 0x00000100 */
9716#define DSI_WPCR2_TCLKZERO0 DSI_WPCR2_TCLKZERO0_Msk
9717#define DSI_WPCR2_TCLKZERO1_Pos (9U)
9718#define DSI_WPCR2_TCLKZERO1_Msk (0x1U << DSI_WPCR2_TCLKZERO1_Pos) /*!< 0x00000200 */
9719#define DSI_WPCR2_TCLKZERO1 DSI_WPCR2_TCLKZERO1_Msk
9720#define DSI_WPCR2_TCLKZERO2_Pos (10U)
9721#define DSI_WPCR2_TCLKZERO2_Msk (0x1U << DSI_WPCR2_TCLKZERO2_Pos) /*!< 0x00000400 */
9722#define DSI_WPCR2_TCLKZERO2 DSI_WPCR2_TCLKZERO2_Msk
9723#define DSI_WPCR2_TCLKZERO3_Pos (11U)
9724#define DSI_WPCR2_TCLKZERO3_Msk (0x1U << DSI_WPCR2_TCLKZERO3_Pos) /*!< 0x00000800 */
9725#define DSI_WPCR2_TCLKZERO3 DSI_WPCR2_TCLKZERO3_Msk
9726#define DSI_WPCR2_TCLKZERO4_Pos (12U)
9727#define DSI_WPCR2_TCLKZERO4_Msk (0x1U << DSI_WPCR2_TCLKZERO4_Pos) /*!< 0x00001000 */
9728#define DSI_WPCR2_TCLKZERO4 DSI_WPCR2_TCLKZERO4_Msk
9729#define DSI_WPCR2_TCLKZERO5_Pos (13U)
9730#define DSI_WPCR2_TCLKZERO5_Msk (0x1U << DSI_WPCR2_TCLKZERO5_Pos) /*!< 0x00002000 */
9731#define DSI_WPCR2_TCLKZERO5 DSI_WPCR2_TCLKZERO5_Msk
9732#define DSI_WPCR2_TCLKZERO6_Pos (14U)
9733#define DSI_WPCR2_TCLKZERO6_Msk (0x1U << DSI_WPCR2_TCLKZERO6_Pos) /*!< 0x00004000 */
9734#define DSI_WPCR2_TCLKZERO6 DSI_WPCR2_TCLKZERO6_Msk
9735#define DSI_WPCR2_TCLKZERO7_Pos (15U)
9736#define DSI_WPCR2_TCLKZERO7_Msk (0x1U << DSI_WPCR2_TCLKZERO7_Pos) /*!< 0x00008000 */
9737#define DSI_WPCR2_TCLKZERO7 DSI_WPCR2_TCLKZERO7_Msk
9738
9739#define DSI_WPCR2_THSPREP_Pos (16U)
9740#define DSI_WPCR2_THSPREP_Msk (0xFFU << DSI_WPCR2_THSPREP_Pos) /*!< 0x00FF0000 */
9741#define DSI_WPCR2_THSPREP DSI_WPCR2_THSPREP_Msk /*!< t-HSPREP */
9742#define DSI_WPCR2_THSPREP0_Pos (16U)
9743#define DSI_WPCR2_THSPREP0_Msk (0x1U << DSI_WPCR2_THSPREP0_Pos) /*!< 0x00010000 */
9744#define DSI_WPCR2_THSPREP0 DSI_WPCR2_THSPREP0_Msk
9745#define DSI_WPCR2_THSPREP1_Pos (17U)
9746#define DSI_WPCR2_THSPREP1_Msk (0x1U << DSI_WPCR2_THSPREP1_Pos) /*!< 0x00020000 */
9747#define DSI_WPCR2_THSPREP1 DSI_WPCR2_THSPREP1_Msk
9748#define DSI_WPCR2_THSPREP2_Pos (18U)
9749#define DSI_WPCR2_THSPREP2_Msk (0x1U << DSI_WPCR2_THSPREP2_Pos) /*!< 0x00040000 */
9750#define DSI_WPCR2_THSPREP2 DSI_WPCR2_THSPREP2_Msk
9751#define DSI_WPCR2_THSPREP3_Pos (19U)
9752#define DSI_WPCR2_THSPREP3_Msk (0x1U << DSI_WPCR2_THSPREP3_Pos) /*!< 0x00080000 */
9753#define DSI_WPCR2_THSPREP3 DSI_WPCR2_THSPREP3_Msk
9754#define DSI_WPCR2_THSPREP4_Pos (20U)
9755#define DSI_WPCR2_THSPREP4_Msk (0x1U << DSI_WPCR2_THSPREP4_Pos) /*!< 0x00100000 */
9756#define DSI_WPCR2_THSPREP4 DSI_WPCR2_THSPREP4_Msk
9757#define DSI_WPCR2_THSPREP5_Pos (21U)
9758#define DSI_WPCR2_THSPREP5_Msk (0x1U << DSI_WPCR2_THSPREP5_Pos) /*!< 0x00200000 */
9759#define DSI_WPCR2_THSPREP5 DSI_WPCR2_THSPREP5_Msk
9760#define DSI_WPCR2_THSPREP6_Pos (22U)
9761#define DSI_WPCR2_THSPREP6_Msk (0x1U << DSI_WPCR2_THSPREP6_Pos) /*!< 0x00400000 */
9762#define DSI_WPCR2_THSPREP6 DSI_WPCR2_THSPREP6_Msk
9763#define DSI_WPCR2_THSPREP7_Pos (23U)
9764#define DSI_WPCR2_THSPREP7_Msk (0x1U << DSI_WPCR2_THSPREP7_Pos) /*!< 0x00800000 */
9765#define DSI_WPCR2_THSPREP7 DSI_WPCR2_THSPREP7_Msk
9766
9767#define DSI_WPCR2_THSTRAIL_Pos (24U)
9768#define DSI_WPCR2_THSTRAIL_Msk (0xFFU << DSI_WPCR2_THSTRAIL_Pos) /*!< 0xFF000000 */
9769#define DSI_WPCR2_THSTRAIL DSI_WPCR2_THSTRAIL_Msk /*!< t-HSTRAIL */
9770#define DSI_WPCR2_THSTRAIL0_Pos (24U)
9771#define DSI_WPCR2_THSTRAIL0_Msk (0x1U << DSI_WPCR2_THSTRAIL0_Pos) /*!< 0x01000000 */
9772#define DSI_WPCR2_THSTRAIL0 DSI_WPCR2_THSTRAIL0_Msk
9773#define DSI_WPCR2_THSTRAIL1_Pos (25U)
9774#define DSI_WPCR2_THSTRAIL1_Msk (0x1U << DSI_WPCR2_THSTRAIL1_Pos) /*!< 0x02000000 */
9775#define DSI_WPCR2_THSTRAIL1 DSI_WPCR2_THSTRAIL1_Msk
9776#define DSI_WPCR2_THSTRAIL2_Pos (26U)
9777#define DSI_WPCR2_THSTRAIL2_Msk (0x1U << DSI_WPCR2_THSTRAIL2_Pos) /*!< 0x04000000 */
9778#define DSI_WPCR2_THSTRAIL2 DSI_WPCR2_THSTRAIL2_Msk
9779#define DSI_WPCR2_THSTRAIL3_Pos (27U)
9780#define DSI_WPCR2_THSTRAIL3_Msk (0x1U << DSI_WPCR2_THSTRAIL3_Pos) /*!< 0x08000000 */
9781#define DSI_WPCR2_THSTRAIL3 DSI_WPCR2_THSTRAIL3_Msk
9782#define DSI_WPCR2_THSTRAIL4_Pos (28U)
9783#define DSI_WPCR2_THSTRAIL4_Msk (0x1U << DSI_WPCR2_THSTRAIL4_Pos) /*!< 0x10000000 */
9784#define DSI_WPCR2_THSTRAIL4 DSI_WPCR2_THSTRAIL4_Msk
9785#define DSI_WPCR2_THSTRAIL5_Pos (29U)
9786#define DSI_WPCR2_THSTRAIL5_Msk (0x1U << DSI_WPCR2_THSTRAIL5_Pos) /*!< 0x20000000 */
9787#define DSI_WPCR2_THSTRAIL5 DSI_WPCR2_THSTRAIL5_Msk
9788#define DSI_WPCR2_THSTRAIL6_Pos (30U)
9789#define DSI_WPCR2_THSTRAIL6_Msk (0x1U << DSI_WPCR2_THSTRAIL6_Pos) /*!< 0x40000000 */
9790#define DSI_WPCR2_THSTRAIL6 DSI_WPCR2_THSTRAIL6_Msk
9791#define DSI_WPCR2_THSTRAIL7_Pos (31U)
9792#define DSI_WPCR2_THSTRAIL7_Msk (0x1U << DSI_WPCR2_THSTRAIL7_Pos) /*!< 0x80000000 */
9793#define DSI_WPCR2_THSTRAIL7 DSI_WPCR2_THSTRAIL7_Msk
9794
9795/******************* Bit definition for DSI_WPCR3 register ***************/
9796#define DSI_WPCR3_THSZERO_Pos (0U)
9797#define DSI_WPCR3_THSZERO_Msk (0xFFU << DSI_WPCR3_THSZERO_Pos) /*!< 0x000000FF */
9798#define DSI_WPCR3_THSZERO DSI_WPCR3_THSZERO_Msk /*!< t-HSZERO */
9799#define DSI_WPCR3_THSZERO0_Pos (0U)
9800#define DSI_WPCR3_THSZERO0_Msk (0x1U << DSI_WPCR3_THSZERO0_Pos) /*!< 0x00000001 */
9801#define DSI_WPCR3_THSZERO0 DSI_WPCR3_THSZERO0_Msk
9802#define DSI_WPCR3_THSZERO1_Pos (1U)
9803#define DSI_WPCR3_THSZERO1_Msk (0x1U << DSI_WPCR3_THSZERO1_Pos) /*!< 0x00000002 */
9804#define DSI_WPCR3_THSZERO1 DSI_WPCR3_THSZERO1_Msk
9805#define DSI_WPCR3_THSZERO2_Pos (2U)
9806#define DSI_WPCR3_THSZERO2_Msk (0x1U << DSI_WPCR3_THSZERO2_Pos) /*!< 0x00000004 */
9807#define DSI_WPCR3_THSZERO2 DSI_WPCR3_THSZERO2_Msk
9808#define DSI_WPCR3_THSZERO3_Pos (3U)
9809#define DSI_WPCR3_THSZERO3_Msk (0x1U << DSI_WPCR3_THSZERO3_Pos) /*!< 0x00000008 */
9810#define DSI_WPCR3_THSZERO3 DSI_WPCR3_THSZERO3_Msk
9811#define DSI_WPCR3_THSZERO4_Pos (4U)
9812#define DSI_WPCR3_THSZERO4_Msk (0x1U << DSI_WPCR3_THSZERO4_Pos) /*!< 0x00000010 */
9813#define DSI_WPCR3_THSZERO4 DSI_WPCR3_THSZERO4_Msk
9814#define DSI_WPCR3_THSZERO5_Pos (5U)
9815#define DSI_WPCR3_THSZERO5_Msk (0x1U << DSI_WPCR3_THSZERO5_Pos) /*!< 0x00000020 */
9816#define DSI_WPCR3_THSZERO5 DSI_WPCR3_THSZERO5_Msk
9817#define DSI_WPCR3_THSZERO6_Pos (6U)
9818#define DSI_WPCR3_THSZERO6_Msk (0x1U << DSI_WPCR3_THSZERO6_Pos) /*!< 0x00000040 */
9819#define DSI_WPCR3_THSZERO6 DSI_WPCR3_THSZERO6_Msk
9820#define DSI_WPCR3_THSZERO7_Pos (7U)
9821#define DSI_WPCR3_THSZERO7_Msk (0x1U << DSI_WPCR3_THSZERO7_Pos) /*!< 0x00000080 */
9822#define DSI_WPCR3_THSZERO7 DSI_WPCR3_THSZERO7_Msk
9823
9824#define DSI_WPCR3_TLPXD_Pos (8U)
9825#define DSI_WPCR3_TLPXD_Msk (0xFFU << DSI_WPCR3_TLPXD_Pos) /*!< 0x0000FF00 */
9826#define DSI_WPCR3_TLPXD DSI_WPCR3_TLPXD_Msk /*!< t-LPXD */
9827#define DSI_WPCR3_TLPXD0_Pos (8U)
9828#define DSI_WPCR3_TLPXD0_Msk (0x1U << DSI_WPCR3_TLPXD0_Pos) /*!< 0x00000100 */
9829#define DSI_WPCR3_TLPXD0 DSI_WPCR3_TLPXD0_Msk
9830#define DSI_WPCR3_TLPXD1_Pos (9U)
9831#define DSI_WPCR3_TLPXD1_Msk (0x1U << DSI_WPCR3_TLPXD1_Pos) /*!< 0x00000200 */
9832#define DSI_WPCR3_TLPXD1 DSI_WPCR3_TLPXD1_Msk
9833#define DSI_WPCR3_TLPXD2_Pos (10U)
9834#define DSI_WPCR3_TLPXD2_Msk (0x1U << DSI_WPCR3_TLPXD2_Pos) /*!< 0x00000400 */
9835#define DSI_WPCR3_TLPXD2 DSI_WPCR3_TLPXD2_Msk
9836#define DSI_WPCR3_TLPXD3_Pos (11U)
9837#define DSI_WPCR3_TLPXD3_Msk (0x1U << DSI_WPCR3_TLPXD3_Pos) /*!< 0x00000800 */
9838#define DSI_WPCR3_TLPXD3 DSI_WPCR3_TLPXD3_Msk
9839#define DSI_WPCR3_TLPXD4_Pos (12U)
9840#define DSI_WPCR3_TLPXD4_Msk (0x1U << DSI_WPCR3_TLPXD4_Pos) /*!< 0x00001000 */
9841#define DSI_WPCR3_TLPXD4 DSI_WPCR3_TLPXD4_Msk
9842#define DSI_WPCR3_TLPXD5_Pos (13U)
9843#define DSI_WPCR3_TLPXD5_Msk (0x1U << DSI_WPCR3_TLPXD5_Pos) /*!< 0x00002000 */
9844#define DSI_WPCR3_TLPXD5 DSI_WPCR3_TLPXD5_Msk
9845#define DSI_WPCR3_TLPXD6_Pos (14U)
9846#define DSI_WPCR3_TLPXD6_Msk (0x1U << DSI_WPCR3_TLPXD6_Pos) /*!< 0x00004000 */
9847#define DSI_WPCR3_TLPXD6 DSI_WPCR3_TLPXD6_Msk
9848#define DSI_WPCR3_TLPXD7_Pos (15U)
9849#define DSI_WPCR3_TLPXD7_Msk (0x1U << DSI_WPCR3_TLPXD7_Pos) /*!< 0x00008000 */
9850#define DSI_WPCR3_TLPXD7 DSI_WPCR3_TLPXD7_Msk
9851
9852#define DSI_WPCR3_THSEXIT_Pos (16U)
9853#define DSI_WPCR3_THSEXIT_Msk (0xFFU << DSI_WPCR3_THSEXIT_Pos) /*!< 0x00FF0000 */
9854#define DSI_WPCR3_THSEXIT DSI_WPCR3_THSEXIT_Msk /*!< t-HSEXIT */
9855#define DSI_WPCR3_THSEXIT0_Pos (16U)
9856#define DSI_WPCR3_THSEXIT0_Msk (0x1U << DSI_WPCR3_THSEXIT0_Pos) /*!< 0x00010000 */
9857#define DSI_WPCR3_THSEXIT0 DSI_WPCR3_THSEXIT0_Msk
9858#define DSI_WPCR3_THSEXIT1_Pos (17U)
9859#define DSI_WPCR3_THSEXIT1_Msk (0x1U << DSI_WPCR3_THSEXIT1_Pos) /*!< 0x00020000 */
9860#define DSI_WPCR3_THSEXIT1 DSI_WPCR3_THSEXIT1_Msk
9861#define DSI_WPCR3_THSEXIT2_Pos (18U)
9862#define DSI_WPCR3_THSEXIT2_Msk (0x1U << DSI_WPCR3_THSEXIT2_Pos) /*!< 0x00040000 */
9863#define DSI_WPCR3_THSEXIT2 DSI_WPCR3_THSEXIT2_Msk
9864#define DSI_WPCR3_THSEXIT3_Pos (19U)
9865#define DSI_WPCR3_THSEXIT3_Msk (0x1U << DSI_WPCR3_THSEXIT3_Pos) /*!< 0x00080000 */
9866#define DSI_WPCR3_THSEXIT3 DSI_WPCR3_THSEXIT3_Msk
9867#define DSI_WPCR3_THSEXIT4_Pos (20U)
9868#define DSI_WPCR3_THSEXIT4_Msk (0x1U << DSI_WPCR3_THSEXIT4_Pos) /*!< 0x00100000 */
9869#define DSI_WPCR3_THSEXIT4 DSI_WPCR3_THSEXIT4_Msk
9870#define DSI_WPCR3_THSEXIT5_Pos (21U)
9871#define DSI_WPCR3_THSEXIT5_Msk (0x1U << DSI_WPCR3_THSEXIT5_Pos) /*!< 0x00200000 */
9872#define DSI_WPCR3_THSEXIT5 DSI_WPCR3_THSEXIT5_Msk
9873#define DSI_WPCR3_THSEXIT6_Pos (22U)
9874#define DSI_WPCR3_THSEXIT6_Msk (0x1U << DSI_WPCR3_THSEXIT6_Pos) /*!< 0x00400000 */
9875#define DSI_WPCR3_THSEXIT6 DSI_WPCR3_THSEXIT6_Msk
9876#define DSI_WPCR3_THSEXIT7_Pos (23U)
9877#define DSI_WPCR3_THSEXIT7_Msk (0x1U << DSI_WPCR3_THSEXIT7_Pos) /*!< 0x00800000 */
9878#define DSI_WPCR3_THSEXIT7 DSI_WPCR3_THSEXIT7_Msk
9879
9880#define DSI_WPCR3_TLPXC_Pos (24U)
9881#define DSI_WPCR3_TLPXC_Msk (0xFFU << DSI_WPCR3_TLPXC_Pos) /*!< 0xFF000000 */
9882#define DSI_WPCR3_TLPXC DSI_WPCR3_TLPXC_Msk /*!< t-LPXC */
9883#define DSI_WPCR3_TLPXC0_Pos (24U)
9884#define DSI_WPCR3_TLPXC0_Msk (0x1U << DSI_WPCR3_TLPXC0_Pos) /*!< 0x01000000 */
9885#define DSI_WPCR3_TLPXC0 DSI_WPCR3_TLPXC0_Msk
9886#define DSI_WPCR3_TLPXC1_Pos (25U)
9887#define DSI_WPCR3_TLPXC1_Msk (0x1U << DSI_WPCR3_TLPXC1_Pos) /*!< 0x02000000 */
9888#define DSI_WPCR3_TLPXC1 DSI_WPCR3_TLPXC1_Msk
9889#define DSI_WPCR3_TLPXC2_Pos (26U)
9890#define DSI_WPCR3_TLPXC2_Msk (0x1U << DSI_WPCR3_TLPXC2_Pos) /*!< 0x04000000 */
9891#define DSI_WPCR3_TLPXC2 DSI_WPCR3_TLPXC2_Msk
9892#define DSI_WPCR3_TLPXC3_Pos (27U)
9893#define DSI_WPCR3_TLPXC3_Msk (0x1U << DSI_WPCR3_TLPXC3_Pos) /*!< 0x08000000 */
9894#define DSI_WPCR3_TLPXC3 DSI_WPCR3_TLPXC3_Msk
9895#define DSI_WPCR3_TLPXC4_Pos (28U)
9896#define DSI_WPCR3_TLPXC4_Msk (0x1U << DSI_WPCR3_TLPXC4_Pos) /*!< 0x10000000 */
9897#define DSI_WPCR3_TLPXC4 DSI_WPCR3_TLPXC4_Msk
9898#define DSI_WPCR3_TLPXC5_Pos (29U)
9899#define DSI_WPCR3_TLPXC5_Msk (0x1U << DSI_WPCR3_TLPXC5_Pos) /*!< 0x20000000 */
9900#define DSI_WPCR3_TLPXC5 DSI_WPCR3_TLPXC5_Msk
9901#define DSI_WPCR3_TLPXC6_Pos (30U)
9902#define DSI_WPCR3_TLPXC6_Msk (0x1U << DSI_WPCR3_TLPXC6_Pos) /*!< 0x40000000 */
9903#define DSI_WPCR3_TLPXC6 DSI_WPCR3_TLPXC6_Msk
9904#define DSI_WPCR3_TLPXC7_Pos (31U)
9905#define DSI_WPCR3_TLPXC7_Msk (0x1U << DSI_WPCR3_TLPXC7_Pos) /*!< 0x80000000 */
9906#define DSI_WPCR3_TLPXC7 DSI_WPCR3_TLPXC7_Msk
9907
9908/******************* Bit definition for DSI_WPCR4 register ***************/
9909#define DSI_WPCR4_TCLKPOST_Pos (0U)
9910#define DSI_WPCR4_TCLKPOST_Msk (0xFFU << DSI_WPCR4_TCLKPOST_Pos) /*!< 0x000000FF */
9911#define DSI_WPCR4_TCLKPOST DSI_WPCR4_TCLKPOST_Msk /*!< t-CLKPOST */
9912#define DSI_WPCR4_TCLKPOST0_Pos (0U)
9913#define DSI_WPCR4_TCLKPOST0_Msk (0x1U << DSI_WPCR4_TCLKPOST0_Pos) /*!< 0x00000001 */
9914#define DSI_WPCR4_TCLKPOST0 DSI_WPCR4_TCLKPOST0_Msk
9915#define DSI_WPCR4_TCLKPOST1_Pos (1U)
9916#define DSI_WPCR4_TCLKPOST1_Msk (0x1U << DSI_WPCR4_TCLKPOST1_Pos) /*!< 0x00000002 */
9917#define DSI_WPCR4_TCLKPOST1 DSI_WPCR4_TCLKPOST1_Msk
9918#define DSI_WPCR4_TCLKPOST2_Pos (2U)
9919#define DSI_WPCR4_TCLKPOST2_Msk (0x1U << DSI_WPCR4_TCLKPOST2_Pos) /*!< 0x00000004 */
9920#define DSI_WPCR4_TCLKPOST2 DSI_WPCR4_TCLKPOST2_Msk
9921#define DSI_WPCR4_TCLKPOST3_Pos (3U)
9922#define DSI_WPCR4_TCLKPOST3_Msk (0x1U << DSI_WPCR4_TCLKPOST3_Pos) /*!< 0x00000008 */
9923#define DSI_WPCR4_TCLKPOST3 DSI_WPCR4_TCLKPOST3_Msk
9924#define DSI_WPCR4_TCLKPOST4_Pos (4U)
9925#define DSI_WPCR4_TCLKPOST4_Msk (0x1U << DSI_WPCR4_TCLKPOST4_Pos) /*!< 0x00000010 */
9926#define DSI_WPCR4_TCLKPOST4 DSI_WPCR4_TCLKPOST4_Msk
9927#define DSI_WPCR4_TCLKPOST5_Pos (5U)
9928#define DSI_WPCR4_TCLKPOST5_Msk (0x1U << DSI_WPCR4_TCLKPOST5_Pos) /*!< 0x00000020 */
9929#define DSI_WPCR4_TCLKPOST5 DSI_WPCR4_TCLKPOST5_Msk
9930#define DSI_WPCR4_TCLKPOST6_Pos (6U)
9931#define DSI_WPCR4_TCLKPOST6_Msk (0x1U << DSI_WPCR4_TCLKPOST6_Pos) /*!< 0x00000040 */
9932#define DSI_WPCR4_TCLKPOST6 DSI_WPCR4_TCLKPOST6_Msk
9933#define DSI_WPCR4_TCLKPOST7_Pos (7U)
9934#define DSI_WPCR4_TCLKPOST7_Msk (0x1U << DSI_WPCR4_TCLKPOST7_Pos) /*!< 0x00000080 */
9935#define DSI_WPCR4_TCLKPOST7 DSI_WPCR4_TCLKPOST7_Msk
9936
9937/******************* Bit definition for DSI_WRPCR register ***************/
9938#define DSI_WRPCR_PLLEN_Pos (0U)
9939#define DSI_WRPCR_PLLEN_Msk (0x1U << DSI_WRPCR_PLLEN_Pos) /*!< 0x00000001 */
9940#define DSI_WRPCR_PLLEN DSI_WRPCR_PLLEN_Msk /*!< PLL Enable */
9941#define DSI_WRPCR_PLL_NDIV_Pos (2U)
9942#define DSI_WRPCR_PLL_NDIV_Msk (0x7FU << DSI_WRPCR_PLL_NDIV_Pos) /*!< 0x000001FC */
9943#define DSI_WRPCR_PLL_NDIV DSI_WRPCR_PLL_NDIV_Msk /*!< PLL Loop Division Factor */
9944#define DSI_WRPCR_PLL_NDIV0_Pos (2U)
9945#define DSI_WRPCR_PLL_NDIV0_Msk (0x1U << DSI_WRPCR_PLL_NDIV0_Pos) /*!< 0x00000004 */
9946#define DSI_WRPCR_PLL_NDIV0 DSI_WRPCR_PLL_NDIV0_Msk
9947#define DSI_WRPCR_PLL_NDIV1_Pos (3U)
9948#define DSI_WRPCR_PLL_NDIV1_Msk (0x1U << DSI_WRPCR_PLL_NDIV1_Pos) /*!< 0x00000008 */
9949#define DSI_WRPCR_PLL_NDIV1 DSI_WRPCR_PLL_NDIV1_Msk
9950#define DSI_WRPCR_PLL_NDIV2_Pos (4U)
9951#define DSI_WRPCR_PLL_NDIV2_Msk (0x1U << DSI_WRPCR_PLL_NDIV2_Pos) /*!< 0x00000010 */
9952#define DSI_WRPCR_PLL_NDIV2 DSI_WRPCR_PLL_NDIV2_Msk
9953#define DSI_WRPCR_PLL_NDIV3_Pos (5U)
9954#define DSI_WRPCR_PLL_NDIV3_Msk (0x1U << DSI_WRPCR_PLL_NDIV3_Pos) /*!< 0x00000020 */
9955#define DSI_WRPCR_PLL_NDIV3 DSI_WRPCR_PLL_NDIV3_Msk
9956#define DSI_WRPCR_PLL_NDIV4_Pos (6U)
9957#define DSI_WRPCR_PLL_NDIV4_Msk (0x1U << DSI_WRPCR_PLL_NDIV4_Pos) /*!< 0x00000040 */
9958#define DSI_WRPCR_PLL_NDIV4 DSI_WRPCR_PLL_NDIV4_Msk
9959#define DSI_WRPCR_PLL_NDIV5_Pos (7U)
9960#define DSI_WRPCR_PLL_NDIV5_Msk (0x1U << DSI_WRPCR_PLL_NDIV5_Pos) /*!< 0x00000080 */
9961#define DSI_WRPCR_PLL_NDIV5 DSI_WRPCR_PLL_NDIV5_Msk
9962#define DSI_WRPCR_PLL_NDIV6_Pos (8U)
9963#define DSI_WRPCR_PLL_NDIV6_Msk (0x1U << DSI_WRPCR_PLL_NDIV6_Pos) /*!< 0x00000100 */
9964#define DSI_WRPCR_PLL_NDIV6 DSI_WRPCR_PLL_NDIV6_Msk
9965
9966#define DSI_WRPCR_PLL_IDF_Pos (11U)
9967#define DSI_WRPCR_PLL_IDF_Msk (0xFU << DSI_WRPCR_PLL_IDF_Pos) /*!< 0x00007800 */
9968#define DSI_WRPCR_PLL_IDF DSI_WRPCR_PLL_IDF_Msk /*!< PLL Input Division Factor */
9969#define DSI_WRPCR_PLL_IDF0_Pos (11U)
9970#define DSI_WRPCR_PLL_IDF0_Msk (0x1U << DSI_WRPCR_PLL_IDF0_Pos) /*!< 0x00000800 */
9971#define DSI_WRPCR_PLL_IDF0 DSI_WRPCR_PLL_IDF0_Msk
9972#define DSI_WRPCR_PLL_IDF1_Pos (12U)
9973#define DSI_WRPCR_PLL_IDF1_Msk (0x1U << DSI_WRPCR_PLL_IDF1_Pos) /*!< 0x00001000 */
9974#define DSI_WRPCR_PLL_IDF1 DSI_WRPCR_PLL_IDF1_Msk
9975#define DSI_WRPCR_PLL_IDF2_Pos (13U)
9976#define DSI_WRPCR_PLL_IDF2_Msk (0x1U << DSI_WRPCR_PLL_IDF2_Pos) /*!< 0x00002000 */
9977#define DSI_WRPCR_PLL_IDF2 DSI_WRPCR_PLL_IDF2_Msk
9978#define DSI_WRPCR_PLL_IDF3_Pos (14U)
9979#define DSI_WRPCR_PLL_IDF3_Msk (0x1U << DSI_WRPCR_PLL_IDF3_Pos) /*!< 0x00004000 */
9980#define DSI_WRPCR_PLL_IDF3 DSI_WRPCR_PLL_IDF3_Msk
9981
9982#define DSI_WRPCR_PLL_ODF_Pos (16U)
9983#define DSI_WRPCR_PLL_ODF_Msk (0x3U << DSI_WRPCR_PLL_ODF_Pos) /*!< 0x00030000 */
9984#define DSI_WRPCR_PLL_ODF DSI_WRPCR_PLL_ODF_Msk /*!< PLL Output Division Factor */
9985#define DSI_WRPCR_PLL_ODF0_Pos (16U)
9986#define DSI_WRPCR_PLL_ODF0_Msk (0x1U << DSI_WRPCR_PLL_ODF0_Pos) /*!< 0x00010000 */
9987#define DSI_WRPCR_PLL_ODF0 DSI_WRPCR_PLL_ODF0_Msk
9988#define DSI_WRPCR_PLL_ODF1_Pos (17U)
9989#define DSI_WRPCR_PLL_ODF1_Msk (0x1U << DSI_WRPCR_PLL_ODF1_Pos) /*!< 0x00020000 */
9990#define DSI_WRPCR_PLL_ODF1 DSI_WRPCR_PLL_ODF1_Msk
9991
9992#define DSI_WRPCR_REGEN_Pos (24U)
9993#define DSI_WRPCR_REGEN_Msk (0x1U << DSI_WRPCR_REGEN_Pos) /*!< 0x01000000 */
9994#define DSI_WRPCR_REGEN DSI_WRPCR_REGEN_Msk /*!< Regulator Enable */
9995
9996/******************************************************************************/
9997/* */
9998/* External Interrupt/Event Controller */
9999/* */
10000/******************************************************************************/
10001/******************* Bit definition for EXTI_IMR register *******************/
10002#define EXTI_IMR_MR0_Pos (0U)
10003#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
10004#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
10005#define EXTI_IMR_MR1_Pos (1U)
10006#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
10007#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
10008#define EXTI_IMR_MR2_Pos (2U)
10009#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
10010#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
10011#define EXTI_IMR_MR3_Pos (3U)
10012#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
10013#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
10014#define EXTI_IMR_MR4_Pos (4U)
10015#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
10016#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
10017#define EXTI_IMR_MR5_Pos (5U)
10018#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
10019#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
10020#define EXTI_IMR_MR6_Pos (6U)
10021#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
10022#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
10023#define EXTI_IMR_MR7_Pos (7U)
10024#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
10025#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
10026#define EXTI_IMR_MR8_Pos (8U)
10027#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
10028#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
10029#define EXTI_IMR_MR9_Pos (9U)
10030#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
10031#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
10032#define EXTI_IMR_MR10_Pos (10U)
10033#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
10034#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
10035#define EXTI_IMR_MR11_Pos (11U)
10036#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
10037#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
10038#define EXTI_IMR_MR12_Pos (12U)
10039#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
10040#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
10041#define EXTI_IMR_MR13_Pos (13U)
10042#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
10043#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
10044#define EXTI_IMR_MR14_Pos (14U)
10045#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
10046#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
10047#define EXTI_IMR_MR15_Pos (15U)
10048#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
10049#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
10050#define EXTI_IMR_MR16_Pos (16U)
10051#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
10052#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
10053#define EXTI_IMR_MR17_Pos (17U)
10054#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
10055#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
10056#define EXTI_IMR_MR18_Pos (18U)
10057#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
10058#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
10059#define EXTI_IMR_MR19_Pos (19U)
10060#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
10061#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
10062#define EXTI_IMR_MR20_Pos (20U)
10063#define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
10064#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
10065#define EXTI_IMR_MR21_Pos (21U)
10066#define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
10067#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
10068#define EXTI_IMR_MR22_Pos (22U)
10069#define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
10070#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
10071
10072/* Reference Defines */
10073#define EXTI_IMR_IM0 EXTI_IMR_MR0
10074#define EXTI_IMR_IM1 EXTI_IMR_MR1
10075#define EXTI_IMR_IM2 EXTI_IMR_MR2
10076#define EXTI_IMR_IM3 EXTI_IMR_MR3
10077#define EXTI_IMR_IM4 EXTI_IMR_MR4
10078#define EXTI_IMR_IM5 EXTI_IMR_MR5
10079#define EXTI_IMR_IM6 EXTI_IMR_MR6
10080#define EXTI_IMR_IM7 EXTI_IMR_MR7
10081#define EXTI_IMR_IM8 EXTI_IMR_MR8
10082#define EXTI_IMR_IM9 EXTI_IMR_MR9
10083#define EXTI_IMR_IM10 EXTI_IMR_MR10
10084#define EXTI_IMR_IM11 EXTI_IMR_MR11
10085#define EXTI_IMR_IM12 EXTI_IMR_MR12
10086#define EXTI_IMR_IM13 EXTI_IMR_MR13
10087#define EXTI_IMR_IM14 EXTI_IMR_MR14
10088#define EXTI_IMR_IM15 EXTI_IMR_MR15
10089#define EXTI_IMR_IM16 EXTI_IMR_MR16
10090#define EXTI_IMR_IM17 EXTI_IMR_MR17
10091#define EXTI_IMR_IM18 EXTI_IMR_MR18
10092#define EXTI_IMR_IM19 EXTI_IMR_MR19
10093#define EXTI_IMR_IM20 EXTI_IMR_MR20
10094#define EXTI_IMR_IM21 EXTI_IMR_MR21
10095#define EXTI_IMR_IM22 EXTI_IMR_MR22
10096#define EXTI_IMR_IM_Pos (0U)
10097#define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
10098#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
10099
10100/******************* Bit definition for EXTI_EMR register *******************/
10101#define EXTI_EMR_MR0_Pos (0U)
10102#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
10103#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
10104#define EXTI_EMR_MR1_Pos (1U)
10105#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
10106#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
10107#define EXTI_EMR_MR2_Pos (2U)
10108#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
10109#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
10110#define EXTI_EMR_MR3_Pos (3U)
10111#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
10112#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
10113#define EXTI_EMR_MR4_Pos (4U)
10114#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
10115#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
10116#define EXTI_EMR_MR5_Pos (5U)
10117#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
10118#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
10119#define EXTI_EMR_MR6_Pos (6U)
10120#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
10121#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
10122#define EXTI_EMR_MR7_Pos (7U)
10123#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
10124#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
10125#define EXTI_EMR_MR8_Pos (8U)
10126#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
10127#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
10128#define EXTI_EMR_MR9_Pos (9U)
10129#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
10130#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
10131#define EXTI_EMR_MR10_Pos (10U)
10132#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
10133#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
10134#define EXTI_EMR_MR11_Pos (11U)
10135#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
10136#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
10137#define EXTI_EMR_MR12_Pos (12U)
10138#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
10139#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
10140#define EXTI_EMR_MR13_Pos (13U)
10141#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
10142#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
10143#define EXTI_EMR_MR14_Pos (14U)
10144#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
10145#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
10146#define EXTI_EMR_MR15_Pos (15U)
10147#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
10148#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
10149#define EXTI_EMR_MR16_Pos (16U)
10150#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
10151#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
10152#define EXTI_EMR_MR17_Pos (17U)
10153#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
10154#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
10155#define EXTI_EMR_MR18_Pos (18U)
10156#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
10157#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
10158#define EXTI_EMR_MR19_Pos (19U)
10159#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
10160#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
10161#define EXTI_EMR_MR20_Pos (20U)
10162#define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
10163#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
10164#define EXTI_EMR_MR21_Pos (21U)
10165#define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
10166#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
10167#define EXTI_EMR_MR22_Pos (22U)
10168#define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
10169#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
10170
10171/* Reference Defines */
10172#define EXTI_EMR_EM0 EXTI_EMR_MR0
10173#define EXTI_EMR_EM1 EXTI_EMR_MR1
10174#define EXTI_EMR_EM2 EXTI_EMR_MR2
10175#define EXTI_EMR_EM3 EXTI_EMR_MR3
10176#define EXTI_EMR_EM4 EXTI_EMR_MR4
10177#define EXTI_EMR_EM5 EXTI_EMR_MR5
10178#define EXTI_EMR_EM6 EXTI_EMR_MR6
10179#define EXTI_EMR_EM7 EXTI_EMR_MR7
10180#define EXTI_EMR_EM8 EXTI_EMR_MR8
10181#define EXTI_EMR_EM9 EXTI_EMR_MR9
10182#define EXTI_EMR_EM10 EXTI_EMR_MR10
10183#define EXTI_EMR_EM11 EXTI_EMR_MR11
10184#define EXTI_EMR_EM12 EXTI_EMR_MR12
10185#define EXTI_EMR_EM13 EXTI_EMR_MR13
10186#define EXTI_EMR_EM14 EXTI_EMR_MR14
10187#define EXTI_EMR_EM15 EXTI_EMR_MR15
10188#define EXTI_EMR_EM16 EXTI_EMR_MR16
10189#define EXTI_EMR_EM17 EXTI_EMR_MR17
10190#define EXTI_EMR_EM18 EXTI_EMR_MR18
10191#define EXTI_EMR_EM19 EXTI_EMR_MR19
10192#define EXTI_EMR_EM20 EXTI_EMR_MR20
10193#define EXTI_EMR_EM21 EXTI_EMR_MR21
10194#define EXTI_EMR_EM22 EXTI_EMR_MR22
10195
10196/****************** Bit definition for EXTI_RTSR register *******************/
10197#define EXTI_RTSR_TR0_Pos (0U)
10198#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
10199#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
10200#define EXTI_RTSR_TR1_Pos (1U)
10201#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
10202#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
10203#define EXTI_RTSR_TR2_Pos (2U)
10204#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
10205#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
10206#define EXTI_RTSR_TR3_Pos (3U)
10207#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
10208#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
10209#define EXTI_RTSR_TR4_Pos (4U)
10210#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
10211#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
10212#define EXTI_RTSR_TR5_Pos (5U)
10213#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
10214#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
10215#define EXTI_RTSR_TR6_Pos (6U)
10216#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
10217#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
10218#define EXTI_RTSR_TR7_Pos (7U)
10219#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
10220#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
10221#define EXTI_RTSR_TR8_Pos (8U)
10222#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
10223#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
10224#define EXTI_RTSR_TR9_Pos (9U)
10225#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
10226#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
10227#define EXTI_RTSR_TR10_Pos (10U)
10228#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
10229#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
10230#define EXTI_RTSR_TR11_Pos (11U)
10231#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
10232#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
10233#define EXTI_RTSR_TR12_Pos (12U)
10234#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
10235#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
10236#define EXTI_RTSR_TR13_Pos (13U)
10237#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
10238#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
10239#define EXTI_RTSR_TR14_Pos (14U)
10240#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
10241#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
10242#define EXTI_RTSR_TR15_Pos (15U)
10243#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
10244#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
10245#define EXTI_RTSR_TR16_Pos (16U)
10246#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
10247#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
10248#define EXTI_RTSR_TR17_Pos (17U)
10249#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
10250#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
10251#define EXTI_RTSR_TR18_Pos (18U)
10252#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
10253#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
10254#define EXTI_RTSR_TR19_Pos (19U)
10255#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
10256#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
10257#define EXTI_RTSR_TR20_Pos (20U)
10258#define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
10259#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
10260#define EXTI_RTSR_TR21_Pos (21U)
10261#define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
10262#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
10263#define EXTI_RTSR_TR22_Pos (22U)
10264#define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
10265#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
10266
10267/****************** Bit definition for EXTI_FTSR register *******************/
10268#define EXTI_FTSR_TR0_Pos (0U)
10269#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
10270#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
10271#define EXTI_FTSR_TR1_Pos (1U)
10272#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
10273#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
10274#define EXTI_FTSR_TR2_Pos (2U)
10275#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
10276#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
10277#define EXTI_FTSR_TR3_Pos (3U)
10278#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
10279#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
10280#define EXTI_FTSR_TR4_Pos (4U)
10281#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
10282#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
10283#define EXTI_FTSR_TR5_Pos (5U)
10284#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
10285#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
10286#define EXTI_FTSR_TR6_Pos (6U)
10287#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
10288#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
10289#define EXTI_FTSR_TR7_Pos (7U)
10290#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
10291#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
10292#define EXTI_FTSR_TR8_Pos (8U)
10293#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
10294#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
10295#define EXTI_FTSR_TR9_Pos (9U)
10296#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
10297#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
10298#define EXTI_FTSR_TR10_Pos (10U)
10299#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
10300#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
10301#define EXTI_FTSR_TR11_Pos (11U)
10302#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
10303#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
10304#define EXTI_FTSR_TR12_Pos (12U)
10305#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
10306#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
10307#define EXTI_FTSR_TR13_Pos (13U)
10308#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
10309#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
10310#define EXTI_FTSR_TR14_Pos (14U)
10311#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
10312#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
10313#define EXTI_FTSR_TR15_Pos (15U)
10314#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
10315#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
10316#define EXTI_FTSR_TR16_Pos (16U)
10317#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
10318#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
10319#define EXTI_FTSR_TR17_Pos (17U)
10320#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
10321#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
10322#define EXTI_FTSR_TR18_Pos (18U)
10323#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
10324#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
10325#define EXTI_FTSR_TR19_Pos (19U)
10326#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
10327#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
10328#define EXTI_FTSR_TR20_Pos (20U)
10329#define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
10330#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
10331#define EXTI_FTSR_TR21_Pos (21U)
10332#define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
10333#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
10334#define EXTI_FTSR_TR22_Pos (22U)
10335#define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
10336#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
10337
10338/****************** Bit definition for EXTI_SWIER register ******************/
10339#define EXTI_SWIER_SWIER0_Pos (0U)
10340#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
10341#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
10342#define EXTI_SWIER_SWIER1_Pos (1U)
10343#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
10344#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
10345#define EXTI_SWIER_SWIER2_Pos (2U)
10346#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
10347#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
10348#define EXTI_SWIER_SWIER3_Pos (3U)
10349#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
10350#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
10351#define EXTI_SWIER_SWIER4_Pos (4U)
10352#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
10353#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
10354#define EXTI_SWIER_SWIER5_Pos (5U)
10355#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
10356#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
10357#define EXTI_SWIER_SWIER6_Pos (6U)
10358#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
10359#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
10360#define EXTI_SWIER_SWIER7_Pos (7U)
10361#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
10362#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
10363#define EXTI_SWIER_SWIER8_Pos (8U)
10364#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
10365#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
10366#define EXTI_SWIER_SWIER9_Pos (9U)
10367#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
10368#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
10369#define EXTI_SWIER_SWIER10_Pos (10U)
10370#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
10371#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
10372#define EXTI_SWIER_SWIER11_Pos (11U)
10373#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
10374#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
10375#define EXTI_SWIER_SWIER12_Pos (12U)
10376#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
10377#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
10378#define EXTI_SWIER_SWIER13_Pos (13U)
10379#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
10380#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
10381#define EXTI_SWIER_SWIER14_Pos (14U)
10382#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
10383#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
10384#define EXTI_SWIER_SWIER15_Pos (15U)
10385#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
10386#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
10387#define EXTI_SWIER_SWIER16_Pos (16U)
10388#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
10389#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
10390#define EXTI_SWIER_SWIER17_Pos (17U)
10391#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
10392#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
10393#define EXTI_SWIER_SWIER18_Pos (18U)
10394#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
10395#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
10396#define EXTI_SWIER_SWIER19_Pos (19U)
10397#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
10398#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
10399#define EXTI_SWIER_SWIER20_Pos (20U)
10400#define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
10401#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
10402#define EXTI_SWIER_SWIER21_Pos (21U)
10403#define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
10404#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
10405#define EXTI_SWIER_SWIER22_Pos (22U)
10406#define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
10407#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
10408
10409/******************* Bit definition for EXTI_PR register ********************/
10410#define EXTI_PR_PR0_Pos (0U)
10411#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
10412#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
10413#define EXTI_PR_PR1_Pos (1U)
10414#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
10415#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
10416#define EXTI_PR_PR2_Pos (2U)
10417#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
10418#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
10419#define EXTI_PR_PR3_Pos (3U)
10420#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
10421#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
10422#define EXTI_PR_PR4_Pos (4U)
10423#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
10424#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
10425#define EXTI_PR_PR5_Pos (5U)
10426#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
10427#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
10428#define EXTI_PR_PR6_Pos (6U)
10429#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
10430#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
10431#define EXTI_PR_PR7_Pos (7U)
10432#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
10433#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
10434#define EXTI_PR_PR8_Pos (8U)
10435#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
10436#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
10437#define EXTI_PR_PR9_Pos (9U)
10438#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
10439#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
10440#define EXTI_PR_PR10_Pos (10U)
10441#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
10442#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
10443#define EXTI_PR_PR11_Pos (11U)
10444#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
10445#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
10446#define EXTI_PR_PR12_Pos (12U)
10447#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
10448#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
10449#define EXTI_PR_PR13_Pos (13U)
10450#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
10451#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
10452#define EXTI_PR_PR14_Pos (14U)
10453#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
10454#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
10455#define EXTI_PR_PR15_Pos (15U)
10456#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
10457#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
10458#define EXTI_PR_PR16_Pos (16U)
10459#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
10460#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
10461#define EXTI_PR_PR17_Pos (17U)
10462#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
10463#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
10464#define EXTI_PR_PR18_Pos (18U)
10465#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
10466#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
10467#define EXTI_PR_PR19_Pos (19U)
10468#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
10469#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
10470#define EXTI_PR_PR20_Pos (20U)
10471#define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
10472#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
10473#define EXTI_PR_PR21_Pos (21U)
10474#define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
10475#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
10476#define EXTI_PR_PR22_Pos (22U)
10477#define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
10478#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
10479
10480/******************************************************************************/
10481/* */
10482/* FLASH */
10483/* */
10484/******************************************************************************/
10485/******************* Bits definition for FLASH_ACR register *****************/
10486#define FLASH_ACR_LATENCY_Pos (0U)
10487#define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
10488#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
10489#define FLASH_ACR_LATENCY_0WS 0x00000000U
10490#define FLASH_ACR_LATENCY_1WS 0x00000001U
10491#define FLASH_ACR_LATENCY_2WS 0x00000002U
10492#define FLASH_ACR_LATENCY_3WS 0x00000003U
10493#define FLASH_ACR_LATENCY_4WS 0x00000004U
10494#define FLASH_ACR_LATENCY_5WS 0x00000005U
10495#define FLASH_ACR_LATENCY_6WS 0x00000006U
10496#define FLASH_ACR_LATENCY_7WS 0x00000007U
10497
10498#define FLASH_ACR_LATENCY_8WS 0x00000008U
10499#define FLASH_ACR_LATENCY_9WS 0x00000009U
10500#define FLASH_ACR_LATENCY_10WS 0x0000000AU
10501#define FLASH_ACR_LATENCY_11WS 0x0000000BU
10502#define FLASH_ACR_LATENCY_12WS 0x0000000CU
10503#define FLASH_ACR_LATENCY_13WS 0x0000000DU
10504#define FLASH_ACR_LATENCY_14WS 0x0000000EU
10505#define FLASH_ACR_LATENCY_15WS 0x0000000FU
10506#define FLASH_ACR_PRFTEN_Pos (8U)
10507#define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
10508#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
10509#define FLASH_ACR_ICEN_Pos (9U)
10510#define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
10511#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
10512#define FLASH_ACR_DCEN_Pos (10U)
10513#define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
10514#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
10515#define FLASH_ACR_ICRST_Pos (11U)
10516#define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
10517#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
10518#define FLASH_ACR_DCRST_Pos (12U)
10519#define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
10520#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
10521#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
10522#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
10523#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
10524#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
10525#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
10526#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
10527
10528/******************* Bits definition for FLASH_SR register ******************/
10529#define FLASH_SR_EOP_Pos (0U)
10530#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
10531#define FLASH_SR_EOP FLASH_SR_EOP_Msk
10532#define FLASH_SR_SOP_Pos (1U)
10533#define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
10534#define FLASH_SR_SOP FLASH_SR_SOP_Msk
10535#define FLASH_SR_WRPERR_Pos (4U)
10536#define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
10537#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
10538#define FLASH_SR_PGAERR_Pos (5U)
10539#define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
10540#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
10541#define FLASH_SR_PGPERR_Pos (6U)
10542#define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
10543#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
10544#define FLASH_SR_PGSERR_Pos (7U)
10545#define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
10546#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
10547#define FLASH_SR_RDERR_Pos (8U)
10548#define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
10549#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
10550#define FLASH_SR_BSY_Pos (16U)
10551#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
10552#define FLASH_SR_BSY FLASH_SR_BSY_Msk
10553
10554/******************* Bits definition for FLASH_CR register ******************/
10555#define FLASH_CR_PG_Pos (0U)
10556#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
10557#define FLASH_CR_PG FLASH_CR_PG_Msk
10558#define FLASH_CR_SER_Pos (1U)
10559#define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
10560#define FLASH_CR_SER FLASH_CR_SER_Msk
10561#define FLASH_CR_MER_Pos (2U)
10562#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
10563#define FLASH_CR_MER FLASH_CR_MER_Msk
10564#define FLASH_CR_MER1 FLASH_CR_MER
10565#define FLASH_CR_SNB_Pos (3U)
10566#define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
10567#define FLASH_CR_SNB FLASH_CR_SNB_Msk
10568#define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
10569#define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
10570#define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
10571#define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
10572#define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
10573#define FLASH_CR_PSIZE_Pos (8U)
10574#define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
10575#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
10576#define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
10577#define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
10578#define FLASH_CR_MER2_Pos (15U)
10579#define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
10580#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
10581#define FLASH_CR_STRT_Pos (16U)
10582#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
10583#define FLASH_CR_STRT FLASH_CR_STRT_Msk
10584#define FLASH_CR_EOPIE_Pos (24U)
10585#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
10586#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
10587#define FLASH_CR_LOCK_Pos (31U)
10588#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
10589#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
10590
10591/******************* Bits definition for FLASH_OPTCR register ***************/
10592#define FLASH_OPTCR_OPTLOCK_Pos (0U)
10593#define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
10594#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
10595#define FLASH_OPTCR_OPTSTRT_Pos (1U)
10596#define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
10597#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
10598
10599#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
10600#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
10601#define FLASH_OPTCR_BOR_LEV_Pos (2U)
10602#define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
10603#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
10604#define FLASH_OPTCR_BFB2_Pos (4U)
10605#define FLASH_OPTCR_BFB2_Msk (0x1U << FLASH_OPTCR_BFB2_Pos) /*!< 0x00000010 */
10606#define FLASH_OPTCR_BFB2 FLASH_OPTCR_BFB2_Msk
10607#define FLASH_OPTCR_WDG_SW_Pos (5U)
10608#define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
10609#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
10610#define FLASH_OPTCR_nRST_STOP_Pos (6U)
10611#define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
10612#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
10613#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
10614#define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
10615#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
10616#define FLASH_OPTCR_RDP_Pos (8U)
10617#define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
10618#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
10619#define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
10620#define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
10621#define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
10622#define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
10623#define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
10624#define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
10625#define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
10626#define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
10627#define FLASH_OPTCR_nWRP_Pos (16U)
10628#define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
10629#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
10630#define FLASH_OPTCR_nWRP_0 0x00010000U
10631#define FLASH_OPTCR_nWRP_1 0x00020000U
10632#define FLASH_OPTCR_nWRP_2 0x00040000U
10633#define FLASH_OPTCR_nWRP_3 0x00080000U
10634#define FLASH_OPTCR_nWRP_4 0x00100000U
10635#define FLASH_OPTCR_nWRP_5 0x00200000U
10636#define FLASH_OPTCR_nWRP_6 0x00400000U
10637#define FLASH_OPTCR_nWRP_7 0x00800000U
10638#define FLASH_OPTCR_nWRP_8 0x01000000U
10639#define FLASH_OPTCR_nWRP_9 0x02000000U
10640#define FLASH_OPTCR_nWRP_10 0x04000000U
10641#define FLASH_OPTCR_nWRP_11 0x08000000U
10642#define FLASH_OPTCR_DB1M_Pos (30U)
10643#define FLASH_OPTCR_DB1M_Msk (0x1U << FLASH_OPTCR_DB1M_Pos) /*!< 0x40000000 */
10644#define FLASH_OPTCR_DB1M FLASH_OPTCR_DB1M_Msk
10645#define FLASH_OPTCR_SPRMOD_Pos (31U)
10646#define FLASH_OPTCR_SPRMOD_Msk (0x1U << FLASH_OPTCR_SPRMOD_Pos) /*!< 0x80000000 */
10647#define FLASH_OPTCR_SPRMOD FLASH_OPTCR_SPRMOD_Msk
10648
10649/****************** Bits definition for FLASH_OPTCR1 register ***************/
10650#define FLASH_OPTCR1_nWRP_Pos (16U)
10651#define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
10652#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
10653#define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
10654#define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
10655#define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
10656#define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
10657#define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
10658#define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
10659#define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
10660#define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
10661#define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
10662#define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
10663#define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
10664#define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
10665
10666/******************************************************************************/
10667/* */
10668/* Flexible Memory Controller */
10669/* */
10670/******************************************************************************/
10671/****************** Bit definition for FMC_BCR1 register *******************/
10672#define FMC_BCR1_MBKEN_Pos (0U)
10673#define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
10674#define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
10675#define FMC_BCR1_MUXEN_Pos (1U)
10676#define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
10677#define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
10678
10679#define FMC_BCR1_MTYP_Pos (2U)
10680#define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
10681#define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
10682#define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
10683#define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
10684
10685#define FMC_BCR1_MWID_Pos (4U)
10686#define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
10687#define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
10688#define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
10689#define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
10690
10691#define FMC_BCR1_FACCEN_Pos (6U)
10692#define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
10693#define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
10694#define FMC_BCR1_BURSTEN_Pos (8U)
10695#define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
10696#define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
10697#define FMC_BCR1_WAITPOL_Pos (9U)
10698#define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
10699#define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
10700#define FMC_BCR1_WAITCFG_Pos (11U)
10701#define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
10702#define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
10703#define FMC_BCR1_WREN_Pos (12U)
10704#define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
10705#define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
10706#define FMC_BCR1_WAITEN_Pos (13U)
10707#define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
10708#define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
10709#define FMC_BCR1_EXTMOD_Pos (14U)
10710#define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
10711#define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
10712#define FMC_BCR1_ASYNCWAIT_Pos (15U)
10713#define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
10714#define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
10715#define FMC_BCR1_CPSIZE_Pos (16U)
10716#define FMC_BCR1_CPSIZE_Msk (0x7U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
10717#define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
10718#define FMC_BCR1_CPSIZE_0 (0x1U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
10719#define FMC_BCR1_CPSIZE_1 (0x2U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
10720#define FMC_BCR1_CPSIZE_2 (0x4U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
10721#define FMC_BCR1_CBURSTRW_Pos (19U)
10722#define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
10723#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
10724#define FMC_BCR1_CCLKEN_Pos (20U)
10725#define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
10726#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
10727#define FMC_BCR1_WFDIS_Pos (21U)
10728#define FMC_BCR1_WFDIS_Msk (0x1U << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
10729#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
10730
10731/****************** Bit definition for FMC_BCR2 register *******************/
10732#define FMC_BCR2_MBKEN_Pos (0U)
10733#define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
10734#define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
10735#define FMC_BCR2_MUXEN_Pos (1U)
10736#define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
10737#define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
10738
10739#define FMC_BCR2_MTYP_Pos (2U)
10740#define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
10741#define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
10742#define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
10743#define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
10744
10745#define FMC_BCR2_MWID_Pos (4U)
10746#define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
10747#define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
10748#define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
10749#define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
10750
10751#define FMC_BCR2_FACCEN_Pos (6U)
10752#define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
10753#define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
10754#define FMC_BCR2_BURSTEN_Pos (8U)
10755#define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
10756#define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
10757#define FMC_BCR2_WAITPOL_Pos (9U)
10758#define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
10759#define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
10760#define FMC_BCR2_WAITCFG_Pos (11U)
10761#define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
10762#define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
10763#define FMC_BCR2_WREN_Pos (12U)
10764#define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
10765#define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
10766#define FMC_BCR2_WAITEN_Pos (13U)
10767#define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
10768#define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
10769#define FMC_BCR2_EXTMOD_Pos (14U)
10770#define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
10771#define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
10772#define FMC_BCR2_ASYNCWAIT_Pos (15U)
10773#define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
10774#define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
10775#define FMC_BCR2_CBURSTRW_Pos (19U)
10776#define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
10777#define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
10778
10779/****************** Bit definition for FMC_BCR3 register *******************/
10780#define FMC_BCR3_MBKEN_Pos (0U)
10781#define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
10782#define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
10783#define FMC_BCR3_MUXEN_Pos (1U)
10784#define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
10785#define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
10786
10787#define FMC_BCR3_MTYP_Pos (2U)
10788#define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
10789#define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
10790#define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
10791#define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
10792
10793#define FMC_BCR3_MWID_Pos (4U)
10794#define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
10795#define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
10796#define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
10797#define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
10798
10799#define FMC_BCR3_FACCEN_Pos (6U)
10800#define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
10801#define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
10802#define FMC_BCR3_BURSTEN_Pos (8U)
10803#define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
10804#define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
10805#define FMC_BCR3_WAITPOL_Pos (9U)
10806#define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
10807#define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
10808#define FMC_BCR3_WAITCFG_Pos (11U)
10809#define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
10810#define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
10811#define FMC_BCR3_WREN_Pos (12U)
10812#define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
10813#define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
10814#define FMC_BCR3_WAITEN_Pos (13U)
10815#define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
10816#define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
10817#define FMC_BCR3_EXTMOD_Pos (14U)
10818#define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
10819#define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
10820#define FMC_BCR3_ASYNCWAIT_Pos (15U)
10821#define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
10822#define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
10823#define FMC_BCR3_CBURSTRW_Pos (19U)
10824#define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
10825#define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
10826
10827/****************** Bit definition for FMC_BCR4 register *******************/
10828#define FMC_BCR4_MBKEN_Pos (0U)
10829#define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
10830#define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
10831#define FMC_BCR4_MUXEN_Pos (1U)
10832#define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
10833#define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
10834
10835#define FMC_BCR4_MTYP_Pos (2U)
10836#define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
10837#define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
10838#define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
10839#define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
10840
10841#define FMC_BCR4_MWID_Pos (4U)
10842#define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
10843#define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
10844#define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
10845#define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
10846
10847#define FMC_BCR4_FACCEN_Pos (6U)
10848#define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
10849#define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
10850#define FMC_BCR4_BURSTEN_Pos (8U)
10851#define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
10852#define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
10853#define FMC_BCR4_WAITPOL_Pos (9U)
10854#define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
10855#define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
10856#define FMC_BCR4_WAITCFG_Pos (11U)
10857#define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
10858#define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
10859#define FMC_BCR4_WREN_Pos (12U)
10860#define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
10861#define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
10862#define FMC_BCR4_WAITEN_Pos (13U)
10863#define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
10864#define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
10865#define FMC_BCR4_EXTMOD_Pos (14U)
10866#define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
10867#define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
10868#define FMC_BCR4_ASYNCWAIT_Pos (15U)
10869#define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
10870#define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
10871#define FMC_BCR4_CBURSTRW_Pos (19U)
10872#define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
10873#define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
10874
10875/****************** Bit definition for FMC_BTR1 register ******************/
10876#define FMC_BTR1_ADDSET_Pos (0U)
10877#define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
10878#define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
10879#define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
10880#define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
10881#define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
10882#define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
10883
10884#define FMC_BTR1_ADDHLD_Pos (4U)
10885#define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
10886#define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
10887#define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
10888#define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
10889#define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
10890#define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
10891
10892#define FMC_BTR1_DATAST_Pos (8U)
10893#define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
10894#define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
10895#define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
10896#define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
10897#define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
10898#define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
10899#define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
10900#define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
10901#define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
10902#define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
10903
10904#define FMC_BTR1_BUSTURN_Pos (16U)
10905#define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
10906#define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
10907#define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
10908#define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
10909#define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
10910#define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
10911
10912#define FMC_BTR1_CLKDIV_Pos (20U)
10913#define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
10914#define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
10915#define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
10916#define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
10917#define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
10918#define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
10919
10920#define FMC_BTR1_DATLAT_Pos (24U)
10921#define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
10922#define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
10923#define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
10924#define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
10925#define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
10926#define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
10927
10928#define FMC_BTR1_ACCMOD_Pos (28U)
10929#define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
10930#define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
10931#define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
10932#define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
10933
10934/****************** Bit definition for FMC_BTR2 register *******************/
10935#define FMC_BTR2_ADDSET_Pos (0U)
10936#define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
10937#define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
10938#define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
10939#define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
10940#define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
10941#define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
10942
10943#define FMC_BTR2_ADDHLD_Pos (4U)
10944#define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
10945#define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
10946#define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
10947#define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
10948#define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
10949#define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
10950
10951#define FMC_BTR2_DATAST_Pos (8U)
10952#define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
10953#define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
10954#define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
10955#define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
10956#define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
10957#define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
10958#define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
10959#define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
10960#define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
10961#define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
10962
10963#define FMC_BTR2_BUSTURN_Pos (16U)
10964#define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
10965#define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
10966#define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
10967#define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
10968#define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
10969#define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
10970
10971#define FMC_BTR2_CLKDIV_Pos (20U)
10972#define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
10973#define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
10974#define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
10975#define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
10976#define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
10977#define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
10978
10979#define FMC_BTR2_DATLAT_Pos (24U)
10980#define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
10981#define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
10982#define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
10983#define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
10984#define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
10985#define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
10986
10987#define FMC_BTR2_ACCMOD_Pos (28U)
10988#define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
10989#define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
10990#define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
10991#define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
10992
10993/******************* Bit definition for FMC_BTR3 register *******************/
10994#define FMC_BTR3_ADDSET_Pos (0U)
10995#define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
10996#define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
10997#define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
10998#define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
10999#define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
11000#define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
11001
11002#define FMC_BTR3_ADDHLD_Pos (4U)
11003#define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
11004#define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
11005#define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
11006#define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
11007#define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
11008#define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
11009
11010#define FMC_BTR3_DATAST_Pos (8U)
11011#define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
11012#define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
11013#define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
11014#define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
11015#define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
11016#define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
11017#define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
11018#define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
11019#define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
11020#define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
11021
11022#define FMC_BTR3_BUSTURN_Pos (16U)
11023#define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
11024#define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
11025#define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
11026#define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
11027#define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
11028#define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
11029
11030#define FMC_BTR3_CLKDIV_Pos (20U)
11031#define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
11032#define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
11033#define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
11034#define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
11035#define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
11036#define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
11037
11038#define FMC_BTR3_DATLAT_Pos (24U)
11039#define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
11040#define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
11041#define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
11042#define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
11043#define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
11044#define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
11045
11046#define FMC_BTR3_ACCMOD_Pos (28U)
11047#define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
11048#define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
11049#define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
11050#define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
11051
11052/****************** Bit definition for FMC_BTR4 register *******************/
11053#define FMC_BTR4_ADDSET_Pos (0U)
11054#define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
11055#define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
11056#define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
11057#define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
11058#define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
11059#define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
11060
11061#define FMC_BTR4_ADDHLD_Pos (4U)
11062#define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
11063#define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
11064#define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
11065#define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
11066#define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
11067#define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
11068
11069#define FMC_BTR4_DATAST_Pos (8U)
11070#define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
11071#define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
11072#define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
11073#define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
11074#define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
11075#define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
11076#define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
11077#define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
11078#define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
11079#define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
11080
11081#define FMC_BTR4_BUSTURN_Pos (16U)
11082#define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
11083#define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
11084#define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
11085#define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
11086#define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
11087#define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
11088
11089#define FMC_BTR4_CLKDIV_Pos (20U)
11090#define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
11091#define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
11092#define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
11093#define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
11094#define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
11095#define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
11096
11097#define FMC_BTR4_DATLAT_Pos (24U)
11098#define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
11099#define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
11100#define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
11101#define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
11102#define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
11103#define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
11104
11105#define FMC_BTR4_ACCMOD_Pos (28U)
11106#define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
11107#define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
11108#define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
11109#define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
11110
11111/****************** Bit definition for FMC_BWTR1 register ******************/
11112#define FMC_BWTR1_ADDSET_Pos (0U)
11113#define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
11114#define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
11115#define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
11116#define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
11117#define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
11118#define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
11119
11120#define FMC_BWTR1_ADDHLD_Pos (4U)
11121#define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
11122#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
11123#define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
11124#define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
11125#define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
11126#define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
11127
11128#define FMC_BWTR1_DATAST_Pos (8U)
11129#define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
11130#define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
11131#define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
11132#define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
11133#define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
11134#define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
11135#define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
11136#define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
11137#define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
11138#define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
11139
11140#define FMC_BWTR1_BUSTURN_Pos (16U)
11141#define FMC_BWTR1_BUSTURN_Msk (0xFU << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
11142#define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
11143#define FMC_BWTR1_BUSTURN_0 (0x1U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
11144#define FMC_BWTR1_BUSTURN_1 (0x2U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
11145#define FMC_BWTR1_BUSTURN_2 (0x4U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
11146#define FMC_BWTR1_BUSTURN_3 (0x8U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
11147
11148#define FMC_BWTR1_ACCMOD_Pos (28U)
11149#define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
11150#define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
11151#define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
11152#define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
11153
11154/****************** Bit definition for FMC_BWTR2 register ******************/
11155#define FMC_BWTR2_ADDSET_Pos (0U)
11156#define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
11157#define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
11158#define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
11159#define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
11160#define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
11161#define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
11162
11163#define FMC_BWTR2_ADDHLD_Pos (4U)
11164#define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
11165#define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
11166#define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
11167#define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
11168#define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
11169#define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
11170
11171#define FMC_BWTR2_DATAST_Pos (8U)
11172#define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
11173#define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
11174#define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
11175#define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
11176#define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
11177#define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
11178#define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
11179#define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
11180#define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
11181#define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
11182
11183#define FMC_BWTR2_BUSTURN_Pos (16U)
11184#define FMC_BWTR2_BUSTURN_Msk (0xFU << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
11185#define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
11186#define FMC_BWTR2_BUSTURN_0 (0x1U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
11187#define FMC_BWTR2_BUSTURN_1 (0x2U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
11188#define FMC_BWTR2_BUSTURN_2 (0x4U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
11189#define FMC_BWTR2_BUSTURN_3 (0x8U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
11190
11191#define FMC_BWTR2_ACCMOD_Pos (28U)
11192#define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
11193#define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
11194#define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
11195#define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
11196
11197/****************** Bit definition for FMC_BWTR3 register ******************/
11198#define FMC_BWTR3_ADDSET_Pos (0U)
11199#define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
11200#define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
11201#define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
11202#define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
11203#define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
11204#define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
11205
11206#define FMC_BWTR3_ADDHLD_Pos (4U)
11207#define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
11208#define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
11209#define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
11210#define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
11211#define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
11212#define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
11213
11214#define FMC_BWTR3_DATAST_Pos (8U)
11215#define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
11216#define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
11217#define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
11218#define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
11219#define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
11220#define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
11221#define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
11222#define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
11223#define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
11224#define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
11225
11226#define FMC_BWTR3_BUSTURN_Pos (16U)
11227#define FMC_BWTR3_BUSTURN_Msk (0xFU << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
11228#define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
11229#define FMC_BWTR3_BUSTURN_0 (0x1U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
11230#define FMC_BWTR3_BUSTURN_1 (0x2U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
11231#define FMC_BWTR3_BUSTURN_2 (0x4U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
11232#define FMC_BWTR3_BUSTURN_3 (0x8U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
11233
11234#define FMC_BWTR3_ACCMOD_Pos (28U)
11235#define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
11236#define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
11237#define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
11238#define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
11239
11240/****************** Bit definition for FMC_BWTR4 register ******************/
11241#define FMC_BWTR4_ADDSET_Pos (0U)
11242#define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
11243#define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
11244#define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
11245#define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
11246#define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
11247#define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
11248
11249#define FMC_BWTR4_ADDHLD_Pos (4U)
11250#define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
11251#define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
11252#define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
11253#define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
11254#define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
11255#define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
11256
11257#define FMC_BWTR4_DATAST_Pos (8U)
11258#define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
11259#define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
11260#define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
11261#define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
11262#define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
11263#define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
11264#define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
11265#define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
11266#define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
11267#define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
11268
11269#define FMC_BWTR4_BUSTURN_Pos (16U)
11270#define FMC_BWTR4_BUSTURN_Msk (0xFU << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
11271#define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
11272#define FMC_BWTR4_BUSTURN_0 (0x1U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
11273#define FMC_BWTR4_BUSTURN_1 (0x2U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
11274#define FMC_BWTR4_BUSTURN_2 (0x4U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
11275#define FMC_BWTR4_BUSTURN_3 (0x8U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
11276
11277#define FMC_BWTR4_ACCMOD_Pos (28U)
11278#define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
11279#define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
11280#define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
11281#define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
11282
11283/****************** Bit definition for FMC_PCR register *******************/
11284#define FMC_PCR_PWAITEN_Pos (1U)
11285#define FMC_PCR_PWAITEN_Msk (0x1U << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
11286#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
11287#define FMC_PCR_PBKEN_Pos (2U)
11288#define FMC_PCR_PBKEN_Msk (0x1U << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
11289#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
11290#define FMC_PCR_PTYP_Pos (3U)
11291#define FMC_PCR_PTYP_Msk (0x1U << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
11292#define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
11293
11294#define FMC_PCR_PWID_Pos (4U)
11295#define FMC_PCR_PWID_Msk (0x3U << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
11296#define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
11297#define FMC_PCR_PWID_0 (0x1U << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
11298#define FMC_PCR_PWID_1 (0x2U << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
11299
11300#define FMC_PCR_ECCEN_Pos (6U)
11301#define FMC_PCR_ECCEN_Msk (0x1U << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
11302#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
11303
11304#define FMC_PCR_TCLR_Pos (9U)
11305#define FMC_PCR_TCLR_Msk (0xFU << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
11306#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
11307#define FMC_PCR_TCLR_0 (0x1U << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
11308#define FMC_PCR_TCLR_1 (0x2U << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
11309#define FMC_PCR_TCLR_2 (0x4U << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
11310#define FMC_PCR_TCLR_3 (0x8U << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
11311
11312#define FMC_PCR_TAR_Pos (13U)
11313#define FMC_PCR_TAR_Msk (0xFU << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
11314#define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
11315#define FMC_PCR_TAR_0 (0x1U << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
11316#define FMC_PCR_TAR_1 (0x2U << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
11317#define FMC_PCR_TAR_2 (0x4U << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
11318#define FMC_PCR_TAR_3 (0x8U << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
11319
11320#define FMC_PCR_ECCPS_Pos (17U)
11321#define FMC_PCR_ECCPS_Msk (0x7U << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
11322#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
11323#define FMC_PCR_ECCPS_0 (0x1U << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
11324#define FMC_PCR_ECCPS_1 (0x2U << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
11325#define FMC_PCR_ECCPS_2 (0x4U << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
11326
11327/******************* Bit definition for FMC_SR register *******************/
11328#define FMC_SR_IRS_Pos (0U)
11329#define FMC_SR_IRS_Msk (0x1U << FMC_SR_IRS_Pos) /*!< 0x00000001 */
11330#define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
11331#define FMC_SR_ILS_Pos (1U)
11332#define FMC_SR_ILS_Msk (0x1U << FMC_SR_ILS_Pos) /*!< 0x00000002 */
11333#define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
11334#define FMC_SR_IFS_Pos (2U)
11335#define FMC_SR_IFS_Msk (0x1U << FMC_SR_IFS_Pos) /*!< 0x00000004 */
11336#define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
11337#define FMC_SR_IREN_Pos (3U)
11338#define FMC_SR_IREN_Msk (0x1U << FMC_SR_IREN_Pos) /*!< 0x00000008 */
11339#define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
11340#define FMC_SR_ILEN_Pos (4U)
11341#define FMC_SR_ILEN_Msk (0x1U << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
11342#define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
11343#define FMC_SR_IFEN_Pos (5U)
11344#define FMC_SR_IFEN_Msk (0x1U << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
11345#define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
11346#define FMC_SR_FEMPT_Pos (6U)
11347#define FMC_SR_FEMPT_Msk (0x1U << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
11348#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
11349
11350/****************** Bit definition for FMC_PMEM register ******************/
11351#define FMC_PMEM_MEMSET2_Pos (0U)
11352#define FMC_PMEM_MEMSET2_Msk (0xFFU << FMC_PMEM_MEMSET2_Pos) /*!< 0x000000FF */
11353#define FMC_PMEM_MEMSET2 FMC_PMEM_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
11354#define FMC_PMEM_MEMSET2_0 (0x01U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000001 */
11355#define FMC_PMEM_MEMSET2_1 (0x02U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000002 */
11356#define FMC_PMEM_MEMSET2_2 (0x04U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000004 */
11357#define FMC_PMEM_MEMSET2_3 (0x08U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000008 */
11358#define FMC_PMEM_MEMSET2_4 (0x10U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000010 */
11359#define FMC_PMEM_MEMSET2_5 (0x20U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000020 */
11360#define FMC_PMEM_MEMSET2_6 (0x40U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000040 */
11361#define FMC_PMEM_MEMSET2_7 (0x80U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000080 */
11362
11363#define FMC_PMEM_MEMWAIT2_Pos (8U)
11364#define FMC_PMEM_MEMWAIT2_Msk (0xFFU << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x0000FF00 */
11365#define FMC_PMEM_MEMWAIT2 FMC_PMEM_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
11366#define FMC_PMEM_MEMWAIT2_0 (0x01U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000100 */
11367#define FMC_PMEM_MEMWAIT2_1 (0x02U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000200 */
11368#define FMC_PMEM_MEMWAIT2_2 (0x04U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000400 */
11369#define FMC_PMEM_MEMWAIT2_3 (0x08U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000800 */
11370#define FMC_PMEM_MEMWAIT2_4 (0x10U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00001000 */
11371#define FMC_PMEM_MEMWAIT2_5 (0x20U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00002000 */
11372#define FMC_PMEM_MEMWAIT2_6 (0x40U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00004000 */
11373#define FMC_PMEM_MEMWAIT2_7 (0x80U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00008000 */
11374
11375#define FMC_PMEM_MEMHOLD2_Pos (16U)
11376#define FMC_PMEM_MEMHOLD2_Msk (0xFFU << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00FF0000 */
11377#define FMC_PMEM_MEMHOLD2 FMC_PMEM_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
11378#define FMC_PMEM_MEMHOLD2_0 (0x01U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00010000 */
11379#define FMC_PMEM_MEMHOLD2_1 (0x02U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00020000 */
11380#define FMC_PMEM_MEMHOLD2_2 (0x04U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00040000 */
11381#define FMC_PMEM_MEMHOLD2_3 (0x08U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00080000 */
11382#define FMC_PMEM_MEMHOLD2_4 (0x10U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00100000 */
11383#define FMC_PMEM_MEMHOLD2_5 (0x20U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00200000 */
11384#define FMC_PMEM_MEMHOLD2_6 (0x40U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00400000 */
11385#define FMC_PMEM_MEMHOLD2_7 (0x80U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00800000 */
11386
11387#define FMC_PMEM_MEMHIZ2_Pos (24U)
11388#define FMC_PMEM_MEMHIZ2_Msk (0xFFU << FMC_PMEM_MEMHIZ2_Pos) /*!< 0xFF000000 */
11389#define FMC_PMEM_MEMHIZ2 FMC_PMEM_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
11390#define FMC_PMEM_MEMHIZ2_0 (0x01U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x01000000 */
11391#define FMC_PMEM_MEMHIZ2_1 (0x02U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x02000000 */
11392#define FMC_PMEM_MEMHIZ2_2 (0x04U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x04000000 */
11393#define FMC_PMEM_MEMHIZ2_3 (0x08U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x08000000 */
11394#define FMC_PMEM_MEMHIZ2_4 (0x10U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x10000000 */
11395#define FMC_PMEM_MEMHIZ2_5 (0x20U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x20000000 */
11396#define FMC_PMEM_MEMHIZ2_6 (0x40U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x40000000 */
11397#define FMC_PMEM_MEMHIZ2_7 (0x80U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x80000000 */
11398
11399/****************** Bit definition for FMC_PATT register ******************/
11400#define FMC_PATT_ATTSET2_Pos (0U)
11401#define FMC_PATT_ATTSET2_Msk (0xFFU << FMC_PATT_ATTSET2_Pos) /*!< 0x000000FF */
11402#define FMC_PATT_ATTSET2 FMC_PATT_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
11403#define FMC_PATT_ATTSET2_0 (0x01U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000001 */
11404#define FMC_PATT_ATTSET2_1 (0x02U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000002 */
11405#define FMC_PATT_ATTSET2_2 (0x04U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000004 */
11406#define FMC_PATT_ATTSET2_3 (0x08U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000008 */
11407#define FMC_PATT_ATTSET2_4 (0x10U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000010 */
11408#define FMC_PATT_ATTSET2_5 (0x20U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000020 */
11409#define FMC_PATT_ATTSET2_6 (0x40U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000040 */
11410#define FMC_PATT_ATTSET2_7 (0x80U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000080 */
11411
11412#define FMC_PATT_ATTWAIT2_Pos (8U)
11413#define FMC_PATT_ATTWAIT2_Msk (0xFFU << FMC_PATT_ATTWAIT2_Pos) /*!< 0x0000FF00 */
11414#define FMC_PATT_ATTWAIT2 FMC_PATT_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
11415#define FMC_PATT_ATTWAIT2_0 (0x01U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000100 */
11416#define FMC_PATT_ATTWAIT2_1 (0x02U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000200 */
11417#define FMC_PATT_ATTWAIT2_2 (0x04U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000400 */
11418#define FMC_PATT_ATTWAIT2_3 (0x08U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000800 */
11419#define FMC_PATT_ATTWAIT2_4 (0x10U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00001000 */
11420#define FMC_PATT_ATTWAIT2_5 (0x20U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00002000 */
11421#define FMC_PATT_ATTWAIT2_6 (0x40U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00004000 */
11422#define FMC_PATT_ATTWAIT2_7 (0x80U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00008000 */
11423
11424#define FMC_PATT_ATTHOLD2_Pos (16U)
11425#define FMC_PATT_ATTHOLD2_Msk (0xFFU << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00FF0000 */
11426#define FMC_PATT_ATTHOLD2 FMC_PATT_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
11427#define FMC_PATT_ATTHOLD2_0 (0x01U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00010000 */
11428#define FMC_PATT_ATTHOLD2_1 (0x02U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00020000 */
11429#define FMC_PATT_ATTHOLD2_2 (0x04U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00040000 */
11430#define FMC_PATT_ATTHOLD2_3 (0x08U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00080000 */
11431#define FMC_PATT_ATTHOLD2_4 (0x10U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00100000 */
11432#define FMC_PATT_ATTHOLD2_5 (0x20U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00200000 */
11433#define FMC_PATT_ATTHOLD2_6 (0x40U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00400000 */
11434#define FMC_PATT_ATTHOLD2_7 (0x80U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00800000 */
11435
11436#define FMC_PATT_ATTHIZ2_Pos (24U)
11437#define FMC_PATT_ATTHIZ2_Msk (0xFFU << FMC_PATT_ATTHIZ2_Pos) /*!< 0xFF000000 */
11438#define FMC_PATT_ATTHIZ2 FMC_PATT_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
11439#define FMC_PATT_ATTHIZ2_0 (0x01U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x01000000 */
11440#define FMC_PATT_ATTHIZ2_1 (0x02U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x02000000 */
11441#define FMC_PATT_ATTHIZ2_2 (0x04U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x04000000 */
11442#define FMC_PATT_ATTHIZ2_3 (0x08U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x08000000 */
11443#define FMC_PATT_ATTHIZ2_4 (0x10U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x10000000 */
11444#define FMC_PATT_ATTHIZ2_5 (0x20U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x20000000 */
11445#define FMC_PATT_ATTHIZ2_6 (0x40U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x40000000 */
11446#define FMC_PATT_ATTHIZ2_7 (0x80U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x80000000 */
11447
11448/****************** Bit definition for FMC_ECCR register ******************/
11449#define FMC_ECCR_ECC2_Pos (0U)
11450#define FMC_ECCR_ECC2_Msk (0xFFFFFFFFU << FMC_ECCR_ECC2_Pos) /*!< 0xFFFFFFFF */
11451#define FMC_ECCR_ECC2 FMC_ECCR_ECC2_Msk /*!<ECC result */
11452
11453/****************** Bit definition for FMC_SDCR1 register ******************/
11454#define FMC_SDCR1_NC_Pos (0U)
11455#define FMC_SDCR1_NC_Msk (0x3U << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */
11456#define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
11457#define FMC_SDCR1_NC_0 (0x1U << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */
11458#define FMC_SDCR1_NC_1 (0x2U << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */
11459
11460#define FMC_SDCR1_NR_Pos (2U)
11461#define FMC_SDCR1_NR_Msk (0x3U << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */
11462#define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
11463#define FMC_SDCR1_NR_0 (0x1U << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */
11464#define FMC_SDCR1_NR_1 (0x2U << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */
11465
11466#define FMC_SDCR1_MWID_Pos (4U)
11467#define FMC_SDCR1_MWID_Msk (0x3U << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */
11468#define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
11469#define FMC_SDCR1_MWID_0 (0x1U << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */
11470#define FMC_SDCR1_MWID_1 (0x2U << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */
11471
11472#define FMC_SDCR1_NB_Pos (6U)
11473#define FMC_SDCR1_NB_Msk (0x1U << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */
11474#define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */
11475
11476#define FMC_SDCR1_CAS_Pos (7U)
11477#define FMC_SDCR1_CAS_Msk (0x3U << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */
11478#define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
11479#define FMC_SDCR1_CAS_0 (0x1U << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */
11480#define FMC_SDCR1_CAS_1 (0x2U << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */
11481
11482#define FMC_SDCR1_WP_Pos (9U)
11483#define FMC_SDCR1_WP_Msk (0x1U << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */
11484#define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */
11485
11486#define FMC_SDCR1_SDCLK_Pos (10U)
11487#define FMC_SDCR1_SDCLK_Msk (0x3U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
11488#define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */
11489#define FMC_SDCR1_SDCLK_0 (0x1U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
11490#define FMC_SDCR1_SDCLK_1 (0x2U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
11491
11492#define FMC_SDCR1_RBURST_Pos (12U)
11493#define FMC_SDCR1_RBURST_Msk (0x1U << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */
11494#define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */
11495
11496#define FMC_SDCR1_RPIPE_Pos (13U)
11497#define FMC_SDCR1_RPIPE_Msk (0x3U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */
11498#define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */
11499#define FMC_SDCR1_RPIPE_0 (0x1U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */
11500#define FMC_SDCR1_RPIPE_1 (0x2U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */
11501
11502/****************** Bit definition for FMC_SDCR2 register ******************/
11503#define FMC_SDCR2_NC_Pos (0U)
11504#define FMC_SDCR2_NC_Msk (0x3U << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */
11505#define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
11506#define FMC_SDCR2_NC_0 (0x1U << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */
11507#define FMC_SDCR2_NC_1 (0x2U << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */
11508
11509#define FMC_SDCR2_NR_Pos (2U)
11510#define FMC_SDCR2_NR_Msk (0x3U << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */
11511#define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
11512#define FMC_SDCR2_NR_0 (0x1U << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */
11513#define FMC_SDCR2_NR_1 (0x2U << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */
11514
11515#define FMC_SDCR2_MWID_Pos (4U)
11516#define FMC_SDCR2_MWID_Msk (0x3U << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */
11517#define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
11518#define FMC_SDCR2_MWID_0 (0x1U << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */
11519#define FMC_SDCR2_MWID_1 (0x2U << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */
11520
11521#define FMC_SDCR2_NB_Pos (6U)
11522#define FMC_SDCR2_NB_Msk (0x1U << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */
11523#define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */
11524
11525#define FMC_SDCR2_CAS_Pos (7U)
11526#define FMC_SDCR2_CAS_Msk (0x3U << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */
11527#define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
11528#define FMC_SDCR2_CAS_0 (0x1U << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */
11529#define FMC_SDCR2_CAS_1 (0x2U << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */
11530
11531#define FMC_SDCR2_WP_Pos (9U)
11532#define FMC_SDCR2_WP_Msk (0x1U << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */
11533#define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */
11534
11535#define FMC_SDCR2_SDCLK_Pos (10U)
11536#define FMC_SDCR2_SDCLK_Msk (0x3U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */
11537#define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */
11538#define FMC_SDCR2_SDCLK_0 (0x1U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */
11539#define FMC_SDCR2_SDCLK_1 (0x2U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */
11540
11541#define FMC_SDCR2_RBURST_Pos (12U)
11542#define FMC_SDCR2_RBURST_Msk (0x1U << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */
11543#define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */
11544
11545#define FMC_SDCR2_RPIPE_Pos (13U)
11546#define FMC_SDCR2_RPIPE_Msk (0x3U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */
11547#define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */
11548#define FMC_SDCR2_RPIPE_0 (0x1U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */
11549#define FMC_SDCR2_RPIPE_1 (0x2U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */
11550
11551/****************** Bit definition for FMC_SDTR1 register ******************/
11552#define FMC_SDTR1_TMRD_Pos (0U)
11553#define FMC_SDTR1_TMRD_Msk (0xFU << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */
11554#define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
11555#define FMC_SDTR1_TMRD_0 (0x1U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */
11556#define FMC_SDTR1_TMRD_1 (0x2U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */
11557#define FMC_SDTR1_TMRD_2 (0x4U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */
11558#define FMC_SDTR1_TMRD_3 (0x8U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */
11559
11560#define FMC_SDTR1_TXSR_Pos (4U)
11561#define FMC_SDTR1_TXSR_Msk (0xFU << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */
11562#define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
11563#define FMC_SDTR1_TXSR_0 (0x1U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */
11564#define FMC_SDTR1_TXSR_1 (0x2U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */
11565#define FMC_SDTR1_TXSR_2 (0x4U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */
11566#define FMC_SDTR1_TXSR_3 (0x8U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */
11567
11568#define FMC_SDTR1_TRAS_Pos (8U)
11569#define FMC_SDTR1_TRAS_Msk (0xFU << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */
11570#define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
11571#define FMC_SDTR1_TRAS_0 (0x1U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */
11572#define FMC_SDTR1_TRAS_1 (0x2U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */
11573#define FMC_SDTR1_TRAS_2 (0x4U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */
11574#define FMC_SDTR1_TRAS_3 (0x8U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */
11575
11576#define FMC_SDTR1_TRC_Pos (12U)
11577#define FMC_SDTR1_TRC_Msk (0xFU << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */
11578#define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
11579#define FMC_SDTR1_TRC_0 (0x1U << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */
11580#define FMC_SDTR1_TRC_1 (0x2U << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */
11581#define FMC_SDTR1_TRC_2 (0x4U << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */
11582
11583#define FMC_SDTR1_TWR_Pos (16U)
11584#define FMC_SDTR1_TWR_Msk (0xFU << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
11585#define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
11586#define FMC_SDTR1_TWR_0 (0x1U << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
11587#define FMC_SDTR1_TWR_1 (0x2U << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
11588#define FMC_SDTR1_TWR_2 (0x4U << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
11589
11590#define FMC_SDTR1_TRP_Pos (20U)
11591#define FMC_SDTR1_TRP_Msk (0xFU << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */
11592#define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
11593#define FMC_SDTR1_TRP_0 (0x1U << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */
11594#define FMC_SDTR1_TRP_1 (0x2U << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */
11595#define FMC_SDTR1_TRP_2 (0x4U << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */
11596
11597#define FMC_SDTR1_TRCD_Pos (24U)
11598#define FMC_SDTR1_TRCD_Msk (0xFU << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
11599#define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
11600#define FMC_SDTR1_TRCD_0 (0x1U << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
11601#define FMC_SDTR1_TRCD_1 (0x2U << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
11602#define FMC_SDTR1_TRCD_2 (0x4U << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
11603
11604/****************** Bit definition for FMC_SDTR2 register ******************/
11605#define FMC_SDTR2_TMRD_Pos (0U)
11606#define FMC_SDTR2_TMRD_Msk (0xFU << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */
11607#define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
11608#define FMC_SDTR2_TMRD_0 (0x1U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */
11609#define FMC_SDTR2_TMRD_1 (0x2U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */
11610#define FMC_SDTR2_TMRD_2 (0x4U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */
11611#define FMC_SDTR2_TMRD_3 (0x8U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */
11612
11613#define FMC_SDTR2_TXSR_Pos (4U)
11614#define FMC_SDTR2_TXSR_Msk (0xFU << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */
11615#define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
11616#define FMC_SDTR2_TXSR_0 (0x1U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */
11617#define FMC_SDTR2_TXSR_1 (0x2U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */
11618#define FMC_SDTR2_TXSR_2 (0x4U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */
11619#define FMC_SDTR2_TXSR_3 (0x8U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */
11620
11621#define FMC_SDTR2_TRAS_Pos (8U)
11622#define FMC_SDTR2_TRAS_Msk (0xFU << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
11623#define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
11624#define FMC_SDTR2_TRAS_0 (0x1U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
11625#define FMC_SDTR2_TRAS_1 (0x2U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
11626#define FMC_SDTR2_TRAS_2 (0x4U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
11627#define FMC_SDTR2_TRAS_3 (0x8U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
11628
11629#define FMC_SDTR2_TRC_Pos (12U)
11630#define FMC_SDTR2_TRC_Msk (0xFU << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
11631#define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
11632#define FMC_SDTR2_TRC_0 (0x1U << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
11633#define FMC_SDTR2_TRC_1 (0x2U << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
11634#define FMC_SDTR2_TRC_2 (0x4U << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
11635
11636#define FMC_SDTR2_TWR_Pos (16U)
11637#define FMC_SDTR2_TWR_Msk (0xFU << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
11638#define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
11639#define FMC_SDTR2_TWR_0 (0x1U << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
11640#define FMC_SDTR2_TWR_1 (0x2U << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
11641#define FMC_SDTR2_TWR_2 (0x4U << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
11642
11643#define FMC_SDTR2_TRP_Pos (20U)
11644#define FMC_SDTR2_TRP_Msk (0xFU << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */
11645#define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
11646#define FMC_SDTR2_TRP_0 (0x1U << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */
11647#define FMC_SDTR2_TRP_1 (0x2U << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */
11648#define FMC_SDTR2_TRP_2 (0x4U << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */
11649
11650#define FMC_SDTR2_TRCD_Pos (24U)
11651#define FMC_SDTR2_TRCD_Msk (0xFU << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */
11652#define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
11653#define FMC_SDTR2_TRCD_0 (0x1U << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */
11654#define FMC_SDTR2_TRCD_1 (0x2U << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */
11655#define FMC_SDTR2_TRCD_2 (0x4U << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */
11656
11657/****************** Bit definition for FMC_SDCMR register ******************/
11658#define FMC_SDCMR_MODE_Pos (0U)
11659#define FMC_SDCMR_MODE_Msk (0x7U << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
11660#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
11661#define FMC_SDCMR_MODE_0 (0x1U << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
11662#define FMC_SDCMR_MODE_1 (0x2U << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
11663#define FMC_SDCMR_MODE_2 (0x4U << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
11664
11665#define FMC_SDCMR_CTB2_Pos (3U)
11666#define FMC_SDCMR_CTB2_Msk (0x1U << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
11667#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
11668
11669#define FMC_SDCMR_CTB1_Pos (4U)
11670#define FMC_SDCMR_CTB1_Msk (0x1U << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
11671#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
11672
11673#define FMC_SDCMR_NRFS_Pos (5U)
11674#define FMC_SDCMR_NRFS_Msk (0xFU << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
11675#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
11676#define FMC_SDCMR_NRFS_0 (0x1U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
11677#define FMC_SDCMR_NRFS_1 (0x2U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
11678#define FMC_SDCMR_NRFS_2 (0x4U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
11679#define FMC_SDCMR_NRFS_3 (0x8U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
11680
11681#define FMC_SDCMR_MRD_Pos (9U)
11682#define FMC_SDCMR_MRD_Msk (0x1FFFU << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
11683#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
11684
11685/****************** Bit definition for FMC_SDRTR register ******************/
11686#define FMC_SDRTR_CRE_Pos (0U)
11687#define FMC_SDRTR_CRE_Msk (0x1U << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
11688#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
11689
11690#define FMC_SDRTR_COUNT_Pos (1U)
11691#define FMC_SDRTR_COUNT_Msk (0x1FFFU << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
11692#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
11693
11694#define FMC_SDRTR_REIE_Pos (14U)
11695#define FMC_SDRTR_REIE_Msk (0x1U << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
11696#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
11697
11698/****************** Bit definition for FMC_SDSR register ******************/
11699#define FMC_SDSR_RE_Pos (0U)
11700#define FMC_SDSR_RE_Msk (0x1U << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
11701#define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
11702
11703#define FMC_SDSR_MODES1_Pos (1U)
11704#define FMC_SDSR_MODES1_Msk (0x3U << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
11705#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
11706#define FMC_SDSR_MODES1_0 (0x1U << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
11707#define FMC_SDSR_MODES1_1 (0x2U << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
11708
11709#define FMC_SDSR_MODES2_Pos (3U)
11710#define FMC_SDSR_MODES2_Msk (0x3U << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
11711#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
11712#define FMC_SDSR_MODES2_0 (0x1U << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
11713#define FMC_SDSR_MODES2_1 (0x2U << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
11714#define FMC_SDSR_BUSY_Pos (5U)
11715#define FMC_SDSR_BUSY_Msk (0x1U << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */
11716#define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */
11717
11718/******************************************************************************/
11719/* */
11720/* General Purpose I/O */
11721/* */
11722/******************************************************************************/
11723/****************** Bits definition for GPIO_MODER register *****************/
11724#define GPIO_MODER_MODE0_Pos (0U)
11725#define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
11726#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
11727#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
11728#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
11729#define GPIO_MODER_MODE1_Pos (2U)
11730#define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
11731#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
11732#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
11733#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
11734#define GPIO_MODER_MODE2_Pos (4U)
11735#define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
11736#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
11737#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
11738#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
11739#define GPIO_MODER_MODE3_Pos (6U)
11740#define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
11741#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
11742#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
11743#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
11744#define GPIO_MODER_MODE4_Pos (8U)
11745#define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
11746#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
11747#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
11748#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
11749#define GPIO_MODER_MODE5_Pos (10U)
11750#define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
11751#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
11752#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
11753#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
11754#define GPIO_MODER_MODE6_Pos (12U)
11755#define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
11756#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
11757#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
11758#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
11759#define GPIO_MODER_MODE7_Pos (14U)
11760#define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
11761#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
11762#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
11763#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
11764#define GPIO_MODER_MODE8_Pos (16U)
11765#define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
11766#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
11767#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
11768#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
11769#define GPIO_MODER_MODE9_Pos (18U)
11770#define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
11771#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
11772#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
11773#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
11774#define GPIO_MODER_MODE10_Pos (20U)
11775#define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
11776#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
11777#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
11778#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
11779#define GPIO_MODER_MODE11_Pos (22U)
11780#define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
11781#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
11782#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
11783#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
11784#define GPIO_MODER_MODE12_Pos (24U)
11785#define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
11786#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
11787#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
11788#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
11789#define GPIO_MODER_MODE13_Pos (26U)
11790#define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
11791#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
11792#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
11793#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
11794#define GPIO_MODER_MODE14_Pos (28U)
11795#define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
11796#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
11797#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
11798#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
11799#define GPIO_MODER_MODE15_Pos (30U)
11800#define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
11801#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
11802#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
11803#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
11804
11805/* Legacy defines */
11806#define GPIO_MODER_MODER0_Pos (0U)
11807#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
11808#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
11809#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
11810#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
11811#define GPIO_MODER_MODER1_Pos (2U)
11812#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
11813#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
11814#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
11815#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
11816#define GPIO_MODER_MODER2_Pos (4U)
11817#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
11818#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
11819#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
11820#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
11821#define GPIO_MODER_MODER3_Pos (6U)
11822#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
11823#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
11824#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
11825#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
11826#define GPIO_MODER_MODER4_Pos (8U)
11827#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
11828#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
11829#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
11830#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
11831#define GPIO_MODER_MODER5_Pos (10U)
11832#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
11833#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
11834#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
11835#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
11836#define GPIO_MODER_MODER6_Pos (12U)
11837#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
11838#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
11839#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
11840#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
11841#define GPIO_MODER_MODER7_Pos (14U)
11842#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
11843#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
11844#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
11845#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
11846#define GPIO_MODER_MODER8_Pos (16U)
11847#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
11848#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
11849#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
11850#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
11851#define GPIO_MODER_MODER9_Pos (18U)
11852#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
11853#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
11854#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
11855#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
11856#define GPIO_MODER_MODER10_Pos (20U)
11857#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
11858#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
11859#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
11860#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
11861#define GPIO_MODER_MODER11_Pos (22U)
11862#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
11863#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
11864#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
11865#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
11866#define GPIO_MODER_MODER12_Pos (24U)
11867#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
11868#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
11869#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
11870#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
11871#define GPIO_MODER_MODER13_Pos (26U)
11872#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
11873#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
11874#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
11875#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
11876#define GPIO_MODER_MODER14_Pos (28U)
11877#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
11878#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
11879#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
11880#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
11881#define GPIO_MODER_MODER15_Pos (30U)
11882#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
11883#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
11884#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
11885#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
11886
11887/****************** Bits definition for GPIO_OTYPER register ****************/
11888#define GPIO_OTYPER_OT0_Pos (0U)
11889#define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
11890#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
11891#define GPIO_OTYPER_OT1_Pos (1U)
11892#define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
11893#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
11894#define GPIO_OTYPER_OT2_Pos (2U)
11895#define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
11896#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
11897#define GPIO_OTYPER_OT3_Pos (3U)
11898#define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
11899#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
11900#define GPIO_OTYPER_OT4_Pos (4U)
11901#define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
11902#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
11903#define GPIO_OTYPER_OT5_Pos (5U)
11904#define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
11905#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
11906#define GPIO_OTYPER_OT6_Pos (6U)
11907#define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
11908#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
11909#define GPIO_OTYPER_OT7_Pos (7U)
11910#define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
11911#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
11912#define GPIO_OTYPER_OT8_Pos (8U)
11913#define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
11914#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
11915#define GPIO_OTYPER_OT9_Pos (9U)
11916#define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
11917#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
11918#define GPIO_OTYPER_OT10_Pos (10U)
11919#define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
11920#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
11921#define GPIO_OTYPER_OT11_Pos (11U)
11922#define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
11923#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
11924#define GPIO_OTYPER_OT12_Pos (12U)
11925#define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
11926#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
11927#define GPIO_OTYPER_OT13_Pos (13U)
11928#define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
11929#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
11930#define GPIO_OTYPER_OT14_Pos (14U)
11931#define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
11932#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
11933#define GPIO_OTYPER_OT15_Pos (15U)
11934#define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
11935#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
11936
11937/* Legacy defines */
11938#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
11939#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
11940#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
11941#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
11942#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
11943#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
11944#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
11945#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
11946#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
11947#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
11948#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
11949#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
11950#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
11951#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
11952#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
11953#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
11954
11955/****************** Bits definition for GPIO_OSPEEDR register ***************/
11956#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
11957#define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
11958#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
11959#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
11960#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
11961#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
11962#define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
11963#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
11964#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
11965#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
11966#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
11967#define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
11968#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
11969#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
11970#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
11971#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
11972#define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
11973#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
11974#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
11975#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
11976#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
11977#define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
11978#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
11979#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
11980#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
11981#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
11982#define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
11983#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
11984#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
11985#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
11986#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
11987#define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
11988#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
11989#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
11990#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
11991#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
11992#define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
11993#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
11994#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
11995#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
11996#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
11997#define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
11998#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
11999#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
12000#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
12001#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
12002#define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
12003#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
12004#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
12005#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
12006#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
12007#define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
12008#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
12009#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
12010#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
12011#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
12012#define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
12013#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
12014#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
12015#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
12016#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
12017#define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
12018#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
12019#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
12020#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
12021#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
12022#define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
12023#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
12024#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
12025#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
12026#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
12027#define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
12028#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
12029#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
12030#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
12031#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
12032#define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
12033#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
12034#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
12035#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
12036
12037/* Legacy defines */
12038#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
12039#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
12040#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
12041#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
12042#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
12043#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
12044#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
12045#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
12046#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
12047#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
12048#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
12049#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
12050#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
12051#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
12052#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
12053#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
12054#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
12055#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
12056#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
12057#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
12058#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
12059#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
12060#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
12061#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
12062#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
12063#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
12064#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
12065#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
12066#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
12067#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
12068#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
12069#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
12070#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
12071#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
12072#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
12073#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
12074#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
12075#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
12076#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
12077#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
12078#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
12079#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
12080#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
12081#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
12082#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
12083#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
12084#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
12085#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
12086
12087/****************** Bits definition for GPIO_PUPDR register *****************/
12088#define GPIO_PUPDR_PUPD0_Pos (0U)
12089#define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
12090#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
12091#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
12092#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
12093#define GPIO_PUPDR_PUPD1_Pos (2U)
12094#define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
12095#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
12096#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
12097#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
12098#define GPIO_PUPDR_PUPD2_Pos (4U)
12099#define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
12100#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
12101#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
12102#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
12103#define GPIO_PUPDR_PUPD3_Pos (6U)
12104#define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
12105#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
12106#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
12107#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
12108#define GPIO_PUPDR_PUPD4_Pos (8U)
12109#define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
12110#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
12111#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
12112#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
12113#define GPIO_PUPDR_PUPD5_Pos (10U)
12114#define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
12115#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
12116#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
12117#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
12118#define GPIO_PUPDR_PUPD6_Pos (12U)
12119#define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
12120#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
12121#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
12122#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
12123#define GPIO_PUPDR_PUPD7_Pos (14U)
12124#define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
12125#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
12126#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
12127#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
12128#define GPIO_PUPDR_PUPD8_Pos (16U)
12129#define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
12130#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
12131#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
12132#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
12133#define GPIO_PUPDR_PUPD9_Pos (18U)
12134#define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
12135#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
12136#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
12137#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
12138#define GPIO_PUPDR_PUPD10_Pos (20U)
12139#define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
12140#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
12141#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
12142#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
12143#define GPIO_PUPDR_PUPD11_Pos (22U)
12144#define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
12145#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
12146#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
12147#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
12148#define GPIO_PUPDR_PUPD12_Pos (24U)
12149#define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
12150#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
12151#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
12152#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
12153#define GPIO_PUPDR_PUPD13_Pos (26U)
12154#define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
12155#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
12156#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
12157#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
12158#define GPIO_PUPDR_PUPD14_Pos (28U)
12159#define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
12160#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
12161#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
12162#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
12163#define GPIO_PUPDR_PUPD15_Pos (30U)
12164#define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
12165#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
12166#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
12167#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
12168
12169/* Legacy defines */
12170#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
12171#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
12172#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
12173#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
12174#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
12175#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
12176#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
12177#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
12178#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
12179#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
12180#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
12181#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
12182#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
12183#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
12184#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
12185#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
12186#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
12187#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
12188#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
12189#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
12190#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
12191#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
12192#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
12193#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
12194#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
12195#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
12196#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
12197#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
12198#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
12199#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
12200#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
12201#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
12202#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
12203#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
12204#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
12205#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
12206#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
12207#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
12208#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
12209#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
12210#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
12211#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
12212#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
12213#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
12214#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
12215#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
12216#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
12217#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
12218
12219/****************** Bits definition for GPIO_IDR register *******************/
12220#define GPIO_IDR_ID0_Pos (0U)
12221#define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
12222#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
12223#define GPIO_IDR_ID1_Pos (1U)
12224#define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
12225#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
12226#define GPIO_IDR_ID2_Pos (2U)
12227#define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
12228#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
12229#define GPIO_IDR_ID3_Pos (3U)
12230#define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
12231#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
12232#define GPIO_IDR_ID4_Pos (4U)
12233#define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
12234#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
12235#define GPIO_IDR_ID5_Pos (5U)
12236#define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
12237#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
12238#define GPIO_IDR_ID6_Pos (6U)
12239#define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
12240#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
12241#define GPIO_IDR_ID7_Pos (7U)
12242#define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
12243#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
12244#define GPIO_IDR_ID8_Pos (8U)
12245#define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
12246#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
12247#define GPIO_IDR_ID9_Pos (9U)
12248#define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
12249#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
12250#define GPIO_IDR_ID10_Pos (10U)
12251#define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
12252#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
12253#define GPIO_IDR_ID11_Pos (11U)
12254#define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
12255#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
12256#define GPIO_IDR_ID12_Pos (12U)
12257#define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
12258#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
12259#define GPIO_IDR_ID13_Pos (13U)
12260#define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
12261#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
12262#define GPIO_IDR_ID14_Pos (14U)
12263#define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
12264#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
12265#define GPIO_IDR_ID15_Pos (15U)
12266#define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
12267#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
12268
12269/* Legacy defines */
12270#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
12271#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
12272#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
12273#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
12274#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
12275#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
12276#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
12277#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
12278#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
12279#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
12280#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
12281#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
12282#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
12283#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
12284#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
12285#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
12286
12287/****************** Bits definition for GPIO_ODR register *******************/
12288#define GPIO_ODR_OD0_Pos (0U)
12289#define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
12290#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
12291#define GPIO_ODR_OD1_Pos (1U)
12292#define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
12293#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
12294#define GPIO_ODR_OD2_Pos (2U)
12295#define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
12296#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
12297#define GPIO_ODR_OD3_Pos (3U)
12298#define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
12299#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
12300#define GPIO_ODR_OD4_Pos (4U)
12301#define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
12302#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
12303#define GPIO_ODR_OD5_Pos (5U)
12304#define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
12305#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
12306#define GPIO_ODR_OD6_Pos (6U)
12307#define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
12308#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
12309#define GPIO_ODR_OD7_Pos (7U)
12310#define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
12311#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
12312#define GPIO_ODR_OD8_Pos (8U)
12313#define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
12314#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
12315#define GPIO_ODR_OD9_Pos (9U)
12316#define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
12317#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
12318#define GPIO_ODR_OD10_Pos (10U)
12319#define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
12320#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
12321#define GPIO_ODR_OD11_Pos (11U)
12322#define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
12323#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
12324#define GPIO_ODR_OD12_Pos (12U)
12325#define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
12326#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
12327#define GPIO_ODR_OD13_Pos (13U)
12328#define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
12329#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
12330#define GPIO_ODR_OD14_Pos (14U)
12331#define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
12332#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
12333#define GPIO_ODR_OD15_Pos (15U)
12334#define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
12335#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
12336/* Legacy defines */
12337#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
12338#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
12339#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
12340#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
12341#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
12342#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
12343#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
12344#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
12345#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
12346#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
12347#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
12348#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
12349#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
12350#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
12351#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
12352#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
12353
12354/****************** Bits definition for GPIO_BSRR register ******************/
12355#define GPIO_BSRR_BS0_Pos (0U)
12356#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
12357#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
12358#define GPIO_BSRR_BS1_Pos (1U)
12359#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
12360#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
12361#define GPIO_BSRR_BS2_Pos (2U)
12362#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
12363#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
12364#define GPIO_BSRR_BS3_Pos (3U)
12365#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
12366#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
12367#define GPIO_BSRR_BS4_Pos (4U)
12368#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
12369#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
12370#define GPIO_BSRR_BS5_Pos (5U)
12371#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
12372#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
12373#define GPIO_BSRR_BS6_Pos (6U)
12374#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
12375#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
12376#define GPIO_BSRR_BS7_Pos (7U)
12377#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
12378#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
12379#define GPIO_BSRR_BS8_Pos (8U)
12380#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
12381#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
12382#define GPIO_BSRR_BS9_Pos (9U)
12383#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
12384#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
12385#define GPIO_BSRR_BS10_Pos (10U)
12386#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
12387#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
12388#define GPIO_BSRR_BS11_Pos (11U)
12389#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
12390#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
12391#define GPIO_BSRR_BS12_Pos (12U)
12392#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
12393#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
12394#define GPIO_BSRR_BS13_Pos (13U)
12395#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
12396#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
12397#define GPIO_BSRR_BS14_Pos (14U)
12398#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
12399#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
12400#define GPIO_BSRR_BS15_Pos (15U)
12401#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
12402#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
12403#define GPIO_BSRR_BR0_Pos (16U)
12404#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
12405#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
12406#define GPIO_BSRR_BR1_Pos (17U)
12407#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
12408#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
12409#define GPIO_BSRR_BR2_Pos (18U)
12410#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
12411#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
12412#define GPIO_BSRR_BR3_Pos (19U)
12413#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
12414#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
12415#define GPIO_BSRR_BR4_Pos (20U)
12416#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
12417#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
12418#define GPIO_BSRR_BR5_Pos (21U)
12419#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
12420#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
12421#define GPIO_BSRR_BR6_Pos (22U)
12422#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
12423#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
12424#define GPIO_BSRR_BR7_Pos (23U)
12425#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
12426#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
12427#define GPIO_BSRR_BR8_Pos (24U)
12428#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
12429#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
12430#define GPIO_BSRR_BR9_Pos (25U)
12431#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
12432#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
12433#define GPIO_BSRR_BR10_Pos (26U)
12434#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
12435#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
12436#define GPIO_BSRR_BR11_Pos (27U)
12437#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
12438#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
12439#define GPIO_BSRR_BR12_Pos (28U)
12440#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
12441#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
12442#define GPIO_BSRR_BR13_Pos (29U)
12443#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
12444#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
12445#define GPIO_BSRR_BR14_Pos (30U)
12446#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
12447#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
12448#define GPIO_BSRR_BR15_Pos (31U)
12449#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
12450#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
12451
12452/* Legacy defines */
12453#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
12454#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
12455#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
12456#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
12457#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
12458#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
12459#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
12460#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
12461#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
12462#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
12463#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
12464#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
12465#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
12466#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
12467#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
12468#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
12469#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
12470#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
12471#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
12472#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
12473#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
12474#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
12475#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
12476#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
12477#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
12478#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
12479#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
12480#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
12481#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
12482#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
12483#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
12484#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
12485/****************** Bit definition for GPIO_LCKR register *********************/
12486#define GPIO_LCKR_LCK0_Pos (0U)
12487#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
12488#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
12489#define GPIO_LCKR_LCK1_Pos (1U)
12490#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
12491#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
12492#define GPIO_LCKR_LCK2_Pos (2U)
12493#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
12494#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
12495#define GPIO_LCKR_LCK3_Pos (3U)
12496#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
12497#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
12498#define GPIO_LCKR_LCK4_Pos (4U)
12499#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
12500#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
12501#define GPIO_LCKR_LCK5_Pos (5U)
12502#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
12503#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
12504#define GPIO_LCKR_LCK6_Pos (6U)
12505#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
12506#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
12507#define GPIO_LCKR_LCK7_Pos (7U)
12508#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
12509#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
12510#define GPIO_LCKR_LCK8_Pos (8U)
12511#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
12512#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
12513#define GPIO_LCKR_LCK9_Pos (9U)
12514#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
12515#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
12516#define GPIO_LCKR_LCK10_Pos (10U)
12517#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
12518#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
12519#define GPIO_LCKR_LCK11_Pos (11U)
12520#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
12521#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
12522#define GPIO_LCKR_LCK12_Pos (12U)
12523#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
12524#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
12525#define GPIO_LCKR_LCK13_Pos (13U)
12526#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
12527#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
12528#define GPIO_LCKR_LCK14_Pos (14U)
12529#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
12530#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
12531#define GPIO_LCKR_LCK15_Pos (15U)
12532#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
12533#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
12534#define GPIO_LCKR_LCKK_Pos (16U)
12535#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
12536#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
12537/****************** Bit definition for GPIO_AFRL register *********************/
12538#define GPIO_AFRL_AFSEL0_Pos (0U)
12539#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
12540#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
12541#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
12542#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
12543#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
12544#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
12545#define GPIO_AFRL_AFSEL1_Pos (4U)
12546#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
12547#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
12548#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
12549#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
12550#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
12551#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
12552#define GPIO_AFRL_AFSEL2_Pos (8U)
12553#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
12554#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
12555#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
12556#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
12557#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
12558#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
12559#define GPIO_AFRL_AFSEL3_Pos (12U)
12560#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
12561#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
12562#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
12563#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
12564#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
12565#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
12566#define GPIO_AFRL_AFSEL4_Pos (16U)
12567#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
12568#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
12569#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
12570#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
12571#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
12572#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
12573#define GPIO_AFRL_AFSEL5_Pos (20U)
12574#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
12575#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
12576#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
12577#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
12578#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
12579#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
12580#define GPIO_AFRL_AFSEL6_Pos (24U)
12581#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
12582#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
12583#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
12584#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
12585#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
12586#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
12587#define GPIO_AFRL_AFSEL7_Pos (28U)
12588#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
12589#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
12590#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
12591#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
12592#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
12593#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
12594
12595/* Legacy defines */
12596#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
12597#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
12598#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
12599#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
12600#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
12601#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
12602#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
12603#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
12604#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
12605#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
12606#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
12607#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
12608#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
12609#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
12610#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
12611#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
12612#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
12613#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
12614#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
12615#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
12616#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
12617#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
12618#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
12619#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
12620#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
12621#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
12622#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
12623#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
12624#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
12625#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
12626#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
12627#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
12628#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
12629#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
12630#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
12631#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
12632#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
12633#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
12634#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
12635#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
12636
12637/****************** Bit definition for GPIO_AFRH register *********************/
12638#define GPIO_AFRH_AFSEL8_Pos (0U)
12639#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
12640#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
12641#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
12642#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
12643#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
12644#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
12645#define GPIO_AFRH_AFSEL9_Pos (4U)
12646#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
12647#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
12648#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
12649#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
12650#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
12651#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
12652#define GPIO_AFRH_AFSEL10_Pos (8U)
12653#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
12654#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
12655#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
12656#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
12657#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
12658#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
12659#define GPIO_AFRH_AFSEL11_Pos (12U)
12660#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
12661#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
12662#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
12663#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
12664#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
12665#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
12666#define GPIO_AFRH_AFSEL12_Pos (16U)
12667#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
12668#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
12669#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
12670#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
12671#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
12672#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
12673#define GPIO_AFRH_AFSEL13_Pos (20U)
12674#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
12675#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
12676#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
12677#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
12678#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
12679#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
12680#define GPIO_AFRH_AFSEL14_Pos (24U)
12681#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
12682#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
12683#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
12684#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
12685#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
12686#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
12687#define GPIO_AFRH_AFSEL15_Pos (28U)
12688#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
12689#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
12690#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
12691#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
12692#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
12693#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
12694
12695/* Legacy defines */
12696#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
12697#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
12698#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
12699#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
12700#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
12701#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
12702#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
12703#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
12704#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
12705#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
12706#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
12707#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
12708#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
12709#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
12710#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
12711#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
12712#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
12713#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
12714#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
12715#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
12716#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
12717#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
12718#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
12719#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
12720#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
12721#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
12722#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
12723#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
12724#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
12725#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
12726#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
12727#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
12728#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
12729#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
12730#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
12731#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
12732#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
12733#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
12734#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
12735#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
12736
12737/****************** Bits definition for GPIO_BRR register ******************/
12738#define GPIO_BRR_BR0_Pos (0U)
12739#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
12740#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
12741#define GPIO_BRR_BR1_Pos (1U)
12742#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
12743#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
12744#define GPIO_BRR_BR2_Pos (2U)
12745#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
12746#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
12747#define GPIO_BRR_BR3_Pos (3U)
12748#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
12749#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
12750#define GPIO_BRR_BR4_Pos (4U)
12751#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
12752#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
12753#define GPIO_BRR_BR5_Pos (5U)
12754#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
12755#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
12756#define GPIO_BRR_BR6_Pos (6U)
12757#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
12758#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
12759#define GPIO_BRR_BR7_Pos (7U)
12760#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
12761#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
12762#define GPIO_BRR_BR8_Pos (8U)
12763#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
12764#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
12765#define GPIO_BRR_BR9_Pos (9U)
12766#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
12767#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
12768#define GPIO_BRR_BR10_Pos (10U)
12769#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
12770#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
12771#define GPIO_BRR_BR11_Pos (11U)
12772#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
12773#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
12774#define GPIO_BRR_BR12_Pos (12U)
12775#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
12776#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
12777#define GPIO_BRR_BR13_Pos (13U)
12778#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
12779#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
12780#define GPIO_BRR_BR14_Pos (14U)
12781#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
12782#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
12783#define GPIO_BRR_BR15_Pos (15U)
12784#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
12785#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
12786
12787
12788/******************************************************************************/
12789/* */
12790/* HASH */
12791/* */
12792/******************************************************************************/
12793/****************** Bits definition for HASH_CR register ********************/
12794#define HASH_CR_INIT_Pos (2U)
12795#define HASH_CR_INIT_Msk (0x1U << HASH_CR_INIT_Pos) /*!< 0x00000004 */
12796#define HASH_CR_INIT HASH_CR_INIT_Msk
12797#define HASH_CR_DMAE_Pos (3U)
12798#define HASH_CR_DMAE_Msk (0x1U << HASH_CR_DMAE_Pos) /*!< 0x00000008 */
12799#define HASH_CR_DMAE HASH_CR_DMAE_Msk
12800#define HASH_CR_DATATYPE_Pos (4U)
12801#define HASH_CR_DATATYPE_Msk (0x3U << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */
12802#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk
12803#define HASH_CR_DATATYPE_0 (0x1U << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */
12804#define HASH_CR_DATATYPE_1 (0x2U << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */
12805#define HASH_CR_MODE_Pos (6U)
12806#define HASH_CR_MODE_Msk (0x1U << HASH_CR_MODE_Pos) /*!< 0x00000040 */
12807#define HASH_CR_MODE HASH_CR_MODE_Msk
12808#define HASH_CR_ALGO_Pos (7U)
12809#define HASH_CR_ALGO_Msk (0x801U << HASH_CR_ALGO_Pos) /*!< 0x00040080 */
12810#define HASH_CR_ALGO HASH_CR_ALGO_Msk
12811#define HASH_CR_ALGO_0 (0x001U << HASH_CR_ALGO_Pos) /*!< 0x00000080 */
12812#define HASH_CR_ALGO_1 (0x800U << HASH_CR_ALGO_Pos) /*!< 0x00040000 */
12813#define HASH_CR_NBW_Pos (8U)
12814#define HASH_CR_NBW_Msk (0xFU << HASH_CR_NBW_Pos) /*!< 0x00000F00 */
12815#define HASH_CR_NBW HASH_CR_NBW_Msk
12816#define HASH_CR_NBW_0 (0x1U << HASH_CR_NBW_Pos) /*!< 0x00000100 */
12817#define HASH_CR_NBW_1 (0x2U << HASH_CR_NBW_Pos) /*!< 0x00000200 */
12818#define HASH_CR_NBW_2 (0x4U << HASH_CR_NBW_Pos) /*!< 0x00000400 */
12819#define HASH_CR_NBW_3 (0x8U << HASH_CR_NBW_Pos) /*!< 0x00000800 */
12820#define HASH_CR_DINNE_Pos (12U)
12821#define HASH_CR_DINNE_Msk (0x1U << HASH_CR_DINNE_Pos) /*!< 0x00001000 */
12822#define HASH_CR_DINNE HASH_CR_DINNE_Msk
12823#define HASH_CR_MDMAT_Pos (13U)
12824#define HASH_CR_MDMAT_Msk (0x1U << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */
12825#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk
12826#define HASH_CR_LKEY_Pos (16U)
12827#define HASH_CR_LKEY_Msk (0x1U << HASH_CR_LKEY_Pos) /*!< 0x00010000 */
12828#define HASH_CR_LKEY HASH_CR_LKEY_Msk
12829
12830/****************** Bits definition for HASH_STR register *******************/
12831#define HASH_STR_NBLW_Pos (0U)
12832#define HASH_STR_NBLW_Msk (0x1FU << HASH_STR_NBLW_Pos) /*!< 0x0000001F */
12833#define HASH_STR_NBLW HASH_STR_NBLW_Msk
12834#define HASH_STR_NBLW_0 (0x01U << HASH_STR_NBLW_Pos) /*!< 0x00000001 */
12835#define HASH_STR_NBLW_1 (0x02U << HASH_STR_NBLW_Pos) /*!< 0x00000002 */
12836#define HASH_STR_NBLW_2 (0x04U << HASH_STR_NBLW_Pos) /*!< 0x00000004 */
12837#define HASH_STR_NBLW_3 (0x08U << HASH_STR_NBLW_Pos) /*!< 0x00000008 */
12838#define HASH_STR_NBLW_4 (0x10U << HASH_STR_NBLW_Pos) /*!< 0x00000010 */
12839#define HASH_STR_DCAL_Pos (8U)
12840#define HASH_STR_DCAL_Msk (0x1U << HASH_STR_DCAL_Pos) /*!< 0x00000100 */
12841#define HASH_STR_DCAL HASH_STR_DCAL_Msk
12842/* Aliases for HASH_STR register */
12843#define HASH_STR_NBW HASH_STR_NBLW
12844#define HASH_STR_NBW_0 HASH_STR_NBLW_0
12845#define HASH_STR_NBW_1 HASH_STR_NBLW_1
12846#define HASH_STR_NBW_2 HASH_STR_NBLW_2
12847#define HASH_STR_NBW_3 HASH_STR_NBLW_3
12848#define HASH_STR_NBW_4 HASH_STR_NBLW_4
12849
12850/****************** Bits definition for HASH_IMR register *******************/
12851#define HASH_IMR_DINIE_Pos (0U)
12852#define HASH_IMR_DINIE_Msk (0x1U << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */
12853#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk
12854#define HASH_IMR_DCIE_Pos (1U)
12855#define HASH_IMR_DCIE_Msk (0x1U << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */
12856#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk
12857/* Aliases for HASH_IMR register */
12858#define HASH_IMR_DINIM HASH_IMR_DINIE
12859#define HASH_IMR_DCIM HASH_IMR_DCIE
12860
12861/****************** Bits definition for HASH_SR register ********************/
12862#define HASH_SR_DINIS_Pos (0U)
12863#define HASH_SR_DINIS_Msk (0x1U << HASH_SR_DINIS_Pos) /*!< 0x00000001 */
12864#define HASH_SR_DINIS HASH_SR_DINIS_Msk
12865#define HASH_SR_DCIS_Pos (1U)
12866#define HASH_SR_DCIS_Msk (0x1U << HASH_SR_DCIS_Pos) /*!< 0x00000002 */
12867#define HASH_SR_DCIS HASH_SR_DCIS_Msk
12868#define HASH_SR_DMAS_Pos (2U)
12869#define HASH_SR_DMAS_Msk (0x1U << HASH_SR_DMAS_Pos) /*!< 0x00000004 */
12870#define HASH_SR_DMAS HASH_SR_DMAS_Msk
12871#define HASH_SR_BUSY_Pos (3U)
12872#define HASH_SR_BUSY_Msk (0x1U << HASH_SR_BUSY_Pos) /*!< 0x00000008 */
12873#define HASH_SR_BUSY HASH_SR_BUSY_Msk
12874
12875/******************************************************************************/
12876/* */
12877/* Inter-integrated Circuit Interface */
12878/* */
12879/******************************************************************************/
12880/******************* Bit definition for I2C_CR1 register ********************/
12881#define I2C_CR1_PE_Pos (0U)
12882#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
12883#define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
12884#define I2C_CR1_SMBUS_Pos (1U)
12885#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
12886#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
12887#define I2C_CR1_SMBTYPE_Pos (3U)
12888#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
12889#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
12890#define I2C_CR1_ENARP_Pos (4U)
12891#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
12892#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
12893#define I2C_CR1_ENPEC_Pos (5U)
12894#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
12895#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
12896#define I2C_CR1_ENGC_Pos (6U)
12897#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
12898#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
12899#define I2C_CR1_NOSTRETCH_Pos (7U)
12900#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
12901#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
12902#define I2C_CR1_START_Pos (8U)
12903#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
12904#define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
12905#define I2C_CR1_STOP_Pos (9U)
12906#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
12907#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
12908#define I2C_CR1_ACK_Pos (10U)
12909#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
12910#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
12911#define I2C_CR1_POS_Pos (11U)
12912#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
12913#define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
12914#define I2C_CR1_PEC_Pos (12U)
12915#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
12916#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
12917#define I2C_CR1_ALERT_Pos (13U)
12918#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
12919#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
12920#define I2C_CR1_SWRST_Pos (15U)
12921#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
12922#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
12923
12924/******************* Bit definition for I2C_CR2 register ********************/
12925#define I2C_CR2_FREQ_Pos (0U)
12926#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
12927#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
12928#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
12929#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
12930#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
12931#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
12932#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
12933#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
12934
12935#define I2C_CR2_ITERREN_Pos (8U)
12936#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
12937#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
12938#define I2C_CR2_ITEVTEN_Pos (9U)
12939#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
12940#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
12941#define I2C_CR2_ITBUFEN_Pos (10U)
12942#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
12943#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
12944#define I2C_CR2_DMAEN_Pos (11U)
12945#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
12946#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
12947#define I2C_CR2_LAST_Pos (12U)
12948#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
12949#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
12950
12951/******************* Bit definition for I2C_OAR1 register *******************/
12952#define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
12953#define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
12954
12955#define I2C_OAR1_ADD0_Pos (0U)
12956#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
12957#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
12958#define I2C_OAR1_ADD1_Pos (1U)
12959#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
12960#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
12961#define I2C_OAR1_ADD2_Pos (2U)
12962#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
12963#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
12964#define I2C_OAR1_ADD3_Pos (3U)
12965#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
12966#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
12967#define I2C_OAR1_ADD4_Pos (4U)
12968#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
12969#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
12970#define I2C_OAR1_ADD5_Pos (5U)
12971#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
12972#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
12973#define I2C_OAR1_ADD6_Pos (6U)
12974#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
12975#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
12976#define I2C_OAR1_ADD7_Pos (7U)
12977#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
12978#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
12979#define I2C_OAR1_ADD8_Pos (8U)
12980#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
12981#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
12982#define I2C_OAR1_ADD9_Pos (9U)
12983#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
12984#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
12985
12986#define I2C_OAR1_ADDMODE_Pos (15U)
12987#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
12988#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
12989
12990/******************* Bit definition for I2C_OAR2 register *******************/
12991#define I2C_OAR2_ENDUAL_Pos (0U)
12992#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
12993#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
12994#define I2C_OAR2_ADD2_Pos (1U)
12995#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
12996#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
12997
12998/******************** Bit definition for I2C_DR register ********************/
12999#define I2C_DR_DR_Pos (0U)
13000#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
13001#define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
13002
13003/******************* Bit definition for I2C_SR1 register ********************/
13004#define I2C_SR1_SB_Pos (0U)
13005#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
13006#define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
13007#define I2C_SR1_ADDR_Pos (1U)
13008#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
13009#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
13010#define I2C_SR1_BTF_Pos (2U)
13011#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
13012#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
13013#define I2C_SR1_ADD10_Pos (3U)
13014#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
13015#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
13016#define I2C_SR1_STOPF_Pos (4U)
13017#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
13018#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
13019#define I2C_SR1_RXNE_Pos (6U)
13020#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
13021#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
13022#define I2C_SR1_TXE_Pos (7U)
13023#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
13024#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
13025#define I2C_SR1_BERR_Pos (8U)
13026#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
13027#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
13028#define I2C_SR1_ARLO_Pos (9U)
13029#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
13030#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
13031#define I2C_SR1_AF_Pos (10U)
13032#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
13033#define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
13034#define I2C_SR1_OVR_Pos (11U)
13035#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
13036#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
13037#define I2C_SR1_PECERR_Pos (12U)
13038#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
13039#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
13040#define I2C_SR1_TIMEOUT_Pos (14U)
13041#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
13042#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
13043#define I2C_SR1_SMBALERT_Pos (15U)
13044#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
13045#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
13046
13047/******************* Bit definition for I2C_SR2 register ********************/
13048#define I2C_SR2_MSL_Pos (0U)
13049#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
13050#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
13051#define I2C_SR2_BUSY_Pos (1U)
13052#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
13053#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
13054#define I2C_SR2_TRA_Pos (2U)
13055#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
13056#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
13057#define I2C_SR2_GENCALL_Pos (4U)
13058#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
13059#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
13060#define I2C_SR2_SMBDEFAULT_Pos (5U)
13061#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
13062#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
13063#define I2C_SR2_SMBHOST_Pos (6U)
13064#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
13065#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
13066#define I2C_SR2_DUALF_Pos (7U)
13067#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
13068#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
13069#define I2C_SR2_PEC_Pos (8U)
13070#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
13071#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
13072
13073/******************* Bit definition for I2C_CCR register ********************/
13074#define I2C_CCR_CCR_Pos (0U)
13075#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
13076#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
13077#define I2C_CCR_DUTY_Pos (14U)
13078#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
13079#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
13080#define I2C_CCR_FS_Pos (15U)
13081#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
13082#define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
13083
13084/****************** Bit definition for I2C_TRISE register *******************/
13085#define I2C_TRISE_TRISE_Pos (0U)
13086#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
13087#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
13088
13089/****************** Bit definition for I2C_FLTR register *******************/
13090#define I2C_FLTR_DNF_Pos (0U)
13091#define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
13092#define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
13093#define I2C_FLTR_ANOFF_Pos (4U)
13094#define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
13095#define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
13096
13097/******************************************************************************/
13098/* */
13099/* Independent WATCHDOG */
13100/* */
13101/******************************************************************************/
13102/******************* Bit definition for IWDG_KR register ********************/
13103#define IWDG_KR_KEY_Pos (0U)
13104#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
13105#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
13106
13107/******************* Bit definition for IWDG_PR register ********************/
13108#define IWDG_PR_PR_Pos (0U)
13109#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
13110#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
13111#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
13112#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
13113#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
13114
13115/******************* Bit definition for IWDG_RLR register *******************/
13116#define IWDG_RLR_RL_Pos (0U)
13117#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
13118#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
13119
13120/******************* Bit definition for IWDG_SR register ********************/
13121#define IWDG_SR_PVU_Pos (0U)
13122#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
13123#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
13124#define IWDG_SR_RVU_Pos (1U)
13125#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
13126#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
13127
13128
13129/******************************************************************************/
13130/* */
13131/* LCD-TFT Display Controller (LTDC) */
13132/* */
13133/******************************************************************************/
13134
13135/******************** Bit definition for LTDC_SSCR register *****************/
13136
13137#define LTDC_SSCR_VSH_Pos (0U)
13138#define LTDC_SSCR_VSH_Msk (0x7FFU << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
13139#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
13140#define LTDC_SSCR_HSW_Pos (16U)
13141#define LTDC_SSCR_HSW_Msk (0xFFFU << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
13142#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
13143
13144/******************** Bit definition for LTDC_BPCR register *****************/
13145
13146#define LTDC_BPCR_AVBP_Pos (0U)
13147#define LTDC_BPCR_AVBP_Msk (0x7FFU << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
13148#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
13149#define LTDC_BPCR_AHBP_Pos (16U)
13150#define LTDC_BPCR_AHBP_Msk (0xFFFU << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
13151#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
13152
13153/******************** Bit definition for LTDC_AWCR register *****************/
13154
13155#define LTDC_AWCR_AAH_Pos (0U)
13156#define LTDC_AWCR_AAH_Msk (0x7FFU << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
13157#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
13158#define LTDC_AWCR_AAW_Pos (16U)
13159#define LTDC_AWCR_AAW_Msk (0xFFFU << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
13160#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
13161
13162/******************** Bit definition for LTDC_TWCR register *****************/
13163
13164#define LTDC_TWCR_TOTALH_Pos (0U)
13165#define LTDC_TWCR_TOTALH_Msk (0x7FFU << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
13166#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
13167#define LTDC_TWCR_TOTALW_Pos (16U)
13168#define LTDC_TWCR_TOTALW_Msk (0xFFFU << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
13169#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
13170
13171/******************** Bit definition for LTDC_GCR register ******************/
13172
13173#define LTDC_GCR_LTDCEN_Pos (0U)
13174#define LTDC_GCR_LTDCEN_Msk (0x1U << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
13175#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
13176#define LTDC_GCR_DBW_Pos (4U)
13177#define LTDC_GCR_DBW_Msk (0x7U << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
13178#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
13179#define LTDC_GCR_DGW_Pos (8U)
13180#define LTDC_GCR_DGW_Msk (0x7U << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
13181#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
13182#define LTDC_GCR_DRW_Pos (12U)
13183#define LTDC_GCR_DRW_Msk (0x7U << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
13184#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
13185#define LTDC_GCR_DEN_Pos (16U)
13186#define LTDC_GCR_DEN_Msk (0x1U << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
13187#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
13188#define LTDC_GCR_PCPOL_Pos (28U)
13189#define LTDC_GCR_PCPOL_Msk (0x1U << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
13190#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
13191#define LTDC_GCR_DEPOL_Pos (29U)
13192#define LTDC_GCR_DEPOL_Msk (0x1U << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
13193#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
13194#define LTDC_GCR_VSPOL_Pos (30U)
13195#define LTDC_GCR_VSPOL_Msk (0x1U << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
13196#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
13197#define LTDC_GCR_HSPOL_Pos (31U)
13198#define LTDC_GCR_HSPOL_Msk (0x1U << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
13199#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
13200
13201/* Legacy defines */
13202#define LTDC_GCR_DTEN LTDC_GCR_DEN
13203
13204/******************** Bit definition for LTDC_SRCR register *****************/
13205
13206#define LTDC_SRCR_IMR_Pos (0U)
13207#define LTDC_SRCR_IMR_Msk (0x1U << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
13208#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
13209#define LTDC_SRCR_VBR_Pos (1U)
13210#define LTDC_SRCR_VBR_Msk (0x1U << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
13211#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
13212
13213/******************** Bit definition for LTDC_BCCR register *****************/
13214
13215#define LTDC_BCCR_BCBLUE_Pos (0U)
13216#define LTDC_BCCR_BCBLUE_Msk (0xFFU << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
13217#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
13218#define LTDC_BCCR_BCGREEN_Pos (8U)
13219#define LTDC_BCCR_BCGREEN_Msk (0xFFU << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
13220#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
13221#define LTDC_BCCR_BCRED_Pos (16U)
13222#define LTDC_BCCR_BCRED_Msk (0xFFU << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
13223#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
13224
13225/******************** Bit definition for LTDC_IER register ******************/
13226
13227#define LTDC_IER_LIE_Pos (0U)
13228#define LTDC_IER_LIE_Msk (0x1U << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
13229#define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
13230#define LTDC_IER_FUIE_Pos (1U)
13231#define LTDC_IER_FUIE_Msk (0x1U << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
13232#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
13233#define LTDC_IER_TERRIE_Pos (2U)
13234#define LTDC_IER_TERRIE_Msk (0x1U << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
13235#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
13236#define LTDC_IER_RRIE_Pos (3U)
13237#define LTDC_IER_RRIE_Msk (0x1U << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
13238#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
13239
13240/******************** Bit definition for LTDC_ISR register ******************/
13241
13242#define LTDC_ISR_LIF_Pos (0U)
13243#define LTDC_ISR_LIF_Msk (0x1U << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
13244#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
13245#define LTDC_ISR_FUIF_Pos (1U)
13246#define LTDC_ISR_FUIF_Msk (0x1U << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
13247#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
13248#define LTDC_ISR_TERRIF_Pos (2U)
13249#define LTDC_ISR_TERRIF_Msk (0x1U << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
13250#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
13251#define LTDC_ISR_RRIF_Pos (3U)
13252#define LTDC_ISR_RRIF_Msk (0x1U << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
13253#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
13254
13255/******************** Bit definition for LTDC_ICR register ******************/
13256
13257#define LTDC_ICR_CLIF_Pos (0U)
13258#define LTDC_ICR_CLIF_Msk (0x1U << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
13259#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
13260#define LTDC_ICR_CFUIF_Pos (1U)
13261#define LTDC_ICR_CFUIF_Msk (0x1U << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
13262#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
13263#define LTDC_ICR_CTERRIF_Pos (2U)
13264#define LTDC_ICR_CTERRIF_Msk (0x1U << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
13265#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
13266#define LTDC_ICR_CRRIF_Pos (3U)
13267#define LTDC_ICR_CRRIF_Msk (0x1U << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
13268#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
13269
13270/******************** Bit definition for LTDC_LIPCR register ****************/
13271
13272#define LTDC_LIPCR_LIPOS_Pos (0U)
13273#define LTDC_LIPCR_LIPOS_Msk (0x7FFU << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
13274#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
13275
13276/******************** Bit definition for LTDC_CPSR register *****************/
13277
13278#define LTDC_CPSR_CYPOS_Pos (0U)
13279#define LTDC_CPSR_CYPOS_Msk (0xFFFFU << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
13280#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
13281#define LTDC_CPSR_CXPOS_Pos (16U)
13282#define LTDC_CPSR_CXPOS_Msk (0xFFFFU << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
13283#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
13284
13285/******************** Bit definition for LTDC_CDSR register *****************/
13286
13287#define LTDC_CDSR_VDES_Pos (0U)
13288#define LTDC_CDSR_VDES_Msk (0x1U << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
13289#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
13290#define LTDC_CDSR_HDES_Pos (1U)
13291#define LTDC_CDSR_HDES_Msk (0x1U << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
13292#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
13293#define LTDC_CDSR_VSYNCS_Pos (2U)
13294#define LTDC_CDSR_VSYNCS_Msk (0x1U << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
13295#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
13296#define LTDC_CDSR_HSYNCS_Pos (3U)
13297#define LTDC_CDSR_HSYNCS_Msk (0x1U << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
13298#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
13299
13300/******************** Bit definition for LTDC_LxCR register *****************/
13301
13302#define LTDC_LxCR_LEN_Pos (0U)
13303#define LTDC_LxCR_LEN_Msk (0x1U << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
13304#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
13305#define LTDC_LxCR_COLKEN_Pos (1U)
13306#define LTDC_LxCR_COLKEN_Msk (0x1U << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
13307#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
13308#define LTDC_LxCR_CLUTEN_Pos (4U)
13309#define LTDC_LxCR_CLUTEN_Msk (0x1U << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
13310#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
13311
13312/******************** Bit definition for LTDC_LxWHPCR register **************/
13313
13314#define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
13315#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
13316#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
13317#define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
13318#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFU << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */
13319#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
13320
13321/******************** Bit definition for LTDC_LxWVPCR register **************/
13322
13323#define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
13324#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
13325#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
13326#define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
13327#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFU << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */
13328#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
13329
13330/******************** Bit definition for LTDC_LxCKCR register ***************/
13331
13332#define LTDC_LxCKCR_CKBLUE_Pos (0U)
13333#define LTDC_LxCKCR_CKBLUE_Msk (0xFFU << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
13334#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
13335#define LTDC_LxCKCR_CKGREEN_Pos (8U)
13336#define LTDC_LxCKCR_CKGREEN_Msk (0xFFU << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
13337#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
13338#define LTDC_LxCKCR_CKRED_Pos (16U)
13339#define LTDC_LxCKCR_CKRED_Msk (0xFFU << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
13340#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
13341
13342/******************** Bit definition for LTDC_LxPFCR register ***************/
13343
13344#define LTDC_LxPFCR_PF_Pos (0U)
13345#define LTDC_LxPFCR_PF_Msk (0x7U << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
13346#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
13347
13348/******************** Bit definition for LTDC_LxCACR register ***************/
13349
13350#define LTDC_LxCACR_CONSTA_Pos (0U)
13351#define LTDC_LxCACR_CONSTA_Msk (0xFFU << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
13352#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
13353
13354/******************** Bit definition for LTDC_LxDCCR register ***************/
13355
13356#define LTDC_LxDCCR_DCBLUE_Pos (0U)
13357#define LTDC_LxDCCR_DCBLUE_Msk (0xFFU << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
13358#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
13359#define LTDC_LxDCCR_DCGREEN_Pos (8U)
13360#define LTDC_LxDCCR_DCGREEN_Msk (0xFFU << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
13361#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
13362#define LTDC_LxDCCR_DCRED_Pos (16U)
13363#define LTDC_LxDCCR_DCRED_Msk (0xFFU << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
13364#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
13365#define LTDC_LxDCCR_DCALPHA_Pos (24U)
13366#define LTDC_LxDCCR_DCALPHA_Msk (0xFFU << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
13367#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
13368
13369/******************** Bit definition for LTDC_LxBFCR register ***************/
13370
13371#define LTDC_LxBFCR_BF2_Pos (0U)
13372#define LTDC_LxBFCR_BF2_Msk (0x7U << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
13373#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
13374#define LTDC_LxBFCR_BF1_Pos (8U)
13375#define LTDC_LxBFCR_BF1_Msk (0x7U << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
13376#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
13377
13378/******************** Bit definition for LTDC_LxCFBAR register **************/
13379
13380#define LTDC_LxCFBAR_CFBADD_Pos (0U)
13381#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
13382#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
13383
13384/******************** Bit definition for LTDC_LxCFBLR register **************/
13385
13386#define LTDC_LxCFBLR_CFBLL_Pos (0U)
13387#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
13388#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
13389#define LTDC_LxCFBLR_CFBP_Pos (16U)
13390#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
13391#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
13392
13393/******************** Bit definition for LTDC_LxCFBLNR register *************/
13394
13395#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
13396#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
13397#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
13398
13399/******************** Bit definition for LTDC_LxCLUTWR register *************/
13400
13401#define LTDC_LxCLUTWR_BLUE_Pos (0U)
13402#define LTDC_LxCLUTWR_BLUE_Msk (0xFFU << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
13403#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
13404#define LTDC_LxCLUTWR_GREEN_Pos (8U)
13405#define LTDC_LxCLUTWR_GREEN_Msk (0xFFU << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
13406#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
13407#define LTDC_LxCLUTWR_RED_Pos (16U)
13408#define LTDC_LxCLUTWR_RED_Msk (0xFFU << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
13409#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
13410#define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
13411#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
13412#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
13413
13414
13415/******************************************************************************/
13416/* */
13417/* Power Control */
13418/* */
13419/******************************************************************************/
13420/******************** Bit definition for PWR_CR register ********************/
13421#define PWR_CR_LPDS_Pos (0U)
13422#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
13423#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
13424#define PWR_CR_PDDS_Pos (1U)
13425#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
13426#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
13427#define PWR_CR_CWUF_Pos (2U)
13428#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
13429#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
13430#define PWR_CR_CSBF_Pos (3U)
13431#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
13432#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
13433#define PWR_CR_PVDE_Pos (4U)
13434#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
13435#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
13436
13437#define PWR_CR_PLS_Pos (5U)
13438#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
13439#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
13440#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
13441#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
13442#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
13443
13444/*!< PVD level configuration */
13445#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
13446#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
13447#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
13448#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
13449#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
13450#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
13451#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
13452#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
13453#define PWR_CR_DBP_Pos (8U)
13454#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
13455#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
13456#define PWR_CR_FPDS_Pos (9U)
13457#define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
13458#define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
13459#define PWR_CR_LPLVDS_Pos (10U)
13460#define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
13461#define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
13462#define PWR_CR_MRLVDS_Pos (11U)
13463#define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
13464#define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main regulator Low Voltage Scaling in Stop mode */
13465#define PWR_CR_ADCDC1_Pos (13U)
13466#define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
13467#define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
13468#define PWR_CR_VOS_Pos (14U)
13469#define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
13470#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
13471#define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
13472#define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
13473#define PWR_CR_ODEN_Pos (16U)
13474#define PWR_CR_ODEN_Msk (0x1U << PWR_CR_ODEN_Pos) /*!< 0x00010000 */
13475#define PWR_CR_ODEN PWR_CR_ODEN_Msk /*!< Over Drive enable */
13476#define PWR_CR_ODSWEN_Pos (17U)
13477#define PWR_CR_ODSWEN_Msk (0x1U << PWR_CR_ODSWEN_Pos) /*!< 0x00020000 */
13478#define PWR_CR_ODSWEN PWR_CR_ODSWEN_Msk /*!< Over Drive switch enabled */
13479#define PWR_CR_UDEN_Pos (18U)
13480#define PWR_CR_UDEN_Msk (0x3U << PWR_CR_UDEN_Pos) /*!< 0x000C0000 */
13481#define PWR_CR_UDEN PWR_CR_UDEN_Msk /*!< Under Drive enable in stop mode */
13482#define PWR_CR_UDEN_0 (0x1U << PWR_CR_UDEN_Pos) /*!< 0x00040000 */
13483#define PWR_CR_UDEN_1 (0x2U << PWR_CR_UDEN_Pos) /*!< 0x00080000 */
13484
13485/* Legacy define */
13486#define PWR_CR_PMODE PWR_CR_VOS
13487#define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
13488#define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
13489
13490/******************* Bit definition for PWR_CSR register ********************/
13491#define PWR_CSR_WUF_Pos (0U)
13492#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
13493#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
13494#define PWR_CSR_SBF_Pos (1U)
13495#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
13496#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
13497#define PWR_CSR_PVDO_Pos (2U)
13498#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
13499#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
13500#define PWR_CSR_BRR_Pos (3U)
13501#define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
13502#define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
13503#define PWR_CSR_WUPP_Pos (7U)
13504#define PWR_CSR_WUPP_Msk (0x1U << PWR_CSR_WUPP_Pos) /*!< 0x00000080 */
13505#define PWR_CSR_WUPP PWR_CSR_WUPP_Msk /*!< WKUP pin Polarity */
13506#define PWR_CSR_EWUP_Pos (8U)
13507#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
13508#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
13509#define PWR_CSR_BRE_Pos (9U)
13510#define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
13511#define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
13512#define PWR_CSR_VOSRDY_Pos (14U)
13513#define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
13514#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
13515#define PWR_CSR_ODRDY_Pos (16U)
13516#define PWR_CSR_ODRDY_Msk (0x1U << PWR_CSR_ODRDY_Pos) /*!< 0x00010000 */
13517#define PWR_CSR_ODRDY PWR_CSR_ODRDY_Msk /*!< Over Drive generator ready */
13518#define PWR_CSR_ODSWRDY_Pos (17U)
13519#define PWR_CSR_ODSWRDY_Msk (0x1U << PWR_CSR_ODSWRDY_Pos) /*!< 0x00020000 */
13520#define PWR_CSR_ODSWRDY PWR_CSR_ODSWRDY_Msk /*!< Over Drive Switch ready */
13521#define PWR_CSR_UDRDY_Pos (18U)
13522#define PWR_CSR_UDRDY_Msk (0x3U << PWR_CSR_UDRDY_Pos) /*!< 0x000C0000 */
13523#define PWR_CSR_UDRDY PWR_CSR_UDRDY_Msk /*!< Under Drive ready */
13524/* Legacy define */
13525#define PWR_CSR_UDSWRDY PWR_CSR_UDRDY
13526
13527/* Legacy define */
13528#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
13529
13530/******************************************************************************/
13531/* */
13532/* QUADSPI */
13533/* */
13534/******************************************************************************/
13535/***************** Bit definition for QUADSPI_CR register *******************/
13536#define QUADSPI_CR_EN_Pos (0U)
13537#define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
13538#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
13539#define QUADSPI_CR_ABORT_Pos (1U)
13540#define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
13541#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
13542#define QUADSPI_CR_DMAEN_Pos (2U)
13543#define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
13544#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
13545#define QUADSPI_CR_TCEN_Pos (3U)
13546#define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
13547#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
13548#define QUADSPI_CR_SSHIFT_Pos (4U)
13549#define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
13550#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< SSHIFT Sample Shift */
13551#define QUADSPI_CR_DFM_Pos (6U)
13552#define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
13553#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
13554#define QUADSPI_CR_FSEL_Pos (7U)
13555#define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
13556#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
13557#define QUADSPI_CR_FTHRES_Pos (8U)
13558#define QUADSPI_CR_FTHRES_Msk (0x1FU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
13559#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
13560#define QUADSPI_CR_FTHRES_0 (0x01U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
13561#define QUADSPI_CR_FTHRES_1 (0x02U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
13562#define QUADSPI_CR_FTHRES_2 (0x04U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
13563#define QUADSPI_CR_FTHRES_3 (0x08U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
13564#define QUADSPI_CR_FTHRES_4 (0x10U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
13565#define QUADSPI_CR_TEIE_Pos (16U)
13566#define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
13567#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
13568#define QUADSPI_CR_TCIE_Pos (17U)
13569#define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
13570#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
13571#define QUADSPI_CR_FTIE_Pos (18U)
13572#define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
13573#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
13574#define QUADSPI_CR_SMIE_Pos (19U)
13575#define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
13576#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
13577#define QUADSPI_CR_TOIE_Pos (20U)
13578#define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
13579#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
13580#define QUADSPI_CR_APMS_Pos (22U)
13581#define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
13582#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
13583#define QUADSPI_CR_PMM_Pos (23U)
13584#define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
13585#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
13586#define QUADSPI_CR_PRESCALER_Pos (24U)
13587#define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
13588#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
13589#define QUADSPI_CR_PRESCALER_0 (0x01U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
13590#define QUADSPI_CR_PRESCALER_1 (0x02U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
13591#define QUADSPI_CR_PRESCALER_2 (0x04U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
13592#define QUADSPI_CR_PRESCALER_3 (0x08U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
13593#define QUADSPI_CR_PRESCALER_4 (0x10U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
13594#define QUADSPI_CR_PRESCALER_5 (0x20U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
13595#define QUADSPI_CR_PRESCALER_6 (0x40U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
13596#define QUADSPI_CR_PRESCALER_7 (0x80U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
13597
13598/***************** Bit definition for QUADSPI_DCR register ******************/
13599#define QUADSPI_DCR_CKMODE_Pos (0U)
13600#define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
13601#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
13602#define QUADSPI_DCR_CSHT_Pos (8U)
13603#define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
13604#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
13605#define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
13606#define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
13607#define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
13608#define QUADSPI_DCR_FSIZE_Pos (16U)
13609#define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
13610#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
13611#define QUADSPI_DCR_FSIZE_0 (0x01U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
13612#define QUADSPI_DCR_FSIZE_1 (0x02U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
13613#define QUADSPI_DCR_FSIZE_2 (0x04U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
13614#define QUADSPI_DCR_FSIZE_3 (0x08U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
13615#define QUADSPI_DCR_FSIZE_4 (0x10U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
13616
13617/****************** Bit definition for QUADSPI_SR register *******************/
13618#define QUADSPI_SR_TEF_Pos (0U)
13619#define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
13620#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
13621#define QUADSPI_SR_TCF_Pos (1U)
13622#define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
13623#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
13624#define QUADSPI_SR_FTF_Pos (2U)
13625#define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
13626#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
13627#define QUADSPI_SR_SMF_Pos (3U)
13628#define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
13629#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
13630#define QUADSPI_SR_TOF_Pos (4U)
13631#define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
13632#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
13633#define QUADSPI_SR_BUSY_Pos (5U)
13634#define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
13635#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
13636#define QUADSPI_SR_FLEVEL_Pos (8U)
13637#define QUADSPI_SR_FLEVEL_Msk (0x3FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
13638#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
13639#define QUADSPI_SR_FLEVEL_0 (0x01U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
13640#define QUADSPI_SR_FLEVEL_1 (0x02U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
13641#define QUADSPI_SR_FLEVEL_2 (0x04U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
13642#define QUADSPI_SR_FLEVEL_3 (0x08U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
13643#define QUADSPI_SR_FLEVEL_4 (0x10U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
13644#define QUADSPI_SR_FLEVEL_5 (0x20U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */
13645
13646/****************** Bit definition for QUADSPI_FCR register ******************/
13647#define QUADSPI_FCR_CTEF_Pos (0U)
13648#define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
13649#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
13650#define QUADSPI_FCR_CTCF_Pos (1U)
13651#define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
13652#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
13653#define QUADSPI_FCR_CSMF_Pos (3U)
13654#define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
13655#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
13656#define QUADSPI_FCR_CTOF_Pos (4U)
13657#define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
13658#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
13659
13660/****************** Bit definition for QUADSPI_DLR register ******************/
13661#define QUADSPI_DLR_DL_Pos (0U)
13662#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
13663#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
13664
13665/****************** Bit definition for QUADSPI_CCR register ******************/
13666#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
13667#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
13668#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
13669#define QUADSPI_CCR_INSTRUCTION_0 (0x01U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
13670#define QUADSPI_CCR_INSTRUCTION_1 (0x02U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
13671#define QUADSPI_CCR_INSTRUCTION_2 (0x04U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
13672#define QUADSPI_CCR_INSTRUCTION_3 (0x08U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
13673#define QUADSPI_CCR_INSTRUCTION_4 (0x10U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
13674#define QUADSPI_CCR_INSTRUCTION_5 (0x20U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
13675#define QUADSPI_CCR_INSTRUCTION_6 (0x40U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
13676#define QUADSPI_CCR_INSTRUCTION_7 (0x80U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
13677#define QUADSPI_CCR_IMODE_Pos (8U)
13678#define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
13679#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
13680#define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
13681#define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
13682#define QUADSPI_CCR_ADMODE_Pos (10U)
13683#define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
13684#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
13685#define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
13686#define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
13687#define QUADSPI_CCR_ADSIZE_Pos (12U)
13688#define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
13689#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
13690#define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
13691#define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
13692#define QUADSPI_CCR_ABMODE_Pos (14U)
13693#define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
13694#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
13695#define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
13696#define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
13697#define QUADSPI_CCR_ABSIZE_Pos (16U)
13698#define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
13699#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
13700#define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
13701#define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
13702#define QUADSPI_CCR_DCYC_Pos (18U)
13703#define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
13704#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
13705#define QUADSPI_CCR_DCYC_0 (0x01U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
13706#define QUADSPI_CCR_DCYC_1 (0x02U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
13707#define QUADSPI_CCR_DCYC_2 (0x04U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
13708#define QUADSPI_CCR_DCYC_3 (0x08U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
13709#define QUADSPI_CCR_DCYC_4 (0x10U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
13710#define QUADSPI_CCR_DMODE_Pos (24U)
13711#define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
13712#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
13713#define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
13714#define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
13715#define QUADSPI_CCR_FMODE_Pos (26U)
13716#define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
13717#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
13718#define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
13719#define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
13720#define QUADSPI_CCR_SIOO_Pos (28U)
13721#define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
13722#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
13723#define QUADSPI_CCR_DHHC_Pos (30U)
13724#define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
13725#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: Delay Half Hclk Cycle */
13726#define QUADSPI_CCR_DDRM_Pos (31U)
13727#define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
13728#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
13729/****************** Bit definition for QUADSPI_AR register *******************/
13730#define QUADSPI_AR_ADDRESS_Pos (0U)
13731#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
13732#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
13733
13734/****************** Bit definition for QUADSPI_ABR register ******************/
13735#define QUADSPI_ABR_ALTERNATE_Pos (0U)
13736#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
13737#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
13738
13739/****************** Bit definition for QUADSPI_DR register *******************/
13740#define QUADSPI_DR_DATA_Pos (0U)
13741#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
13742#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
13743
13744/****************** Bit definition for QUADSPI_PSMKR register ****************/
13745#define QUADSPI_PSMKR_MASK_Pos (0U)
13746#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
13747#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
13748
13749/****************** Bit definition for QUADSPI_PSMAR register ****************/
13750#define QUADSPI_PSMAR_MATCH_Pos (0U)
13751#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
13752#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
13753
13754/****************** Bit definition for QUADSPI_PIR register *****************/
13755#define QUADSPI_PIR_INTERVAL_Pos (0U)
13756#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
13757#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
13758
13759/****************** Bit definition for QUADSPI_LPTR register *****************/
13760#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
13761#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
13762#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
13763
13764/******************************************************************************/
13765/* */
13766/* Reset and Clock Control */
13767/* */
13768/******************************************************************************/
13769/******************** Bit definition for RCC_CR register ********************/
13770#define RCC_CR_HSION_Pos (0U)
13771#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
13772#define RCC_CR_HSION RCC_CR_HSION_Msk
13773#define RCC_CR_HSIRDY_Pos (1U)
13774#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
13775#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
13776
13777#define RCC_CR_HSITRIM_Pos (3U)
13778#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
13779#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
13780#define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
13781#define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
13782#define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
13783#define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
13784#define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
13785
13786#define RCC_CR_HSICAL_Pos (8U)
13787#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
13788#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
13789#define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
13790#define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
13791#define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
13792#define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
13793#define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
13794#define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
13795#define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
13796#define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
13797
13798#define RCC_CR_HSEON_Pos (16U)
13799#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
13800#define RCC_CR_HSEON RCC_CR_HSEON_Msk
13801#define RCC_CR_HSERDY_Pos (17U)
13802#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
13803#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
13804#define RCC_CR_HSEBYP_Pos (18U)
13805#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
13806#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
13807#define RCC_CR_CSSON_Pos (19U)
13808#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
13809#define RCC_CR_CSSON RCC_CR_CSSON_Msk
13810#define RCC_CR_PLLON_Pos (24U)
13811#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
13812#define RCC_CR_PLLON RCC_CR_PLLON_Msk
13813#define RCC_CR_PLLRDY_Pos (25U)
13814#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
13815#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
13816/*
13817 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
13818 */
13819#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
13820
13821#define RCC_CR_PLLI2SON_Pos (26U)
13822#define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
13823#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
13824#define RCC_CR_PLLI2SRDY_Pos (27U)
13825#define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
13826#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
13827/*
13828 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
13829 */
13830#define RCC_PLLSAI_SUPPORT /*!< Support PLLSAI oscillator */
13831
13832#define RCC_CR_PLLSAION_Pos (28U)
13833#define RCC_CR_PLLSAION_Msk (0x1U << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */
13834#define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
13835#define RCC_CR_PLLSAIRDY_Pos (29U)
13836#define RCC_CR_PLLSAIRDY_Msk (0x1U << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */
13837#define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
13838
13839/******************** Bit definition for RCC_PLLCFGR register ***************/
13840#define RCC_PLLCFGR_PLLM_Pos (0U)
13841#define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
13842#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
13843#define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
13844#define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
13845#define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
13846#define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
13847#define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
13848#define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
13849
13850#define RCC_PLLCFGR_PLLN_Pos (6U)
13851#define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
13852#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
13853#define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
13854#define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
13855#define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
13856#define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
13857#define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
13858#define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
13859#define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
13860#define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
13861#define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
13862
13863#define RCC_PLLCFGR_PLLP_Pos (16U)
13864#define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
13865#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
13866#define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
13867#define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
13868
13869#define RCC_PLLCFGR_PLLSRC_Pos (22U)
13870#define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
13871#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
13872#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
13873#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
13874#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
13875#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
13876
13877#define RCC_PLLCFGR_PLLQ_Pos (24U)
13878#define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
13879#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
13880#define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
13881#define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
13882#define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
13883#define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
13884
13885#define RCC_PLLCFGR_PLLR_Pos (28U)
13886#define RCC_PLLCFGR_PLLR_Msk (0x7U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x70000000 */
13887#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
13888#define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x10000000 */
13889#define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
13890#define RCC_PLLCFGR_PLLR_2 (0x4U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
13891
13892/******************** Bit definition for RCC_CFGR register ******************/
13893/*!< SW configuration */
13894#define RCC_CFGR_SW_Pos (0U)
13895#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
13896#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
13897#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
13898#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
13899
13900#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
13901#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
13902#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
13903
13904/*!< SWS configuration */
13905#define RCC_CFGR_SWS_Pos (2U)
13906#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
13907#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
13908#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
13909#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
13910
13911#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
13912#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
13913#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
13914
13915/*!< HPRE configuration */
13916#define RCC_CFGR_HPRE_Pos (4U)
13917#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
13918#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
13919#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
13920#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
13921#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
13922#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
13923
13924#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
13925#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
13926#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
13927#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
13928#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
13929#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
13930#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
13931#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
13932#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
13933
13934/*!< PPRE1 configuration */
13935#define RCC_CFGR_PPRE1_Pos (10U)
13936#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
13937#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
13938#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
13939#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
13940#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
13941
13942#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
13943#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
13944#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
13945#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
13946#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
13947
13948/*!< PPRE2 configuration */
13949#define RCC_CFGR_PPRE2_Pos (13U)
13950#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
13951#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
13952#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
13953#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
13954#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
13955
13956#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
13957#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
13958#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
13959#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
13960#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
13961
13962/*!< RTCPRE configuration */
13963#define RCC_CFGR_RTCPRE_Pos (16U)
13964#define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
13965#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
13966#define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
13967#define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
13968#define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
13969#define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
13970#define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
13971
13972/*!< MCO1 configuration */
13973#define RCC_CFGR_MCO1_Pos (21U)
13974#define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
13975#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
13976#define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
13977#define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
13978
13979#define RCC_CFGR_I2SSRC_Pos (23U)
13980#define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
13981#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
13982
13983#define RCC_CFGR_MCO1PRE_Pos (24U)
13984#define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
13985#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
13986#define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
13987#define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
13988#define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
13989
13990#define RCC_CFGR_MCO2PRE_Pos (27U)
13991#define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
13992#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
13993#define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
13994#define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
13995#define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
13996
13997#define RCC_CFGR_MCO2_Pos (30U)
13998#define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
13999#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
14000#define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
14001#define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
14002
14003/******************** Bit definition for RCC_CIR register *******************/
14004#define RCC_CIR_LSIRDYF_Pos (0U)
14005#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
14006#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
14007#define RCC_CIR_LSERDYF_Pos (1U)
14008#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
14009#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
14010#define RCC_CIR_HSIRDYF_Pos (2U)
14011#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
14012#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
14013#define RCC_CIR_HSERDYF_Pos (3U)
14014#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
14015#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
14016#define RCC_CIR_PLLRDYF_Pos (4U)
14017#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
14018#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
14019#define RCC_CIR_PLLI2SRDYF_Pos (5U)
14020#define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
14021#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
14022
14023#define RCC_CIR_PLLSAIRDYF_Pos (6U)
14024#define RCC_CIR_PLLSAIRDYF_Msk (0x1U << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */
14025#define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
14026#define RCC_CIR_CSSF_Pos (7U)
14027#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
14028#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
14029#define RCC_CIR_LSIRDYIE_Pos (8U)
14030#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
14031#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
14032#define RCC_CIR_LSERDYIE_Pos (9U)
14033#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
14034#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
14035#define RCC_CIR_HSIRDYIE_Pos (10U)
14036#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
14037#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
14038#define RCC_CIR_HSERDYIE_Pos (11U)
14039#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
14040#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
14041#define RCC_CIR_PLLRDYIE_Pos (12U)
14042#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
14043#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
14044#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
14045#define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
14046#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
14047
14048#define RCC_CIR_PLLSAIRDYIE_Pos (14U)
14049#define RCC_CIR_PLLSAIRDYIE_Msk (0x1U << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */
14050#define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
14051#define RCC_CIR_LSIRDYC_Pos (16U)
14052#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
14053#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
14054#define RCC_CIR_LSERDYC_Pos (17U)
14055#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
14056#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
14057#define RCC_CIR_HSIRDYC_Pos (18U)
14058#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
14059#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
14060#define RCC_CIR_HSERDYC_Pos (19U)
14061#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
14062#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
14063#define RCC_CIR_PLLRDYC_Pos (20U)
14064#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
14065#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
14066#define RCC_CIR_PLLI2SRDYC_Pos (21U)
14067#define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
14068#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
14069#define RCC_CIR_PLLSAIRDYC_Pos (22U)
14070#define RCC_CIR_PLLSAIRDYC_Msk (0x1U << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */
14071#define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
14072
14073#define RCC_CIR_CSSC_Pos (23U)
14074#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
14075#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
14076
14077/******************** Bit definition for RCC_AHB1RSTR register **************/
14078#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
14079#define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
14080#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
14081#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
14082#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
14083#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
14084#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
14085#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
14086#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
14087#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
14088#define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
14089#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
14090#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
14091#define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
14092#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
14093#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
14094#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
14095#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
14096#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
14097#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
14098#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
14099#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
14100#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
14101#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
14102#define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
14103#define RCC_AHB1RSTR_GPIOIRST_Msk (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
14104#define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
14105#define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
14106#define RCC_AHB1RSTR_GPIOJRST_Msk (0x1U << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
14107#define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
14108#define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
14109#define RCC_AHB1RSTR_GPIOKRST_Msk (0x1U << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
14110#define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
14111#define RCC_AHB1RSTR_CRCRST_Pos (12U)
14112#define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
14113#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
14114#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
14115#define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
14116#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
14117#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
14118#define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
14119#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
14120#define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
14121#define RCC_AHB1RSTR_DMA2DRST_Msk (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */
14122#define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
14123#define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
14124#define RCC_AHB1RSTR_ETHMACRST_Msk (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
14125#define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
14126#define RCC_AHB1RSTR_OTGHRST_Pos (29U)
14127#define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
14128#define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
14129
14130/******************** Bit definition for RCC_AHB2RSTR register **************/
14131#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
14132#define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
14133#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
14134#define RCC_AHB2RSTR_CRYPRST_Pos (4U)
14135#define RCC_AHB2RSTR_CRYPRST_Msk (0x1U << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
14136#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
14137#define RCC_AHB2RSTR_HASHRST_Pos (5U)
14138#define RCC_AHB2RSTR_HASHRST_Msk (0x1U << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
14139#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
14140 /* maintained for legacy purpose */
14141#define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
14142#define RCC_AHB2RSTR_RNGRST_Pos (6U)
14143#define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
14144#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
14145#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
14146#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
14147#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
14148/******************** Bit definition for RCC_AHB3RSTR register **************/
14149#define RCC_AHB3RSTR_FMCRST_Pos (0U)
14150#define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
14151#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
14152#define RCC_AHB3RSTR_QSPIRST_Pos (1U)
14153#define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000002 */
14154#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
14155
14156
14157/******************** Bit definition for RCC_APB1RSTR register **************/
14158#define RCC_APB1RSTR_TIM2RST_Pos (0U)
14159#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
14160#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
14161#define RCC_APB1RSTR_TIM3RST_Pos (1U)
14162#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
14163#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
14164#define RCC_APB1RSTR_TIM4RST_Pos (2U)
14165#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
14166#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
14167#define RCC_APB1RSTR_TIM5RST_Pos (3U)
14168#define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
14169#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
14170#define RCC_APB1RSTR_TIM6RST_Pos (4U)
14171#define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
14172#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
14173#define RCC_APB1RSTR_TIM7RST_Pos (5U)
14174#define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
14175#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
14176#define RCC_APB1RSTR_TIM12RST_Pos (6U)
14177#define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
14178#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
14179#define RCC_APB1RSTR_TIM13RST_Pos (7U)
14180#define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
14181#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
14182#define RCC_APB1RSTR_TIM14RST_Pos (8U)
14183#define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
14184#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
14185#define RCC_APB1RSTR_WWDGRST_Pos (11U)
14186#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
14187#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
14188#define RCC_APB1RSTR_SPI2RST_Pos (14U)
14189#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
14190#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
14191#define RCC_APB1RSTR_SPI3RST_Pos (15U)
14192#define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
14193#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
14194#define RCC_APB1RSTR_USART2RST_Pos (17U)
14195#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
14196#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
14197#define RCC_APB1RSTR_USART3RST_Pos (18U)
14198#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
14199#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
14200#define RCC_APB1RSTR_UART4RST_Pos (19U)
14201#define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
14202#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
14203#define RCC_APB1RSTR_UART5RST_Pos (20U)
14204#define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
14205#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
14206#define RCC_APB1RSTR_I2C1RST_Pos (21U)
14207#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
14208#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
14209#define RCC_APB1RSTR_I2C2RST_Pos (22U)
14210#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
14211#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
14212#define RCC_APB1RSTR_I2C3RST_Pos (23U)
14213#define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
14214#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
14215#define RCC_APB1RSTR_CAN1RST_Pos (25U)
14216#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
14217#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
14218#define RCC_APB1RSTR_CAN2RST_Pos (26U)
14219#define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
14220#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
14221#define RCC_APB1RSTR_PWRRST_Pos (28U)
14222#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
14223#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
14224#define RCC_APB1RSTR_DACRST_Pos (29U)
14225#define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
14226#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
14227#define RCC_APB1RSTR_UART7RST_Pos (30U)
14228#define RCC_APB1RSTR_UART7RST_Msk (0x1U << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
14229#define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
14230#define RCC_APB1RSTR_UART8RST_Pos (31U)
14231#define RCC_APB1RSTR_UART8RST_Msk (0x1U << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
14232#define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
14233
14234/******************** Bit definition for RCC_APB2RSTR register **************/
14235#define RCC_APB2RSTR_TIM1RST_Pos (0U)
14236#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
14237#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
14238#define RCC_APB2RSTR_TIM8RST_Pos (1U)
14239#define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
14240#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
14241#define RCC_APB2RSTR_USART1RST_Pos (4U)
14242#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
14243#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
14244#define RCC_APB2RSTR_USART6RST_Pos (5U)
14245#define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
14246#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
14247#define RCC_APB2RSTR_ADCRST_Pos (8U)
14248#define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
14249#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
14250#define RCC_APB2RSTR_SDIORST_Pos (11U)
14251#define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
14252#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
14253#define RCC_APB2RSTR_SPI1RST_Pos (12U)
14254#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
14255#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
14256#define RCC_APB2RSTR_SPI4RST_Pos (13U)
14257#define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
14258#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
14259#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
14260#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
14261#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
14262#define RCC_APB2RSTR_TIM9RST_Pos (16U)
14263#define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
14264#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
14265#define RCC_APB2RSTR_TIM10RST_Pos (17U)
14266#define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
14267#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
14268#define RCC_APB2RSTR_TIM11RST_Pos (18U)
14269#define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
14270#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
14271#define RCC_APB2RSTR_SPI5RST_Pos (20U)
14272#define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
14273#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
14274#define RCC_APB2RSTR_SPI6RST_Pos (21U)
14275#define RCC_APB2RSTR_SPI6RST_Msk (0x1U << RCC_APB2RSTR_SPI6RST_Pos) /*!< 0x00200000 */
14276#define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
14277#define RCC_APB2RSTR_SAI1RST_Pos (22U)
14278#define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
14279#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
14280#define RCC_APB2RSTR_LTDCRST_Pos (26U)
14281#define RCC_APB2RSTR_LTDCRST_Msk (0x1U << RCC_APB2RSTR_LTDCRST_Pos) /*!< 0x04000000 */
14282#define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk
14283#define RCC_APB2RSTR_DSIRST_Pos (27U)
14284#define RCC_APB2RSTR_DSIRST_Msk (0x1U << RCC_APB2RSTR_DSIRST_Pos) /*!< 0x08000000 */
14285#define RCC_APB2RSTR_DSIRST RCC_APB2RSTR_DSIRST_Msk
14286
14287/* Old SPI1RST bit definition, maintained for legacy purpose */
14288#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
14289
14290/******************** Bit definition for RCC_AHB1ENR register ***************/
14291#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
14292#define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
14293#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
14294#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
14295#define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
14296#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
14297#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
14298#define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
14299#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
14300#define RCC_AHB1ENR_GPIODEN_Pos (3U)
14301#define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
14302#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
14303#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
14304#define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
14305#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
14306#define RCC_AHB1ENR_GPIOFEN_Pos (5U)
14307#define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
14308#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
14309#define RCC_AHB1ENR_GPIOGEN_Pos (6U)
14310#define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
14311#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
14312#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
14313#define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
14314#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
14315#define RCC_AHB1ENR_GPIOIEN_Pos (8U)
14316#define RCC_AHB1ENR_GPIOIEN_Msk (0x1U << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */
14317#define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
14318#define RCC_AHB1ENR_GPIOJEN_Pos (9U)
14319#define RCC_AHB1ENR_GPIOJEN_Msk (0x1U << RCC_AHB1ENR_GPIOJEN_Pos) /*!< 0x00000200 */
14320#define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
14321#define RCC_AHB1ENR_GPIOKEN_Pos (10U)
14322#define RCC_AHB1ENR_GPIOKEN_Msk (0x1U << RCC_AHB1ENR_GPIOKEN_Pos) /*!< 0x00000400 */
14323#define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
14324#define RCC_AHB1ENR_CRCEN_Pos (12U)
14325#define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
14326#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
14327#define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
14328#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
14329#define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
14330#define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
14331#define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1U << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
14332#define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
14333#define RCC_AHB1ENR_DMA1EN_Pos (21U)
14334#define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
14335#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
14336#define RCC_AHB1ENR_DMA2EN_Pos (22U)
14337#define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
14338#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
14339#define RCC_AHB1ENR_DMA2DEN_Pos (23U)
14340#define RCC_AHB1ENR_DMA2DEN_Msk (0x1U << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00800000 */
14341#define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
14342#define RCC_AHB1ENR_ETHMACEN_Pos (25U)
14343#define RCC_AHB1ENR_ETHMACEN_Msk (0x1U << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */
14344#define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
14345#define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
14346#define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
14347#define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
14348#define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
14349#define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
14350#define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
14351#define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
14352#define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
14353#define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
14354#define RCC_AHB1ENR_OTGHSEN_Pos (29U)
14355#define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
14356#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
14357#define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
14358#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
14359#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
14360/******************** Bit definition for RCC_AHB2ENR register ***************/
14361/*
14362 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
14363 */
14364#define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
14365
14366#define RCC_AHB2ENR_DCMIEN_Pos (0U)
14367#define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
14368#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
14369#define RCC_AHB2ENR_CRYPEN_Pos (4U)
14370#define RCC_AHB2ENR_CRYPEN_Msk (0x1U << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
14371#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
14372#define RCC_AHB2ENR_HASHEN_Pos (5U)
14373#define RCC_AHB2ENR_HASHEN_Msk (0x1U << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
14374#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
14375#define RCC_AHB2ENR_RNGEN_Pos (6U)
14376#define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
14377#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
14378#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
14379#define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
14380#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
14381
14382/******************** Bit definition for RCC_AHB3ENR register ***************/
14383/*
14384 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
14385 */
14386#define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
14387
14388#define RCC_AHB3ENR_FMCEN_Pos (0U)
14389#define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
14390#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
14391#define RCC_AHB3ENR_QSPIEN_Pos (1U)
14392#define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000002 */
14393#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
14394
14395/******************** Bit definition for RCC_APB1ENR register ***************/
14396#define RCC_APB1ENR_TIM2EN_Pos (0U)
14397#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
14398#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
14399#define RCC_APB1ENR_TIM3EN_Pos (1U)
14400#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
14401#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
14402#define RCC_APB1ENR_TIM4EN_Pos (2U)
14403#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
14404#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
14405#define RCC_APB1ENR_TIM5EN_Pos (3U)
14406#define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
14407#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
14408#define RCC_APB1ENR_TIM6EN_Pos (4U)
14409#define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
14410#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
14411#define RCC_APB1ENR_TIM7EN_Pos (5U)
14412#define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
14413#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
14414#define RCC_APB1ENR_TIM12EN_Pos (6U)
14415#define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
14416#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
14417#define RCC_APB1ENR_TIM13EN_Pos (7U)
14418#define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
14419#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
14420#define RCC_APB1ENR_TIM14EN_Pos (8U)
14421#define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
14422#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
14423#define RCC_APB1ENR_WWDGEN_Pos (11U)
14424#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
14425#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
14426#define RCC_APB1ENR_SPI2EN_Pos (14U)
14427#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
14428#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
14429#define RCC_APB1ENR_SPI3EN_Pos (15U)
14430#define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
14431#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
14432#define RCC_APB1ENR_USART2EN_Pos (17U)
14433#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
14434#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
14435#define RCC_APB1ENR_USART3EN_Pos (18U)
14436#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
14437#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
14438#define RCC_APB1ENR_UART4EN_Pos (19U)
14439#define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
14440#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
14441#define RCC_APB1ENR_UART5EN_Pos (20U)
14442#define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
14443#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
14444#define RCC_APB1ENR_I2C1EN_Pos (21U)
14445#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
14446#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
14447#define RCC_APB1ENR_I2C2EN_Pos (22U)
14448#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
14449#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
14450#define RCC_APB1ENR_I2C3EN_Pos (23U)
14451#define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
14452#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
14453#define RCC_APB1ENR_CAN1EN_Pos (25U)
14454#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
14455#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
14456#define RCC_APB1ENR_CAN2EN_Pos (26U)
14457#define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
14458#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
14459#define RCC_APB1ENR_PWREN_Pos (28U)
14460#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
14461#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
14462#define RCC_APB1ENR_DACEN_Pos (29U)
14463#define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
14464#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
14465#define RCC_APB1ENR_UART7EN_Pos (30U)
14466#define RCC_APB1ENR_UART7EN_Msk (0x1U << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */
14467#define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
14468#define RCC_APB1ENR_UART8EN_Pos (31U)
14469#define RCC_APB1ENR_UART8EN_Msk (0x1U << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */
14470#define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
14471
14472/******************** Bit definition for RCC_APB2ENR register ***************/
14473#define RCC_APB2ENR_TIM1EN_Pos (0U)
14474#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
14475#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
14476#define RCC_APB2ENR_TIM8EN_Pos (1U)
14477#define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
14478#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
14479#define RCC_APB2ENR_USART1EN_Pos (4U)
14480#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
14481#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
14482#define RCC_APB2ENR_USART6EN_Pos (5U)
14483#define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
14484#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
14485#define RCC_APB2ENR_ADC1EN_Pos (8U)
14486#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
14487#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
14488#define RCC_APB2ENR_ADC2EN_Pos (9U)
14489#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
14490#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
14491#define RCC_APB2ENR_ADC3EN_Pos (10U)
14492#define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
14493#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
14494#define RCC_APB2ENR_SDIOEN_Pos (11U)
14495#define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
14496#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
14497#define RCC_APB2ENR_SPI1EN_Pos (12U)
14498#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
14499#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
14500#define RCC_APB2ENR_SPI4EN_Pos (13U)
14501#define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
14502#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
14503#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
14504#define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
14505#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
14506#define RCC_APB2ENR_TIM9EN_Pos (16U)
14507#define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
14508#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
14509#define RCC_APB2ENR_TIM10EN_Pos (17U)
14510#define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
14511#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
14512#define RCC_APB2ENR_TIM11EN_Pos (18U)
14513#define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
14514#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
14515#define RCC_APB2ENR_SPI5EN_Pos (20U)
14516#define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
14517#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
14518#define RCC_APB2ENR_SPI6EN_Pos (21U)
14519#define RCC_APB2ENR_SPI6EN_Msk (0x1U << RCC_APB2ENR_SPI6EN_Pos) /*!< 0x00200000 */
14520#define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
14521#define RCC_APB2ENR_SAI1EN_Pos (22U)
14522#define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
14523#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
14524#define RCC_APB2ENR_LTDCEN_Pos (26U)
14525#define RCC_APB2ENR_LTDCEN_Msk (0x1U << RCC_APB2ENR_LTDCEN_Pos) /*!< 0x04000000 */
14526#define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk
14527#define RCC_APB2ENR_DSIEN_Pos (27U)
14528#define RCC_APB2ENR_DSIEN_Msk (0x1U << RCC_APB2ENR_DSIEN_Pos) /*!< 0x08000000 */
14529#define RCC_APB2ENR_DSIEN RCC_APB2ENR_DSIEN_Msk
14530
14531/******************** Bit definition for RCC_AHB1LPENR register *************/
14532#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
14533#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
14534#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
14535#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
14536#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
14537#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
14538#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
14539#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
14540#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
14541#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
14542#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
14543#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
14544#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
14545#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
14546#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
14547#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
14548#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
14549#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
14550#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
14551#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
14552#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
14553#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
14554#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
14555#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
14556#define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
14557#define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
14558#define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
14559#define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
14560#define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
14561#define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
14562#define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
14563#define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
14564#define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
14565#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
14566#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
14567#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
14568#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
14569#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
14570#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
14571#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
14572#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
14573#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
14574#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
14575#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
14576#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
14577#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
14578#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
14579#define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
14580#define RCC_AHB1LPENR_SRAM3LPEN_Pos (19U)
14581#define RCC_AHB1LPENR_SRAM3LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM3LPEN_Pos) /*!< 0x00080000 */
14582#define RCC_AHB1LPENR_SRAM3LPEN RCC_AHB1LPENR_SRAM3LPEN_Msk
14583#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
14584#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
14585#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
14586#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
14587#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
14588#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
14589#define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
14590#define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */
14591#define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
14592
14593#define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
14594#define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
14595#define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
14596#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
14597#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
14598#define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
14599#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
14600#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
14601#define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
14602#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
14603#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
14604#define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
14605#define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
14606#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
14607#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
14608#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
14609#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
14610#define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
14611
14612/******************** Bit definition for RCC_AHB2LPENR register *************/
14613#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
14614#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
14615#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
14616#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
14617#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1U << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
14618#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
14619#define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
14620#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1U << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
14621#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
14622#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
14623#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
14624#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
14625#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
14626#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
14627#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
14628
14629/******************** Bit definition for RCC_AHB3LPENR register *************/
14630#define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
14631#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
14632#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
14633#define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
14634#define RCC_AHB3LPENR_QSPILPEN_Msk (0x1U << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */
14635#define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
14636
14637/******************** Bit definition for RCC_APB1LPENR register *************/
14638#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
14639#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
14640#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
14641#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
14642#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
14643#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
14644#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
14645#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
14646#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
14647#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
14648#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
14649#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
14650#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
14651#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
14652#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
14653#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
14654#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
14655#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
14656#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
14657#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
14658#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
14659#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
14660#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
14661#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
14662#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
14663#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
14664#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
14665#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
14666#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
14667#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
14668#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
14669#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
14670#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
14671#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
14672#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
14673#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
14674#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
14675#define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
14676#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
14677#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
14678#define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
14679#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
14680#define RCC_APB1LPENR_UART4LPEN_Pos (19U)
14681#define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
14682#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
14683#define RCC_APB1LPENR_UART5LPEN_Pos (20U)
14684#define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
14685#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
14686#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
14687#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
14688#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
14689#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
14690#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
14691#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
14692#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
14693#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
14694#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
14695#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
14696#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
14697#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
14698#define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
14699#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
14700#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
14701#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
14702#define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
14703#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
14704#define RCC_APB1LPENR_DACLPEN_Pos (29U)
14705#define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
14706#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
14707#define RCC_APB1LPENR_UART7LPEN_Pos (30U)
14708#define RCC_APB1LPENR_UART7LPEN_Msk (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
14709#define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
14710#define RCC_APB1LPENR_UART8LPEN_Pos (31U)
14711#define RCC_APB1LPENR_UART8LPEN_Msk (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
14712#define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
14713
14714/******************** Bit definition for RCC_APB2LPENR register *************/
14715#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
14716#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
14717#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
14718#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
14719#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
14720#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
14721#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
14722#define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
14723#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
14724#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
14725#define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
14726#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
14727#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
14728#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
14729#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
14730#define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
14731#define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
14732#define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
14733#define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
14734#define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
14735#define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
14736#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
14737#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
14738#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
14739#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
14740#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
14741#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
14742#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
14743#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
14744#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
14745#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
14746#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
14747#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
14748#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
14749#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
14750#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
14751#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
14752#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
14753#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
14754#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
14755#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
14756#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
14757#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
14758#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
14759#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
14760#define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
14761#define RCC_APB2LPENR_SPI6LPEN_Msk (0x1U << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */
14762#define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
14763#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
14764#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
14765#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
14766#define RCC_APB2LPENR_LTDCLPEN_Pos (26U)
14767#define RCC_APB2LPENR_LTDCLPEN_Msk (0x1U << RCC_APB2LPENR_LTDCLPEN_Pos) /*!< 0x04000000 */
14768#define RCC_APB2LPENR_LTDCLPEN RCC_APB2LPENR_LTDCLPEN_Msk
14769#define RCC_APB2LPENR_DSILPEN_Pos (27U)
14770#define RCC_APB2LPENR_DSILPEN_Msk (0x1U << RCC_APB2LPENR_DSILPEN_Pos) /*!< 0x08000000 */
14771#define RCC_APB2LPENR_DSILPEN RCC_APB2LPENR_DSILPEN_Msk
14772
14773/******************** Bit definition for RCC_BDCR register ******************/
14774#define RCC_BDCR_LSEON_Pos (0U)
14775#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
14776#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
14777#define RCC_BDCR_LSERDY_Pos (1U)
14778#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
14779#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
14780#define RCC_BDCR_LSEBYP_Pos (2U)
14781#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
14782#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
14783#define RCC_BDCR_LSEMOD_Pos (3U)
14784#define RCC_BDCR_LSEMOD_Msk (0x1U << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */
14785#define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
14786
14787#define RCC_BDCR_RTCSEL_Pos (8U)
14788#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
14789#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
14790#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
14791#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
14792
14793#define RCC_BDCR_RTCEN_Pos (15U)
14794#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
14795#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
14796#define RCC_BDCR_BDRST_Pos (16U)
14797#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
14798#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
14799
14800/******************** Bit definition for RCC_CSR register *******************/
14801#define RCC_CSR_LSION_Pos (0U)
14802#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
14803#define RCC_CSR_LSION RCC_CSR_LSION_Msk
14804#define RCC_CSR_LSIRDY_Pos (1U)
14805#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
14806#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
14807#define RCC_CSR_RMVF_Pos (24U)
14808#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
14809#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
14810#define RCC_CSR_BORRSTF_Pos (25U)
14811#define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
14812#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
14813#define RCC_CSR_PINRSTF_Pos (26U)
14814#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
14815#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
14816#define RCC_CSR_PORRSTF_Pos (27U)
14817#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
14818#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
14819#define RCC_CSR_SFTRSTF_Pos (28U)
14820#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
14821#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
14822#define RCC_CSR_IWDGRSTF_Pos (29U)
14823#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
14824#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
14825#define RCC_CSR_WWDGRSTF_Pos (30U)
14826#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
14827#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
14828#define RCC_CSR_LPWRRSTF_Pos (31U)
14829#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
14830#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
14831/* Legacy defines */
14832#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
14833#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
14834
14835/******************** Bit definition for RCC_SSCGR register *****************/
14836#define RCC_SSCGR_MODPER_Pos (0U)
14837#define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
14838#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
14839#define RCC_SSCGR_INCSTEP_Pos (13U)
14840#define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
14841#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
14842#define RCC_SSCGR_SPREADSEL_Pos (30U)
14843#define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
14844#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
14845#define RCC_SSCGR_SSCGEN_Pos (31U)
14846#define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
14847#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
14848
14849/******************** Bit definition for RCC_PLLI2SCFGR register ************/
14850#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
14851#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
14852#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
14853#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
14854#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
14855#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
14856#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
14857#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
14858#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
14859#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
14860#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
14861#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
14862
14863#define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
14864#define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
14865#define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
14866#define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
14867#define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
14868#define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
14869#define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
14870#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
14871#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
14872#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
14873#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
14874#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
14875#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
14876
14877/******************** Bit definition for RCC_PLLSAICFGR register ************/
14878#define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
14879#define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
14880#define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
14881#define RCC_PLLSAICFGR_PLLSAIN_0 (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
14882#define RCC_PLLSAICFGR_PLLSAIN_1 (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
14883#define RCC_PLLSAICFGR_PLLSAIN_2 (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
14884#define RCC_PLLSAICFGR_PLLSAIN_3 (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
14885#define RCC_PLLSAICFGR_PLLSAIN_4 (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
14886#define RCC_PLLSAICFGR_PLLSAIN_5 (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
14887#define RCC_PLLSAICFGR_PLLSAIN_6 (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
14888#define RCC_PLLSAICFGR_PLLSAIN_7 (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
14889#define RCC_PLLSAICFGR_PLLSAIN_8 (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
14890
14891#define RCC_PLLSAICFGR_PLLSAIP_Pos (16U)
14892#define RCC_PLLSAICFGR_PLLSAIP_Msk (0x3U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00030000 */
14893#define RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP_Msk
14894#define RCC_PLLSAICFGR_PLLSAIP_0 (0x1U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00010000 */
14895#define RCC_PLLSAICFGR_PLLSAIP_1 (0x2U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00020000 */
14896
14897#define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
14898#define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
14899#define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
14900#define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
14901#define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
14902#define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
14903#define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
14904
14905#define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
14906#define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */
14907#define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
14908#define RCC_PLLSAICFGR_PLLSAIR_0 (0x1U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */
14909#define RCC_PLLSAICFGR_PLLSAIR_1 (0x2U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */
14910#define RCC_PLLSAICFGR_PLLSAIR_2 (0x4U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
14911
14912/******************** Bit definition for RCC_DCKCFGR register ***************/
14913#define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U)
14914#define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
14915#define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk
14916#define RCC_DCKCFGR_PLLI2SDIVQ_0 (0x01U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
14917#define RCC_DCKCFGR_PLLI2SDIVQ_1 (0x02U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
14918#define RCC_DCKCFGR_PLLI2SDIVQ_2 (0x04U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
14919#define RCC_DCKCFGR_PLLI2SDIVQ_3 (0x08U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
14920#define RCC_DCKCFGR_PLLI2SDIVQ_4 (0x10U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
14921
14922#define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U)
14923#define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
14924#define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk
14925#define RCC_DCKCFGR_PLLSAIDIVQ_0 (0x01U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
14926#define RCC_DCKCFGR_PLLSAIDIVQ_1 (0x02U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
14927#define RCC_DCKCFGR_PLLSAIDIVQ_2 (0x04U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
14928#define RCC_DCKCFGR_PLLSAIDIVQ_3 (0x08U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
14929#define RCC_DCKCFGR_PLLSAIDIVQ_4 (0x10U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
14930#define RCC_DCKCFGR_PLLSAIDIVR_Pos (16U)
14931#define RCC_DCKCFGR_PLLSAIDIVR_Msk (0x3U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */
14932#define RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_Msk
14933#define RCC_DCKCFGR_PLLSAIDIVR_0 (0x1U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00010000 */
14934#define RCC_DCKCFGR_PLLSAIDIVR_1 (0x2U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00020000 */
14935
14936#define RCC_DCKCFGR_SAI1ASRC_Pos (20U)
14937#define RCC_DCKCFGR_SAI1ASRC_Msk (0x3U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00300000 */
14938#define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk
14939#define RCC_DCKCFGR_SAI1ASRC_0 (0x1U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00100000 */
14940#define RCC_DCKCFGR_SAI1ASRC_1 (0x2U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00200000 */
14941#define RCC_DCKCFGR_SAI1BSRC_Pos (22U)
14942#define RCC_DCKCFGR_SAI1BSRC_Msk (0x3U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00C00000 */
14943#define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk
14944#define RCC_DCKCFGR_SAI1BSRC_0 (0x1U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00400000 */
14945#define RCC_DCKCFGR_SAI1BSRC_1 (0x2U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00800000 */
14946#define RCC_DCKCFGR_TIMPRE_Pos (24U)
14947#define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
14948#define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
14949#define RCC_DCKCFGR_CK48MSEL_Pos (27U)
14950#define RCC_DCKCFGR_CK48MSEL_Msk (0x1U << RCC_DCKCFGR_CK48MSEL_Pos) /*!< 0x08000000 */
14951#define RCC_DCKCFGR_CK48MSEL RCC_DCKCFGR_CK48MSEL_Msk
14952#define RCC_DCKCFGR_SDIOSEL_Pos (28U)
14953#define RCC_DCKCFGR_SDIOSEL_Msk (0x1U << RCC_DCKCFGR_SDIOSEL_Pos) /*!< 0x10000000 */
14954#define RCC_DCKCFGR_SDIOSEL RCC_DCKCFGR_SDIOSEL_Msk
14955#define RCC_DCKCFGR_DSISEL_Pos (29U)
14956#define RCC_DCKCFGR_DSISEL_Msk (0x1U << RCC_DCKCFGR_DSISEL_Pos) /*!< 0x20000000 */
14957#define RCC_DCKCFGR_DSISEL RCC_DCKCFGR_DSISEL_Msk
14958
14959
14960/******************************************************************************/
14961/* */
14962/* RNG */
14963/* */
14964/******************************************************************************/
14965/******************** Bits definition for RNG_CR register *******************/
14966#define RNG_CR_RNGEN_Pos (2U)
14967#define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
14968#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
14969#define RNG_CR_IE_Pos (3U)
14970#define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
14971#define RNG_CR_IE RNG_CR_IE_Msk
14972
14973/******************** Bits definition for RNG_SR register *******************/
14974#define RNG_SR_DRDY_Pos (0U)
14975#define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
14976#define RNG_SR_DRDY RNG_SR_DRDY_Msk
14977#define RNG_SR_CECS_Pos (1U)
14978#define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
14979#define RNG_SR_CECS RNG_SR_CECS_Msk
14980#define RNG_SR_SECS_Pos (2U)
14981#define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
14982#define RNG_SR_SECS RNG_SR_SECS_Msk
14983#define RNG_SR_CEIS_Pos (5U)
14984#define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
14985#define RNG_SR_CEIS RNG_SR_CEIS_Msk
14986#define RNG_SR_SEIS_Pos (6U)
14987#define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
14988#define RNG_SR_SEIS RNG_SR_SEIS_Msk
14989
14990/******************************************************************************/
14991/* */
14992/* Real-Time Clock (RTC) */
14993/* */
14994/******************************************************************************/
14995/*
14996 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
14997 */
14998#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
14999#define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
15000/******************** Bits definition for RTC_TR register *******************/
15001#define RTC_TR_PM_Pos (22U)
15002#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
15003#define RTC_TR_PM RTC_TR_PM_Msk
15004#define RTC_TR_HT_Pos (20U)
15005#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
15006#define RTC_TR_HT RTC_TR_HT_Msk
15007#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
15008#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
15009#define RTC_TR_HU_Pos (16U)
15010#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
15011#define RTC_TR_HU RTC_TR_HU_Msk
15012#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
15013#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
15014#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
15015#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
15016#define RTC_TR_MNT_Pos (12U)
15017#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
15018#define RTC_TR_MNT RTC_TR_MNT_Msk
15019#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
15020#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
15021#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
15022#define RTC_TR_MNU_Pos (8U)
15023#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
15024#define RTC_TR_MNU RTC_TR_MNU_Msk
15025#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
15026#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
15027#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
15028#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
15029#define RTC_TR_ST_Pos (4U)
15030#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
15031#define RTC_TR_ST RTC_TR_ST_Msk
15032#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
15033#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
15034#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
15035#define RTC_TR_SU_Pos (0U)
15036#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
15037#define RTC_TR_SU RTC_TR_SU_Msk
15038#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
15039#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
15040#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
15041#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
15042
15043/******************** Bits definition for RTC_DR register *******************/
15044#define RTC_DR_YT_Pos (20U)
15045#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
15046#define RTC_DR_YT RTC_DR_YT_Msk
15047#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
15048#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
15049#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
15050#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
15051#define RTC_DR_YU_Pos (16U)
15052#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
15053#define RTC_DR_YU RTC_DR_YU_Msk
15054#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
15055#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
15056#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
15057#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
15058#define RTC_DR_WDU_Pos (13U)
15059#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
15060#define RTC_DR_WDU RTC_DR_WDU_Msk
15061#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
15062#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
15063#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
15064#define RTC_DR_MT_Pos (12U)
15065#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
15066#define RTC_DR_MT RTC_DR_MT_Msk
15067#define RTC_DR_MU_Pos (8U)
15068#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
15069#define RTC_DR_MU RTC_DR_MU_Msk
15070#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
15071#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
15072#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
15073#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
15074#define RTC_DR_DT_Pos (4U)
15075#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
15076#define RTC_DR_DT RTC_DR_DT_Msk
15077#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
15078#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
15079#define RTC_DR_DU_Pos (0U)
15080#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
15081#define RTC_DR_DU RTC_DR_DU_Msk
15082#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
15083#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
15084#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
15085#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
15086
15087/******************** Bits definition for RTC_CR register *******************/
15088#define RTC_CR_COE_Pos (23U)
15089#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
15090#define RTC_CR_COE RTC_CR_COE_Msk
15091#define RTC_CR_OSEL_Pos (21U)
15092#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
15093#define RTC_CR_OSEL RTC_CR_OSEL_Msk
15094#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
15095#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
15096#define RTC_CR_POL_Pos (20U)
15097#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
15098#define RTC_CR_POL RTC_CR_POL_Msk
15099#define RTC_CR_COSEL_Pos (19U)
15100#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
15101#define RTC_CR_COSEL RTC_CR_COSEL_Msk
15102#define RTC_CR_BKP_Pos (18U)
15103#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
15104#define RTC_CR_BKP RTC_CR_BKP_Msk
15105#define RTC_CR_SUB1H_Pos (17U)
15106#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
15107#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
15108#define RTC_CR_ADD1H_Pos (16U)
15109#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
15110#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
15111#define RTC_CR_TSIE_Pos (15U)
15112#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
15113#define RTC_CR_TSIE RTC_CR_TSIE_Msk
15114#define RTC_CR_WUTIE_Pos (14U)
15115#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
15116#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
15117#define RTC_CR_ALRBIE_Pos (13U)
15118#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
15119#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
15120#define RTC_CR_ALRAIE_Pos (12U)
15121#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
15122#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
15123#define RTC_CR_TSE_Pos (11U)
15124#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
15125#define RTC_CR_TSE RTC_CR_TSE_Msk
15126#define RTC_CR_WUTE_Pos (10U)
15127#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
15128#define RTC_CR_WUTE RTC_CR_WUTE_Msk
15129#define RTC_CR_ALRBE_Pos (9U)
15130#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
15131#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
15132#define RTC_CR_ALRAE_Pos (8U)
15133#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
15134#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
15135#define RTC_CR_DCE_Pos (7U)
15136#define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
15137#define RTC_CR_DCE RTC_CR_DCE_Msk
15138#define RTC_CR_FMT_Pos (6U)
15139#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
15140#define RTC_CR_FMT RTC_CR_FMT_Msk
15141#define RTC_CR_BYPSHAD_Pos (5U)
15142#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
15143#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
15144#define RTC_CR_REFCKON_Pos (4U)
15145#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
15146#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
15147#define RTC_CR_TSEDGE_Pos (3U)
15148#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
15149#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
15150#define RTC_CR_WUCKSEL_Pos (0U)
15151#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
15152#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
15153#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
15154#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
15155#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
15156
15157/* Legacy defines */
15158#define RTC_CR_BCK RTC_CR_BKP
15159
15160/******************** Bits definition for RTC_ISR register ******************/
15161#define RTC_ISR_RECALPF_Pos (16U)
15162#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
15163#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
15164#define RTC_ISR_TAMP1F_Pos (13U)
15165#define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
15166#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
15167#define RTC_ISR_TAMP2F_Pos (14U)
15168#define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
15169#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
15170#define RTC_ISR_TSOVF_Pos (12U)
15171#define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
15172#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
15173#define RTC_ISR_TSF_Pos (11U)
15174#define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
15175#define RTC_ISR_TSF RTC_ISR_TSF_Msk
15176#define RTC_ISR_WUTF_Pos (10U)
15177#define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
15178#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
15179#define RTC_ISR_ALRBF_Pos (9U)
15180#define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
15181#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
15182#define RTC_ISR_ALRAF_Pos (8U)
15183#define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
15184#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
15185#define RTC_ISR_INIT_Pos (7U)
15186#define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
15187#define RTC_ISR_INIT RTC_ISR_INIT_Msk
15188#define RTC_ISR_INITF_Pos (6U)
15189#define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
15190#define RTC_ISR_INITF RTC_ISR_INITF_Msk
15191#define RTC_ISR_RSF_Pos (5U)
15192#define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
15193#define RTC_ISR_RSF RTC_ISR_RSF_Msk
15194#define RTC_ISR_INITS_Pos (4U)
15195#define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
15196#define RTC_ISR_INITS RTC_ISR_INITS_Msk
15197#define RTC_ISR_SHPF_Pos (3U)
15198#define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
15199#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
15200#define RTC_ISR_WUTWF_Pos (2U)
15201#define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
15202#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
15203#define RTC_ISR_ALRBWF_Pos (1U)
15204#define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
15205#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
15206#define RTC_ISR_ALRAWF_Pos (0U)
15207#define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
15208#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
15209
15210/******************** Bits definition for RTC_PRER register *****************/
15211#define RTC_PRER_PREDIV_A_Pos (16U)
15212#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
15213#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
15214#define RTC_PRER_PREDIV_S_Pos (0U)
15215#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
15216#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
15217
15218/******************** Bits definition for RTC_WUTR register *****************/
15219#define RTC_WUTR_WUT_Pos (0U)
15220#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
15221#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
15222
15223/******************** Bits definition for RTC_CALIBR register ***************/
15224#define RTC_CALIBR_DCS_Pos (7U)
15225#define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
15226#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
15227#define RTC_CALIBR_DC_Pos (0U)
15228#define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
15229#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
15230
15231/******************** Bits definition for RTC_ALRMAR register ***************/
15232#define RTC_ALRMAR_MSK4_Pos (31U)
15233#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
15234#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
15235#define RTC_ALRMAR_WDSEL_Pos (30U)
15236#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
15237#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
15238#define RTC_ALRMAR_DT_Pos (28U)
15239#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
15240#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
15241#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
15242#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
15243#define RTC_ALRMAR_DU_Pos (24U)
15244#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
15245#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
15246#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
15247#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
15248#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
15249#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
15250#define RTC_ALRMAR_MSK3_Pos (23U)
15251#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
15252#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
15253#define RTC_ALRMAR_PM_Pos (22U)
15254#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
15255#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
15256#define RTC_ALRMAR_HT_Pos (20U)
15257#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
15258#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
15259#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
15260#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
15261#define RTC_ALRMAR_HU_Pos (16U)
15262#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
15263#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
15264#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
15265#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
15266#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
15267#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
15268#define RTC_ALRMAR_MSK2_Pos (15U)
15269#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
15270#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
15271#define RTC_ALRMAR_MNT_Pos (12U)
15272#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
15273#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
15274#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
15275#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
15276#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
15277#define RTC_ALRMAR_MNU_Pos (8U)
15278#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
15279#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
15280#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
15281#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
15282#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
15283#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
15284#define RTC_ALRMAR_MSK1_Pos (7U)
15285#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
15286#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
15287#define RTC_ALRMAR_ST_Pos (4U)
15288#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
15289#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
15290#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
15291#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
15292#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
15293#define RTC_ALRMAR_SU_Pos (0U)
15294#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
15295#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
15296#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
15297#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
15298#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
15299#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
15300
15301/******************** Bits definition for RTC_ALRMBR register ***************/
15302#define RTC_ALRMBR_MSK4_Pos (31U)
15303#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
15304#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
15305#define RTC_ALRMBR_WDSEL_Pos (30U)
15306#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
15307#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
15308#define RTC_ALRMBR_DT_Pos (28U)
15309#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
15310#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
15311#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
15312#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
15313#define RTC_ALRMBR_DU_Pos (24U)
15314#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
15315#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
15316#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
15317#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
15318#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
15319#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
15320#define RTC_ALRMBR_MSK3_Pos (23U)
15321#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
15322#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
15323#define RTC_ALRMBR_PM_Pos (22U)
15324#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
15325#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
15326#define RTC_ALRMBR_HT_Pos (20U)
15327#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
15328#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
15329#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
15330#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
15331#define RTC_ALRMBR_HU_Pos (16U)
15332#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
15333#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
15334#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
15335#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
15336#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
15337#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
15338#define RTC_ALRMBR_MSK2_Pos (15U)
15339#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
15340#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
15341#define RTC_ALRMBR_MNT_Pos (12U)
15342#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
15343#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
15344#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
15345#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
15346#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
15347#define RTC_ALRMBR_MNU_Pos (8U)
15348#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
15349#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
15350#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
15351#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
15352#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
15353#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
15354#define RTC_ALRMBR_MSK1_Pos (7U)
15355#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
15356#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
15357#define RTC_ALRMBR_ST_Pos (4U)
15358#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
15359#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
15360#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
15361#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
15362#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
15363#define RTC_ALRMBR_SU_Pos (0U)
15364#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
15365#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
15366#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
15367#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
15368#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
15369#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
15370
15371/******************** Bits definition for RTC_WPR register ******************/
15372#define RTC_WPR_KEY_Pos (0U)
15373#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
15374#define RTC_WPR_KEY RTC_WPR_KEY_Msk
15375
15376/******************** Bits definition for RTC_SSR register ******************/
15377#define RTC_SSR_SS_Pos (0U)
15378#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
15379#define RTC_SSR_SS RTC_SSR_SS_Msk
15380
15381/******************** Bits definition for RTC_SHIFTR register ***************/
15382#define RTC_SHIFTR_SUBFS_Pos (0U)
15383#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
15384#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
15385#define RTC_SHIFTR_ADD1S_Pos (31U)
15386#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
15387#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
15388
15389/******************** Bits definition for RTC_TSTR register *****************/
15390#define RTC_TSTR_PM_Pos (22U)
15391#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
15392#define RTC_TSTR_PM RTC_TSTR_PM_Msk
15393#define RTC_TSTR_HT_Pos (20U)
15394#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
15395#define RTC_TSTR_HT RTC_TSTR_HT_Msk
15396#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
15397#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
15398#define RTC_TSTR_HU_Pos (16U)
15399#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
15400#define RTC_TSTR_HU RTC_TSTR_HU_Msk
15401#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
15402#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
15403#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
15404#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
15405#define RTC_TSTR_MNT_Pos (12U)
15406#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
15407#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
15408#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
15409#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
15410#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
15411#define RTC_TSTR_MNU_Pos (8U)
15412#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
15413#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
15414#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
15415#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
15416#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
15417#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
15418#define RTC_TSTR_ST_Pos (4U)
15419#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
15420#define RTC_TSTR_ST RTC_TSTR_ST_Msk
15421#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
15422#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
15423#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
15424#define RTC_TSTR_SU_Pos (0U)
15425#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
15426#define RTC_TSTR_SU RTC_TSTR_SU_Msk
15427#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
15428#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
15429#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
15430#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
15431
15432/******************** Bits definition for RTC_TSDR register *****************/
15433#define RTC_TSDR_WDU_Pos (13U)
15434#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
15435#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
15436#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
15437#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
15438#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
15439#define RTC_TSDR_MT_Pos (12U)
15440#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
15441#define RTC_TSDR_MT RTC_TSDR_MT_Msk
15442#define RTC_TSDR_MU_Pos (8U)
15443#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
15444#define RTC_TSDR_MU RTC_TSDR_MU_Msk
15445#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
15446#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
15447#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
15448#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
15449#define RTC_TSDR_DT_Pos (4U)
15450#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
15451#define RTC_TSDR_DT RTC_TSDR_DT_Msk
15452#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
15453#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
15454#define RTC_TSDR_DU_Pos (0U)
15455#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
15456#define RTC_TSDR_DU RTC_TSDR_DU_Msk
15457#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
15458#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
15459#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
15460#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
15461
15462/******************** Bits definition for RTC_TSSSR register ****************/
15463#define RTC_TSSSR_SS_Pos (0U)
15464#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
15465#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
15466
15467/******************** Bits definition for RTC_CAL register *****************/
15468#define RTC_CALR_CALP_Pos (15U)
15469#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
15470#define RTC_CALR_CALP RTC_CALR_CALP_Msk
15471#define RTC_CALR_CALW8_Pos (14U)
15472#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
15473#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
15474#define RTC_CALR_CALW16_Pos (13U)
15475#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
15476#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
15477#define RTC_CALR_CALM_Pos (0U)
15478#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
15479#define RTC_CALR_CALM RTC_CALR_CALM_Msk
15480#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
15481#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
15482#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
15483#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
15484#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
15485#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
15486#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
15487#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
15488#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
15489
15490/******************** Bits definition for RTC_TAFCR register ****************/
15491#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
15492#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
15493#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
15494#define RTC_TAFCR_TSINSEL_Pos (17U)
15495#define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
15496#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
15497#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
15498#define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
15499#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
15500#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
15501#define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
15502#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
15503#define RTC_TAFCR_TAMPPRCH_Pos (13U)
15504#define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
15505#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
15506#define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
15507#define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
15508#define RTC_TAFCR_TAMPFLT_Pos (11U)
15509#define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
15510#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
15511#define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
15512#define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
15513#define RTC_TAFCR_TAMPFREQ_Pos (8U)
15514#define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
15515#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
15516#define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
15517#define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
15518#define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
15519#define RTC_TAFCR_TAMPTS_Pos (7U)
15520#define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
15521#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
15522#define RTC_TAFCR_TAMP2TRG_Pos (4U)
15523#define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
15524#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
15525#define RTC_TAFCR_TAMP2E_Pos (3U)
15526#define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
15527#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
15528#define RTC_TAFCR_TAMPIE_Pos (2U)
15529#define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
15530#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
15531#define RTC_TAFCR_TAMP1TRG_Pos (1U)
15532#define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
15533#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
15534#define RTC_TAFCR_TAMP1E_Pos (0U)
15535#define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
15536#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
15537
15538/* Legacy defines */
15539#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
15540
15541/******************** Bits definition for RTC_ALRMASSR register *************/
15542#define RTC_ALRMASSR_MASKSS_Pos (24U)
15543#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
15544#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
15545#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
15546#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
15547#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
15548#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
15549#define RTC_ALRMASSR_SS_Pos (0U)
15550#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
15551#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
15552
15553/******************** Bits definition for RTC_ALRMBSSR register *************/
15554#define RTC_ALRMBSSR_MASKSS_Pos (24U)
15555#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
15556#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
15557#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
15558#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
15559#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
15560#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
15561#define RTC_ALRMBSSR_SS_Pos (0U)
15562#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
15563#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
15564
15565/******************** Bits definition for RTC_BKP0R register ****************/
15566#define RTC_BKP0R_Pos (0U)
15567#define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
15568#define RTC_BKP0R RTC_BKP0R_Msk
15569
15570/******************** Bits definition for RTC_BKP1R register ****************/
15571#define RTC_BKP1R_Pos (0U)
15572#define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
15573#define RTC_BKP1R RTC_BKP1R_Msk
15574
15575/******************** Bits definition for RTC_BKP2R register ****************/
15576#define RTC_BKP2R_Pos (0U)
15577#define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
15578#define RTC_BKP2R RTC_BKP2R_Msk
15579
15580/******************** Bits definition for RTC_BKP3R register ****************/
15581#define RTC_BKP3R_Pos (0U)
15582#define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
15583#define RTC_BKP3R RTC_BKP3R_Msk
15584
15585/******************** Bits definition for RTC_BKP4R register ****************/
15586#define RTC_BKP4R_Pos (0U)
15587#define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
15588#define RTC_BKP4R RTC_BKP4R_Msk
15589
15590/******************** Bits definition for RTC_BKP5R register ****************/
15591#define RTC_BKP5R_Pos (0U)
15592#define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
15593#define RTC_BKP5R RTC_BKP5R_Msk
15594
15595/******************** Bits definition for RTC_BKP6R register ****************/
15596#define RTC_BKP6R_Pos (0U)
15597#define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
15598#define RTC_BKP6R RTC_BKP6R_Msk
15599
15600/******************** Bits definition for RTC_BKP7R register ****************/
15601#define RTC_BKP7R_Pos (0U)
15602#define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
15603#define RTC_BKP7R RTC_BKP7R_Msk
15604
15605/******************** Bits definition for RTC_BKP8R register ****************/
15606#define RTC_BKP8R_Pos (0U)
15607#define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
15608#define RTC_BKP8R RTC_BKP8R_Msk
15609
15610/******************** Bits definition for RTC_BKP9R register ****************/
15611#define RTC_BKP9R_Pos (0U)
15612#define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
15613#define RTC_BKP9R RTC_BKP9R_Msk
15614
15615/******************** Bits definition for RTC_BKP10R register ***************/
15616#define RTC_BKP10R_Pos (0U)
15617#define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
15618#define RTC_BKP10R RTC_BKP10R_Msk
15619
15620/******************** Bits definition for RTC_BKP11R register ***************/
15621#define RTC_BKP11R_Pos (0U)
15622#define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
15623#define RTC_BKP11R RTC_BKP11R_Msk
15624
15625/******************** Bits definition for RTC_BKP12R register ***************/
15626#define RTC_BKP12R_Pos (0U)
15627#define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
15628#define RTC_BKP12R RTC_BKP12R_Msk
15629
15630/******************** Bits definition for RTC_BKP13R register ***************/
15631#define RTC_BKP13R_Pos (0U)
15632#define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
15633#define RTC_BKP13R RTC_BKP13R_Msk
15634
15635/******************** Bits definition for RTC_BKP14R register ***************/
15636#define RTC_BKP14R_Pos (0U)
15637#define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
15638#define RTC_BKP14R RTC_BKP14R_Msk
15639
15640/******************** Bits definition for RTC_BKP15R register ***************/
15641#define RTC_BKP15R_Pos (0U)
15642#define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
15643#define RTC_BKP15R RTC_BKP15R_Msk
15644
15645/******************** Bits definition for RTC_BKP16R register ***************/
15646#define RTC_BKP16R_Pos (0U)
15647#define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
15648#define RTC_BKP16R RTC_BKP16R_Msk
15649
15650/******************** Bits definition for RTC_BKP17R register ***************/
15651#define RTC_BKP17R_Pos (0U)
15652#define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
15653#define RTC_BKP17R RTC_BKP17R_Msk
15654
15655/******************** Bits definition for RTC_BKP18R register ***************/
15656#define RTC_BKP18R_Pos (0U)
15657#define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
15658#define RTC_BKP18R RTC_BKP18R_Msk
15659
15660/******************** Bits definition for RTC_BKP19R register ***************/
15661#define RTC_BKP19R_Pos (0U)
15662#define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
15663#define RTC_BKP19R RTC_BKP19R_Msk
15664
15665/******************** Number of backup registers ******************************/
15666#define RTC_BKP_NUMBER 0x000000014U
15667
15668/******************************************************************************/
15669/* */
15670/* Serial Audio Interface */
15671/* */
15672/******************************************************************************/
15673/******************** Bit definition for SAI_GCR register *******************/
15674#define SAI_GCR_SYNCIN_Pos (0U)
15675#define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
15676#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
15677#define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
15678#define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
15679
15680#define SAI_GCR_SYNCOUT_Pos (4U)
15681#define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
15682#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
15683#define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
15684#define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
15685
15686/******************* Bit definition for SAI_xCR1 register *******************/
15687#define SAI_xCR1_MODE_Pos (0U)
15688#define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
15689#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
15690#define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
15691#define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
15692
15693#define SAI_xCR1_PRTCFG_Pos (2U)
15694#define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
15695#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
15696#define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
15697#define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
15698
15699#define SAI_xCR1_DS_Pos (5U)
15700#define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
15701#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
15702#define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
15703#define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
15704#define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
15705
15706#define SAI_xCR1_LSBFIRST_Pos (8U)
15707#define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
15708#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
15709#define SAI_xCR1_CKSTR_Pos (9U)
15710#define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
15711#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
15712
15713#define SAI_xCR1_SYNCEN_Pos (10U)
15714#define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
15715#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
15716#define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
15717#define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
15718
15719#define SAI_xCR1_MONO_Pos (12U)
15720#define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
15721#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
15722#define SAI_xCR1_OUTDRIV_Pos (13U)
15723#define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
15724#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
15725#define SAI_xCR1_SAIEN_Pos (16U)
15726#define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
15727#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
15728#define SAI_xCR1_DMAEN_Pos (17U)
15729#define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
15730#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
15731#define SAI_xCR1_NODIV_Pos (19U)
15732#define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
15733#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
15734
15735#define SAI_xCR1_MCKDIV_Pos (20U)
15736#define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
15737#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
15738#define SAI_xCR1_MCKDIV_0 (0x1U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
15739#define SAI_xCR1_MCKDIV_1 (0x2U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
15740#define SAI_xCR1_MCKDIV_2 (0x4U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
15741#define SAI_xCR1_MCKDIV_3 (0x8U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
15742
15743/******************* Bit definition for SAI_xCR2 register *******************/
15744#define SAI_xCR2_FTH_Pos (0U)
15745#define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
15746#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
15747#define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
15748#define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
15749#define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
15750
15751#define SAI_xCR2_FFLUSH_Pos (3U)
15752#define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
15753#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
15754#define SAI_xCR2_TRIS_Pos (4U)
15755#define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
15756#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
15757#define SAI_xCR2_MUTE_Pos (5U)
15758#define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
15759#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
15760#define SAI_xCR2_MUTEVAL_Pos (6U)
15761#define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
15762#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
15763
15764#define SAI_xCR2_MUTECNT_Pos (7U)
15765#define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
15766#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
15767#define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
15768#define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
15769#define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
15770#define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
15771#define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
15772#define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
15773
15774#define SAI_xCR2_CPL_Pos (13U)
15775#define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
15776#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
15777
15778#define SAI_xCR2_COMP_Pos (14U)
15779#define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
15780#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
15781#define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
15782#define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
15783
15784/****************** Bit definition for SAI_xFRCR register *******************/
15785#define SAI_xFRCR_FRL_Pos (0U)
15786#define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
15787#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[1:0](Frame length) */
15788#define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
15789#define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
15790#define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
15791#define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
15792#define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
15793#define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
15794#define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
15795#define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
15796
15797#define SAI_xFRCR_FSALL_Pos (8U)
15798#define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
15799#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[1:0] (Frame synchronization active level length) */
15800#define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
15801#define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
15802#define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
15803#define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
15804#define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
15805#define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
15806#define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
15807
15808#define SAI_xFRCR_FSDEF_Pos (16U)
15809#define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
15810#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
15811#define SAI_xFRCR_FSPOL_Pos (17U)
15812#define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
15813#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
15814#define SAI_xFRCR_FSOFF_Pos (18U)
15815#define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
15816#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
15817/* Legacy defines */
15818#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
15819
15820/****************** Bit definition for SAI_xSLOTR register *******************/
15821#define SAI_xSLOTR_FBOFF_Pos (0U)
15822#define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
15823#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
15824#define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
15825#define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
15826#define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
15827#define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
15828#define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
15829
15830#define SAI_xSLOTR_SLOTSZ_Pos (6U)
15831#define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
15832#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
15833#define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
15834#define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
15835
15836#define SAI_xSLOTR_NBSLOT_Pos (8U)
15837#define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
15838#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
15839#define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
15840#define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
15841#define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
15842#define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
15843
15844#define SAI_xSLOTR_SLOTEN_Pos (16U)
15845#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
15846#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
15847
15848/******************* Bit definition for SAI_xIMR register *******************/
15849#define SAI_xIMR_OVRUDRIE_Pos (0U)
15850#define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
15851#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
15852#define SAI_xIMR_MUTEDETIE_Pos (1U)
15853#define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
15854#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
15855#define SAI_xIMR_WCKCFGIE_Pos (2U)
15856#define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
15857#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
15858#define SAI_xIMR_FREQIE_Pos (3U)
15859#define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
15860#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
15861#define SAI_xIMR_CNRDYIE_Pos (4U)
15862#define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
15863#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
15864#define SAI_xIMR_AFSDETIE_Pos (5U)
15865#define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
15866#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
15867#define SAI_xIMR_LFSDETIE_Pos (6U)
15868#define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
15869#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
15870
15871/******************** Bit definition for SAI_xSR register *******************/
15872#define SAI_xSR_OVRUDR_Pos (0U)
15873#define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
15874#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
15875#define SAI_xSR_MUTEDET_Pos (1U)
15876#define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
15877#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
15878#define SAI_xSR_WCKCFG_Pos (2U)
15879#define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
15880#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
15881#define SAI_xSR_FREQ_Pos (3U)
15882#define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
15883#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
15884#define SAI_xSR_CNRDY_Pos (4U)
15885#define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
15886#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
15887#define SAI_xSR_AFSDET_Pos (5U)
15888#define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
15889#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
15890#define SAI_xSR_LFSDET_Pos (6U)
15891#define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
15892#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
15893
15894#define SAI_xSR_FLVL_Pos (16U)
15895#define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
15896#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
15897#define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
15898#define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
15899#define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
15900
15901/****************** Bit definition for SAI_xCLRFR register ******************/
15902#define SAI_xCLRFR_COVRUDR_Pos (0U)
15903#define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
15904#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
15905#define SAI_xCLRFR_CMUTEDET_Pos (1U)
15906#define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
15907#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
15908#define SAI_xCLRFR_CWCKCFG_Pos (2U)
15909#define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
15910#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
15911#define SAI_xCLRFR_CFREQ_Pos (3U)
15912#define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
15913#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
15914#define SAI_xCLRFR_CCNRDY_Pos (4U)
15915#define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
15916#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
15917#define SAI_xCLRFR_CAFSDET_Pos (5U)
15918#define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
15919#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
15920#define SAI_xCLRFR_CLFSDET_Pos (6U)
15921#define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
15922#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
15923
15924/****************** Bit definition for SAI_xDR register ******************/
15925#define SAI_xDR_DATA_Pos (0U)
15926#define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
15927#define SAI_xDR_DATA SAI_xDR_DATA_Msk
15928
15929
15930/******************************************************************************/
15931/* */
15932/* SD host Interface */
15933/* */
15934/******************************************************************************/
15935/****************** Bit definition for SDIO_POWER register ******************/
15936#define SDIO_POWER_PWRCTRL_Pos (0U)
15937#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
15938#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
15939#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
15940#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
15941
15942/****************** Bit definition for SDIO_CLKCR register ******************/
15943#define SDIO_CLKCR_CLKDIV_Pos (0U)
15944#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
15945#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
15946#define SDIO_CLKCR_CLKEN_Pos (8U)
15947#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
15948#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
15949#define SDIO_CLKCR_PWRSAV_Pos (9U)
15950#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
15951#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
15952#define SDIO_CLKCR_BYPASS_Pos (10U)
15953#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
15954#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
15955
15956#define SDIO_CLKCR_WIDBUS_Pos (11U)
15957#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
15958#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
15959#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
15960#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
15961
15962#define SDIO_CLKCR_NEGEDGE_Pos (13U)
15963#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
15964#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
15965#define SDIO_CLKCR_HWFC_EN_Pos (14U)
15966#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
15967#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
15968
15969/******************* Bit definition for SDIO_ARG register *******************/
15970#define SDIO_ARG_CMDARG_Pos (0U)
15971#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
15972#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
15973
15974/******************* Bit definition for SDIO_CMD register *******************/
15975#define SDIO_CMD_CMDINDEX_Pos (0U)
15976#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
15977#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
15978
15979#define SDIO_CMD_WAITRESP_Pos (6U)
15980#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
15981#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
15982#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
15983#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
15984
15985#define SDIO_CMD_WAITINT_Pos (8U)
15986#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
15987#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
15988#define SDIO_CMD_WAITPEND_Pos (9U)
15989#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
15990#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
15991#define SDIO_CMD_CPSMEN_Pos (10U)
15992#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
15993#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
15994#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
15995#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
15996#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
15997
15998/***************** Bit definition for SDIO_RESPCMD register *****************/
15999#define SDIO_RESPCMD_RESPCMD_Pos (0U)
16000#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
16001#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
16002
16003/****************** Bit definition for SDIO_RESP0 register ******************/
16004#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
16005#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
16006#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
16007
16008/****************** Bit definition for SDIO_RESP1 register ******************/
16009#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
16010#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
16011#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
16012
16013/****************** Bit definition for SDIO_RESP2 register ******************/
16014#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
16015#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
16016#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
16017
16018/****************** Bit definition for SDIO_RESP3 register ******************/
16019#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
16020#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
16021#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
16022
16023/****************** Bit definition for SDIO_RESP4 register ******************/
16024#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
16025#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
16026#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
16027
16028/****************** Bit definition for SDIO_DTIMER register *****************/
16029#define SDIO_DTIMER_DATATIME_Pos (0U)
16030#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
16031#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
16032
16033/****************** Bit definition for SDIO_DLEN register *******************/
16034#define SDIO_DLEN_DATALENGTH_Pos (0U)
16035#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
16036#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
16037
16038/****************** Bit definition for SDIO_DCTRL register ******************/
16039#define SDIO_DCTRL_DTEN_Pos (0U)
16040#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
16041#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
16042#define SDIO_DCTRL_DTDIR_Pos (1U)
16043#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
16044#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
16045#define SDIO_DCTRL_DTMODE_Pos (2U)
16046#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
16047#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
16048#define SDIO_DCTRL_DMAEN_Pos (3U)
16049#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
16050#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
16051
16052#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
16053#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
16054#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
16055#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
16056#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
16057#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
16058#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
16059
16060#define SDIO_DCTRL_RWSTART_Pos (8U)
16061#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
16062#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
16063#define SDIO_DCTRL_RWSTOP_Pos (9U)
16064#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
16065#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
16066#define SDIO_DCTRL_RWMOD_Pos (10U)
16067#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
16068#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
16069#define SDIO_DCTRL_SDIOEN_Pos (11U)
16070#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
16071#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
16072
16073/****************** Bit definition for SDIO_DCOUNT register *****************/
16074#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
16075#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
16076#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
16077
16078/****************** Bit definition for SDIO_STA register ********************/
16079#define SDIO_STA_CCRCFAIL_Pos (0U)
16080#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
16081#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
16082#define SDIO_STA_DCRCFAIL_Pos (1U)
16083#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
16084#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
16085#define SDIO_STA_CTIMEOUT_Pos (2U)
16086#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
16087#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
16088#define SDIO_STA_DTIMEOUT_Pos (3U)
16089#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
16090#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
16091#define SDIO_STA_TXUNDERR_Pos (4U)
16092#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
16093#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
16094#define SDIO_STA_RXOVERR_Pos (5U)
16095#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
16096#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
16097#define SDIO_STA_CMDREND_Pos (6U)
16098#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
16099#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
16100#define SDIO_STA_CMDSENT_Pos (7U)
16101#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
16102#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
16103#define SDIO_STA_DATAEND_Pos (8U)
16104#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
16105#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
16106#define SDIO_STA_DBCKEND_Pos (10U)
16107#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
16108#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
16109#define SDIO_STA_CMDACT_Pos (11U)
16110#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
16111#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
16112#define SDIO_STA_TXACT_Pos (12U)
16113#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
16114#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
16115#define SDIO_STA_RXACT_Pos (13U)
16116#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
16117#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
16118#define SDIO_STA_TXFIFOHE_Pos (14U)
16119#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
16120#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
16121#define SDIO_STA_RXFIFOHF_Pos (15U)
16122#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
16123#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
16124#define SDIO_STA_TXFIFOF_Pos (16U)
16125#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
16126#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
16127#define SDIO_STA_RXFIFOF_Pos (17U)
16128#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
16129#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
16130#define SDIO_STA_TXFIFOE_Pos (18U)
16131#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
16132#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
16133#define SDIO_STA_RXFIFOE_Pos (19U)
16134#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
16135#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
16136#define SDIO_STA_TXDAVL_Pos (20U)
16137#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
16138#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
16139#define SDIO_STA_RXDAVL_Pos (21U)
16140#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
16141#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
16142#define SDIO_STA_SDIOIT_Pos (22U)
16143#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
16144#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
16145
16146/******************* Bit definition for SDIO_ICR register *******************/
16147#define SDIO_ICR_CCRCFAILC_Pos (0U)
16148#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
16149#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
16150#define SDIO_ICR_DCRCFAILC_Pos (1U)
16151#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
16152#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
16153#define SDIO_ICR_CTIMEOUTC_Pos (2U)
16154#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
16155#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
16156#define SDIO_ICR_DTIMEOUTC_Pos (3U)
16157#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
16158#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
16159#define SDIO_ICR_TXUNDERRC_Pos (4U)
16160#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
16161#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
16162#define SDIO_ICR_RXOVERRC_Pos (5U)
16163#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
16164#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
16165#define SDIO_ICR_CMDRENDC_Pos (6U)
16166#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
16167#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
16168#define SDIO_ICR_CMDSENTC_Pos (7U)
16169#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
16170#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
16171#define SDIO_ICR_DATAENDC_Pos (8U)
16172#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
16173#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
16174#define SDIO_ICR_DBCKENDC_Pos (10U)
16175#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
16176#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
16177#define SDIO_ICR_SDIOITC_Pos (22U)
16178#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
16179#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
16180
16181/****************** Bit definition for SDIO_MASK register *******************/
16182#define SDIO_MASK_CCRCFAILIE_Pos (0U)
16183#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
16184#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
16185#define SDIO_MASK_DCRCFAILIE_Pos (1U)
16186#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
16187#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
16188#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
16189#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
16190#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
16191#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
16192#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
16193#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
16194#define SDIO_MASK_TXUNDERRIE_Pos (4U)
16195#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
16196#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
16197#define SDIO_MASK_RXOVERRIE_Pos (5U)
16198#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
16199#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
16200#define SDIO_MASK_CMDRENDIE_Pos (6U)
16201#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
16202#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
16203#define SDIO_MASK_CMDSENTIE_Pos (7U)
16204#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
16205#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
16206#define SDIO_MASK_DATAENDIE_Pos (8U)
16207#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
16208#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
16209#define SDIO_MASK_DBCKENDIE_Pos (10U)
16210#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
16211#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
16212#define SDIO_MASK_CMDACTIE_Pos (11U)
16213#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
16214#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
16215#define SDIO_MASK_TXACTIE_Pos (12U)
16216#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
16217#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
16218#define SDIO_MASK_RXACTIE_Pos (13U)
16219#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
16220#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
16221#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
16222#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
16223#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
16224#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
16225#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
16226#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
16227#define SDIO_MASK_TXFIFOFIE_Pos (16U)
16228#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
16229#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
16230#define SDIO_MASK_RXFIFOFIE_Pos (17U)
16231#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
16232#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
16233#define SDIO_MASK_TXFIFOEIE_Pos (18U)
16234#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
16235#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
16236#define SDIO_MASK_RXFIFOEIE_Pos (19U)
16237#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
16238#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
16239#define SDIO_MASK_TXDAVLIE_Pos (20U)
16240#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
16241#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
16242#define SDIO_MASK_RXDAVLIE_Pos (21U)
16243#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
16244#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
16245#define SDIO_MASK_SDIOITIE_Pos (22U)
16246#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
16247#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
16248
16249/***************** Bit definition for SDIO_FIFOCNT register *****************/
16250#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
16251#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
16252#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
16253
16254/****************** Bit definition for SDIO_FIFO register *******************/
16255#define SDIO_FIFO_FIFODATA_Pos (0U)
16256#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
16257#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
16258
16259/******************************************************************************/
16260/* */
16261/* Serial Peripheral Interface */
16262/* */
16263/******************************************************************************/
16264#define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
16265
16266/******************* Bit definition for SPI_CR1 register ********************/
16267#define SPI_CR1_CPHA_Pos (0U)
16268#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
16269#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
16270#define SPI_CR1_CPOL_Pos (1U)
16271#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
16272#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
16273#define SPI_CR1_MSTR_Pos (2U)
16274#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
16275#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
16276
16277#define SPI_CR1_BR_Pos (3U)
16278#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
16279#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
16280#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
16281#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
16282#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
16283
16284#define SPI_CR1_SPE_Pos (6U)
16285#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
16286#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
16287#define SPI_CR1_LSBFIRST_Pos (7U)
16288#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
16289#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
16290#define SPI_CR1_SSI_Pos (8U)
16291#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
16292#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
16293#define SPI_CR1_SSM_Pos (9U)
16294#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
16295#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
16296#define SPI_CR1_RXONLY_Pos (10U)
16297#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
16298#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
16299#define SPI_CR1_DFF_Pos (11U)
16300#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
16301#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
16302#define SPI_CR1_CRCNEXT_Pos (12U)
16303#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
16304#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
16305#define SPI_CR1_CRCEN_Pos (13U)
16306#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
16307#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
16308#define SPI_CR1_BIDIOE_Pos (14U)
16309#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
16310#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
16311#define SPI_CR1_BIDIMODE_Pos (15U)
16312#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
16313#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
16314
16315/******************* Bit definition for SPI_CR2 register ********************/
16316#define SPI_CR2_RXDMAEN_Pos (0U)
16317#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
16318#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
16319#define SPI_CR2_TXDMAEN_Pos (1U)
16320#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
16321#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
16322#define SPI_CR2_SSOE_Pos (2U)
16323#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
16324#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
16325#define SPI_CR2_FRF_Pos (4U)
16326#define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
16327#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
16328#define SPI_CR2_ERRIE_Pos (5U)
16329#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
16330#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
16331#define SPI_CR2_RXNEIE_Pos (6U)
16332#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
16333#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
16334#define SPI_CR2_TXEIE_Pos (7U)
16335#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
16336#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
16337
16338/******************** Bit definition for SPI_SR register ********************/
16339#define SPI_SR_RXNE_Pos (0U)
16340#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
16341#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
16342#define SPI_SR_TXE_Pos (1U)
16343#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
16344#define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
16345#define SPI_SR_CHSIDE_Pos (2U)
16346#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
16347#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
16348#define SPI_SR_UDR_Pos (3U)
16349#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
16350#define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
16351#define SPI_SR_CRCERR_Pos (4U)
16352#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
16353#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
16354#define SPI_SR_MODF_Pos (5U)
16355#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
16356#define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
16357#define SPI_SR_OVR_Pos (6U)
16358#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
16359#define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
16360#define SPI_SR_BSY_Pos (7U)
16361#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
16362#define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
16363#define SPI_SR_FRE_Pos (8U)
16364#define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
16365#define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
16366
16367/******************** Bit definition for SPI_DR register ********************/
16368#define SPI_DR_DR_Pos (0U)
16369#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
16370#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
16371
16372/******************* Bit definition for SPI_CRCPR register ******************/
16373#define SPI_CRCPR_CRCPOLY_Pos (0U)
16374#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
16375#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
16376
16377/****************** Bit definition for SPI_RXCRCR register ******************/
16378#define SPI_RXCRCR_RXCRC_Pos (0U)
16379#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
16380#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
16381
16382/****************** Bit definition for SPI_TXCRCR register ******************/
16383#define SPI_TXCRCR_TXCRC_Pos (0U)
16384#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
16385#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
16386
16387/****************** Bit definition for SPI_I2SCFGR register *****************/
16388#define SPI_I2SCFGR_CHLEN_Pos (0U)
16389#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
16390#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
16391
16392#define SPI_I2SCFGR_DATLEN_Pos (1U)
16393#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
16394#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
16395#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
16396#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
16397
16398#define SPI_I2SCFGR_CKPOL_Pos (3U)
16399#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
16400#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
16401
16402#define SPI_I2SCFGR_I2SSTD_Pos (4U)
16403#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
16404#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
16405#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
16406#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
16407
16408#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
16409#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
16410#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
16411
16412#define SPI_I2SCFGR_I2SCFG_Pos (8U)
16413#define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
16414#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
16415#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
16416#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
16417
16418#define SPI_I2SCFGR_I2SE_Pos (10U)
16419#define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
16420#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
16421#define SPI_I2SCFGR_I2SMOD_Pos (11U)
16422#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
16423#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
16424#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
16425#define SPI_I2SCFGR_ASTRTEN_Msk (0x1U << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
16426#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
16427
16428/****************** Bit definition for SPI_I2SPR register *******************/
16429#define SPI_I2SPR_I2SDIV_Pos (0U)
16430#define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
16431#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
16432#define SPI_I2SPR_ODD_Pos (8U)
16433#define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
16434#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
16435#define SPI_I2SPR_MCKOE_Pos (9U)
16436#define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
16437#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
16438
16439/******************************************************************************/
16440/* */
16441/* SYSCFG */
16442/* */
16443/******************************************************************************/
16444/****************** Bit definition for SYSCFG_MEMRMP register ***************/
16445#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
16446#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
16447#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
16448#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
16449#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
16450#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
16451#define SYSCFG_MEMRMP_UFB_MODE_Pos (8U)
16452#define SYSCFG_MEMRMP_UFB_MODE_Msk (0x1U << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */
16453#define SYSCFG_MEMRMP_UFB_MODE SYSCFG_MEMRMP_UFB_MODE_Msk /*!< User Flash Bank mode */
16454#define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
16455#define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
16456#define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC memory mapping swap */
16457#define SYSCFG_MEMRMP_SWP_FMC_0 (0x1U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
16458/* Legacy Defines */
16459#define SYSCFG_SWP_FMC SYSCFG_MEMRMP_SWP_FMC
16460/****************** Bit definition for SYSCFG_PMC register ******************/
16461#define SYSCFG_PMC_ADCxDC2_Pos (16U)
16462#define SYSCFG_PMC_ADCxDC2_Msk (0x7U << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
16463#define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */
16464#define SYSCFG_PMC_ADC1DC2_Pos (16U)
16465#define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
16466#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
16467#define SYSCFG_PMC_ADC2DC2_Pos (17U)
16468#define SYSCFG_PMC_ADC2DC2_Msk (0x1U << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */
16469#define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */
16470#define SYSCFG_PMC_ADC3DC2_Pos (18U)
16471#define SYSCFG_PMC_ADC3DC2_Msk (0x1U << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */
16472#define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */
16473#define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
16474#define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
16475#define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */
16476
16477/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
16478#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
16479#define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
16480#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
16481#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
16482#define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
16483#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
16484#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
16485#define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
16486#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
16487#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
16488#define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
16489#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
16490/**
16491 * @brief EXTI0 configuration
16492 */
16493#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
16494#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
16495#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
16496#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
16497#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
16498#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
16499#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
16500#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
16501#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
16502#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
16503#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
16504
16505/**
16506 * @brief EXTI1 configuration
16507 */
16508#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
16509#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
16510#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
16511#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
16512#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
16513#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
16514#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
16515#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
16516#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
16517#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
16518#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
16519
16520/**
16521 * @brief EXTI2 configuration
16522 */
16523#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
16524#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
16525#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
16526#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
16527#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
16528#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
16529#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
16530#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
16531#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
16532#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
16533#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
16534
16535/**
16536 * @brief EXTI3 configuration
16537 */
16538#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
16539#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
16540#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
16541#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
16542#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
16543#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
16544#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
16545#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
16546#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
16547#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
16548#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
16549
16550/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
16551#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
16552#define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
16553#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
16554#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
16555#define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
16556#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
16557#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
16558#define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
16559#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
16560#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
16561#define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
16562#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
16563
16564/**
16565 * @brief EXTI4 configuration
16566 */
16567#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
16568#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
16569#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
16570#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
16571#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
16572#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
16573#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
16574#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
16575#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
16576#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
16577#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
16578
16579/**
16580 * @brief EXTI5 configuration
16581 */
16582#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
16583#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
16584#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
16585#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
16586#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
16587#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
16588#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
16589#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
16590#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
16591#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
16592#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
16593
16594/**
16595 * @brief EXTI6 configuration
16596 */
16597#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
16598#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
16599#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
16600#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
16601#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
16602#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
16603#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
16604#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
16605#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
16606#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
16607#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
16608
16609/**
16610 * @brief EXTI7 configuration
16611 */
16612#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
16613#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
16614#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
16615#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
16616#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
16617#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
16618#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
16619#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
16620#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
16621#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
16622#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
16623
16624/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
16625#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
16626#define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
16627#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
16628#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
16629#define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
16630#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
16631#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
16632#define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
16633#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
16634#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
16635#define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
16636#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
16637
16638/**
16639 * @brief EXTI8 configuration
16640 */
16641#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
16642#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
16643#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
16644#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
16645#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
16646#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
16647#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
16648#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
16649#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
16650#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
16651
16652/**
16653 * @brief EXTI9 configuration
16654 */
16655#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
16656#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
16657#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
16658#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
16659#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
16660#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
16661#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
16662#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
16663#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
16664#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
16665
16666/**
16667 * @brief EXTI10 configuration
16668 */
16669#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
16670#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
16671#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
16672#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
16673#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
16674#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
16675#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
16676#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
16677#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
16678#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
16679
16680/**
16681 * @brief EXTI11 configuration
16682 */
16683#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
16684#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
16685#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
16686#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
16687#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
16688#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
16689#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
16690#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
16691#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
16692#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
16693
16694
16695/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
16696#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
16697#define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
16698#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
16699#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
16700#define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
16701#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
16702#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
16703#define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
16704#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
16705#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
16706#define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
16707#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
16708
16709/**
16710 * @brief EXTI12 configuration
16711 */
16712#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
16713#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
16714#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
16715#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
16716#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
16717#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
16718#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
16719#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
16720#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
16721#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
16722
16723/**
16724 * @brief EXTI13 configuration
16725 */
16726#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
16727#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
16728#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
16729#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
16730#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
16731#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
16732#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
16733#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
16734#define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */
16735#define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */
16736
16737/**
16738 * @brief EXTI14 configuration
16739 */
16740#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
16741#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
16742#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
16743#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
16744#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
16745#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
16746#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
16747#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
16748#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
16749#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
16750
16751/**
16752 * @brief EXTI15 configuration
16753 */
16754#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
16755#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
16756#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
16757#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
16758#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
16759#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
16760#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
16761#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
16762#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
16763#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
16764
16765/****************** Bit definition for SYSCFG_CMPCR register ****************/
16766#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
16767#define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
16768#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
16769#define SYSCFG_CMPCR_READY_Pos (8U)
16770#define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
16771#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
16772
16773/******************************************************************************/
16774/* */
16775/* TIM */
16776/* */
16777/******************************************************************************/
16778/******************* Bit definition for TIM_CR1 register ********************/
16779#define TIM_CR1_CEN_Pos (0U)
16780#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
16781#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
16782#define TIM_CR1_UDIS_Pos (1U)
16783#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
16784#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
16785#define TIM_CR1_URS_Pos (2U)
16786#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
16787#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
16788#define TIM_CR1_OPM_Pos (3U)
16789#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
16790#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
16791#define TIM_CR1_DIR_Pos (4U)
16792#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
16793#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
16794
16795#define TIM_CR1_CMS_Pos (5U)
16796#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
16797#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
16798#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
16799#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
16800
16801#define TIM_CR1_ARPE_Pos (7U)
16802#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
16803#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
16804
16805#define TIM_CR1_CKD_Pos (8U)
16806#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
16807#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
16808#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
16809#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
16810
16811/******************* Bit definition for TIM_CR2 register ********************/
16812#define TIM_CR2_CCPC_Pos (0U)
16813#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
16814#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
16815#define TIM_CR2_CCUS_Pos (2U)
16816#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
16817#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
16818#define TIM_CR2_CCDS_Pos (3U)
16819#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
16820#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
16821
16822#define TIM_CR2_MMS_Pos (4U)
16823#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
16824#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
16825#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
16826#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
16827#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
16828
16829#define TIM_CR2_TI1S_Pos (7U)
16830#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
16831#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
16832#define TIM_CR2_OIS1_Pos (8U)
16833#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
16834#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
16835#define TIM_CR2_OIS1N_Pos (9U)
16836#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
16837#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
16838#define TIM_CR2_OIS2_Pos (10U)
16839#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
16840#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
16841#define TIM_CR2_OIS2N_Pos (11U)
16842#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
16843#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
16844#define TIM_CR2_OIS3_Pos (12U)
16845#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
16846#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
16847#define TIM_CR2_OIS3N_Pos (13U)
16848#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
16849#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
16850#define TIM_CR2_OIS4_Pos (14U)
16851#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
16852#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
16853
16854/******************* Bit definition for TIM_SMCR register *******************/
16855#define TIM_SMCR_SMS_Pos (0U)
16856#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
16857#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
16858#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
16859#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
16860#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
16861
16862#define TIM_SMCR_TS_Pos (4U)
16863#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
16864#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
16865#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
16866#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
16867#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
16868
16869#define TIM_SMCR_MSM_Pos (7U)
16870#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
16871#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
16872
16873#define TIM_SMCR_ETF_Pos (8U)
16874#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
16875#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
16876#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
16877#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
16878#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
16879#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
16880
16881#define TIM_SMCR_ETPS_Pos (12U)
16882#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
16883#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
16884#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
16885#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
16886
16887#define TIM_SMCR_ECE_Pos (14U)
16888#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
16889#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
16890#define TIM_SMCR_ETP_Pos (15U)
16891#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
16892#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
16893
16894/******************* Bit definition for TIM_DIER register *******************/
16895#define TIM_DIER_UIE_Pos (0U)
16896#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
16897#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
16898#define TIM_DIER_CC1IE_Pos (1U)
16899#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
16900#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
16901#define TIM_DIER_CC2IE_Pos (2U)
16902#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
16903#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
16904#define TIM_DIER_CC3IE_Pos (3U)
16905#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
16906#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
16907#define TIM_DIER_CC4IE_Pos (4U)
16908#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
16909#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
16910#define TIM_DIER_COMIE_Pos (5U)
16911#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
16912#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
16913#define TIM_DIER_TIE_Pos (6U)
16914#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
16915#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
16916#define TIM_DIER_BIE_Pos (7U)
16917#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
16918#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
16919#define TIM_DIER_UDE_Pos (8U)
16920#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
16921#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
16922#define TIM_DIER_CC1DE_Pos (9U)
16923#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
16924#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
16925#define TIM_DIER_CC2DE_Pos (10U)
16926#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
16927#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
16928#define TIM_DIER_CC3DE_Pos (11U)
16929#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
16930#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
16931#define TIM_DIER_CC4DE_Pos (12U)
16932#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
16933#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
16934#define TIM_DIER_COMDE_Pos (13U)
16935#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
16936#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
16937#define TIM_DIER_TDE_Pos (14U)
16938#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
16939#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
16940
16941/******************** Bit definition for TIM_SR register ********************/
16942#define TIM_SR_UIF_Pos (0U)
16943#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
16944#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
16945#define TIM_SR_CC1IF_Pos (1U)
16946#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
16947#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
16948#define TIM_SR_CC2IF_Pos (2U)
16949#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
16950#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
16951#define TIM_SR_CC3IF_Pos (3U)
16952#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
16953#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
16954#define TIM_SR_CC4IF_Pos (4U)
16955#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
16956#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
16957#define TIM_SR_COMIF_Pos (5U)
16958#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
16959#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
16960#define TIM_SR_TIF_Pos (6U)
16961#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
16962#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
16963#define TIM_SR_BIF_Pos (7U)
16964#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
16965#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
16966#define TIM_SR_CC1OF_Pos (9U)
16967#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
16968#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
16969#define TIM_SR_CC2OF_Pos (10U)
16970#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
16971#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
16972#define TIM_SR_CC3OF_Pos (11U)
16973#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
16974#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
16975#define TIM_SR_CC4OF_Pos (12U)
16976#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
16977#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
16978
16979/******************* Bit definition for TIM_EGR register ********************/
16980#define TIM_EGR_UG_Pos (0U)
16981#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
16982#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
16983#define TIM_EGR_CC1G_Pos (1U)
16984#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
16985#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
16986#define TIM_EGR_CC2G_Pos (2U)
16987#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
16988#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
16989#define TIM_EGR_CC3G_Pos (3U)
16990#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
16991#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
16992#define TIM_EGR_CC4G_Pos (4U)
16993#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
16994#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
16995#define TIM_EGR_COMG_Pos (5U)
16996#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
16997#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
16998#define TIM_EGR_TG_Pos (6U)
16999#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
17000#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
17001#define TIM_EGR_BG_Pos (7U)
17002#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
17003#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
17004
17005/****************** Bit definition for TIM_CCMR1 register *******************/
17006#define TIM_CCMR1_CC1S_Pos (0U)
17007#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
17008#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
17009#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
17010#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
17011
17012#define TIM_CCMR1_OC1FE_Pos (2U)
17013#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
17014#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
17015#define TIM_CCMR1_OC1PE_Pos (3U)
17016#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
17017#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
17018
17019#define TIM_CCMR1_OC1M_Pos (4U)
17020#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
17021#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
17022#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
17023#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
17024#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
17025
17026#define TIM_CCMR1_OC1CE_Pos (7U)
17027#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
17028#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
17029
17030#define TIM_CCMR1_CC2S_Pos (8U)
17031#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
17032#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
17033#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
17034#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
17035
17036#define TIM_CCMR1_OC2FE_Pos (10U)
17037#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
17038#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
17039#define TIM_CCMR1_OC2PE_Pos (11U)
17040#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
17041#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
17042
17043#define TIM_CCMR1_OC2M_Pos (12U)
17044#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
17045#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
17046#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
17047#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
17048#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
17049
17050#define TIM_CCMR1_OC2CE_Pos (15U)
17051#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
17052#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
17053
17054/*----------------------------------------------------------------------------*/
17055
17056#define TIM_CCMR1_IC1PSC_Pos (2U)
17057#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
17058#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
17059#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
17060#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
17061
17062#define TIM_CCMR1_IC1F_Pos (4U)
17063#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
17064#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
17065#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
17066#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
17067#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
17068#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
17069
17070#define TIM_CCMR1_IC2PSC_Pos (10U)
17071#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
17072#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
17073#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
17074#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
17075
17076#define TIM_CCMR1_IC2F_Pos (12U)
17077#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
17078#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
17079#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
17080#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
17081#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
17082#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
17083
17084/****************** Bit definition for TIM_CCMR2 register *******************/
17085#define TIM_CCMR2_CC3S_Pos (0U)
17086#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
17087#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
17088#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
17089#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
17090
17091#define TIM_CCMR2_OC3FE_Pos (2U)
17092#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
17093#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
17094#define TIM_CCMR2_OC3PE_Pos (3U)
17095#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
17096#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
17097
17098#define TIM_CCMR2_OC3M_Pos (4U)
17099#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
17100#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
17101#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
17102#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
17103#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
17104
17105#define TIM_CCMR2_OC3CE_Pos (7U)
17106#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
17107#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
17108
17109#define TIM_CCMR2_CC4S_Pos (8U)
17110#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
17111#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
17112#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
17113#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
17114
17115#define TIM_CCMR2_OC4FE_Pos (10U)
17116#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
17117#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
17118#define TIM_CCMR2_OC4PE_Pos (11U)
17119#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
17120#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
17121
17122#define TIM_CCMR2_OC4M_Pos (12U)
17123#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
17124#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
17125#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
17126#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
17127#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
17128
17129#define TIM_CCMR2_OC4CE_Pos (15U)
17130#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
17131#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
17132
17133/*----------------------------------------------------------------------------*/
17134
17135#define TIM_CCMR2_IC3PSC_Pos (2U)
17136#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
17137#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
17138#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
17139#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
17140
17141#define TIM_CCMR2_IC3F_Pos (4U)
17142#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
17143#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
17144#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
17145#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
17146#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
17147#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
17148
17149#define TIM_CCMR2_IC4PSC_Pos (10U)
17150#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
17151#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
17152#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
17153#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
17154
17155#define TIM_CCMR2_IC4F_Pos (12U)
17156#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
17157#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
17158#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
17159#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
17160#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
17161#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
17162
17163/******************* Bit definition for TIM_CCER register *******************/
17164#define TIM_CCER_CC1E_Pos (0U)
17165#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
17166#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
17167#define TIM_CCER_CC1P_Pos (1U)
17168#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
17169#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
17170#define TIM_CCER_CC1NE_Pos (2U)
17171#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
17172#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
17173#define TIM_CCER_CC1NP_Pos (3U)
17174#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
17175#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
17176#define TIM_CCER_CC2E_Pos (4U)
17177#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
17178#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
17179#define TIM_CCER_CC2P_Pos (5U)
17180#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
17181#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
17182#define TIM_CCER_CC2NE_Pos (6U)
17183#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
17184#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
17185#define TIM_CCER_CC2NP_Pos (7U)
17186#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
17187#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
17188#define TIM_CCER_CC3E_Pos (8U)
17189#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
17190#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
17191#define TIM_CCER_CC3P_Pos (9U)
17192#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
17193#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
17194#define TIM_CCER_CC3NE_Pos (10U)
17195#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
17196#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
17197#define TIM_CCER_CC3NP_Pos (11U)
17198#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
17199#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
17200#define TIM_CCER_CC4E_Pos (12U)
17201#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
17202#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
17203#define TIM_CCER_CC4P_Pos (13U)
17204#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
17205#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
17206#define TIM_CCER_CC4NP_Pos (15U)
17207#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
17208#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
17209
17210/******************* Bit definition for TIM_CNT register ********************/
17211#define TIM_CNT_CNT_Pos (0U)
17212#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
17213#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
17214
17215/******************* Bit definition for TIM_PSC register ********************/
17216#define TIM_PSC_PSC_Pos (0U)
17217#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
17218#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
17219
17220/******************* Bit definition for TIM_ARR register ********************/
17221#define TIM_ARR_ARR_Pos (0U)
17222#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
17223#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
17224
17225/******************* Bit definition for TIM_RCR register ********************/
17226#define TIM_RCR_REP_Pos (0U)
17227#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
17228#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
17229
17230/******************* Bit definition for TIM_CCR1 register *******************/
17231#define TIM_CCR1_CCR1_Pos (0U)
17232#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
17233#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
17234
17235/******************* Bit definition for TIM_CCR2 register *******************/
17236#define TIM_CCR2_CCR2_Pos (0U)
17237#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
17238#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
17239
17240/******************* Bit definition for TIM_CCR3 register *******************/
17241#define TIM_CCR3_CCR3_Pos (0U)
17242#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
17243#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
17244
17245/******************* Bit definition for TIM_CCR4 register *******************/
17246#define TIM_CCR4_CCR4_Pos (0U)
17247#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
17248#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
17249
17250/******************* Bit definition for TIM_BDTR register *******************/
17251#define TIM_BDTR_DTG_Pos (0U)
17252#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
17253#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
17254#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
17255#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
17256#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
17257#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
17258#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
17259#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
17260#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
17261#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
17262
17263#define TIM_BDTR_LOCK_Pos (8U)
17264#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
17265#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
17266#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
17267#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
17268
17269#define TIM_BDTR_OSSI_Pos (10U)
17270#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
17271#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
17272#define TIM_BDTR_OSSR_Pos (11U)
17273#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
17274#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
17275#define TIM_BDTR_BKE_Pos (12U)
17276#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
17277#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
17278#define TIM_BDTR_BKP_Pos (13U)
17279#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
17280#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
17281#define TIM_BDTR_AOE_Pos (14U)
17282#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
17283#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
17284#define TIM_BDTR_MOE_Pos (15U)
17285#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
17286#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
17287
17288/******************* Bit definition for TIM_DCR register ********************/
17289#define TIM_DCR_DBA_Pos (0U)
17290#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
17291#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
17292#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
17293#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
17294#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
17295#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
17296#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
17297
17298#define TIM_DCR_DBL_Pos (8U)
17299#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
17300#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
17301#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
17302#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
17303#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
17304#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
17305#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
17306
17307/******************* Bit definition for TIM_DMAR register *******************/
17308#define TIM_DMAR_DMAB_Pos (0U)
17309#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
17310#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
17311
17312/******************* Bit definition for TIM_OR register *********************/
17313#define TIM_OR_TI1_RMP_Pos (0U)
17314#define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
17315#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
17316#define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
17317#define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
17318
17319#define TIM_OR_TI4_RMP_Pos (6U)
17320#define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
17321#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
17322#define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
17323#define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
17324#define TIM_OR_ITR1_RMP_Pos (10U)
17325#define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
17326#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
17327#define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
17328#define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
17329
17330
17331/******************************************************************************/
17332/* */
17333/* Universal Synchronous Asynchronous Receiver Transmitter */
17334/* */
17335/******************************************************************************/
17336/******************* Bit definition for USART_SR register *******************/
17337#define USART_SR_PE_Pos (0U)
17338#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
17339#define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
17340#define USART_SR_FE_Pos (1U)
17341#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
17342#define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
17343#define USART_SR_NE_Pos (2U)
17344#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
17345#define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
17346#define USART_SR_ORE_Pos (3U)
17347#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
17348#define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
17349#define USART_SR_IDLE_Pos (4U)
17350#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
17351#define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
17352#define USART_SR_RXNE_Pos (5U)
17353#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
17354#define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
17355#define USART_SR_TC_Pos (6U)
17356#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
17357#define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
17358#define USART_SR_TXE_Pos (7U)
17359#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
17360#define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
17361#define USART_SR_LBD_Pos (8U)
17362#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
17363#define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
17364#define USART_SR_CTS_Pos (9U)
17365#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
17366#define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
17367
17368/******************* Bit definition for USART_DR register *******************/
17369#define USART_DR_DR_Pos (0U)
17370#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
17371#define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
17372
17373/****************** Bit definition for USART_BRR register *******************/
17374#define USART_BRR_DIV_Fraction_Pos (0U)
17375#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
17376#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
17377#define USART_BRR_DIV_Mantissa_Pos (4U)
17378#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
17379#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
17380
17381/****************** Bit definition for USART_CR1 register *******************/
17382#define USART_CR1_SBK_Pos (0U)
17383#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
17384#define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
17385#define USART_CR1_RWU_Pos (1U)
17386#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
17387#define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
17388#define USART_CR1_RE_Pos (2U)
17389#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
17390#define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
17391#define USART_CR1_TE_Pos (3U)
17392#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
17393#define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
17394#define USART_CR1_IDLEIE_Pos (4U)
17395#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
17396#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
17397#define USART_CR1_RXNEIE_Pos (5U)
17398#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
17399#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
17400#define USART_CR1_TCIE_Pos (6U)
17401#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
17402#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
17403#define USART_CR1_TXEIE_Pos (7U)
17404#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
17405#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */
17406#define USART_CR1_PEIE_Pos (8U)
17407#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
17408#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
17409#define USART_CR1_PS_Pos (9U)
17410#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
17411#define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
17412#define USART_CR1_PCE_Pos (10U)
17413#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
17414#define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
17415#define USART_CR1_WAKE_Pos (11U)
17416#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
17417#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
17418#define USART_CR1_M_Pos (12U)
17419#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
17420#define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
17421#define USART_CR1_UE_Pos (13U)
17422#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
17423#define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
17424#define USART_CR1_OVER8_Pos (15U)
17425#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
17426#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
17427
17428/****************** Bit definition for USART_CR2 register *******************/
17429#define USART_CR2_ADD_Pos (0U)
17430#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
17431#define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
17432#define USART_CR2_LBDL_Pos (5U)
17433#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
17434#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
17435#define USART_CR2_LBDIE_Pos (6U)
17436#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
17437#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
17438#define USART_CR2_LBCL_Pos (8U)
17439#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
17440#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
17441#define USART_CR2_CPHA_Pos (9U)
17442#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
17443#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
17444#define USART_CR2_CPOL_Pos (10U)
17445#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
17446#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
17447#define USART_CR2_CLKEN_Pos (11U)
17448#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
17449#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
17450
17451#define USART_CR2_STOP_Pos (12U)
17452#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
17453#define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
17454#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
17455#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
17456
17457#define USART_CR2_LINEN_Pos (14U)
17458#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
17459#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
17460
17461/****************** Bit definition for USART_CR3 register *******************/
17462#define USART_CR3_EIE_Pos (0U)
17463#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
17464#define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
17465#define USART_CR3_IREN_Pos (1U)
17466#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
17467#define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
17468#define USART_CR3_IRLP_Pos (2U)
17469#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
17470#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
17471#define USART_CR3_HDSEL_Pos (3U)
17472#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
17473#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
17474#define USART_CR3_NACK_Pos (4U)
17475#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
17476#define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
17477#define USART_CR3_SCEN_Pos (5U)
17478#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
17479#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
17480#define USART_CR3_DMAR_Pos (6U)
17481#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
17482#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
17483#define USART_CR3_DMAT_Pos (7U)
17484#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
17485#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
17486#define USART_CR3_RTSE_Pos (8U)
17487#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
17488#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
17489#define USART_CR3_CTSE_Pos (9U)
17490#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
17491#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
17492#define USART_CR3_CTSIE_Pos (10U)
17493#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
17494#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
17495#define USART_CR3_ONEBIT_Pos (11U)
17496#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
17497#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
17498
17499/****************** Bit definition for USART_GTPR register ******************/
17500#define USART_GTPR_PSC_Pos (0U)
17501#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
17502#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
17503#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
17504#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
17505#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
17506#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
17507#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
17508#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
17509#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
17510#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
17511
17512#define USART_GTPR_GT_Pos (8U)
17513#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
17514#define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
17515
17516/******************************************************************************/
17517/* */
17518/* Window WATCHDOG */
17519/* */
17520/******************************************************************************/
17521/******************* Bit definition for WWDG_CR register ********************/
17522#define WWDG_CR_T_Pos (0U)
17523#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
17524#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
17525#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
17526#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
17527#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
17528#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
17529#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
17530#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
17531#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
17532/* Legacy defines */
17533#define WWDG_CR_T0 WWDG_CR_T_0
17534#define WWDG_CR_T1 WWDG_CR_T_1
17535#define WWDG_CR_T2 WWDG_CR_T_2
17536#define WWDG_CR_T3 WWDG_CR_T_3
17537#define WWDG_CR_T4 WWDG_CR_T_4
17538#define WWDG_CR_T5 WWDG_CR_T_5
17539#define WWDG_CR_T6 WWDG_CR_T_6
17540
17541#define WWDG_CR_WDGA_Pos (7U)
17542#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
17543#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
17544
17545/******************* Bit definition for WWDG_CFR register *******************/
17546#define WWDG_CFR_W_Pos (0U)
17547#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
17548#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
17549#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
17550#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
17551#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
17552#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
17553#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
17554#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
17555#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
17556/* Legacy defines */
17557#define WWDG_CFR_W0 WWDG_CFR_W_0
17558#define WWDG_CFR_W1 WWDG_CFR_W_1
17559#define WWDG_CFR_W2 WWDG_CFR_W_2
17560#define WWDG_CFR_W3 WWDG_CFR_W_3
17561#define WWDG_CFR_W4 WWDG_CFR_W_4
17562#define WWDG_CFR_W5 WWDG_CFR_W_5
17563#define WWDG_CFR_W6 WWDG_CFR_W_6
17564
17565#define WWDG_CFR_WDGTB_Pos (7U)
17566#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
17567#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
17568#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
17569#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
17570/* Legacy defines */
17571#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
17572#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
17573
17574#define WWDG_CFR_EWI_Pos (9U)
17575#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
17576#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
17577
17578/******************* Bit definition for WWDG_SR register ********************/
17579#define WWDG_SR_EWIF_Pos (0U)
17580#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
17581#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
17582
17583
17584/******************************************************************************/
17585/* */
17586/* DBG */
17587/* */
17588/******************************************************************************/
17589/******************** Bit definition for DBGMCU_IDCODE register *************/
17590#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
17591#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
17592#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
17593#define DBGMCU_IDCODE_REV_ID_Pos (16U)
17594#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
17595#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
17596
17597/******************** Bit definition for DBGMCU_CR register *****************/
17598#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
17599#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
17600#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
17601#define DBGMCU_CR_DBG_STOP_Pos (1U)
17602#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
17603#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
17604#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
17605#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
17606#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
17607#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
17608#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
17609#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
17610
17611#define DBGMCU_CR_TRACE_MODE_Pos (6U)
17612#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
17613#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
17614#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
17615#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
17616
17617/******************** Bit definition for DBGMCU_APB1_FZ register ************/
17618#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
17619#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
17620#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
17621#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
17622#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
17623#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
17624#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
17625#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
17626#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
17627#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
17628#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
17629#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
17630#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
17631#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
17632#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
17633#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
17634#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
17635#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
17636#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
17637#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
17638#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
17639#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
17640#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
17641#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
17642#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
17643#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
17644#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
17645#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
17646#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
17647#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
17648#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
17649#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
17650#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
17651#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
17652#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
17653#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
17654#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
17655#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
17656#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
17657#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
17658#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
17659#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
17660#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
17661#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
17662#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
17663#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
17664#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
17665#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
17666#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
17667#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
17668#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
17669#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
17670#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
17671#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
17672/* Old IWDGSTOP bit definition, maintained for legacy purpose */
17673#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
17674
17675/******************** Bit definition for DBGMCU_APB2_FZ register ************/
17676#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
17677#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
17678#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
17679#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
17680#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
17681#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
17682#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
17683#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
17684#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
17685#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
17686#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
17687#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
17688#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
17689#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
17690#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
17691
17692/******************************************************************************/
17693/* */
17694/* Ethernet MAC Registers bits definitions */
17695/* */
17696/******************************************************************************/
17697/* Bit definition for Ethernet MAC Control Register register */
17698#define ETH_MACCR_WD_Pos (23U)
17699#define ETH_MACCR_WD_Msk (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
17700#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
17701#define ETH_MACCR_JD_Pos (22U)
17702#define ETH_MACCR_JD_Msk (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
17703#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
17704#define ETH_MACCR_IFG_Pos (17U)
17705#define ETH_MACCR_IFG_Msk (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
17706#define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
17707#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
17708#define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
17709#define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
17710#define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
17711#define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
17712#define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
17713#define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
17714#define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
17715#define ETH_MACCR_CSD_Pos (16U)
17716#define ETH_MACCR_CSD_Msk (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
17717#define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
17718#define ETH_MACCR_FES_Pos (14U)
17719#define ETH_MACCR_FES_Msk (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
17720#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
17721#define ETH_MACCR_ROD_Pos (13U)
17722#define ETH_MACCR_ROD_Msk (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
17723#define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
17724#define ETH_MACCR_LM_Pos (12U)
17725#define ETH_MACCR_LM_Msk (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
17726#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
17727#define ETH_MACCR_DM_Pos (11U)
17728#define ETH_MACCR_DM_Msk (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
17729#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
17730#define ETH_MACCR_IPCO_Pos (10U)
17731#define ETH_MACCR_IPCO_Msk (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
17732#define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
17733#define ETH_MACCR_RD_Pos (9U)
17734#define ETH_MACCR_RD_Msk (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
17735#define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
17736#define ETH_MACCR_APCS_Pos (7U)
17737#define ETH_MACCR_APCS_Msk (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
17738#define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
17739#define ETH_MACCR_BL_Pos (5U)
17740#define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
17741#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
17742 a transmission attempt during retries after a collision: 0 =< r <2^k */
17743#define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
17744#define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
17745#define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
17746#define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
17747#define ETH_MACCR_DC_Pos (4U)
17748#define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
17749#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
17750#define ETH_MACCR_TE_Pos (3U)
17751#define ETH_MACCR_TE_Msk (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
17752#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
17753#define ETH_MACCR_RE_Pos (2U)
17754#define ETH_MACCR_RE_Msk (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
17755#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
17756
17757/* Bit definition for Ethernet MAC Frame Filter Register */
17758#define ETH_MACFFR_RA_Pos (31U)
17759#define ETH_MACFFR_RA_Msk (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
17760#define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
17761#define ETH_MACFFR_HPF_Pos (10U)
17762#define ETH_MACFFR_HPF_Msk (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
17763#define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
17764#define ETH_MACFFR_SAF_Pos (9U)
17765#define ETH_MACFFR_SAF_Msk (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
17766#define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
17767#define ETH_MACFFR_SAIF_Pos (8U)
17768#define ETH_MACFFR_SAIF_Msk (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
17769#define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
17770#define ETH_MACFFR_PCF_Pos (6U)
17771#define ETH_MACFFR_PCF_Msk (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
17772#define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
17773#define ETH_MACFFR_PCF_BlockAll_Pos (6U)
17774#define ETH_MACFFR_PCF_BlockAll_Msk (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
17775#define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
17776#define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
17777#define ETH_MACFFR_PCF_ForwardAll_Msk (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
17778#define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
17779#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
17780#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
17781#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
17782#define ETH_MACFFR_BFD_Pos (5U)
17783#define ETH_MACFFR_BFD_Msk (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
17784#define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
17785#define ETH_MACFFR_PAM_Pos (4U)
17786#define ETH_MACFFR_PAM_Msk (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
17787#define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
17788#define ETH_MACFFR_DAIF_Pos (3U)
17789#define ETH_MACFFR_DAIF_Msk (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
17790#define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
17791#define ETH_MACFFR_HM_Pos (2U)
17792#define ETH_MACFFR_HM_Msk (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
17793#define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
17794#define ETH_MACFFR_HU_Pos (1U)
17795#define ETH_MACFFR_HU_Msk (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
17796#define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
17797#define ETH_MACFFR_PM_Pos (0U)
17798#define ETH_MACFFR_PM_Msk (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
17799#define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
17800
17801/* Bit definition for Ethernet MAC Hash Table High Register */
17802#define ETH_MACHTHR_HTH_Pos (0U)
17803#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
17804#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
17805
17806/* Bit definition for Ethernet MAC Hash Table Low Register */
17807#define ETH_MACHTLR_HTL_Pos (0U)
17808#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
17809#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
17810
17811/* Bit definition for Ethernet MAC MII Address Register */
17812#define ETH_MACMIIAR_PA_Pos (11U)
17813#define ETH_MACMIIAR_PA_Msk (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
17814#define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
17815#define ETH_MACMIIAR_MR_Pos (6U)
17816#define ETH_MACMIIAR_MR_Msk (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
17817#define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
17818#define ETH_MACMIIAR_CR_Pos (2U)
17819#define ETH_MACMIIAR_CR_Msk (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
17820#define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
17821#define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
17822#define ETH_MACMIIAR_CR_Div62_Pos (2U)
17823#define ETH_MACMIIAR_CR_Div62_Msk (0x1U << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
17824#define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
17825#define ETH_MACMIIAR_CR_Div16_Pos (3U)
17826#define ETH_MACMIIAR_CR_Div16_Msk (0x1U << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
17827#define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
17828#define ETH_MACMIIAR_CR_Div26_Pos (2U)
17829#define ETH_MACMIIAR_CR_Div26_Msk (0x3U << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
17830#define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
17831#define ETH_MACMIIAR_CR_Div102_Pos (4U)
17832#define ETH_MACMIIAR_CR_Div102_Msk (0x1U << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
17833#define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
17834#define ETH_MACMIIAR_MW_Pos (1U)
17835#define ETH_MACMIIAR_MW_Msk (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
17836#define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
17837#define ETH_MACMIIAR_MB_Pos (0U)
17838#define ETH_MACMIIAR_MB_Msk (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
17839#define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
17840
17841/* Bit definition for Ethernet MAC MII Data Register */
17842#define ETH_MACMIIDR_MD_Pos (0U)
17843#define ETH_MACMIIDR_MD_Msk (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
17844#define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
17845
17846/* Bit definition for Ethernet MAC Flow Control Register */
17847#define ETH_MACFCR_PT_Pos (16U)
17848#define ETH_MACFCR_PT_Msk (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
17849#define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
17850#define ETH_MACFCR_ZQPD_Pos (7U)
17851#define ETH_MACFCR_ZQPD_Msk (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
17852#define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
17853#define ETH_MACFCR_PLT_Pos (4U)
17854#define ETH_MACFCR_PLT_Msk (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
17855#define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
17856#define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
17857#define ETH_MACFCR_PLT_Minus28_Pos (4U)
17858#define ETH_MACFCR_PLT_Minus28_Msk (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
17859#define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
17860#define ETH_MACFCR_PLT_Minus144_Pos (5U)
17861#define ETH_MACFCR_PLT_Minus144_Msk (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
17862#define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
17863#define ETH_MACFCR_PLT_Minus256_Pos (4U)
17864#define ETH_MACFCR_PLT_Minus256_Msk (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
17865#define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
17866#define ETH_MACFCR_UPFD_Pos (3U)
17867#define ETH_MACFCR_UPFD_Msk (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
17868#define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
17869#define ETH_MACFCR_RFCE_Pos (2U)
17870#define ETH_MACFCR_RFCE_Msk (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
17871#define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
17872#define ETH_MACFCR_TFCE_Pos (1U)
17873#define ETH_MACFCR_TFCE_Msk (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
17874#define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
17875#define ETH_MACFCR_FCBBPA_Pos (0U)
17876#define ETH_MACFCR_FCBBPA_Msk (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
17877#define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
17878
17879/* Bit definition for Ethernet MAC VLAN Tag Register */
17880#define ETH_MACVLANTR_VLANTC_Pos (16U)
17881#define ETH_MACVLANTR_VLANTC_Msk (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
17882#define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
17883#define ETH_MACVLANTR_VLANTI_Pos (0U)
17884#define ETH_MACVLANTR_VLANTI_Msk (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
17885#define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
17886
17887/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
17888#define ETH_MACRWUFFR_D_Pos (0U)
17889#define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
17890#define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
17891/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
17892 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
17893/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
17894 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
17895 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
17896 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
17897 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
17898 RSVD - Filter1 Command - RSVD - Filter0 Command
17899 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
17900 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
17901 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
17902
17903/* Bit definition for Ethernet MAC PMT Control and Status Register */
17904#define ETH_MACPMTCSR_WFFRPR_Pos (31U)
17905#define ETH_MACPMTCSR_WFFRPR_Msk (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
17906#define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
17907#define ETH_MACPMTCSR_GU_Pos (9U)
17908#define ETH_MACPMTCSR_GU_Msk (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
17909#define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
17910#define ETH_MACPMTCSR_WFR_Pos (6U)
17911#define ETH_MACPMTCSR_WFR_Msk (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
17912#define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
17913#define ETH_MACPMTCSR_MPR_Pos (5U)
17914#define ETH_MACPMTCSR_MPR_Msk (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
17915#define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
17916#define ETH_MACPMTCSR_WFE_Pos (2U)
17917#define ETH_MACPMTCSR_WFE_Msk (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
17918#define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
17919#define ETH_MACPMTCSR_MPE_Pos (1U)
17920#define ETH_MACPMTCSR_MPE_Msk (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
17921#define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
17922#define ETH_MACPMTCSR_PD_Pos (0U)
17923#define ETH_MACPMTCSR_PD_Msk (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
17924#define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
17925
17926/* Bit definition for Ethernet MAC debug Register */
17927#define ETH_MACDBGR_TFF_Pos (25U)
17928#define ETH_MACDBGR_TFF_Msk (0x1U << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
17929#define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
17930#define ETH_MACDBGR_TFNE_Pos (24U)
17931#define ETH_MACDBGR_TFNE_Msk (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
17932#define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
17933#define ETH_MACDBGR_TFWA_Pos (22U)
17934#define ETH_MACDBGR_TFWA_Msk (0x1U << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */
17935#define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
17936#define ETH_MACDBGR_TFRS_Pos (20U)
17937#define ETH_MACDBGR_TFRS_Msk (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
17938#define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
17939#define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
17940#define ETH_MACDBGR_TFRS_WRITING_Msk (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
17941#define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
17942#define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
17943#define ETH_MACDBGR_TFRS_WAITING_Msk (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
17944#define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
17945#define ETH_MACDBGR_TFRS_READ_Pos (20U)
17946#define ETH_MACDBGR_TFRS_READ_Msk (0x1U << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
17947#define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
17948#define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
17949#define ETH_MACDBGR_MTP_Pos (19U)
17950#define ETH_MACDBGR_MTP_Msk (0x1U << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
17951#define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
17952#define ETH_MACDBGR_MTFCS_Pos (17U)
17953#define ETH_MACDBGR_MTFCS_Msk (0x3U << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
17954#define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
17955#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
17956#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
17957#define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
17958#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
17959#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
17960#define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
17961#define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
17962#define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
17963#define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
17964#define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
17965#define ETH_MACDBGR_MMTEA_Pos (16U)
17966#define ETH_MACDBGR_MMTEA_Msk (0x1U << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
17967#define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
17968#define ETH_MACDBGR_RFFL_Pos (8U)
17969#define ETH_MACDBGR_RFFL_Msk (0x3U << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
17970#define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
17971#define ETH_MACDBGR_RFFL_FULL_Pos (8U)
17972#define ETH_MACDBGR_RFFL_FULL_Msk (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
17973#define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
17974#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
17975#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
17976#define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
17977#define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
17978#define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
17979#define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
17980#define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
17981#define ETH_MACDBGR_RFRCS_Pos (5U)
17982#define ETH_MACDBGR_RFRCS_Msk (0x3U << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
17983#define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
17984#define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
17985#define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
17986#define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
17987#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
17988#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
17989#define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
17990#define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
17991#define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
17992#define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
17993#define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
17994#define ETH_MACDBGR_RFWRA_Pos (4U)
17995#define ETH_MACDBGR_RFWRA_Msk (0x1U << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
17996#define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
17997#define ETH_MACDBGR_MSFRWCS_Pos (1U)
17998#define ETH_MACDBGR_MSFRWCS_Msk (0x3U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
17999#define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
18000#define ETH_MACDBGR_MSFRWCS_1 (0x2U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
18001#define ETH_MACDBGR_MSFRWCS_0 (0x1U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
18002#define ETH_MACDBGR_MMRPEA_Pos (0U)
18003#define ETH_MACDBGR_MMRPEA_Msk (0x1U << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
18004#define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
18005
18006/* Bit definition for Ethernet MAC Status Register */
18007#define ETH_MACSR_TSTS_Pos (9U)
18008#define ETH_MACSR_TSTS_Msk (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
18009#define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
18010#define ETH_MACSR_MMCTS_Pos (6U)
18011#define ETH_MACSR_MMCTS_Msk (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
18012#define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
18013#define ETH_MACSR_MMMCRS_Pos (5U)
18014#define ETH_MACSR_MMMCRS_Msk (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
18015#define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
18016#define ETH_MACSR_MMCS_Pos (4U)
18017#define ETH_MACSR_MMCS_Msk (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
18018#define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
18019#define ETH_MACSR_PMTS_Pos (3U)
18020#define ETH_MACSR_PMTS_Msk (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
18021#define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
18022
18023/* Bit definition for Ethernet MAC Interrupt Mask Register */
18024#define ETH_MACIMR_TSTIM_Pos (9U)
18025#define ETH_MACIMR_TSTIM_Msk (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
18026#define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
18027#define ETH_MACIMR_PMTIM_Pos (3U)
18028#define ETH_MACIMR_PMTIM_Msk (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
18029#define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
18030
18031/* Bit definition for Ethernet MAC Address0 High Register */
18032#define ETH_MACA0HR_MACA0H_Pos (0U)
18033#define ETH_MACA0HR_MACA0H_Msk (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
18034#define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
18035
18036/* Bit definition for Ethernet MAC Address0 Low Register */
18037#define ETH_MACA0LR_MACA0L_Pos (0U)
18038#define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
18039#define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
18040
18041/* Bit definition for Ethernet MAC Address1 High Register */
18042#define ETH_MACA1HR_AE_Pos (31U)
18043#define ETH_MACA1HR_AE_Msk (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
18044#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
18045#define ETH_MACA1HR_SA_Pos (30U)
18046#define ETH_MACA1HR_SA_Msk (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
18047#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
18048#define ETH_MACA1HR_MBC_Pos (24U)
18049#define ETH_MACA1HR_MBC_Msk (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
18050#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
18051#define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
18052#define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
18053#define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
18054#define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
18055#define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
18056#define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
18057#define ETH_MACA1HR_MACA1H_Pos (0U)
18058#define ETH_MACA1HR_MACA1H_Msk (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
18059#define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
18060
18061/* Bit definition for Ethernet MAC Address1 Low Register */
18062#define ETH_MACA1LR_MACA1L_Pos (0U)
18063#define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
18064#define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
18065
18066/* Bit definition for Ethernet MAC Address2 High Register */
18067#define ETH_MACA2HR_AE_Pos (31U)
18068#define ETH_MACA2HR_AE_Msk (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
18069#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
18070#define ETH_MACA2HR_SA_Pos (30U)
18071#define ETH_MACA2HR_SA_Msk (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
18072#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
18073#define ETH_MACA2HR_MBC_Pos (24U)
18074#define ETH_MACA2HR_MBC_Msk (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
18075#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
18076#define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
18077#define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
18078#define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
18079#define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
18080#define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
18081#define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
18082#define ETH_MACA2HR_MACA2H_Pos (0U)
18083#define ETH_MACA2HR_MACA2H_Msk (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
18084#define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
18085
18086/* Bit definition for Ethernet MAC Address2 Low Register */
18087#define ETH_MACA2LR_MACA2L_Pos (0U)
18088#define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
18089#define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
18090
18091/* Bit definition for Ethernet MAC Address3 High Register */
18092#define ETH_MACA3HR_AE_Pos (31U)
18093#define ETH_MACA3HR_AE_Msk (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
18094#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
18095#define ETH_MACA3HR_SA_Pos (30U)
18096#define ETH_MACA3HR_SA_Msk (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
18097#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
18098#define ETH_MACA3HR_MBC_Pos (24U)
18099#define ETH_MACA3HR_MBC_Msk (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
18100#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
18101#define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
18102#define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
18103#define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
18104#define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
18105#define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
18106#define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
18107#define ETH_MACA3HR_MACA3H_Pos (0U)
18108#define ETH_MACA3HR_MACA3H_Msk (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
18109#define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
18110
18111/* Bit definition for Ethernet MAC Address3 Low Register */
18112#define ETH_MACA3LR_MACA3L_Pos (0U)
18113#define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
18114#define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
18115
18116/******************************************************************************/
18117/* Ethernet MMC Registers bits definition */
18118/******************************************************************************/
18119
18120/* Bit definition for Ethernet MMC Contol Register */
18121#define ETH_MMCCR_MCFHP_Pos (5U)
18122#define ETH_MMCCR_MCFHP_Msk (0x1U << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
18123#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
18124#define ETH_MMCCR_MCP_Pos (4U)
18125#define ETH_MMCCR_MCP_Msk (0x1U << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
18126#define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
18127#define ETH_MMCCR_MCF_Pos (3U)
18128#define ETH_MMCCR_MCF_Msk (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
18129#define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
18130#define ETH_MMCCR_ROR_Pos (2U)
18131#define ETH_MMCCR_ROR_Msk (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
18132#define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
18133#define ETH_MMCCR_CSR_Pos (1U)
18134#define ETH_MMCCR_CSR_Msk (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
18135#define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
18136#define ETH_MMCCR_CR_Pos (0U)
18137#define ETH_MMCCR_CR_Msk (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
18138#define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
18139
18140/* Bit definition for Ethernet MMC Receive Interrupt Register */
18141#define ETH_MMCRIR_RGUFS_Pos (17U)
18142#define ETH_MMCRIR_RGUFS_Msk (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
18143#define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
18144#define ETH_MMCRIR_RFAES_Pos (6U)
18145#define ETH_MMCRIR_RFAES_Msk (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
18146#define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
18147#define ETH_MMCRIR_RFCES_Pos (5U)
18148#define ETH_MMCRIR_RFCES_Msk (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
18149#define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
18150
18151/* Bit definition for Ethernet MMC Transmit Interrupt Register */
18152#define ETH_MMCTIR_TGFS_Pos (21U)
18153#define ETH_MMCTIR_TGFS_Msk (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
18154#define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
18155#define ETH_MMCTIR_TGFMSCS_Pos (15U)
18156#define ETH_MMCTIR_TGFMSCS_Msk (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
18157#define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
18158#define ETH_MMCTIR_TGFSCS_Pos (14U)
18159#define ETH_MMCTIR_TGFSCS_Msk (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
18160#define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
18161
18162/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
18163#define ETH_MMCRIMR_RGUFM_Pos (17U)
18164#define ETH_MMCRIMR_RGUFM_Msk (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
18165#define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
18166#define ETH_MMCRIMR_RFAEM_Pos (6U)
18167#define ETH_MMCRIMR_RFAEM_Msk (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
18168#define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
18169#define ETH_MMCRIMR_RFCEM_Pos (5U)
18170#define ETH_MMCRIMR_RFCEM_Msk (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
18171#define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
18172
18173/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
18174#define ETH_MMCTIMR_TGFM_Pos (21U)
18175#define ETH_MMCTIMR_TGFM_Msk (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
18176#define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
18177#define ETH_MMCTIMR_TGFMSCM_Pos (15U)
18178#define ETH_MMCTIMR_TGFMSCM_Msk (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
18179#define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
18180#define ETH_MMCTIMR_TGFSCM_Pos (14U)
18181#define ETH_MMCTIMR_TGFSCM_Msk (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
18182#define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
18183
18184/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
18185#define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
18186#define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
18187#define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
18188
18189/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
18190#define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
18191#define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
18192#define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
18193
18194/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
18195#define ETH_MMCTGFCR_TGFC_Pos (0U)
18196#define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
18197#define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
18198
18199/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
18200#define ETH_MMCRFCECR_RFCEC_Pos (0U)
18201#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
18202#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
18203
18204/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
18205#define ETH_MMCRFAECR_RFAEC_Pos (0U)
18206#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
18207#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
18208
18209/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
18210#define ETH_MMCRGUFCR_RGUFC_Pos (0U)
18211#define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
18212#define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
18213
18214/******************************************************************************/
18215/* Ethernet PTP Registers bits definition */
18216/******************************************************************************/
18217
18218/* Bit definition for Ethernet PTP Time Stamp Contol Register */
18219#define ETH_PTPTSCR_TSCNT_Pos (16U)
18220#define ETH_PTPTSCR_TSCNT_Msk (0x3U << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
18221#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
18222#define ETH_PTPTSSR_TSSMRME_Pos (15U)
18223#define ETH_PTPTSSR_TSSMRME_Msk (0x1U << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
18224#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
18225#define ETH_PTPTSSR_TSSEME_Pos (14U)
18226#define ETH_PTPTSSR_TSSEME_Msk (0x1U << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
18227#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
18228#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
18229#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
18230#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
18231#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
18232#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
18233#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
18234#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
18235#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
18236#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
18237#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
18238#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
18239#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
18240#define ETH_PTPTSSR_TSSSR_Pos (9U)
18241#define ETH_PTPTSSR_TSSSR_Msk (0x1U << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
18242#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
18243#define ETH_PTPTSSR_TSSARFE_Pos (8U)
18244#define ETH_PTPTSSR_TSSARFE_Msk (0x1U << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
18245#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
18246
18247#define ETH_PTPTSCR_TSARU_Pos (5U)
18248#define ETH_PTPTSCR_TSARU_Msk (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
18249#define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
18250#define ETH_PTPTSCR_TSITE_Pos (4U)
18251#define ETH_PTPTSCR_TSITE_Msk (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
18252#define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
18253#define ETH_PTPTSCR_TSSTU_Pos (3U)
18254#define ETH_PTPTSCR_TSSTU_Msk (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
18255#define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
18256#define ETH_PTPTSCR_TSSTI_Pos (2U)
18257#define ETH_PTPTSCR_TSSTI_Msk (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
18258#define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
18259#define ETH_PTPTSCR_TSFCU_Pos (1U)
18260#define ETH_PTPTSCR_TSFCU_Msk (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
18261#define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
18262#define ETH_PTPTSCR_TSE_Pos (0U)
18263#define ETH_PTPTSCR_TSE_Msk (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
18264#define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
18265
18266/* Bit definition for Ethernet PTP Sub-Second Increment Register */
18267#define ETH_PTPSSIR_STSSI_Pos (0U)
18268#define ETH_PTPSSIR_STSSI_Msk (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
18269#define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
18270
18271/* Bit definition for Ethernet PTP Time Stamp High Register */
18272#define ETH_PTPTSHR_STS_Pos (0U)
18273#define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
18274#define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
18275
18276/* Bit definition for Ethernet PTP Time Stamp Low Register */
18277#define ETH_PTPTSLR_STPNS_Pos (31U)
18278#define ETH_PTPTSLR_STPNS_Msk (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
18279#define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
18280#define ETH_PTPTSLR_STSS_Pos (0U)
18281#define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
18282#define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
18283
18284/* Bit definition for Ethernet PTP Time Stamp High Update Register */
18285#define ETH_PTPTSHUR_TSUS_Pos (0U)
18286#define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
18287#define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
18288
18289/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
18290#define ETH_PTPTSLUR_TSUPNS_Pos (31U)
18291#define ETH_PTPTSLUR_TSUPNS_Msk (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
18292#define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
18293#define ETH_PTPTSLUR_TSUSS_Pos (0U)
18294#define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
18295#define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
18296
18297/* Bit definition for Ethernet PTP Time Stamp Addend Register */
18298#define ETH_PTPTSAR_TSA_Pos (0U)
18299#define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
18300#define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
18301
18302/* Bit definition for Ethernet PTP Target Time High Register */
18303#define ETH_PTPTTHR_TTSH_Pos (0U)
18304#define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
18305#define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
18306
18307/* Bit definition for Ethernet PTP Target Time Low Register */
18308#define ETH_PTPTTLR_TTSL_Pos (0U)
18309#define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
18310#define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
18311
18312/* Bit definition for Ethernet PTP Time Stamp Status Register */
18313#define ETH_PTPTSSR_TSTTR_Pos (5U)
18314#define ETH_PTPTSSR_TSTTR_Msk (0x1U << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
18315#define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
18316#define ETH_PTPTSSR_TSSO_Pos (4U)
18317#define ETH_PTPTSSR_TSSO_Msk (0x1U << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
18318#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
18319
18320/******************************************************************************/
18321/* Ethernet DMA Registers bits definition */
18322/******************************************************************************/
18323
18324/* Bit definition for Ethernet DMA Bus Mode Register */
18325#define ETH_DMABMR_AAB_Pos (25U)
18326#define ETH_DMABMR_AAB_Msk (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
18327#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
18328#define ETH_DMABMR_FPM_Pos (24U)
18329#define ETH_DMABMR_FPM_Msk (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
18330#define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
18331#define ETH_DMABMR_USP_Pos (23U)
18332#define ETH_DMABMR_USP_Msk (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
18333#define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
18334#define ETH_DMABMR_RDP_Pos (17U)
18335#define ETH_DMABMR_RDP_Msk (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
18336#define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
18337#define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
18338#define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
18339#define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
18340#define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
18341#define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
18342#define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
18343#define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
18344#define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
18345#define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
18346#define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
18347#define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
18348#define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
18349#define ETH_DMABMR_FB_Pos (16U)
18350#define ETH_DMABMR_FB_Msk (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
18351#define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
18352#define ETH_DMABMR_RTPR_Pos (14U)
18353#define ETH_DMABMR_RTPR_Msk (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
18354#define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
18355#define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
18356#define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
18357#define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
18358#define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
18359#define ETH_DMABMR_PBL_Pos (8U)
18360#define ETH_DMABMR_PBL_Msk (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
18361#define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
18362#define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
18363#define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
18364#define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
18365#define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
18366#define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
18367#define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
18368#define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
18369#define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
18370#define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
18371#define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
18372#define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
18373#define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
18374#define ETH_DMABMR_EDE_Pos (7U)
18375#define ETH_DMABMR_EDE_Msk (0x1U << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
18376#define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
18377#define ETH_DMABMR_DSL_Pos (2U)
18378#define ETH_DMABMR_DSL_Msk (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
18379#define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
18380#define ETH_DMABMR_DA_Pos (1U)
18381#define ETH_DMABMR_DA_Msk (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
18382#define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
18383#define ETH_DMABMR_SR_Pos (0U)
18384#define ETH_DMABMR_SR_Msk (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
18385#define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
18386
18387/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
18388#define ETH_DMATPDR_TPD_Pos (0U)
18389#define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
18390#define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
18391
18392/* Bit definition for Ethernet DMA Receive Poll Demand Register */
18393#define ETH_DMARPDR_RPD_Pos (0U)
18394#define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
18395#define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
18396
18397/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
18398#define ETH_DMARDLAR_SRL_Pos (0U)
18399#define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
18400#define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
18401
18402/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
18403#define ETH_DMATDLAR_STL_Pos (0U)
18404#define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
18405#define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
18406
18407/* Bit definition for Ethernet DMA Status Register */
18408#define ETH_DMASR_TSTS_Pos (29U)
18409#define ETH_DMASR_TSTS_Msk (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
18410#define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
18411#define ETH_DMASR_PMTS_Pos (28U)
18412#define ETH_DMASR_PMTS_Msk (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
18413#define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
18414#define ETH_DMASR_MMCS_Pos (27U)
18415#define ETH_DMASR_MMCS_Msk (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
18416#define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
18417#define ETH_DMASR_EBS_Pos (23U)
18418#define ETH_DMASR_EBS_Msk (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
18419#define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
18420 /* combination with EBS[2:0] for GetFlagStatus function */
18421#define ETH_DMASR_EBS_DescAccess_Pos (25U)
18422#define ETH_DMASR_EBS_DescAccess_Msk (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
18423#define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
18424#define ETH_DMASR_EBS_ReadTransf_Pos (24U)
18425#define ETH_DMASR_EBS_ReadTransf_Msk (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
18426#define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
18427#define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
18428#define ETH_DMASR_EBS_DataTransfTx_Msk (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
18429#define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
18430#define ETH_DMASR_TPS_Pos (20U)
18431#define ETH_DMASR_TPS_Msk (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
18432#define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
18433#define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
18434#define ETH_DMASR_TPS_Fetching_Pos (20U)
18435#define ETH_DMASR_TPS_Fetching_Msk (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
18436#define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
18437#define ETH_DMASR_TPS_Waiting_Pos (21U)
18438#define ETH_DMASR_TPS_Waiting_Msk (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
18439#define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
18440#define ETH_DMASR_TPS_Reading_Pos (20U)
18441#define ETH_DMASR_TPS_Reading_Msk (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
18442#define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
18443#define ETH_DMASR_TPS_Suspended_Pos (21U)
18444#define ETH_DMASR_TPS_Suspended_Msk (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
18445#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
18446#define ETH_DMASR_TPS_Closing_Pos (20U)
18447#define ETH_DMASR_TPS_Closing_Msk (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
18448#define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
18449#define ETH_DMASR_RPS_Pos (17U)
18450#define ETH_DMASR_RPS_Msk (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
18451#define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
18452#define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
18453#define ETH_DMASR_RPS_Fetching_Pos (17U)
18454#define ETH_DMASR_RPS_Fetching_Msk (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
18455#define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
18456#define ETH_DMASR_RPS_Waiting_Pos (17U)
18457#define ETH_DMASR_RPS_Waiting_Msk (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
18458#define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
18459#define ETH_DMASR_RPS_Suspended_Pos (19U)
18460#define ETH_DMASR_RPS_Suspended_Msk (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
18461#define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
18462#define ETH_DMASR_RPS_Closing_Pos (17U)
18463#define ETH_DMASR_RPS_Closing_Msk (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
18464#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
18465#define ETH_DMASR_RPS_Queuing_Pos (17U)
18466#define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
18467#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
18468#define ETH_DMASR_NIS_Pos (16U)
18469#define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
18470#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
18471#define ETH_DMASR_AIS_Pos (15U)
18472#define ETH_DMASR_AIS_Msk (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
18473#define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
18474#define ETH_DMASR_ERS_Pos (14U)
18475#define ETH_DMASR_ERS_Msk (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
18476#define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
18477#define ETH_DMASR_FBES_Pos (13U)
18478#define ETH_DMASR_FBES_Msk (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
18479#define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
18480#define ETH_DMASR_ETS_Pos (10U)
18481#define ETH_DMASR_ETS_Msk (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
18482#define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
18483#define ETH_DMASR_RWTS_Pos (9U)
18484#define ETH_DMASR_RWTS_Msk (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
18485#define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
18486#define ETH_DMASR_RPSS_Pos (8U)
18487#define ETH_DMASR_RPSS_Msk (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
18488#define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
18489#define ETH_DMASR_RBUS_Pos (7U)
18490#define ETH_DMASR_RBUS_Msk (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
18491#define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
18492#define ETH_DMASR_RS_Pos (6U)
18493#define ETH_DMASR_RS_Msk (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
18494#define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
18495#define ETH_DMASR_TUS_Pos (5U)
18496#define ETH_DMASR_TUS_Msk (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
18497#define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
18498#define ETH_DMASR_ROS_Pos (4U)
18499#define ETH_DMASR_ROS_Msk (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
18500#define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
18501#define ETH_DMASR_TJTS_Pos (3U)
18502#define ETH_DMASR_TJTS_Msk (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
18503#define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
18504#define ETH_DMASR_TBUS_Pos (2U)
18505#define ETH_DMASR_TBUS_Msk (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
18506#define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
18507#define ETH_DMASR_TPSS_Pos (1U)
18508#define ETH_DMASR_TPSS_Msk (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
18509#define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
18510#define ETH_DMASR_TS_Pos (0U)
18511#define ETH_DMASR_TS_Msk (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
18512#define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
18513
18514/* Bit definition for Ethernet DMA Operation Mode Register */
18515#define ETH_DMAOMR_DTCEFD_Pos (26U)
18516#define ETH_DMAOMR_DTCEFD_Msk (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
18517#define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
18518#define ETH_DMAOMR_RSF_Pos (25U)
18519#define ETH_DMAOMR_RSF_Msk (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
18520#define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
18521#define ETH_DMAOMR_DFRF_Pos (24U)
18522#define ETH_DMAOMR_DFRF_Msk (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
18523#define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
18524#define ETH_DMAOMR_TSF_Pos (21U)
18525#define ETH_DMAOMR_TSF_Msk (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
18526#define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
18527#define ETH_DMAOMR_FTF_Pos (20U)
18528#define ETH_DMAOMR_FTF_Msk (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
18529#define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
18530#define ETH_DMAOMR_TTC_Pos (14U)
18531#define ETH_DMAOMR_TTC_Msk (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
18532#define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
18533#define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
18534#define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
18535#define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
18536#define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
18537#define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
18538#define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
18539#define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
18540#define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
18541#define ETH_DMAOMR_ST_Pos (13U)
18542#define ETH_DMAOMR_ST_Msk (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
18543#define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
18544#define ETH_DMAOMR_FEF_Pos (7U)
18545#define ETH_DMAOMR_FEF_Msk (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
18546#define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
18547#define ETH_DMAOMR_FUGF_Pos (6U)
18548#define ETH_DMAOMR_FUGF_Msk (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
18549#define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
18550#define ETH_DMAOMR_RTC_Pos (3U)
18551#define ETH_DMAOMR_RTC_Msk (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
18552#define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
18553#define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
18554#define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
18555#define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
18556#define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
18557#define ETH_DMAOMR_OSF_Pos (2U)
18558#define ETH_DMAOMR_OSF_Msk (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
18559#define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
18560#define ETH_DMAOMR_SR_Pos (1U)
18561#define ETH_DMAOMR_SR_Msk (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
18562#define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
18563
18564/* Bit definition for Ethernet DMA Interrupt Enable Register */
18565#define ETH_DMAIER_NISE_Pos (16U)
18566#define ETH_DMAIER_NISE_Msk (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
18567#define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
18568#define ETH_DMAIER_AISE_Pos (15U)
18569#define ETH_DMAIER_AISE_Msk (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
18570#define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
18571#define ETH_DMAIER_ERIE_Pos (14U)
18572#define ETH_DMAIER_ERIE_Msk (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
18573#define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
18574#define ETH_DMAIER_FBEIE_Pos (13U)
18575#define ETH_DMAIER_FBEIE_Msk (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
18576#define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
18577#define ETH_DMAIER_ETIE_Pos (10U)
18578#define ETH_DMAIER_ETIE_Msk (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
18579#define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
18580#define ETH_DMAIER_RWTIE_Pos (9U)
18581#define ETH_DMAIER_RWTIE_Msk (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
18582#define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
18583#define ETH_DMAIER_RPSIE_Pos (8U)
18584#define ETH_DMAIER_RPSIE_Msk (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
18585#define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
18586#define ETH_DMAIER_RBUIE_Pos (7U)
18587#define ETH_DMAIER_RBUIE_Msk (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
18588#define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
18589#define ETH_DMAIER_RIE_Pos (6U)
18590#define ETH_DMAIER_RIE_Msk (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
18591#define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
18592#define ETH_DMAIER_TUIE_Pos (5U)
18593#define ETH_DMAIER_TUIE_Msk (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
18594#define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
18595#define ETH_DMAIER_ROIE_Pos (4U)
18596#define ETH_DMAIER_ROIE_Msk (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
18597#define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
18598#define ETH_DMAIER_TJTIE_Pos (3U)
18599#define ETH_DMAIER_TJTIE_Msk (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
18600#define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
18601#define ETH_DMAIER_TBUIE_Pos (2U)
18602#define ETH_DMAIER_TBUIE_Msk (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
18603#define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
18604#define ETH_DMAIER_TPSIE_Pos (1U)
18605#define ETH_DMAIER_TPSIE_Msk (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
18606#define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
18607#define ETH_DMAIER_TIE_Pos (0U)
18608#define ETH_DMAIER_TIE_Msk (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
18609#define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
18610
18611/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
18612#define ETH_DMAMFBOCR_OFOC_Pos (28U)
18613#define ETH_DMAMFBOCR_OFOC_Msk (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
18614#define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
18615#define ETH_DMAMFBOCR_MFA_Pos (17U)
18616#define ETH_DMAMFBOCR_MFA_Msk (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
18617#define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
18618#define ETH_DMAMFBOCR_OMFC_Pos (16U)
18619#define ETH_DMAMFBOCR_OMFC_Msk (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
18620#define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
18621#define ETH_DMAMFBOCR_MFC_Pos (0U)
18622#define ETH_DMAMFBOCR_MFC_Msk (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
18623#define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
18624
18625/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
18626#define ETH_DMACHTDR_HTDAP_Pos (0U)
18627#define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
18628#define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
18629
18630/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
18631#define ETH_DMACHRDR_HRDAP_Pos (0U)
18632#define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
18633#define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
18634
18635/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
18636#define ETH_DMACHTBAR_HTBAP_Pos (0U)
18637#define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
18638#define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
18639
18640/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
18641#define ETH_DMACHRBAR_HRBAP_Pos (0U)
18642#define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
18643#define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
18644
18645/******************************************************************************/
18646/* */
18647/* USB_OTG */
18648/* */
18649/******************************************************************************/
18650/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
18651#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
18652#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
18653#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
18654#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
18655#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
18656#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
18657#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
18658#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
18659#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
18660#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
18661#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
18662#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
18663#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
18664#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
18665#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
18666#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
18667#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
18668#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
18669#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
18670#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
18671#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
18672#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
18673#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
18674#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
18675#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
18676#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
18677#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
18678#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
18679#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
18680#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
18681#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
18682#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
18683#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
18684#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
18685#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
18686#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
18687#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
18688#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
18689#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
18690#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
18691#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
18692#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
18693#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
18694#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
18695#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
18696#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
18697#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
18698#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
18699#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
18700#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
18701#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
18702#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
18703#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
18704#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
18705
18706/******************** Bit definition forUSB_OTG_HCFG register ********************/
18707
18708#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
18709#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
18710#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
18711#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
18712#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
18713#define USB_OTG_HCFG_FSLSS_Pos (2U)
18714#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
18715#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
18716
18717/******************** Bit definition for USB_OTG_DCFG register ********************/
18718
18719#define USB_OTG_DCFG_DSPD_Pos (0U)
18720#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
18721#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
18722#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
18723#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
18724#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
18725#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
18726#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
18727
18728#define USB_OTG_DCFG_DAD_Pos (4U)
18729#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
18730#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
18731#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
18732#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
18733#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
18734#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
18735#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
18736#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
18737#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
18738
18739#define USB_OTG_DCFG_PFIVL_Pos (11U)
18740#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
18741#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
18742#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
18743#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
18744
18745#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
18746#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
18747#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
18748#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
18749#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
18750
18751/******************** Bit definition for USB_OTG_PCGCR register ********************/
18752#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
18753#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
18754#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
18755#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
18756#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
18757#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
18758#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
18759#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
18760#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
18761
18762/******************** Bit definition for USB_OTG_GOTGINT register ********************/
18763#define USB_OTG_GOTGINT_SEDET_Pos (2U)
18764#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
18765#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
18766#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
18767#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
18768#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
18769#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
18770#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
18771#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
18772#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
18773#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
18774#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
18775#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
18776#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
18777#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
18778#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
18779#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
18780#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
18781#define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
18782#define USB_OTG_GOTGINT_IDCHNG_Msk (0x1U << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
18783#define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */
18784
18785/******************** Bit definition for USB_OTG_DCTL register ********************/
18786#define USB_OTG_DCTL_RWUSIG_Pos (0U)
18787#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
18788#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
18789#define USB_OTG_DCTL_SDIS_Pos (1U)
18790#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
18791#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
18792#define USB_OTG_DCTL_GINSTS_Pos (2U)
18793#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
18794#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
18795#define USB_OTG_DCTL_GONSTS_Pos (3U)
18796#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
18797#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
18798
18799#define USB_OTG_DCTL_TCTL_Pos (4U)
18800#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
18801#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
18802#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
18803#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
18804#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
18805#define USB_OTG_DCTL_SGINAK_Pos (7U)
18806#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
18807#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
18808#define USB_OTG_DCTL_CGINAK_Pos (8U)
18809#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
18810#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
18811#define USB_OTG_DCTL_SGONAK_Pos (9U)
18812#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
18813#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
18814#define USB_OTG_DCTL_CGONAK_Pos (10U)
18815#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
18816#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
18817#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
18818#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
18819#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
18820
18821/******************** Bit definition for USB_OTG_HFIR register ********************/
18822#define USB_OTG_HFIR_FRIVL_Pos (0U)
18823#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
18824#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
18825
18826/******************** Bit definition for USB_OTG_HFNUM register ********************/
18827#define USB_OTG_HFNUM_FRNUM_Pos (0U)
18828#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
18829#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
18830#define USB_OTG_HFNUM_FTREM_Pos (16U)
18831#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
18832#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
18833
18834/******************** Bit definition for USB_OTG_DSTS register ********************/
18835#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
18836#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
18837#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
18838
18839#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
18840#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
18841#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
18842#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
18843#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
18844#define USB_OTG_DSTS_EERR_Pos (3U)
18845#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
18846#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
18847#define USB_OTG_DSTS_FNSOF_Pos (8U)
18848#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
18849#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
18850
18851/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
18852#define USB_OTG_GAHBCFG_GINT_Pos (0U)
18853#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
18854#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
18855#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
18856#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
18857#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
18858#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
18859#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
18860#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
18861#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
18862#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
18863#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
18864#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
18865#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
18866#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
18867#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
18868#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
18869#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
18870#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
18871#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
18872
18873/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
18874
18875#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
18876#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
18877#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
18878#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
18879#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
18880#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
18881#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
18882#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
18883#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
18884#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
18885#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
18886#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
18887#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
18888#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
18889#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
18890#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
18891#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
18892#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
18893#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
18894#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
18895#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
18896#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
18897#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
18898#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
18899#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
18900#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
18901#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
18902#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
18903#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
18904#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
18905#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
18906#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
18907#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
18908#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
18909#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
18910#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
18911#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
18912#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
18913#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
18914#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
18915#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
18916#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
18917#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
18918#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
18919#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
18920#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
18921#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
18922#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
18923#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
18924#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
18925#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
18926#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
18927#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
18928#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
18929#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
18930#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
18931#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
18932#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
18933#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
18934#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
18935#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
18936
18937/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
18938#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
18939#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
18940#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
18941#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
18942#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
18943#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
18944#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
18945#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
18946#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
18947#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
18948#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
18949#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
18950#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
18951#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
18952#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
18953
18954
18955#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
18956#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
18957#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
18958#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
18959#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
18960#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
18961#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
18962#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
18963#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
18964#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
18965#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
18966#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
18967#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
18968#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
18969
18970/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
18971#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
18972#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
18973#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
18974#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
18975#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
18976#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
18977#define USB_OTG_DIEPMSK_TOM_Pos (3U)
18978#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
18979#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
18980#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
18981#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
18982#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
18983#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
18984#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
18985#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
18986#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
18987#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
18988#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
18989#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
18990#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
18991#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
18992#define USB_OTG_DIEPMSK_BIM_Pos (9U)
18993#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
18994#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
18995
18996/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
18997#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
18998#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
18999#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
19000#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
19001#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
19002#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
19003#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
19004#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
19005#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
19006#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
19007#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
19008#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
19009#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
19010#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
19011
19012#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
19013#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
19014#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
19015#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
19016#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
19017#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
19018#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
19019#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
19020#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
19021#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
19022#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
19023
19024/******************** Bit definition for USB_OTG_HAINT register ********************/
19025#define USB_OTG_HAINT_HAINT_Pos (0U)
19026#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
19027#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
19028
19029/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
19030#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
19031#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
19032#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
19033#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
19034#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
19035#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
19036#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
19037#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
19038#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
19039#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
19040#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
19041#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
19042#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
19043#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
19044#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
19045#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
19046#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
19047#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
19048#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
19049#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
19050#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
19051#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
19052#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
19053#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
19054
19055/******************** Bit definition for USB_OTG_GINTSTS register ********************/
19056#define USB_OTG_GINTSTS_CMOD_Pos (0U)
19057#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
19058#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
19059#define USB_OTG_GINTSTS_MMIS_Pos (1U)
19060#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
19061#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
19062#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
19063#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
19064#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
19065#define USB_OTG_GINTSTS_SOF_Pos (3U)
19066#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
19067#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
19068#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
19069#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
19070#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
19071#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
19072#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
19073#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
19074#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
19075#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
19076#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
19077#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
19078#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
19079#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
19080#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
19081#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
19082#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
19083#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
19084#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
19085#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
19086#define USB_OTG_GINTSTS_USBRST_Pos (12U)
19087#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
19088#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
19089#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
19090#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
19091#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
19092#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
19093#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
19094#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
19095#define USB_OTG_GINTSTS_EOPF_Pos (15U)
19096#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
19097#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
19098#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
19099#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
19100#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
19101#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
19102#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
19103#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
19104#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
19105#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
19106#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
19107#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
19108#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
19109#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
19110#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
19111#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
19112#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
19113#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
19114#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
19115#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
19116#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
19117#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
19118#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
19119#define USB_OTG_GINTSTS_HCINT_Pos (25U)
19120#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
19121#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
19122#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
19123#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
19124#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
19125#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
19126#define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
19127#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
19128#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
19129#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
19130#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
19131#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
19132#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
19133#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
19134#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
19135#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
19136#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
19137#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
19138#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
19139#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
19140
19141/******************** Bit definition for USB_OTG_GINTMSK register ********************/
19142#define USB_OTG_GINTMSK_MMISM_Pos (1U)
19143#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
19144#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
19145#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
19146#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
19147#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
19148#define USB_OTG_GINTMSK_SOFM_Pos (3U)
19149#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
19150#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
19151#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
19152#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
19153#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
19154#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
19155#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
19156#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
19157#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
19158#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
19159#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
19160#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
19161#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
19162#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
19163#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
19164#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
19165#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
19166#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
19167#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
19168#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
19169#define USB_OTG_GINTMSK_USBRST_Pos (12U)
19170#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
19171#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
19172#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
19173#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
19174#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
19175#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
19176#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
19177#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
19178#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
19179#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
19180#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
19181#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
19182#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
19183#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
19184#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
19185#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
19186#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
19187#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
19188#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
19189#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
19190#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
19191#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
19192#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
19193#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
19194#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
19195#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
19196#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
19197#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
19198#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
19199#define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
19200#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1U << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
19201#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */
19202#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
19203#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
19204#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
19205#define USB_OTG_GINTMSK_HCIM_Pos (25U)
19206#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
19207#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
19208#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
19209#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
19210#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
19211#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
19212#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
19213#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
19214#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
19215#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
19216#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
19217#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
19218#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
19219#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
19220#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
19221#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
19222#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
19223#define USB_OTG_GINTMSK_WUIM_Pos (31U)
19224#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
19225#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
19226
19227/******************** Bit definition for USB_OTG_DAINT register ********************/
19228#define USB_OTG_DAINT_IEPINT_Pos (0U)
19229#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
19230#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
19231#define USB_OTG_DAINT_OEPINT_Pos (16U)
19232#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
19233#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
19234
19235/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
19236#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
19237#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
19238#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
19239
19240/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
19241#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
19242#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
19243#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
19244#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
19245#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
19246#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
19247#define USB_OTG_GRXSTSP_DPID_Pos (15U)
19248#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
19249#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
19250#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
19251#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
19252#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
19253
19254/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
19255#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
19256#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
19257#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
19258#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
19259#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
19260#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
19261
19262/******************** Bit definition for OTG register ********************/
19263
19264#define USB_OTG_CHNUM_Pos (0U)
19265#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
19266#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
19267#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
19268#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
19269#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
19270#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
19271#define USB_OTG_BCNT_Pos (4U)
19272#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
19273#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
19274
19275#define USB_OTG_DPID_Pos (15U)
19276#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
19277#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
19278#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
19279#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
19280
19281#define USB_OTG_PKTSTS_Pos (17U)
19282#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
19283#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
19284#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
19285#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
19286#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
19287#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
19288
19289#define USB_OTG_EPNUM_Pos (0U)
19290#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
19291#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
19292#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
19293#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
19294#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
19295#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
19296
19297#define USB_OTG_FRMNUM_Pos (21U)
19298#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
19299#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
19300#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
19301#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
19302#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
19303#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
19304
19305/******************** Bit definition for OTG register ********************/
19306
19307#define USB_OTG_CHNUM_Pos (0U)
19308#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
19309#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
19310#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
19311#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
19312#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
19313#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
19314#define USB_OTG_BCNT_Pos (4U)
19315#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
19316#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
19317
19318#define USB_OTG_DPID_Pos (15U)
19319#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
19320#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
19321#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
19322#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
19323
19324#define USB_OTG_PKTSTS_Pos (17U)
19325#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
19326#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
19327#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
19328#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
19329#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
19330#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
19331
19332#define USB_OTG_EPNUM_Pos (0U)
19333#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
19334#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
19335#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
19336#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
19337#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
19338#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
19339
19340#define USB_OTG_FRMNUM_Pos (21U)
19341#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
19342#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
19343#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
19344#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
19345#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
19346#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
19347
19348/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
19349#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
19350#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
19351#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
19352
19353/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
19354#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
19355#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
19356#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
19357
19358/******************** Bit definition for OTG register ********************/
19359#define USB_OTG_NPTXFSA_Pos (0U)
19360#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
19361#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
19362#define USB_OTG_NPTXFD_Pos (16U)
19363#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
19364#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
19365#define USB_OTG_TX0FSA_Pos (0U)
19366#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
19367#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
19368#define USB_OTG_TX0FD_Pos (16U)
19369#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
19370#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
19371
19372/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
19373#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
19374#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
19375#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
19376
19377/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
19378#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
19379#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
19380#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
19381
19382#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
19383#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
19384#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
19385#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
19386#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
19387#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
19388#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
19389#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
19390#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
19391#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
19392#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
19393
19394#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
19395#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
19396#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
19397#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
19398#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
19399#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
19400#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
19401#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
19402#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
19403#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
19404
19405/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
19406#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
19407#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
19408#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
19409#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
19410#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
19411#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
19412
19413#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
19414#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
19415#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
19416#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
19417#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
19418#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
19419#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
19420#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
19421#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
19422#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
19423#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
19424#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
19425#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
19426#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
19427#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
19428
19429#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
19430#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
19431#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
19432#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
19433#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
19434#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
19435#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
19436#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
19437#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
19438#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
19439#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
19440#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
19441#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
19442#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
19443#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
19444
19445/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
19446#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
19447#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
19448#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
19449
19450/******************** Bit definition for USB_OTG_DEACHINT register ********************/
19451#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
19452#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
19453#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
19454#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
19455#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
19456#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
19457
19458/******************** Bit definition for USB_OTG_GCCFG register ********************/
19459#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
19460#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
19461#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
19462#define USB_OTG_GCCFG_VBDEN_Pos (21U)
19463#define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
19464#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< USB VBUS Detection Enable */
19465
19466/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
19467#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
19468#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
19469#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
19470#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
19471#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
19472#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
19473
19474/******************** Bit definition for USB_OTG_CID register ********************/
19475#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
19476#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
19477#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
19478
19479/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
19480#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
19481#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
19482#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
19483#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
19484#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
19485#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
19486#define USB_OTG_GLPMCFG_BESL_Pos (2U)
19487#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
19488#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
19489#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
19490#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
19491#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
19492#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
19493#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
19494#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
19495#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
19496#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
19497#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
19498#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
19499#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
19500#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
19501#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
19502#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
19503#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
19504#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
19505#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
19506#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
19507#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
19508#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
19509#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
19510#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
19511#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
19512#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
19513#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
19514#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
19515#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
19516#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
19517#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
19518#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
19519#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
19520#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
19521#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
19522#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
19523#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
19524#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
19525
19526/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
19527#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
19528#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
19529#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
19530#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
19531#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
19532#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
19533#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
19534#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
19535#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
19536#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
19537#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
19538#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
19539#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
19540#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
19541#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
19542#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
19543#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
19544#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
19545#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
19546#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
19547#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
19548#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
19549#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
19550#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
19551#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
19552#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
19553#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
19554
19555/******************** Bit definition for USB_OTG_HPRT register ********************/
19556#define USB_OTG_HPRT_PCSTS_Pos (0U)
19557#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
19558#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
19559#define USB_OTG_HPRT_PCDET_Pos (1U)
19560#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
19561#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
19562#define USB_OTG_HPRT_PENA_Pos (2U)
19563#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
19564#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
19565#define USB_OTG_HPRT_PENCHNG_Pos (3U)
19566#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
19567#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
19568#define USB_OTG_HPRT_POCA_Pos (4U)
19569#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
19570#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
19571#define USB_OTG_HPRT_POCCHNG_Pos (5U)
19572#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
19573#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
19574#define USB_OTG_HPRT_PRES_Pos (6U)
19575#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
19576#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
19577#define USB_OTG_HPRT_PSUSP_Pos (7U)
19578#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
19579#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
19580#define USB_OTG_HPRT_PRST_Pos (8U)
19581#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
19582#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
19583
19584#define USB_OTG_HPRT_PLSTS_Pos (10U)
19585#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
19586#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
19587#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
19588#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
19589#define USB_OTG_HPRT_PPWR_Pos (12U)
19590#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
19591#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
19592
19593#define USB_OTG_HPRT_PTCTL_Pos (13U)
19594#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
19595#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
19596#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
19597#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
19598#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
19599#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
19600
19601#define USB_OTG_HPRT_PSPD_Pos (17U)
19602#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
19603#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
19604#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
19605#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
19606
19607/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
19608#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
19609#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
19610#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
19611#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
19612#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
19613#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
19614#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
19615#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
19616#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
19617#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
19618#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
19619#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
19620#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
19621#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
19622#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
19623#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
19624#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
19625#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
19626#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
19627#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
19628#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
19629#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
19630#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
19631#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
19632#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
19633#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
19634#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
19635#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
19636#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
19637#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
19638#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
19639#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
19640#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
19641
19642/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
19643#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
19644#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
19645#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
19646#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
19647#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
19648#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
19649
19650/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
19651#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
19652#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
19653#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
19654#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
19655#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
19656#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
19657#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
19658#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
19659#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
19660#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
19661#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
19662#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
19663
19664#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
19665#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
19666#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
19667#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
19668#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
19669#define USB_OTG_DIEPCTL_STALL_Pos (21U)
19670#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
19671#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
19672
19673#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
19674#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
19675#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
19676#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
19677#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
19678#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
19679#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
19680#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
19681#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
19682#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
19683#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
19684#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
19685#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
19686#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
19687#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
19688#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
19689#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
19690#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
19691#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
19692#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
19693#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
19694#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
19695#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
19696#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
19697#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
19698
19699/******************** Bit definition for USB_OTG_HCCHAR register ********************/
19700#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
19701#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
19702#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
19703
19704#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
19705#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
19706#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
19707#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
19708#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
19709#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
19710#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
19711#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
19712#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
19713#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
19714#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
19715#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
19716#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
19717
19718#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
19719#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
19720#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
19721#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
19722#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
19723
19724#define USB_OTG_HCCHAR_MC_Pos (20U)
19725#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
19726#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
19727#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
19728#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
19729
19730#define USB_OTG_HCCHAR_DAD_Pos (22U)
19731#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
19732#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
19733#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
19734#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
19735#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
19736#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
19737#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
19738#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
19739#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
19740#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
19741#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
19742#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
19743#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
19744#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
19745#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
19746#define USB_OTG_HCCHAR_CHENA_Pos (31U)
19747#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
19748#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
19749
19750/******************** Bit definition for USB_OTG_HCSPLT register ********************/
19751
19752#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
19753#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
19754#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
19755#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
19756#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
19757#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
19758#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
19759#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
19760#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
19761#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
19762
19763#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
19764#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
19765#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
19766#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
19767#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
19768#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
19769#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
19770#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
19771#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
19772#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
19773
19774#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
19775#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
19776#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
19777#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
19778#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
19779#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
19780#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
19781#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
19782#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
19783#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
19784#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
19785
19786/******************** Bit definition for USB_OTG_HCINT register ********************/
19787#define USB_OTG_HCINT_XFRC_Pos (0U)
19788#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
19789#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
19790#define USB_OTG_HCINT_CHH_Pos (1U)
19791#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
19792#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
19793#define USB_OTG_HCINT_AHBERR_Pos (2U)
19794#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
19795#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
19796#define USB_OTG_HCINT_STALL_Pos (3U)
19797#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
19798#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
19799#define USB_OTG_HCINT_NAK_Pos (4U)
19800#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
19801#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
19802#define USB_OTG_HCINT_ACK_Pos (5U)
19803#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
19804#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
19805#define USB_OTG_HCINT_NYET_Pos (6U)
19806#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
19807#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
19808#define USB_OTG_HCINT_TXERR_Pos (7U)
19809#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
19810#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
19811#define USB_OTG_HCINT_BBERR_Pos (8U)
19812#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
19813#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
19814#define USB_OTG_HCINT_FRMOR_Pos (9U)
19815#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
19816#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
19817#define USB_OTG_HCINT_DTERR_Pos (10U)
19818#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
19819#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
19820
19821/******************** Bit definition for USB_OTG_DIEPINT register ********************/
19822#define USB_OTG_DIEPINT_XFRC_Pos (0U)
19823#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
19824#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
19825#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
19826#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
19827#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
19828#define USB_OTG_DIEPINT_TOC_Pos (3U)
19829#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
19830#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
19831#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
19832#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
19833#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
19834#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
19835#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
19836#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
19837#define USB_OTG_DIEPINT_TXFE_Pos (7U)
19838#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
19839#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
19840#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
19841#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
19842#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
19843#define USB_OTG_DIEPINT_BNA_Pos (9U)
19844#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
19845#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
19846#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
19847#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
19848#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
19849#define USB_OTG_DIEPINT_BERR_Pos (12U)
19850#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
19851#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
19852#define USB_OTG_DIEPINT_NAK_Pos (13U)
19853#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
19854#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
19855
19856/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
19857#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
19858#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
19859#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
19860#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
19861#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
19862#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
19863#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
19864#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
19865#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
19866#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
19867#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
19868#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
19869#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
19870#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
19871#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
19872#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
19873#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
19874#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
19875#define USB_OTG_HCINTMSK_NYET_Pos (6U)
19876#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
19877#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
19878#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
19879#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
19880#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
19881#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
19882#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
19883#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
19884#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
19885#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
19886#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
19887#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
19888#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
19889#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
19890
19891/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
19892
19893#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
19894#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
19895#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
19896#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
19897#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
19898#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
19899#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
19900#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
19901#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
19902/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
19903#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
19904#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
19905#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
19906#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
19907#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
19908#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
19909#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
19910#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
19911#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
19912#define USB_OTG_HCTSIZ_DPID_Pos (29U)
19913#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
19914#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
19915#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
19916#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
19917
19918/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
19919#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
19920#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
19921#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
19922
19923/******************** Bit definition for USB_OTG_HCDMA register ********************/
19924#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
19925#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
19926#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
19927
19928/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
19929#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
19930#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
19931#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
19932
19933/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
19934#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
19935#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
19936#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
19937#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
19938#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
19939#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
19940
19941/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
19942
19943#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
19944#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
19945#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
19946#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
19947#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
19948#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
19949#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
19950#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
19951#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
19952#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
19953#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
19954#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
19955#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
19956#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
19957#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
19958#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
19959#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
19960#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
19961#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
19962#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
19963#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
19964#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
19965#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
19966#define USB_OTG_DOEPCTL_STALL_Pos (21U)
19967#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
19968#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
19969#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
19970#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
19971#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
19972#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
19973#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
19974#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
19975#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
19976#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
19977#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
19978#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
19979#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
19980#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
19981
19982/******************** Bit definition for USB_OTG_DOEPINT register ********************/
19983#define USB_OTG_DOEPINT_XFRC_Pos (0U)
19984#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
19985#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
19986#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
19987#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
19988#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
19989#define USB_OTG_DOEPINT_STUP_Pos (3U)
19990#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
19991#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
19992#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
19993#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
19994#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
19995#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
19996#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
19997#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */
19998#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
19999#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
20000#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
20001#define USB_OTG_DOEPINT_NYET_Pos (14U)
20002#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
20003#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
20004
20005/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
20006
20007#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
20008#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
20009#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
20010#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
20011#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
20012#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
20013
20014#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
20015#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
20016#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
20017#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
20018#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
20019
20020/******************** Bit definition for PCGCCTL register ********************/
20021#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
20022#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
20023#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
20024#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
20025#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
20026#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
20027#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
20028#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
20029#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
20030
20031/**
20032 * @}
20033 */
20034
20035/**
20036 * @}
20037 */
20038
20039/** @addtogroup Exported_macros
20040 * @{
20041 */
20042
20043/******************************* ADC Instances ********************************/
20044#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
20045 ((INSTANCE) == ADC2) || \
20046 ((INSTANCE) == ADC3))
20047
20048#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
20049
20050#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
20051
20052/******************************* CAN Instances ********************************/
20053#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
20054 ((INSTANCE) == CAN2))
20055/******************************* CRC Instances ********************************/
20056#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
20057
20058/******************************* DAC Instances ********************************/
20059#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
20060
20061/******************************* DCMI Instances *******************************/
20062#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
20063
20064/******************************* DMA2D Instances *******************************/
20065#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
20066
20067/******************************** DMA Instances *******************************/
20068#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
20069 ((INSTANCE) == DMA1_Stream1) || \
20070 ((INSTANCE) == DMA1_Stream2) || \
20071 ((INSTANCE) == DMA1_Stream3) || \
20072 ((INSTANCE) == DMA1_Stream4) || \
20073 ((INSTANCE) == DMA1_Stream5) || \
20074 ((INSTANCE) == DMA1_Stream6) || \
20075 ((INSTANCE) == DMA1_Stream7) || \
20076 ((INSTANCE) == DMA2_Stream0) || \
20077 ((INSTANCE) == DMA2_Stream1) || \
20078 ((INSTANCE) == DMA2_Stream2) || \
20079 ((INSTANCE) == DMA2_Stream3) || \
20080 ((INSTANCE) == DMA2_Stream4) || \
20081 ((INSTANCE) == DMA2_Stream5) || \
20082 ((INSTANCE) == DMA2_Stream6) || \
20083 ((INSTANCE) == DMA2_Stream7))
20084
20085/******************************* GPIO Instances *******************************/
20086#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
20087 ((INSTANCE) == GPIOB) || \
20088 ((INSTANCE) == GPIOC) || \
20089 ((INSTANCE) == GPIOD) || \
20090 ((INSTANCE) == GPIOE) || \
20091 ((INSTANCE) == GPIOF) || \
20092 ((INSTANCE) == GPIOG) || \
20093 ((INSTANCE) == GPIOH) || \
20094 ((INSTANCE) == GPIOI) || \
20095 ((INSTANCE) == GPIOJ) || \
20096 ((INSTANCE) == GPIOK))
20097
20098/******************************** I2C Instances *******************************/
20099#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
20100 ((INSTANCE) == I2C2) || \
20101 ((INSTANCE) == I2C3))
20102
20103/******************************* SMBUS Instances ******************************/
20104#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
20105
20106/******************************** I2S Instances *******************************/
20107
20108#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
20109 ((INSTANCE) == SPI3))
20110
20111/*************************** I2S Extended Instances ***************************/
20112#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
20113 ((INSTANCE) == I2S3ext))
20114/* Legacy Defines */
20115#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
20116
20117/****************************** LTDC Instances ********************************/
20118#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
20119/******************************* RNG Instances ********************************/
20120#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
20121
20122/****************************** RTC Instances *********************************/
20123#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
20124
20125/******************************* SAI Instances ********************************/
20126#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
20127 ((PERIPH) == SAI1_Block_B))
20128/* Legacy define */
20129
20130#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
20131
20132/******************************** SPI Instances *******************************/
20133#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
20134 ((INSTANCE) == SPI2) || \
20135 ((INSTANCE) == SPI3) || \
20136 ((INSTANCE) == SPI4) || \
20137 ((INSTANCE) == SPI5) || \
20138 ((INSTANCE) == SPI6))
20139
20140
20141/****************** TIM Instances : All supported instances *******************/
20142#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20143 ((INSTANCE) == TIM2) || \
20144 ((INSTANCE) == TIM3) || \
20145 ((INSTANCE) == TIM4) || \
20146 ((INSTANCE) == TIM5) || \
20147 ((INSTANCE) == TIM6) || \
20148 ((INSTANCE) == TIM7) || \
20149 ((INSTANCE) == TIM8) || \
20150 ((INSTANCE) == TIM9) || \
20151 ((INSTANCE) == TIM10)|| \
20152 ((INSTANCE) == TIM11)|| \
20153 ((INSTANCE) == TIM12)|| \
20154 ((INSTANCE) == TIM13)|| \
20155 ((INSTANCE) == TIM14))
20156
20157/************* TIM Instances : at least 1 capture/compare channel *************/
20158#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20159 ((INSTANCE) == TIM2) || \
20160 ((INSTANCE) == TIM3) || \
20161 ((INSTANCE) == TIM4) || \
20162 ((INSTANCE) == TIM5) || \
20163 ((INSTANCE) == TIM8) || \
20164 ((INSTANCE) == TIM9) || \
20165 ((INSTANCE) == TIM10) || \
20166 ((INSTANCE) == TIM11) || \
20167 ((INSTANCE) == TIM12) || \
20168 ((INSTANCE) == TIM13) || \
20169 ((INSTANCE) == TIM14))
20170
20171/************ TIM Instances : at least 2 capture/compare channels *************/
20172#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20173 ((INSTANCE) == TIM2) || \
20174 ((INSTANCE) == TIM3) || \
20175 ((INSTANCE) == TIM4) || \
20176 ((INSTANCE) == TIM5) || \
20177 ((INSTANCE) == TIM8) || \
20178 ((INSTANCE) == TIM9) || \
20179 ((INSTANCE) == TIM12))
20180
20181/************ TIM Instances : at least 3 capture/compare channels *************/
20182#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20183 ((INSTANCE) == TIM2) || \
20184 ((INSTANCE) == TIM3) || \
20185 ((INSTANCE) == TIM4) || \
20186 ((INSTANCE) == TIM5) || \
20187 ((INSTANCE) == TIM8))
20188
20189/************ TIM Instances : at least 4 capture/compare channels *************/
20190#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20191 ((INSTANCE) == TIM2) || \
20192 ((INSTANCE) == TIM3) || \
20193 ((INSTANCE) == TIM4) || \
20194 ((INSTANCE) == TIM5) || \
20195 ((INSTANCE) == TIM8))
20196
20197/******************** TIM Instances : Advanced-control timers *****************/
20198#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20199 ((INSTANCE) == TIM8))
20200
20201/******************* TIM Instances : Timer input XOR function *****************/
20202#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20203 ((INSTANCE) == TIM2) || \
20204 ((INSTANCE) == TIM3) || \
20205 ((INSTANCE) == TIM4) || \
20206 ((INSTANCE) == TIM5) || \
20207 ((INSTANCE) == TIM8))
20208
20209/****************** TIM Instances : DMA requests generation (UDE) *************/
20210#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20211 ((INSTANCE) == TIM2) || \
20212 ((INSTANCE) == TIM3) || \
20213 ((INSTANCE) == TIM4) || \
20214 ((INSTANCE) == TIM5) || \
20215 ((INSTANCE) == TIM6) || \
20216 ((INSTANCE) == TIM7) || \
20217 ((INSTANCE) == TIM8))
20218
20219/************ TIM Instances : DMA requests generation (CCxDE) *****************/
20220#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20221 ((INSTANCE) == TIM2) || \
20222 ((INSTANCE) == TIM3) || \
20223 ((INSTANCE) == TIM4) || \
20224 ((INSTANCE) == TIM5) || \
20225 ((INSTANCE) == TIM8))
20226
20227/************ TIM Instances : DMA requests generation (COMDE) *****************/
20228#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20229 ((INSTANCE) == TIM2) || \
20230 ((INSTANCE) == TIM3) || \
20231 ((INSTANCE) == TIM4) || \
20232 ((INSTANCE) == TIM5) || \
20233 ((INSTANCE) == TIM8))
20234
20235/******************** TIM Instances : DMA burst feature ***********************/
20236#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20237 ((INSTANCE) == TIM2) || \
20238 ((INSTANCE) == TIM3) || \
20239 ((INSTANCE) == TIM4) || \
20240 ((INSTANCE) == TIM5) || \
20241 ((INSTANCE) == TIM8))
20242
20243/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
20244#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20245 ((INSTANCE) == TIM2) || \
20246 ((INSTANCE) == TIM3) || \
20247 ((INSTANCE) == TIM4) || \
20248 ((INSTANCE) == TIM5) || \
20249 ((INSTANCE) == TIM6) || \
20250 ((INSTANCE) == TIM7) || \
20251 ((INSTANCE) == TIM8))
20252
20253/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
20254#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20255 ((INSTANCE) == TIM2) || \
20256 ((INSTANCE) == TIM3) || \
20257 ((INSTANCE) == TIM4) || \
20258 ((INSTANCE) == TIM5) || \
20259 ((INSTANCE) == TIM8) || \
20260 ((INSTANCE) == TIM9) || \
20261 ((INSTANCE) == TIM12))
20262
20263/********************** TIM Instances : 32 bit Counter ************************/
20264#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
20265 ((INSTANCE) == TIM5))
20266
20267/***************** TIM Instances : external trigger input availabe ************/
20268#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20269 ((INSTANCE) == TIM2) || \
20270 ((INSTANCE) == TIM3) || \
20271 ((INSTANCE) == TIM4) || \
20272 ((INSTANCE) == TIM5) || \
20273 ((INSTANCE) == TIM8))
20274
20275/****************** TIM Instances : remapping capability **********************/
20276#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
20277 ((INSTANCE) == TIM5) || \
20278 ((INSTANCE) == TIM11))
20279
20280/******************* TIM Instances : output(s) available **********************/
20281#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
20282 ((((INSTANCE) == TIM1) && \
20283 (((CHANNEL) == TIM_CHANNEL_1) || \
20284 ((CHANNEL) == TIM_CHANNEL_2) || \
20285 ((CHANNEL) == TIM_CHANNEL_3) || \
20286 ((CHANNEL) == TIM_CHANNEL_4))) \
20287 || \
20288 (((INSTANCE) == TIM2) && \
20289 (((CHANNEL) == TIM_CHANNEL_1) || \
20290 ((CHANNEL) == TIM_CHANNEL_2) || \
20291 ((CHANNEL) == TIM_CHANNEL_3) || \
20292 ((CHANNEL) == TIM_CHANNEL_4))) \
20293 || \
20294 (((INSTANCE) == TIM3) && \
20295 (((CHANNEL) == TIM_CHANNEL_1) || \
20296 ((CHANNEL) == TIM_CHANNEL_2) || \
20297 ((CHANNEL) == TIM_CHANNEL_3) || \
20298 ((CHANNEL) == TIM_CHANNEL_4))) \
20299 || \
20300 (((INSTANCE) == TIM4) && \
20301 (((CHANNEL) == TIM_CHANNEL_1) || \
20302 ((CHANNEL) == TIM_CHANNEL_2) || \
20303 ((CHANNEL) == TIM_CHANNEL_3) || \
20304 ((CHANNEL) == TIM_CHANNEL_4))) \
20305 || \
20306 (((INSTANCE) == TIM5) && \
20307 (((CHANNEL) == TIM_CHANNEL_1) || \
20308 ((CHANNEL) == TIM_CHANNEL_2) || \
20309 ((CHANNEL) == TIM_CHANNEL_3) || \
20310 ((CHANNEL) == TIM_CHANNEL_4))) \
20311 || \
20312 (((INSTANCE) == TIM8) && \
20313 (((CHANNEL) == TIM_CHANNEL_1) || \
20314 ((CHANNEL) == TIM_CHANNEL_2) || \
20315 ((CHANNEL) == TIM_CHANNEL_3) || \
20316 ((CHANNEL) == TIM_CHANNEL_4))) \
20317 || \
20318 (((INSTANCE) == TIM9) && \
20319 (((CHANNEL) == TIM_CHANNEL_1) || \
20320 ((CHANNEL) == TIM_CHANNEL_2))) \
20321 || \
20322 (((INSTANCE) == TIM10) && \
20323 (((CHANNEL) == TIM_CHANNEL_1))) \
20324 || \
20325 (((INSTANCE) == TIM11) && \
20326 (((CHANNEL) == TIM_CHANNEL_1))) \
20327 || \
20328 (((INSTANCE) == TIM12) && \
20329 (((CHANNEL) == TIM_CHANNEL_1) || \
20330 ((CHANNEL) == TIM_CHANNEL_2))) \
20331 || \
20332 (((INSTANCE) == TIM13) && \
20333 (((CHANNEL) == TIM_CHANNEL_1))) \
20334 || \
20335 (((INSTANCE) == TIM14) && \
20336 (((CHANNEL) == TIM_CHANNEL_1))))
20337
20338/************ TIM Instances : complementary output(s) available ***************/
20339#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
20340 ((((INSTANCE) == TIM1) && \
20341 (((CHANNEL) == TIM_CHANNEL_1) || \
20342 ((CHANNEL) == TIM_CHANNEL_2) || \
20343 ((CHANNEL) == TIM_CHANNEL_3))) \
20344 || \
20345 (((INSTANCE) == TIM8) && \
20346 (((CHANNEL) == TIM_CHANNEL_1) || \
20347 ((CHANNEL) == TIM_CHANNEL_2) || \
20348 ((CHANNEL) == TIM_CHANNEL_3))))
20349
20350/****************** TIM Instances : supporting counting mode selection ********/
20351#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20352 ((INSTANCE) == TIM2) || \
20353 ((INSTANCE) == TIM3) || \
20354 ((INSTANCE) == TIM4) || \
20355 ((INSTANCE) == TIM5) || \
20356 ((INSTANCE) == TIM8))
20357
20358/****************** TIM Instances : supporting clock division *****************/
20359#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20360 ((INSTANCE) == TIM2) || \
20361 ((INSTANCE) == TIM3) || \
20362 ((INSTANCE) == TIM4) || \
20363 ((INSTANCE) == TIM5) || \
20364 ((INSTANCE) == TIM8) || \
20365 ((INSTANCE) == TIM9) || \
20366 ((INSTANCE) == TIM10)|| \
20367 ((INSTANCE) == TIM11)|| \
20368 ((INSTANCE) == TIM12)|| \
20369 ((INSTANCE) == TIM13)|| \
20370 ((INSTANCE) == TIM14))
20371
20372/****************** TIM Instances : supporting commutation event generation ***/
20373#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
20374 ((INSTANCE) == TIM8))
20375
20376
20377/****************** TIM Instances : supporting OCxREF clear *******************/
20378#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20379 ((INSTANCE) == TIM2) || \
20380 ((INSTANCE) == TIM3) || \
20381 ((INSTANCE) == TIM4) || \
20382 ((INSTANCE) == TIM5) || \
20383 ((INSTANCE) == TIM8))
20384
20385/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
20386#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20387 ((INSTANCE) == TIM2) || \
20388 ((INSTANCE) == TIM3) || \
20389 ((INSTANCE) == TIM4) || \
20390 ((INSTANCE) == TIM5) || \
20391 ((INSTANCE) == TIM8) || \
20392 ((INSTANCE) == TIM9) || \
20393 ((INSTANCE) == TIM12))
20394
20395/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
20396#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20397 ((INSTANCE) == TIM2) || \
20398 ((INSTANCE) == TIM3) || \
20399 ((INSTANCE) == TIM4) || \
20400 ((INSTANCE) == TIM5) || \
20401 ((INSTANCE) == TIM8))
20402
20403/****************** TIM Instances : supporting repetition counter *************/
20404#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20405 ((INSTANCE) == TIM8))
20406
20407/****************** TIM Instances : supporting encoder interface **************/
20408#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20409 ((INSTANCE) == TIM2) || \
20410 ((INSTANCE) == TIM3) || \
20411 ((INSTANCE) == TIM4) || \
20412 ((INSTANCE) == TIM5) || \
20413 ((INSTANCE) == TIM8) || \
20414 ((INSTANCE) == TIM9) || \
20415 ((INSTANCE) == TIM12))
20416/****************** TIM Instances : supporting Hall sensor interface **********/
20417#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20418 ((INSTANCE) == TIM2) || \
20419 ((INSTANCE) == TIM3) || \
20420 ((INSTANCE) == TIM4) || \
20421 ((INSTANCE) == TIM5) || \
20422 ((INSTANCE) == TIM8))
20423/****************** TIM Instances : supporting the break function *************/
20424#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20425 ((INSTANCE) == TIM8))
20426
20427/******************** USART Instances : Synchronous mode **********************/
20428#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20429 ((INSTANCE) == USART2) || \
20430 ((INSTANCE) == USART3) || \
20431 ((INSTANCE) == USART6))
20432
20433/******************** UART Instances : Half-Duplex mode **********************/
20434#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20435 ((INSTANCE) == USART2) || \
20436 ((INSTANCE) == USART3) || \
20437 ((INSTANCE) == UART4) || \
20438 ((INSTANCE) == UART5) || \
20439 ((INSTANCE) == USART6) || \
20440 ((INSTANCE) == UART7) || \
20441 ((INSTANCE) == UART8))
20442
20443/* Legacy defines */
20444#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
20445
20446/****************** UART Instances : Hardware Flow control ********************/
20447#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20448 ((INSTANCE) == USART2) || \
20449 ((INSTANCE) == USART3) || \
20450 ((INSTANCE) == USART6))
20451/******************** UART Instances : LIN mode **********************/
20452#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
20453
20454/********************* UART Instances : Smart card mode ***********************/
20455#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20456 ((INSTANCE) == USART2) || \
20457 ((INSTANCE) == USART3) || \
20458 ((INSTANCE) == USART6))
20459
20460/*********************** UART Instances : IRDA mode ***************************/
20461#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20462 ((INSTANCE) == USART2) || \
20463 ((INSTANCE) == USART3) || \
20464 ((INSTANCE) == UART4) || \
20465 ((INSTANCE) == UART5) || \
20466 ((INSTANCE) == USART6) || \
20467 ((INSTANCE) == UART7) || \
20468 ((INSTANCE) == UART8))
20469
20470/*********************** PCD Instances ****************************************/
20471#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
20472 ((INSTANCE) == USB_OTG_HS))
20473
20474/*********************** HCD Instances ****************************************/
20475#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
20476 ((INSTANCE) == USB_OTG_HS))
20477
20478/****************************** SDIO Instances ********************************/
20479#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
20480
20481/****************************** IWDG Instances ********************************/
20482#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
20483
20484/****************************** WWDG Instances ********************************/
20485#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
20486
20487
20488/****************************** QSPI Instances ********************************/
20489#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
20490/****************************** USB Exported Constants ************************/
20491#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
20492#define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
20493#define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
20494#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
20495#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16U
20496#define USB_OTG_HS_MAX_IN_ENDPOINTS 8U /* Including EP0 */
20497#define USB_OTG_HS_MAX_OUT_ENDPOINTS 8U /* Including EP0 */
20498#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
20499
20500/*
20501 * @brief Specific devices reset values definitions
20502 */
20503#define RCC_PLLCFGR_RST_VALUE 0x24003010U
20504#define RCC_PLLI2SCFGR_RST_VALUE 0x24003000U
20505#define RCC_PLLSAICFGR_RST_VALUE 0x24003000U
20506
20507#define RCC_MAX_FREQUENCY 180000000U /*!< Max frequency of family in Hz*/
20508#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
20509#define RCC_MAX_FREQUENCY_SCALE2 168000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
20510#define RCC_MAX_FREQUENCY_SCALE3 120000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
20511#define RCC_PLLVCO_OUTPUT_MIN 192000000U /*!< Frequency min for PLLVCO output, in Hz */
20512#define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
20513#define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
20514#define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
20515
20516#define RCC_PLLN_MIN_VALUE 50U
20517#define RCC_PLLN_MAX_VALUE 432U
20518
20519#define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
20520#define FLASH_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
20521#define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
20522#define FLASH_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
20523#define FLASH_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
20524
20525#define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
20526#define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
20527#define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
20528#define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
20529#define FLASH_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
20530
20531#define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
20532#define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
20533#define FLASH_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
20534
20535/******************************************************************************/
20536/* For a painless codes migration between the STM32F4xx device product */
20537/* lines, the aliases defined below are put in place to overcome the */
20538/* differences in the interrupt handlers and IRQn definitions. */
20539/* No need to update developed interrupt code when moving across */
20540/* product lines within the same STM32F4 Family */
20541/******************************************************************************/
20542/* Aliases for __IRQn */
20543#define FSMC_IRQn FMC_IRQn
20544
20545/* Aliases for __IRQHandler */
20546#define FSMC_IRQHandler FMC_IRQHandler
20547
20548/**
20549 * @}
20550 */
20551
20552/**
20553 * @}
20554 */
20555
20556/**
20557 * @}
20558 */
20559
20560#ifdef __cplusplus
20561}
20562#endif /* __cplusplus */
20563
20564#endif /* __STM32F479xx_H */
20565
20566
20567
20568/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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