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1/**
2 ******************************************************************************
3 * @file stm32f745xx.h
4 * @author MCD Application Team
5 * @version V1.2.0
6 * @date 30-December-2016
7 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
8 *
9 * This file contains:
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral�s registers hardware
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
18 *
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ******************************************************************************
42 */
43
44/** @addtogroup CMSIS_Device
45 * @{
46 */
47
48/** @addtogroup stm32f745xx
49 * @{
50 */
51
52#ifndef __STM32F745xx_H
53#define __STM32F745xx_H
54
55#ifdef __cplusplus
56 extern "C" {
57#endif /* __cplusplus */
58
59/** @addtogroup Configuration_section_for_CMSIS
60 * @{
61 */
62
63/**
64 * @brief STM32F7xx Interrupt Number Definition, according to the selected device
65 * in @ref Library_configuration_section
66 */
67typedef enum
68{
69/****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
70 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
71 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */
72 BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */
73 UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */
74 SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */
75 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */
76 PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */
77 SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */
78/****** STM32 specific Interrupt Numbers **********************************************************************/
79 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
80 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
81 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
82 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
83 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
84 RCC_IRQn = 5, /*!< RCC global Interrupt */
85 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
86 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
87 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
88 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
89 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
90 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
91 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
92 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
93 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
94 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
95 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
96 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
97 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
98 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
99 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
100 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
101 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
102 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
103 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
104 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
105 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
106 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
107 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
108 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
109 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
110 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
111 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
112 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
113 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
114 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
115 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
116 USART1_IRQn = 37, /*!< USART1 global Interrupt */
117 USART2_IRQn = 38, /*!< USART2 global Interrupt */
118 USART3_IRQn = 39, /*!< USART3 global Interrupt */
119 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
120 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
121 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
122 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
123 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
124 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
125 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
126 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
127 FMC_IRQn = 48, /*!< FMC global Interrupt */
128 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
129 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
130 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
131 UART4_IRQn = 52, /*!< UART4 global Interrupt */
132 UART5_IRQn = 53, /*!< UART5 global Interrupt */
133 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
134 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
135 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
136 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
137 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
138 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
139 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
140 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
141 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
142 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
143 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
144 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
145 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
146 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
147 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
148 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
149 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
150 USART6_IRQn = 71, /*!< USART6 global interrupt */
151 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
152 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
153 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
154 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
155 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
156 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
157 DCMI_IRQn = 78, /*!< DCMI global interrupt */
158 RNG_IRQn = 80, /*!< RNG global interrupt */
159 FPU_IRQn = 81, /*!< FPU global interrupt */
160 UART7_IRQn = 82, /*!< UART7 global interrupt */
161 UART8_IRQn = 83, /*!< UART8 global interrupt */
162 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
163 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
164 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
165 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
166 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
167 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
168 QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
169 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
170 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
171 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
172 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
173 SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
174} IRQn_Type;
175
176/**
177 * @}
178 */
179
180/**
181 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
182 */
183#define __CM7_REV 0x0001U /*!< Cortex-M7 revision r0p1 */
184#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
185#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
186#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
187#define __FPU_PRESENT 1 /*!< FPU present */
188#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
189#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
190#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
191
192
193#include "system_stm32f7xx.h"
194#include <stdint.h>
195
196/** @addtogroup Peripheral_registers_structures
197 * @{
198 */
199
200/**
201 * @brief Analog to Digital Converter
202 */
203
204typedef struct
205{
206 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
207 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
208 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
209 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
210 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
211 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
212 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
213 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
214 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
215 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
216 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
217 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
218 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
219 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
220 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
221 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
222 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
223 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
224 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
225 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
226} ADC_TypeDef;
227
228typedef struct
229{
230 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
231 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
232 __IO uint32_t CDR; /*!< ADC common regular data register for dual
233 AND triple modes, Address offset: ADC1 base address + 0x308 */
234} ADC_Common_TypeDef;
235
236
237/**
238 * @brief Controller Area Network TxMailBox
239 */
240
241typedef struct
242{
243 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
244 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
245 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
246 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
247} CAN_TxMailBox_TypeDef;
248
249/**
250 * @brief Controller Area Network FIFOMailBox
251 */
252
253typedef struct
254{
255 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
256 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
257 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
258 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
259} CAN_FIFOMailBox_TypeDef;
260
261/**
262 * @brief Controller Area Network FilterRegister
263 */
264
265typedef struct
266{
267 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
268 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
269} CAN_FilterRegister_TypeDef;
270
271/**
272 * @brief Controller Area Network
273 */
274
275typedef struct
276{
277 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
278 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
279 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
280 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
281 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
282 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
283 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
284 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
285 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
286 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
287 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
288 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
289 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
290 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
291 uint32_t RESERVED2; /*!< Reserved, 0x208 */
292 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
293 uint32_t RESERVED3; /*!< Reserved, 0x210 */
294 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
295 uint32_t RESERVED4; /*!< Reserved, 0x218 */
296 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
297 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
298 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
299} CAN_TypeDef;
300
301/**
302 * @brief HDMI-CEC
303 */
304
305typedef struct
306{
307 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
308 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
309 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
310 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
311 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
312 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
313}CEC_TypeDef;
314
315/**
316 * @brief CRC calculation unit
317 */
318
319typedef struct
320{
321 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
322 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
323 uint8_t RESERVED0; /*!< Reserved, 0x05 */
324 uint16_t RESERVED1; /*!< Reserved, 0x06 */
325 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
326 uint32_t RESERVED2; /*!< Reserved, 0x0C */
327 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
328 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
329} CRC_TypeDef;
330
331/**
332 * @brief Digital to Analog Converter
333 */
334
335typedef struct
336{
337 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
338 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
339 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
340 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
341 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
342 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
343 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
344 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
345 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
346 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
347 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
348 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
349 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
350 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
351} DAC_TypeDef;
352
353
354/**
355 * @brief Debug MCU
356 */
357
358typedef struct
359{
360 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
361 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
362 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
363 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
364}DBGMCU_TypeDef;
365
366/**
367 * @brief DCMI
368 */
369
370typedef struct
371{
372 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
373 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
374 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
375 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
376 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
377 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
378 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
379 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
380 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
381 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
382 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
383} DCMI_TypeDef;
384
385/**
386 * @brief DMA Controller
387 */
388
389typedef struct
390{
391 __IO uint32_t CR; /*!< DMA stream x configuration register */
392 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
393 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
394 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
395 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
396 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
397} DMA_Stream_TypeDef;
398
399typedef struct
400{
401 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
402 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
403 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
404 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
405} DMA_TypeDef;
406
407/**
408 * @brief DMA2D Controller
409 */
410
411typedef struct
412{
413 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
414 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
415 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
416 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
417 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
418 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
419 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
420 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
421 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
422 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
423 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
424 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
425 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
426 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
427 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
428 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
429 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
430 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
431 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
432 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
433 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
434 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
435 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
436} DMA2D_TypeDef;
437
438
439/**
440 * @brief Ethernet MAC
441 */
442
443typedef struct
444{
445 __IO uint32_t MACCR;
446 __IO uint32_t MACFFR;
447 __IO uint32_t MACHTHR;
448 __IO uint32_t MACHTLR;
449 __IO uint32_t MACMIIAR;
450 __IO uint32_t MACMIIDR;
451 __IO uint32_t MACFCR;
452 __IO uint32_t MACVLANTR; /* 8 */
453 uint32_t RESERVED0[2];
454 __IO uint32_t MACRWUFFR; /* 11 */
455 __IO uint32_t MACPMTCSR;
456 uint32_t RESERVED1;
457 __IO uint32_t MACDBGR;
458 __IO uint32_t MACSR; /* 15 */
459 __IO uint32_t MACIMR;
460 __IO uint32_t MACA0HR;
461 __IO uint32_t MACA0LR;
462 __IO uint32_t MACA1HR;
463 __IO uint32_t MACA1LR;
464 __IO uint32_t MACA2HR;
465 __IO uint32_t MACA2LR;
466 __IO uint32_t MACA3HR;
467 __IO uint32_t MACA3LR; /* 24 */
468 uint32_t RESERVED2[40];
469 __IO uint32_t MMCCR; /* 65 */
470 __IO uint32_t MMCRIR;
471 __IO uint32_t MMCTIR;
472 __IO uint32_t MMCRIMR;
473 __IO uint32_t MMCTIMR; /* 69 */
474 uint32_t RESERVED3[14];
475 __IO uint32_t MMCTGFSCCR; /* 84 */
476 __IO uint32_t MMCTGFMSCCR;
477 uint32_t RESERVED4[5];
478 __IO uint32_t MMCTGFCR;
479 uint32_t RESERVED5[10];
480 __IO uint32_t MMCRFCECR;
481 __IO uint32_t MMCRFAECR;
482 uint32_t RESERVED6[10];
483 __IO uint32_t MMCRGUFCR;
484 uint32_t RESERVED7[334];
485 __IO uint32_t PTPTSCR;
486 __IO uint32_t PTPSSIR;
487 __IO uint32_t PTPTSHR;
488 __IO uint32_t PTPTSLR;
489 __IO uint32_t PTPTSHUR;
490 __IO uint32_t PTPTSLUR;
491 __IO uint32_t PTPTSAR;
492 __IO uint32_t PTPTTHR;
493 __IO uint32_t PTPTTLR;
494 __IO uint32_t RESERVED8;
495 __IO uint32_t PTPTSSR;
496 uint32_t RESERVED9[565];
497 __IO uint32_t DMABMR;
498 __IO uint32_t DMATPDR;
499 __IO uint32_t DMARPDR;
500 __IO uint32_t DMARDLAR;
501 __IO uint32_t DMATDLAR;
502 __IO uint32_t DMASR;
503 __IO uint32_t DMAOMR;
504 __IO uint32_t DMAIER;
505 __IO uint32_t DMAMFBOCR;
506 __IO uint32_t DMARSWTR;
507 uint32_t RESERVED10[8];
508 __IO uint32_t DMACHTDR;
509 __IO uint32_t DMACHRDR;
510 __IO uint32_t DMACHTBAR;
511 __IO uint32_t DMACHRBAR;
512} ETH_TypeDef;
513
514/**
515 * @brief External Interrupt/Event Controller
516 */
517
518typedef struct
519{
520 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
521 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
522 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
523 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
524 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
525 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
526} EXTI_TypeDef;
527
528/**
529 * @brief FLASH Registers
530 */
531
532typedef struct
533{
534 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
535 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
536 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
537 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
538 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
539 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
540 __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */
541} FLASH_TypeDef;
542
543
544
545/**
546 * @brief Flexible Memory Controller
547 */
548
549typedef struct
550{
551 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
552} FMC_Bank1_TypeDef;
553
554/**
555 * @brief Flexible Memory Controller Bank1E
556 */
557
558typedef struct
559{
560 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
561} FMC_Bank1E_TypeDef;
562
563/**
564 * @brief Flexible Memory Controller Bank3
565 */
566
567typedef struct
568{
569 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
570 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
571 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
572 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
573 uint32_t RESERVED0; /*!< Reserved, 0x90 */
574 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
575} FMC_Bank3_TypeDef;
576
577/**
578 * @brief Flexible Memory Controller Bank5_6
579 */
580
581typedef struct
582{
583 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
584 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
585 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
586 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
587 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
588} FMC_Bank5_6_TypeDef;
589
590
591/**
592 * @brief General Purpose I/O
593 */
594
595typedef struct
596{
597 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
598 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
599 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
600 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
601 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
602 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
603 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
604 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
605 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
606} GPIO_TypeDef;
607
608/**
609 * @brief System configuration controller
610 */
611
612typedef struct
613{
614 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
615 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
616 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
617 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
618 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
619} SYSCFG_TypeDef;
620
621/**
622 * @brief Inter-integrated Circuit Interface
623 */
624
625typedef struct
626{
627 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
628 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
629 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
630 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
631 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
632 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
633 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
634 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
635 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
636 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
637 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
638} I2C_TypeDef;
639
640/**
641 * @brief Independent WATCHDOG
642 */
643
644typedef struct
645{
646 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
647 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
648 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
649 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
650 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
651} IWDG_TypeDef;
652
653
654
655/**
656 * @brief Power Control
657 */
658
659typedef struct
660{
661 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
662 __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */
663 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
664 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */
665} PWR_TypeDef;
666
667
668/**
669 * @brief Reset and Clock Control
670 */
671
672typedef struct
673{
674 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
675 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
676 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
677 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
678 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
679 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
680 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
681 uint32_t RESERVED0; /*!< Reserved, 0x1C */
682 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
683 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
684 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
685 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
686 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
687 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
688 uint32_t RESERVED2; /*!< Reserved, 0x3C */
689 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
690 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
691 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
692 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
693 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
694 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
695 uint32_t RESERVED4; /*!< Reserved, 0x5C */
696 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
697 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
698 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
699 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
700 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
701 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
702 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
703 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
704 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
705 __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */
706 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */
707
708} RCC_TypeDef;
709
710/**
711 * @brief Real-Time Clock
712 */
713
714typedef struct
715{
716 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
717 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
718 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
719 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
720 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
721 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
722 uint32_t reserved; /*!< Reserved */
723 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
724 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
725 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
726 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
727 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
728 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
729 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
730 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
731 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
732 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
733 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
734 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
735 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
736 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
737 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
738 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
739 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
740 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
741 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
742 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
743 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
744 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
745 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
746 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
747 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
748 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
749 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
750 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
751 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
752 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
753 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
754 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
755 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
756 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
757 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
758 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
759 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
760 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
761 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
762 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
763 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
764 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
765 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
766 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
767 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
768} RTC_TypeDef;
769
770
771/**
772 * @brief Serial Audio Interface
773 */
774
775typedef struct
776{
777 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
778} SAI_TypeDef;
779
780typedef struct
781{
782 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
783 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
784 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
785 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
786 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
787 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
788 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
789 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
790} SAI_Block_TypeDef;
791
792/**
793 * @brief SPDIF-RX Interface
794 */
795
796typedef struct
797{
798 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
799 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
800 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
801 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
802 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
803 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
804 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
805} SPDIFRX_TypeDef;
806
807/**
808 * @brief SD host Interface
809 */
810
811typedef struct
812{
813 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
814 __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */
815 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
816 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
817 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
818 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
819 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
820 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
821 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
822 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
823 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
824 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
825 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
826 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
827 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
828 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
829 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
830 __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
831 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
832 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
833} SDMMC_TypeDef;
834
835/**
836 * @brief Serial Peripheral Interface
837 */
838
839typedef struct
840{
841 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
842 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
843 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
844 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
845 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
846 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
847 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
848 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
849 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
850} SPI_TypeDef;
851
852/**
853 * @brief QUAD Serial Peripheral Interface
854 */
855
856typedef struct
857{
858 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
859 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
860 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
861 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
862 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
863 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
864 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
865 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
866 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
867 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
868 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
869 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
870 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
871} QUADSPI_TypeDef;
872
873/**
874 * @brief TIM
875 */
876
877typedef struct
878{
879 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
880 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
881 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
882 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
883 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
884 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
885 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
886 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
887 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
888 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
889 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
890 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
891 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
892 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
893 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
894 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
895 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
896 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
897 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
898 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
899 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
900 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
901 __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */
902 __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */
903
904} TIM_TypeDef;
905
906/**
907 * @brief LPTIMIMER
908 */
909typedef struct
910{
911 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
912 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
913 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
914 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
915 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
916 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
917 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
918 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
919} LPTIM_TypeDef;
920
921
922/**
923 * @brief Universal Synchronous Asynchronous Receiver Transmitter
924 */
925
926typedef struct
927{
928 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
929 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
930 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
931 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
932 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
933 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
934 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
935 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
936 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
937 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
938 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
939} USART_TypeDef;
940
941
942/**
943 * @brief Window WATCHDOG
944 */
945
946typedef struct
947{
948 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
949 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
950 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
951} WWDG_TypeDef;
952
953
954/**
955 * @brief RNG
956 */
957
958typedef struct
959{
960 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
961 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
962 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
963} RNG_TypeDef;
964
965/**
966 * @}
967 */
968
969/**
970 * @brief USB_OTG_Core_Registers
971 */
972typedef struct
973{
974 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
975 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
976 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
977 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
978 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
979 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
980 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
981 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
982 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
983 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
984 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
985 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
986 uint32_t Reserved30[2]; /*!< Reserved 030h */
987 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
988 __IO uint32_t CID; /*!< User ID Register 03Ch */
989 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
990 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
991 uint32_t Reserved6; /*!< Reserved 050h */
992 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
993 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
994 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
995 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
996 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
997 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
998 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
999} USB_OTG_GlobalTypeDef;
1000
1001
1002/**
1003 * @brief USB_OTG_device_Registers
1004 */
1005typedef struct
1006{
1007 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
1008 __IO uint32_t DCTL; /*!< dev Control Register 804h */
1009 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
1010 uint32_t Reserved0C; /*!< Reserved 80Ch */
1011 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
1012 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
1013 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
1014 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
1015 uint32_t Reserved20; /*!< Reserved 820h */
1016 uint32_t Reserved9; /*!< Reserved 824h */
1017 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
1018 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
1019 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
1020 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
1021 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
1022 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
1023 uint32_t Reserved40; /*!< dedicated EP mask 840h */
1024 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
1025 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
1026 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
1027} USB_OTG_DeviceTypeDef;
1028
1029
1030/**
1031 * @brief USB_OTG_IN_Endpoint-Specific_Register
1032 */
1033typedef struct
1034{
1035 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
1036 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
1037 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
1038 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
1039 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
1040 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
1041 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
1042 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
1043} USB_OTG_INEndpointTypeDef;
1044
1045
1046/**
1047 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1048 */
1049typedef struct
1050{
1051 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
1052 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
1053 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
1054 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
1055 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
1056 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
1057 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
1058} USB_OTG_OUTEndpointTypeDef;
1059
1060
1061/**
1062 * @brief USB_OTG_Host_Mode_Register_Structures
1063 */
1064typedef struct
1065{
1066 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
1067 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
1068 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
1069 uint32_t Reserved40C; /*!< Reserved 40Ch */
1070 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
1071 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
1072 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
1073} USB_OTG_HostTypeDef;
1074
1075/**
1076 * @brief USB_OTG_Host_Channel_Specific_Registers
1077 */
1078typedef struct
1079{
1080 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
1081 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
1082 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
1083 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
1084 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
1085 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
1086 uint32_t Reserved[2]; /*!< Reserved */
1087} USB_OTG_HostChannelTypeDef;
1088/**
1089 * @}
1090 */
1091
1092
1093
1094
1095/** @addtogroup Peripheral_memory_map
1096 * @{
1097 */
1098#define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */
1099#define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over ITCM */
1100#define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */
1101#define RAMDTCM_BASE 0x20000000U /*!< Base address of : 64KB system data RAM accessible over DTCM */
1102#define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */
1103#define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */
1104#define QSPI_BASE 0x90000000U /*!< Base address of : QSPI memories accessible over AXI */
1105#define FMC_R_BASE 0xA0000000U /*!< Base address of : FMC Control registers */
1106#define QSPI_R_BASE 0xA0001000U /*!< Base address of : QSPI Control registers */
1107#define SRAM1_BASE 0x20010000U /*!< Base address of : 240KB RAM1 accessible over AXI/AHB */
1108#define SRAM2_BASE 0x2004C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
1109#define FLASH_END 0x080FFFFFU /*!< FLASH end address */
1110#define FLASH_OTP_BASE 0x1FF0F000U /*!< Base address of : (up to 1024 Bytes) embedded FLASH OTP Area */
1111#define FLASH_OTP_END 0x1FF0F41FU /*!< End address of : (up to 1024 Bytes) embedded FLASH OTP Area */
1112
1113/* Legacy define */
1114#define FLASH_BASE FLASHAXI_BASE
1115
1116/*!< Peripheral memory map */
1117#define APB1PERIPH_BASE PERIPH_BASE
1118#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1119#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1120#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
1121
1122/*!< APB1 peripherals */
1123#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1124#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1125#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1126#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1127#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1128#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1129#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
1130#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
1131#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
1132#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
1133#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1134#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1135#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1136#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1137#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1138#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)
1139#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1140#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1141#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1142#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1143#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1144#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1145#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1146#define I2C4_BASE (APB1PERIPH_BASE + 0x6000U)
1147#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1148#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
1149#define CEC_BASE (APB1PERIPH_BASE + 0x6C00U)
1150#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1151#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1152#define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
1153#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
1154
1155/*!< APB2 peripherals */
1156#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
1157#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
1158#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
1159#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
1160#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
1161#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
1162#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
1163#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
1164#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U)
1165#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1166#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
1167#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
1168#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
1169#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
1170#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
1171#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
1172#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
1173#define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
1174#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
1175#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
1176#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
1177#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
1178#define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
1179#define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
1180/*!< AHB1 peripherals */
1181#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
1182#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1183#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1184#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1185#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1186#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1187#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1188#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1189#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
1190#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
1191#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
1192#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1193#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1194#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1195#define UID_BASE 0x1FF0F420U /*!< Unique device ID register base address */
1196#define FLASHSIZE_BASE 0x1FF0F442U /*!< FLASH Size register base address */
1197#define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
1198/* Legacy define */
1199#define PACKAGESIZE_BASE PACKAGE_BASE
1200
1201#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1202#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1203#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1204#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1205#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1206#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1207#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1208#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1209#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1210#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1211#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1212#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1213#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1214#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1215#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1216#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1217#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1218#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1219#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
1220#define ETH_MAC_BASE (ETH_BASE)
1221#define ETH_MMC_BASE (ETH_BASE + 0x0100U)
1222#define ETH_PTP_BASE (ETH_BASE + 0x0700U)
1223#define ETH_DMA_BASE (ETH_BASE + 0x1000U)
1224#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
1225/*!< AHB2 peripherals */
1226#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
1227#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1228/*!< FMC Bankx registers base address */
1229#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1230#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1231#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
1232#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
1233
1234/* Debug MCU registers base address */
1235#define DBGMCU_BASE 0xE0042000U
1236
1237/*!< USB registers base address */
1238#define USB_OTG_HS_PERIPH_BASE 0x40040000U
1239#define USB_OTG_FS_PERIPH_BASE 0x50000000U
1240
1241#define USB_OTG_GLOBAL_BASE 0x000U
1242#define USB_OTG_DEVICE_BASE 0x800U
1243#define USB_OTG_IN_ENDPOINT_BASE 0x900U
1244#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1245#define USB_OTG_EP_REG_SIZE 0x20U
1246#define USB_OTG_HOST_BASE 0x400U
1247#define USB_OTG_HOST_PORT_BASE 0x440U
1248#define USB_OTG_HOST_CHANNEL_BASE 0x500U
1249#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1250#define USB_OTG_PCGCCTL_BASE 0xE00U
1251#define USB_OTG_FIFO_BASE 0x1000U
1252#define USB_OTG_FIFO_SIZE 0x1000U
1253
1254/**
1255 * @}
1256 */
1257
1258/** @addtogroup Peripheral_declaration
1259 * @{
1260 */
1261#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1262#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1263#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1264#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1265#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1266#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1267#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1268#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1269#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1270#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1271#define RTC ((RTC_TypeDef *) RTC_BASE)
1272#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1273#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1274#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1275#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1276#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
1277#define USART2 ((USART_TypeDef *) USART2_BASE)
1278#define USART3 ((USART_TypeDef *) USART3_BASE)
1279#define UART4 ((USART_TypeDef *) UART4_BASE)
1280#define UART5 ((USART_TypeDef *) UART5_BASE)
1281#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1282#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1283#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1284#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
1285#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1286#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1287#define CEC ((CEC_TypeDef *) CEC_BASE)
1288#define PWR ((PWR_TypeDef *) PWR_BASE)
1289#define DAC1 ((DAC_TypeDef *) DAC_BASE)
1290#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1291#define UART7 ((USART_TypeDef *) UART7_BASE)
1292#define UART8 ((USART_TypeDef *) UART8_BASE)
1293#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1294#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1295#define USART1 ((USART_TypeDef *) USART1_BASE)
1296#define USART6 ((USART_TypeDef *) USART6_BASE)
1297#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1298#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1299#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1300#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1301#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
1302#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1303#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1304#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1305#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1306#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1307#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1308#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1309#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1310#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1311#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1312#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1313#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1314#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1315#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1316#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1317#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1318#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1319#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1320#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1321#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1322#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1323#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1324#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1325#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1326#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1327#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1328#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1329#define CRC ((CRC_TypeDef *) CRC_BASE)
1330#define RCC ((RCC_TypeDef *) RCC_BASE)
1331#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1332#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1333#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1334#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1335#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1336#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1337#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1338#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1339#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1340#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1341#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1342#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1343#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1344#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1345#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1346#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1347#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1348#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1349#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1350#define ETH ((ETH_TypeDef *) ETH_BASE)
1351#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1352#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1353#define RNG ((RNG_TypeDef *) RNG_BASE)
1354#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1355#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1356#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1357#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1358#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1359#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1360#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1361#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1362
1363/**
1364 * @}
1365 */
1366
1367/** @addtogroup Exported_constants
1368 * @{
1369 */
1370
1371 /** @addtogroup Peripheral_Registers_Bits_Definition
1372 * @{
1373 */
1374
1375/******************************************************************************/
1376/* Peripheral Registers_Bits_Definition */
1377/******************************************************************************/
1378
1379/******************************************************************************/
1380/* */
1381/* Analog to Digital Converter */
1382/* */
1383/******************************************************************************/
1384/******************** Bit definition for ADC_SR register ********************/
1385#define ADC_SR_AWD_Pos (0U)
1386#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
1387#define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
1388#define ADC_SR_EOC_Pos (1U)
1389#define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
1390#define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
1391#define ADC_SR_JEOC_Pos (2U)
1392#define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
1393#define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
1394#define ADC_SR_JSTRT_Pos (3U)
1395#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
1396#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
1397#define ADC_SR_STRT_Pos (4U)
1398#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
1399#define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
1400#define ADC_SR_OVR_Pos (5U)
1401#define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
1402#define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
1403
1404/******************* Bit definition for ADC_CR1 register ********************/
1405#define ADC_CR1_AWDCH_Pos (0U)
1406#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
1407#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1408#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
1409#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
1410#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
1411#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
1412#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
1413#define ADC_CR1_EOCIE_Pos (5U)
1414#define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
1415#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
1416#define ADC_CR1_AWDIE_Pos (6U)
1417#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
1418#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
1419#define ADC_CR1_JEOCIE_Pos (7U)
1420#define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
1421#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
1422#define ADC_CR1_SCAN_Pos (8U)
1423#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
1424#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
1425#define ADC_CR1_AWDSGL_Pos (9U)
1426#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
1427#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
1428#define ADC_CR1_JAUTO_Pos (10U)
1429#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
1430#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
1431#define ADC_CR1_DISCEN_Pos (11U)
1432#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
1433#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
1434#define ADC_CR1_JDISCEN_Pos (12U)
1435#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
1436#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
1437#define ADC_CR1_DISCNUM_Pos (13U)
1438#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
1439#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1440#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
1441#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
1442#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
1443#define ADC_CR1_JAWDEN_Pos (22U)
1444#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
1445#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
1446#define ADC_CR1_AWDEN_Pos (23U)
1447#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
1448#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
1449#define ADC_CR1_RES_Pos (24U)
1450#define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
1451#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
1452#define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
1453#define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
1454#define ADC_CR1_OVRIE_Pos (26U)
1455#define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
1456#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
1457
1458/******************* Bit definition for ADC_CR2 register ********************/
1459#define ADC_CR2_ADON_Pos (0U)
1460#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
1461#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
1462#define ADC_CR2_CONT_Pos (1U)
1463#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
1464#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
1465#define ADC_CR2_DMA_Pos (8U)
1466#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
1467#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
1468#define ADC_CR2_DDS_Pos (9U)
1469#define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
1470#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
1471#define ADC_CR2_EOCS_Pos (10U)
1472#define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
1473#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
1474#define ADC_CR2_ALIGN_Pos (11U)
1475#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
1476#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
1477#define ADC_CR2_JEXTSEL_Pos (16U)
1478#define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
1479#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1480#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
1481#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
1482#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
1483#define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
1484#define ADC_CR2_JEXTEN_Pos (20U)
1485#define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
1486#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1487#define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
1488#define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
1489#define ADC_CR2_JSWSTART_Pos (22U)
1490#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
1491#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
1492#define ADC_CR2_EXTSEL_Pos (24U)
1493#define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
1494#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1495#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
1496#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
1497#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
1498#define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
1499#define ADC_CR2_EXTEN_Pos (28U)
1500#define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
1501#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1502#define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
1503#define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
1504#define ADC_CR2_SWSTART_Pos (30U)
1505#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
1506#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
1507
1508/****************** Bit definition for ADC_SMPR1 register *******************/
1509#define ADC_SMPR1_SMP10_Pos (0U)
1510#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
1511#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1512#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
1513#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
1514#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
1515#define ADC_SMPR1_SMP11_Pos (3U)
1516#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
1517#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1518#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
1519#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
1520#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
1521#define ADC_SMPR1_SMP12_Pos (6U)
1522#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
1523#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1524#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
1525#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
1526#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
1527#define ADC_SMPR1_SMP13_Pos (9U)
1528#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
1529#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1530#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
1531#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
1532#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
1533#define ADC_SMPR1_SMP14_Pos (12U)
1534#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
1535#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1536#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
1537#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
1538#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
1539#define ADC_SMPR1_SMP15_Pos (15U)
1540#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
1541#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1542#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
1543#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
1544#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
1545#define ADC_SMPR1_SMP16_Pos (18U)
1546#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
1547#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1548#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
1549#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
1550#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
1551#define ADC_SMPR1_SMP17_Pos (21U)
1552#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
1553#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1554#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
1555#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
1556#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
1557#define ADC_SMPR1_SMP18_Pos (24U)
1558#define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
1559#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1560#define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
1561#define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
1562#define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
1563
1564/****************** Bit definition for ADC_SMPR2 register *******************/
1565#define ADC_SMPR2_SMP0_Pos (0U)
1566#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
1567#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1568#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
1569#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
1570#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
1571#define ADC_SMPR2_SMP1_Pos (3U)
1572#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
1573#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1574#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
1575#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
1576#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
1577#define ADC_SMPR2_SMP2_Pos (6U)
1578#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
1579#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1580#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
1581#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
1582#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
1583#define ADC_SMPR2_SMP3_Pos (9U)
1584#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
1585#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1586#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
1587#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
1588#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
1589#define ADC_SMPR2_SMP4_Pos (12U)
1590#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
1591#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1592#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
1593#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
1594#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
1595#define ADC_SMPR2_SMP5_Pos (15U)
1596#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
1597#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1598#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
1599#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
1600#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
1601#define ADC_SMPR2_SMP6_Pos (18U)
1602#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
1603#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1604#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
1605#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
1606#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
1607#define ADC_SMPR2_SMP7_Pos (21U)
1608#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
1609#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1610#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
1611#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
1612#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
1613#define ADC_SMPR2_SMP8_Pos (24U)
1614#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
1615#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1616#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
1617#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
1618#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
1619#define ADC_SMPR2_SMP9_Pos (27U)
1620#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
1621#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1622#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
1623#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
1624#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
1625
1626/****************** Bit definition for ADC_JOFR1 register *******************/
1627#define ADC_JOFR1_JOFFSET1_Pos (0U)
1628#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
1629#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
1630
1631/****************** Bit definition for ADC_JOFR2 register *******************/
1632#define ADC_JOFR2_JOFFSET2_Pos (0U)
1633#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
1634#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
1635
1636/****************** Bit definition for ADC_JOFR3 register *******************/
1637#define ADC_JOFR3_JOFFSET3_Pos (0U)
1638#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
1639#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
1640
1641/****************** Bit definition for ADC_JOFR4 register *******************/
1642#define ADC_JOFR4_JOFFSET4_Pos (0U)
1643#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
1644#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
1645
1646/******************* Bit definition for ADC_HTR register ********************/
1647#define ADC_HTR_HT_Pos (0U)
1648#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
1649#define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
1650
1651/******************* Bit definition for ADC_LTR register ********************/
1652#define ADC_LTR_LT_Pos (0U)
1653#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
1654#define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
1655
1656/******************* Bit definition for ADC_SQR1 register *******************/
1657#define ADC_SQR1_SQ13_Pos (0U)
1658#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
1659#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1660#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
1661#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
1662#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
1663#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
1664#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
1665#define ADC_SQR1_SQ14_Pos (5U)
1666#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
1667#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1668#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
1669#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
1670#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
1671#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
1672#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
1673#define ADC_SQR1_SQ15_Pos (10U)
1674#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
1675#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1676#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
1677#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
1678#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
1679#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
1680#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
1681#define ADC_SQR1_SQ16_Pos (15U)
1682#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
1683#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1684#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
1685#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
1686#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
1687#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
1688#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
1689#define ADC_SQR1_L_Pos (20U)
1690#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
1691#define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
1692#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
1693#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
1694#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
1695#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
1696
1697/******************* Bit definition for ADC_SQR2 register *******************/
1698#define ADC_SQR2_SQ7_Pos (0U)
1699#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
1700#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1701#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
1702#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
1703#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
1704#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
1705#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
1706#define ADC_SQR2_SQ8_Pos (5U)
1707#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
1708#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1709#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
1710#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
1711#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
1712#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
1713#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
1714#define ADC_SQR2_SQ9_Pos (10U)
1715#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
1716#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1717#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
1718#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
1719#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
1720#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
1721#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
1722#define ADC_SQR2_SQ10_Pos (15U)
1723#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
1724#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1725#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
1726#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
1727#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
1728#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
1729#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
1730#define ADC_SQR2_SQ11_Pos (20U)
1731#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
1732#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1733#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
1734#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
1735#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
1736#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
1737#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
1738#define ADC_SQR2_SQ12_Pos (25U)
1739#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
1740#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1741#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
1742#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
1743#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
1744#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
1745#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
1746
1747/******************* Bit definition for ADC_SQR3 register *******************/
1748#define ADC_SQR3_SQ1_Pos (0U)
1749#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
1750#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1751#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
1752#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
1753#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
1754#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
1755#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
1756#define ADC_SQR3_SQ2_Pos (5U)
1757#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
1758#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1759#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
1760#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
1761#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
1762#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
1763#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
1764#define ADC_SQR3_SQ3_Pos (10U)
1765#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
1766#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1767#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
1768#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
1769#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
1770#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
1771#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
1772#define ADC_SQR3_SQ4_Pos (15U)
1773#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
1774#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1775#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
1776#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
1777#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
1778#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
1779#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
1780#define ADC_SQR3_SQ5_Pos (20U)
1781#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
1782#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1783#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
1784#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
1785#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
1786#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
1787#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
1788#define ADC_SQR3_SQ6_Pos (25U)
1789#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
1790#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1791#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
1792#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
1793#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
1794#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
1795#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
1796
1797/******************* Bit definition for ADC_JSQR register *******************/
1798#define ADC_JSQR_JSQ1_Pos (0U)
1799#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
1800#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1801#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
1802#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
1803#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
1804#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
1805#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
1806#define ADC_JSQR_JSQ2_Pos (5U)
1807#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
1808#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1809#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
1810#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
1811#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
1812#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
1813#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
1814#define ADC_JSQR_JSQ3_Pos (10U)
1815#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
1816#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1817#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
1818#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
1819#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
1820#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
1821#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
1822#define ADC_JSQR_JSQ4_Pos (15U)
1823#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
1824#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1825#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
1826#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
1827#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
1828#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
1829#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
1830#define ADC_JSQR_JL_Pos (20U)
1831#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
1832#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
1833#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
1834#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
1835
1836/******************* Bit definition for ADC_JDR1 register *******************/
1837#define ADC_JDR1_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
1838
1839/******************* Bit definition for ADC_JDR2 register *******************/
1840#define ADC_JDR2_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
1841
1842/******************* Bit definition for ADC_JDR3 register *******************/
1843#define ADC_JDR3_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
1844
1845/******************* Bit definition for ADC_JDR4 register *******************/
1846#define ADC_JDR4_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
1847
1848/******************** Bit definition for ADC_DR register ********************/
1849#define ADC_DR_DATA_Pos (0U)
1850#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
1851#define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
1852#define ADC_DR_ADC2DATA_Pos (16U)
1853#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
1854#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
1855
1856/******************* Bit definition for ADC_CSR register ********************/
1857#define ADC_CSR_AWD1_Pos (0U)
1858#define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
1859#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
1860#define ADC_CSR_EOC1_Pos (1U)
1861#define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
1862#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
1863#define ADC_CSR_JEOC1_Pos (2U)
1864#define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
1865#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
1866#define ADC_CSR_JSTRT1_Pos (3U)
1867#define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
1868#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
1869#define ADC_CSR_STRT1_Pos (4U)
1870#define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
1871#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
1872#define ADC_CSR_OVR1_Pos (5U)
1873#define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
1874#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 Overrun flag */
1875#define ADC_CSR_AWD2_Pos (8U)
1876#define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
1877#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
1878#define ADC_CSR_EOC2_Pos (9U)
1879#define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
1880#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
1881#define ADC_CSR_JEOC2_Pos (10U)
1882#define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
1883#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
1884#define ADC_CSR_JSTRT2_Pos (11U)
1885#define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
1886#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
1887#define ADC_CSR_STRT2_Pos (12U)
1888#define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
1889#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
1890#define ADC_CSR_OVR2_Pos (13U)
1891#define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
1892#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 Overrun flag */
1893#define ADC_CSR_AWD3_Pos (16U)
1894#define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
1895#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
1896#define ADC_CSR_EOC3_Pos (17U)
1897#define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
1898#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
1899#define ADC_CSR_JEOC3_Pos (18U)
1900#define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
1901#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
1902#define ADC_CSR_JSTRT3_Pos (19U)
1903#define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
1904#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
1905#define ADC_CSR_STRT3_Pos (20U)
1906#define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
1907#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
1908#define ADC_CSR_OVR3_Pos (21U)
1909#define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
1910#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 Overrun flag */
1911
1912/* Legacy defines */
1913#define ADC_CSR_DOVR1 ADC_CSR_OVR1
1914#define ADC_CSR_DOVR2 ADC_CSR_OVR2
1915#define ADC_CSR_DOVR3 ADC_CSR_OVR3
1916
1917
1918/******************* Bit definition for ADC_CCR register ********************/
1919#define ADC_CCR_MULTI_Pos (0U)
1920#define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
1921#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1922#define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
1923#define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
1924#define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
1925#define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
1926#define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
1927#define ADC_CCR_DELAY_Pos (8U)
1928#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
1929#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1930#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
1931#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
1932#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
1933#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
1934#define ADC_CCR_DDS_Pos (13U)
1935#define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
1936#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
1937#define ADC_CCR_DMA_Pos (14U)
1938#define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
1939#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1940#define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
1941#define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
1942#define ADC_CCR_ADCPRE_Pos (16U)
1943#define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
1944#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
1945#define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
1946#define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
1947#define ADC_CCR_VBATE_Pos (22U)
1948#define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
1949#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
1950#define ADC_CCR_TSVREFE_Pos (23U)
1951#define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
1952#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
1953
1954/******************* Bit definition for ADC_CDR register ********************/
1955#define ADC_CDR_DATA1_Pos (0U)
1956#define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
1957#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
1958#define ADC_CDR_DATA2_Pos (16U)
1959#define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
1960#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
1961
1962/* Legacy defines */
1963#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
1964#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
1965
1966/******************************************************************************/
1967/* */
1968/* Controller Area Network */
1969/* */
1970/******************************************************************************/
1971/*!<CAN control and status registers */
1972/******************* Bit definition for CAN_MCR register ********************/
1973#define CAN_MCR_INRQ_Pos (0U)
1974#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
1975#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
1976#define CAN_MCR_SLEEP_Pos (1U)
1977#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
1978#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
1979#define CAN_MCR_TXFP_Pos (2U)
1980#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
1981#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
1982#define CAN_MCR_RFLM_Pos (3U)
1983#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
1984#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
1985#define CAN_MCR_NART_Pos (4U)
1986#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
1987#define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
1988#define CAN_MCR_AWUM_Pos (5U)
1989#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
1990#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
1991#define CAN_MCR_ABOM_Pos (6U)
1992#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
1993#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
1994#define CAN_MCR_TTCM_Pos (7U)
1995#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
1996#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
1997#define CAN_MCR_RESET_Pos (15U)
1998#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
1999#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
2000
2001/******************* Bit definition for CAN_MSR register ********************/
2002#define CAN_MSR_INAK_Pos (0U)
2003#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
2004#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
2005#define CAN_MSR_SLAK_Pos (1U)
2006#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
2007#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
2008#define CAN_MSR_ERRI_Pos (2U)
2009#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
2010#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
2011#define CAN_MSR_WKUI_Pos (3U)
2012#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
2013#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
2014#define CAN_MSR_SLAKI_Pos (4U)
2015#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
2016#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
2017#define CAN_MSR_TXM_Pos (8U)
2018#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
2019#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
2020#define CAN_MSR_RXM_Pos (9U)
2021#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
2022#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
2023#define CAN_MSR_SAMP_Pos (10U)
2024#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
2025#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
2026#define CAN_MSR_RX_Pos (11U)
2027#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
2028#define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
2029
2030/******************* Bit definition for CAN_TSR register ********************/
2031#define CAN_TSR_RQCP0_Pos (0U)
2032#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
2033#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
2034#define CAN_TSR_TXOK0_Pos (1U)
2035#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
2036#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
2037#define CAN_TSR_ALST0_Pos (2U)
2038#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
2039#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
2040#define CAN_TSR_TERR0_Pos (3U)
2041#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
2042#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
2043#define CAN_TSR_ABRQ0_Pos (7U)
2044#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
2045#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
2046#define CAN_TSR_RQCP1_Pos (8U)
2047#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
2048#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
2049#define CAN_TSR_TXOK1_Pos (9U)
2050#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
2051#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
2052#define CAN_TSR_ALST1_Pos (10U)
2053#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
2054#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
2055#define CAN_TSR_TERR1_Pos (11U)
2056#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
2057#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
2058#define CAN_TSR_ABRQ1_Pos (15U)
2059#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
2060#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
2061#define CAN_TSR_RQCP2_Pos (16U)
2062#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
2063#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
2064#define CAN_TSR_TXOK2_Pos (17U)
2065#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
2066#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
2067#define CAN_TSR_ALST2_Pos (18U)
2068#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
2069#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
2070#define CAN_TSR_TERR2_Pos (19U)
2071#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
2072#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
2073#define CAN_TSR_ABRQ2_Pos (23U)
2074#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
2075#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
2076#define CAN_TSR_CODE_Pos (24U)
2077#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
2078#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
2079
2080#define CAN_TSR_TME_Pos (26U)
2081#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
2082#define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
2083#define CAN_TSR_TME0_Pos (26U)
2084#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
2085#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
2086#define CAN_TSR_TME1_Pos (27U)
2087#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
2088#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
2089#define CAN_TSR_TME2_Pos (28U)
2090#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
2091#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
2092
2093#define CAN_TSR_LOW_Pos (29U)
2094#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
2095#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
2096#define CAN_TSR_LOW0_Pos (29U)
2097#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
2098#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
2099#define CAN_TSR_LOW1_Pos (30U)
2100#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
2101#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
2102#define CAN_TSR_LOW2_Pos (31U)
2103#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
2104#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
2105
2106/******************* Bit definition for CAN_RF0R register *******************/
2107#define CAN_RF0R_FMP0_Pos (0U)
2108#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
2109#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
2110#define CAN_RF0R_FULL0_Pos (3U)
2111#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
2112#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
2113#define CAN_RF0R_FOVR0_Pos (4U)
2114#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
2115#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
2116#define CAN_RF0R_RFOM0_Pos (5U)
2117#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
2118#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
2119
2120/******************* Bit definition for CAN_RF1R register *******************/
2121#define CAN_RF1R_FMP1_Pos (0U)
2122#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
2123#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
2124#define CAN_RF1R_FULL1_Pos (3U)
2125#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
2126#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
2127#define CAN_RF1R_FOVR1_Pos (4U)
2128#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
2129#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
2130#define CAN_RF1R_RFOM1_Pos (5U)
2131#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
2132#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
2133
2134/******************** Bit definition for CAN_IER register *******************/
2135#define CAN_IER_TMEIE_Pos (0U)
2136#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
2137#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
2138#define CAN_IER_FMPIE0_Pos (1U)
2139#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
2140#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
2141#define CAN_IER_FFIE0_Pos (2U)
2142#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
2143#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
2144#define CAN_IER_FOVIE0_Pos (3U)
2145#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
2146#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
2147#define CAN_IER_FMPIE1_Pos (4U)
2148#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
2149#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
2150#define CAN_IER_FFIE1_Pos (5U)
2151#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
2152#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
2153#define CAN_IER_FOVIE1_Pos (6U)
2154#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
2155#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
2156#define CAN_IER_EWGIE_Pos (8U)
2157#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
2158#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
2159#define CAN_IER_EPVIE_Pos (9U)
2160#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
2161#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
2162#define CAN_IER_BOFIE_Pos (10U)
2163#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
2164#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
2165#define CAN_IER_LECIE_Pos (11U)
2166#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
2167#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
2168#define CAN_IER_ERRIE_Pos (15U)
2169#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
2170#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
2171#define CAN_IER_WKUIE_Pos (16U)
2172#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
2173#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
2174#define CAN_IER_SLKIE_Pos (17U)
2175#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
2176#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
2177
2178/******************** Bit definition for CAN_ESR register *******************/
2179#define CAN_ESR_EWGF_Pos (0U)
2180#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
2181#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
2182#define CAN_ESR_EPVF_Pos (1U)
2183#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
2184#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
2185#define CAN_ESR_BOFF_Pos (2U)
2186#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
2187#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
2188
2189#define CAN_ESR_LEC_Pos (4U)
2190#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
2191#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
2192#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
2193#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
2194#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
2195
2196#define CAN_ESR_TEC_Pos (16U)
2197#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
2198#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
2199#define CAN_ESR_REC_Pos (24U)
2200#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
2201#define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
2202
2203/******************* Bit definition for CAN_BTR register ********************/
2204#define CAN_BTR_BRP_Pos (0U)
2205#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
2206#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
2207#define CAN_BTR_TS1_Pos (16U)
2208#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
2209#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
2210#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
2211#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
2212#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
2213#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
2214#define CAN_BTR_TS2_Pos (20U)
2215#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
2216#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
2217#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
2218#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
2219#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
2220#define CAN_BTR_SJW_Pos (24U)
2221#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
2222#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
2223#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
2224#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
2225#define CAN_BTR_LBKM_Pos (30U)
2226#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
2227#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
2228#define CAN_BTR_SILM_Pos (31U)
2229#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
2230#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
2231
2232/*!<Mailbox registers */
2233/****************** Bit definition for CAN_TI0R register ********************/
2234#define CAN_TI0R_TXRQ_Pos (0U)
2235#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
2236#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
2237#define CAN_TI0R_RTR_Pos (1U)
2238#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
2239#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
2240#define CAN_TI0R_IDE_Pos (2U)
2241#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
2242#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
2243#define CAN_TI0R_EXID_Pos (3U)
2244#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
2245#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
2246#define CAN_TI0R_STID_Pos (21U)
2247#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
2248#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2249
2250/****************** Bit definition for CAN_TDT0R register *******************/
2251#define CAN_TDT0R_DLC_Pos (0U)
2252#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
2253#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
2254#define CAN_TDT0R_TGT_Pos (8U)
2255#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
2256#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
2257#define CAN_TDT0R_TIME_Pos (16U)
2258#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2259#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
2260
2261/****************** Bit definition for CAN_TDL0R register *******************/
2262#define CAN_TDL0R_DATA0_Pos (0U)
2263#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
2264#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
2265#define CAN_TDL0R_DATA1_Pos (8U)
2266#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2267#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
2268#define CAN_TDL0R_DATA2_Pos (16U)
2269#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2270#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
2271#define CAN_TDL0R_DATA3_Pos (24U)
2272#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
2273#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
2274
2275/****************** Bit definition for CAN_TDH0R register *******************/
2276#define CAN_TDH0R_DATA4_Pos (0U)
2277#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
2278#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
2279#define CAN_TDH0R_DATA5_Pos (8U)
2280#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2281#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
2282#define CAN_TDH0R_DATA6_Pos (16U)
2283#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2284#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
2285#define CAN_TDH0R_DATA7_Pos (24U)
2286#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
2287#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
2288
2289/******************* Bit definition for CAN_TI1R register *******************/
2290#define CAN_TI1R_TXRQ_Pos (0U)
2291#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
2292#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
2293#define CAN_TI1R_RTR_Pos (1U)
2294#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
2295#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
2296#define CAN_TI1R_IDE_Pos (2U)
2297#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
2298#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
2299#define CAN_TI1R_EXID_Pos (3U)
2300#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
2301#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
2302#define CAN_TI1R_STID_Pos (21U)
2303#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
2304#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2305
2306/******************* Bit definition for CAN_TDT1R register ******************/
2307#define CAN_TDT1R_DLC_Pos (0U)
2308#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
2309#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
2310#define CAN_TDT1R_TGT_Pos (8U)
2311#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
2312#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
2313#define CAN_TDT1R_TIME_Pos (16U)
2314#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2315#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
2316
2317/******************* Bit definition for CAN_TDL1R register ******************/
2318#define CAN_TDL1R_DATA0_Pos (0U)
2319#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
2320#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
2321#define CAN_TDL1R_DATA1_Pos (8U)
2322#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2323#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
2324#define CAN_TDL1R_DATA2_Pos (16U)
2325#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2326#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
2327#define CAN_TDL1R_DATA3_Pos (24U)
2328#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
2329#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
2330
2331/******************* Bit definition for CAN_TDH1R register ******************/
2332#define CAN_TDH1R_DATA4_Pos (0U)
2333#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
2334#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
2335#define CAN_TDH1R_DATA5_Pos (8U)
2336#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2337#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
2338#define CAN_TDH1R_DATA6_Pos (16U)
2339#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2340#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
2341#define CAN_TDH1R_DATA7_Pos (24U)
2342#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
2343#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
2344
2345/******************* Bit definition for CAN_TI2R register *******************/
2346#define CAN_TI2R_TXRQ_Pos (0U)
2347#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
2348#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
2349#define CAN_TI2R_RTR_Pos (1U)
2350#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
2351#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
2352#define CAN_TI2R_IDE_Pos (2U)
2353#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
2354#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
2355#define CAN_TI2R_EXID_Pos (3U)
2356#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
2357#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
2358#define CAN_TI2R_STID_Pos (21U)
2359#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
2360#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2361
2362/******************* Bit definition for CAN_TDT2R register ******************/
2363#define CAN_TDT2R_DLC_Pos (0U)
2364#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
2365#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
2366#define CAN_TDT2R_TGT_Pos (8U)
2367#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
2368#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
2369#define CAN_TDT2R_TIME_Pos (16U)
2370#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
2371#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
2372
2373/******************* Bit definition for CAN_TDL2R register ******************/
2374#define CAN_TDL2R_DATA0_Pos (0U)
2375#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
2376#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
2377#define CAN_TDL2R_DATA1_Pos (8U)
2378#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
2379#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
2380#define CAN_TDL2R_DATA2_Pos (16U)
2381#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
2382#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
2383#define CAN_TDL2R_DATA3_Pos (24U)
2384#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
2385#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
2386
2387/******************* Bit definition for CAN_TDH2R register ******************/
2388#define CAN_TDH2R_DATA4_Pos (0U)
2389#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
2390#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
2391#define CAN_TDH2R_DATA5_Pos (8U)
2392#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
2393#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
2394#define CAN_TDH2R_DATA6_Pos (16U)
2395#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
2396#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
2397#define CAN_TDH2R_DATA7_Pos (24U)
2398#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
2399#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
2400
2401/******************* Bit definition for CAN_RI0R register *******************/
2402#define CAN_RI0R_RTR_Pos (1U)
2403#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
2404#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
2405#define CAN_RI0R_IDE_Pos (2U)
2406#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
2407#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
2408#define CAN_RI0R_EXID_Pos (3U)
2409#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
2410#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
2411#define CAN_RI0R_STID_Pos (21U)
2412#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
2413#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2414
2415/******************* Bit definition for CAN_RDT0R register ******************/
2416#define CAN_RDT0R_DLC_Pos (0U)
2417#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
2418#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
2419#define CAN_RDT0R_FMI_Pos (8U)
2420#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
2421#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
2422#define CAN_RDT0R_TIME_Pos (16U)
2423#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2424#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
2425
2426/******************* Bit definition for CAN_RDL0R register ******************/
2427#define CAN_RDL0R_DATA0_Pos (0U)
2428#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
2429#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
2430#define CAN_RDL0R_DATA1_Pos (8U)
2431#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2432#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
2433#define CAN_RDL0R_DATA2_Pos (16U)
2434#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2435#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
2436#define CAN_RDL0R_DATA3_Pos (24U)
2437#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
2438#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
2439
2440/******************* Bit definition for CAN_RDH0R register ******************/
2441#define CAN_RDH0R_DATA4_Pos (0U)
2442#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
2443#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
2444#define CAN_RDH0R_DATA5_Pos (8U)
2445#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2446#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
2447#define CAN_RDH0R_DATA6_Pos (16U)
2448#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2449#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
2450#define CAN_RDH0R_DATA7_Pos (24U)
2451#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
2452#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
2453
2454/******************* Bit definition for CAN_RI1R register *******************/
2455#define CAN_RI1R_RTR_Pos (1U)
2456#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
2457#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
2458#define CAN_RI1R_IDE_Pos (2U)
2459#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
2460#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
2461#define CAN_RI1R_EXID_Pos (3U)
2462#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
2463#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
2464#define CAN_RI1R_STID_Pos (21U)
2465#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
2466#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2467
2468/******************* Bit definition for CAN_RDT1R register ******************/
2469#define CAN_RDT1R_DLC_Pos (0U)
2470#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
2471#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
2472#define CAN_RDT1R_FMI_Pos (8U)
2473#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
2474#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
2475#define CAN_RDT1R_TIME_Pos (16U)
2476#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2477#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
2478
2479/******************* Bit definition for CAN_RDL1R register ******************/
2480#define CAN_RDL1R_DATA0_Pos (0U)
2481#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
2482#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
2483#define CAN_RDL1R_DATA1_Pos (8U)
2484#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2485#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
2486#define CAN_RDL1R_DATA2_Pos (16U)
2487#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2488#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
2489#define CAN_RDL1R_DATA3_Pos (24U)
2490#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
2491#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
2492
2493/******************* Bit definition for CAN_RDH1R register ******************/
2494#define CAN_RDH1R_DATA4_Pos (0U)
2495#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
2496#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
2497#define CAN_RDH1R_DATA5_Pos (8U)
2498#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2499#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
2500#define CAN_RDH1R_DATA6_Pos (16U)
2501#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2502#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
2503#define CAN_RDH1R_DATA7_Pos (24U)
2504#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
2505#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
2506
2507/*!<CAN filter registers */
2508/******************* Bit definition for CAN_FMR register ********************/
2509#define CAN_FMR_FINIT ((uint8_t)0x01U) /*!<Filter Init Mode */
2510#define CAN_FMR_CAN2SB_Pos (8U)
2511#define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
2512#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
2513
2514/******************* Bit definition for CAN_FM1R register *******************/
2515#define CAN_FM1R_FBM_Pos (0U)
2516#define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
2517#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
2518#define CAN_FM1R_FBM0_Pos (0U)
2519#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
2520#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
2521#define CAN_FM1R_FBM1_Pos (1U)
2522#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
2523#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
2524#define CAN_FM1R_FBM2_Pos (2U)
2525#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
2526#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
2527#define CAN_FM1R_FBM3_Pos (3U)
2528#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
2529#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
2530#define CAN_FM1R_FBM4_Pos (4U)
2531#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
2532#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
2533#define CAN_FM1R_FBM5_Pos (5U)
2534#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
2535#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
2536#define CAN_FM1R_FBM6_Pos (6U)
2537#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
2538#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
2539#define CAN_FM1R_FBM7_Pos (7U)
2540#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
2541#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
2542#define CAN_FM1R_FBM8_Pos (8U)
2543#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
2544#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
2545#define CAN_FM1R_FBM9_Pos (9U)
2546#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
2547#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
2548#define CAN_FM1R_FBM10_Pos (10U)
2549#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
2550#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
2551#define CAN_FM1R_FBM11_Pos (11U)
2552#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
2553#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
2554#define CAN_FM1R_FBM12_Pos (12U)
2555#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
2556#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
2557#define CAN_FM1R_FBM13_Pos (13U)
2558#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
2559#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
2560
2561/******************* Bit definition for CAN_FS1R register *******************/
2562#define CAN_FS1R_FSC_Pos (0U)
2563#define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
2564#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
2565#define CAN_FS1R_FSC0_Pos (0U)
2566#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
2567#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
2568#define CAN_FS1R_FSC1_Pos (1U)
2569#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
2570#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
2571#define CAN_FS1R_FSC2_Pos (2U)
2572#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
2573#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
2574#define CAN_FS1R_FSC3_Pos (3U)
2575#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
2576#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
2577#define CAN_FS1R_FSC4_Pos (4U)
2578#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
2579#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
2580#define CAN_FS1R_FSC5_Pos (5U)
2581#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
2582#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
2583#define CAN_FS1R_FSC6_Pos (6U)
2584#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
2585#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
2586#define CAN_FS1R_FSC7_Pos (7U)
2587#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
2588#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
2589#define CAN_FS1R_FSC8_Pos (8U)
2590#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
2591#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
2592#define CAN_FS1R_FSC9_Pos (9U)
2593#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
2594#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
2595#define CAN_FS1R_FSC10_Pos (10U)
2596#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
2597#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
2598#define CAN_FS1R_FSC11_Pos (11U)
2599#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
2600#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
2601#define CAN_FS1R_FSC12_Pos (12U)
2602#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
2603#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
2604#define CAN_FS1R_FSC13_Pos (13U)
2605#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
2606#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
2607
2608/****************** Bit definition for CAN_FFA1R register *******************/
2609#define CAN_FFA1R_FFA_Pos (0U)
2610#define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
2611#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
2612#define CAN_FFA1R_FFA0_Pos (0U)
2613#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
2614#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
2615#define CAN_FFA1R_FFA1_Pos (1U)
2616#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
2617#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
2618#define CAN_FFA1R_FFA2_Pos (2U)
2619#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
2620#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
2621#define CAN_FFA1R_FFA3_Pos (3U)
2622#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
2623#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
2624#define CAN_FFA1R_FFA4_Pos (4U)
2625#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
2626#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
2627#define CAN_FFA1R_FFA5_Pos (5U)
2628#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
2629#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
2630#define CAN_FFA1R_FFA6_Pos (6U)
2631#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
2632#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
2633#define CAN_FFA1R_FFA7_Pos (7U)
2634#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
2635#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
2636#define CAN_FFA1R_FFA8_Pos (8U)
2637#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
2638#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
2639#define CAN_FFA1R_FFA9_Pos (9U)
2640#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
2641#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
2642#define CAN_FFA1R_FFA10_Pos (10U)
2643#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
2644#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
2645#define CAN_FFA1R_FFA11_Pos (11U)
2646#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
2647#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
2648#define CAN_FFA1R_FFA12_Pos (12U)
2649#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
2650#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
2651#define CAN_FFA1R_FFA13_Pos (13U)
2652#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
2653#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
2654
2655/******************* Bit definition for CAN_FA1R register *******************/
2656#define CAN_FA1R_FACT_Pos (0U)
2657#define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
2658#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
2659#define CAN_FA1R_FACT0_Pos (0U)
2660#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
2661#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
2662#define CAN_FA1R_FACT1_Pos (1U)
2663#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
2664#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
2665#define CAN_FA1R_FACT2_Pos (2U)
2666#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
2667#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
2668#define CAN_FA1R_FACT3_Pos (3U)
2669#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
2670#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
2671#define CAN_FA1R_FACT4_Pos (4U)
2672#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
2673#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
2674#define CAN_FA1R_FACT5_Pos (5U)
2675#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
2676#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
2677#define CAN_FA1R_FACT6_Pos (6U)
2678#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
2679#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
2680#define CAN_FA1R_FACT7_Pos (7U)
2681#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
2682#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
2683#define CAN_FA1R_FACT8_Pos (8U)
2684#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
2685#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
2686#define CAN_FA1R_FACT9_Pos (9U)
2687#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
2688#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
2689#define CAN_FA1R_FACT10_Pos (10U)
2690#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
2691#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
2692#define CAN_FA1R_FACT11_Pos (11U)
2693#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
2694#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
2695#define CAN_FA1R_FACT12_Pos (12U)
2696#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
2697#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
2698#define CAN_FA1R_FACT13_Pos (13U)
2699#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
2700#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
2701
2702/******************* Bit definition for CAN_F0R1 register *******************/
2703#define CAN_F0R1_FB0_Pos (0U)
2704#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
2705#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
2706#define CAN_F0R1_FB1_Pos (1U)
2707#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
2708#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
2709#define CAN_F0R1_FB2_Pos (2U)
2710#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
2711#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
2712#define CAN_F0R1_FB3_Pos (3U)
2713#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
2714#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
2715#define CAN_F0R1_FB4_Pos (4U)
2716#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
2717#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
2718#define CAN_F0R1_FB5_Pos (5U)
2719#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
2720#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
2721#define CAN_F0R1_FB6_Pos (6U)
2722#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
2723#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
2724#define CAN_F0R1_FB7_Pos (7U)
2725#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
2726#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
2727#define CAN_F0R1_FB8_Pos (8U)
2728#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
2729#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
2730#define CAN_F0R1_FB9_Pos (9U)
2731#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
2732#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
2733#define CAN_F0R1_FB10_Pos (10U)
2734#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
2735#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
2736#define CAN_F0R1_FB11_Pos (11U)
2737#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
2738#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
2739#define CAN_F0R1_FB12_Pos (12U)
2740#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
2741#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
2742#define CAN_F0R1_FB13_Pos (13U)
2743#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
2744#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
2745#define CAN_F0R1_FB14_Pos (14U)
2746#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
2747#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
2748#define CAN_F0R1_FB15_Pos (15U)
2749#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
2750#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
2751#define CAN_F0R1_FB16_Pos (16U)
2752#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
2753#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
2754#define CAN_F0R1_FB17_Pos (17U)
2755#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
2756#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
2757#define CAN_F0R1_FB18_Pos (18U)
2758#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
2759#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
2760#define CAN_F0R1_FB19_Pos (19U)
2761#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
2762#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
2763#define CAN_F0R1_FB20_Pos (20U)
2764#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
2765#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
2766#define CAN_F0R1_FB21_Pos (21U)
2767#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
2768#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
2769#define CAN_F0R1_FB22_Pos (22U)
2770#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
2771#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
2772#define CAN_F0R1_FB23_Pos (23U)
2773#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
2774#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
2775#define CAN_F0R1_FB24_Pos (24U)
2776#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
2777#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
2778#define CAN_F0R1_FB25_Pos (25U)
2779#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
2780#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
2781#define CAN_F0R1_FB26_Pos (26U)
2782#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
2783#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
2784#define CAN_F0R1_FB27_Pos (27U)
2785#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
2786#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
2787#define CAN_F0R1_FB28_Pos (28U)
2788#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
2789#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
2790#define CAN_F0R1_FB29_Pos (29U)
2791#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
2792#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
2793#define CAN_F0R1_FB30_Pos (30U)
2794#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
2795#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
2796#define CAN_F0R1_FB31_Pos (31U)
2797#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
2798#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
2799
2800/******************* Bit definition for CAN_F1R1 register *******************/
2801#define CAN_F1R1_FB0_Pos (0U)
2802#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
2803#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
2804#define CAN_F1R1_FB1_Pos (1U)
2805#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
2806#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
2807#define CAN_F1R1_FB2_Pos (2U)
2808#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
2809#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
2810#define CAN_F1R1_FB3_Pos (3U)
2811#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
2812#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
2813#define CAN_F1R1_FB4_Pos (4U)
2814#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
2815#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
2816#define CAN_F1R1_FB5_Pos (5U)
2817#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
2818#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
2819#define CAN_F1R1_FB6_Pos (6U)
2820#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
2821#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
2822#define CAN_F1R1_FB7_Pos (7U)
2823#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
2824#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
2825#define CAN_F1R1_FB8_Pos (8U)
2826#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
2827#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
2828#define CAN_F1R1_FB9_Pos (9U)
2829#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
2830#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
2831#define CAN_F1R1_FB10_Pos (10U)
2832#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
2833#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
2834#define CAN_F1R1_FB11_Pos (11U)
2835#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
2836#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
2837#define CAN_F1R1_FB12_Pos (12U)
2838#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
2839#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
2840#define CAN_F1R1_FB13_Pos (13U)
2841#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
2842#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
2843#define CAN_F1R1_FB14_Pos (14U)
2844#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
2845#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
2846#define CAN_F1R1_FB15_Pos (15U)
2847#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
2848#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
2849#define CAN_F1R1_FB16_Pos (16U)
2850#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
2851#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
2852#define CAN_F1R1_FB17_Pos (17U)
2853#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
2854#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
2855#define CAN_F1R1_FB18_Pos (18U)
2856#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
2857#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
2858#define CAN_F1R1_FB19_Pos (19U)
2859#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
2860#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
2861#define CAN_F1R1_FB20_Pos (20U)
2862#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
2863#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
2864#define CAN_F1R1_FB21_Pos (21U)
2865#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
2866#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
2867#define CAN_F1R1_FB22_Pos (22U)
2868#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
2869#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
2870#define CAN_F1R1_FB23_Pos (23U)
2871#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
2872#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
2873#define CAN_F1R1_FB24_Pos (24U)
2874#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
2875#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
2876#define CAN_F1R1_FB25_Pos (25U)
2877#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
2878#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
2879#define CAN_F1R1_FB26_Pos (26U)
2880#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
2881#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
2882#define CAN_F1R1_FB27_Pos (27U)
2883#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
2884#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
2885#define CAN_F1R1_FB28_Pos (28U)
2886#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
2887#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
2888#define CAN_F1R1_FB29_Pos (29U)
2889#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
2890#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
2891#define CAN_F1R1_FB30_Pos (30U)
2892#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
2893#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
2894#define CAN_F1R1_FB31_Pos (31U)
2895#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
2896#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
2897
2898/******************* Bit definition for CAN_F2R1 register *******************/
2899#define CAN_F2R1_FB0_Pos (0U)
2900#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
2901#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
2902#define CAN_F2R1_FB1_Pos (1U)
2903#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
2904#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
2905#define CAN_F2R1_FB2_Pos (2U)
2906#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
2907#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
2908#define CAN_F2R1_FB3_Pos (3U)
2909#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
2910#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
2911#define CAN_F2R1_FB4_Pos (4U)
2912#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
2913#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
2914#define CAN_F2R1_FB5_Pos (5U)
2915#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
2916#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
2917#define CAN_F2R1_FB6_Pos (6U)
2918#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
2919#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
2920#define CAN_F2R1_FB7_Pos (7U)
2921#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
2922#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
2923#define CAN_F2R1_FB8_Pos (8U)
2924#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
2925#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
2926#define CAN_F2R1_FB9_Pos (9U)
2927#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
2928#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
2929#define CAN_F2R1_FB10_Pos (10U)
2930#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
2931#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
2932#define CAN_F2R1_FB11_Pos (11U)
2933#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
2934#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
2935#define CAN_F2R1_FB12_Pos (12U)
2936#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
2937#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
2938#define CAN_F2R1_FB13_Pos (13U)
2939#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
2940#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
2941#define CAN_F2R1_FB14_Pos (14U)
2942#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
2943#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
2944#define CAN_F2R1_FB15_Pos (15U)
2945#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
2946#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
2947#define CAN_F2R1_FB16_Pos (16U)
2948#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
2949#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
2950#define CAN_F2R1_FB17_Pos (17U)
2951#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
2952#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
2953#define CAN_F2R1_FB18_Pos (18U)
2954#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
2955#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
2956#define CAN_F2R1_FB19_Pos (19U)
2957#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
2958#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
2959#define CAN_F2R1_FB20_Pos (20U)
2960#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
2961#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
2962#define CAN_F2R1_FB21_Pos (21U)
2963#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
2964#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
2965#define CAN_F2R1_FB22_Pos (22U)
2966#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
2967#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
2968#define CAN_F2R1_FB23_Pos (23U)
2969#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
2970#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
2971#define CAN_F2R1_FB24_Pos (24U)
2972#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
2973#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
2974#define CAN_F2R1_FB25_Pos (25U)
2975#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
2976#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
2977#define CAN_F2R1_FB26_Pos (26U)
2978#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
2979#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
2980#define CAN_F2R1_FB27_Pos (27U)
2981#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
2982#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
2983#define CAN_F2R1_FB28_Pos (28U)
2984#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
2985#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
2986#define CAN_F2R1_FB29_Pos (29U)
2987#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
2988#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
2989#define CAN_F2R1_FB30_Pos (30U)
2990#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
2991#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
2992#define CAN_F2R1_FB31_Pos (31U)
2993#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
2994#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
2995
2996/******************* Bit definition for CAN_F3R1 register *******************/
2997#define CAN_F3R1_FB0_Pos (0U)
2998#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
2999#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
3000#define CAN_F3R1_FB1_Pos (1U)
3001#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
3002#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
3003#define CAN_F3R1_FB2_Pos (2U)
3004#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
3005#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
3006#define CAN_F3R1_FB3_Pos (3U)
3007#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
3008#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
3009#define CAN_F3R1_FB4_Pos (4U)
3010#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
3011#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
3012#define CAN_F3R1_FB5_Pos (5U)
3013#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
3014#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
3015#define CAN_F3R1_FB6_Pos (6U)
3016#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
3017#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
3018#define CAN_F3R1_FB7_Pos (7U)
3019#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
3020#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
3021#define CAN_F3R1_FB8_Pos (8U)
3022#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
3023#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
3024#define CAN_F3R1_FB9_Pos (9U)
3025#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
3026#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
3027#define CAN_F3R1_FB10_Pos (10U)
3028#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
3029#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
3030#define CAN_F3R1_FB11_Pos (11U)
3031#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
3032#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
3033#define CAN_F3R1_FB12_Pos (12U)
3034#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
3035#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
3036#define CAN_F3R1_FB13_Pos (13U)
3037#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
3038#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
3039#define CAN_F3R1_FB14_Pos (14U)
3040#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
3041#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
3042#define CAN_F3R1_FB15_Pos (15U)
3043#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
3044#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
3045#define CAN_F3R1_FB16_Pos (16U)
3046#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
3047#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
3048#define CAN_F3R1_FB17_Pos (17U)
3049#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
3050#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
3051#define CAN_F3R1_FB18_Pos (18U)
3052#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
3053#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
3054#define CAN_F3R1_FB19_Pos (19U)
3055#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
3056#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
3057#define CAN_F3R1_FB20_Pos (20U)
3058#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
3059#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
3060#define CAN_F3R1_FB21_Pos (21U)
3061#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
3062#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
3063#define CAN_F3R1_FB22_Pos (22U)
3064#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
3065#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
3066#define CAN_F3R1_FB23_Pos (23U)
3067#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
3068#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
3069#define CAN_F3R1_FB24_Pos (24U)
3070#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
3071#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
3072#define CAN_F3R1_FB25_Pos (25U)
3073#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
3074#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
3075#define CAN_F3R1_FB26_Pos (26U)
3076#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
3077#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
3078#define CAN_F3R1_FB27_Pos (27U)
3079#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
3080#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
3081#define CAN_F3R1_FB28_Pos (28U)
3082#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
3083#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
3084#define CAN_F3R1_FB29_Pos (29U)
3085#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
3086#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
3087#define CAN_F3R1_FB30_Pos (30U)
3088#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
3089#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
3090#define CAN_F3R1_FB31_Pos (31U)
3091#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
3092#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
3093
3094/******************* Bit definition for CAN_F4R1 register *******************/
3095#define CAN_F4R1_FB0_Pos (0U)
3096#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
3097#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
3098#define CAN_F4R1_FB1_Pos (1U)
3099#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
3100#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
3101#define CAN_F4R1_FB2_Pos (2U)
3102#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
3103#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
3104#define CAN_F4R1_FB3_Pos (3U)
3105#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
3106#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
3107#define CAN_F4R1_FB4_Pos (4U)
3108#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
3109#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
3110#define CAN_F4R1_FB5_Pos (5U)
3111#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
3112#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
3113#define CAN_F4R1_FB6_Pos (6U)
3114#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
3115#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
3116#define CAN_F4R1_FB7_Pos (7U)
3117#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
3118#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
3119#define CAN_F4R1_FB8_Pos (8U)
3120#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
3121#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
3122#define CAN_F4R1_FB9_Pos (9U)
3123#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
3124#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
3125#define CAN_F4R1_FB10_Pos (10U)
3126#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
3127#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
3128#define CAN_F4R1_FB11_Pos (11U)
3129#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
3130#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
3131#define CAN_F4R1_FB12_Pos (12U)
3132#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
3133#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
3134#define CAN_F4R1_FB13_Pos (13U)
3135#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
3136#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
3137#define CAN_F4R1_FB14_Pos (14U)
3138#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
3139#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
3140#define CAN_F4R1_FB15_Pos (15U)
3141#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
3142#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
3143#define CAN_F4R1_FB16_Pos (16U)
3144#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
3145#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
3146#define CAN_F4R1_FB17_Pos (17U)
3147#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
3148#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
3149#define CAN_F4R1_FB18_Pos (18U)
3150#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
3151#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
3152#define CAN_F4R1_FB19_Pos (19U)
3153#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
3154#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
3155#define CAN_F4R1_FB20_Pos (20U)
3156#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
3157#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
3158#define CAN_F4R1_FB21_Pos (21U)
3159#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
3160#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
3161#define CAN_F4R1_FB22_Pos (22U)
3162#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
3163#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
3164#define CAN_F4R1_FB23_Pos (23U)
3165#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
3166#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
3167#define CAN_F4R1_FB24_Pos (24U)
3168#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
3169#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
3170#define CAN_F4R1_FB25_Pos (25U)
3171#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
3172#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
3173#define CAN_F4R1_FB26_Pos (26U)
3174#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
3175#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
3176#define CAN_F4R1_FB27_Pos (27U)
3177#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
3178#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
3179#define CAN_F4R1_FB28_Pos (28U)
3180#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
3181#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
3182#define CAN_F4R1_FB29_Pos (29U)
3183#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
3184#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
3185#define CAN_F4R1_FB30_Pos (30U)
3186#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
3187#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
3188#define CAN_F4R1_FB31_Pos (31U)
3189#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
3190#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
3191
3192/******************* Bit definition for CAN_F5R1 register *******************/
3193#define CAN_F5R1_FB0_Pos (0U)
3194#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
3195#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
3196#define CAN_F5R1_FB1_Pos (1U)
3197#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
3198#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
3199#define CAN_F5R1_FB2_Pos (2U)
3200#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
3201#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
3202#define CAN_F5R1_FB3_Pos (3U)
3203#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
3204#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
3205#define CAN_F5R1_FB4_Pos (4U)
3206#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
3207#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
3208#define CAN_F5R1_FB5_Pos (5U)
3209#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
3210#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
3211#define CAN_F5R1_FB6_Pos (6U)
3212#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
3213#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
3214#define CAN_F5R1_FB7_Pos (7U)
3215#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
3216#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
3217#define CAN_F5R1_FB8_Pos (8U)
3218#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
3219#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
3220#define CAN_F5R1_FB9_Pos (9U)
3221#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
3222#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
3223#define CAN_F5R1_FB10_Pos (10U)
3224#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
3225#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
3226#define CAN_F5R1_FB11_Pos (11U)
3227#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
3228#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
3229#define CAN_F5R1_FB12_Pos (12U)
3230#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
3231#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
3232#define CAN_F5R1_FB13_Pos (13U)
3233#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
3234#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
3235#define CAN_F5R1_FB14_Pos (14U)
3236#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
3237#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
3238#define CAN_F5R1_FB15_Pos (15U)
3239#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
3240#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
3241#define CAN_F5R1_FB16_Pos (16U)
3242#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
3243#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
3244#define CAN_F5R1_FB17_Pos (17U)
3245#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
3246#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
3247#define CAN_F5R1_FB18_Pos (18U)
3248#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
3249#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
3250#define CAN_F5R1_FB19_Pos (19U)
3251#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
3252#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
3253#define CAN_F5R1_FB20_Pos (20U)
3254#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
3255#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
3256#define CAN_F5R1_FB21_Pos (21U)
3257#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
3258#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
3259#define CAN_F5R1_FB22_Pos (22U)
3260#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
3261#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
3262#define CAN_F5R1_FB23_Pos (23U)
3263#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
3264#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
3265#define CAN_F5R1_FB24_Pos (24U)
3266#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
3267#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
3268#define CAN_F5R1_FB25_Pos (25U)
3269#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
3270#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
3271#define CAN_F5R1_FB26_Pos (26U)
3272#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
3273#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
3274#define CAN_F5R1_FB27_Pos (27U)
3275#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
3276#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
3277#define CAN_F5R1_FB28_Pos (28U)
3278#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
3279#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
3280#define CAN_F5R1_FB29_Pos (29U)
3281#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
3282#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
3283#define CAN_F5R1_FB30_Pos (30U)
3284#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
3285#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
3286#define CAN_F5R1_FB31_Pos (31U)
3287#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
3288#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
3289
3290/******************* Bit definition for CAN_F6R1 register *******************/
3291#define CAN_F6R1_FB0_Pos (0U)
3292#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
3293#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
3294#define CAN_F6R1_FB1_Pos (1U)
3295#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
3296#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
3297#define CAN_F6R1_FB2_Pos (2U)
3298#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
3299#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
3300#define CAN_F6R1_FB3_Pos (3U)
3301#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
3302#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
3303#define CAN_F6R1_FB4_Pos (4U)
3304#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
3305#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
3306#define CAN_F6R1_FB5_Pos (5U)
3307#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
3308#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
3309#define CAN_F6R1_FB6_Pos (6U)
3310#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
3311#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
3312#define CAN_F6R1_FB7_Pos (7U)
3313#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
3314#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
3315#define CAN_F6R1_FB8_Pos (8U)
3316#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
3317#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
3318#define CAN_F6R1_FB9_Pos (9U)
3319#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
3320#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
3321#define CAN_F6R1_FB10_Pos (10U)
3322#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
3323#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
3324#define CAN_F6R1_FB11_Pos (11U)
3325#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
3326#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
3327#define CAN_F6R1_FB12_Pos (12U)
3328#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
3329#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
3330#define CAN_F6R1_FB13_Pos (13U)
3331#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
3332#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
3333#define CAN_F6R1_FB14_Pos (14U)
3334#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
3335#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
3336#define CAN_F6R1_FB15_Pos (15U)
3337#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
3338#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
3339#define CAN_F6R1_FB16_Pos (16U)
3340#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
3341#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
3342#define CAN_F6R1_FB17_Pos (17U)
3343#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
3344#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
3345#define CAN_F6R1_FB18_Pos (18U)
3346#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
3347#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
3348#define CAN_F6R1_FB19_Pos (19U)
3349#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
3350#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
3351#define CAN_F6R1_FB20_Pos (20U)
3352#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
3353#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
3354#define CAN_F6R1_FB21_Pos (21U)
3355#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
3356#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
3357#define CAN_F6R1_FB22_Pos (22U)
3358#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
3359#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
3360#define CAN_F6R1_FB23_Pos (23U)
3361#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
3362#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
3363#define CAN_F6R1_FB24_Pos (24U)
3364#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
3365#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
3366#define CAN_F6R1_FB25_Pos (25U)
3367#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
3368#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
3369#define CAN_F6R1_FB26_Pos (26U)
3370#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
3371#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
3372#define CAN_F6R1_FB27_Pos (27U)
3373#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
3374#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
3375#define CAN_F6R1_FB28_Pos (28U)
3376#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
3377#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
3378#define CAN_F6R1_FB29_Pos (29U)
3379#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
3380#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
3381#define CAN_F6R1_FB30_Pos (30U)
3382#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
3383#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
3384#define CAN_F6R1_FB31_Pos (31U)
3385#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
3386#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
3387
3388/******************* Bit definition for CAN_F7R1 register *******************/
3389#define CAN_F7R1_FB0_Pos (0U)
3390#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
3391#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
3392#define CAN_F7R1_FB1_Pos (1U)
3393#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
3394#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
3395#define CAN_F7R1_FB2_Pos (2U)
3396#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
3397#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
3398#define CAN_F7R1_FB3_Pos (3U)
3399#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
3400#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
3401#define CAN_F7R1_FB4_Pos (4U)
3402#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
3403#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
3404#define CAN_F7R1_FB5_Pos (5U)
3405#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
3406#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
3407#define CAN_F7R1_FB6_Pos (6U)
3408#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
3409#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
3410#define CAN_F7R1_FB7_Pos (7U)
3411#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
3412#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
3413#define CAN_F7R1_FB8_Pos (8U)
3414#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
3415#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
3416#define CAN_F7R1_FB9_Pos (9U)
3417#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
3418#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
3419#define CAN_F7R1_FB10_Pos (10U)
3420#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
3421#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
3422#define CAN_F7R1_FB11_Pos (11U)
3423#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
3424#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
3425#define CAN_F7R1_FB12_Pos (12U)
3426#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
3427#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
3428#define CAN_F7R1_FB13_Pos (13U)
3429#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
3430#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
3431#define CAN_F7R1_FB14_Pos (14U)
3432#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
3433#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
3434#define CAN_F7R1_FB15_Pos (15U)
3435#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
3436#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
3437#define CAN_F7R1_FB16_Pos (16U)
3438#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
3439#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
3440#define CAN_F7R1_FB17_Pos (17U)
3441#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
3442#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
3443#define CAN_F7R1_FB18_Pos (18U)
3444#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
3445#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
3446#define CAN_F7R1_FB19_Pos (19U)
3447#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
3448#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
3449#define CAN_F7R1_FB20_Pos (20U)
3450#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
3451#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
3452#define CAN_F7R1_FB21_Pos (21U)
3453#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
3454#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
3455#define CAN_F7R1_FB22_Pos (22U)
3456#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
3457#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
3458#define CAN_F7R1_FB23_Pos (23U)
3459#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
3460#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
3461#define CAN_F7R1_FB24_Pos (24U)
3462#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
3463#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
3464#define CAN_F7R1_FB25_Pos (25U)
3465#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
3466#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
3467#define CAN_F7R1_FB26_Pos (26U)
3468#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
3469#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
3470#define CAN_F7R1_FB27_Pos (27U)
3471#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
3472#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
3473#define CAN_F7R1_FB28_Pos (28U)
3474#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
3475#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
3476#define CAN_F7R1_FB29_Pos (29U)
3477#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
3478#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
3479#define CAN_F7R1_FB30_Pos (30U)
3480#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
3481#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
3482#define CAN_F7R1_FB31_Pos (31U)
3483#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
3484#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
3485
3486/******************* Bit definition for CAN_F8R1 register *******************/
3487#define CAN_F8R1_FB0_Pos (0U)
3488#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
3489#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
3490#define CAN_F8R1_FB1_Pos (1U)
3491#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
3492#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
3493#define CAN_F8R1_FB2_Pos (2U)
3494#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
3495#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
3496#define CAN_F8R1_FB3_Pos (3U)
3497#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
3498#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
3499#define CAN_F8R1_FB4_Pos (4U)
3500#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
3501#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
3502#define CAN_F8R1_FB5_Pos (5U)
3503#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
3504#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
3505#define CAN_F8R1_FB6_Pos (6U)
3506#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
3507#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
3508#define CAN_F8R1_FB7_Pos (7U)
3509#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
3510#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
3511#define CAN_F8R1_FB8_Pos (8U)
3512#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
3513#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
3514#define CAN_F8R1_FB9_Pos (9U)
3515#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
3516#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
3517#define CAN_F8R1_FB10_Pos (10U)
3518#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
3519#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
3520#define CAN_F8R1_FB11_Pos (11U)
3521#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
3522#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
3523#define CAN_F8R1_FB12_Pos (12U)
3524#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
3525#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
3526#define CAN_F8R1_FB13_Pos (13U)
3527#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
3528#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
3529#define CAN_F8R1_FB14_Pos (14U)
3530#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
3531#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
3532#define CAN_F8R1_FB15_Pos (15U)
3533#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
3534#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
3535#define CAN_F8R1_FB16_Pos (16U)
3536#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
3537#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
3538#define CAN_F8R1_FB17_Pos (17U)
3539#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
3540#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
3541#define CAN_F8R1_FB18_Pos (18U)
3542#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
3543#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
3544#define CAN_F8R1_FB19_Pos (19U)
3545#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
3546#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
3547#define CAN_F8R1_FB20_Pos (20U)
3548#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
3549#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
3550#define CAN_F8R1_FB21_Pos (21U)
3551#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
3552#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
3553#define CAN_F8R1_FB22_Pos (22U)
3554#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
3555#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
3556#define CAN_F8R1_FB23_Pos (23U)
3557#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
3558#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
3559#define CAN_F8R1_FB24_Pos (24U)
3560#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
3561#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
3562#define CAN_F8R1_FB25_Pos (25U)
3563#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
3564#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
3565#define CAN_F8R1_FB26_Pos (26U)
3566#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
3567#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
3568#define CAN_F8R1_FB27_Pos (27U)
3569#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
3570#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
3571#define CAN_F8R1_FB28_Pos (28U)
3572#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
3573#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
3574#define CAN_F8R1_FB29_Pos (29U)
3575#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
3576#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
3577#define CAN_F8R1_FB30_Pos (30U)
3578#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
3579#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
3580#define CAN_F8R1_FB31_Pos (31U)
3581#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
3582#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
3583
3584/******************* Bit definition for CAN_F9R1 register *******************/
3585#define CAN_F9R1_FB0_Pos (0U)
3586#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
3587#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
3588#define CAN_F9R1_FB1_Pos (1U)
3589#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
3590#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
3591#define CAN_F9R1_FB2_Pos (2U)
3592#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
3593#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
3594#define CAN_F9R1_FB3_Pos (3U)
3595#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
3596#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
3597#define CAN_F9R1_FB4_Pos (4U)
3598#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
3599#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
3600#define CAN_F9R1_FB5_Pos (5U)
3601#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
3602#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
3603#define CAN_F9R1_FB6_Pos (6U)
3604#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
3605#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
3606#define CAN_F9R1_FB7_Pos (7U)
3607#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
3608#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
3609#define CAN_F9R1_FB8_Pos (8U)
3610#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
3611#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
3612#define CAN_F9R1_FB9_Pos (9U)
3613#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
3614#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
3615#define CAN_F9R1_FB10_Pos (10U)
3616#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
3617#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
3618#define CAN_F9R1_FB11_Pos (11U)
3619#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
3620#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
3621#define CAN_F9R1_FB12_Pos (12U)
3622#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
3623#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
3624#define CAN_F9R1_FB13_Pos (13U)
3625#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
3626#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
3627#define CAN_F9R1_FB14_Pos (14U)
3628#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
3629#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
3630#define CAN_F9R1_FB15_Pos (15U)
3631#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
3632#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
3633#define CAN_F9R1_FB16_Pos (16U)
3634#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
3635#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
3636#define CAN_F9R1_FB17_Pos (17U)
3637#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
3638#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
3639#define CAN_F9R1_FB18_Pos (18U)
3640#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
3641#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
3642#define CAN_F9R1_FB19_Pos (19U)
3643#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
3644#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
3645#define CAN_F9R1_FB20_Pos (20U)
3646#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
3647#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
3648#define CAN_F9R1_FB21_Pos (21U)
3649#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
3650#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
3651#define CAN_F9R1_FB22_Pos (22U)
3652#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
3653#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
3654#define CAN_F9R1_FB23_Pos (23U)
3655#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
3656#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
3657#define CAN_F9R1_FB24_Pos (24U)
3658#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
3659#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
3660#define CAN_F9R1_FB25_Pos (25U)
3661#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
3662#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
3663#define CAN_F9R1_FB26_Pos (26U)
3664#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
3665#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
3666#define CAN_F9R1_FB27_Pos (27U)
3667#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
3668#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
3669#define CAN_F9R1_FB28_Pos (28U)
3670#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
3671#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
3672#define CAN_F9R1_FB29_Pos (29U)
3673#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
3674#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
3675#define CAN_F9R1_FB30_Pos (30U)
3676#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
3677#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
3678#define CAN_F9R1_FB31_Pos (31U)
3679#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
3680#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
3681
3682/******************* Bit definition for CAN_F10R1 register ******************/
3683#define CAN_F10R1_FB0_Pos (0U)
3684#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
3685#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
3686#define CAN_F10R1_FB1_Pos (1U)
3687#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
3688#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
3689#define CAN_F10R1_FB2_Pos (2U)
3690#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
3691#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
3692#define CAN_F10R1_FB3_Pos (3U)
3693#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
3694#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
3695#define CAN_F10R1_FB4_Pos (4U)
3696#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
3697#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
3698#define CAN_F10R1_FB5_Pos (5U)
3699#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
3700#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
3701#define CAN_F10R1_FB6_Pos (6U)
3702#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */