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diff --git a/lib/chibios/os/common/ext/ST/STM32G0xx/stm32g070xx.h b/lib/chibios/os/common/ext/ST/STM32G0xx/stm32g070xx.h
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1/**
2 ******************************************************************************
3 * @file stm32g070xx.h
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
6 * This file contains all the peripheral register's definitions, bits
7 * definitions and memory mapping for stm32g070xx devices.
8 *
9 * This file contains:
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral's registers hardware
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
18 * All rights reserved.</center></h2>
19 *
20 * This software component is licensed by ST under BSD 3-Clause license,
21 * the "License"; You may not use this file except in compliance with the
22 * License. You may obtain a copy of the License at:
23 * opensource.org/licenses/BSD-3-Clause
24 *
25 ******************************************************************************
26 */
27
28/** @addtogroup CMSIS_Device
29 * @{
30 */
31
32/** @addtogroup stm32g070xx
33 * @{
34 */
35
36#ifndef STM32G070xx_H
37#define STM32G070xx_H
38
39#ifdef __cplusplus
40 extern "C" {
41#endif /* __cplusplus */
42
43/** @addtogroup Configuration_section_for_CMSIS
44 * @{
45 */
46
47/**
48 * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
49 */
50#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */
51#define __MPU_PRESENT 1 /*!< STM32G0xx provides an MPU */
52#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */
53#define __NVIC_PRIO_BITS 2 /*!< STM32G0xx uses 2 Bits for the Priority Levels */
54#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
55
56/**
57 * @}
58 */
59
60/** @addtogroup Peripheral_interrupt_number_definition
61 * @{
62 */
63
64/**
65 * @brief stm32g070xx Interrupt Number Definition, according to the selected device
66 * in @ref Library_configuration_section
67 */
68
69/*!< Interrupt Number Definition */
70typedef enum
71{
72/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/
73 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
74 HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
75 SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
76 PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
77 SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
78/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/
79 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
80 RTC_TAMP_IRQn = 2, /*!< RTC interrupt through the EXTI line 19 & 21 */
81 FLASH_IRQn = 3, /*!< FLASH global Interrupt */
82 RCC_IRQn = 4, /*!< RCC global Interrupt */
83 EXTI0_1_IRQn = 5, /*!< EXTI 0 and 1 Interrupts */
84 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
85 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
86 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
87 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
88 DMA1_Ch4_7_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 and DMAMUX1 Overrun Interrupts */
89 ADC1_IRQn = 12, /*!< ADC1 Interrupts */
90 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
91 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
92 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
93 TIM6_IRQn = 17, /*!< TIM6 global Interrupts */
94 TIM7_IRQn = 18, /*!< TIM7 global Interrupt */
95 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
96 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
97 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
98 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
99 I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */
100 I2C2_IRQn = 24, /*!< I2C2 Interrupt */
101 SPI1_IRQn = 25, /*!< SPI1 Interrupt */
102 SPI2_IRQn = 26, /*!< SPI2 Interrupt */
103 USART1_IRQn = 27, /*!< USART1 Interrupt */
104 USART2_IRQn = 28, /*!< USART2 Interrupt */
105 USART3_4_IRQn = 29, /*!< USART3, USART4 globlal Interrupts */
106} IRQn_Type;
107
108/**
109 * @}
110 */
111
112#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
113#include "system_stm32g0xx.h"
114#include <stdint.h>
115
116/** @addtogroup Peripheral_registers_structures
117 * @{
118 */
119
120/**
121 * @brief Analog to Digital Converter
122 */
123typedef struct
124{
125 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
126 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
127 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
128 __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */
129 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
130 __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */
131 uint32_t RESERVED1; /*!< Reserved, 0x18 */
132 uint32_t RESERVED2; /*!< Reserved, 0x1C */
133 __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
134 __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
135 __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */
136 __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */
137 uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */
138 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
139 uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */
140 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */
141 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */
142 uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */
143 __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */
144} ADC_TypeDef;
145
146typedef struct
147{
148 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
149} ADC_Common_TypeDef;
150
151
152
153/**
154 * @brief CRC calculation unit
155 */
156typedef struct
157{
158 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
159 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
160 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
161 uint32_t RESERVED1; /*!< Reserved, 0x0C */
162 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
163 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
164} CRC_TypeDef;
165
166
167/**
168 * @brief Debug MCU
169 */
170typedef struct
171{
172 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
173 __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */
174 __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */
175 __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */
176} DBG_TypeDef;
177
178/**
179 * @brief DMA Controller
180 */
181typedef struct
182{
183 __IO uint32_t CCR; /*!< DMA channel x configuration register */
184 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
185 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
186 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
187} DMA_Channel_TypeDef;
188
189typedef struct
190{
191 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
192 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
193} DMA_TypeDef;
194
195/**
196 * @brief DMA Multiplexer
197 */
198typedef struct
199{
200 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */
201}DMAMUX_Channel_TypeDef;
202
203typedef struct
204{
205 __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */
206 __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */
207}DMAMUX_ChannelStatus_TypeDef;
208
209typedef struct
210{
211 __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */
212}DMAMUX_RequestGen_TypeDef;
213
214typedef struct
215{
216 __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */
217 __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */
218}DMAMUX_RequestGenStatus_TypeDef;
219
220/**
221 * @brief Asynch Interrupt/Event Controller (EXTI)
222 */
223typedef struct
224{
225 __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */
226 __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */
227 __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */
228 __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */
229 __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */
230 uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */
231 uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */
232 uint32_t RESERVED3[11]; /*!< Reserved 3, 0x34 -- 0x5C */
233 __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */
234 uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */
235 __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */
236 __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */
237} EXTI_TypeDef;
238
239/**
240 * @brief FLASH Registers
241 */
242typedef struct
243{
244 __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */
245 uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */
246 __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */
247 __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */
248 __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */
249 __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */
250 __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
251 uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
252 __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */
253 uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x24--0x28 */
254 __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */
255 __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */
256 uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x34--0x38 */
257} FLASH_TypeDef;
258
259/**
260 * @brief General Purpose I/O
261 */
262typedef struct
263{
264 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
265 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
266 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
267 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
268 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
269 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
270 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
271 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
272 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
273 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
274} GPIO_TypeDef;
275
276
277/**
278 * @brief Inter-integrated Circuit Interface
279 */
280typedef struct
281{
282 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
283 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
284 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
285 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
286 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
287 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
288 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
289 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
290 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
291 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
292 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
293} I2C_TypeDef;
294
295/**
296 * @brief Independent WATCHDOG
297 */
298typedef struct
299{
300 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
301 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
302 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
303 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
304 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
305} IWDG_TypeDef;
306
307
308
309/**
310 * @brief Power Control
311 */
312typedef struct
313{
314 __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */
315 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */
316 __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */
317 __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */
318 __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */
319 __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */
320 __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */
321 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
322 __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */
323 __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */
324 __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */
325 __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */
326 __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */
327 __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */
328 __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */
329 __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */
330 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x40 */
331 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x44 */
332 __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */
333 __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */
334} PWR_TypeDef;
335
336/**
337 * @brief Reset and Clock Control
338 */
339typedef struct
340{
341 __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */
342 __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */
343 __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */
344 __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */
345 __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */
346 __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
347 __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */
348 __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */
349 __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */
350 __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */
351 __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */
352 __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */
353 __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */
354 __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */
355 __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */
356 __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */
357 __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */
358 __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */
359 __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */
360 __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */
361 __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */
362 __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */
363 __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */
364 __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x5C */
365 __IO uint32_t CSR; /*!< RCC Unregulated Domain Clock Control and Status Register, Address offset: 0x60 */
366} RCC_TypeDef;
367
368/**
369 * @brief Real-Time Clock
370 */
371typedef struct
372{
373 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
374 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
375 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
376 __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
377 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
378 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
379 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
380 uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */
381 uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */
382 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
383 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
384 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
385 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
386 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
387 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
388 uint32_t RESERVED2; /*!< Reserved Address offset: 0x1C */
389 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
390 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
391 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
392 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
393 __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
394 __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */
395 uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */
396 __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */
397 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */
398} RTC_TypeDef;
399
400/**
401 * @brief Tamper and backup registers
402 */
403typedef struct
404{
405 __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */
406 __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */
407 uint32_t RESERVED0; /*!< Reserved Address offset: 0x08 */
408 __IO uint32_t FLTCR; /*!< Reserved Address offset: 0x0C */
409 uint32_t RESERVED1[7]; /*!< Reserved Address offset: 0x10 -- 0x28 */
410 __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */
411 __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */
412 __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register, Address offset: 0x34 */
413 uint32_t RESERVED2; /*!< Reserved Address offset: 0x38 */
414 __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */
415 uint32_t RESERVED3[48]; /*!< Reserved Address offset: 0x54 -- 0xFC */
416 __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
417 __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
418 __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
419 __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
420 __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
421} TAMP_TypeDef;
422
423 /**
424 * @brief Serial Peripheral Interface
425 */
426typedef struct
427{
428 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
429 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
430 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
431 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
432 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
433 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
434 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
435 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
436 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
437} SPI_TypeDef;
438
439/**
440 * @brief System configuration controller
441 */
442typedef struct
443{
444 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
445 uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */
446 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
447 uint32_t RESERVED1[25]; /*!< Reserved 0x1C */
448 __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */
449} SYSCFG_TypeDef;
450
451/**
452 * @brief TIM
453 */
454typedef struct
455{
456 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
457 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
458 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
459 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
460 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
461 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
462 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
463 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
464 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
465 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
466 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
467 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
468 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
469 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
470 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
471 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
472 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
473 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
474 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
475 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
476 __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */
477 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
478 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
479 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
480 __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */
481 __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */
482 __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
483} TIM_TypeDef;
484
485/**
486 * @brief Universal Synchronous Asynchronous Receiver Transmitter
487 */
488typedef struct
489{
490 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
491 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
492 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
493 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
494 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
495 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
496 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
497 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
498 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
499 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
500 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
501 __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
502} USART_TypeDef;
503
504
505/**
506 * @brief Window WATCHDOG
507 */
508typedef struct
509{
510 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
511 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
512 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
513} WWDG_TypeDef;
514
515
516
517/** @addtogroup Peripheral_memory_map
518 * @{
519 */
520#define FLASH_BASE (0x08000000UL) /*!< FLASH base address */
521#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */
522#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
523#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */
524
525#define SRAM_SIZE_MAX (0x00008000UL) /*!< maximum SRAM size (up to 32 KBytes) */
526
527/*!< Peripheral memory map */
528#define APBPERIPH_BASE (PERIPH_BASE)
529#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
530
531/*!< APB peripherals */
532
533#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL)
534#define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL)
535#define TIM7_BASE (APBPERIPH_BASE + 0x00001400UL)
536#define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL)
537#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
538#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
539#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
540#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL)
541#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
542#define USART3_BASE (APBPERIPH_BASE + 0x00004800UL)
543#define USART4_BASE (APBPERIPH_BASE + 0x00004C00UL)
544#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
545#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL)
546#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
547#define TAMP_BASE (APBPERIPH_BASE + 0x0000B000UL)
548#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
549#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
550#define ADC1_COMMON_BASE (APBPERIPH_BASE + 0x00012708UL)
551#define ADC_BASE (ADC1_COMMON_BASE) /* Kept for legacy purpose */
552#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL)
553#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
554#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL)
555#define TIM15_BASE (APBPERIPH_BASE + 0x00014000UL)
556#define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL)
557#define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL)
558#define DBG_BASE (APBPERIPH_BASE + 0x00015800UL)
559
560
561/*!< AHB peripherals */
562#define DMA1_BASE (AHBPERIPH_BASE)
563#define DMAMUX1_BASE (AHBPERIPH_BASE + 0x00000800UL)
564#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
565#define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL)
566#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL)
567#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
568
569
570#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
571#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
572#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
573#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
574#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
575#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
576#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
577
578#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
579#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL)
580#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL)
581#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL)
582#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL)
583#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL)
584#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL)
585
586#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL)
587#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL)
588#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL)
589#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL)
590
591#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL)
592#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL)
593#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC)
594
595/*!< IOPORT */
596#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL)
597#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL)
598#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL)
599#define GPIOD_BASE (IOPORT_BASE + 0x00000C00UL)
600#define GPIOF_BASE (IOPORT_BASE + 0x00001400UL)
601
602/*!< Device Electronic Signature */
603#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */
604#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */
605#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */
606
607/**
608 * @}
609 */
610
611/** @addtogroup Peripheral_declaration
612 * @{
613 */
614#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
615#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
616#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
617#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
618#define RTC ((RTC_TypeDef *) RTC_BASE)
619#define TAMP ((TAMP_TypeDef *) TAMP_BASE)
620#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
621#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
622#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
623#define USART2 ((USART_TypeDef *) USART2_BASE)
624#define USART3 ((USART_TypeDef *) USART3_BASE)
625#define USART4 ((USART_TypeDef *) USART4_BASE)
626#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
627#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
628#define PWR ((PWR_TypeDef *) PWR_BASE)
629#define RCC ((RCC_TypeDef *) RCC_BASE)
630#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
631#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
632#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
633#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
634#define USART1 ((USART_TypeDef *) USART1_BASE)
635#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
636#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
637#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
638#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
639
640#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
641#define CRC ((CRC_TypeDef *) CRC_BASE)
642#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
643#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
644#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
645#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
646#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
647#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
648#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
649#define ADC (ADC1_COMMON) /* Kept for legacy purpose */
650
651
652
653#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
654#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
655#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
656#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
657#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
658#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
659#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
660
661#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
662#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
663#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
664#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
665#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
666#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
667#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
668#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
669
670#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
671#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
672#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
673#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
674
675#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
676#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
677#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE)
678
679#define DBG ((DBG_TypeDef *) DBG_BASE)
680
681/**
682 * @}
683 */
684
685/** @addtogroup Exported_constants
686 * @{
687 */
688
689 /** @addtogroup Peripheral_Registers_Bits_Definition
690 * @{
691 */
692
693/******************************************************************************/
694/* Peripheral Registers Bits Definition */
695/******************************************************************************/
696
697/******************************************************************************/
698/* */
699/* Analog to Digital Converter (ADC) */
700/* */
701/******************************************************************************/
702/******************** Bit definition for ADC_ISR register *******************/
703#define ADC_ISR_ADRDY_Pos (0U)
704#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
705#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
706#define ADC_ISR_EOSMP_Pos (1U)
707#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
708#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
709#define ADC_ISR_EOC_Pos (2U)
710#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
711#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
712#define ADC_ISR_EOS_Pos (3U)
713#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
714#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
715#define ADC_ISR_OVR_Pos (4U)
716#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
717#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
718#define ADC_ISR_AWD1_Pos (7U)
719#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
720#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
721#define ADC_ISR_AWD2_Pos (8U)
722#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
723#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
724#define ADC_ISR_AWD3_Pos (9U)
725#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
726#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
727#define ADC_ISR_EOCAL_Pos (11U)
728#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
729#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */
730#define ADC_ISR_CCRDY_Pos (13U)
731#define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */
732#define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */
733
734/* Legacy defines */
735#define ADC_ISR_EOSEQ (ADC_ISR_EOS)
736
737/******************** Bit definition for ADC_IER register *******************/
738#define ADC_IER_ADRDYIE_Pos (0U)
739#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
740#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
741#define ADC_IER_EOSMPIE_Pos (1U)
742#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
743#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
744#define ADC_IER_EOCIE_Pos (2U)
745#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
746#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
747#define ADC_IER_EOSIE_Pos (3U)
748#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
749#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
750#define ADC_IER_OVRIE_Pos (4U)
751#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
752#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
753#define ADC_IER_AWD1IE_Pos (7U)
754#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
755#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
756#define ADC_IER_AWD2IE_Pos (8U)
757#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
758#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
759#define ADC_IER_AWD3IE_Pos (9U)
760#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
761#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
762#define ADC_IER_EOCALIE_Pos (11U)
763#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
764#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */
765#define ADC_IER_CCRDYIE_Pos (13U)
766#define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */
767#define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */
768
769/* Legacy defines */
770#define ADC_IER_EOSEQIE (ADC_IER_EOSIE)
771
772/******************** Bit definition for ADC_CR register ********************/
773#define ADC_CR_ADEN_Pos (0U)
774#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
775#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
776#define ADC_CR_ADDIS_Pos (1U)
777#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
778#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
779#define ADC_CR_ADSTART_Pos (2U)
780#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
781#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
782#define ADC_CR_ADSTP_Pos (4U)
783#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
784#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
785#define ADC_CR_ADVREGEN_Pos (28U)
786#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
787#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
788#define ADC_CR_ADCAL_Pos (31U)
789#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
790#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
791
792/******************** Bit definition for ADC_CFGR1 register *****************/
793#define ADC_CFGR1_DMAEN_Pos (0U)
794#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
795#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */
796#define ADC_CFGR1_DMACFG_Pos (1U)
797#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
798#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */
799
800#define ADC_CFGR1_SCANDIR_Pos (2U)
801#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
802#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */
803
804#define ADC_CFGR1_RES_Pos (3U)
805#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
806#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */
807#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
808#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
809
810#define ADC_CFGR1_ALIGN_Pos (5U)
811#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
812#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */
813
814#define ADC_CFGR1_EXTSEL_Pos (6U)
815#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
816#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */
817#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
818#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
819#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
820
821#define ADC_CFGR1_EXTEN_Pos (10U)
822#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
823#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */
824#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
825#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
826
827#define ADC_CFGR1_OVRMOD_Pos (12U)
828#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
829#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */
830#define ADC_CFGR1_CONT_Pos (13U)
831#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
832#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */
833#define ADC_CFGR1_WAIT_Pos (14U)
834#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
835#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */
836#define ADC_CFGR1_AUTOFF_Pos (15U)
837#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
838#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */
839#define ADC_CFGR1_DISCEN_Pos (16U)
840#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
841#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
842#define ADC_CFGR1_CHSELRMOD_Pos (21U)
843#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */
844#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */
845
846#define ADC_CFGR1_AWD1SGL_Pos (22U)
847#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
848#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
849#define ADC_CFGR1_AWD1EN_Pos (23U)
850#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
851#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
852
853#define ADC_CFGR1_AWD1CH_Pos (26U)
854#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */
855#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
856#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */
857#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */
858#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */
859#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */
860#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */
861
862/* Legacy defines */
863#define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT)
864
865/******************** Bit definition for ADC_CFGR2 register *****************/
866#define ADC_CFGR2_OVSE_Pos (0U)
867#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
868#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
869
870#define ADC_CFGR2_OVSR_Pos (2U)
871#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
872#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
873#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
874#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
875#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
876
877#define ADC_CFGR2_OVSS_Pos (5U)
878#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
879#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
880#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
881#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
882#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
883#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
884
885#define ADC_CFGR2_TOVS_Pos (9U)
886#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */
887#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
888
889#define ADC_CFGR2_LFTRIG_Pos (29U)
890#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */
891#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */
892
893#define ADC_CFGR2_CKMODE_Pos (30U)
894#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
895#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */
896#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
897#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
898
899/******************** Bit definition for ADC_SMPR register ******************/
900#define ADC_SMPR_SMP1_Pos (0U)
901#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */
902#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */
903#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */
904#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */
905#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */
906
907#define ADC_SMPR_SMP2_Pos (4U)
908#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */
909#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */
910#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */
911#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */
912#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */
913
914#define ADC_SMPR_SMPSEL_Pos (8U)
915#define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */
916#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */
917#define ADC_SMPR_SMPSEL0_Pos (8U)
918#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */
919#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */
920#define ADC_SMPR_SMPSEL1_Pos (9U)
921#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */
922#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */
923#define ADC_SMPR_SMPSEL2_Pos (10U)
924#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */
925#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */
926#define ADC_SMPR_SMPSEL3_Pos (11U)
927#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */
928#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */
929#define ADC_SMPR_SMPSEL4_Pos (12U)
930#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */
931#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */
932#define ADC_SMPR_SMPSEL5_Pos (13U)
933#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */
934#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */
935#define ADC_SMPR_SMPSEL6_Pos (14U)
936#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */
937#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */
938#define ADC_SMPR_SMPSEL7_Pos (15U)
939#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */
940#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */
941#define ADC_SMPR_SMPSEL8_Pos (16U)
942#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */
943#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */
944#define ADC_SMPR_SMPSEL9_Pos (17U)
945#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */
946#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */
947#define ADC_SMPR_SMPSEL10_Pos (18U)
948#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */
949#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */
950#define ADC_SMPR_SMPSEL11_Pos (19U)
951#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */
952#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */
953#define ADC_SMPR_SMPSEL12_Pos (20U)
954#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */
955#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */
956#define ADC_SMPR_SMPSEL13_Pos (21U)
957#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */
958#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */
959#define ADC_SMPR_SMPSEL14_Pos (22U)
960#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */
961#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */
962#define ADC_SMPR_SMPSEL15_Pos (23U)
963#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */
964#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */
965#define ADC_SMPR_SMPSEL16_Pos (24U)
966#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */
967#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */
968#define ADC_SMPR_SMPSEL17_Pos (25U)
969#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */
970#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */
971#define ADC_SMPR_SMPSEL18_Pos (26U)
972#define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */
973#define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */
974
975/******************** Bit definition for ADC_TR1 register *******************/
976#define ADC_TR1_LT1_Pos (0U)
977#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
978#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
979#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
980#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
981#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
982#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
983#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
984#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
985#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
986#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
987#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
988#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
989#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
990#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
991
992#define ADC_TR1_HT1_Pos (16U)
993#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
994#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
995#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
996#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
997#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
998#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
999#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
1000#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
1001#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
1002#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
1003#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
1004#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
1005#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
1006#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
1007
1008/******************** Bit definition for ADC_TR2 register *******************/
1009#define ADC_TR2_LT2_Pos (0U)
1010#define ADC_TR2_LT2_Msk (0xFFFUL << ADC_TR2_LT2_Pos) /*!< 0x00000FFF */
1011#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
1012#define ADC_TR2_LT2_0 (0x001UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
1013#define ADC_TR2_LT2_1 (0x002UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
1014#define ADC_TR2_LT2_2 (0x004UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
1015#define ADC_TR2_LT2_3 (0x008UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
1016#define ADC_TR2_LT2_4 (0x010UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
1017#define ADC_TR2_LT2_5 (0x020UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
1018#define ADC_TR2_LT2_6 (0x040UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
1019#define ADC_TR2_LT2_7 (0x080UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
1020#define ADC_TR2_LT2_8 (0x100UL << ADC_TR2_LT2_Pos) /*!< 0x00000100 */
1021#define ADC_TR2_LT2_9 (0x200UL << ADC_TR2_LT2_Pos) /*!< 0x00000200 */
1022#define ADC_TR2_LT2_10 (0x400UL << ADC_TR2_LT2_Pos) /*!< 0x00000400 */
1023#define ADC_TR2_LT2_11 (0x800UL << ADC_TR2_LT2_Pos) /*!< 0x00000800 */
1024
1025#define ADC_TR2_HT2_Pos (16U)
1026#define ADC_TR2_HT2_Msk (0xFFFUL << ADC_TR2_HT2_Pos) /*!< 0x0FFF0000 */
1027#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
1028#define ADC_TR2_HT2_0 (0x001UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
1029#define ADC_TR2_HT2_1 (0x002UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
1030#define ADC_TR2_HT2_2 (0x004UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
1031#define ADC_TR2_HT2_3 (0x008UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
1032#define ADC_TR2_HT2_4 (0x010UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
1033#define ADC_TR2_HT2_5 (0x020UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
1034#define ADC_TR2_HT2_6 (0x040UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
1035#define ADC_TR2_HT2_7 (0x080UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
1036#define ADC_TR2_HT2_8 (0x100UL << ADC_TR2_HT2_Pos) /*!< 0x01000000 */
1037#define ADC_TR2_HT2_9 (0x200UL << ADC_TR2_HT2_Pos) /*!< 0x02000000 */
1038#define ADC_TR2_HT2_10 (0x400UL << ADC_TR2_HT2_Pos) /*!< 0x04000000 */
1039#define ADC_TR2_HT2_11 (0x800UL << ADC_TR2_HT2_Pos) /*!< 0x08000000 */
1040
1041/******************** Bit definition for ADC_CHSELR register ****************/
1042#define ADC_CHSELR_CHSEL_Pos (0U)
1043#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
1044#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
1045#define ADC_CHSELR_CHSEL18_Pos (18U)
1046#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
1047#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
1048#define ADC_CHSELR_CHSEL17_Pos (17U)
1049#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
1050#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
1051#define ADC_CHSELR_CHSEL16_Pos (16U)
1052#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */
1053#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
1054#define ADC_CHSELR_CHSEL15_Pos (15U)
1055#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
1056#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
1057#define ADC_CHSELR_CHSEL14_Pos (14U)
1058#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
1059#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
1060#define ADC_CHSELR_CHSEL13_Pos (13U)
1061#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
1062#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
1063#define ADC_CHSELR_CHSEL12_Pos (12U)
1064#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
1065#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
1066#define ADC_CHSELR_CHSEL11_Pos (11U)
1067#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
1068#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
1069#define ADC_CHSELR_CHSEL10_Pos (10U)
1070#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
1071#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
1072#define ADC_CHSELR_CHSEL9_Pos (9U)
1073#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
1074#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
1075#define ADC_CHSELR_CHSEL8_Pos (8U)
1076#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
1077#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
1078#define ADC_CHSELR_CHSEL7_Pos (7U)
1079#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
1080#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
1081#define ADC_CHSELR_CHSEL6_Pos (6U)
1082#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
1083#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
1084#define ADC_CHSELR_CHSEL5_Pos (5U)
1085#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
1086#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
1087#define ADC_CHSELR_CHSEL4_Pos (4U)
1088#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
1089#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
1090#define ADC_CHSELR_CHSEL3_Pos (3U)
1091#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
1092#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
1093#define ADC_CHSELR_CHSEL2_Pos (2U)
1094#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
1095#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
1096#define ADC_CHSELR_CHSEL1_Pos (1U)
1097#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
1098#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
1099#define ADC_CHSELR_CHSEL0_Pos (0U)
1100#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
1101#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
1102
1103#define ADC_CHSELR_SQ_ALL_Pos (0U)
1104#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */
1105#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */
1106
1107#define ADC_CHSELR_SQ8_Pos (28U)
1108#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */
1109#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */
1110#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */
1111#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */
1112#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */
1113#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */
1114
1115#define ADC_CHSELR_SQ7_Pos (24U)
1116#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */
1117#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */
1118#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */
1119#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */
1120#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */
1121#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */
1122
1123#define ADC_CHSELR_SQ6_Pos (20U)
1124#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */
1125#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */
1126#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */
1127#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */
1128#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */
1129#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */
1130
1131#define ADC_CHSELR_SQ5_Pos (16U)
1132#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */
1133#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */
1134#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */
1135#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */
1136#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */
1137#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */
1138
1139#define ADC_CHSELR_SQ4_Pos (12U)
1140#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */
1141#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */
1142#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */
1143#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */
1144#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */
1145#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */
1146
1147#define ADC_CHSELR_SQ3_Pos (8U)
1148#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */
1149#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */
1150#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */
1151#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */
1152#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */
1153#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */
1154
1155#define ADC_CHSELR_SQ2_Pos (4U)
1156#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */
1157#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */
1158#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */
1159#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */
1160#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */
1161#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */
1162
1163#define ADC_CHSELR_SQ1_Pos (0U)
1164#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */
1165#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */
1166#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */
1167#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */
1168#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */
1169#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */
1170
1171/******************** Bit definition for ADC_TR3 register *******************/
1172#define ADC_TR3_LT3_Pos (0U)
1173#define ADC_TR3_LT3_Msk (0xFFFUL << ADC_TR3_LT3_Pos) /*!< 0x00000FFF */
1174#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
1175#define ADC_TR3_LT3_0 (0x001UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
1176#define ADC_TR3_LT3_1 (0x002UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
1177#define ADC_TR3_LT3_2 (0x004UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
1178#define ADC_TR3_LT3_3 (0x008UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
1179#define ADC_TR3_LT3_4 (0x010UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
1180#define ADC_TR3_LT3_5 (0x020UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
1181#define ADC_TR3_LT3_6 (0x040UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
1182#define ADC_TR3_LT3_7 (0x080UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
1183#define ADC_TR3_LT3_8 (0x100UL << ADC_TR3_LT3_Pos) /*!< 0x00000100 */
1184#define ADC_TR3_LT3_9 (0x200UL << ADC_TR3_LT3_Pos) /*!< 0x00000200 */
1185#define ADC_TR3_LT3_10 (0x400UL << ADC_TR3_LT3_Pos) /*!< 0x00000400 */
1186#define ADC_TR3_LT3_11 (0x800UL << ADC_TR3_LT3_Pos) /*!< 0x00000800 */
1187
1188#define ADC_TR3_HT3_Pos (16U)
1189#define ADC_TR3_HT3_Msk (0xFFFUL << ADC_TR3_HT3_Pos) /*!< 0x0FFF0000 */
1190#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
1191#define ADC_TR3_HT3_0 (0x001UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
1192#define ADC_TR3_HT3_1 (0x002UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
1193#define ADC_TR3_HT3_2 (0x004UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
1194#define ADC_TR3_HT3_3 (0x008UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
1195#define ADC_TR3_HT3_4 (0x010UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
1196#define ADC_TR3_HT3_5 (0x020UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
1197#define ADC_TR3_HT3_6 (0x040UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
1198#define ADC_TR3_HT3_7 (0x080UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
1199#define ADC_TR3_HT3_8 (0x100UL << ADC_TR3_HT3_Pos) /*!< 0x01000000 */
1200#define ADC_TR3_HT3_9 (0x200UL << ADC_TR3_HT3_Pos) /*!< 0x02000000 */
1201#define ADC_TR3_HT3_10 (0x400UL << ADC_TR3_HT3_Pos) /*!< 0x04000000 */
1202#define ADC_TR3_HT3_11 (0x800UL << ADC_TR3_HT3_Pos) /*!< 0x08000000 */
1203
1204/******************** Bit definition for ADC_DR register ********************/
1205#define ADC_DR_DATA_Pos (0U)
1206#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
1207#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
1208#define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */
1209#define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */
1210#define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */
1211#define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */
1212#define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */
1213#define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */
1214#define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */
1215#define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */
1216#define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */
1217#define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */
1218#define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */
1219#define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */
1220#define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */
1221#define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */
1222#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */
1223#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */
1224
1225/******************** Bit definition for ADC_AWD2CR register ****************/
1226#define ADC_AWD2CR_AWD2CH_Pos (0U)
1227#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
1228#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
1229#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
1230#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
1231#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
1232#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
1233#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
1234#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
1235#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
1236#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
1237#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
1238#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
1239#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
1240#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
1241#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
1242#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
1243#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
1244#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
1245#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
1246#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
1247#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
1248
1249/******************** Bit definition for ADC_AWD3CR register ****************/
1250#define ADC_AWD3CR_AWD3CH_Pos (0U)
1251#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
1252#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
1253#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
1254#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
1255#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
1256#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
1257#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
1258#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
1259#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
1260#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
1261#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
1262#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
1263#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
1264#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
1265#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
1266#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
1267#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
1268#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
1269#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
1270#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
1271#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
1272
1273/******************** Bit definition for ADC_CALFACT register ***************/
1274#define ADC_CALFACT_CALFACT_Pos (0U)
1275#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
1276#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */
1277#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */
1278#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */
1279#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */
1280#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */
1281#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */
1282#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */
1283#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */
1284
1285/************************* ADC Common registers *****************************/
1286/******************** Bit definition for ADC_CCR register *******************/
1287#define ADC_CCR_PRESC_Pos (18U)
1288#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
1289#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
1290#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
1291#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
1292#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
1293#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
1294
1295#define ADC_CCR_VREFEN_Pos (22U)
1296#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
1297#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
1298#define ADC_CCR_TSEN_Pos (23U)
1299#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
1300#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
1301#define ADC_CCR_VBATEN_Pos (24U)
1302#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
1303#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
1304
1305#define ADC_CCR_LFMEN_Pos (25U)
1306#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
1307#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */
1308
1309
1310/******************************************************************************/
1311/* */
1312/* CRC calculation unit */
1313/* */
1314/******************************************************************************/
1315/******************* Bit definition for CRC_DR register *********************/
1316#define CRC_DR_DR_Pos (0U)
1317#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
1318#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
1319
1320/******************* Bit definition for CRC_IDR register ********************/
1321#define CRC_IDR_IDR_Pos (0U)
1322#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
1323#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */
1324
1325/******************** Bit definition for CRC_CR register ********************/
1326#define CRC_CR_RESET_Pos (0U)
1327#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
1328#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
1329#define CRC_CR_POLYSIZE_Pos (3U)
1330#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
1331#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
1332#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
1333#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
1334#define CRC_CR_REV_IN_Pos (5U)
1335#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
1336#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
1337#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
1338#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
1339#define CRC_CR_REV_OUT_Pos (7U)
1340#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
1341#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
1342
1343/******************* Bit definition for CRC_INIT register *******************/
1344#define CRC_INIT_INIT_Pos (0U)
1345#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
1346#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
1347
1348/******************* Bit definition for CRC_POL register ********************/
1349#define CRC_POL_POL_Pos (0U)
1350#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
1351#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
1352
1353
1354
1355/******************************************************************************/
1356/* */
1357/* Debug MCU */
1358/* */
1359/******************************************************************************/
1360
1361/******************************************************************************/
1362/* */
1363/* DMA Controller (DMA) */
1364/* */
1365/******************************************************************************/
1366
1367/******************* Bit definition for DMA_ISR register ********************/
1368#define DMA_ISR_GIF1_Pos (0U)
1369#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
1370#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
1371#define DMA_ISR_TCIF1_Pos (1U)
1372#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
1373#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
1374#define DMA_ISR_HTIF1_Pos (2U)
1375#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
1376#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
1377#define DMA_ISR_TEIF1_Pos (3U)
1378#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
1379#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
1380#define DMA_ISR_GIF2_Pos (4U)
1381#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
1382#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
1383#define DMA_ISR_TCIF2_Pos (5U)
1384#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
1385#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
1386#define DMA_ISR_HTIF2_Pos (6U)
1387#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
1388#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
1389#define DMA_ISR_TEIF2_Pos (7U)
1390#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
1391#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
1392#define DMA_ISR_GIF3_Pos (8U)
1393#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
1394#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
1395#define DMA_ISR_TCIF3_Pos (9U)
1396#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
1397#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
1398#define DMA_ISR_HTIF3_Pos (10U)
1399#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
1400#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
1401#define DMA_ISR_TEIF3_Pos (11U)
1402#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
1403#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
1404#define DMA_ISR_GIF4_Pos (12U)
1405#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
1406#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
1407#define DMA_ISR_TCIF4_Pos (13U)
1408#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
1409#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
1410#define DMA_ISR_HTIF4_Pos (14U)
1411#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
1412#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
1413#define DMA_ISR_TEIF4_Pos (15U)
1414#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
1415#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
1416#define DMA_ISR_GIF5_Pos (16U)
1417#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
1418#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
1419#define DMA_ISR_TCIF5_Pos (17U)
1420#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
1421#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
1422#define DMA_ISR_HTIF5_Pos (18U)
1423#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
1424#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
1425#define DMA_ISR_TEIF5_Pos (19U)
1426#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
1427#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
1428#define DMA_ISR_GIF6_Pos (20U)
1429#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
1430#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
1431#define DMA_ISR_TCIF6_Pos (21U)
1432#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
1433#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
1434#define DMA_ISR_HTIF6_Pos (22U)
1435#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
1436#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
1437#define DMA_ISR_TEIF6_Pos (23U)
1438#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
1439#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
1440#define DMA_ISR_GIF7_Pos (24U)
1441#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
1442#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
1443#define DMA_ISR_TCIF7_Pos (25U)
1444#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
1445#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
1446#define DMA_ISR_HTIF7_Pos (26U)
1447#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
1448#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
1449#define DMA_ISR_TEIF7_Pos (27U)
1450#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
1451#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
1452
1453/******************* Bit definition for DMA_IFCR register *******************/
1454#define DMA_IFCR_CGIF1_Pos (0U)
1455#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
1456#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
1457#define DMA_IFCR_CTCIF1_Pos (1U)
1458#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
1459#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
1460#define DMA_IFCR_CHTIF1_Pos (2U)
1461#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1462#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
1463#define DMA_IFCR_CTEIF1_Pos (3U)
1464#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
1465#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
1466#define DMA_IFCR_CGIF2_Pos (4U)
1467#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
1468#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
1469#define DMA_IFCR_CTCIF2_Pos (5U)
1470#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
1471#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
1472#define DMA_IFCR_CHTIF2_Pos (6U)
1473#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
1474#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
1475#define DMA_IFCR_CTEIF2_Pos (7U)
1476#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
1477#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
1478#define DMA_IFCR_CGIF3_Pos (8U)
1479#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
1480#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
1481#define DMA_IFCR_CTCIF3_Pos (9U)
1482#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
1483#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
1484#define DMA_IFCR_CHTIF3_Pos (10U)
1485#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
1486#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
1487#define DMA_IFCR_CTEIF3_Pos (11U)
1488#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
1489#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
1490#define DMA_IFCR_CGIF4_Pos (12U)
1491#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
1492#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
1493#define DMA_IFCR_CTCIF4_Pos (13U)
1494#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
1495#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
1496#define DMA_IFCR_CHTIF4_Pos (14U)
1497#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
1498#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
1499#define DMA_IFCR_CTEIF4_Pos (15U)
1500#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
1501#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
1502#define DMA_IFCR_CGIF5_Pos (16U)
1503#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
1504#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
1505#define DMA_IFCR_CTCIF5_Pos (17U)
1506#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
1507#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
1508#define DMA_IFCR_CHTIF5_Pos (18U)
1509#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
1510#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
1511#define DMA_IFCR_CTEIF5_Pos (19U)
1512#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
1513#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
1514#define DMA_IFCR_CGIF6_Pos (20U)
1515#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
1516#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
1517#define DMA_IFCR_CTCIF6_Pos (21U)
1518#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
1519#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
1520#define DMA_IFCR_CHTIF6_Pos (22U)
1521#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
1522#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
1523#define DMA_IFCR_CTEIF6_Pos (23U)
1524#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
1525#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
1526#define DMA_IFCR_CGIF7_Pos (24U)
1527#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
1528#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
1529#define DMA_IFCR_CTCIF7_Pos (25U)
1530#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
1531#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
1532#define DMA_IFCR_CHTIF7_Pos (26U)
1533#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
1534#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
1535#define DMA_IFCR_CTEIF7_Pos (27U)
1536#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
1537#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
1538
1539/******************* Bit definition for DMA_CCR register ********************/
1540#define DMA_CCR_EN_Pos (0U)
1541#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
1542#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
1543#define DMA_CCR_TCIE_Pos (1U)
1544#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
1545#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
1546#define DMA_CCR_HTIE_Pos (2U)
1547#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
1548#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
1549#define DMA_CCR_TEIE_Pos (3U)
1550#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
1551#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
1552#define DMA_CCR_DIR_Pos (4U)
1553#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
1554#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
1555#define DMA_CCR_CIRC_Pos (5U)
1556#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
1557#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
1558#define DMA_CCR_PINC_Pos (6U)
1559#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
1560#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
1561#define DMA_CCR_MINC_Pos (7U)
1562#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
1563#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
1564
1565#define DMA_CCR_PSIZE_Pos (8U)
1566#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
1567#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
1568#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
1569#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
1570
1571#define DMA_CCR_MSIZE_Pos (10U)
1572#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
1573#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
1574#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
1575#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
1576
1577#define DMA_CCR_PL_Pos (12U)
1578#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
1579#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
1580#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
1581#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
1582
1583#define DMA_CCR_MEM2MEM_Pos (14U)
1584#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
1585#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
1586
1587/****************** Bit definition for DMA_CNDTR register *******************/
1588#define DMA_CNDTR_NDT_Pos (0U)
1589#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
1590#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
1591
1592/****************** Bit definition for DMA_CPAR register ********************/
1593#define DMA_CPAR_PA_Pos (0U)
1594#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
1595#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
1596
1597/****************** Bit definition for DMA_CMAR register ********************/
1598#define DMA_CMAR_MA_Pos (0U)
1599#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
1600#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
1601
1602/******************************************************************************/
1603/* */
1604/* DMAMUX Controller */
1605/* */
1606/******************************************************************************/
1607/******************** Bits definition for DMAMUX_CxCR register **************/
1608#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
1609#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */
1610#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */
1611#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
1612#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
1613#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
1614#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
1615#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
1616#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
1617#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
1618#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
1619#define DMAMUX_CxCR_SOIE_Pos (8U)
1620#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
1621#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */
1622#define DMAMUX_CxCR_EGE_Pos (9U)
1623#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */
1624#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */
1625#define DMAMUX_CxCR_SE_Pos (16U)
1626#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */
1627#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */
1628#define DMAMUX_CxCR_SPOL_Pos (17U)
1629#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
1630#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */
1631#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */
1632#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */
1633#define DMAMUX_CxCR_NBREQ_Pos (19U)
1634#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
1635#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */
1636#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
1637#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
1638#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
1639#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
1640#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
1641#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
1642#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
1643#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */
1644#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
1645#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
1646#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
1647#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
1648#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
1649
1650/******************* Bits definition for DMAMUX_CSR register **************/
1651#define DMAMUX_CSR_SOF0_Pos (0U)
1652#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */
1653#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */
1654#define DMAMUX_CSR_SOF1_Pos (1U)
1655#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */
1656#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */
1657#define DMAMUX_CSR_SOF2_Pos (2U)
1658#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */
1659#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */
1660#define DMAMUX_CSR_SOF3_Pos (3U)
1661#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */
1662#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Synchronization Overrun Flag 3 */
1663#define DMAMUX_CSR_SOF4_Pos (4U)
1664#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */
1665#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Synchronization Overrun Flag 4 */
1666#define DMAMUX_CSR_SOF5_Pos (5U)
1667#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */
1668#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Synchronization Overrun Flag 5 */
1669#define DMAMUX_CSR_SOF6_Pos (6U)
1670#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */
1671#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Synchronization Overrun Flag 6 */
1672
1673/******************** Bits definition for DMAMUX_CFR register **************/
1674#define DMAMUX_CFR_CSOF0_Pos (0U)
1675#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
1676#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */
1677#define DMAMUX_CFR_CSOF1_Pos (1U)
1678#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
1679#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */
1680#define DMAMUX_CFR_CSOF2_Pos (2U)
1681#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
1682#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */
1683#define DMAMUX_CFR_CSOF3_Pos (3U)
1684#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
1685#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Clear Overrun Flag 3 */
1686#define DMAMUX_CFR_CSOF4_Pos (4U)
1687#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
1688#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Clear Overrun Flag 4 */
1689#define DMAMUX_CFR_CSOF5_Pos (5U)
1690#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
1691#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Clear Overrun Flag 5 */
1692#define DMAMUX_CFR_CSOF6_Pos (6U)
1693#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
1694#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Clear Overrun Flag 6 */
1695
1696/******************** Bits definition for DMAMUX_RGxCR register ************/
1697#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
1698#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
1699#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */
1700#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
1701#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
1702#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
1703#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
1704#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
1705#define DMAMUX_RGxCR_OIE_Pos (8U)
1706#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
1707#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */
1708#define DMAMUX_RGxCR_GE_Pos (16U)
1709#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */
1710#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */
1711#define DMAMUX_RGxCR_GPOL_Pos (17U)
1712#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
1713#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */
1714#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
1715#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
1716#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
1717#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
1718#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */
1719#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
1720#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */
1721#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */
1722#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */
1723#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */
1724
1725/******************** Bits definition for DMAMUX_RGSR register **************/
1726#define DMAMUX_RGSR_OF0_Pos (0U)
1727#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */
1728#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */
1729#define DMAMUX_RGSR_OF1_Pos (1U)
1730#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */
1731#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */
1732#define DMAMUX_RGSR_OF2_Pos (2U)
1733#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */
1734#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */
1735#define DMAMUX_RGSR_OF3_Pos (3U)
1736#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */
1737#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */
1738
1739/******************** Bits definition for DMAMUX_RGCFR register **************/
1740#define DMAMUX_RGCFR_COF0_Pos (0U)
1741#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
1742#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */
1743#define DMAMUX_RGCFR_COF1_Pos (1U)
1744#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
1745#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */
1746#define DMAMUX_RGCFR_COF2_Pos (2U)
1747#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
1748#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */
1749#define DMAMUX_RGCFR_COF3_Pos (3U)
1750#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
1751#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */
1752
1753/******************************************************************************/
1754/* */
1755/* External Interrupt/Event Controller */
1756/* */
1757/******************************************************************************/
1758/****************** Bit definition for EXTI_RTSR1 register ******************/
1759#define EXTI_RTSR1_RT0_Pos (0U)
1760#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
1761#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */
1762#define EXTI_RTSR1_RT1_Pos (1U)
1763#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
1764#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */
1765#define EXTI_RTSR1_RT2_Pos (2U)
1766#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
1767#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */
1768#define EXTI_RTSR1_RT3_Pos (3U)
1769#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
1770#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */
1771#define EXTI_RTSR1_RT4_Pos (4U)
1772#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
1773#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */
1774#define EXTI_RTSR1_RT5_Pos (5U)
1775#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
1776#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */
1777#define EXTI_RTSR1_RT6_Pos (6U)
1778#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
1779#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */
1780#define EXTI_RTSR1_RT7_Pos (7U)
1781#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
1782#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */
1783#define EXTI_RTSR1_RT8_Pos (8U)
1784#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
1785#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */
1786#define EXTI_RTSR1_RT9_Pos (9U)
1787#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
1788#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */
1789#define EXTI_RTSR1_RT10_Pos (10U)
1790#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
1791#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */
1792#define EXTI_RTSR1_RT11_Pos (11U)
1793#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
1794#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */
1795#define EXTI_RTSR1_RT12_Pos (12U)
1796#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
1797#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */
1798#define EXTI_RTSR1_RT13_Pos (13U)
1799#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
1800#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */
1801#define EXTI_RTSR1_RT14_Pos (14U)
1802#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
1803#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */
1804#define EXTI_RTSR1_RT15_Pos (15U)
1805#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
1806#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */
1807
1808/****************** Bit definition for EXTI_FTSR1 register ******************/
1809#define EXTI_FTSR1_FT0_Pos (0U)
1810#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
1811#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */
1812#define EXTI_FTSR1_FT1_Pos (1U)
1813#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
1814#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */
1815#define EXTI_FTSR1_FT2_Pos (2U)
1816#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
1817#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */
1818#define EXTI_FTSR1_FT3_Pos (3U)
1819#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
1820#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */
1821#define EXTI_FTSR1_FT4_Pos (4U)
1822#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
1823#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */
1824#define EXTI_FTSR1_FT5_Pos (5U)
1825#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
1826#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */
1827#define EXTI_FTSR1_FT6_Pos (6U)
1828#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
1829#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */
1830#define EXTI_FTSR1_FT7_Pos (7U)
1831#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
1832#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */
1833#define EXTI_FTSR1_FT8_Pos (8U)
1834#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
1835#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */
1836#define EXTI_FTSR1_FT9_Pos (9U)
1837#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
1838#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */
1839#define EXTI_FTSR1_FT10_Pos (10U)
1840#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
1841#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */
1842#define EXTI_FTSR1_FT11_Pos (11U)
1843#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
1844#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */
1845#define EXTI_FTSR1_FT12_Pos (12U)
1846#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
1847#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */
1848#define EXTI_FTSR1_FT13_Pos (13U)
1849#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
1850#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */
1851#define EXTI_FTSR1_FT14_Pos (14U)
1852#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
1853#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */
1854#define EXTI_FTSR1_FT15_Pos (15U)
1855#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
1856#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */
1857
1858/****************** Bit definition for EXTI_SWIER1 register *****************/
1859#define EXTI_SWIER1_SWI0_Pos (0U)
1860#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
1861#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
1862#define EXTI_SWIER1_SWI1_Pos (1U)
1863#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
1864#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
1865#define EXTI_SWIER1_SWI2_Pos (2U)
1866#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
1867#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
1868#define EXTI_SWIER1_SWI3_Pos (3U)
1869#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
1870#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
1871#define EXTI_SWIER1_SWI4_Pos (4U)
1872#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
1873#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
1874#define EXTI_SWIER1_SWI5_Pos (5U)
1875#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
1876#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
1877#define EXTI_SWIER1_SWI6_Pos (6U)
1878#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
1879#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
1880#define EXTI_SWIER1_SWI7_Pos (7U)
1881#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
1882#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
1883#define EXTI_SWIER1_SWI8_Pos (8U)
1884#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
1885#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
1886#define EXTI_SWIER1_SWI9_Pos (9U)
1887#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
1888#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
1889#define EXTI_SWIER1_SWI10_Pos (10U)
1890#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
1891#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
1892#define EXTI_SWIER1_SWI11_Pos (11U)
1893#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
1894#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
1895#define EXTI_SWIER1_SWI12_Pos (12U)
1896#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
1897#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
1898#define EXTI_SWIER1_SWI13_Pos (13U)
1899#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
1900#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
1901#define EXTI_SWIER1_SWI14_Pos (14U)
1902#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
1903#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
1904#define EXTI_SWIER1_SWI15_Pos (15U)
1905#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
1906#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
1907
1908/******************* Bit definition for EXTI_RPR1 register ******************/
1909#define EXTI_RPR1_RPIF0_Pos (0U)
1910#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */
1911#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */
1912#define EXTI_RPR1_RPIF1_Pos (1U)
1913#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */
1914#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */
1915#define EXTI_RPR1_RPIF2_Pos (2U)
1916#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */
1917#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */
1918#define EXTI_RPR1_RPIF3_Pos (3U)
1919#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */
1920#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */
1921#define EXTI_RPR1_RPIF4_Pos (4U)
1922#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */
1923#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */
1924#define EXTI_RPR1_RPIF5_Pos (5U)
1925#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */
1926#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */
1927#define EXTI_RPR1_RPIF6_Pos (6U)
1928#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */
1929#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */
1930#define EXTI_RPR1_RPIF7_Pos (7U)
1931#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */
1932#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */
1933#define EXTI_RPR1_RPIF8_Pos (8U)
1934#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */
1935#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */
1936#define EXTI_RPR1_RPIF9_Pos (9U)
1937#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */
1938#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */
1939#define EXTI_RPR1_RPIF10_Pos (10U)
1940#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */
1941#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */
1942#define EXTI_RPR1_RPIF11_Pos (11U)
1943#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */
1944#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */
1945#define EXTI_RPR1_RPIF12_Pos (12U)
1946#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */
1947#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */
1948#define EXTI_RPR1_RPIF13_Pos (13U)
1949#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */
1950#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */
1951#define EXTI_RPR1_RPIF14_Pos (14U)
1952#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */
1953#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */
1954#define EXTI_RPR1_RPIF15_Pos (15U)
1955#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */
1956#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */
1957
1958/******************* Bit definition for EXTI_FPR1 register ******************/
1959#define EXTI_FPR1_FPIF0_Pos (0U)
1960#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */
1961#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */
1962#define EXTI_FPR1_FPIF1_Pos (1U)
1963#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */
1964#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */
1965#define EXTI_FPR1_FPIF2_Pos (2U)
1966#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */
1967#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */
1968#define EXTI_FPR1_FPIF3_Pos (3U)
1969#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */
1970#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */
1971#define EXTI_FPR1_FPIF4_Pos (4U)
1972#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */
1973#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */
1974#define EXTI_FPR1_FPIF5_Pos (5U)
1975#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */
1976#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */
1977#define EXTI_FPR1_FPIF6_Pos (6U)
1978#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */
1979#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */
1980#define EXTI_FPR1_FPIF7_Pos (7U)
1981#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */
1982#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */
1983#define EXTI_FPR1_FPIF8_Pos (8U)
1984#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */
1985#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */
1986#define EXTI_FPR1_FPIF9_Pos (9U)
1987#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */
1988#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */
1989#define EXTI_FPR1_FPIF10_Pos (10U)
1990#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */
1991#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */
1992#define EXTI_FPR1_FPIF11_Pos (11U)
1993#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */
1994#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */
1995#define EXTI_FPR1_FPIF12_Pos (12U)
1996#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */
1997#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */
1998#define EXTI_FPR1_FPIF13_Pos (13U)
1999#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */
2000#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */
2001#define EXTI_FPR1_FPIF14_Pos (14U)
2002#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */
2003#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */
2004#define EXTI_FPR1_FPIF15_Pos (15U)
2005#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */
2006#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */
2007
2008/***************** Bit definition for EXTI_EXTICR1 register **************/
2009#define EXTI_EXTICR1_EXTI0_Pos (0U)
2010#define EXTI_EXTICR1_EXTI0_Msk (0x7UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */
2011#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
2012#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */
2013#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */
2014#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */
2015#define EXTI_EXTICR1_EXTI1_Pos (8U)
2016#define EXTI_EXTICR1_EXTI1_Msk (0x7UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000700 */
2017#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
2018#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */
2019#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */
2020#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */
2021#define EXTI_EXTICR1_EXTI2_Pos (16U)
2022#define EXTI_EXTICR1_EXTI2_Msk (0x7UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00070000 */
2023#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
2024#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */
2025#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */
2026#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */
2027#define EXTI_EXTICR1_EXTI3_Pos (24U)
2028#define EXTI_EXTICR1_EXTI3_Msk (0x7UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x07000000 */
2029#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
2030#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */
2031#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */
2032#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */
2033
2034/***************** Bit definition for EXTI_EXTICR2 register **************/
2035#define EXTI_EXTICR2_EXTI4_Pos (0U)
2036#define EXTI_EXTICR2_EXTI4_Msk (0x7UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */
2037#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
2038#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */
2039#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */
2040#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */
2041#define EXTI_EXTICR2_EXTI5_Pos (8U)
2042#define EXTI_EXTICR2_EXTI5_Msk (0x7UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000700 */
2043#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
2044#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */
2045#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */
2046#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */
2047#define EXTI_EXTICR2_EXTI6_Pos (16U)
2048#define EXTI_EXTICR2_EXTI6_Msk (0x7UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00070000 */
2049#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
2050#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */
2051#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */
2052#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */
2053#define EXTI_EXTICR2_EXTI7_Pos (24U)
2054#define EXTI_EXTICR2_EXTI7_Msk (0x7UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x07000000 */
2055#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
2056#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */
2057#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */
2058#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */
2059
2060/***************** Bit definition for EXTI_EXTICR3 register **************/
2061#define EXTI_EXTICR3_EXTI8_Pos (0U)
2062#define EXTI_EXTICR3_EXTI8_Msk (0x7UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */
2063#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
2064#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */
2065#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */
2066#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */
2067#define EXTI_EXTICR3_EXTI9_Pos (8U)
2068#define EXTI_EXTICR3_EXTI9_Msk (0x7UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000700 */
2069#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
2070#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */
2071#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */
2072#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */
2073#define EXTI_EXTICR3_EXTI10_Pos (16U)
2074#define EXTI_EXTICR3_EXTI10_Msk (0x7UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00070000 */
2075#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
2076#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */
2077#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */
2078#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */
2079#define EXTI_EXTICR3_EXTI11_Pos (24U)
2080#define EXTI_EXTICR3_EXTI11_Msk (0x7UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x07000000 */
2081#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
2082#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */
2083#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */
2084#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */
2085
2086/***************** Bit definition for EXTI_EXTICR4 register **************/
2087#define EXTI_EXTICR4_EXTI12_Pos (0U)
2088#define EXTI_EXTICR4_EXTI12_Msk (0x7UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
2089#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
2090#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */
2091#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */
2092#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */
2093#define EXTI_EXTICR4_EXTI13_Pos (8U)
2094#define EXTI_EXTICR4_EXTI13_Msk (0x7UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000700 */
2095#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
2096#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */
2097#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */
2098#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */
2099#define EXTI_EXTICR4_EXTI14_Pos (16U)
2100#define EXTI_EXTICR4_EXTI14_Msk (0x7UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00070000 */
2101#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
2102#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */
2103#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */
2104#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */
2105#define EXTI_EXTICR4_EXTI15_Pos (24U)
2106#define EXTI_EXTICR4_EXTI15_Msk (0x7UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x07000000 */
2107#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
2108#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */
2109#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */
2110#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */
2111
2112/******************* Bit definition for EXTI_IMR1 register ******************/
2113#define EXTI_IMR1_IM0_Pos (0U)
2114#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
2115#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
2116#define EXTI_IMR1_IM1_Pos (1U)
2117#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
2118#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
2119#define EXTI_IMR1_IM2_Pos (2U)
2120#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
2121#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
2122#define EXTI_IMR1_IM3_Pos (3U)
2123#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
2124#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
2125#define EXTI_IMR1_IM4_Pos (4U)
2126#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
2127#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
2128#define EXTI_IMR1_IM5_Pos (5U)
2129#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
2130#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
2131#define EXTI_IMR1_IM6_Pos (6U)
2132#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
2133#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
2134#define EXTI_IMR1_IM7_Pos (7U)
2135#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
2136#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
2137#define EXTI_IMR1_IM8_Pos (8U)
2138#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
2139#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
2140#define EXTI_IMR1_IM9_Pos (9U)
2141#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
2142#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
2143#define EXTI_IMR1_IM10_Pos (10U)
2144#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
2145#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
2146#define EXTI_IMR1_IM11_Pos (11U)
2147#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
2148#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
2149#define EXTI_IMR1_IM12_Pos (12U)
2150#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
2151#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
2152#define EXTI_IMR1_IM13_Pos (13U)
2153#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
2154#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
2155#define EXTI_IMR1_IM14_Pos (14U)
2156#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
2157#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
2158#define EXTI_IMR1_IM15_Pos (15U)
2159#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
2160#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
2161#define EXTI_IMR1_IM19_Pos (19U)
2162#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
2163#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
2164#define EXTI_IMR1_IM20_Pos (20U)
2165#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
2166#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
2167#define EXTI_IMR1_IM21_Pos (21U)
2168#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
2169#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
2170#define EXTI_IMR1_IM22_Pos (22U)
2171#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
2172#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
2173#define EXTI_IMR1_IM23_Pos (23U)
2174#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
2175#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
2176#define EXTI_IMR1_IM24_Pos (24U)
2177#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
2178#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
2179#define EXTI_IMR1_IM25_Pos (25U)
2180#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
2181#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
2182#define EXTI_IMR1_IM26_Pos (26U)
2183#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
2184#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
2185#define EXTI_IMR1_IM31_Pos (31U)
2186#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
2187#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
2188#define EXTI_IMR1_IM_Pos (0U)
2189#define EXTI_IMR1_IM_Msk (0x86A8FFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x86A8FFFFU */
2190#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
2191
2192
2193/******************* Bit definition for EXTI_EMR1 register ******************/
2194#define EXTI_EMR1_EM0_Pos (0U)
2195#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
2196#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
2197#define EXTI_EMR1_EM1_Pos (1U)
2198#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
2199#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
2200#define EXTI_EMR1_EM2_Pos (2U)
2201#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
2202#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
2203#define EXTI_EMR1_EM3_Pos (3U)
2204#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
2205#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
2206#define EXTI_EMR1_EM4_Pos (4U)
2207#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
2208#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
2209#define EXTI_EMR1_EM5_Pos (5U)
2210#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
2211#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
2212#define EXTI_EMR1_EM6_Pos (6U)
2213#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
2214#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
2215#define EXTI_EMR1_EM7_Pos (7U)
2216#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
2217#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
2218#define EXTI_EMR1_EM8_Pos (8U)
2219#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
2220#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
2221#define EXTI_EMR1_EM9_Pos (9U)
2222#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
2223#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
2224#define EXTI_EMR1_EM10_Pos (10U)
2225#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
2226#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
2227#define EXTI_EMR1_EM11_Pos (11U)
2228#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
2229#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
2230#define EXTI_EMR1_EM12_Pos (12U)
2231#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
2232#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
2233#define EXTI_EMR1_EM13_Pos (13U)
2234#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
2235#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
2236#define EXTI_EMR1_EM14_Pos (14U)
2237#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
2238#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
2239#define EXTI_EMR1_EM15_Pos (15U)
2240#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
2241#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
2242#define EXTI_EMR1_EM17_Pos (17U)
2243#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
2244#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
2245#define EXTI_EMR1_EM18_Pos (18U)
2246#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
2247#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
2248#define EXTI_EMR1_EM19_Pos (19U)
2249#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
2250#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
2251#define EXTI_EMR1_EM21_Pos (21U)
2252#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
2253#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
2254#define EXTI_EMR1_EM23_Pos (23U)
2255#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
2256#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
2257#define EXTI_EMR1_EM25_Pos (25U)
2258#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
2259#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
2260#define EXTI_EMR1_EM26_Pos (26U)
2261#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
2262#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
2263#define EXTI_EMR1_EM31_Pos (31U)
2264#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
2265#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
2266
2267
2268
2269/******************************************************************************/
2270/* */
2271/* FLASH */
2272/* */
2273/******************************************************************************/
2274/* Note: No specific macro feature on this device */
2275
2276/******************* Bits definition for FLASH_ACR register *****************/
2277#define FLASH_ACR_LATENCY_Pos (0U)
2278#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
2279#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
2280#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
2281#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
2282#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
2283#define FLASH_ACR_PRFTEN_Pos (8U)
2284#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
2285#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
2286#define FLASH_ACR_ICEN_Pos (9U)
2287#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
2288#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
2289#define FLASH_ACR_ICRST_Pos (11U)
2290#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
2291#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
2292#define FLASH_ACR_PROGEMPTY_Pos (16U)
2293#define FLASH_ACR_PROGEMPTY_Msk (0x1UL << FLASH_ACR_PROGEMPTY_Pos) /*!< 0x00010000 */
2294#define FLASH_ACR_PROGEMPTY FLASH_ACR_PROGEMPTY_Msk
2295
2296/******************* Bits definition for FLASH_SR register ******************/
2297#define FLASH_SR_EOP_Pos (0U)
2298#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
2299#define FLASH_SR_EOP FLASH_SR_EOP_Msk
2300#define FLASH_SR_OPERR_Pos (1U)
2301#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
2302#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
2303#define FLASH_SR_PROGERR_Pos (3U)
2304#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
2305#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
2306#define FLASH_SR_WRPERR_Pos (4U)
2307#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
2308#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
2309#define FLASH_SR_PGAERR_Pos (5U)
2310#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
2311#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
2312#define FLASH_SR_SIZERR_Pos (6U)
2313#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
2314#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
2315#define FLASH_SR_PGSERR_Pos (7U)
2316#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
2317#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
2318#define FLASH_SR_MISERR_Pos (8U)
2319#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
2320#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
2321#define FLASH_SR_FASTERR_Pos (9U)
2322#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
2323#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
2324#define FLASH_SR_OPTVERR_Pos (15U)
2325#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
2326#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
2327#define FLASH_SR_BSY1_Pos (16U)
2328#define FLASH_SR_BSY1_Msk (0x1UL << FLASH_SR_BSY1_Pos) /*!< 0x00010000 */
2329#define FLASH_SR_BSY1 FLASH_SR_BSY1_Msk
2330#define FLASH_SR_CFGBSY_Pos (18U)
2331#define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */
2332#define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk
2333
2334/******************* Bits definition for FLASH_CR register ******************/
2335#define FLASH_CR_PG_Pos (0U)
2336#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
2337#define FLASH_CR_PG FLASH_CR_PG_Msk
2338#define FLASH_CR_PER_Pos (1U)
2339#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */
2340#define FLASH_CR_PER FLASH_CR_PER_Msk
2341#define FLASH_CR_MER1_Pos (2U)
2342#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
2343#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
2344#define FLASH_CR_PNB_Pos (3U)
2345#define FLASH_CR_PNB_Msk (0x3FUL << FLASH_CR_PNB_Pos) /*!< 0x000001F8 */
2346#define FLASH_CR_PNB FLASH_CR_PNB_Msk
2347#define FLASH_CR_STRT_Pos (16U)
2348#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
2349#define FLASH_CR_STRT FLASH_CR_STRT_Msk
2350#define FLASH_CR_OPTSTRT_Pos (17U)
2351#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
2352#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
2353#define FLASH_CR_FSTPG_Pos (18U)
2354#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
2355#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
2356#define FLASH_CR_EOPIE_Pos (24U)
2357#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
2358#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
2359#define FLASH_CR_ERRIE_Pos (25U)
2360#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
2361#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
2362#define FLASH_CR_OBL_LAUNCH_Pos (27U)
2363#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
2364#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
2365#define FLASH_CR_OPTLOCK_Pos (30U)
2366#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
2367#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
2368#define FLASH_CR_LOCK_Pos (31U)
2369#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
2370#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
2371
2372/******************* Bits definition for FLASH_ECCR register ****************/
2373#define FLASH_ECCR_ADDR_ECC_Pos (0U)
2374#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x00003FFF */
2375#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
2376#define FLASH_ECCR_SYSF_ECC_Pos (20U)
2377#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
2378#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
2379#define FLASH_ECCR_ECCCIE_Pos (24U)
2380#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */
2381#define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk
2382#define FLASH_ECCR_ECCC_Pos (30U)
2383#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
2384#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
2385#define FLASH_ECCR_ECCD_Pos (31U)
2386#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
2387#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
2388
2389/******************* Bits definition for FLASH_OPTR register ****************/
2390#define FLASH_OPTR_RDP_Pos (0U)
2391#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
2392#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
2393#define FLASH_OPTR_nRST_STOP_Pos (13U)
2394#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */
2395#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
2396#define FLASH_OPTR_nRST_STDBY_Pos (14U)
2397#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */
2398#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
2399#define FLASH_OPTR_IWDG_SW_Pos (16U)
2400#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
2401#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
2402#define FLASH_OPTR_IWDG_STOP_Pos (17U)
2403#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
2404#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
2405#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
2406#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
2407#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
2408#define FLASH_OPTR_WWDG_SW_Pos (19U)
2409#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
2410#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
2411#define FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U)
2412#define FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */
2413#define FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk
2414#define FLASH_OPTR_nBOOT_SEL_Pos (24U)
2415#define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */
2416#define FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk
2417#define FLASH_OPTR_nBOOT1_Pos (25U)
2418#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */
2419#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
2420#define FLASH_OPTR_nBOOT0_Pos (26U)
2421#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */
2422#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
2423
2424
2425/****************** Bits definition for FLASH_WRP1AR register ***************/
2426#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
2427#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000003F */
2428#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
2429#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
2430#define FLASH_WRP1AR_WRP1A_END_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x003F0000 */
2431#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
2432
2433/****************** Bits definition for FLASH_WRP1BR register ***************/
2434#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
2435#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000003F */
2436#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
2437#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
2438#define FLASH_WRP1BR_WRP1B_END_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x003F0000 */
2439#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
2440
2441
2442
2443/******************************************************************************/
2444/* */
2445/* General Purpose I/O */
2446/* */
2447/******************************************************************************/
2448/****************** Bits definition for GPIO_MODER register *****************/
2449#define GPIO_MODER_MODE0_Pos (0U)
2450#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
2451#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
2452#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
2453#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
2454#define GPIO_MODER_MODE1_Pos (2U)
2455#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
2456#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
2457#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
2458#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
2459#define GPIO_MODER_MODE2_Pos (4U)
2460#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
2461#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
2462#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
2463#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
2464#define GPIO_MODER_MODE3_Pos (6U)
2465#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
2466#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
2467#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
2468#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
2469#define GPIO_MODER_MODE4_Pos (8U)
2470#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
2471#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
2472#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
2473#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
2474#define GPIO_MODER_MODE5_Pos (10U)
2475#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
2476#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
2477#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
2478#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
2479#define GPIO_MODER_MODE6_Pos (12U)
2480#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
2481#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
2482#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
2483#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
2484#define GPIO_MODER_MODE7_Pos (14U)
2485#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
2486#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
2487#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
2488#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
2489#define GPIO_MODER_MODE8_Pos (16U)
2490#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
2491#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
2492#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
2493#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
2494#define GPIO_MODER_MODE9_Pos (18U)
2495#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
2496#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
2497#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
2498#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
2499#define GPIO_MODER_MODE10_Pos (20U)
2500#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
2501#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
2502#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
2503#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
2504#define GPIO_MODER_MODE11_Pos (22U)
2505#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
2506#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
2507#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
2508#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
2509#define GPIO_MODER_MODE12_Pos (24U)
2510#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
2511#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
2512#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
2513#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
2514#define GPIO_MODER_MODE13_Pos (26U)
2515#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
2516#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
2517#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
2518#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
2519#define GPIO_MODER_MODE14_Pos (28U)
2520#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
2521#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
2522#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
2523#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
2524#define GPIO_MODER_MODE15_Pos (30U)
2525#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
2526#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
2527#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
2528#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
2529
2530/****************** Bits definition for GPIO_OTYPER register ****************/
2531#define GPIO_OTYPER_OT0_Pos (0U)
2532#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
2533#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
2534#define GPIO_OTYPER_OT1_Pos (1U)
2535#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
2536#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
2537#define GPIO_OTYPER_OT2_Pos (2U)
2538#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
2539#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
2540#define GPIO_OTYPER_OT3_Pos (3U)
2541#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
2542#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
2543#define GPIO_OTYPER_OT4_Pos (4U)
2544#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
2545#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
2546#define GPIO_OTYPER_OT5_Pos (5U)
2547#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
2548#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
2549#define GPIO_OTYPER_OT6_Pos (6U)
2550#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
2551#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
2552#define GPIO_OTYPER_OT7_Pos (7U)
2553#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
2554#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
2555#define GPIO_OTYPER_OT8_Pos (8U)
2556#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
2557#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
2558#define GPIO_OTYPER_OT9_Pos (9U)
2559#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
2560#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
2561#define GPIO_OTYPER_OT10_Pos (10U)
2562#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
2563#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
2564#define GPIO_OTYPER_OT11_Pos (11U)
2565#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
2566#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
2567#define GPIO_OTYPER_OT12_Pos (12U)
2568#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
2569#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
2570#define GPIO_OTYPER_OT13_Pos (13U)
2571#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
2572#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
2573#define GPIO_OTYPER_OT14_Pos (14U)
2574#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
2575#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
2576#define GPIO_OTYPER_OT15_Pos (15U)
2577#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
2578#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
2579
2580/****************** Bits definition for GPIO_OSPEEDR register ***************/
2581#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
2582#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
2583#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
2584#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
2585#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
2586#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
2587#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
2588#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
2589#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
2590#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
2591#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
2592#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
2593#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
2594#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
2595#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
2596#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
2597#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
2598#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
2599#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
2600#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
2601#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
2602#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
2603#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
2604#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
2605#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
2606#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
2607#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
2608#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
2609#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
2610#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
2611#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
2612#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
2613#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
2614#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
2615#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
2616#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
2617#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
2618#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
2619#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
2620#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
2621#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
2622#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
2623#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
2624#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
2625#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
2626#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
2627#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
2628#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
2629#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
2630#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
2631#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
2632#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
2633#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
2634#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
2635#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
2636#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
2637#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
2638#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
2639#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
2640#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
2641#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
2642#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
2643#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
2644#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
2645#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
2646#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
2647#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
2648#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
2649#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
2650#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
2651#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
2652#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
2653#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
2654#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
2655#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
2656#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
2657#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
2658#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
2659#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
2660#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
2661
2662/****************** Bits definition for GPIO_PUPDR register *****************/
2663#define GPIO_PUPDR_PUPD0_Pos (0U)
2664#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
2665#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
2666#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
2667#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
2668#define GPIO_PUPDR_PUPD1_Pos (2U)
2669#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
2670#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
2671#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
2672#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
2673#define GPIO_PUPDR_PUPD2_Pos (4U)
2674#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
2675#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
2676#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
2677#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
2678#define GPIO_PUPDR_PUPD3_Pos (6U)
2679#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
2680#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
2681#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
2682#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
2683#define GPIO_PUPDR_PUPD4_Pos (8U)
2684#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
2685#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
2686#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
2687#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
2688#define GPIO_PUPDR_PUPD5_Pos (10U)
2689#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
2690#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
2691#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
2692#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
2693#define GPIO_PUPDR_PUPD6_Pos (12U)
2694#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
2695#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
2696#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
2697#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
2698#define GPIO_PUPDR_PUPD7_Pos (14U)
2699#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
2700#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
2701#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
2702#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
2703#define GPIO_PUPDR_PUPD8_Pos (16U)
2704#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
2705#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
2706#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
2707#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
2708#define GPIO_PUPDR_PUPD9_Pos (18U)
2709#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
2710#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
2711#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
2712#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
2713#define GPIO_PUPDR_PUPD10_Pos (20U)
2714#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
2715#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
2716#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
2717#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
2718#define GPIO_PUPDR_PUPD11_Pos (22U)
2719#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
2720#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
2721#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
2722#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
2723#define GPIO_PUPDR_PUPD12_Pos (24U)
2724#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
2725#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
2726#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
2727#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
2728#define GPIO_PUPDR_PUPD13_Pos (26U)
2729#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
2730#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
2731#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
2732#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
2733#define GPIO_PUPDR_PUPD14_Pos (28U)
2734#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
2735#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
2736#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
2737#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
2738#define GPIO_PUPDR_PUPD15_Pos (30U)
2739#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
2740#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
2741#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
2742#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
2743
2744/****************** Bits definition for GPIO_IDR register *******************/
2745#define GPIO_IDR_ID0_Pos (0U)
2746#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
2747#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
2748#define GPIO_IDR_ID1_Pos (1U)
2749#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
2750#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
2751#define GPIO_IDR_ID2_Pos (2U)
2752#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
2753#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
2754#define GPIO_IDR_ID3_Pos (3U)
2755#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
2756#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
2757#define GPIO_IDR_ID4_Pos (4U)
2758#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
2759#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
2760#define GPIO_IDR_ID5_Pos (5U)
2761#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
2762#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
2763#define GPIO_IDR_ID6_Pos (6U)
2764#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
2765#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
2766#define GPIO_IDR_ID7_Pos (7U)
2767#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
2768#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
2769#define GPIO_IDR_ID8_Pos (8U)
2770#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
2771#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
2772#define GPIO_IDR_ID9_Pos (9U)
2773#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
2774#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
2775#define GPIO_IDR_ID10_Pos (10U)
2776#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
2777#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
2778#define GPIO_IDR_ID11_Pos (11U)
2779#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
2780#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
2781#define GPIO_IDR_ID12_Pos (12U)
2782#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
2783#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
2784#define GPIO_IDR_ID13_Pos (13U)
2785#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
2786#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
2787#define GPIO_IDR_ID14_Pos (14U)
2788#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
2789#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
2790#define GPIO_IDR_ID15_Pos (15U)
2791#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
2792#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
2793
2794/****************** Bits definition for GPIO_ODR register *******************/
2795#define GPIO_ODR_OD0_Pos (0U)
2796#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
2797#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
2798#define GPIO_ODR_OD1_Pos (1U)
2799#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
2800#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
2801#define GPIO_ODR_OD2_Pos (2U)
2802#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
2803#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
2804#define GPIO_ODR_OD3_Pos (3U)
2805#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
2806#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
2807#define GPIO_ODR_OD4_Pos (4U)
2808#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
2809#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
2810#define GPIO_ODR_OD5_Pos (5U)
2811#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
2812#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
2813#define GPIO_ODR_OD6_Pos (6U)
2814#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
2815#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
2816#define GPIO_ODR_OD7_Pos (7U)
2817#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
2818#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
2819#define GPIO_ODR_OD8_Pos (8U)
2820#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
2821#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
2822#define GPIO_ODR_OD9_Pos (9U)
2823#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
2824#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
2825#define GPIO_ODR_OD10_Pos (10U)
2826#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
2827#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
2828#define GPIO_ODR_OD11_Pos (11U)
2829#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
2830#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
2831#define GPIO_ODR_OD12_Pos (12U)
2832#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
2833#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
2834#define GPIO_ODR_OD13_Pos (13U)
2835#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
2836#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
2837#define GPIO_ODR_OD14_Pos (14U)
2838#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
2839#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
2840#define GPIO_ODR_OD15_Pos (15U)
2841#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
2842#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
2843
2844/****************** Bits definition for GPIO_BSRR register ******************/
2845#define GPIO_BSRR_BS0_Pos (0U)
2846#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
2847#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
2848#define GPIO_BSRR_BS1_Pos (1U)
2849#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
2850#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
2851#define GPIO_BSRR_BS2_Pos (2U)
2852#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
2853#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
2854#define GPIO_BSRR_BS3_Pos (3U)
2855#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
2856#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
2857#define GPIO_BSRR_BS4_Pos (4U)
2858#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
2859#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
2860#define GPIO_BSRR_BS5_Pos (5U)
2861#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
2862#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
2863#define GPIO_BSRR_BS6_Pos (6U)
2864#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
2865#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
2866#define GPIO_BSRR_BS7_Pos (7U)
2867#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
2868#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
2869#define GPIO_BSRR_BS8_Pos (8U)
2870#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
2871#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
2872#define GPIO_BSRR_BS9_Pos (9U)
2873#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
2874#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
2875#define GPIO_BSRR_BS10_Pos (10U)
2876#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
2877#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
2878#define GPIO_BSRR_BS11_Pos (11U)
2879#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
2880#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
2881#define GPIO_BSRR_BS12_Pos (12U)
2882#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
2883#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
2884#define GPIO_BSRR_BS13_Pos (13U)
2885#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
2886#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
2887#define GPIO_BSRR_BS14_Pos (14U)
2888#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
2889#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
2890#define GPIO_BSRR_BS15_Pos (15U)
2891#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
2892#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
2893#define GPIO_BSRR_BR0_Pos (16U)
2894#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
2895#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
2896#define GPIO_BSRR_BR1_Pos (17U)
2897#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
2898#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
2899#define GPIO_BSRR_BR2_Pos (18U)
2900#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
2901#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
2902#define GPIO_BSRR_BR3_Pos (19U)
2903#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
2904#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
2905#define GPIO_BSRR_BR4_Pos (20U)
2906#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
2907#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
2908#define GPIO_BSRR_BR5_Pos (21U)
2909#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
2910#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
2911#define GPIO_BSRR_BR6_Pos (22U)
2912#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
2913#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
2914#define GPIO_BSRR_BR7_Pos (23U)
2915#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
2916#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
2917#define GPIO_BSRR_BR8_Pos (24U)
2918#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
2919#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
2920#define GPIO_BSRR_BR9_Pos (25U)
2921#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
2922#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
2923#define GPIO_BSRR_BR10_Pos (26U)
2924#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
2925#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
2926#define GPIO_BSRR_BR11_Pos (27U)
2927#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
2928#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
2929#define GPIO_BSRR_BR12_Pos (28U)
2930#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
2931#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
2932#define GPIO_BSRR_BR13_Pos (29U)
2933#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
2934#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
2935#define GPIO_BSRR_BR14_Pos (30U)
2936#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
2937#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
2938#define GPIO_BSRR_BR15_Pos (31U)
2939#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
2940#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
2941
2942/****************** Bit definition for GPIO_LCKR register *********************/
2943#define GPIO_LCKR_LCK0_Pos (0U)
2944#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
2945#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
2946#define GPIO_LCKR_LCK1_Pos (1U)
2947#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
2948#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
2949#define GPIO_LCKR_LCK2_Pos (2U)
2950#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
2951#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
2952#define GPIO_LCKR_LCK3_Pos (3U)
2953#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
2954#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
2955#define GPIO_LCKR_LCK4_Pos (4U)
2956#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
2957#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
2958#define GPIO_LCKR_LCK5_Pos (5U)
2959#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
2960#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
2961#define GPIO_LCKR_LCK6_Pos (6U)
2962#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
2963#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
2964#define GPIO_LCKR_LCK7_Pos (7U)
2965#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
2966#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
2967#define GPIO_LCKR_LCK8_Pos (8U)
2968#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
2969#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
2970#define GPIO_LCKR_LCK9_Pos (9U)
2971#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
2972#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
2973#define GPIO_LCKR_LCK10_Pos (10U)
2974#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
2975#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
2976#define GPIO_LCKR_LCK11_Pos (11U)
2977#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
2978#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
2979#define GPIO_LCKR_LCK12_Pos (12U)
2980#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
2981#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
2982#define GPIO_LCKR_LCK13_Pos (13U)
2983#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
2984#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
2985#define GPIO_LCKR_LCK14_Pos (14U)
2986#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
2987#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
2988#define GPIO_LCKR_LCK15_Pos (15U)
2989#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
2990#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
2991#define GPIO_LCKR_LCKK_Pos (16U)
2992#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
2993#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
2994
2995/****************** Bit definition for GPIO_AFRL register *********************/
2996#define GPIO_AFRL_AFSEL0_Pos (0U)
2997#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
2998#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
2999#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
3000#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
3001#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
3002#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
3003#define GPIO_AFRL_AFSEL1_Pos (4U)
3004#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
3005#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
3006#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
3007#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
3008#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
3009#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
3010#define GPIO_AFRL_AFSEL2_Pos (8U)
3011#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
3012#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
3013#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
3014#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
3015#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
3016#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
3017#define GPIO_AFRL_AFSEL3_Pos (12U)
3018#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
3019#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
3020#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
3021#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
3022#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
3023#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
3024#define GPIO_AFRL_AFSEL4_Pos (16U)
3025#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
3026#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
3027#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
3028#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
3029#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
3030#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
3031#define GPIO_AFRL_AFSEL5_Pos (20U)
3032#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
3033#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
3034#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
3035#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
3036#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
3037#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
3038#define GPIO_AFRL_AFSEL6_Pos (24U)
3039#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
3040#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
3041#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
3042#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
3043#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
3044#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
3045#define GPIO_AFRL_AFSEL7_Pos (28U)
3046#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
3047#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
3048#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
3049#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
3050#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
3051#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
3052
3053/****************** Bit definition for GPIO_AFRH register *********************/
3054#define GPIO_AFRH_AFSEL8_Pos (0U)
3055#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
3056#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
3057#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
3058#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
3059#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
3060#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
3061#define GPIO_AFRH_AFSEL9_Pos (4U)
3062#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
3063#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
3064#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
3065#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
3066#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
3067#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
3068#define GPIO_AFRH_AFSEL10_Pos (8U)
3069#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
3070#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
3071#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
3072#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
3073#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
3074#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
3075#define GPIO_AFRH_AFSEL11_Pos (12U)
3076#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
3077#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
3078#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
3079#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
3080#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
3081#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
3082#define GPIO_AFRH_AFSEL12_Pos (16U)
3083#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
3084#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
3085#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
3086#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
3087#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
3088#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
3089#define GPIO_AFRH_AFSEL13_Pos (20U)
3090#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
3091#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
3092#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
3093#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
3094#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
3095#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
3096#define GPIO_AFRH_AFSEL14_Pos (24U)
3097#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
3098#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
3099#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
3100#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
3101#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
3102#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
3103#define GPIO_AFRH_AFSEL15_Pos (28U)
3104#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
3105#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
3106#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
3107#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
3108#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
3109#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
3110
3111/****************** Bits definition for GPIO_BRR register ******************/
3112#define GPIO_BRR_BR0_Pos (0U)
3113#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
3114#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
3115#define GPIO_BRR_BR1_Pos (1U)
3116#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
3117#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
3118#define GPIO_BRR_BR2_Pos (2U)
3119#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
3120#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
3121#define GPIO_BRR_BR3_Pos (3U)
3122#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
3123#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
3124#define GPIO_BRR_BR4_Pos (4U)
3125#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
3126#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
3127#define GPIO_BRR_BR5_Pos (5U)
3128#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
3129#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
3130#define GPIO_BRR_BR6_Pos (6U)
3131#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
3132#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
3133#define GPIO_BRR_BR7_Pos (7U)
3134#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
3135#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
3136#define GPIO_BRR_BR8_Pos (8U)
3137#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
3138#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
3139#define GPIO_BRR_BR9_Pos (9U)
3140#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
3141#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
3142#define GPIO_BRR_BR10_Pos (10U)
3143#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
3144#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
3145#define GPIO_BRR_BR11_Pos (11U)
3146#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
3147#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
3148#define GPIO_BRR_BR12_Pos (12U)
3149#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
3150#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
3151#define GPIO_BRR_BR13_Pos (13U)
3152#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
3153#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
3154#define GPIO_BRR_BR14_Pos (14U)
3155#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
3156#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
3157#define GPIO_BRR_BR15_Pos (15U)
3158#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
3159#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
3160
3161
3162/******************************************************************************/
3163/* */
3164/* Inter-integrated Circuit Interface (I2C) */
3165/* */
3166/******************************************************************************/
3167/******************* Bit definition for I2C_CR1 register *******************/
3168#define I2C_CR1_PE_Pos (0U)
3169#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
3170#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
3171#define I2C_CR1_TXIE_Pos (1U)
3172#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
3173#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
3174#define I2C_CR1_RXIE_Pos (2U)
3175#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
3176#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
3177#define I2C_CR1_ADDRIE_Pos (3U)
3178#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
3179#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
3180#define I2C_CR1_NACKIE_Pos (4U)
3181#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
3182#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
3183#define I2C_CR1_STOPIE_Pos (5U)
3184#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
3185#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
3186#define I2C_CR1_TCIE_Pos (6U)
3187#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
3188#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
3189#define I2C_CR1_ERRIE_Pos (7U)
3190#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
3191#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
3192#define I2C_CR1_DNF_Pos (8U)
3193#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
3194#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
3195#define I2C_CR1_ANFOFF_Pos (12U)
3196#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
3197#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
3198#define I2C_CR1_SWRST_Pos (13U)
3199#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
3200#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
3201#define I2C_CR1_TXDMAEN_Pos (14U)
3202#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
3203#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
3204#define I2C_CR1_RXDMAEN_Pos (15U)
3205#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
3206#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
3207#define I2C_CR1_SBC_Pos (16U)
3208#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
3209#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
3210#define I2C_CR1_NOSTRETCH_Pos (17U)
3211#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
3212#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
3213#define I2C_CR1_WUPEN_Pos (18U)
3214#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
3215#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
3216#define I2C_CR1_GCEN_Pos (19U)
3217#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
3218#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
3219#define I2C_CR1_SMBHEN_Pos (20U)
3220#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
3221#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
3222#define I2C_CR1_SMBDEN_Pos (21U)
3223#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
3224#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
3225#define I2C_CR1_ALERTEN_Pos (22U)
3226#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
3227#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
3228#define I2C_CR1_PECEN_Pos (23U)
3229#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
3230#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
3231
3232/****************** Bit definition for I2C_CR2 register ********************/
3233#define I2C_CR2_SADD_Pos (0U)
3234#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
3235#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
3236#define I2C_CR2_RD_WRN_Pos (10U)
3237#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
3238#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
3239#define I2C_CR2_ADD10_Pos (11U)
3240#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
3241#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
3242#define I2C_CR2_HEAD10R_Pos (12U)
3243#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
3244#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
3245#define I2C_CR2_START_Pos (13U)
3246#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
3247#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
3248#define I2C_CR2_STOP_Pos (14U)
3249#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
3250#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
3251#define I2C_CR2_NACK_Pos (15U)
3252#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
3253#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
3254#define I2C_CR2_NBYTES_Pos (16U)
3255#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
3256#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
3257#define I2C_CR2_RELOAD_Pos (24U)
3258#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
3259#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
3260#define I2C_CR2_AUTOEND_Pos (25U)
3261#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
3262#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
3263#define I2C_CR2_PECBYTE_Pos (26U)
3264#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
3265#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
3266
3267/******************* Bit definition for I2C_OAR1 register ******************/
3268#define I2C_OAR1_OA1_Pos (0U)
3269#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
3270#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
3271#define I2C_OAR1_OA1MODE_Pos (10U)
3272#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
3273#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
3274#define I2C_OAR1_OA1EN_Pos (15U)
3275#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
3276#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
3277
3278/******************* Bit definition for I2C_OAR2 register ******************/
3279#define I2C_OAR2_OA2_Pos (1U)
3280#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
3281#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
3282#define I2C_OAR2_OA2MSK_Pos (8U)
3283#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
3284#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
3285#define I2C_OAR2_OA2NOMASK (0U) /*!< No mask */
3286#define I2C_OAR2_OA2MASK01_Pos (8U)
3287#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
3288#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
3289#define I2C_OAR2_OA2MASK02_Pos (9U)
3290#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
3291#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
3292#define I2C_OAR2_OA2MASK03_Pos (8U)
3293#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
3294#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
3295#define I2C_OAR2_OA2MASK04_Pos (10U)
3296#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
3297#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
3298#define I2C_OAR2_OA2MASK05_Pos (8U)
3299#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
3300#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
3301#define I2C_OAR2_OA2MASK06_Pos (9U)
3302#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
3303#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
3304#define I2C_OAR2_OA2MASK07_Pos (8U)
3305#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
3306#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
3307#define I2C_OAR2_OA2EN_Pos (15U)
3308#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
3309#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
3310
3311/******************* Bit definition for I2C_TIMINGR register *******************/
3312#define I2C_TIMINGR_SCLL_Pos (0U)
3313#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
3314#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
3315#define I2C_TIMINGR_SCLH_Pos (8U)
3316#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
3317#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
3318#define I2C_TIMINGR_SDADEL_Pos (16U)
3319#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
3320#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
3321#define I2C_TIMINGR_SCLDEL_Pos (20U)
3322#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
3323#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
3324#define I2C_TIMINGR_PRESC_Pos (28U)
3325#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
3326#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
3327
3328/******************* Bit definition for I2C_TIMEOUTR register *******************/
3329#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
3330#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
3331#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
3332#define I2C_TIMEOUTR_TIDLE_Pos (12U)
3333#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
3334#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
3335#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
3336#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
3337#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
3338#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
3339#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
3340#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
3341#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
3342#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
3343#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
3344
3345/****************** Bit definition for I2C_ISR register *********************/
3346#define I2C_ISR_TXE_Pos (0U)
3347#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
3348#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
3349#define I2C_ISR_TXIS_Pos (1U)
3350#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
3351#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
3352#define I2C_ISR_RXNE_Pos (2U)
3353#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
3354#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
3355#define I2C_ISR_ADDR_Pos (3U)
3356#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
3357#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
3358#define I2C_ISR_NACKF_Pos (4U)
3359#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
3360#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
3361#define I2C_ISR_STOPF_Pos (5U)
3362#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
3363#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
3364#define I2C_ISR_TC_Pos (6U)
3365#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
3366#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
3367#define I2C_ISR_TCR_Pos (7U)
3368#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
3369#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
3370#define I2C_ISR_BERR_Pos (8U)
3371#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
3372#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
3373#define I2C_ISR_ARLO_Pos (9U)
3374#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
3375#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
3376#define I2C_ISR_OVR_Pos (10U)
3377#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
3378#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
3379#define I2C_ISR_PECERR_Pos (11U)
3380#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
3381#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
3382#define I2C_ISR_TIMEOUT_Pos (12U)
3383#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
3384#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
3385#define I2C_ISR_ALERT_Pos (13U)
3386#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
3387#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
3388#define I2C_ISR_BUSY_Pos (15U)
3389#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
3390#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
3391#define I2C_ISR_DIR_Pos (16U)
3392#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
3393#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
3394#define I2C_ISR_ADDCODE_Pos (17U)
3395#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
3396#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
3397
3398/****************** Bit definition for I2C_ICR register *********************/
3399#define I2C_ICR_ADDRCF_Pos (3U)
3400#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
3401#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
3402#define I2C_ICR_NACKCF_Pos (4U)
3403#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
3404#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
3405#define I2C_ICR_STOPCF_Pos (5U)
3406#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
3407#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
3408#define I2C_ICR_BERRCF_Pos (8U)
3409#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
3410#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
3411#define I2C_ICR_ARLOCF_Pos (9U)
3412#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
3413#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
3414#define I2C_ICR_OVRCF_Pos (10U)
3415#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
3416#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
3417#define I2C_ICR_PECCF_Pos (11U)
3418#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
3419#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
3420#define I2C_ICR_TIMOUTCF_Pos (12U)
3421#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
3422#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
3423#define I2C_ICR_ALERTCF_Pos (13U)
3424#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
3425#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
3426
3427/****************** Bit definition for I2C_PECR register *********************/
3428#define I2C_PECR_PEC_Pos (0U)
3429#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
3430#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
3431
3432/****************** Bit definition for I2C_RXDR register *********************/
3433#define I2C_RXDR_RXDATA_Pos (0U)
3434#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
3435#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
3436
3437/****************** Bit definition for I2C_TXDR register *********************/
3438#define I2C_TXDR_TXDATA_Pos (0U)
3439#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
3440#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
3441
3442
3443/******************************************************************************/
3444/* */
3445/* Independent WATCHDOG (IWDG) */
3446/* */
3447/******************************************************************************/
3448/******************* Bit definition for IWDG_KR register ********************/
3449#define IWDG_KR_KEY_Pos (0U)
3450#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
3451#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
3452
3453/******************* Bit definition for IWDG_PR register ********************/
3454#define IWDG_PR_PR_Pos (0U)
3455#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
3456#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
3457#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
3458#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
3459#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
3460
3461/******************* Bit definition for IWDG_RLR register *******************/
3462#define IWDG_RLR_RL_Pos (0U)
3463#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
3464#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
3465
3466/******************* Bit definition for IWDG_SR register ********************/
3467#define IWDG_SR_PVU_Pos (0U)
3468#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
3469#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
3470#define IWDG_SR_RVU_Pos (1U)
3471#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
3472#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
3473#define IWDG_SR_WVU_Pos (2U)
3474#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
3475#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
3476
3477/******************* Bit definition for IWDG_KR register ********************/
3478#define IWDG_WINR_WIN_Pos (0U)
3479#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
3480#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
3481
3482
3483/******************************************************************************/
3484/* */
3485/* Power Control */
3486/* */
3487/******************************************************************************/
3488/* Note: No specific macro feature on this device */
3489
3490/******************** Bit definition for PWR_CR1 register ********************/
3491#define PWR_CR1_LPMS_Pos (0U)
3492#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
3493#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low Power Mode Selection */
3494#define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
3495#define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
3496#define PWR_CR1_FPD_STOP_Pos (3U)
3497#define PWR_CR1_FPD_STOP_Msk (0x1UL << PWR_CR1_FPD_STOP_Pos) /*!< 0x00000008 */
3498#define PWR_CR1_FPD_STOP PWR_CR1_FPD_STOP_Msk /*!< Flash power down mode during stop */
3499#define PWR_CR1_FPD_LPRUN_Pos (4U)
3500#define PWR_CR1_FPD_LPRUN_Msk (0x1UL << PWR_CR1_FPD_LPRUN_Pos) /*!< 0x00000010 */
3501#define PWR_CR1_FPD_LPRUN PWR_CR1_FPD_LPRUN_Msk /*!< Flash power down mode during run */
3502#define PWR_CR1_FPD_LPSLP_Pos (5U)
3503#define PWR_CR1_FPD_LPSLP_Msk (0x1UL << PWR_CR1_FPD_LPSLP_Pos) /*!< 0x00000020 */
3504#define PWR_CR1_FPD_LPSLP PWR_CR1_FPD_LPSLP_Msk /*!< Flash power down mode during sleep */
3505#define PWR_CR1_DBP_Pos (8U)
3506#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
3507#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Backup Domain write protection */
3508#define PWR_CR1_VOS_Pos (9U)
3509#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x00000600 */
3510#define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< Voltage scaling */
3511#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< Voltage scaling bit 0 */
3512#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< Voltage scaling bit 1 */
3513#define PWR_CR1_LPR_Pos (14U)
3514#define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
3515#define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator Low-Power Run mode */
3516
3517
3518/******************** Bit definition for PWR_CR3 register ********************/
3519#define PWR_CR3_EWUP_Pos (0U)
3520#define PWR_CR3_EWUP_Msk (0x3BUL << PWR_CR3_EWUP_Pos) /*!< 0x0000003B */
3521#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable all Wake-Up Pins */
3522#define PWR_CR3_EWUP1_Pos (0U)
3523#define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
3524#define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable WKUP pin 1 */
3525#define PWR_CR3_EWUP2_Pos (1U)
3526#define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
3527#define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable WKUP pin 2 */
3528#define PWR_CR3_EWUP4_Pos (3U)
3529#define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
3530#define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable WKUP pin 4 */
3531#define PWR_CR3_EWUP5_Pos (4U)
3532#define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
3533#define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable WKUP pin 5 */
3534#define PWR_CR3_EWUP6_Pos (5U)
3535#define PWR_CR3_EWUP6_Msk (0x1UL << PWR_CR3_EWUP6_Pos) /*!< 0x00000020 */
3536#define PWR_CR3_EWUP6 PWR_CR3_EWUP6_Msk /*!< Enable WKUP pin 6 */
3537#define PWR_CR3_APC_Pos (10U)
3538#define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */
3539#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
3540#define PWR_CR3_EIWUL_Pos (15U)
3541#define PWR_CR3_EIWUL_Msk (0x1UL << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
3542#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
3543
3544/******************** Bit definition for PWR_CR4 register ********************/
3545#define PWR_CR4_WP_Pos (0U)
3546#define PWR_CR4_WP_Msk (0x3BUL << PWR_CR4_WP_Pos) /*!< 0x0000003B */
3547#define PWR_CR4_WP PWR_CR4_WP_Msk /*!< all Wake-Up Pin polarity */
3548#define PWR_CR4_WP1_Pos (0U)
3549#define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos) /*!< 0x00000001 */
3550#define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */
3551#define PWR_CR4_WP2_Pos (1U)
3552#define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos) /*!< 0x00000002 */
3553#define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */
3554#define PWR_CR4_WP4_Pos (3U)
3555#define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos) /*!< 0x00000008 */
3556#define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */
3557#define PWR_CR4_WP5_Pos (4U)
3558#define PWR_CR4_WP5_Msk (0x1UL << PWR_CR4_WP5_Pos) /*!< 0x00000010 */
3559#define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */
3560#define PWR_CR4_WP6_Pos (5U)
3561#define PWR_CR4_WP6_Msk (0x1UL << PWR_CR4_WP6_Pos) /*!< 0x00000020 */
3562#define PWR_CR4_WP6 PWR_CR4_WP6_Msk /*!< Wake-Up Pin 6 polarity */
3563#define PWR_CR4_VBE_Pos (8U)
3564#define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
3565#define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
3566#define PWR_CR4_VBRS_Pos (9U)
3567#define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
3568#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
3569
3570/******************** Bit definition for PWR_SR1 register ********************/
3571#define PWR_SR1_WUF_Pos (0U)
3572#define PWR_SR1_WUF_Msk (0x3BUL << PWR_SR1_WUF_Pos) /*!< 0x0000003B */
3573#define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wakeup Flags */
3574#define PWR_SR1_WUF1_Pos (0U)
3575#define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
3576#define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wakeup Flag 1 */
3577#define PWR_SR1_WUF2_Pos (1U)
3578#define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
3579#define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wakeup Flag 2 */
3580#define PWR_SR1_WUF4_Pos (3U)
3581#define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
3582#define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wakeup Flag 4 */
3583#define PWR_SR1_WUF5_Pos (4U)
3584#define PWR_SR1_WUF5_Msk (0x1UL << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */
3585#define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wakeup Flag 5 */
3586#define PWR_SR1_WUF6_Pos (5U)
3587#define PWR_SR1_WUF6_Msk (0x1UL << PWR_SR1_WUF6_Pos) /*!< 0x00000020 */
3588#define PWR_SR1_WUF6 PWR_SR1_WUF6_Msk /*!< Wakeup Flag 6 */
3589#define PWR_SR1_SBF_Pos (8U)
3590#define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
3591#define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Standby Flag */
3592#define PWR_SR1_WUFI_Pos (15U)
3593#define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
3594#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wakeup Flag Internal */
3595
3596/******************** Bit definition for PWR_SR2 register ********************/
3597#define PWR_SR2_FLASH_RDY_Pos (7U)
3598#define PWR_SR2_FLASH_RDY_Msk (0x1UL << PWR_SR2_FLASH_RDY_Pos) /*!< 0x00000080 */
3599#define PWR_SR2_FLASH_RDY PWR_SR2_FLASH_RDY_Msk /*!< Flash Ready */
3600#define PWR_SR2_REGLPS_Pos (8U)
3601#define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
3602#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Regulator Low Power started */
3603#define PWR_SR2_REGLPF_Pos (9U)
3604#define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
3605#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Regulator Low Power flag */
3606#define PWR_SR2_VOSF_Pos (10U)
3607#define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
3608#define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
3609
3610/******************** Bit definition for PWR_SCR register ********************/
3611#define PWR_SCR_CWUF_Pos (0U)
3612#define PWR_SCR_CWUF_Msk (0x3BUL << PWR_SCR_CWUF_Pos) /*!< 0x0000003B */
3613#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
3614#define PWR_SCR_CWUF1_Pos (0U)
3615#define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
3616#define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
3617#define PWR_SCR_CWUF2_Pos (1U)
3618#define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
3619#define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
3620#define PWR_SCR_CWUF4_Pos (3U)
3621#define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
3622#define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
3623#define PWR_SCR_CWUF5_Pos (4U)
3624#define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
3625#define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */
3626#define PWR_SCR_CWUF6_Pos (5U)
3627#define PWR_SCR_CWUF6_Msk (0x1UL << PWR_SCR_CWUF6_Pos) /*!< 0x00000020 */
3628#define PWR_SCR_CWUF6 PWR_SCR_CWUF6_Msk /*!< Clear Wake-up Flag 6 */
3629#define PWR_SCR_CSBF_Pos (8U)
3630#define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
3631#define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Standby Flag */
3632
3633/******************** Bit definition for PWR_PUCRA register *****************/
3634#define PWR_PUCRA_PU0_Pos (0U)
3635#define PWR_PUCRA_PU0_Msk (0x1UL << PWR_PUCRA_PU0_Pos) /*!< 0x00000001 */
3636#define PWR_PUCRA_PU0 PWR_PUCRA_PU0_Msk /*!< Pin PA0 Pull-Up set */
3637#define PWR_PUCRA_PU1_Pos (1U)
3638#define PWR_PUCRA_PU1_Msk (0x1UL << PWR_PUCRA_PU1_Pos) /*!< 0x00000002 */
3639#define PWR_PUCRA_PU1 PWR_PUCRA_PU1_Msk /*!< Pin PA1 Pull-Up set */
3640#define PWR_PUCRA_PU2_Pos (2U)
3641#define PWR_PUCRA_PU2_Msk (0x1UL << PWR_PUCRA_PU2_Pos) /*!< 0x00000004 */
3642#define PWR_PUCRA_PU2 PWR_PUCRA_PU2_Msk /*!< Pin PA2 Pull-Up set */
3643#define PWR_PUCRA_PU3_Pos (3U)
3644#define PWR_PUCRA_PU3_Msk (0x1UL << PWR_PUCRA_PU3_Pos) /*!< 0x00000008 */
3645#define PWR_PUCRA_PU3 PWR_PUCRA_PU3_Msk /*!< Pin PA3 Pull-Up set */
3646#define PWR_PUCRA_PU4_Pos (4U)
3647#define PWR_PUCRA_PU4_Msk (0x1UL << PWR_PUCRA_PU4_Pos) /*!< 0x00000010 */
3648#define PWR_PUCRA_PU4 PWR_PUCRA_PU4_Msk /*!< Pin PA4 Pull-Up set */
3649#define PWR_PUCRA_PU5_Pos (5U)
3650#define PWR_PUCRA_PU5_Msk (0x1UL << PWR_PUCRA_PU5_Pos) /*!< 0x00000020 */
3651#define PWR_PUCRA_PU5 PWR_PUCRA_PU5_Msk /*!< Pin PA5 Pull-Up set */
3652#define PWR_PUCRA_PU6_Pos (6U)
3653#define PWR_PUCRA_PU6_Msk (0x1UL << PWR_PUCRA_PU6_Pos) /*!< 0x00000040 */
3654#define PWR_PUCRA_PU6 PWR_PUCRA_PU6_Msk /*!< Pin PA6 Pull-Up set */
3655#define PWR_PUCRA_PU7_Pos (7U)
3656#define PWR_PUCRA_PU7_Msk (0x1UL << PWR_PUCRA_PU7_Pos) /*!< 0x00000080 */
3657#define PWR_PUCRA_PU7 PWR_PUCRA_PU7_Msk /*!< Pin PA7 Pull-Up set */
3658#define PWR_PUCRA_PU8_Pos (8U)
3659#define PWR_PUCRA_PU8_Msk (0x1UL << PWR_PUCRA_PU8_Pos) /*!< 0x00000100 */
3660#define PWR_PUCRA_PU8 PWR_PUCRA_PU8_Msk /*!< Pin PA8 Pull-Up set */
3661#define PWR_PUCRA_PU9_Pos (9U)
3662#define PWR_PUCRA_PU9_Msk (0x1UL << PWR_PUCRA_PU9_Pos) /*!< 0x00000200 */
3663#define PWR_PUCRA_PU9 PWR_PUCRA_PU9_Msk /*!< Pin PA9 Pull-Up set */
3664#define PWR_PUCRA_PU10_Pos (10U)
3665#define PWR_PUCRA_PU10_Msk (0x1UL << PWR_PUCRA_PU10_Pos) /*!< 0x00000400 */
3666#define PWR_PUCRA_PU10 PWR_PUCRA_PU10_Msk /*!< Pin PA10 Pull-Up set */
3667#define PWR_PUCRA_PU11_Pos (11U)
3668#define PWR_PUCRA_PU11_Msk (0x1UL << PWR_PUCRA_PU11_Pos) /*!< 0x00000800 */
3669#define PWR_PUCRA_PU11 PWR_PUCRA_PU11_Msk /*!< Pin PA11 Pull-Up set */
3670#define PWR_PUCRA_PU12_Pos (12U)
3671#define PWR_PUCRA_PU12_Msk (0x1UL << PWR_PUCRA_PU12_Pos) /*!< 0x00001000 */
3672#define PWR_PUCRA_PU12 PWR_PUCRA_PU12_Msk /*!< Pin PA12 Pull-Up set */
3673#define PWR_PUCRA_PU13_Pos (13U)
3674#define PWR_PUCRA_PU13_Msk (0x1UL << PWR_PUCRA_PU13_Pos) /*!< 0x00002000 */
3675#define PWR_PUCRA_PU13 PWR_PUCRA_PU13_Msk /*!< Pin PA13 Pull-Up set */
3676#define PWR_PUCRA_PU14_Pos (14U)
3677#define PWR_PUCRA_PU14_Msk (0x1UL << PWR_PUCRA_PU14_Pos) /*!< 0x00004000 */
3678#define PWR_PUCRA_PU14 PWR_PUCRA_PU14_Msk /*!< Pin PA14 Pull-Up set */
3679#define PWR_PUCRA_PU15_Pos (15U)
3680#define PWR_PUCRA_PU15_Msk (0x1UL << PWR_PUCRA_PU15_Pos) /*!< 0x00008000 */
3681#define PWR_PUCRA_PU15 PWR_PUCRA_PU15_Msk /*!< Pin PA15 Pull-Up set */
3682
3683/******************** Bit definition for PWR_PDCRA register *****************/
3684#define PWR_PDCRA_PD0_Pos (0U)
3685#define PWR_PDCRA_PD0_Msk (0x1UL << PWR_PDCRA_PD0_Pos) /*!< 0x00000001 */
3686#define PWR_PDCRA_PD0 PWR_PDCRA_PD0_Msk /*!< Pin PA0 Pull-Down set */
3687#define PWR_PDCRA_PD1_Pos (1U)
3688#define PWR_PDCRA_PD1_Msk (0x1UL << PWR_PDCRA_PD1_Pos) /*!< 0x00000002 */
3689#define PWR_PDCRA_PD1 PWR_PDCRA_PD1_Msk /*!< Pin PA1 Pull-Down set */
3690#define PWR_PDCRA_PD2_Pos (2U)
3691#define PWR_PDCRA_PD2_Msk (0x1UL << PWR_PDCRA_PD2_Pos) /*!< 0x00000004 */
3692#define PWR_PDCRA_PD2 PWR_PDCRA_PD2_Msk /*!< Pin PA2 Pull-Down set */
3693#define PWR_PDCRA_PD3_Pos (3U)
3694#define PWR_PDCRA_PD3_Msk (0x1UL << PWR_PDCRA_PD3_Pos) /*!< 0x00000008 */
3695#define PWR_PDCRA_PD3 PWR_PDCRA_PD3_Msk /*!< Pin PA3 Pull-Down set */
3696#define PWR_PDCRA_PD4_Pos (4U)
3697#define PWR_PDCRA_PD4_Msk (0x1UL << PWR_PDCRA_PD4_Pos) /*!< 0x00000010 */
3698#define PWR_PDCRA_PD4 PWR_PDCRA_PD4_Msk /*!< Pin PA4 Pull-Down set */
3699#define PWR_PDCRA_PD5_Pos (5U)
3700#define PWR_PDCRA_PD5_Msk (0x1UL << PWR_PDCRA_PD5_Pos) /*!< 0x00000020 */
3701#define PWR_PDCRA_PD5 PWR_PDCRA_PD5_Msk /*!< Pin PA5 Pull-Down set */
3702#define PWR_PDCRA_PD6_Pos (6U)
3703#define PWR_PDCRA_PD6_Msk (0x1UL << PWR_PDCRA_PD6_Pos) /*!< 0x00000040 */
3704#define PWR_PDCRA_PD6 PWR_PDCRA_PD6_Msk /*!< Pin PA6 Pull-Down set */
3705#define PWR_PDCRA_PD7_Pos (7U)
3706#define PWR_PDCRA_PD7_Msk (0x1UL << PWR_PDCRA_PD7_Pos) /*!< 0x00000080 */
3707#define PWR_PDCRA_PD7 PWR_PDCRA_PD7_Msk /*!< Pin PA7 Pull-Down set */
3708#define PWR_PDCRA_PD8_Pos (8U)
3709#define PWR_PDCRA_PD8_Msk (0x1UL << PWR_PDCRA_PD8_Pos) /*!< 0x00000100 */
3710#define PWR_PDCRA_PD8 PWR_PDCRA_PD8_Msk /*!< Pin PA8 Pull-Down set */
3711#define PWR_PDCRA_PD9_Pos (9U)
3712#define PWR_PDCRA_PD9_Msk (0x1UL << PWR_PDCRA_PD9_Pos) /*!< 0x00000200 */
3713#define PWR_PDCRA_PD9 PWR_PDCRA_PD9_Msk /*!< Pin PA9 Pull-Down set */
3714#define PWR_PDCRA_PD10_Pos (10U)
3715#define PWR_PDCRA_PD10_Msk (0x1UL << PWR_PDCRA_PD10_Pos) /*!< 0x00000400 */
3716#define PWR_PDCRA_PD10 PWR_PDCRA_PD10_Msk /*!< Pin PA10 Pull-Down set */
3717#define PWR_PDCRA_PD11_Pos (11U)
3718#define PWR_PDCRA_PD11_Msk (0x1UL << PWR_PDCRA_PD11_Pos) /*!< 0x00000800 */
3719#define PWR_PDCRA_PD11 PWR_PDCRA_PD11_Msk /*!< Pin PA11 Pull-Down set */
3720#define PWR_PDCRA_PD12_Pos (12U)
3721#define PWR_PDCRA_PD12_Msk (0x1UL << PWR_PDCRA_PD12_Pos) /*!< 0x00001000 */
3722#define PWR_PDCRA_PD12 PWR_PDCRA_PD12_Msk /*!< Pin PA12 Pull-Down set */
3723#define PWR_PDCRA_PD13_Pos (13U)
3724#define PWR_PDCRA_PD13_Msk (0x1UL << PWR_PDCRA_PD13_Pos) /*!< 0x00002000 */
3725#define PWR_PDCRA_PD13 PWR_PDCRA_PD13_Msk /*!< Pin PA13 Pull-Down set */
3726#define PWR_PDCRA_PD14_Pos (14U)
3727#define PWR_PDCRA_PD14_Msk (0x1UL << PWR_PDCRA_PD14_Pos) /*!< 0x00004000 */
3728#define PWR_PDCRA_PD14 PWR_PDCRA_PD14_Msk /*!< Pin PA14 Pull-Down set */
3729#define PWR_PDCRA_PD15_Pos (15U)
3730#define PWR_PDCRA_PD15_Msk (0x1UL << PWR_PDCRA_PD15_Pos) /*!< 0x00008000 */
3731#define PWR_PDCRA_PD15 PWR_PDCRA_PD15_Msk /*!< Pin PA15 Pull-Down set */
3732
3733/******************** Bit definition for PWR_PUCRB register *****************/
3734#define PWR_PUCRB_PU0_Pos (0U)
3735#define PWR_PUCRB_PU0_Msk (0x1UL << PWR_PUCRB_PU0_Pos) /*!< 0x00000001 */
3736#define PWR_PUCRB_PU0 PWR_PUCRB_PU0_Msk /*!< Pin PB0 Pull-Up set */
3737#define PWR_PUCRB_PU1_Pos (1U)
3738#define PWR_PUCRB_PU1_Msk (0x1UL << PWR_PUCRB_PU1_Pos) /*!< 0x00000002 */
3739#define PWR_PUCRB_PU1 PWR_PUCRB_PU1_Msk /*!< Pin PB1 Pull-Up set */
3740#define PWR_PUCRB_PU2_Pos (2U)
3741#define PWR_PUCRB_PU2_Msk (0x1UL << PWR_PUCRB_PU2_Pos) /*!< 0x00000004 */
3742#define PWR_PUCRB_PU2 PWR_PUCRB_PU2_Msk /*!< Pin PB2 Pull-Up set */
3743#define PWR_PUCRB_PU3_Pos (3U)
3744#define PWR_PUCRB_PU3_Msk (0x1UL << PWR_PUCRB_PU3_Pos) /*!< 0x00000008 */
3745#define PWR_PUCRB_PU3 PWR_PUCRB_PU3_Msk /*!< Pin PB3 Pull-Up set */
3746#define PWR_PUCRB_PU4_Pos (4U)
3747#define PWR_PUCRB_PU4_Msk (0x1UL << PWR_PUCRB_PU4_Pos) /*!< 0x00000010 */
3748#define PWR_PUCRB_PU4 PWR_PUCRB_PU4_Msk /*!< Pin PB4 Pull-Up set */
3749#define PWR_PUCRB_PU5_Pos (5U)
3750#define PWR_PUCRB_PU5_Msk (0x1UL << PWR_PUCRB_PU5_Pos) /*!< 0x00000020 */
3751#define PWR_PUCRB_PU5 PWR_PUCRB_PU5_Msk /*!< Pin PB5 Pull-Up set */
3752#define PWR_PUCRB_PU6_Pos (6U)
3753#define PWR_PUCRB_PU6_Msk (0x1UL << PWR_PUCRB_PU6_Pos) /*!< 0x00000040 */
3754#define PWR_PUCRB_PU6 PWR_PUCRB_PU6_Msk /*!< Pin PB6 Pull-Up set */
3755#define PWR_PUCRB_PU7_Pos (7U)
3756#define PWR_PUCRB_PU7_Msk (0x1UL << PWR_PUCRB_PU7_Pos) /*!< 0x00000080 */
3757#define PWR_PUCRB_PU7 PWR_PUCRB_PU7_Msk /*!< Pin PB7 Pull-Up set */
3758#define PWR_PUCRB_PU8_Pos (8U)
3759#define PWR_PUCRB_PU8_Msk (0x1UL << PWR_PUCRB_PU8_Pos) /*!< 0x00000100 */
3760#define PWR_PUCRB_PU8 PWR_PUCRB_PU8_Msk /*!< Pin PB8 Pull-Up set */
3761#define PWR_PUCRB_PU9_Pos (9U)
3762#define PWR_PUCRB_PU9_Msk (0x1UL << PWR_PUCRB_PU9_Pos) /*!< 0x00000200 */
3763#define PWR_PUCRB_PU9 PWR_PUCRB_PU9_Msk /*!< Pin PB9 Pull-Up set */
3764#define PWR_PUCRB_PU10_Pos (10U)
3765#define PWR_PUCRB_PU10_Msk (0x1UL << PWR_PUCRB_PU10_Pos) /*!< 0x00000400 */
3766#define PWR_PUCRB_PU10 PWR_PUCRB_PU10_Msk /*!< Pin PB10 Pull-Up set */
3767#define PWR_PUCRB_PU11_Pos (11U)
3768#define PWR_PUCRB_PU11_Msk (0x1UL << PWR_PUCRB_PU11_Pos) /*!< 0x00000800 */
3769#define PWR_PUCRB_PU11 PWR_PUCRB_PU11_Msk /*!< Pin PB11 Pull-Up set */
3770#define PWR_PUCRB_PU12_Pos (12U)
3771#define PWR_PUCRB_PU12_Msk (0x1UL << PWR_PUCRB_PU12_Pos) /*!< 0x00001000 */
3772#define PWR_PUCRB_PU12 PWR_PUCRB_PU12_Msk /*!< Pin PB12 Pull-Up set */
3773#define PWR_PUCRB_PU13_Pos (13U)
3774#define PWR_PUCRB_PU13_Msk (0x1UL << PWR_PUCRB_PU13_Pos) /*!< 0x00002000 */
3775#define PWR_PUCRB_PU13 PWR_PUCRB_PU13_Msk /*!< Pin PB13 Pull-Up set */
3776#define PWR_PUCRB_PU14_Pos (14U)
3777#define PWR_PUCRB_PU14_Msk (0x1UL << PWR_PUCRB_PU14_Pos) /*!< 0x00004000 */
3778#define PWR_PUCRB_PU14 PWR_PUCRB_PU14_Msk /*!< Pin PB14 Pull-Up set */
3779#define PWR_PUCRB_PU15_Pos (15U)
3780#define PWR_PUCRB_PU15_Msk (0x1UL << PWR_PUCRB_PU15_Pos) /*!< 0x00008000 */
3781#define PWR_PUCRB_PU15 PWR_PUCRB_PU15_Msk /*!< Pin PB15 Pull-Up set */
3782
3783/******************** Bit definition for PWR_PDCRB register *****************/
3784#define PWR_PDCRB_PD0_Pos (0U)
3785#define PWR_PDCRB_PD0_Msk (0x1UL << PWR_PDCRB_PD0_Pos) /*!< 0x00000001 */
3786#define PWR_PDCRB_PD0 PWR_PDCRB_PD0_Msk /*!< Pin PB0 Pull-Down set */
3787#define PWR_PDCRB_PD1_Pos (1U)
3788#define PWR_PDCRB_PD1_Msk (0x1UL << PWR_PDCRB_PD1_Pos) /*!< 0x00000002 */
3789#define PWR_PDCRB_PD1 PWR_PDCRB_PD1_Msk /*!< Pin PB1 Pull-Down set */
3790#define PWR_PDCRB_PD2_Pos (2U)
3791#define PWR_PDCRB_PD2_Msk (0x1UL << PWR_PDCRB_PD2_Pos) /*!< 0x00000004 */
3792#define PWR_PDCRB_PD2 PWR_PDCRB_PD2_Msk /*!< Pin PB2 Pull-Down set */
3793#define PWR_PDCRB_PD3_Pos (3U)
3794#define PWR_PDCRB_PD3_Msk (0x1UL << PWR_PDCRB_PD3_Pos) /*!< 0x00000008 */
3795#define PWR_PDCRB_PD3 PWR_PDCRB_PD3_Msk /*!< Pin PB3 Pull-Down set */
3796#define PWR_PDCRB_PD4_Pos (4U)
3797#define PWR_PDCRB_PD4_Msk (0x1UL << PWR_PDCRB_PD4_Pos) /*!< 0x00000010 */
3798#define PWR_PDCRB_PD4 PWR_PDCRB_PD4_Msk /*!< Pin PB4 Pull-Down set */
3799#define PWR_PDCRB_PD5_Pos (5U)
3800#define PWR_PDCRB_PD5_Msk (0x1UL << PWR_PDCRB_PD5_Pos) /*!< 0x00000020 */
3801#define PWR_PDCRB_PD5 PWR_PDCRB_PD5_Msk /*!< Pin PB5 Pull-Down set */
3802#define PWR_PDCRB_PD6_Pos (6U)
3803#define PWR_PDCRB_PD6_Msk (0x1UL << PWR_PDCRB_PD6_Pos) /*!< 0x00000040 */
3804#define PWR_PDCRB_PD6 PWR_PDCRB_PD6_Msk /*!< Pin PB6 Pull-Down set */
3805#define PWR_PDCRB_PD7_Pos (7U)
3806#define PWR_PDCRB_PD7_Msk (0x1UL << PWR_PDCRB_PD7_Pos) /*!< 0x00000080 */
3807#define PWR_PDCRB_PD7 PWR_PDCRB_PD7_Msk /*!< Pin PB7 Pull-Down set */
3808#define PWR_PDCRB_PD8_Pos (8U)
3809#define PWR_PDCRB_PD8_Msk (0x1UL << PWR_PDCRB_PD8_Pos) /*!< 0x00000100 */
3810#define PWR_PDCRB_PD8 PWR_PDCRB_PD8_Msk /*!< Pin PB8 Pull-Down set */
3811#define PWR_PDCRB_PD9_Pos (9U)
3812#define PWR_PDCRB_PD9_Msk (0x1UL << PWR_PDCRB_PD9_Pos) /*!< 0x00000200 */
3813#define PWR_PDCRB_PD9 PWR_PDCRB_PD9_Msk /*!< Pin PB9 Pull-Down set */
3814#define PWR_PDCRB_PD10_Pos (10U)
3815#define PWR_PDCRB_PD10_Msk (0x1UL << PWR_PDCRB_PD10_Pos) /*!< 0x00000400 */
3816#define PWR_PDCRB_PD10 PWR_PDCRB_PD10_Msk /*!< Pin PB10 Pull-Down set */
3817#define PWR_PDCRB_PD11_Pos (11U)
3818#define PWR_PDCRB_PD11_Msk (0x1UL << PWR_PDCRB_PD11_Pos) /*!< 0x00000800 */
3819#define PWR_PDCRB_PD11 PWR_PDCRB_PD11_Msk /*!< Pin PB11 Pull-Down set */
3820#define PWR_PDCRB_PD12_Pos (12U)
3821#define PWR_PDCRB_PD12_Msk (0x1UL << PWR_PDCRB_PD12_Pos) /*!< 0x00001000 */
3822#define PWR_PDCRB_PD12 PWR_PDCRB_PD12_Msk /*!< Pin PB12 Pull-Down set */
3823#define PWR_PDCRB_PD13_Pos (13U)
3824#define PWR_PDCRB_PD13_Msk (0x1UL << PWR_PDCRB_PD13_Pos) /*!< 0x00002000 */
3825#define PWR_PDCRB_PD13 PWR_PDCRB_PD13_Msk /*!< Pin PB13 Pull-Down set */
3826#define PWR_PDCRB_PD14_Pos (14U)
3827#define PWR_PDCRB_PD14_Msk (0x1UL << PWR_PDCRB_PD14_Pos) /*!< 0x00004000 */
3828#define PWR_PDCRB_PD14 PWR_PDCRB_PD14_Msk /*!< Pin PB14 Pull-Down set */
3829#define PWR_PDCRB_PD15_Pos (15U)
3830#define PWR_PDCRB_PD15_Msk (0x1UL << PWR_PDCRB_PD15_Pos) /*!< 0x00008000 */
3831#define PWR_PDCRB_PD15 PWR_PDCRB_PD15_Msk /*!< Pin PB15 Pull-Down set */
3832
3833/******************** Bit definition for PWR_PUCRC register *****************/
3834#define PWR_PUCRC_PU0_Pos (0U)
3835#define PWR_PUCRC_PU0_Msk (0x1UL << PWR_PUCRC_PU0_Pos) /*!< 0x00000001 */
3836#define PWR_PUCRC_PU0 PWR_PUCRC_PU0_Msk /*!< Pin PC0 Pull-Up set */
3837#define PWR_PUCRC_PU1_Pos (1U)
3838#define PWR_PUCRC_PU1_Msk (0x1UL << PWR_PUCRC_PU1_Pos) /*!< 0x00000002 */
3839#define PWR_PUCRC_PU1 PWR_PUCRC_PU1_Msk /*!< Pin PC1 Pull-Up set */
3840#define PWR_PUCRC_PU2_Pos (2U)
3841#define PWR_PUCRC_PU2_Msk (0x1UL << PWR_PUCRC_PU2_Pos) /*!< 0x00000004 */
3842#define PWR_PUCRC_PU2 PWR_PUCRC_PU2_Msk /*!< Pin PC2 Pull-Up set */
3843#define PWR_PUCRC_PU3_Pos (3U)
3844#define PWR_PUCRC_PU3_Msk (0x1UL << PWR_PUCRC_PU3_Pos) /*!< 0x00000008 */
3845#define PWR_PUCRC_PU3 PWR_PUCRC_PU3_Msk /*!< Pin PC3 Pull-Up set */
3846#define PWR_PUCRC_PU4_Pos (4U)
3847#define PWR_PUCRC_PU4_Msk (0x1UL << PWR_PUCRC_PU4_Pos) /*!< 0x00000010 */
3848#define PWR_PUCRC_PU4 PWR_PUCRC_PU4_Msk /*!< Pin PC4 Pull-Up set */
3849#define PWR_PUCRC_PU5_Pos (5U)
3850#define PWR_PUCRC_PU5_Msk (0x1UL << PWR_PUCRC_PU5_Pos) /*!< 0x00000020 */
3851#define PWR_PUCRC_PU5 PWR_PUCRC_PU5_Msk /*!< Pin PC5 Pull-Up set */
3852#define PWR_PUCRC_PU6_Pos (6U)
3853#define PWR_PUCRC_PU6_Msk (0x1UL << PWR_PUCRC_PU6_Pos) /*!< 0x00000040 */
3854#define PWR_PUCRC_PU6 PWR_PUCRC_PU6_Msk /*!< Pin PC6 Pull-Up set */
3855#define PWR_PUCRC_PU7_Pos (7U)
3856#define PWR_PUCRC_PU7_Msk (0x1UL << PWR_PUCRC_PU7_Pos) /*!< 0x00000080 */
3857#define PWR_PUCRC_PU7 PWR_PUCRC_PU7_Msk /*!< Pin PC7 Pull-Up set */
3858#define PWR_PUCRC_PU8_Pos (8U)
3859#define PWR_PUCRC_PU8_Msk (0x1UL << PWR_PUCRC_PU8_Pos) /*!< 0x00000100 */
3860#define PWR_PUCRC_PU8 PWR_PUCRC_PU8_Msk /*!< Pin PC8 Pull-Up set */
3861#define PWR_PUCRC_PU9_Pos (9U)
3862#define PWR_PUCRC_PU9_Msk (0x1UL << PWR_PUCRC_PU9_Pos) /*!< 0x00000200 */
3863#define PWR_PUCRC_PU9 PWR_PUCRC_PU9_Msk /*!< Pin PC9 Pull-Up set */
3864#define PWR_PUCRC_PU10_Pos (10U)
3865#define PWR_PUCRC_PU10_Msk (0x1UL << PWR_PUCRC_PU10_Pos) /*!< 0x00000400 */
3866#define PWR_PUCRC_PU10 PWR_PUCRC_PU10_Msk /*!< Pin PC10 Pull-Up set */
3867#define PWR_PUCRC_PU11_Pos (11U)
3868#define PWR_PUCRC_PU11_Msk (0x1UL << PWR_PUCRC_PU11_Pos) /*!< 0x00000800 */
3869#define PWR_PUCRC_PU11 PWR_PUCRC_PU11_Msk /*!< Pin PC11 Pull-Up set */
3870#define PWR_PUCRC_PU12_Pos (12U)
3871#define PWR_PUCRC_PU12_Msk (0x1UL << PWR_PUCRC_PU12_Pos) /*!< 0x00001000 */
3872#define PWR_PUCRC_PU12 PWR_PUCRC_PU12_Msk /*!< Pin PC12 Pull-Up set */
3873#define PWR_PUCRC_PU13_Pos (13U)
3874#define PWR_PUCRC_PU13_Msk (0x1UL << PWR_PUCRC_PU13_Pos) /*!< 0x00002000 */
3875#define PWR_PUCRC_PU13 PWR_PUCRC_PU13_Msk /*!< Pin PC13 Pull-Up set */
3876#define PWR_PUCRC_PU14_Pos (14U)
3877#define PWR_PUCRC_PU14_Msk (0x1UL << PWR_PUCRC_PU14_Pos) /*!< 0x00004000 */
3878#define PWR_PUCRC_PU14 PWR_PUCRC_PU14_Msk /*!< Pin PC14 Pull-Up set */
3879#define PWR_PUCRC_PU15_Pos (15U)
3880#define PWR_PUCRC_PU15_Msk (0x1UL << PWR_PUCRC_PU15_Pos) /*!< 0x00008000 */
3881#define PWR_PUCRC_PU15 PWR_PUCRC_PU15_Msk /*!< Pin PC15 Pull-Up set */
3882
3883/******************** Bit definition for PWR_PDCRC register *****************/
3884#define PWR_PDCRC_PD0_Pos (0U)
3885#define PWR_PDCRC_PD0_Msk (0x1UL << PWR_PDCRC_PD0_Pos) /*!< 0x00000001 */
3886#define PWR_PDCRC_PD0 PWR_PDCRC_PD0_Msk /*!< Pin PC0 Pull-Down set */
3887#define PWR_PDCRC_PD1_Pos (1U)
3888#define PWR_PDCRC_PD1_Msk (0x1UL << PWR_PDCRC_PD1_Pos) /*!< 0x00000002 */
3889#define PWR_PDCRC_PD1 PWR_PDCRC_PD1_Msk /*!< Pin PC1 Pull-Down set */
3890#define PWR_PDCRC_PD2_Pos (2U)
3891#define PWR_PDCRC_PD2_Msk (0x1UL << PWR_PDCRC_PD2_Pos) /*!< 0x00000004 */
3892#define PWR_PDCRC_PD2 PWR_PDCRC_PD2_Msk /*!< Pin PC2 Pull-Down set */
3893#define PWR_PDCRC_PD3_Pos (3U)
3894#define PWR_PDCRC_PD3_Msk (0x1UL << PWR_PDCRC_PD3_Pos) /*!< 0x00000008 */
3895#define PWR_PDCRC_PD3 PWR_PDCRC_PD3_Msk /*!< Pin PC3 Pull-Down set */
3896#define PWR_PDCRC_PD4_Pos (4U)
3897#define PWR_PDCRC_PD4_Msk (0x1UL << PWR_PDCRC_PD4_Pos) /*!< 0x00000010 */
3898#define PWR_PDCRC_PD4 PWR_PDCRC_PD4_Msk /*!< Pin PC4 Pull-Down set */
3899#define PWR_PDCRC_PD5_Pos (5U)
3900#define PWR_PDCRC_PD5_Msk (0x1UL << PWR_PDCRC_PD5_Pos) /*!< 0x00000020 */
3901#define PWR_PDCRC_PD5 PWR_PDCRC_PD5_Msk /*!< Pin PC5 Pull-Down set */
3902#define PWR_PDCRC_PD6_Pos (6U)
3903#define PWR_PDCRC_PD6_Msk (0x1UL << PWR_PDCRC_PD6_Pos) /*!< 0x00000040 */
3904#define PWR_PDCRC_PD6 PWR_PDCRC_PD6_Msk /*!< Pin PC6 Pull-Down set */
3905#define PWR_PDCRC_PD7_Pos (7U)
3906#define PWR_PDCRC_PD7_Msk (0x1UL << PWR_PDCRC_PD7_Pos) /*!< 0x00000080 */
3907#define PWR_PDCRC_PD7 PWR_PDCRC_PD7_Msk /*!< Pin PC7 Pull-Down set */
3908#define PWR_PDCRC_PD8_Pos (8U)
3909#define PWR_PDCRC_PD8_Msk (0x1UL << PWR_PDCRC_PD8_Pos) /*!< 0x00000100 */
3910#define PWR_PDCRC_PD8 PWR_PDCRC_PD8_Msk /*!< Pin PC8 Pull-Down set */
3911#define PWR_PDCRC_PD9_Pos (9U)
3912#define PWR_PDCRC_PD9_Msk (0x1UL << PWR_PDCRC_PD9_Pos) /*!< 0x00000200 */
3913#define PWR_PDCRC_PD9 PWR_PDCRC_PD9_Msk /*!< Pin PC9 Pull-Down set */
3914#define PWR_PDCRC_PD10_Pos (10U)
3915#define PWR_PDCRC_PD10_Msk (0x1UL << PWR_PDCRC_PD10_Pos) /*!< 0x00000400 */
3916#define PWR_PDCRC_PD10 PWR_PDCRC_PD10_Msk /*!< Pin PC10 Pull-Down set */
3917#define PWR_PDCRC_PD11_Pos (11U)
3918#define PWR_PDCRC_PD11_Msk (0x1UL << PWR_PDCRC_PD11_Pos) /*!< 0x00000800 */
3919#define PWR_PDCRC_PD11 PWR_PDCRC_PD11_Msk /*!< Pin PC11 Pull-Down set */
3920#define PWR_PDCRC_PD12_Pos (12U)
3921#define PWR_PDCRC_PD12_Msk (0x1UL << PWR_PDCRC_PD12_Pos) /*!< 0x00001000 */
3922#define PWR_PDCRC_PD12 PWR_PDCRC_PD12_Msk /*!< Pin PC12 Pull-Down set */
3923#define PWR_PDCRC_PD13_Pos (13U)
3924#define PWR_PDCRC_PD13_Msk (0x1UL << PWR_PDCRC_PD13_Pos) /*!< 0x00002000 */
3925#define PWR_PDCRC_PD13 PWR_PDCRC_PD13_Msk /*!< Pin PC13 Pull-Down set */
3926#define PWR_PDCRC_PD14_Pos (14U)
3927#define PWR_PDCRC_PD14_Msk (0x1UL << PWR_PDCRC_PD14_Pos) /*!< 0x00004000 */
3928#define PWR_PDCRC_PD14 PWR_PDCRC_PD14_Msk /*!< Pin PC14 Pull-Down set */
3929#define PWR_PDCRC_PD15_Pos (15U)
3930#define PWR_PDCRC_PD15_Msk (0x1UL << PWR_PDCRC_PD15_Pos) /*!< 0x00008000 */
3931#define PWR_PDCRC_PD15 PWR_PDCRC_PD15_Msk /*!< Pin PC15 Pull-Down set */
3932
3933/******************** Bit definition for PWR_PUCRD register *****************/
3934#define PWR_PUCRD_PU0_Pos (0U)
3935#define PWR_PUCRD_PU0_Msk (0x1UL << PWR_PUCRD_PU0_Pos) /*!< 0x00000001 */
3936#define PWR_PUCRD_PU0 PWR_PUCRD_PU0_Msk /*!< Pin PD0 Pull-Up set */
3937#define PWR_PUCRD_PU1_Pos (1U)
3938#define PWR_PUCRD_PU1_Msk (0x1UL << PWR_PUCRD_PU1_Pos) /*!< 0x00000002 */
3939#define PWR_PUCRD_PU1 PWR_PUCRD_PU1_Msk /*!< Pin PD1 Pull-Up set */
3940#define PWR_PUCRD_PU2_Pos (2U)
3941#define PWR_PUCRD_PU2_Msk (0x1UL << PWR_PUCRD_PU2_Pos) /*!< 0x00000004 */
3942#define PWR_PUCRD_PU2 PWR_PUCRD_PU2_Msk /*!< Pin PD2 Pull-Up set */
3943#define PWR_PUCRD_PU3_Pos (3U)
3944#define PWR_PUCRD_PU3_Msk (0x1UL << PWR_PUCRD_PU3_Pos) /*!< 0x00000008 */
3945#define PWR_PUCRD_PU3 PWR_PUCRD_PU3_Msk /*!< Pin PD3 Pull-Up set */
3946#define PWR_PUCRD_PU4_Pos (4U)
3947#define PWR_PUCRD_PU4_Msk (0x1UL << PWR_PUCRD_PU4_Pos) /*!< 0x00000010 */
3948#define PWR_PUCRD_PU4 PWR_PUCRD_PU4_Msk /*!< Pin PD4 Pull-Up set */
3949#define PWR_PUCRD_PU5_Pos (5U)
3950#define PWR_PUCRD_PU5_Msk (0x1UL << PWR_PUCRD_PU5_Pos) /*!< 0x00000020 */
3951#define PWR_PUCRD_PU5 PWR_PUCRD_PU5_Msk /*!< Pin PD5 Pull-Up set */
3952#define PWR_PUCRD_PU6_Pos (6U)
3953#define PWR_PUCRD_PU6_Msk (0x1UL << PWR_PUCRD_PU6_Pos) /*!< 0x00000040 */
3954#define PWR_PUCRD_PU6 PWR_PUCRD_PU6_Msk /*!< Pin PD6 Pull-Up set */
3955#define PWR_PUCRD_PU8_Pos (8U)
3956#define PWR_PUCRD_PU8_Msk (0x1UL << PWR_PUCRD_PU8_Pos) /*!< 0x00000100 */
3957#define PWR_PUCRD_PU8 PWR_PUCRD_PU8_Msk /*!< Pin PD8 Pull-Up set */
3958#define PWR_PUCRD_PU9_Pos (9U)
3959#define PWR_PUCRD_PU9_Msk (0x1UL << PWR_PUCRD_PU9_Pos) /*!< 0x00000200 */
3960#define PWR_PUCRD_PU9 PWR_PUCRD_PU9_Msk /*!< Pin PD9 Pull-Up set */
3961
3962/******************** Bit definition for PWR_PDCRD register *****************/
3963#define PWR_PDCRD_PD0_Pos (0U)
3964#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
3965#define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Pin PD0 Pull-Down set */
3966#define PWR_PDCRD_PD1_Pos (1U)
3967#define PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */
3968#define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Pin PD1 Pull-Down set */
3969#define PWR_PDCRD_PD2_Pos (2U)
3970#define PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */
3971#define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Pin PD2 Pull-Down set */
3972#define PWR_PDCRD_PD3_Pos (3U)
3973#define PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */
3974#define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Pin PD3 Pull-Down set */
3975#define PWR_PDCRD_PD4_Pos (4U)
3976#define PWR_PDCRD_PD4_Msk (0x1UL << PWR_PDCRD_PD4_Pos) /*!< 0x00000010 */
3977#define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk /*!< Pin PD4 Pull-Down set */
3978#define PWR_PDCRD_PD5_Pos (5U)
3979#define PWR_PDCRD_PD5_Msk (0x1UL << PWR_PDCRD_PD5_Pos) /*!< 0x00000020 */
3980#define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk /*!< Pin PD5 Pull-Down set */
3981#define PWR_PDCRD_PD6_Pos (6U)
3982#define PWR_PDCRD_PD6_Msk (0x1UL << PWR_PDCRD_PD6_Pos) /*!< 0x00000040 */
3983#define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk /*!< Pin PD6 Pull-Down set */
3984#define PWR_PDCRD_PD8_Pos (8U)
3985#define PWR_PDCRD_PD8_Msk (0x1UL << PWR_PDCRD_PD8_Pos) /*!< 0x00000100 */
3986#define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk /*!< Pin PD8 Pull-Down set */
3987#define PWR_PDCRD_PD9_Pos (9U)
3988#define PWR_PDCRD_PD9_Msk (0x1UL << PWR_PDCRD_PD9_Pos) /*!< 0x00000200 */
3989#define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk /*!< Pin PD9 Pull-Down set */
3990
3991/******************** Bit definition for PWR_PUCRF register *****************/
3992#define PWR_PUCRF_PU0_Pos (0U)
3993#define PWR_PUCRF_PU0_Msk (0x1UL << PWR_PUCRF_PU0_Pos) /*!< 0x00000001 */
3994#define PWR_PUCRF_PU0 PWR_PUCRF_PU0_Msk /*!< Pin PF0 Pull-Up set */
3995#define PWR_PUCRF_PU1_Pos (1U)
3996#define PWR_PUCRF_PU1_Msk (0x1UL << PWR_PUCRF_PU1_Pos) /*!< 0x00000002 */
3997#define PWR_PUCRF_PU1 PWR_PUCRF_PU1_Msk /*!< Pin PF1 Pull-Up set */
3998#define PWR_PUCRF_PU2_Pos (2U)
3999#define PWR_PUCRF_PU2_Msk (0x1UL << PWR_PUCRF_PU2_Pos) /*!< 0x00000004 */
4000#define PWR_PUCRF_PU2 PWR_PUCRF_PU2_Msk /*!< Pin PF2 Pull-Up set */
4001#define PWR_PUCRF_PU3_Pos (3U)
4002#define PWR_PUCRF_PU3_Msk (0x1UL << PWR_PUCRF_PU3_Pos) /*!< 0x00000008 */
4003#define PWR_PUCRF_PU3 PWR_PUCRF_PU3_Msk /*!< Pin PF3 Pull-Up set */
4004#define PWR_PUCRF_PU4_Pos (4U)
4005#define PWR_PUCRF_PU4_Msk (0x1UL << PWR_PUCRF_PU4_Pos) /*!< 0x00000010 */
4006#define PWR_PUCRF_PU4 PWR_PUCRF_PU4_Msk /*!< Pin PF4 Pull-Up set */
4007
4008/******************** Bit definition for PWR_PDCRF register *****************/
4009#define PWR_PDCRF_PD0_Pos (0U)
4010#define PWR_PDCRF_PD0_Msk (0x1UL << PWR_PDCRF_PD0_Pos) /*!< 0x00000001 */
4011#define PWR_PDCRF_PD0 PWR_PDCRF_PD0_Msk /*!< Pin PF0 Pull-Down set */
4012#define PWR_PDCRF_PD1_Pos (1U)
4013#define PWR_PDCRF_PD1_Msk (0x1UL << PWR_PDCRF_PD1_Pos) /*!< 0x00000002 */
4014#define PWR_PDCRF_PD1 PWR_PDCRF_PD1_Msk /*!< Pin PF1 Pull-Down set */
4015#define PWR_PDCRF_PD2_Pos (2U)
4016#define PWR_PDCRF_PD2_Msk (0x1UL << PWR_PDCRF_PD2_Pos) /*!< 0x00000004 */
4017#define PWR_PDCRF_PD2 PWR_PDCRF_PD2_Msk /*!< Pin PF2 Pull-Down set */
4018#define PWR_PDCRF_PD3_Pos (3U)
4019#define PWR_PDCRF_PD3_Msk (0x1UL << PWR_PDCRF_PD3_Pos) /*!< 0x00000008 */
4020#define PWR_PDCRF_PD3 PWR_PDCRF_PD3_Msk /*!< Pin PF3 Pull-Down set */
4021#define PWR_PDCRF_PD4_Pos (4U)
4022#define PWR_PDCRF_PD4_Msk (0x1UL << PWR_PDCRF_PD4_Pos) /*!< 0x00000010 */
4023#define PWR_PDCRF_PD4 PWR_PDCRF_PD4_Msk /*!< Pin PF4 Pull-Down set */
4024
4025/******************************************************************************/
4026/* */
4027/* Reset and Clock Control */
4028/* */
4029/******************************************************************************/
4030/*
4031* @brief Specific device feature definitions (not present on all devices in the STM32G0 serie)
4032*/
4033
4034/******************** Bit definition for RCC_CR register *****************/
4035#define RCC_CR_HSION_Pos (8U)
4036#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */
4037#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
4038#define RCC_CR_HSIKERON_Pos (9U)
4039#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
4040#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
4041#define RCC_CR_HSIRDY_Pos (10U)
4042#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
4043#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
4044#define RCC_CR_HSIDIV_Pos (11U)
4045#define RCC_CR_HSIDIV_Msk (0x7UL << RCC_CR_HSIDIV_Pos) /*!< 0x00003800 */
4046#define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk /*!< HSIDIV[13:11] Internal High Speed clock division factor */
4047#define RCC_CR_HSIDIV_0 (0x1UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000800 */
4048#define RCC_CR_HSIDIV_1 (0x2UL << RCC_CR_HSIDIV_Pos) /*!< 0x00001000 */
4049#define RCC_CR_HSIDIV_2 (0x4UL << RCC_CR_HSIDIV_Pos) /*!< 0x00002000 */
4050#define RCC_CR_HSEON_Pos (16U)
4051#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
4052#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
4053#define RCC_CR_HSERDY_Pos (17U)
4054#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
4055#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready */
4056#define RCC_CR_HSEBYP_Pos (18U)
4057#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
4058#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
4059#define RCC_CR_CSSON_Pos (19U)
4060#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
4061#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
4062
4063#define RCC_CR_PLLON_Pos (24U)
4064#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
4065#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
4066#define RCC_CR_PLLRDY_Pos (25U)
4067#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
4068#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
4069
4070/******************** Bit definition for RCC_ICSCR register ***************/
4071/*!< HSICAL configuration */
4072#define RCC_ICSCR_HSICAL_Pos (0U)
4073#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
4074#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
4075#define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000001 */
4076#define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000002 */
4077#define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000004 */
4078#define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000008 */
4079#define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000010 */
4080#define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000020 */
4081#define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000040 */
4082#define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000080 */
4083
4084/*!< HSITRIM configuration */
4085#define RCC_ICSCR_HSITRIM_Pos (8U)
4086#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00007F00 */
4087#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[14:8] bits */
4088#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000100 */
4089#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000200 */
4090#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000400 */
4091#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000800 */
4092#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001000 */
4093#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00002000 */
4094#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00004000 */
4095
4096/******************** Bit definition for RCC_CFGR register ***************/
4097/*!< SW configuration */
4098#define RCC_CFGR_SW_Pos (0U)
4099#define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos) /*!< 0x00000007 */
4100#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[2:0] bits (System clock Switch) */
4101#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
4102#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
4103#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */
4104
4105/*!< SWS configuration */
4106#define RCC_CFGR_SWS_Pos (3U)
4107#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */
4108#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[2:0] bits (System Clock Switch Status) */
4109#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
4110#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */
4111#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */
4112
4113#define RCC_CFGR_SWS_HSI (0UL) /*!< HSI used as system clock */
4114#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */
4115#define RCC_CFGR_SWS_PLL (0x00000010UL) /*!< PLL used as system clock */
4116#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */
4117#define RCC_CFGR_SWS_LSE (0x00000020UL) /*!< LSE used as system clock */
4118
4119/*!< HPRE configuration */
4120#define RCC_CFGR_HPRE_Pos (8U)
4121#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */
4122#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
4123#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000100 */
4124#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000200 */
4125#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000400 */
4126#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000800 */
4127
4128/*!< PPRE configuration */
4129#define RCC_CFGR_PPRE_Pos (12U)
4130#define RCC_CFGR_PPRE_Msk (0x7UL << RCC_CFGR_PPRE_Pos) /*!< 0x00007000 */
4131#define RCC_CFGR_PPRE RCC_CFGR_PPRE_Msk /*!< PRE1[2:0] bits (APB prescaler) */
4132#define RCC_CFGR_PPRE_0 (0x1UL << RCC_CFGR_PPRE_Pos) /*!< 0x00001000 */
4133#define RCC_CFGR_PPRE_1 (0x2UL << RCC_CFGR_PPRE_Pos) /*!< 0x00002000 */
4134#define RCC_CFGR_PPRE_2 (0x4UL << RCC_CFGR_PPRE_Pos) /*!< 0x00004000 */
4135
4136/*!< MCOSEL configuration */
4137#define RCC_CFGR_MCOSEL_Pos (24U)
4138#define RCC_CFGR_MCOSEL_Msk (0x7UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
4139#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [2:0] bits (Clock output selection) */
4140#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
4141#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
4142#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
4143
4144/*!< MCO Prescaler configuration */
4145#define RCC_CFGR_MCOPRE_Pos (28U)
4146#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
4147#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler [2:0] */
4148#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
4149#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
4150#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
4151
4152/******************** Bit definition for RCC_PLLCFGR register ***************/
4153#define RCC_PLLCFGR_PLLSRC_Pos (0U)
4154#define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
4155#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
4156#define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
4157#define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
4158
4159#define RCC_PLLCFGR_PLLSRC_NONE (0x00000000UL) /*!< No clock sent to PLL */
4160#define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
4161#define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
4162#define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI source clock selected */
4163#define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
4164#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
4165#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE source clock selected */
4166
4167#define RCC_PLLCFGR_PLLM_Pos (4U)
4168#define RCC_PLLCFGR_PLLM_Msk (0x7UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */
4169#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
4170#define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
4171#define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
4172#define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
4173
4174#define RCC_PLLCFGR_PLLN_Pos (8U)
4175#define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
4176#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
4177#define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
4178#define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
4179#define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
4180#define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
4181#define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
4182#define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
4183#define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
4184
4185#define RCC_PLLCFGR_PLLPEN_Pos (16U)
4186#define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
4187#define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
4188
4189#define RCC_PLLCFGR_PLLP_Pos (17U)
4190#define RCC_PLLCFGR_PLLP_Msk (0x1FUL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x003E0000 */
4191#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
4192#define RCC_PLLCFGR_PLLP_0 (0x01UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
4193#define RCC_PLLCFGR_PLLP_1 (0x02UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00040000 */
4194#define RCC_PLLCFGR_PLLP_2 (0x04UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00080000 */
4195#define RCC_PLLCFGR_PLLP_3 (0x08UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00100000 */
4196#define RCC_PLLCFGR_PLLP_4 (0x10UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00200000 */
4197
4198
4199#define RCC_PLLCFGR_PLLREN_Pos (28U)
4200#define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x10000000 */
4201#define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
4202
4203#define RCC_PLLCFGR_PLLR_Pos (29U)
4204#define RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0xE0000000 */
4205#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
4206#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
4207#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
4208#define RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x80000000 */
4209
4210/******************** Bit definition for RCC_CIER register ******************/
4211#define RCC_CIER_LSIRDYIE_Pos (0U)
4212#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
4213#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
4214#define RCC_CIER_LSERDYIE_Pos (1U)
4215#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
4216#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
4217#define RCC_CIER_HSIRDYIE_Pos (3U)
4218#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
4219#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
4220#define RCC_CIER_HSERDYIE_Pos (4U)
4221#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
4222#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
4223#define RCC_CIER_PLLRDYIE_Pos (5U)
4224#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
4225#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
4226
4227/******************** Bit definition for RCC_CIFR register ******************/
4228#define RCC_CIFR_LSIRDYF_Pos (0U)
4229#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
4230#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
4231#define RCC_CIFR_LSERDYF_Pos (1U)
4232#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
4233#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
4234#define RCC_CIFR_HSIRDYF_Pos (3U)
4235#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
4236#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
4237#define RCC_CIFR_HSERDYF_Pos (4U)
4238#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
4239#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
4240#define RCC_CIFR_PLLRDYF_Pos (5U)
4241#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
4242#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
4243#define RCC_CIFR_CSSF_Pos (8U)
4244#define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
4245#define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
4246#define RCC_CIFR_LSECSSF_Pos (9U)
4247#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
4248#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
4249
4250/******************** Bit definition for RCC_CICR register ******************/
4251#define RCC_CICR_LSIRDYC_Pos (0U)
4252#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
4253#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
4254#define RCC_CICR_LSERDYC_Pos (1U)
4255#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
4256#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
4257#define RCC_CICR_HSIRDYC_Pos (3U)
4258#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
4259#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
4260#define RCC_CICR_HSERDYC_Pos (4U)
4261#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
4262#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
4263#define RCC_CICR_PLLRDYC_Pos (5U)
4264#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
4265#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
4266#define RCC_CICR_CSSC_Pos (8U)
4267#define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
4268#define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
4269#define RCC_CICR_LSECSSC_Pos (9U)
4270#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
4271#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
4272
4273/******************** Bit definition for RCC_IOPRSTR register ****************/
4274#define RCC_IOPRSTR_GPIOARST_Pos (0U)
4275#define RCC_IOPRSTR_GPIOARST_Msk (0x1UL << RCC_IOPRSTR_GPIOARST_Pos) /*!< 0x00000001 */
4276#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_GPIOARST_Msk
4277#define RCC_IOPRSTR_GPIOBRST_Pos (1U)
4278#define RCC_IOPRSTR_GPIOBRST_Msk (0x1UL << RCC_IOPRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
4279#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_GPIOBRST_Msk
4280#define RCC_IOPRSTR_GPIOCRST_Pos (2U)
4281#define RCC_IOPRSTR_GPIOCRST_Msk (0x1UL << RCC_IOPRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
4282#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_GPIOCRST_Msk
4283#define RCC_IOPRSTR_GPIODRST_Pos (3U)
4284#define RCC_IOPRSTR_GPIODRST_Msk (0x1UL << RCC_IOPRSTR_GPIODRST_Pos) /*!< 0x00000008 */
4285#define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_GPIODRST_Msk
4286#define RCC_IOPRSTR_GPIOFRST_Pos (5U)
4287#define RCC_IOPRSTR_GPIOFRST_Msk (0x1UL << RCC_IOPRSTR_GPIOFRST_Pos) /*!< 0x00000020 */
4288#define RCC_IOPRSTR_GPIOFRST RCC_IOPRSTR_GPIOFRST_Msk
4289
4290/******************** Bit definition for RCC_AHBRSTR register ***************/
4291#define RCC_AHBRSTR_DMA1RST_Pos (0U)
4292#define RCC_AHBRSTR_DMA1RST_Msk (0x1UL << RCC_AHBRSTR_DMA1RST_Pos) /*!< 0x00000001 */
4293#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMA1RST_Msk
4294#define RCC_AHBRSTR_FLASHRST_Pos (8U)
4295#define RCC_AHBRSTR_FLASHRST_Msk (0x1UL << RCC_AHBRSTR_FLASHRST_Pos) /*!< 0x00000100 */
4296#define RCC_AHBRSTR_FLASHRST RCC_AHBRSTR_FLASHRST_Msk
4297#define RCC_AHBRSTR_CRCRST_Pos (12U)
4298#define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
4299#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk
4300
4301/******************** Bit definition for RCC_APBRSTR1 register **************/
4302#define RCC_APBRSTR1_TIM3RST_Pos (1U)
4303#define RCC_APBRSTR1_TIM3RST_Msk (0x1UL << RCC_APBRSTR1_TIM3RST_Pos) /*!< 0x00000002 */
4304#define RCC_APBRSTR1_TIM3RST RCC_APBRSTR1_TIM3RST_Msk
4305#define RCC_APBRSTR1_TIM6RST_Pos (4U)
4306#define RCC_APBRSTR1_TIM6RST_Msk (0x1UL << RCC_APBRSTR1_TIM6RST_Pos) /*!< 0x00000010 */
4307#define RCC_APBRSTR1_TIM6RST RCC_APBRSTR1_TIM6RST_Msk
4308#define RCC_APBRSTR1_TIM7RST_Pos (5U)
4309#define RCC_APBRSTR1_TIM7RST_Msk (0x1UL << RCC_APBRSTR1_TIM7RST_Pos) /*!< 0x00000020 */
4310#define RCC_APBRSTR1_TIM7RST RCC_APBRSTR1_TIM7RST_Msk
4311#define RCC_APBRSTR1_SPI2RST_Pos (14U)
4312#define RCC_APBRSTR1_SPI2RST_Msk (0x1UL << RCC_APBRSTR1_SPI2RST_Pos) /*!< 0x00004000 */
4313#define RCC_APBRSTR1_SPI2RST RCC_APBRSTR1_SPI2RST_Msk
4314#define RCC_APBRSTR1_USART2RST_Pos (17U)
4315#define RCC_APBRSTR1_USART2RST_Msk (0x1UL << RCC_APBRSTR1_USART2RST_Pos) /*!< 0x00020000 */
4316#define RCC_APBRSTR1_USART2RST RCC_APBRSTR1_USART2RST_Msk
4317#define RCC_APBRSTR1_USART3RST_Pos (18U)
4318#define RCC_APBRSTR1_USART3RST_Msk (0x1UL << RCC_APBRSTR1_USART3RST_Pos) /*!< 0x00040000 */
4319#define RCC_APBRSTR1_USART3RST RCC_APBRSTR1_USART3RST_Msk
4320#define RCC_APBRSTR1_USART4RST_Pos (19U)
4321#define RCC_APBRSTR1_USART4RST_Msk (0x1UL << RCC_APBRSTR1_USART4RST_Pos) /*!< 0x00080000 */
4322#define RCC_APBRSTR1_USART4RST RCC_APBRSTR1_USART4RST_Msk
4323#define RCC_APBRSTR1_I2C1RST_Pos (21U)
4324#define RCC_APBRSTR1_I2C1RST_Msk (0x1UL << RCC_APBRSTR1_I2C1RST_Pos) /*!< 0x00200000 */
4325#define RCC_APBRSTR1_I2C1RST RCC_APBRSTR1_I2C1RST_Msk
4326#define RCC_APBRSTR1_I2C2RST_Pos (22U)
4327#define RCC_APBRSTR1_I2C2RST_Msk (0x1UL << RCC_APBRSTR1_I2C2RST_Pos) /*!< 0x00400000 */
4328#define RCC_APBRSTR1_I2C2RST RCC_APBRSTR1_I2C2RST_Msk
4329#define RCC_APBRSTR1_DBGRST_Pos (27U)
4330#define RCC_APBRSTR1_DBGRST_Msk (0x1UL << RCC_APBRSTR1_DBGRST_Pos) /*!< 0x08000000 */
4331#define RCC_APBRSTR1_DBGRST RCC_APBRSTR1_DBGRST_Msk
4332#define RCC_APBRSTR1_PWRRST_Pos (28U)
4333#define RCC_APBRSTR1_PWRRST_Msk (0x1UL << RCC_APBRSTR1_PWRRST_Pos) /*!< 0x10000000 */
4334#define RCC_APBRSTR1_PWRRST RCC_APBRSTR1_PWRRST_Msk
4335
4336/******************** Bit definition for RCC_APBRSTR2 register **************/
4337#define RCC_APBRSTR2_SYSCFGRST_Pos (0U)
4338#define RCC_APBRSTR2_SYSCFGRST_Msk (0x1UL << RCC_APBRSTR2_SYSCFGRST_Pos) /*!< 0x00000001 */
4339#define RCC_APBRSTR2_SYSCFGRST RCC_APBRSTR2_SYSCFGRST_Msk
4340#define RCC_APBRSTR2_TIM1RST_Pos (11U)
4341#define RCC_APBRSTR2_TIM1RST_Msk (0x1UL << RCC_APBRSTR2_TIM1RST_Pos) /*!< 0x00000800 */
4342#define RCC_APBRSTR2_TIM1RST RCC_APBRSTR2_TIM1RST_Msk
4343#define RCC_APBRSTR2_SPI1RST_Pos (12U)
4344#define RCC_APBRSTR2_SPI1RST_Msk (0x1UL << RCC_APBRSTR2_SPI1RST_Pos) /*!< 0x00001000 */
4345#define RCC_APBRSTR2_SPI1RST RCC_APBRSTR2_SPI1RST_Msk
4346#define RCC_APBRSTR2_USART1RST_Pos (14U)
4347#define RCC_APBRSTR2_USART1RST_Msk (0x1UL << RCC_APBRSTR2_USART1RST_Pos) /*!< 0x00004000 */
4348#define RCC_APBRSTR2_USART1RST RCC_APBRSTR2_USART1RST_Msk
4349#define RCC_APBRSTR2_TIM14RST_Pos (15U)
4350#define RCC_APBRSTR2_TIM14RST_Msk (0x1UL << RCC_APBRSTR2_TIM14RST_Pos) /*!< 0x00008000 */
4351#define RCC_APBRSTR2_TIM14RST RCC_APBRSTR2_TIM14RST_Msk
4352#define RCC_APBRSTR2_TIM15RST_Pos (16U)
4353#define RCC_APBRSTR2_TIM15RST_Msk (0x1UL << RCC_APBRSTR2_TIM15RST_Pos) /*!< 0x00010000 */
4354#define RCC_APBRSTR2_TIM15RST RCC_APBRSTR2_TIM15RST_Msk
4355#define RCC_APBRSTR2_TIM16RST_Pos (17U)
4356#define RCC_APBRSTR2_TIM16RST_Msk (0x1UL << RCC_APBRSTR2_TIM16RST_Pos) /*!< 0x00020000 */
4357#define RCC_APBRSTR2_TIM16RST RCC_APBRSTR2_TIM16RST_Msk
4358#define RCC_APBRSTR2_TIM17RST_Pos (18U)
4359#define RCC_APBRSTR2_TIM17RST_Msk (0x1UL << RCC_APBRSTR2_TIM17RST_Pos) /*!< 0x00040000 */
4360#define RCC_APBRSTR2_TIM17RST RCC_APBRSTR2_TIM17RST_Msk
4361#define RCC_APBRSTR2_ADCRST_Pos (20U)
4362#define RCC_APBRSTR2_ADCRST_Msk (0x1UL << RCC_APBRSTR2_ADCRST_Pos) /*!< 0x00100000 */
4363#define RCC_APBRSTR2_ADCRST RCC_APBRSTR2_ADCRST_Msk
4364
4365/******************** Bit definition for RCC_IOPENR register ****************/
4366#define RCC_IOPENR_GPIOAEN_Pos (0U)
4367#define RCC_IOPENR_GPIOAEN_Msk (0x1UL << RCC_IOPENR_GPIOAEN_Pos) /*!< 0x00000001 */
4368#define RCC_IOPENR_GPIOAEN RCC_IOPENR_GPIOAEN_Msk
4369#define RCC_IOPENR_GPIOBEN_Pos (1U)
4370#define RCC_IOPENR_GPIOBEN_Msk (0x1UL << RCC_IOPENR_GPIOBEN_Pos) /*!< 0x00000002 */
4371#define RCC_IOPENR_GPIOBEN RCC_IOPENR_GPIOBEN_Msk
4372#define RCC_IOPENR_GPIOCEN_Pos (2U)
4373#define RCC_IOPENR_GPIOCEN_Msk (0x1UL << RCC_IOPENR_GPIOCEN_Pos) /*!< 0x00000004 */
4374#define RCC_IOPENR_GPIOCEN RCC_IOPENR_GPIOCEN_Msk
4375#define RCC_IOPENR_GPIODEN_Pos (3U)
4376#define RCC_IOPENR_GPIODEN_Msk (0x1UL << RCC_IOPENR_GPIODEN_Pos) /*!< 0x00000008 */
4377#define RCC_IOPENR_GPIODEN RCC_IOPENR_GPIODEN_Msk
4378#define RCC_IOPENR_GPIOFEN_Pos (5U)
4379#define RCC_IOPENR_GPIOFEN_Msk (0x1UL << RCC_IOPENR_GPIOFEN_Pos) /*!< 0x00000020 */
4380#define RCC_IOPENR_GPIOFEN RCC_IOPENR_GPIOFEN_Msk
4381
4382/******************** Bit definition for RCC_AHBENR register ****************/
4383#define RCC_AHBENR_DMA1EN_Pos (0U)
4384#define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
4385#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk
4386#define RCC_AHBENR_FLASHEN_Pos (8U)
4387#define RCC_AHBENR_FLASHEN_Msk (0x1UL << RCC_AHBENR_FLASHEN_Pos) /*!< 0x00000100 */
4388#define RCC_AHBENR_FLASHEN RCC_AHBENR_FLASHEN_Msk
4389#define RCC_AHBENR_CRCEN_Pos (12U)
4390#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
4391#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk
4392
4393/******************** Bit definition for RCC_APBENR1 register ***************/
4394#define RCC_APBENR1_TIM3EN_Pos (1U)
4395#define RCC_APBENR1_TIM3EN_Msk (0x1UL << RCC_APBENR1_TIM3EN_Pos) /*!< 0x00000002 */
4396#define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk
4397#define RCC_APBENR1_TIM6EN_Pos (4U)
4398#define RCC_APBENR1_TIM6EN_Msk (0x1UL << RCC_APBENR1_TIM6EN_Pos) /*!< 0x00000010 */
4399#define RCC_APBENR1_TIM6EN RCC_APBENR1_TIM6EN_Msk
4400#define RCC_APBENR1_TIM7EN_Pos (5U)
4401#define RCC_APBENR1_TIM7EN_Msk (0x1UL << RCC_APBENR1_TIM7EN_Pos) /*!< 0x00000020 */
4402#define RCC_APBENR1_TIM7EN RCC_APBENR1_TIM7EN_Msk
4403#define RCC_APBENR1_RTCAPBEN_Pos (10U)
4404#define RCC_APBENR1_RTCAPBEN_Msk (0x1UL << RCC_APBENR1_RTCAPBEN_Pos) /*!< 0x00000400 */
4405#define RCC_APBENR1_RTCAPBEN RCC_APBENR1_RTCAPBEN_Msk
4406#define RCC_APBENR1_WWDGEN_Pos (11U)
4407#define RCC_APBENR1_WWDGEN_Msk (0x1UL << RCC_APBENR1_WWDGEN_Pos) /*!< 0x00000800 */
4408#define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk
4409#define RCC_APBENR1_SPI2EN_Pos (14U)
4410#define RCC_APBENR1_SPI2EN_Msk (0x1UL << RCC_APBENR1_SPI2EN_Pos) /*!< 0x00004000 */
4411#define RCC_APBENR1_SPI2EN RCC_APBENR1_SPI2EN_Msk
4412#define RCC_APBENR1_USART2EN_Pos (17U)
4413#define RCC_APBENR1_USART2EN_Msk (0x1UL << RCC_APBENR1_USART2EN_Pos) /*!< 0x00020000 */
4414#define RCC_APBENR1_USART2EN RCC_APBENR1_USART2EN_Msk
4415#define RCC_APBENR1_USART3EN_Pos (18U)
4416#define RCC_APBENR1_USART3EN_Msk (0x1UL << RCC_APBENR1_USART3EN_Pos) /*!< 0x00040000 */
4417#define RCC_APBENR1_USART3EN RCC_APBENR1_USART3EN_Msk
4418#define RCC_APBENR1_USART4EN_Pos (19U)
4419#define RCC_APBENR1_USART4EN_Msk (0x1UL << RCC_APBENR1_USART4EN_Pos) /*!< 0x00080000 */
4420#define RCC_APBENR1_USART4EN RCC_APBENR1_USART4EN_Msk
4421#define RCC_APBENR1_I2C1EN_Pos (21U)
4422#define RCC_APBENR1_I2C1EN_Msk (0x1UL << RCC_APBENR1_I2C1EN_Pos) /*!< 0x00200000 */
4423#define RCC_APBENR1_I2C1EN RCC_APBENR1_I2C1EN_Msk
4424#define RCC_APBENR1_I2C2EN_Pos (22U)
4425#define RCC_APBENR1_I2C2EN_Msk (0x1UL << RCC_APBENR1_I2C2EN_Pos) /*!< 0x00400000 */
4426#define RCC_APBENR1_I2C2EN RCC_APBENR1_I2C2EN_Msk
4427#define RCC_APBENR1_DBGEN_Pos (27U)
4428#define RCC_APBENR1_DBGEN_Msk (0x1UL << RCC_APBENR1_DBGEN_Pos) /*!< 0x08000000 */
4429#define RCC_APBENR1_DBGEN RCC_APBENR1_DBGEN_Msk
4430#define RCC_APBENR1_PWREN_Pos (28U)
4431#define RCC_APBENR1_PWREN_Msk (0x1UL << RCC_APBENR1_PWREN_Pos) /*!< 0x10000000 */
4432#define RCC_APBENR1_PWREN RCC_APBENR1_PWREN_Msk
4433
4434/******************** Bit definition for RCC_APBENR2 register **************/
4435#define RCC_APBENR2_SYSCFGEN_Pos (0U)
4436#define RCC_APBENR2_SYSCFGEN_Msk (0x1UL << RCC_APBENR2_SYSCFGEN_Pos) /*!< 0x00000001 */
4437#define RCC_APBENR2_SYSCFGEN RCC_APBENR2_SYSCFGEN_Msk
4438#define RCC_APBENR2_TIM1EN_Pos (11U)
4439#define RCC_APBENR2_TIM1EN_Msk (0x1UL << RCC_APBENR2_TIM1EN_Pos) /*!< 0x00000800 */
4440#define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk
4441#define RCC_APBENR2_SPI1EN_Pos (12U)
4442#define RCC_APBENR2_SPI1EN_Msk (0x1UL << RCC_APBENR2_SPI1EN_Pos) /*!< 0x00001000 */
4443#define RCC_APBENR2_SPI1EN RCC_APBENR2_SPI1EN_Msk
4444#define RCC_APBENR2_USART1EN_Pos (14U)
4445#define RCC_APBENR2_USART1EN_Msk (0x1UL << RCC_APBENR2_USART1EN_Pos) /*!< 0x00004000 */
4446#define RCC_APBENR2_USART1EN RCC_APBENR2_USART1EN_Msk
4447#define RCC_APBENR2_TIM14EN_Pos (15U)
4448#define RCC_APBENR2_TIM14EN_Msk (0x1UL << RCC_APBENR2_TIM14EN_Pos) /*!< 0x00008000 */
4449#define RCC_APBENR2_TIM14EN RCC_APBENR2_TIM14EN_Msk
4450#define RCC_APBENR2_TIM15EN_Pos (16U)
4451#define RCC_APBENR2_TIM15EN_Msk (0x1UL << RCC_APBENR2_TIM15EN_Pos) /*!< 0x00010000 */
4452#define RCC_APBENR2_TIM15EN RCC_APBENR2_TIM15EN_Msk
4453#define RCC_APBENR2_TIM16EN_Pos (17U)
4454#define RCC_APBENR2_TIM16EN_Msk (0x1UL << RCC_APBENR2_TIM16EN_Pos) /*!< 0x00020000 */
4455#define RCC_APBENR2_TIM16EN RCC_APBENR2_TIM16EN_Msk
4456#define RCC_APBENR2_TIM17EN_Pos (18U)
4457#define RCC_APBENR2_TIM17EN_Msk (0x1UL << RCC_APBENR2_TIM17EN_Pos) /*!< 0x00040000 */
4458#define RCC_APBENR2_TIM17EN RCC_APBENR2_TIM17EN_Msk
4459#define RCC_APBENR2_ADCEN_Pos (20U)
4460#define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos) /*!< 0x00100000 */
4461#define RCC_APBENR2_ADCEN RCC_APBENR2_ADCEN_Msk
4462
4463/******************** Bit definition for RCC_IOPSMENR register *************/
4464#define RCC_IOPSMENR_GPIOASMEN_Pos (0U)
4465#define RCC_IOPSMENR_GPIOASMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
4466#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_GPIOASMEN_Msk
4467#define RCC_IOPSMENR_GPIOBSMEN_Pos (1U)
4468#define RCC_IOPSMENR_GPIOBSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
4469#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_GPIOBSMEN_Msk
4470#define RCC_IOPSMENR_GPIOCSMEN_Pos (2U)
4471#define RCC_IOPSMENR_GPIOCSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
4472#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_GPIOCSMEN_Msk
4473#define RCC_IOPSMENR_GPIODSMEN_Pos (3U)
4474#define RCC_IOPSMENR_GPIODSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIODSMEN_Pos) /*!< 0x00000008 */
4475#define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_GPIODSMEN_Msk
4476#define RCC_IOPSMENR_GPIOFSMEN_Pos (5U)
4477#define RCC_IOPSMENR_GPIOFSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOFSMEN_Pos) /*!< 0x00000020 */
4478#define RCC_IOPSMENR_GPIOFSMEN RCC_IOPSMENR_GPIOFSMEN_Msk
4479
4480/******************** Bit definition for RCC_AHBSMENR register *************/
4481#define RCC_AHBSMENR_DMA1SMEN_Pos (0U)
4482#define RCC_AHBSMENR_DMA1SMEN_Msk (0x1UL << RCC_AHBSMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
4483#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMA1SMEN_Msk
4484#define RCC_AHBSMENR_FLASHSMEN_Pos (8U)
4485#define RCC_AHBSMENR_FLASHSMEN_Msk (0x1UL << RCC_AHBSMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
4486#define RCC_AHBSMENR_FLASHSMEN RCC_AHBSMENR_FLASHSMEN_Msk
4487#define RCC_AHBSMENR_SRAMSMEN_Pos (9U)
4488#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */
4489#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk
4490#define RCC_AHBSMENR_CRCSMEN_Pos (12U)
4491#define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */
4492#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk
4493
4494/******************** Bit definition for RCC_APBSMENR1 register *************/
4495#define RCC_APBSMENR1_TIM3SMEN_Pos (1U)
4496#define RCC_APBSMENR1_TIM3SMEN_Msk (0x1UL << RCC_APBSMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */
4497#define RCC_APBSMENR1_TIM3SMEN RCC_APBSMENR1_TIM3SMEN_Msk
4498#define RCC_APBSMENR1_TIM6SMEN_Pos (4U)
4499#define RCC_APBSMENR1_TIM6SMEN_Msk (0x1UL << RCC_APBSMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
4500#define RCC_APBSMENR1_TIM6SMEN RCC_APBSMENR1_TIM6SMEN_Msk
4501#define RCC_APBSMENR1_TIM7SMEN_Pos (5U)
4502#define RCC_APBSMENR1_TIM7SMEN_Msk (0x1UL << RCC_APBSMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */
4503#define RCC_APBSMENR1_TIM7SMEN RCC_APBSMENR1_TIM7SMEN_Msk
4504#define RCC_APBSMENR1_RTCAPBSMEN_Pos (10U)
4505#define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
4506#define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk
4507#define RCC_APBSMENR1_WWDGSMEN_Pos (11U)
4508#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
4509#define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk
4510#define RCC_APBSMENR1_SPI2SMEN_Pos (14U)
4511#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
4512#define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk
4513#define RCC_APBSMENR1_USART2SMEN_Pos (17U)
4514#define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
4515#define RCC_APBSMENR1_USART2SMEN RCC_APBSMENR1_USART2SMEN_Msk
4516#define RCC_APBSMENR1_USART3SMEN_Pos (18U)
4517#define RCC_APBSMENR1_USART3SMEN_Msk (0x1UL << RCC_APBSMENR1_USART3SMEN_Pos) /*!< 0x00040000 */
4518#define RCC_APBSMENR1_USART3SMEN RCC_APBSMENR1_USART3SMEN_Msk
4519#define RCC_APBSMENR1_USART4SMEN_Pos (19U)
4520#define RCC_APBSMENR1_USART4SMEN_Msk (0x1UL << RCC_APBSMENR1_USART4SMEN_Pos) /*!< 0x00080000 */
4521#define RCC_APBSMENR1_USART4SMEN RCC_APBSMENR1_USART4SMEN_Msk
4522#define RCC_APBSMENR1_I2C1SMEN_Pos (21U)
4523#define RCC_APBSMENR1_I2C1SMEN_Msk (0x1UL << RCC_APBSMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
4524#define RCC_APBSMENR1_I2C1SMEN RCC_APBSMENR1_I2C1SMEN_Msk
4525#define RCC_APBSMENR1_I2C2SMEN_Pos (22U)
4526#define RCC_APBSMENR1_I2C2SMEN_Msk (0x1UL << RCC_APBSMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */
4527#define RCC_APBSMENR1_I2C2SMEN RCC_APBSMENR1_I2C2SMEN_Msk
4528#define RCC_APBSMENR1_DBGSMEN_Pos (27U)
4529#define RCC_APBSMENR1_DBGSMEN_Msk (0x1UL << RCC_APBSMENR1_DBGSMEN_Pos) /*!< 0x08000000 */
4530#define RCC_APBSMENR1_DBGSMEN RCC_APBSMENR1_DBGSMEN_Msk
4531#define RCC_APBSMENR1_PWRSMEN_Pos (28U)
4532#define RCC_APBSMENR1_PWRSMEN_Msk (0x1UL << RCC_APBSMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
4533#define RCC_APBSMENR1_PWRSMEN RCC_APBSMENR1_PWRSMEN_Msk
4534
4535/******************** Bit definition for RCC_APBSMENR2 register *************/
4536#define RCC_APBSMENR2_SYSCFGSMEN_Pos (0U)
4537#define RCC_APBSMENR2_SYSCFGSMEN_Msk (0x1UL << RCC_APBSMENR2_SYSCFGSMEN_Pos) /*!< 0x00000001 */
4538#define RCC_APBSMENR2_SYSCFGSMEN RCC_APBSMENR2_SYSCFGSMEN_Msk
4539#define RCC_APBSMENR2_TIM1SMEN_Pos (11U)
4540#define RCC_APBSMENR2_TIM1SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM1SMEN_Pos) /*!< 0x00000800 */
4541#define RCC_APBSMENR2_TIM1SMEN RCC_APBSMENR2_TIM1SMEN_Msk
4542#define RCC_APBSMENR2_SPI1SMEN_Pos (12U)
4543#define RCC_APBSMENR2_SPI1SMEN_Msk (0x1UL << RCC_APBSMENR2_SPI1SMEN_Pos) /*!< 0x00001000 */
4544#define RCC_APBSMENR2_SPI1SMEN RCC_APBSMENR2_SPI1SMEN_Msk
4545#define RCC_APBSMENR2_USART1SMEN_Pos (14U)
4546#define RCC_APBSMENR2_USART1SMEN_Msk (0x1UL << RCC_APBSMENR2_USART1SMEN_Pos) /*!< 0x00004000 */
4547#define RCC_APBSMENR2_USART1SMEN RCC_APBSMENR2_USART1SMEN_Msk
4548#define RCC_APBSMENR2_TIM14SMEN_Pos (15U)
4549#define RCC_APBSMENR2_TIM14SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM14SMEN_Pos) /*!< 0x00008000 */
4550#define RCC_APBSMENR2_TIM14SMEN RCC_APBSMENR2_TIM14SMEN_Msk
4551#define RCC_APBSMENR2_TIM15SMEN_Pos (16U)
4552#define RCC_APBSMENR2_TIM15SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM15SMEN_Pos) /*!< 0x00010000 */
4553#define RCC_APBSMENR2_TIM15SMEN RCC_APBSMENR2_TIM15SMEN_Msk
4554#define RCC_APBSMENR2_TIM16SMEN_Pos (17U)
4555#define RCC_APBSMENR2_TIM16SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM16SMEN_Pos) /*!< 0x00020000 */
4556#define RCC_APBSMENR2_TIM16SMEN RCC_APBSMENR2_TIM16SMEN_Msk
4557#define RCC_APBSMENR2_TIM17SMEN_Pos (18U)
4558#define RCC_APBSMENR2_TIM17SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM17SMEN_Pos) /*!< 0x00040000 */
4559#define RCC_APBSMENR2_TIM17SMEN RCC_APBSMENR2_TIM17SMEN_Msk
4560#define RCC_APBSMENR2_ADCSMEN_Pos (20U)
4561#define RCC_APBSMENR2_ADCSMEN_Msk (0x1UL << RCC_APBSMENR2_ADCSMEN_Pos) /*!< 0x00100000 */
4562#define RCC_APBSMENR2_ADCSMEN RCC_APBSMENR2_ADCSMEN_Msk
4563
4564/******************** Bit definition for RCC_CCIPR register ******************/
4565#define RCC_CCIPR_USART1SEL_Pos (0U)
4566#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
4567#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
4568#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
4569#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
4570
4571#define RCC_CCIPR_USART2SEL_Pos (2U)
4572#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
4573#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
4574#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
4575#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
4576
4577
4578
4579#define RCC_CCIPR_I2C1SEL_Pos (12U)
4580#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
4581#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
4582#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
4583#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
4584
4585#define RCC_CCIPR_I2S1SEL_Pos (14U)
4586#define RCC_CCIPR_I2S1SEL_Msk (0x3UL << RCC_CCIPR_I2S1SEL_Pos) /*!< 0x0000C000 */
4587#define RCC_CCIPR_I2S1SEL RCC_CCIPR_I2S1SEL_Msk
4588#define RCC_CCIPR_I2S1SEL_0 (0x1UL << RCC_CCIPR_I2S1SEL_Pos) /*!< 0x00004000 */
4589#define RCC_CCIPR_I2S1SEL_1 (0x2UL << RCC_CCIPR_I2S1SEL_Pos) /*!< 0x00008000 */
4590
4591
4592
4593
4594#define RCC_CCIPR_ADCSEL_Pos (30U)
4595#define RCC_CCIPR_ADCSEL_Msk (0x3UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0xC0000000 */
4596#define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk
4597#define RCC_CCIPR_ADCSEL_0 (0x1UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x40000000 */
4598#define RCC_CCIPR_ADCSEL_1 (0x2UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x80000000 */
4599
4600/******************** Bit definition for RCC_BDCR register ******************/
4601#define RCC_BDCR_LSEON_Pos (0U)
4602#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
4603#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
4604#define RCC_BDCR_LSERDY_Pos (1U)
4605#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
4606#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
4607#define RCC_BDCR_LSEBYP_Pos (2U)
4608#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
4609#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
4610
4611#define RCC_BDCR_LSEDRV_Pos (3U)
4612#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
4613#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
4614#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
4615#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
4616
4617#define RCC_BDCR_LSECSSON_Pos (5U)
4618#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
4619#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
4620#define RCC_BDCR_LSECSSD_Pos (6U)
4621#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
4622#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
4623
4624#define RCC_BDCR_RTCSEL_Pos (8U)
4625#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
4626#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
4627#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
4628#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
4629
4630#define RCC_BDCR_RTCEN_Pos (15U)
4631#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
4632#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
4633#define RCC_BDCR_BDRST_Pos (16U)
4634#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
4635#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
4636
4637#define RCC_BDCR_LSCOEN_Pos (24U)
4638#define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
4639#define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
4640#define RCC_BDCR_LSCOSEL_Pos (25U)
4641#define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
4642#define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
4643
4644/******************** Bit definition for RCC_CSR register *******************/
4645#define RCC_CSR_LSION_Pos (0U)
4646#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
4647#define RCC_CSR_LSION RCC_CSR_LSION_Msk
4648#define RCC_CSR_LSIRDY_Pos (1U)
4649#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
4650#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
4651
4652#define RCC_CSR_RMVF_Pos (23U)
4653#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
4654#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
4655#define RCC_CSR_OBLRSTF_Pos (25U)
4656#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
4657#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
4658#define RCC_CSR_PINRSTF_Pos (26U)
4659#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
4660#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
4661#define RCC_CSR_PWRRSTF_Pos (27U)
4662#define RCC_CSR_PWRRSTF_Msk (0x1UL << RCC_CSR_PWRRSTF_Pos) /*!< 0x08000000 */
4663#define RCC_CSR_PWRRSTF RCC_CSR_PWRRSTF_Msk
4664#define RCC_CSR_SFTRSTF_Pos (28U)
4665#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
4666#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
4667#define RCC_CSR_IWDGRSTF_Pos (29U)
4668#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
4669#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
4670#define RCC_CSR_WWDGRSTF_Pos (30U)
4671#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
4672#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
4673#define RCC_CSR_LPWRRSTF_Pos (31U)
4674#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
4675#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
4676
4677/******************************************************************************/
4678/* */
4679/* Real-Time Clock (RTC) */
4680/* */
4681/******************************************************************************/
4682/*
4683* @brief Specific device feature definitions
4684*/
4685#define RTC_WAKEUP_SUPPORT
4686#define RTC_BACKUP_SUPPORT
4687
4688/******************** Bits definition for RTC_TR register *******************/
4689#define RTC_TR_PM_Pos (22U)
4690#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
4691#define RTC_TR_PM RTC_TR_PM_Msk
4692#define RTC_TR_HT_Pos (20U)
4693#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
4694#define RTC_TR_HT RTC_TR_HT_Msk
4695#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
4696#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
4697#define RTC_TR_HU_Pos (16U)
4698#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
4699#define RTC_TR_HU RTC_TR_HU_Msk
4700#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
4701#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
4702#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
4703#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
4704#define RTC_TR_MNT_Pos (12U)
4705#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
4706#define RTC_TR_MNT RTC_TR_MNT_Msk
4707#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
4708#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
4709#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
4710#define RTC_TR_MNU_Pos (8U)
4711#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
4712#define RTC_TR_MNU RTC_TR_MNU_Msk
4713#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
4714#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
4715#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
4716#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
4717#define RTC_TR_ST_Pos (4U)
4718#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
4719#define RTC_TR_ST RTC_TR_ST_Msk
4720#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
4721#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
4722#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
4723#define RTC_TR_SU_Pos (0U)
4724#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
4725#define RTC_TR_SU RTC_TR_SU_Msk
4726#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
4727#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
4728#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
4729#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
4730
4731/******************** Bits definition for RTC_DR register *******************/
4732#define RTC_DR_YT_Pos (20U)
4733#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
4734#define RTC_DR_YT RTC_DR_YT_Msk
4735#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
4736#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
4737#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
4738#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
4739#define RTC_DR_YU_Pos (16U)
4740#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
4741#define RTC_DR_YU RTC_DR_YU_Msk
4742#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
4743#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
4744#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
4745#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
4746#define RTC_DR_WDU_Pos (13U)
4747#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
4748#define RTC_DR_WDU RTC_DR_WDU_Msk
4749#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
4750#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
4751#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
4752#define RTC_DR_MT_Pos (12U)
4753#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
4754#define RTC_DR_MT RTC_DR_MT_Msk
4755#define RTC_DR_MU_Pos (8U)
4756#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
4757#define RTC_DR_MU RTC_DR_MU_Msk
4758#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
4759#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
4760#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
4761#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
4762#define RTC_DR_DT_Pos (4U)
4763#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
4764#define RTC_DR_DT RTC_DR_DT_Msk
4765#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
4766#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
4767#define RTC_DR_DU_Pos (0U)
4768#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
4769#define RTC_DR_DU RTC_DR_DU_Msk
4770#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
4771#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
4772#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
4773#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
4774
4775/******************** Bits definition for RTC_SSR register ******************/
4776#define RTC_SSR_SS_Pos (0U)
4777#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
4778#define RTC_SSR_SS RTC_SSR_SS_Msk
4779
4780/******************** Bits definition for RTC_ICSR register ******************/
4781#define RTC_ICSR_RECALPF_Pos (16U)
4782#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */
4783#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk
4784#define RTC_ICSR_INIT_Pos (7U)
4785#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */
4786#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk
4787#define RTC_ICSR_INITF_Pos (6U)
4788#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */
4789#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk
4790#define RTC_ICSR_RSF_Pos (5U)
4791#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */
4792#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk
4793#define RTC_ICSR_INITS_Pos (4U)
4794#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */
4795#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk
4796#define RTC_ICSR_SHPF_Pos (3U)
4797#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */
4798#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk
4799#define RTC_ICSR_WUTWF_Pos (2U)
4800#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */
4801#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk /*!< Wakeup timer write flag > */
4802#define RTC_ICSR_ALRBWF_Pos (1U)
4803#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */
4804#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk
4805#define RTC_ICSR_ALRAWF_Pos (0U)
4806#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */
4807#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk
4808
4809/******************** Bits definition for RTC_PRER register *****************/
4810#define RTC_PRER_PREDIV_A_Pos (16U)
4811#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
4812#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
4813#define RTC_PRER_PREDIV_S_Pos (0U)
4814#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
4815#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
4816
4817/******************** Bits definition for RTC_WUTR register *****************/
4818#define RTC_WUTR_WUT_Pos (0U)
4819#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
4820#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wakeup auto-reload value bits > */
4821
4822/******************** Bits definition for RTC_CR register *******************/
4823#define RTC_CR_OUT2EN_Pos (31U)
4824#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */
4825#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!< RTC_OUT2 output enable */
4826#define RTC_CR_TAMPALRM_TYPE_Pos (30U)
4827#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */
4828#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!< TAMPALARM output type */
4829#define RTC_CR_TAMPALRM_PU_Pos (29U)
4830#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */
4831#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!< TAMPALARM output pull-up config */
4832#define RTC_CR_TAMPOE_Pos (26U)
4833#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */
4834#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!< Tamper detection output enable on TAMPALARM */
4835#define RTC_CR_TAMPTS_Pos (25U)
4836#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */
4837#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!< Activate timestamp on tamper detection event */
4838#define RTC_CR_ITSE_Pos (24U)
4839#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
4840#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!< Timestamp on internal event enable */
4841#define RTC_CR_COE_Pos (23U)
4842#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
4843#define RTC_CR_COE RTC_CR_COE_Msk
4844#define RTC_CR_OSEL_Pos (21U)
4845#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
4846#define RTC_CR_OSEL RTC_CR_OSEL_Msk
4847#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
4848#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
4849#define RTC_CR_POL_Pos (20U)
4850#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
4851#define RTC_CR_POL RTC_CR_POL_Msk
4852#define RTC_CR_COSEL_Pos (19U)
4853#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
4854#define RTC_CR_COSEL RTC_CR_COSEL_Msk
4855#define RTC_CR_BKP_Pos (18U)
4856#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
4857#define RTC_CR_BKP RTC_CR_BKP_Msk
4858#define RTC_CR_SUB1H_Pos (17U)
4859#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
4860#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
4861#define RTC_CR_ADD1H_Pos (16U)
4862#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
4863#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
4864#define RTC_CR_TSIE_Pos (15U)
4865#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
4866#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable > */
4867#define RTC_CR_WUTIE_Pos (14U)
4868#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
4869#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wakeup timer interrupt enable > */
4870#define RTC_CR_ALRBIE_Pos (13U)
4871#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
4872#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
4873#define RTC_CR_ALRAIE_Pos (12U)
4874#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
4875#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
4876#define RTC_CR_TSE_Pos (11U)
4877#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
4878#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable > */
4879#define RTC_CR_WUTE_Pos (10U)
4880#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
4881#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wakeup timer enable > */
4882#define RTC_CR_ALRBE_Pos (9U)
4883#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
4884#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
4885#define RTC_CR_ALRAE_Pos (8U)
4886#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
4887#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
4888#define RTC_CR_FMT_Pos (6U)
4889#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
4890#define RTC_CR_FMT RTC_CR_FMT_Msk
4891#define RTC_CR_BYPSHAD_Pos (5U)
4892#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
4893#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
4894#define RTC_CR_REFCKON_Pos (4U)
4895#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
4896#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
4897#define RTC_CR_TSEDGE_Pos (3U)
4898#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
4899#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge > */
4900#define RTC_CR_WUCKSEL_Pos (0U)
4901#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
4902#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< Wakeup clock selection > */
4903#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
4904#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
4905#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
4906
4907/******************** Bits definition for RTC_WPR register ******************/
4908#define RTC_WPR_KEY_Pos (0U)
4909#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
4910#define RTC_WPR_KEY RTC_WPR_KEY_Msk
4911
4912/******************** Bits definition for RTC_CALR register *****************/
4913#define RTC_CALR_CALP_Pos (15U)
4914#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
4915#define RTC_CALR_CALP RTC_CALR_CALP_Msk
4916#define RTC_CALR_CALW8_Pos (14U)
4917#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
4918#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
4919#define RTC_CALR_CALW16_Pos (13U)
4920#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
4921#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
4922#define RTC_CALR_CALM_Pos (0U)
4923#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
4924#define RTC_CALR_CALM RTC_CALR_CALM_Msk
4925#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
4926#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
4927#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
4928#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
4929#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
4930#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
4931#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
4932#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
4933#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
4934
4935/******************** Bits definition for RTC_SHIFTR register ***************/
4936#define RTC_SHIFTR_SUBFS_Pos (0U)
4937#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
4938#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
4939#define RTC_SHIFTR_ADD1S_Pos (31U)
4940#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
4941#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
4942
4943/******************** Bits definition for RTC_TSTR register *****************/
4944#define RTC_TSTR_PM_Pos (22U)
4945#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
4946#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< AM-PM notation > */
4947#define RTC_TSTR_HT_Pos (20U)
4948#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
4949#define RTC_TSTR_HT RTC_TSTR_HT_Msk
4950#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
4951#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
4952#define RTC_TSTR_HU_Pos (16U)
4953#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
4954#define RTC_TSTR_HU RTC_TSTR_HU_Msk
4955#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
4956#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
4957#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
4958#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
4959#define RTC_TSTR_MNT_Pos (12U)
4960#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
4961#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
4962#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
4963#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
4964#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
4965#define RTC_TSTR_MNU_Pos (8U)
4966#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
4967#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
4968#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
4969#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
4970#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
4971#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
4972#define RTC_TSTR_ST_Pos (4U)
4973#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
4974#define RTC_TSTR_ST RTC_TSTR_ST_Msk
4975#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
4976#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
4977#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
4978#define RTC_TSTR_SU_Pos (0U)
4979#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
4980#define RTC_TSTR_SU RTC_TSTR_SU_Msk
4981#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
4982#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
4983#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
4984#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
4985
4986/******************** Bits definition for RTC_TSDR register *****************/
4987#define RTC_TSDR_WDU_Pos (13U)
4988#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
4989#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Week day units > */
4990#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
4991#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
4992#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
4993#define RTC_TSDR_MT_Pos (12U)
4994#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
4995#define RTC_TSDR_MT RTC_TSDR_MT_Msk
4996#define RTC_TSDR_MU_Pos (8U)
4997#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
4998#define RTC_TSDR_MU RTC_TSDR_MU_Msk
4999#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
5000#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
5001#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
5002#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
5003#define RTC_TSDR_DT_Pos (4U)
5004#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
5005#define RTC_TSDR_DT RTC_TSDR_DT_Msk
5006#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
5007#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
5008#define RTC_TSDR_DU_Pos (0U)
5009#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
5010#define RTC_TSDR_DU RTC_TSDR_DU_Msk
5011#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
5012#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
5013#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
5014#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
5015
5016/******************** Bits definition for RTC_TSSSR register ****************/
5017#define RTC_TSSSR_SS_Pos (0U)
5018#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
5019#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Sub second value > */
5020
5021/******************** Bits definition for RTC_ALRMAR register ***************/
5022#define RTC_ALRMAR_MSK4_Pos (31U)
5023#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
5024#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
5025#define RTC_ALRMAR_WDSEL_Pos (30U)
5026#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
5027#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
5028#define RTC_ALRMAR_DT_Pos (28U)
5029#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
5030#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
5031#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
5032#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
5033#define RTC_ALRMAR_DU_Pos (24U)
5034#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
5035#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
5036#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
5037#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
5038#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
5039#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
5040#define RTC_ALRMAR_MSK3_Pos (23U)
5041#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
5042#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
5043#define RTC_ALRMAR_PM_Pos (22U)
5044#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
5045#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
5046#define RTC_ALRMAR_HT_Pos (20U)
5047#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
5048#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
5049#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
5050#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
5051#define RTC_ALRMAR_HU_Pos (16U)
5052#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
5053#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
5054#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
5055#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
5056#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
5057#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
5058#define RTC_ALRMAR_MSK2_Pos (15U)
5059#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
5060#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
5061#define RTC_ALRMAR_MNT_Pos (12U)
5062#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
5063#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
5064#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
5065#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
5066#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
5067#define RTC_ALRMAR_MNU_Pos (8U)
5068#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
5069#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
5070#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
5071#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
5072#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
5073#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
5074#define RTC_ALRMAR_MSK1_Pos (7U)
5075#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
5076#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
5077#define RTC_ALRMAR_ST_Pos (4U)
5078#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
5079#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
5080#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
5081#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
5082#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
5083#define RTC_ALRMAR_SU_Pos (0U)
5084#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
5085#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
5086#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
5087#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
5088#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
5089#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
5090
5091/******************** Bits definition for RTC_ALRMASSR register *************/
5092#define RTC_ALRMASSR_MASKSS_Pos (24U)
5093#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
5094#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
5095#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
5096#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
5097#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
5098#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
5099#define RTC_ALRMASSR_SS_Pos (0U)
5100#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
5101#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
5102
5103/******************** Bits definition for RTC_ALRMBR register ***************/
5104#define RTC_ALRMBR_MSK4_Pos (31U)
5105#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
5106#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
5107#define RTC_ALRMBR_WDSEL_Pos (30U)
5108#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
5109#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
5110#define RTC_ALRMBR_DT_Pos (28U)
5111#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
5112#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
5113#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
5114#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
5115#define RTC_ALRMBR_DU_Pos (24U)
5116#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
5117#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
5118#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
5119#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
5120#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
5121#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
5122#define RTC_ALRMBR_MSK3_Pos (23U)
5123#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
5124#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
5125#define RTC_ALRMBR_PM_Pos (22U)
5126#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
5127#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
5128#define RTC_ALRMBR_HT_Pos (20U)
5129#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
5130#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
5131#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
5132#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
5133#define RTC_ALRMBR_HU_Pos (16U)
5134#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
5135#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
5136#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
5137#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
5138#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
5139#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
5140#define RTC_ALRMBR_MSK2_Pos (15U)
5141#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
5142#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
5143#define RTC_ALRMBR_MNT_Pos (12U)
5144#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
5145#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
5146#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
5147#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
5148#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
5149#define RTC_ALRMBR_MNU_Pos (8U)
5150#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
5151#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
5152#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
5153#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
5154#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
5155#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
5156#define RTC_ALRMBR_MSK1_Pos (7U)
5157#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
5158#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
5159#define RTC_ALRMBR_ST_Pos (4U)
5160#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
5161#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
5162#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
5163#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
5164#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
5165#define RTC_ALRMBR_SU_Pos (0U)
5166#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
5167#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
5168#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
5169#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
5170#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
5171#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
5172
5173/******************** Bits definition for RTC_ALRMASSR register *************/
5174#define RTC_ALRMBSSR_MASKSS_Pos (24U)
5175#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
5176#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
5177#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
5178#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
5179#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
5180#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
5181#define RTC_ALRMBSSR_SS_Pos (0U)
5182#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
5183#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
5184
5185/******************** Bits definition for RTC_SR register *******************/
5186#define RTC_SR_ITSF_Pos (5U)
5187#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */
5188#define RTC_SR_ITSF RTC_SR_ITSF_Msk
5189#define RTC_SR_TSOVF_Pos (4U)
5190#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */
5191#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk /*!< Timestamp overflow flag > */
5192#define RTC_SR_TSF_Pos (3U)
5193#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */
5194#define RTC_SR_TSF RTC_SR_TSF_Msk /*!< Timestamp flag > */
5195#define RTC_SR_WUTF_Pos (2U)
5196#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */
5197#define RTC_SR_WUTF RTC_SR_WUTF_Msk /*!< Wakeup timer flag > */
5198#define RTC_SR_ALRBF_Pos (1U)
5199#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */
5200#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk
5201#define RTC_SR_ALRAF_Pos (0U)
5202#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */
5203#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk
5204
5205/******************** Bits definition for RTC_MISR register *****************/
5206#define RTC_MISR_ITSMF_Pos (5U)
5207#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */
5208#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk
5209#define RTC_MISR_TSOVMF_Pos (4U)
5210#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */
5211#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk /*!< Timestamp overflow masked flag > */
5212#define RTC_MISR_TSMF_Pos (3U)
5213#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */
5214#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk /*!< Timestamp masked flag > */
5215#define RTC_MISR_WUTMF_Pos (2U)
5216#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */
5217#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk /*!< Wakeup timer masked flag > */
5218#define RTC_MISR_ALRBMF_Pos (1U)
5219#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */
5220#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk
5221#define RTC_MISR_ALRAMF_Pos (0U)
5222#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */
5223#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk
5224
5225/******************** Bits definition for RTC_SCR register ******************/
5226#define RTC_SCR_CITSF_Pos (5U)
5227#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */
5228#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk
5229#define RTC_SCR_CTSOVF_Pos (4U)
5230#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */
5231#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk /*!< Clear timestamp overflow flag > */
5232#define RTC_SCR_CTSF_Pos (3U)
5233#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */
5234#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk /*!< Clear timestamp flag > */
5235#define RTC_SCR_CWUTF_Pos (2U)
5236#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */
5237#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk /*!< Clear wakeup timer flag > */
5238#define RTC_SCR_CALRBF_Pos (1U)
5239#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */
5240#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk
5241#define RTC_SCR_CALRAF_Pos (0U)
5242#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
5243#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
5244
5245
5246/******************************************************************************/
5247/* */
5248/* Tamper and backup register (TAMP) */
5249/* */
5250/******************************************************************************/
5251/******************** Bits definition for TAMP_CR1 register *****************/
5252#define TAMP_CR1_TAMP1E_Pos (0U)
5253#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */
5254#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk
5255#define TAMP_CR1_TAMP2E_Pos (1U)
5256#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */
5257#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk
5258#define TAMP_CR1_ITAMP3E_Pos (18U)
5259#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */
5260#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk
5261#define TAMP_CR1_ITAMP4E_Pos (19U)
5262#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */
5263#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk
5264#define TAMP_CR1_ITAMP5E_Pos (20U)
5265#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */
5266#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk
5267#define TAMP_CR1_ITAMP6E_Pos (21U)
5268#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */
5269#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk
5270
5271/******************** Bits definition for TAMP_CR2 register *****************/
5272#define TAMP_CR2_TAMP1NOERASE_Pos (0U)
5273#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */
5274#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk
5275#define TAMP_CR2_TAMP2NOERASE_Pos (1U)
5276#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */
5277#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk
5278#define TAMP_CR2_TAMP1MSK_Pos (16U)
5279#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */
5280#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk
5281#define TAMP_CR2_TAMP2MSK_Pos (17U)
5282#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */
5283#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk
5284#define TAMP_CR2_TAMP1TRG_Pos (24U)
5285#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */
5286#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk
5287#define TAMP_CR2_TAMP2TRG_Pos (25U)
5288#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */
5289#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk
5290
5291/******************** Bits definition for TAMP_FLTCR register ***************/
5292#define TAMP_FLTCR_TAMPFREQ_0 0x00000001U
5293#define TAMP_FLTCR_TAMPFREQ_1 0x00000002U
5294#define TAMP_FLTCR_TAMPFREQ_2 0x00000004U
5295#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
5296#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
5297#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
5298#define TAMP_FLTCR_TAMPFLT_0 0x00000008U
5299#define TAMP_FLTCR_TAMPFLT_1 0x00000010U
5300#define TAMP_FLTCR_TAMPFLT_Pos (3U)
5301#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
5302#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
5303#define TAMP_FLTCR_TAMPPRCH_0 0x00000020U
5304#define TAMP_FLTCR_TAMPPRCH_1 0x00000040U
5305#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
5306#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
5307#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
5308#define TAMP_FLTCR_TAMPPUDIS_Pos (7U)
5309#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */
5310#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk
5311
5312/******************** Bits definition for TAMP_IER register *****************/
5313#define TAMP_IER_TAMP1IE_Pos (0U)
5314#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */
5315#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk
5316#define TAMP_IER_TAMP2IE_Pos (1U)
5317#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */
5318#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk
5319#define TAMP_IER_ITAMP3IE_Pos (18U)
5320#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */
5321#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk
5322#define TAMP_IER_ITAMP4IE_Pos (19U)
5323#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */
5324#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk
5325#define TAMP_IER_ITAMP5IE_Pos (20U)
5326#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */
5327#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk
5328#define TAMP_IER_ITAMP6IE_Pos (21U)
5329#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */
5330#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk
5331
5332/******************** Bits definition for TAMP_SR register ******************/
5333#define TAMP_SR_TAMP1F_Pos (0U)
5334#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */
5335#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk
5336#define TAMP_SR_TAMP2F_Pos (1U)
5337#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */
5338#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk
5339#define TAMP_SR_ITAMP3F_Pos (18U)
5340#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */
5341#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk
5342#define TAMP_SR_ITAMP4F_Pos (19U)
5343#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */
5344#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk
5345#define TAMP_SR_ITAMP5F_Pos (20U)
5346#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */
5347#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk
5348#define TAMP_SR_ITAMP6F_Pos (21U)
5349#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */
5350#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk
5351
5352/******************** Bits definition for TAMP_MISR register ****************/
5353#define TAMP_MISR_TAMP1MF_Pos (0U)
5354#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */
5355#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk
5356#define TAMP_MISR_TAMP2MF_Pos (1U)
5357#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */
5358#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk
5359#define TAMP_MISR_ITAMP3MF_Pos (18U)
5360#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */
5361#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk
5362#define TAMP_MISR_ITAMP4MF_Pos (19U)
5363#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */
5364#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk
5365#define TAMP_MISR_ITAMP5MF_Pos (20U)
5366#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */
5367#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk
5368#define TAMP_MISR_ITAMP6MF_Pos (21U)
5369#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */
5370#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk
5371
5372/******************** Bits definition for TAMP_SCR register *****************/
5373#define TAMP_SCR_CTAMP1F_Pos (0U)
5374#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */
5375#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk
5376#define TAMP_SCR_CTAMP2F_Pos (1U)
5377#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */
5378#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk
5379#define TAMP_SCR_CITAMP3F_Pos (18U)
5380#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */
5381#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk
5382#define TAMP_SCR_CITAMP4F_Pos (19U)
5383#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */
5384#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk
5385#define TAMP_SCR_CITAMP5F_Pos (20U)
5386#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */
5387#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk
5388#define TAMP_SCR_CITAMP6F_Pos (21U)
5389#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */
5390#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk
5391
5392/******************** Bits definition for TAMP_BKP0R register ***************/
5393#define TAMP_BKP0R_Pos (0U)
5394#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */
5395#define TAMP_BKP0R TAMP_BKP0R_Msk
5396
5397/******************** Bits definition for TAMP_BKP1R register ***************/
5398#define TAMP_BKP1R_Pos (0U)
5399#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */
5400#define TAMP_BKP1R TAMP_BKP1R_Msk
5401
5402/******************** Bits definition for TAMP_BKP2R register ***************/
5403#define TAMP_BKP2R_Pos (0U)
5404#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */
5405#define TAMP_BKP2R TAMP_BKP2R_Msk
5406
5407/******************** Bits definition for TAMP_BKP3R register ***************/
5408#define TAMP_BKP3R_Pos (0U)
5409#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */
5410#define TAMP_BKP3R TAMP_BKP3R_Msk
5411
5412/******************** Bits definition for TAMP_BKP4R register ***************/
5413#define TAMP_BKP4R_Pos (0U)
5414#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
5415#define TAMP_BKP4R TAMP_BKP4R_Msk
5416
5417
5418/******************************************************************************/
5419/* */
5420/* Serial Peripheral Interface (SPI) */
5421/* */
5422/******************************************************************************/
5423/*
5424 * @brief Specific device feature definitions (not present on all devices in the STM32G0 serie)
5425 */
5426#define SPI_I2S_SUPPORT /*!< I2S support */
5427
5428/******************* Bit definition for SPI_CR1 register ********************/
5429#define SPI_CR1_CPHA_Pos (0U)
5430#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
5431#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
5432#define SPI_CR1_CPOL_Pos (1U)
5433#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
5434#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
5435#define SPI_CR1_MSTR_Pos (2U)
5436#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
5437#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
5438
5439#define SPI_CR1_BR_Pos (3U)
5440#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
5441#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
5442#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
5443#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
5444#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
5445
5446#define SPI_CR1_SPE_Pos (6U)
5447#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
5448#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
5449#define SPI_CR1_LSBFIRST_Pos (7U)
5450#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
5451#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
5452#define SPI_CR1_SSI_Pos (8U)
5453#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
5454#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
5455#define SPI_CR1_SSM_Pos (9U)
5456#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
5457#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
5458#define SPI_CR1_RXONLY_Pos (10U)
5459#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
5460#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
5461#define SPI_CR1_CRCL_Pos (11U)
5462#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
5463#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
5464#define SPI_CR1_CRCNEXT_Pos (12U)
5465#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
5466#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
5467#define SPI_CR1_CRCEN_Pos (13U)
5468#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
5469#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
5470#define SPI_CR1_BIDIOE_Pos (14U)
5471#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
5472#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
5473#define SPI_CR1_BIDIMODE_Pos (15U)
5474#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
5475#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
5476
5477/******************* Bit definition for SPI_CR2 register ********************/
5478#define SPI_CR2_RXDMAEN_Pos (0U)
5479#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
5480#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
5481#define SPI_CR2_TXDMAEN_Pos (1U)
5482#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
5483#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
5484#define SPI_CR2_SSOE_Pos (2U)
5485#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
5486#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
5487#define SPI_CR2_NSSP_Pos (3U)
5488#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
5489#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
5490#define SPI_CR2_FRF_Pos (4U)
5491#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
5492#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
5493#define SPI_CR2_ERRIE_Pos (5U)
5494#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
5495#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
5496#define SPI_CR2_RXNEIE_Pos (6U)
5497#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
5498#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
5499#define SPI_CR2_TXEIE_Pos (7U)
5500#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
5501#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
5502#define SPI_CR2_DS_Pos (8U)
5503#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
5504#define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
5505#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */
5506#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */
5507#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */
5508#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */
5509#define SPI_CR2_FRXTH_Pos (12U)
5510#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
5511#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
5512#define SPI_CR2_LDMARX_Pos (13U)
5513#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
5514#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
5515#define SPI_CR2_LDMATX_Pos (14U)
5516#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
5517#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
5518
5519/******************** Bit definition for SPI_SR register ********************/
5520#define SPI_SR_RXNE_Pos (0U)
5521#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
5522#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
5523#define SPI_SR_TXE_Pos (1U)
5524#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
5525#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
5526#define SPI_SR_CHSIDE_Pos (2U)
5527#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
5528#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
5529#define SPI_SR_UDR_Pos (3U)
5530#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
5531#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
5532#define SPI_SR_CRCERR_Pos (4U)
5533#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
5534#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
5535#define SPI_SR_MODF_Pos (5U)
5536#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
5537#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
5538#define SPI_SR_OVR_Pos (6U)
5539#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
5540#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
5541#define SPI_SR_BSY_Pos (7U)
5542#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
5543#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
5544#define SPI_SR_FRE_Pos (8U)
5545#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
5546#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
5547#define SPI_SR_FRLVL_Pos (9U)
5548#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
5549#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
5550#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
5551#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
5552#define SPI_SR_FTLVL_Pos (11U)
5553#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
5554#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
5555#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
5556#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
5557
5558/******************** Bit definition for SPI_DR register ********************/
5559#define SPI_DR_DR_Pos (0U)
5560#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
5561#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
5562
5563/******************* Bit definition for SPI_CRCPR register ******************/
5564#define SPI_CRCPR_CRCPOLY_Pos (0U)
5565#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
5566#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
5567
5568/****************** Bit definition for SPI_RXCRCR register ******************/
5569#define SPI_RXCRCR_RXCRC_Pos (0U)
5570#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
5571#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
5572
5573/****************** Bit definition for SPI_TXCRCR register ******************/
5574#define SPI_TXCRCR_TXCRC_Pos (0U)
5575#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
5576#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
5577
5578/****************** Bit definition for SPI_I2SCFGR register *****************/
5579#define SPI_I2SCFGR_CHLEN_Pos (0U)
5580#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
5581#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
5582#define SPI_I2SCFGR_DATLEN_Pos (1U)
5583#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
5584#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
5585#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
5586#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
5587#define SPI_I2SCFGR_CKPOL_Pos (3U)
5588#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
5589#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
5590#define SPI_I2SCFGR_I2SSTD_Pos (4U)
5591#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
5592#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
5593#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
5594#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
5595#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
5596#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
5597#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
5598#define SPI_I2SCFGR_I2SCFG_Pos (8U)
5599#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
5600#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
5601#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
5602#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
5603#define SPI_I2SCFGR_I2SE_Pos (10U)
5604#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
5605#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
5606#define SPI_I2SCFGR_I2SMOD_Pos (11U)
5607#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
5608#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
5609#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
5610#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
5611#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
5612
5613/****************** Bit definition for SPI_I2SPR register *******************/
5614#define SPI_I2SPR_I2SDIV_Pos (0U)
5615#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
5616#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
5617#define SPI_I2SPR_ODD_Pos (8U)
5618#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
5619#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
5620#define SPI_I2SPR_MCKOE_Pos (9U)
5621#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
5622#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
5623
5624/******************************************************************************/
5625/* */
5626/* SYSCFG */
5627/* */
5628/******************************************************************************/
5629/***************** Bit definition for SYSCFG_CFGR1 register ****************/
5630#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
5631#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
5632#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
5633#define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
5634#define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
5635#define SYSCFG_CFGR1_PA11_RMP_Pos (3U)
5636#define SYSCFG_CFGR1_PA11_RMP_Msk (0x1UL << SYSCFG_CFGR1_PA11_RMP_Pos) /*!< 0x00000008 */
5637#define SYSCFG_CFGR1_PA11_RMP SYSCFG_CFGR1_PA11_RMP_Msk /*!< PA11 Remap */
5638#define SYSCFG_CFGR1_PA12_RMP_Pos (4U)
5639#define SYSCFG_CFGR1_PA12_RMP_Msk (0x1UL << SYSCFG_CFGR1_PA12_RMP_Pos) /*!< 0x00000010 */
5640#define SYSCFG_CFGR1_PA12_RMP SYSCFG_CFGR1_PA12_RMP_Msk /*!< PA12 Remap */
5641#define SYSCFG_CFGR1_IR_POL_Pos (5U)
5642#define SYSCFG_CFGR1_IR_POL_Msk (0x1UL << SYSCFG_CFGR1_IR_POL_Pos) /*!< 0x00000020 */
5643#define SYSCFG_CFGR1_IR_POL SYSCFG_CFGR1_IR_POL_Msk /*!< IROut Polarity Selection */
5644#define SYSCFG_CFGR1_IR_MOD_Pos (6U)
5645#define SYSCFG_CFGR1_IR_MOD_Msk (0x3UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x000000C0 */
5646#define SYSCFG_CFGR1_IR_MOD SYSCFG_CFGR1_IR_MOD_Msk /*!< IRDA Modulation Envelope signal source selection */
5647#define SYSCFG_CFGR1_IR_MOD_0 (0x1UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000040 */
5648#define SYSCFG_CFGR1_IR_MOD_1 (0x2UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000080 */
5649#define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
5650#define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
5651#define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
5652#define SYSCFG_CFGR1_UCPD1_STROBE_Pos (9U)
5653#define SYSCFG_CFGR1_UCPD1_STROBE_Msk (0x1UL << SYSCFG_CFGR1_UCPD1_STROBE_Pos) /*!< 0x00000200 */
5654#define SYSCFG_CFGR1_UCPD1_STROBE SYSCFG_CFGR1_UCPD1_STROBE_Msk /*!< Strobe signal bit for UCPD1 */
5655#define SYSCFG_CFGR1_UCPD2_STROBE_Pos (10U)
5656#define SYSCFG_CFGR1_UCPD2_STROBE_Msk (0x1UL << SYSCFG_CFGR1_UCPD2_STROBE_Pos) /*!< 0x00000400 */
5657#define SYSCFG_CFGR1_UCPD2_STROBE SYSCFG_CFGR1_UCPD2_STROBE_Msk /*!< Strobe signal bit for UCPD2 */
5658#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
5659#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
5660#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
5661#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
5662#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
5663#define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
5664#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
5665#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
5666#define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
5667#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
5668#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
5669#define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
5670#define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
5671#define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
5672#define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
5673#define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
5674#define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
5675#define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< Enable I2C2 Fast mode plus */
5676#define SYSCFG_CFGR1_I2C_PA9_FMP_Pos (22U)
5677#define SYSCFG_CFGR1_I2C_PA9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PA9_FMP_Pos) /*!< 0x00400000 */
5678#define SYSCFG_CFGR1_I2C_PA9_FMP SYSCFG_CFGR1_I2C_PA9_FMP_Msk /*!< Enable Fast Mode Plus on PA9 */
5679#define SYSCFG_CFGR1_I2C_PA10_FMP_Pos (23U)
5680#define SYSCFG_CFGR1_I2C_PA10_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PA10_FMP_Pos) /*!< 0x00800000 */
5681#define SYSCFG_CFGR1_I2C_PA10_FMP SYSCFG_CFGR1_I2C_PA10_FMP_Msk /*!< Enable Fast Mode Plus on PA10 */
5682
5683/****************** Bit definition for SYSCFG_CFGR2 register ****************/
5684#define SYSCFG_CFGR2_CLL_Pos (0U)
5685#define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
5686#define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
5687#define SYSCFG_CFGR2_SPL_Pos (1U)
5688#define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
5689#define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
5690#define SYSCFG_CFGR2_ECCL_Pos (3U)
5691#define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
5692#define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECCL */
5693#define SYSCFG_CFGR2_SPF_Pos (8U)
5694#define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
5695#define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity error flag */
5696#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SPF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
5697
5698/***************** Bit definition for SYSCFG_ITLINEx ISR Wrapper register ****************/
5699#define SYSCFG_ITLINE0_SR_EWDG_Pos (0U)
5700#define SYSCFG_ITLINE0_SR_EWDG_Msk (0x1UL << SYSCFG_ITLINE0_SR_EWDG_Pos) /*!< 0x00000001 */
5701#define SYSCFG_ITLINE0_SR_EWDG SYSCFG_ITLINE0_SR_EWDG_Msk /*!< EWDG interrupt */
5702#define SYSCFG_ITLINE2_SR_TAMPER_Pos (0U)
5703#define SYSCFG_ITLINE2_SR_TAMPER_Msk (0x1UL << SYSCFG_ITLINE2_SR_TAMPER_Pos) /*!< 0x00000001 */
5704#define SYSCFG_ITLINE2_SR_TAMPER SYSCFG_ITLINE2_SR_TAMPER_Msk /*!< TAMPER -> exti[21] interrupt */
5705#define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos (1U)
5706#define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk (0x1UL << SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos) /*!< 0x00000002 */
5707#define SYSCFG_ITLINE2_SR_RTC_WAKEUP SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk /*!< RTC_WAKEUP -> exti[19] interrupt .... */
5708#define SYSCFG_ITLINE3_SR_FLASH_ECC_Pos (0U)
5709#define SYSCFG_ITLINE3_SR_FLASH_ECC_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ECC_Pos) /*!< 0x00000001 */
5710#define SYSCFG_ITLINE3_SR_FLASH_ECC SYSCFG_ITLINE3_SR_FLASH_ECC_Msk /*!< Flash ITF ECC interrupt */
5711#define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos (1U)
5712#define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000002 */
5713#define SYSCFG_ITLINE3_SR_FLASH_ITF SYSCFG_ITLINE3_SR_FLASH_ITF_Msk /*!< FLASH ITF interrupt */
5714#define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos (0U)
5715#define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk (0x1UL << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos) /*!< 0x00000001 */
5716#define SYSCFG_ITLINE4_SR_CLK_CTRL SYSCFG_ITLINE4_SR_CLK_CTRL_Msk /*!< RCC interrupt */
5717#define SYSCFG_ITLINE5_SR_EXTI0_Pos (0U)
5718#define SYSCFG_ITLINE5_SR_EXTI0_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */
5719#define SYSCFG_ITLINE5_SR_EXTI0 SYSCFG_ITLINE5_SR_EXTI0_Msk /*!< External Interrupt 0 */
5720#define SYSCFG_ITLINE5_SR_EXTI1_Pos (1U)
5721#define SYSCFG_ITLINE5_SR_EXTI1_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI1_Pos) /*!< 0x00000002 */
5722#define SYSCFG_ITLINE5_SR_EXTI1 SYSCFG_ITLINE5_SR_EXTI1_Msk /*!< External Interrupt 1 */
5723#define SYSCFG_ITLINE6_SR_EXTI2_Pos (0U)
5724#define SYSCFG_ITLINE6_SR_EXTI2_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI2_Pos) /*!< 0x00000001 */
5725#define SYSCFG_ITLINE6_SR_EXTI2 SYSCFG_ITLINE6_SR_EXTI2_Msk /*!< External Interrupt 2 */
5726#define SYSCFG_ITLINE6_SR_EXTI3_Pos (1U)
5727#define SYSCFG_ITLINE6_SR_EXTI3_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI3_Pos) /*!< 0x00000002 */
5728#define SYSCFG_ITLINE6_SR_EXTI3 SYSCFG_ITLINE6_SR_EXTI3_Msk /*!< External Interrupt 3 */
5729#define SYSCFG_ITLINE7_SR_EXTI4_Pos (0U)
5730#define SYSCFG_ITLINE7_SR_EXTI4_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI4_Pos) /*!< 0x00000001 */
5731#define SYSCFG_ITLINE7_SR_EXTI4 SYSCFG_ITLINE7_SR_EXTI4_Msk /*!< External Interrupt 4 */
5732#define SYSCFG_ITLINE7_SR_EXTI5_Pos (1U)
5733#define SYSCFG_ITLINE7_SR_EXTI5_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI5_Pos) /*!< 0x00000002 */
5734#define SYSCFG_ITLINE7_SR_EXTI5 SYSCFG_ITLINE7_SR_EXTI5_Msk /*!< External Interrupt 5 */
5735#define SYSCFG_ITLINE7_SR_EXTI6_Pos (2U)
5736#define SYSCFG_ITLINE7_SR_EXTI6_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI6_Pos) /*!< 0x00000004 */
5737#define SYSCFG_ITLINE7_SR_EXTI6 SYSCFG_ITLINE7_SR_EXTI6_Msk /*!< External Interrupt 6 */
5738#define SYSCFG_ITLINE7_SR_EXTI7_Pos (3U)
5739#define SYSCFG_ITLINE7_SR_EXTI7_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI7_Pos) /*!< 0x00000008 */
5740#define SYSCFG_ITLINE7_SR_EXTI7 SYSCFG_ITLINE7_SR_EXTI7_Msk /*!< External Interrupt 7 */
5741#define SYSCFG_ITLINE7_SR_EXTI8_Pos (4U)
5742#define SYSCFG_ITLINE7_SR_EXTI8_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI8_Pos) /*!< 0x00000010 */
5743#define SYSCFG_ITLINE7_SR_EXTI8 SYSCFG_ITLINE7_SR_EXTI8_Msk /*!< External Interrupt 8 */
5744#define SYSCFG_ITLINE7_SR_EXTI9_Pos (5U)
5745#define SYSCFG_ITLINE7_SR_EXTI9_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI9_Pos) /*!< 0x00000020 */
5746#define SYSCFG_ITLINE7_SR_EXTI9 SYSCFG_ITLINE7_SR_EXTI9_Msk /*!< External Interrupt 9 */
5747#define SYSCFG_ITLINE7_SR_EXTI10_Pos (6U)
5748#define SYSCFG_ITLINE7_SR_EXTI10_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI10_Pos) /*!< 0x00000040 */
5749#define SYSCFG_ITLINE7_SR_EXTI10 SYSCFG_ITLINE7_SR_EXTI10_Msk /*!< External Interrupt 10 */
5750#define SYSCFG_ITLINE7_SR_EXTI11_Pos (7U)
5751#define SYSCFG_ITLINE7_SR_EXTI11_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI11_Pos) /*!< 0x00000080 */
5752#define SYSCFG_ITLINE7_SR_EXTI11 SYSCFG_ITLINE7_SR_EXTI11_Msk /*!< External Interrupt 11 */
5753#define SYSCFG_ITLINE7_SR_EXTI12_Pos (8U)
5754#define SYSCFG_ITLINE7_SR_EXTI12_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI12_Pos) /*!< 0x00000100 */
5755#define SYSCFG_ITLINE7_SR_EXTI12 SYSCFG_ITLINE7_SR_EXTI12_Msk /*!< External Interrupt 12 */
5756#define SYSCFG_ITLINE7_SR_EXTI13_Pos (9U)
5757#define SYSCFG_ITLINE7_SR_EXTI13_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI13_Pos) /*!< 0x00000200 */
5758#define SYSCFG_ITLINE7_SR_EXTI13 SYSCFG_ITLINE7_SR_EXTI13_Msk /*!< External Interrupt 13 */
5759#define SYSCFG_ITLINE7_SR_EXTI14_Pos (10U)
5760#define SYSCFG_ITLINE7_SR_EXTI14_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI14_Pos) /*!< 0x00000400 */
5761#define SYSCFG_ITLINE7_SR_EXTI14 SYSCFG_ITLINE7_SR_EXTI14_Msk /*!< External Interrupt 14 */
5762#define SYSCFG_ITLINE7_SR_EXTI15_Pos (11U)
5763#define SYSCFG_ITLINE7_SR_EXTI15_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI15_Pos) /*!< 0x00000800 */
5764#define SYSCFG_ITLINE7_SR_EXTI15 SYSCFG_ITLINE7_SR_EXTI15_Msk /*!< External Interrupt 15 */
5765#define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos (0U)
5766#define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk (0x1UL << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos) /*!< 0x00000001 */
5767#define SYSCFG_ITLINE9_SR_DMA1_CH1 SYSCFG_ITLINE9_SR_DMA1_CH1_Msk /*!< DMA1 Channel 1 Interrupt */
5768#define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos (0U)
5769#define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos) /*!< 0x00000001 */
5770#define SYSCFG_ITLINE10_SR_DMA1_CH2 SYSCFG_ITLINE10_SR_DMA1_CH2_Msk /*!< DMA1 Channel 2 Interrupt */
5771#define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U)
5772#define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */
5773#define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA2 Channel 3 Interrupt */
5774#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U)
5775#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */
5776#define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */
5777#define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos (1U)
5778#define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000002 */
5779#define SYSCFG_ITLINE11_SR_DMA1_CH4 SYSCFG_ITLINE11_SR_DMA1_CH4_Msk /*!< DMA1 Channel 4 Interrupt */
5780#define SYSCFG_ITLINE11_SR_DMA1_CH5_Pos (2U)
5781#define SYSCFG_ITLINE11_SR_DMA1_CH5_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos) /*!< 0x00000004 */
5782#define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 Interrupt */
5783#define SYSCFG_ITLINE11_SR_DMA1_CH6_Pos (3U)
5784#define SYSCFG_ITLINE11_SR_DMA1_CH6_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH6_Pos) /*!< 0x00000008 */
5785#define SYSCFG_ITLINE11_SR_DMA1_CH6 SYSCFG_ITLINE11_SR_DMA1_CH6_Msk /*!< DMA1 Channel 6 Interrupt */
5786#define SYSCFG_ITLINE11_SR_DMA1_CH7_Pos (4U)
5787#define SYSCFG_ITLINE11_SR_DMA1_CH7_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH7_Pos) /*!< 0x00000010 */
5788#define SYSCFG_ITLINE11_SR_DMA1_CH7 SYSCFG_ITLINE11_SR_DMA1_CH7_Msk /*!< DMA1 Channel 7 Interrupt */
5789#define SYSCFG_ITLINE12_SR_ADC_Pos (0U)
5790#define SYSCFG_ITLINE12_SR_ADC_Msk (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */
5791#define SYSCFG_ITLINE12_SR_ADC SYSCFG_ITLINE12_SR_ADC_Msk /*!< ADC Interrupt */
5792#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0U)
5793#define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */
5794#define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */
5795#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1U)
5796#define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */
5797#define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */
5798#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2U)
5799#define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */
5800#define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */
5801#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3U)
5802#define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */
5803#define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */
5804#define SYSCFG_ITLINE14_SR_TIM1_CC_Pos (0U)
5805#define SYSCFG_ITLINE14_SR_TIM1_CC_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC_Pos) /*!< 0x00000001 */
5806#define SYSCFG_ITLINE14_SR_TIM1_CC SYSCFG_ITLINE14_SR_TIM1_CC_Msk /*!< TIM1 CC Interrupt */
5807#define SYSCFG_ITLINE16_SR_TIM3_GLB_Pos (0U)
5808#define SYSCFG_ITLINE16_SR_TIM3_GLB_Msk (0x1UL << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos) /*!< 0x00000001 */
5809#define SYSCFG_ITLINE16_SR_TIM3_GLB SYSCFG_ITLINE16_SR_TIM3_GLB_Msk /*!< TIM3 GLB Interrupt */
5810#define SYSCFG_ITLINE17_SR_TIM6_GLB_Pos (0U)
5811#define SYSCFG_ITLINE17_SR_TIM6_GLB_Msk (0x1UL << SYSCFG_ITLINE17_SR_TIM6_GLB_Pos) /*!< 0x00000001 */
5812#define SYSCFG_ITLINE17_SR_TIM6_GLB SYSCFG_ITLINE17_SR_TIM6_GLB_Msk /*!< TIM6 GLB Interrupt */
5813#define SYSCFG_ITLINE18_SR_TIM7_GLB_Pos (0U)
5814#define SYSCFG_ITLINE18_SR_TIM7_GLB_Msk (0x1UL << SYSCFG_ITLINE18_SR_TIM7_GLB_Pos) /*!< 0x00000001 */
5815#define SYSCFG_ITLINE18_SR_TIM7_GLB SYSCFG_ITLINE18_SR_TIM7_GLB_Msk /*!< TIM7 GLB Interrupt */
5816#define SYSCFG_ITLINE19_SR_TIM14_GLB_Pos (0U)
5817#define SYSCFG_ITLINE19_SR_TIM14_GLB_Msk (0x1UL << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos) /*!< 0x00000001 */
5818#define SYSCFG_ITLINE19_SR_TIM14_GLB SYSCFG_ITLINE19_SR_TIM14_GLB_Msk /*!< TIM14 GLB Interrupt */
5819#define SYSCFG_ITLINE20_SR_TIM15_GLB_Pos (0U)
5820#define SYSCFG_ITLINE20_SR_TIM15_GLB_Msk (0x1UL << SYSCFG_ITLINE20_SR_TIM15_GLB_Pos) /*!< 0x00000001 */
5821#define SYSCFG_ITLINE20_SR_TIM15_GLB SYSCFG_ITLINE20_SR_TIM15_GLB_Msk /*!< TIM15 GLB Interrupt */
5822#define SYSCFG_ITLINE21_SR_TIM16_GLB_Pos (0U)
5823#define SYSCFG_ITLINE21_SR_TIM16_GLB_Msk (0x1UL << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos) /*!< 0x00000001 */
5824#define SYSCFG_ITLINE21_SR_TIM16_GLB SYSCFG_ITLINE21_SR_TIM16_GLB_Msk /*!< TIM16 GLB Interrupt */
5825#define SYSCFG_ITLINE22_SR_TIM17_GLB_Pos (0U)
5826#define SYSCFG_ITLINE22_SR_TIM17_GLB_Msk (0x1UL << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos) /*!< 0x00000001 */
5827#define SYSCFG_ITLINE22_SR_TIM17_GLB SYSCFG_ITLINE22_SR_TIM17_GLB_Msk /*!< TIM17 GLB Interrupt */
5828#define SYSCFG_ITLINE23_SR_I2C1_GLB_Pos (0U)
5829#define SYSCFG_ITLINE23_SR_I2C1_GLB_Msk (0x1UL << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos) /*!< 0x00000001 */
5830#define SYSCFG_ITLINE23_SR_I2C1_GLB SYSCFG_ITLINE23_SR_I2C1_GLB_Msk /*!< I2C1 GLB Interrupt -> exti[23] */
5831#define SYSCFG_ITLINE24_SR_I2C2_GLB_Pos (0U)
5832#define SYSCFG_ITLINE24_SR_I2C2_GLB_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C2_GLB_Pos) /*!< 0x00000001 */
5833#define SYSCFG_ITLINE24_SR_I2C2_GLB SYSCFG_ITLINE24_SR_I2C2_GLB_Msk /*!< I2C2 GLB Interrupt */
5834#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U)
5835#define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */
5836#define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */
5837#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U)
5838#define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */
5839#define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */
5840#define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U)
5841#define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */
5842#define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt -> exti[25] */
5843#define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U)
5844#define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */
5845#define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt -> exti[26] */
5846#define SYSCFG_ITLINE29_SR_USART3_GLB_Pos (0U)
5847#define SYSCFG_ITLINE29_SR_USART3_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART3_GLB_Pos) /*!< 0x00000001 */
5848#define SYSCFG_ITLINE29_SR_USART3_GLB SYSCFG_ITLINE29_SR_USART3_GLB_Msk /*!< USART3 GLB Interrupt */
5849#define SYSCFG_ITLINE29_SR_USART4_GLB_Pos (1U)
5850#define SYSCFG_ITLINE29_SR_USART4_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART4_GLB_Pos) /*!< 0x00000002 */
5851#define SYSCFG_ITLINE29_SR_USART4_GLB SYSCFG_ITLINE29_SR_USART4_GLB_Msk /*!< USART4 GLB Interrupt */
5852
5853/******************************************************************************/
5854/* */
5855/* TIM */
5856/* */
5857/******************************************************************************/
5858/******************* Bit definition for TIM_CR1 register ********************/
5859#define TIM_CR1_CEN_Pos (0U)
5860#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
5861#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
5862#define TIM_CR1_UDIS_Pos (1U)
5863#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
5864#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
5865#define TIM_CR1_URS_Pos (2U)
5866#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
5867#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
5868#define TIM_CR1_OPM_Pos (3U)
5869#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
5870#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
5871#define TIM_CR1_DIR_Pos (4U)
5872#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
5873#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
5874
5875#define TIM_CR1_CMS_Pos (5U)
5876#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
5877#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
5878#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
5879#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
5880
5881#define TIM_CR1_ARPE_Pos (7U)
5882#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
5883#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
5884
5885#define TIM_CR1_CKD_Pos (8U)
5886#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
5887#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
5888#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
5889#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
5890
5891#define TIM_CR1_UIFREMAP_Pos (11U)
5892#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
5893#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
5894
5895/******************* Bit definition for TIM_CR2 register ********************/
5896#define TIM_CR2_CCPC_Pos (0U)
5897#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
5898#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
5899#define TIM_CR2_CCUS_Pos (2U)
5900#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
5901#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
5902#define TIM_CR2_CCDS_Pos (3U)
5903#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
5904#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
5905
5906#define TIM_CR2_MMS_Pos (4U)
5907#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
5908#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
5909#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
5910#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
5911#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
5912
5913#define TIM_CR2_TI1S_Pos (7U)
5914#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
5915#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
5916#define TIM_CR2_OIS1_Pos (8U)
5917#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
5918#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
5919#define TIM_CR2_OIS1N_Pos (9U)
5920#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
5921#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
5922#define TIM_CR2_OIS2_Pos (10U)
5923#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
5924#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
5925#define TIM_CR2_OIS2N_Pos (11U)
5926#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
5927#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
5928#define TIM_CR2_OIS3_Pos (12U)
5929#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
5930#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
5931#define TIM_CR2_OIS3N_Pos (13U)
5932#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
5933#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
5934#define TIM_CR2_OIS4_Pos (14U)
5935#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
5936#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
5937#define TIM_CR2_OIS5_Pos (16U)
5938#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
5939#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
5940#define TIM_CR2_OIS6_Pos (18U)
5941#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
5942#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
5943
5944#define TIM_CR2_MMS2_Pos (20U)
5945#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
5946#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
5947#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
5948#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
5949#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
5950#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
5951
5952/******************* Bit definition for TIM_SMCR register *******************/
5953#define TIM_SMCR_SMS_Pos (0U)
5954#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
5955#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
5956#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
5957#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
5958#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
5959#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
5960
5961#define TIM_SMCR_OCCS_Pos (3U)
5962#define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
5963#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
5964
5965#define TIM_SMCR_TS_Pos (4U)
5966#define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */
5967#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
5968#define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
5969#define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
5970#define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
5971#define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */
5972#define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */
5973
5974#define TIM_SMCR_MSM_Pos (7U)
5975#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
5976#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
5977
5978#define TIM_SMCR_ETF_Pos (8U)
5979#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
5980#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
5981#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
5982#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
5983#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
5984#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
5985
5986#define TIM_SMCR_ETPS_Pos (12U)
5987#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
5988#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
5989#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
5990#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
5991
5992#define TIM_SMCR_ECE_Pos (14U)
5993#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
5994#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
5995#define TIM_SMCR_ETP_Pos (15U)
5996#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
5997#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
5998
5999/******************* Bit definition for TIM_DIER register *******************/
6000#define TIM_DIER_UIE_Pos (0U)
6001#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
6002#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
6003#define TIM_DIER_CC1IE_Pos (1U)
6004#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
6005#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
6006#define TIM_DIER_CC2IE_Pos (2U)
6007#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
6008#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
6009#define TIM_DIER_CC3IE_Pos (3U)
6010#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
6011#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
6012#define TIM_DIER_CC4IE_Pos (4U)
6013#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
6014#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
6015#define TIM_DIER_COMIE_Pos (5U)
6016#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
6017#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
6018#define TIM_DIER_TIE_Pos (6U)
6019#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
6020#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
6021#define TIM_DIER_BIE_Pos (7U)
6022#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
6023#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
6024#define TIM_DIER_UDE_Pos (8U)
6025#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
6026#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
6027#define TIM_DIER_CC1DE_Pos (9U)
6028#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
6029#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
6030#define TIM_DIER_CC2DE_Pos (10U)
6031#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
6032#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
6033#define TIM_DIER_CC3DE_Pos (11U)
6034#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
6035#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
6036#define TIM_DIER_CC4DE_Pos (12U)
6037#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
6038#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
6039#define TIM_DIER_COMDE_Pos (13U)
6040#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
6041#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
6042#define TIM_DIER_TDE_Pos (14U)
6043#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
6044#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
6045
6046/******************** Bit definition for TIM_SR register ********************/
6047#define TIM_SR_UIF_Pos (0U)
6048#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
6049#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
6050#define TIM_SR_CC1IF_Pos (1U)
6051#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
6052#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
6053#define TIM_SR_CC2IF_Pos (2U)
6054#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
6055#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
6056#define TIM_SR_CC3IF_Pos (3U)
6057#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
6058#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
6059#define TIM_SR_CC4IF_Pos (4U)
6060#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
6061#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
6062#define TIM_SR_COMIF_Pos (5U)
6063#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
6064#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
6065#define TIM_SR_TIF_Pos (6U)
6066#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
6067#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
6068#define TIM_SR_BIF_Pos (7U)
6069#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
6070#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
6071#define TIM_SR_B2IF_Pos (8U)
6072#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
6073#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
6074#define TIM_SR_CC1OF_Pos (9U)
6075#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
6076#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
6077#define TIM_SR_CC2OF_Pos (10U)
6078#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
6079#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
6080#define TIM_SR_CC3OF_Pos (11U)
6081#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
6082#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
6083#define TIM_SR_CC4OF_Pos (12U)
6084#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
6085#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
6086#define TIM_SR_SBIF_Pos (13U)
6087#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
6088#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
6089#define TIM_SR_CC5IF_Pos (16U)
6090#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
6091#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
6092#define TIM_SR_CC6IF_Pos (17U)
6093#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
6094#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
6095
6096
6097/******************* Bit definition for TIM_EGR register ********************/
6098#define TIM_EGR_UG_Pos (0U)
6099#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
6100#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
6101#define TIM_EGR_CC1G_Pos (1U)
6102#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
6103#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
6104#define TIM_EGR_CC2G_Pos (2U)
6105#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
6106#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
6107#define TIM_EGR_CC3G_Pos (3U)
6108#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
6109#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
6110#define TIM_EGR_CC4G_Pos (4U)
6111#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
6112#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
6113#define TIM_EGR_COMG_Pos (5U)
6114#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
6115#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
6116#define TIM_EGR_TG_Pos (6U)
6117#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
6118#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
6119#define TIM_EGR_BG_Pos (7U)
6120#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
6121#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
6122#define TIM_EGR_B2G_Pos (8U)
6123#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
6124#define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
6125
6126
6127/****************** Bit definition for TIM_CCMR1 register *******************/
6128#define TIM_CCMR1_CC1S_Pos (0U)
6129#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
6130#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
6131#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
6132#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
6133
6134#define TIM_CCMR1_OC1FE_Pos (2U)
6135#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
6136#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
6137#define TIM_CCMR1_OC1PE_Pos (3U)
6138#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
6139#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
6140
6141#define TIM_CCMR1_OC1M_Pos (4U)
6142#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
6143#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
6144#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
6145#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
6146#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
6147#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
6148
6149#define TIM_CCMR1_OC1CE_Pos (7U)
6150#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
6151#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
6152
6153#define TIM_CCMR1_CC2S_Pos (8U)
6154#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
6155#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
6156#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
6157#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
6158
6159#define TIM_CCMR1_OC2FE_Pos (10U)
6160#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
6161#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
6162#define TIM_CCMR1_OC2PE_Pos (11U)
6163#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
6164#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
6165
6166#define TIM_CCMR1_OC2M_Pos (12U)
6167#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
6168#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
6169#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
6170#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
6171#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
6172#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
6173
6174#define TIM_CCMR1_OC2CE_Pos (15U)
6175#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
6176#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
6177
6178/*----------------------------------------------------------------------------*/
6179#define TIM_CCMR1_IC1PSC_Pos (2U)
6180#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
6181#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
6182#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
6183#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
6184
6185#define TIM_CCMR1_IC1F_Pos (4U)
6186#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
6187#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
6188#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
6189#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
6190#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
6191#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
6192
6193#define TIM_CCMR1_IC2PSC_Pos (10U)
6194#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
6195#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
6196#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
6197#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
6198
6199#define TIM_CCMR1_IC2F_Pos (12U)
6200#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
6201#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
6202#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
6203#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
6204#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
6205#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
6206
6207/****************** Bit definition for TIM_CCMR2 register *******************/
6208#define TIM_CCMR2_CC3S_Pos (0U)
6209#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
6210#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
6211#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
6212#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
6213
6214#define TIM_CCMR2_OC3FE_Pos (2U)
6215#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
6216#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
6217#define TIM_CCMR2_OC3PE_Pos (3U)
6218#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
6219#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
6220
6221#define TIM_CCMR2_OC3M_Pos (4U)
6222#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
6223#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
6224#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
6225#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
6226#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
6227#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
6228
6229#define TIM_CCMR2_OC3CE_Pos (7U)
6230#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
6231#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
6232
6233#define TIM_CCMR2_CC4S_Pos (8U)
6234#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
6235#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
6236#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
6237#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
6238
6239#define TIM_CCMR2_OC4FE_Pos (10U)
6240#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
6241#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
6242#define TIM_CCMR2_OC4PE_Pos (11U)
6243#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
6244#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
6245
6246#define TIM_CCMR2_OC4M_Pos (12U)
6247#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
6248#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
6249#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
6250#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
6251#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
6252#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
6253
6254#define TIM_CCMR2_OC4CE_Pos (15U)
6255#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
6256#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
6257
6258/*----------------------------------------------------------------------------*/
6259#define TIM_CCMR2_IC3PSC_Pos (2U)
6260#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
6261#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
6262#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
6263#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
6264
6265#define TIM_CCMR2_IC3F_Pos (4U)
6266#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
6267#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
6268#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
6269#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
6270#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
6271#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
6272
6273#define TIM_CCMR2_IC4PSC_Pos (10U)
6274#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
6275#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
6276#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
6277#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
6278
6279#define TIM_CCMR2_IC4F_Pos (12U)
6280#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
6281#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
6282#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
6283#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
6284#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
6285#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
6286
6287/****************** Bit definition for TIM_CCMR3 register *******************/
6288#define TIM_CCMR3_OC5FE_Pos (2U)
6289#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
6290#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
6291#define TIM_CCMR3_OC5PE_Pos (3U)
6292#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
6293#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
6294
6295#define TIM_CCMR3_OC5M_Pos (4U)
6296#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
6297#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
6298#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
6299#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
6300#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
6301#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
6302
6303#define TIM_CCMR3_OC5CE_Pos (7U)
6304#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
6305#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
6306
6307#define TIM_CCMR3_OC6FE_Pos (10U)
6308#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
6309#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
6310#define TIM_CCMR3_OC6PE_Pos (11U)
6311#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
6312#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
6313
6314#define TIM_CCMR3_OC6M_Pos (12U)
6315#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
6316#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
6317#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
6318#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
6319#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
6320#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
6321
6322#define TIM_CCMR3_OC6CE_Pos (15U)
6323#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
6324#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
6325
6326/******************* Bit definition for TIM_CCER register *******************/
6327#define TIM_CCER_CC1E_Pos (0U)
6328#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
6329#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
6330#define TIM_CCER_CC1P_Pos (1U)
6331#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
6332#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
6333#define TIM_CCER_CC1NE_Pos (2U)
6334#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
6335#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
6336#define TIM_CCER_CC1NP_Pos (3U)
6337#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
6338#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
6339#define TIM_CCER_CC2E_Pos (4U)
6340#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
6341#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
6342#define TIM_CCER_CC2P_Pos (5U)
6343#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
6344#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
6345#define TIM_CCER_CC2NE_Pos (6U)
6346#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
6347#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
6348#define TIM_CCER_CC2NP_Pos (7U)
6349#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
6350#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
6351#define TIM_CCER_CC3E_Pos (8U)
6352#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
6353#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
6354#define TIM_CCER_CC3P_Pos (9U)
6355#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
6356#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
6357#define TIM_CCER_CC3NE_Pos (10U)
6358#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
6359#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
6360#define TIM_CCER_CC3NP_Pos (11U)
6361#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
6362#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
6363#define TIM_CCER_CC4E_Pos (12U)
6364#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
6365#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
6366#define TIM_CCER_CC4P_Pos (13U)
6367#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
6368#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
6369#define TIM_CCER_CC4NP_Pos (15U)
6370#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
6371#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
6372#define TIM_CCER_CC5E_Pos (16U)
6373#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
6374#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
6375#define TIM_CCER_CC5P_Pos (17U)
6376#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
6377#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
6378#define TIM_CCER_CC6E_Pos (20U)
6379#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
6380#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
6381#define TIM_CCER_CC6P_Pos (21U)
6382#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
6383#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
6384
6385/******************* Bit definition for TIM_CNT register ********************/
6386#define TIM_CNT_CNT_Pos (0U)
6387#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
6388#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
6389#define TIM_CNT_UIFCPY_Pos (31U)
6390#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
6391#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
6392
6393/******************* Bit definition for TIM_PSC register ********************/
6394#define TIM_PSC_PSC_Pos (0U)
6395#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
6396#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
6397
6398/******************* Bit definition for TIM_ARR register ********************/
6399#define TIM_ARR_ARR_Pos (0U)
6400#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
6401#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
6402
6403/******************* Bit definition for TIM_RCR register ********************/
6404#define TIM_RCR_REP_Pos (0U)
6405#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
6406#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
6407
6408/******************* Bit definition for TIM_CCR1 register *******************/
6409#define TIM_CCR1_CCR1_Pos (0U)
6410#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
6411#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
6412
6413/******************* Bit definition for TIM_CCR2 register *******************/
6414#define TIM_CCR2_CCR2_Pos (0U)
6415#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
6416#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
6417
6418/******************* Bit definition for TIM_CCR3 register *******************/
6419#define TIM_CCR3_CCR3_Pos (0U)
6420#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
6421#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
6422
6423/******************* Bit definition for TIM_CCR4 register *******************/
6424#define TIM_CCR4_CCR4_Pos (0U)
6425#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
6426#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
6427
6428/******************* Bit definition for TIM_CCR5 register *******************/
6429#define TIM_CCR5_CCR5_Pos (0U)
6430#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
6431#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
6432#define TIM_CCR5_GC5C1_Pos (29U)
6433#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
6434#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
6435#define TIM_CCR5_GC5C2_Pos (30U)
6436#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
6437#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
6438#define TIM_CCR5_GC5C3_Pos (31U)
6439#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
6440#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
6441
6442/******************* Bit definition for TIM_CCR6 register *******************/
6443#define TIM_CCR6_CCR6_Pos (0U)
6444#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
6445#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
6446
6447/******************* Bit definition for TIM_BDTR register *******************/
6448#define TIM_BDTR_DTG_Pos (0U)
6449#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
6450#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
6451#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
6452#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
6453#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
6454#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
6455#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
6456#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
6457#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
6458#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
6459
6460#define TIM_BDTR_LOCK_Pos (8U)
6461#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
6462#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
6463#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
6464#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
6465
6466#define TIM_BDTR_OSSI_Pos (10U)
6467#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
6468#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
6469#define TIM_BDTR_OSSR_Pos (11U)
6470#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
6471#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
6472#define TIM_BDTR_BKE_Pos (12U)
6473#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
6474#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
6475#define TIM_BDTR_BKP_Pos (13U)
6476#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
6477#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
6478#define TIM_BDTR_AOE_Pos (14U)
6479#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
6480#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
6481#define TIM_BDTR_MOE_Pos (15U)
6482#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
6483#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
6484
6485#define TIM_BDTR_BKF_Pos (16U)
6486#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
6487#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
6488#define TIM_BDTR_BK2F_Pos (20U)
6489#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
6490#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
6491
6492#define TIM_BDTR_BK2E_Pos (24U)
6493#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
6494#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
6495#define TIM_BDTR_BK2P_Pos (25U)
6496#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
6497#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
6498
6499#define TIM_BDTR_BKDSRM_Pos (26U)
6500#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
6501#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
6502#define TIM_BDTR_BK2DSRM_Pos (27U)
6503#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
6504#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
6505
6506#define TIM_BDTR_BKBID_Pos (28U)
6507#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
6508#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break BIDirectional */
6509#define TIM_BDTR_BK2BID_Pos (29U)
6510#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
6511#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 BIDirectional */
6512
6513/******************* Bit definition for TIM_DCR register ********************/
6514#define TIM_DCR_DBA_Pos (0U)
6515#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
6516#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
6517#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
6518#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
6519#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
6520#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
6521#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
6522
6523#define TIM_DCR_DBL_Pos (8U)
6524#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
6525#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
6526#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
6527#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
6528#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
6529#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
6530#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
6531
6532/******************* Bit definition for TIM_DMAR register *******************/
6533#define TIM_DMAR_DMAB_Pos (0U)
6534#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
6535#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
6536
6537/******************* Bit definition for TIM1_OR1 register *******************/
6538#define TIM1_OR1_OCREF_CLR_Pos (0U)
6539#define TIM1_OR1_OCREF_CLR_Msk (0x1UL << TIM1_OR1_OCREF_CLR_Pos) /*!< 0x00000001 */
6540#define TIM1_OR1_OCREF_CLR TIM1_OR1_OCREF_CLR_Msk /*!<OCREF clear input selection */
6541
6542/******************* Bit definition for TIM1_AF1 register *******************/
6543#define TIM1_AF1_BKINE_Pos (0U)
6544#define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
6545#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BRK BKIN input enable */
6546#define TIM1_AF1_BKCMP1E_Pos (1U)
6547#define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
6548#define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */
6549#define TIM1_AF1_BKCMP2E_Pos (2U)
6550#define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
6551#define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */
6552#define TIM1_AF1_BKINP_Pos (9U)
6553#define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
6554#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
6555#define TIM1_AF1_BKCMP1P_Pos (10U)
6556#define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
6557#define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
6558#define TIM1_AF1_BKCMP2P_Pos (11U)
6559#define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
6560#define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
6561
6562#define TIM1_AF1_ETRSEL_Pos (14U)
6563#define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
6564#define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
6565#define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */
6566#define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */
6567#define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */
6568#define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */
6569
6570/******************* Bit definition for TIM1_AF2 register *******************/
6571#define TIM1_AF2_BK2INE_Pos (0U)
6572#define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
6573#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
6574#define TIM1_AF2_BK2CMP1E_Pos (1U)
6575#define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
6576#define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
6577#define TIM1_AF2_BK2CMP2E_Pos (2U)
6578#define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
6579#define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
6580#define TIM1_AF2_BK2INP_Pos (9U)
6581#define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
6582#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */
6583#define TIM1_AF2_BK2CMP1P_Pos (10U)
6584#define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
6585#define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
6586#define TIM1_AF2_BK2CMP2P_Pos (11U)
6587#define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
6588#define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
6589
6590
6591/******************* Bit definition for TIM3_OR1 register *******************/
6592#define TIM3_OR1_OCREF_CLR_Pos (0U)
6593#define TIM3_OR1_OCREF_CLR_Msk (0x1UL << TIM3_OR1_OCREF_CLR_Pos) /*!< 0x00000001 */
6594#define TIM3_OR1_OCREF_CLR TIM3_OR1_OCREF_CLR_Msk /*!<OCREF clear input selection */
6595
6596/******************* Bit definition for TIM3_AF1 register *******************/
6597#define TIM3_AF1_ETRSEL_Pos (14U)
6598#define TIM3_AF1_ETRSEL_Msk (0xFUL << TIM3_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
6599#define TIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM3 ETR source selection) */
6600#define TIM3_AF1_ETRSEL_0 (0x1UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00004000 */
6601#define TIM3_AF1_ETRSEL_1 (0x2UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00008000 */
6602#define TIM3_AF1_ETRSEL_2 (0x4UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00010000 */
6603#define TIM3_AF1_ETRSEL_3 (0x8UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00020000 */
6604
6605/******************* Bit definition for TIM14_AF1 register *******************/
6606#define TIM14_AF1_ETRSEL_Pos (14U)
6607#define TIM14_AF1_ETRSEL_Msk (0xFUL << TIM14_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
6608#define TIM14_AF1_ETRSEL TIM14_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM3 ETR source selection) */
6609#define TIM14_AF1_ETRSEL_0 (0x1UL << TIM14_AF1_ETRSEL_Pos) /*!< 0x00004000 */
6610#define TIM14_AF1_ETRSEL_1 (0x2UL << TIM14_AF1_ETRSEL_Pos) /*!< 0x00008000 */
6611#define TIM14_AF1_ETRSEL_2 (0x4UL << TIM14_AF1_ETRSEL_Pos) /*!< 0x00010000 */
6612#define TIM14_AF1_ETRSEL_3 (0x8UL << TIM14_AF1_ETRSEL_Pos) /*!< 0x00020000 */
6613
6614/******************* Bit definition for TIM15_AF1 register ******************/
6615#define TIM15_AF1_BKINE_Pos (0U)
6616#define TIM15_AF1_BKINE_Msk (0x1UL << TIM15_AF1_BKINE_Pos) /*!< 0x00000001 */
6617#define TIM15_AF1_BKINE TIM15_AF1_BKINE_Msk /*!<BRK BKIN input enable */
6618#define TIM15_AF1_BKCMP1E_Pos (1U)
6619#define TIM15_AF1_BKCMP1E_Msk (0x1UL << TIM15_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
6620#define TIM15_AF1_BKCMP1E TIM15_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */
6621#define TIM15_AF1_BKCMP2E_Pos (2U)
6622#define TIM15_AF1_BKCMP2E_Msk (0x1UL << TIM15_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
6623#define TIM15_AF1_BKCMP2E TIM15_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */
6624#define TIM15_AF1_BKINP_Pos (9U)
6625#define TIM15_AF1_BKINP_Msk (0x1UL << TIM15_AF1_BKINP_Pos) /*!< 0x00000200 */
6626#define TIM15_AF1_BKINP TIM15_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
6627#define TIM15_AF1_BKCMP1P_Pos (10U)
6628#define TIM15_AF1_BKCMP1P_Msk (0x1UL << TIM15_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
6629#define TIM15_AF1_BKCMP1P TIM15_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
6630#define TIM15_AF1_BKCMP2P_Pos (11U)
6631#define TIM15_AF1_BKCMP2P_Msk (0x1UL << TIM15_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
6632#define TIM15_AF1_BKCMP2P TIM15_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
6633
6634/******************* Bit definition for TIM16_AF1 register ******************/
6635#define TIM16_AF1_BKINE_Pos (0U)
6636#define TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos) /*!< 0x00000001 */
6637#define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk /*!<BRK BKIN input enable */
6638#define TIM16_AF1_BKCMP1E_Pos (1U)
6639#define TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
6640#define TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */
6641#define TIM16_AF1_BKCMP2E_Pos (2U)
6642#define TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
6643#define TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */
6644#define TIM16_AF1_BKINP_Pos (9U)
6645#define TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos) /*!< 0x00000200 */
6646#define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
6647#define TIM16_AF1_BKCMP1P_Pos (10U)
6648#define TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
6649#define TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
6650#define TIM16_AF1_BKCMP2P_Pos (11U)
6651#define TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
6652#define TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
6653
6654/******************* Bit definition for TIM17_AF1 register ******************/
6655#define TIM17_AF1_BKINE_Pos (0U)
6656#define TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos) /*!< 0x00000001 */
6657#define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk /*!<BRK BKIN input enable */
6658#define TIM17_AF1_BKCMP1E_Pos (1U)
6659#define TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
6660#define TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */
6661#define TIM17_AF1_BKCMP2E_Pos (2U)
6662#define TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
6663#define TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */
6664#define TIM17_AF1_BKINP_Pos (9U)
6665#define TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos) /*!< 0x00000200 */
6666#define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
6667#define TIM17_AF1_BKCMP1P_Pos (10U)
6668#define TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
6669#define TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
6670#define TIM17_AF1_BKCMP2P_Pos (11U)
6671#define TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
6672#define TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
6673
6674/******************* Bit definition for TIM_TISEL register *********************/
6675#define TIM_TISEL_TI1SEL_Pos (0U)
6676#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
6677#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
6678#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
6679#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
6680#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
6681#define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
6682
6683#define TIM_TISEL_TI2SEL_Pos (8U)
6684#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
6685#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
6686#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
6687#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
6688#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
6689#define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
6690
6691#define TIM_TISEL_TI3SEL_Pos (16U)
6692#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
6693#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
6694#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
6695#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
6696#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
6697#define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
6698
6699#define TIM_TISEL_TI4SEL_Pos (24U)
6700#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
6701#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
6702#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
6703#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
6704#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
6705#define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
6706
6707
6708
6709/******************************************************************************/
6710/* */
6711/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
6712/* */
6713/******************************************************************************/
6714/****************** Bit definition for USART_CR1 register *******************/
6715#define USART_CR1_UE_Pos (0U)
6716#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
6717#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
6718#define USART_CR1_UESM_Pos (1U)
6719#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
6720#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
6721#define USART_CR1_RE_Pos (2U)
6722#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
6723#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
6724#define USART_CR1_TE_Pos (3U)
6725#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
6726#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
6727#define USART_CR1_IDLEIE_Pos (4U)
6728#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
6729#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
6730#define USART_CR1_RXNEIE_RXFNEIE_Pos (5U)
6731#define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
6732#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk /*!< RXNE/RXFIFO not empty Interrupt Enable */
6733#define USART_CR1_TCIE_Pos (6U)
6734#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
6735#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
6736#define USART_CR1_TXEIE_TXFNFIE_Pos (7U)
6737#define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */
6738#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk /*!< TXE/TXFIFO not full Interrupt Enable */
6739#define USART_CR1_PEIE_Pos (8U)
6740#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
6741#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
6742#define USART_CR1_PS_Pos (9U)
6743#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
6744#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
6745#define USART_CR1_PCE_Pos (10U)
6746#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
6747#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
6748#define USART_CR1_WAKE_Pos (11U)
6749#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
6750#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
6751#define USART_CR1_M_Pos (12U)
6752#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
6753#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
6754#define USART_CR1_M0_Pos (12U)
6755#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
6756#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
6757#define USART_CR1_MME_Pos (13U)
6758#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
6759#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
6760#define USART_CR1_CMIE_Pos (14U)
6761#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
6762#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
6763#define USART_CR1_OVER8_Pos (15U)
6764#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
6765#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
6766#define USART_CR1_DEDT_Pos (16U)
6767#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
6768#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
6769#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
6770#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
6771#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
6772#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
6773#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
6774#define USART_CR1_DEAT_Pos (21U)
6775#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
6776#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
6777#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
6778#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
6779#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
6780#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
6781#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
6782#define USART_CR1_RTOIE_Pos (26U)
6783#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
6784#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
6785#define USART_CR1_EOBIE_Pos (27U)
6786#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
6787#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
6788#define USART_CR1_M1_Pos (28U)
6789#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
6790#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
6791#define USART_CR1_FIFOEN_Pos (29U)
6792#define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
6793#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
6794#define USART_CR1_TXFEIE_Pos (30U)
6795#define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
6796#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */
6797#define USART_CR1_RXFFIE_Pos (31U)
6798#define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
6799#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */
6800
6801/****************** Bit definition for USART_CR2 register *******************/
6802#define USART_CR2_SLVEN_Pos (0U)
6803#define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
6804#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */
6805#define USART_CR2_DIS_NSS_Pos (3U)
6806#define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
6807#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< NSS input pin disable for SPI slave selection */
6808#define USART_CR2_ADDM7_Pos (4U)
6809#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
6810#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
6811#define USART_CR2_LBDL_Pos (5U)
6812#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
6813#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
6814#define USART_CR2_LBDIE_Pos (6U)
6815#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
6816#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
6817#define USART_CR2_LBCL_Pos (8U)
6818#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
6819#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
6820#define USART_CR2_CPHA_Pos (9U)
6821#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
6822#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
6823#define USART_CR2_CPOL_Pos (10U)
6824#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
6825#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
6826#define USART_CR2_CLKEN_Pos (11U)
6827#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
6828#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
6829#define USART_CR2_STOP_Pos (12U)
6830#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
6831#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
6832#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
6833#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
6834#define USART_CR2_LINEN_Pos (14U)
6835#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
6836#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
6837#define USART_CR2_SWAP_Pos (15U)
6838#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
6839#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
6840#define USART_CR2_RXINV_Pos (16U)
6841#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
6842#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
6843#define USART_CR2_TXINV_Pos (17U)
6844#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
6845#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
6846#define USART_CR2_DATAINV_Pos (18U)
6847#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
6848#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
6849#define USART_CR2_MSBFIRST_Pos (19U)
6850#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
6851#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
6852#define USART_CR2_ABREN_Pos (20U)
6853#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
6854#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
6855#define USART_CR2_ABRMODE_Pos (21U)
6856#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
6857#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
6858#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
6859#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
6860#define USART_CR2_RTOEN_Pos (23U)
6861#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
6862#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
6863#define USART_CR2_ADD_Pos (24U)
6864#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
6865#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
6866
6867/****************** Bit definition for USART_CR3 register *******************/
6868#define USART_CR3_EIE_Pos (0U)
6869#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
6870#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
6871#define USART_CR3_IREN_Pos (1U)
6872#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
6873#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
6874#define USART_CR3_IRLP_Pos (2U)
6875#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
6876#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
6877#define USART_CR3_HDSEL_Pos (3U)
6878#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
6879#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
6880#define USART_CR3_NACK_Pos (4U)
6881#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
6882#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
6883#define USART_CR3_SCEN_Pos (5U)
6884#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
6885#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
6886#define USART_CR3_DMAR_Pos (6U)
6887#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
6888#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
6889#define USART_CR3_DMAT_Pos (7U)
6890#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
6891#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
6892#define USART_CR3_RTSE_Pos (8U)
6893#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
6894#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
6895#define USART_CR3_CTSE_Pos (9U)
6896#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
6897#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
6898#define USART_CR3_CTSIE_Pos (10U)
6899#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
6900#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
6901#define USART_CR3_ONEBIT_Pos (11U)
6902#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
6903#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
6904#define USART_CR3_OVRDIS_Pos (12U)
6905#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
6906#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
6907#define USART_CR3_DDRE_Pos (13U)
6908#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
6909#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
6910#define USART_CR3_DEM_Pos (14U)
6911#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
6912#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
6913#define USART_CR3_DEP_Pos (15U)
6914#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
6915#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
6916#define USART_CR3_SCARCNT_Pos (17U)
6917#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
6918#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
6919#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
6920#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
6921#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
6922#define USART_CR3_WUS_Pos (20U)
6923#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
6924#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
6925#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
6926#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
6927#define USART_CR3_WUFIE_Pos (22U)
6928#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
6929#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
6930#define USART_CR3_TXFTIE_Pos (23U)
6931#define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */
6932#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */
6933#define USART_CR3_TCBGTIE_Pos (24U)
6934#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
6935#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
6936#define USART_CR3_RXFTCFG_Pos (25U)
6937#define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
6938#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFIFO FIFO threshold configuration */
6939#define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
6940#define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
6941#define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
6942#define USART_CR3_RXFTIE_Pos (28U)
6943#define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */
6944#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */
6945#define USART_CR3_TXFTCFG_Pos (29U)
6946#define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
6947#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO threshold configuration */
6948#define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
6949#define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
6950#define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
6951
6952/****************** Bit definition for USART_BRR register *******************/
6953#define USART_BRR_BRR ((uint16_t)0xFFFF) /*!< USART Baud rate register [15:0] */
6954
6955/****************** Bit definition for USART_GTPR register ******************/
6956#define USART_GTPR_PSC_Pos (0U)
6957#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
6958#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
6959#define USART_GTPR_GT_Pos (8U)
6960#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
6961#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
6962
6963/******************* Bit definition for USART_RTOR register *****************/
6964#define USART_RTOR_RTO_Pos (0U)
6965#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
6966#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
6967#define USART_RTOR_BLEN_Pos (24U)
6968#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
6969#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
6970
6971/******************* Bit definition for USART_RQR register ******************/
6972#define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate Request */
6973#define USART_RQR_SBKRQ ((uint16_t)0x0002) /*!< Send Break Request */
6974#define USART_RQR_MMRQ ((uint16_t)0x0004) /*!< Mute Mode Request */
6975#define USART_RQR_RXFRQ ((uint16_t)0x0008) /*!< Receive Data flush Request */
6976#define USART_RQR_TXFRQ ((uint16_t)0x0010) /*!< Transmit data flush Request */
6977
6978/******************* Bit definition for USART_ISR register ******************/
6979#define USART_ISR_PE_Pos (0U)
6980#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
6981#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
6982#define USART_ISR_FE_Pos (1U)
6983#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
6984#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
6985#define USART_ISR_NE_Pos (2U)
6986#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
6987#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
6988#define USART_ISR_ORE_Pos (3U)
6989#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
6990#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
6991#define USART_ISR_IDLE_Pos (4U)
6992#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
6993#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
6994#define USART_ISR_RXNE_RXFNE_Pos (5U)
6995#define USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos) /*!< 0x00000020 */
6996#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk /*!< Read Data Register Not Empty/RXFIFO Not Empty */
6997#define USART_ISR_TC_Pos (6U)
6998#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
6999#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
7000#define USART_ISR_TXE_TXFNF_Pos (7U)
7001#define USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos) /*!< 0x00000080 */
7002#define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk /*!< Transmit Data Register Empty/TXFIFO Not Full */
7003#define USART_ISR_LBDF_Pos (8U)
7004#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
7005#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
7006#define USART_ISR_CTSIF_Pos (9U)
7007#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
7008#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
7009#define USART_ISR_CTS_Pos (10U)
7010#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
7011#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
7012#define USART_ISR_RTOF_Pos (11U)
7013#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
7014#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
7015#define USART_ISR_EOBF_Pos (12U)
7016#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
7017#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
7018#define USART_ISR_UDR_Pos (13U)
7019#define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */
7020#define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI Slave Underrun Error Flag */
7021#define USART_ISR_ABRE_Pos (14U)
7022#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
7023#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
7024#define USART_ISR_ABRF_Pos (15U)
7025#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
7026#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
7027#define USART_ISR_BUSY_Pos (16U)
7028#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
7029#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
7030#define USART_ISR_CMF_Pos (17U)
7031#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
7032#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
7033#define USART_ISR_SBKF_Pos (18U)
7034#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
7035#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
7036#define USART_ISR_RWU_Pos (19U)
7037#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
7038#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
7039#define USART_ISR_WUF_Pos (20U)
7040#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
7041#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
7042#define USART_ISR_TEACK_Pos (21U)
7043#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
7044#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
7045#define USART_ISR_REACK_Pos (22U)
7046#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
7047#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
7048#define USART_ISR_TXFE_Pos (23U)
7049#define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
7050#define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty Flag */
7051#define USART_ISR_RXFF_Pos (24U)
7052#define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */
7053#define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full Flag */
7054#define USART_ISR_TCBGT_Pos (25U)
7055#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
7056#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time Completion Flag */
7057#define USART_ISR_RXFT_Pos (26U)
7058#define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
7059#define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO Threshold Flag */
7060#define USART_ISR_TXFT_Pos (27U)
7061#define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
7062#define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO Threshold Flag */
7063
7064/******************* Bit definition for USART_ICR register ******************/
7065#define USART_ICR_PECF_Pos (0U)
7066#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
7067#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
7068#define USART_ICR_FECF_Pos (1U)
7069#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
7070#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
7071#define USART_ICR_NECF_Pos (2U)
7072#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */
7073#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
7074#define USART_ICR_ORECF_Pos (3U)
7075#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
7076#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
7077#define USART_ICR_IDLECF_Pos (4U)
7078#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
7079#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
7080#define USART_ICR_TXFECF_Pos (5U)
7081#define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
7082#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO Empty Clear Flag */
7083#define USART_ICR_TCCF_Pos (6U)
7084#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
7085#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
7086#define USART_ICR_TCBGTCF_Pos (7U)
7087#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
7088#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
7089#define USART_ICR_LBDCF_Pos (8U)
7090#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
7091#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
7092#define USART_ICR_CTSCF_Pos (9U)
7093#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
7094#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
7095#define USART_ICR_RTOCF_Pos (11U)
7096#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
7097#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
7098#define USART_ICR_EOBCF_Pos (12U)
7099#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
7100#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
7101#define USART_ICR_UDRCF_Pos (13U)
7102#define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
7103#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */
7104#define USART_ICR_CMCF_Pos (17U)
7105#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
7106#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
7107#define USART_ICR_WUCF_Pos (20U)
7108#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
7109#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
7110
7111/******************* Bit definition for USART_RDR register ******************/
7112#define USART_RDR_RDR_Pos (0U)
7113#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
7114#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
7115
7116/******************* Bit definition for USART_TDR register ******************/
7117#define USART_TDR_TDR_Pos (0U)
7118#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
7119#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
7120
7121/******************* Bit definition for USART_PRESC register ****************/
7122#define USART_PRESC_PRESCALER_Pos (0U)
7123#define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
7124#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
7125#define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
7126#define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
7127#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
7128#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
7129
7130
7131
7132/******************************************************************************/
7133/* */
7134/* Window WATCHDOG */
7135/* */
7136/******************************************************************************/
7137/******************* Bit definition for WWDG_CR register ********************/
7138#define WWDG_CR_T_Pos (0U)
7139#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
7140#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
7141#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
7142#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
7143#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
7144#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
7145#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
7146#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
7147#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
7148
7149#define WWDG_CR_WDGA_Pos (7U)
7150#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
7151#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
7152
7153/******************* Bit definition for WWDG_CFR register *******************/
7154#define WWDG_CFR_W_Pos (0U)
7155#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
7156#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
7157#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
7158#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
7159#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
7160#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
7161#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
7162#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
7163#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
7164
7165#define WWDG_CFR_WDGTB_Pos (11U)
7166#define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */
7167#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */
7168#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */
7169#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */
7170#define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */
7171
7172#define WWDG_CFR_EWI_Pos (9U)
7173#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
7174#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
7175
7176/******************* Bit definition for WWDG_SR register ********************/
7177#define WWDG_SR_EWIF_Pos (0U)
7178#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
7179#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
7180
7181/******************************************************************************/
7182/* */
7183/* Debug MCU */
7184/* */
7185/******************************************************************************/
7186/******************** Bit definition for DBG_IDCODE register *************/
7187#define DBG_IDCODE_DEV_ID_Pos (0U)
7188#define DBG_IDCODE_DEV_ID_Msk (0xFFFUL << DBG_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
7189#define DBG_IDCODE_DEV_ID DBG_IDCODE_DEV_ID_Msk
7190#define DBG_IDCODE_REV_ID_Pos (16U)
7191#define DBG_IDCODE_REV_ID_Msk (0xFFFFUL << DBG_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
7192#define DBG_IDCODE_REV_ID DBG_IDCODE_REV_ID_Msk
7193
7194/******************** Bit definition for DBG_CR register *****************/
7195#define DBG_CR_DBG_STOP_Pos (1U)
7196#define DBG_CR_DBG_STOP_Msk (0x1UL << DBG_CR_DBG_STOP_Pos) /*!< 0x00000002 */
7197#define DBG_CR_DBG_STOP DBG_CR_DBG_STOP_Msk
7198#define DBG_CR_DBG_STANDBY_Pos (2U)
7199#define DBG_CR_DBG_STANDBY_Msk (0x1UL << DBG_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
7200#define DBG_CR_DBG_STANDBY DBG_CR_DBG_STANDBY_Msk
7201
7202
7203/******************** Bit definition for DBG_APB_FZ1 register ***********/
7204#define DBG_APB_FZ1_DBG_TIM3_STOP_Pos (1U)
7205#define DBG_APB_FZ1_DBG_TIM3_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
7206#define DBG_APB_FZ1_DBG_TIM3_STOP DBG_APB_FZ1_DBG_TIM3_STOP_Msk
7207#define DBG_APB_FZ1_DBG_TIM6_STOP_Pos (4U)
7208#define DBG_APB_FZ1_DBG_TIM6_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
7209#define DBG_APB_FZ1_DBG_TIM6_STOP DBG_APB_FZ1_DBG_TIM6_STOP_Msk
7210#define DBG_APB_FZ1_DBG_TIM7_STOP_Pos (5U)
7211#define DBG_APB_FZ1_DBG_TIM7_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
7212#define DBG_APB_FZ1_DBG_TIM7_STOP DBG_APB_FZ1_DBG_TIM7_STOP_Msk
7213#define DBG_APB_FZ1_DBG_RTC_STOP_Pos (10U)
7214#define DBG_APB_FZ1_DBG_RTC_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
7215#define DBG_APB_FZ1_DBG_RTC_STOP DBG_APB_FZ1_DBG_RTC_STOP_Msk
7216#define DBG_APB_FZ1_DBG_WWDG_STOP_Pos (11U)
7217#define DBG_APB_FZ1_DBG_WWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
7218#define DBG_APB_FZ1_DBG_WWDG_STOP DBG_APB_FZ1_DBG_WWDG_STOP_Msk
7219#define DBG_APB_FZ1_DBG_IWDG_STOP_Pos (12U)
7220#define DBG_APB_FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
7221#define DBG_APB_FZ1_DBG_IWDG_STOP DBG_APB_FZ1_DBG_IWDG_STOP_Msk
7222#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos (21U)
7223#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos) /*!< 0x00200000 */
7224#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk
7225
7226/******************** Bit definition for DBG_APB_FZ2 register ************/
7227#define DBG_APB_FZ2_DBG_TIM1_STOP_Pos (11U)
7228#define DBG_APB_FZ2_DBG_TIM1_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
7229#define DBG_APB_FZ2_DBG_TIM1_STOP DBG_APB_FZ2_DBG_TIM1_STOP_Msk
7230#define DBG_APB_FZ2_DBG_TIM14_STOP_Pos (15U)
7231#define DBG_APB_FZ2_DBG_TIM14_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM14_STOP_Pos) /*!< 0x00008000 */
7232#define DBG_APB_FZ2_DBG_TIM14_STOP DBG_APB_FZ2_DBG_TIM14_STOP_Msk
7233#define DBG_APB_FZ2_DBG_TIM15_STOP_Pos (16U)
7234#define DBG_APB_FZ2_DBG_TIM15_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
7235#define DBG_APB_FZ2_DBG_TIM15_STOP DBG_APB_FZ2_DBG_TIM15_STOP_Msk
7236#define DBG_APB_FZ2_DBG_TIM16_STOP_Pos (17U)
7237#define DBG_APB_FZ2_DBG_TIM16_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
7238#define DBG_APB_FZ2_DBG_TIM16_STOP DBG_APB_FZ2_DBG_TIM16_STOP_Msk
7239#define DBG_APB_FZ2_DBG_TIM17_STOP_Pos (18U)
7240#define DBG_APB_FZ2_DBG_TIM17_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
7241#define DBG_APB_FZ2_DBG_TIM17_STOP DBG_APB_FZ2_DBG_TIM17_STOP_Msk
7242
7243
7244/** @addtogroup Exported_macros
7245 * @{
7246 */
7247
7248/******************************* ADC Instances ********************************/
7249#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
7250
7251#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
7252
7253
7254
7255
7256/******************************* CRC Instances ********************************/
7257#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
7258
7259
7260/******************************** DMA Instances *******************************/
7261#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
7262 ((INSTANCE) == DMA1_Channel2) || \
7263 ((INSTANCE) == DMA1_Channel3) || \
7264 ((INSTANCE) == DMA1_Channel4) || \
7265 ((INSTANCE) == DMA1_Channel5) || \
7266 ((INSTANCE) == DMA1_Channel6) || \
7267 ((INSTANCE) == DMA1_Channel7))
7268
7269/******************************** DMAMUX Instances ****************************/
7270#define IS_DMAMUX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMAMUX1)
7271
7272#define IS_DMAMUX_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
7273 ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
7274 ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
7275 ((INSTANCE) == DMAMUX1_RequestGenerator3))
7276
7277/******************************* GPIO Instances *******************************/
7278#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
7279 ((INSTANCE) == GPIOB) || \
7280 ((INSTANCE) == GPIOC) || \
7281 ((INSTANCE) == GPIOD) || \
7282 ((INSTANCE) == GPIOF))
7283
7284/******************************* GPIO AF Instances ****************************/
7285#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
7286
7287/**************************** GPIO Lock Instances *****************************/
7288#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
7289 ((INSTANCE) == GPIOB) || \
7290 ((INSTANCE) == GPIOC))
7291
7292/******************************** I2C Instances *******************************/
7293#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
7294 ((INSTANCE) == I2C2))
7295
7296
7297/****************************** RTC Instances *********************************/
7298#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
7299
7300/****************************** SMBUS Instances *******************************/
7301#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
7302
7303/****************************** WAKEUP_FROMSTOP Instances *******************************/
7304#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
7305
7306/******************************** SPI Instances *******************************/
7307#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
7308 ((INSTANCE) == SPI2))
7309/******************************** SPI Instances *******************************/
7310#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
7311
7312
7313/****************** TIM Instances : All supported instances *******************/
7314#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7315 ((INSTANCE) == TIM3) || \
7316 ((INSTANCE) == TIM6) || \
7317 ((INSTANCE) == TIM7) || \
7318 ((INSTANCE) == TIM14) || \
7319 ((INSTANCE) == TIM15) || \
7320 ((INSTANCE) == TIM16) || \
7321 ((INSTANCE) == TIM17))
7322
7323/****************** TIM Instances : supporting 32 bits counter ****************/
7324#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0)
7325
7326/****************** TIM Instances : supporting the break function *************/
7327#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7328 ((INSTANCE) == TIM15) || \
7329 ((INSTANCE) == TIM16) || \
7330 ((INSTANCE) == TIM17))
7331
7332/************** TIM Instances : supporting Break source selection *************/
7333#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7334 ((INSTANCE) == TIM15) || \
7335 ((INSTANCE) == TIM16) || \
7336 ((INSTANCE) == TIM17))
7337
7338/****************** TIM Instances : supporting 2 break inputs *****************/
7339#define IS_TIM_BKIN2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
7340
7341/************* TIM Instances : at least 1 capture/compare channel *************/
7342#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7343 ((INSTANCE) == TIM3) || \
7344 ((INSTANCE) == TIM14) || \
7345 ((INSTANCE) == TIM15) || \
7346 ((INSTANCE) == TIM16) || \
7347 ((INSTANCE) == TIM17))
7348
7349/************ TIM Instances : at least 2 capture/compare channels *************/
7350#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7351 ((INSTANCE) == TIM3) || \
7352 ((INSTANCE) == TIM15))
7353
7354/************ TIM Instances : at least 3 capture/compare channels *************/
7355#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7356 ((INSTANCE) == TIM3))
7357
7358/************ TIM Instances : at least 4 capture/compare channels *************/
7359#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7360 ((INSTANCE) == TIM3))
7361
7362/****************** TIM Instances : at least 5 capture/compare channels *******/
7363#define IS_TIM_CC5_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
7364
7365/****************** TIM Instances : at least 6 capture/compare channels *******/
7366#define IS_TIM_CC6_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
7367
7368/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
7369#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7370 ((INSTANCE) == TIM15) || \
7371 ((INSTANCE) == TIM16) || \
7372 ((INSTANCE) == TIM17))
7373
7374/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
7375#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7376 ((INSTANCE) == TIM3) || \
7377 ((INSTANCE) == TIM6) || \
7378 ((INSTANCE) == TIM7) || \
7379 ((INSTANCE) == TIM15) || \
7380 ((INSTANCE) == TIM16) || \
7381 ((INSTANCE) == TIM17))
7382
7383/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
7384#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7385 ((INSTANCE) == TIM3) || \
7386 ((INSTANCE) == TIM14) || \
7387 ((INSTANCE) == TIM15) || \
7388 ((INSTANCE) == TIM16) || \
7389 ((INSTANCE) == TIM17))
7390
7391/******************** TIM Instances : DMA burst feature ***********************/
7392#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7393 ((INSTANCE) == TIM3) || \
7394 ((INSTANCE) == TIM15) || \
7395 ((INSTANCE) == TIM16) || \
7396 ((INSTANCE) == TIM17))
7397
7398/******************* TIM Instances : output(s) available **********************/
7399#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
7400 ((((INSTANCE) == TIM1) && \
7401 (((CHANNEL) == TIM_CHANNEL_1) || \
7402 ((CHANNEL) == TIM_CHANNEL_2) || \
7403 ((CHANNEL) == TIM_CHANNEL_3) || \
7404 ((CHANNEL) == TIM_CHANNEL_4) || \
7405 ((CHANNEL) == TIM_CHANNEL_5) || \
7406 ((CHANNEL) == TIM_CHANNEL_6))) \
7407 || \
7408 (((INSTANCE) == TIM3) && \
7409 (((CHANNEL) == TIM_CHANNEL_1) || \
7410 ((CHANNEL) == TIM_CHANNEL_2) || \
7411 ((CHANNEL) == TIM_CHANNEL_3) || \
7412 ((CHANNEL) == TIM_CHANNEL_4))) \
7413 || \
7414 (((INSTANCE) == TIM14) && \
7415 (((CHANNEL) == TIM_CHANNEL_1))) \
7416 || \
7417 (((INSTANCE) == TIM15) && \
7418 (((CHANNEL) == TIM_CHANNEL_1) || \
7419 ((CHANNEL) == TIM_CHANNEL_2))) \
7420 || \
7421 (((INSTANCE) == TIM16) && \
7422 (((CHANNEL) == TIM_CHANNEL_1))) \
7423 || \
7424 (((INSTANCE) == TIM17) && \
7425 (((CHANNEL) == TIM_CHANNEL_1))))
7426
7427/****************** TIM Instances : supporting complementary output(s) ********/
7428#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
7429 ((((INSTANCE) == TIM1) && \
7430 (((CHANNEL) == TIM_CHANNEL_1) || \
7431 ((CHANNEL) == TIM_CHANNEL_2) || \
7432 ((CHANNEL) == TIM_CHANNEL_3))) \
7433 || \
7434 (((INSTANCE) == TIM15) && \
7435 ((CHANNEL) == TIM_CHANNEL_1)) \
7436 || \
7437 (((INSTANCE) == TIM16) && \
7438 ((CHANNEL) == TIM_CHANNEL_1)) \
7439 || \
7440 (((INSTANCE) == TIM17) && \
7441 ((CHANNEL) == TIM_CHANNEL_1)))
7442
7443/****************** TIM Instances : supporting clock division *****************/
7444#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7445 ((INSTANCE) == TIM3) || \
7446 ((INSTANCE) == TIM14) || \
7447 ((INSTANCE) == TIM15) || \
7448 ((INSTANCE) == TIM16) || \
7449 ((INSTANCE) == TIM17))
7450
7451/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
7452#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7453 ((INSTANCE) == TIM3))
7454
7455/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
7456#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7457 ((INSTANCE) == TIM3))
7458
7459/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
7460#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7461 ((INSTANCE) == TIM3) || \
7462 ((INSTANCE) == TIM15))
7463
7464/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
7465#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7466 ((INSTANCE) == TIM3) || \
7467 ((INSTANCE) == TIM15))
7468
7469/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
7470#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
7471
7472/****************** TIM Instances : supporting commutation event generation ***/
7473#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7474 ((INSTANCE) == TIM15) || \
7475 ((INSTANCE) == TIM16) || \
7476 ((INSTANCE) == TIM17))
7477
7478/****************** TIM Instances : supporting counting mode selection ********/
7479#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7480 ((INSTANCE) == TIM3))
7481
7482/****************** TIM Instances : supporting encoder interface **************/
7483#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7484 ((INSTANCE) == TIM3))
7485
7486/****************** TIM Instances : supporting Hall sensor interface **********/
7487#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7488 ((INSTANCE) == TIM3))
7489
7490/**************** TIM Instances : external trigger input available ************/
7491#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7492 ((INSTANCE) == TIM3))
7493
7494/************* TIM Instances : supporting ETR source selection ***************/
7495#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7496 ((INSTANCE) == TIM3))
7497
7498/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
7499#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7500 ((INSTANCE) == TIM3) || \
7501 ((INSTANCE) == TIM6) || \
7502 ((INSTANCE) == TIM7) || \
7503 ((INSTANCE) == TIM15))
7504
7505/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
7506#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7507 ((INSTANCE) == TIM3) || \
7508 ((INSTANCE) == TIM15))
7509
7510/****************** TIM Instances : supporting OCxREF clear *******************/
7511#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7512 ((INSTANCE) == TIM3))
7513
7514/****************** TIM Instances : remapping capability **********************/
7515#define IS_TIM_REMAP_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
7516
7517/****************** TIM Instances : supporting repetition counter *************/
7518#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7519 ((INSTANCE) == TIM15) || \
7520 ((INSTANCE) == TIM16) || \
7521 ((INSTANCE) == TIM17))
7522
7523/****************** TIM Instances : supporting synchronization ****************/
7524#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
7525
7526/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
7527#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
7528
7529/******************* TIM Instances : Timer input XOR function *****************/
7530#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
7531 ((INSTANCE) == TIM3) || \
7532 ((INSTANCE) == TIM15))
7533
7534/******************* TIM Instances : Timer input selection ********************/
7535#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM14) || \
7536 ((INSTANCE) == TIM15) || \
7537 ((INSTANCE) == TIM16) || \
7538 ((INSTANCE) == TIM17))
7539
7540/************ TIM Instances : Advanced timers ********************************/
7541#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
7542
7543/******************** UART Instances : Asynchronous mode **********************/
7544#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7545 ((INSTANCE) == USART2) || \
7546 ((INSTANCE) == USART3) || \
7547 ((INSTANCE) == USART4))
7548
7549/******************** USART Instances : Synchronous mode **********************/
7550#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7551 ((INSTANCE) == USART2) || \
7552 ((INSTANCE) == USART3) || \
7553 ((INSTANCE) == USART4))
7554
7555/****************** UART Instances : Hardware Flow control ********************/
7556#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7557 ((INSTANCE) == USART2) || \
7558 ((INSTANCE) == USART3) || \
7559 ((INSTANCE) == USART4))
7560
7561/********************* USART Instances : Smard card mode ***********************/
7562#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7563 ((INSTANCE) == USART2))
7564
7565/****************** UART Instances : Auto Baud Rate detection ****************/
7566#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7567 ((INSTANCE) == USART2))
7568
7569/******************** UART Instances : Half-Duplex mode **********************/
7570#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7571 ((INSTANCE) == USART2) || \
7572 ((INSTANCE) == USART3) || \
7573 ((INSTANCE) == USART4))
7574
7575/******************** UART Instances : LIN mode **********************/
7576#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7577 ((INSTANCE) == USART2))
7578
7579/******************** UART Instances : Wake-up from Stop mode **********************/
7580#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7581 ((INSTANCE) == USART2))
7582
7583/****************** UART Instances : Driver Enable *****************/
7584#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7585 ((INSTANCE) == USART2) || \
7586 ((INSTANCE) == USART3) || \
7587 ((INSTANCE) == USART4))
7588
7589/****************** UART Instances : SPI Slave selection mode ***************/
7590#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7591 ((INSTANCE) == USART2) || \
7592 ((INSTANCE) == USART3) || \
7593 ((INSTANCE) == USART4))
7594
7595
7596/****************** UART Instances : Driver Enable *****************/
7597#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7598 ((INSTANCE) == USART2))
7599
7600/*********************** UART Instances : IRDA mode ***************************/
7601#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7602 ((INSTANCE) == USART2))
7603
7604#define IS_LPUART_INSTANCE(INSTANCE) (0U)
7605
7606/****************************** IWDG Instances ********************************/
7607#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
7608
7609/****************************** WWDG Instances ********************************/
7610#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
7611
7612
7613/**
7614 * @}
7615 */
7616
7617 /**
7618 * @}
7619 */
7620
7621/**
7622 * @}
7623 */
7624
7625#ifdef __cplusplus
7626}
7627#endif /* __cplusplus */
7628
7629#endif /* STM32G070xx_H */
7630
7631/**
7632 * @}
7633 */
7634
7635 /**
7636 * @}
7637 */
7638
7639/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 22:57:38 +0100