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1/**
2 ******************************************************************************
3 * @file stm32g071xx.h
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
6 * This file contains all the peripheral register's definitions, bits
7 * definitions and memory mapping for stm32g071xx devices.
8 *
9 * This file contains:
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral's registers hardware
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
18 * All rights reserved.</center></h2>
19 *
20 * This software component is licensed by ST under BSD 3-Clause license,
21 * the "License"; You may not use this file except in compliance with the
22 * License. You may obtain a copy of the License at:
23 * opensource.org/licenses/BSD-3-Clause
24 *
25 ******************************************************************************
26 */
27
28/** @addtogroup CMSIS_Device
29 * @{
30 */
31
32/** @addtogroup stm32g071xx
33 * @{
34 */
35
36#ifndef STM32G071xx_H
37#define STM32G071xx_H
38
39#ifdef __cplusplus
40 extern "C" {
41#endif /* __cplusplus */
42
43/** @addtogroup Configuration_section_for_CMSIS
44 * @{
45 */
46
47/**
48 * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
49 */
50#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */
51#define __MPU_PRESENT 1 /*!< STM32G0xx provides an MPU */
52#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */
53#define __NVIC_PRIO_BITS 2 /*!< STM32G0xx uses 2 Bits for the Priority Levels */
54#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
55
56/**
57 * @}
58 */
59
60/** @addtogroup Peripheral_interrupt_number_definition
61 * @{
62 */
63
64/**
65 * @brief stm32g071xx Interrupt Number Definition, according to the selected device
66 * in @ref Library_configuration_section
67 */
68
69/*!< Interrupt Number Definition */
70typedef enum
71{
72/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/
73 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
74 HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
75 SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
76 PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
77 SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
78/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/
79 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
80 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt(EXTI line 16) */
81 RTC_TAMP_IRQn = 2, /*!< RTC interrupt through the EXTI line 19 & 21 */
82 FLASH_IRQn = 3, /*!< FLASH global Interrupt */
83 RCC_IRQn = 4, /*!< RCC global Interrupt */
84 EXTI0_1_IRQn = 5, /*!< EXTI 0 and 1 Interrupts */
85 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
86 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
87 UCPD1_2_IRQn = 8, /*!< UCPD1 and UCPD2 global Interrupt */
88 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
89 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
90 DMA1_Ch4_7_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 and DMAMUX1 Overrun Interrupts */
91 ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts (combined with EXTI 17 & 18) */
92 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
93 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
94 TIM2_IRQn = 15, /*!< TIM2 Interrupt */
95 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
96 TIM6_DAC_LPTIM1_IRQn = 17, /*!< TIM6, DAC and LPTIM1 global Interrupts */
97 TIM7_LPTIM2_IRQn = 18, /*!< TIM7 and LPTIM2 global Interrupt */
98 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
99 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
100 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
101 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
102 I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */
103 I2C2_IRQn = 24, /*!< I2C2 Interrupt */
104 SPI1_IRQn = 25, /*!< SPI1 Interrupt */
105 SPI2_IRQn = 26, /*!< SPI2 Interrupt */
106 USART1_IRQn = 27, /*!< USART1 Interrupt */
107 USART2_IRQn = 28, /*!< USART2 Interrupt */
108 USART3_4_LPUART1_IRQn = 29, /*!< USART3, USART4 and LPUART1 globlal Interrupts (combined with EXTI 28) */
109 CEC_IRQn = 30, /*!< CEC Interrupt(combined with EXTI 27) */
110} IRQn_Type;
111
112/**
113 * @}
114 */
115
116#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
117#include "system_stm32g0xx.h"
118#include <stdint.h>
119
120/** @addtogroup Peripheral_registers_structures
121 * @{
122 */
123
124/**
125 * @brief Analog to Digital Converter
126 */
127typedef struct
128{
129 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
130 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
131 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
132 __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */
133 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
134 __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */
135 uint32_t RESERVED1; /*!< Reserved, 0x18 */
136 uint32_t RESERVED2; /*!< Reserved, 0x1C */
137 __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
138 __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
139 __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */
140 __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */
141 uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */
142 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
143 uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */
144 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */
145 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */
146 uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */
147 __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */
148} ADC_TypeDef;
149
150typedef struct
151{
152 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
153} ADC_Common_TypeDef;
154
155/**
156 * @brief HDMI-CEC
157 */
158typedef struct
159{
160 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
161 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
162 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
163 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
164 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
165 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
166}CEC_TypeDef;
167
168/**
169 * @brief Comparator
170 */
171typedef struct
172{
173 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
174} COMP_TypeDef;
175
176typedef struct
177{
178 __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */
179 __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */
180} COMP_Common_TypeDef;
181
182/**
183 * @brief CRC calculation unit
184 */
185typedef struct
186{
187 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
188 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
189 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
190 uint32_t RESERVED1; /*!< Reserved, 0x0C */
191 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
192 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
193} CRC_TypeDef;
194
195/**
196 * @brief Digital to Analog Converter
197 */
198typedef struct
199{
200 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
201 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
202 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
203 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
204 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
205 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
206 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
207 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
208 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
209 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
210 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
211 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
212 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
213 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
214 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
215 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
216 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
217 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
218 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
219 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
220} DAC_TypeDef;
221
222/**
223 * @brief Debug MCU
224 */
225typedef struct
226{
227 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
228 __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */
229 __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */
230 __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */
231} DBG_TypeDef;
232
233/**
234 * @brief DMA Controller
235 */
236typedef struct
237{
238 __IO uint32_t CCR; /*!< DMA channel x configuration register */
239 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
240 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
241 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
242} DMA_Channel_TypeDef;
243
244typedef struct
245{
246 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
247 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
248} DMA_TypeDef;
249
250/**
251 * @brief DMA Multiplexer
252 */
253typedef struct
254{
255 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */
256}DMAMUX_Channel_TypeDef;
257
258typedef struct
259{
260 __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */
261 __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */
262}DMAMUX_ChannelStatus_TypeDef;
263
264typedef struct
265{
266 __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */
267}DMAMUX_RequestGen_TypeDef;
268
269typedef struct
270{
271 __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */
272 __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */
273}DMAMUX_RequestGenStatus_TypeDef;
274
275/**
276 * @brief Asynch Interrupt/Event Controller (EXTI)
277 */
278typedef struct
279{
280 __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */
281 __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */
282 __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */
283 __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */
284 __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */
285 uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */
286 uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */
287 uint32_t RESERVED3[11]; /*!< Reserved 3, 0x34 -- 0x5C */
288 __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */
289 uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */
290 __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */
291 __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */
292 uint32_t RESERVED5[2]; /*!< Reserved 5, 0x88 -- 0x8C */
293 __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */
294 __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */
295} EXTI_TypeDef;
296
297/**
298 * @brief FLASH Registers
299 */
300typedef struct
301{
302 __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */
303 uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */
304 __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */
305 __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */
306 __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */
307 __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */
308 __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
309 uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
310 __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */
311 __IO uint32_t PCROP1ASR; /*!< FLASH Bank PCROP area A Start address register, Address offset: 0x24 */
312 __IO uint32_t PCROP1AER; /*!< FLASH Bank PCROP area A End address register, Address offset: 0x28 */
313 __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */
314 __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */
315 __IO uint32_t PCROP1BSR; /*!< FLASH Bank PCROP area B Start address register, Address offset: 0x34 */
316 __IO uint32_t PCROP1BER; /*!< FLASH Bank PCROP area B End address register, Address offset: 0x38 */
317 uint32_t RESERVED3[17];/*!< Reserved3, Address offset: 0x3C */
318 __IO uint32_t SECR; /*!< FLASH security register , Address offset: 0x80 */
319} FLASH_TypeDef;
320
321/**
322 * @brief General Purpose I/O
323 */
324typedef struct
325{
326 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
327 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
328 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
329 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
330 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
331 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
332 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
333 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
334 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
335 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
336} GPIO_TypeDef;
337
338
339/**
340 * @brief Inter-integrated Circuit Interface
341 */
342typedef struct
343{
344 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
345 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
346 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
347 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
348 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
349 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
350 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
351 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
352 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
353 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
354 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
355} I2C_TypeDef;
356
357/**
358 * @brief Independent WATCHDOG
359 */
360typedef struct
361{
362 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
363 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
364 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
365 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
366 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
367} IWDG_TypeDef;
368
369/**
370 * @brief LPTIMER
371 */
372typedef struct
373{
374 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
375 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
376 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
377 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
378 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
379 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
380 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
381 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
382 __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x20 */
383 __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */
384} LPTIM_TypeDef;
385
386
387/**
388 * @brief Power Control
389 */
390typedef struct
391{
392 __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */
393 __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */
394 __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */
395 __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */
396 __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */
397 __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */
398 __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */
399 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
400 __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */
401 __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */
402 __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */
403 __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */
404 __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */
405 __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */
406 __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */
407 __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */
408 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x40 */
409 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x44 */
410 __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */
411 __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */
412} PWR_TypeDef;
413
414/**
415 * @brief Reset and Clock Control
416 */
417typedef struct
418{
419 __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */
420 __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */
421 __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */
422 __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */
423 __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */
424 __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
425 __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */
426 __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */
427 __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */
428 __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */
429 __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */
430 __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */
431 __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */
432 __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */
433 __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */
434 __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */
435 __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */
436 __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */
437 __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */
438 __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */
439 __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */
440 __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */
441 __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */
442 __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x5C */
443 __IO uint32_t CSR; /*!< RCC Unregulated Domain Clock Control and Status Register, Address offset: 0x60 */
444} RCC_TypeDef;
445
446/**
447 * @brief Real-Time Clock
448 */
449typedef struct
450{
451 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
452 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
453 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
454 __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
455 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
456 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
457 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
458 uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */
459 uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */
460 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
461 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
462 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
463 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
464 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
465 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
466 uint32_t RESERVED2; /*!< Reserved Address offset: 0x1C */
467 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
468 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
469 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
470 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
471 __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
472 __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */
473 uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */
474 __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */
475 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */
476} RTC_TypeDef;
477
478/**
479 * @brief Tamper and backup registers
480 */
481typedef struct
482{
483 __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */
484 __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */
485 uint32_t RESERVED0; /*!< Reserved Address offset: 0x08 */
486 __IO uint32_t FLTCR; /*!< Reserved Address offset: 0x0C */
487 uint32_t RESERVED1[7]; /*!< Reserved Address offset: 0x10 -- 0x28 */
488 __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */
489 __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */
490 __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register, Address offset: 0x34 */
491 uint32_t RESERVED2; /*!< Reserved Address offset: 0x38 */
492 __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */
493 uint32_t RESERVED3[48]; /*!< Reserved Address offset: 0x54 -- 0xFC */
494 __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
495 __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
496 __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
497 __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
498 __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
499} TAMP_TypeDef;
500
501 /**
502 * @brief Serial Peripheral Interface
503 */
504typedef struct
505{
506 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
507 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
508 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
509 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
510 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
511 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
512 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
513 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
514 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
515} SPI_TypeDef;
516
517/**
518 * @brief System configuration controller
519 */
520typedef struct
521{
522 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
523 uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */
524 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
525 uint32_t RESERVED1[25]; /*!< Reserved 0x1C */
526 __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */
527} SYSCFG_TypeDef;
528
529/**
530 * @brief TIM
531 */
532typedef struct
533{
534 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
535 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
536 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
537 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
538 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
539 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
540 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
541 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
542 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
543 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
544 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
545 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
546 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
547 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
548 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
549 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
550 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
551 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
552 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
553 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
554 __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */
555 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
556 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
557 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
558 __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */
559 __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */
560 __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
561} TIM_TypeDef;
562
563/**
564 * @brief Universal Synchronous Asynchronous Receiver Transmitter
565 */
566typedef struct
567{
568 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
569 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
570 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
571 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
572 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
573 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
574 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
575 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
576 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
577 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
578 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
579 __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
580} USART_TypeDef;
581
582/**
583 * @brief VREFBUF
584 */
585typedef struct
586{
587 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
588 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
589} VREFBUF_TypeDef;
590
591/**
592 * @brief Window WATCHDOG
593 */
594typedef struct
595{
596 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
597 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
598 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
599} WWDG_TypeDef;
600
601
602/**
603 * @brief UCPD
604 */
605typedef struct
606{
607 __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */
608 __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */
609 __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */
610 __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */
611 __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */
612 __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */
613 __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */
614 __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */
615 __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */
616 __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */
617 __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */
618 __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */
619 __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */
620 __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */
621 __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
622
623} UCPD_TypeDef;
624
625/**
626 * @}
627 */
628
629/** @addtogroup Peripheral_memory_map
630 * @{
631 */
632#define FLASH_BASE (0x08000000UL) /*!< FLASH base address */
633#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */
634#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
635#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */
636
637#define SRAM_SIZE_MAX (0x00008000UL) /*!< maximum SRAM size (up to 32 KBytes) */
638
639/*!< Peripheral memory map */
640#define APBPERIPH_BASE (PERIPH_BASE)
641#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
642
643/*!< APB peripherals */
644
645#define TIM2_BASE (APBPERIPH_BASE + 0UL)
646#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL)
647#define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL)
648#define TIM7_BASE (APBPERIPH_BASE + 0x00001400UL)
649#define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL)
650#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
651#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
652#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
653#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL)
654#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
655#define USART3_BASE (APBPERIPH_BASE + 0x00004800UL)
656#define USART4_BASE (APBPERIPH_BASE + 0x00004C00UL)
657#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
658#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL)
659#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
660#define DAC1_BASE (APBPERIPH_BASE + 0x00007400UL)
661#define DAC_BASE (APBPERIPH_BASE + 0x00007400UL) /* Kept for legacy purpose */
662#define CEC_BASE (APBPERIPH_BASE + 0x00007800UL)
663#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL)
664#define LPUART1_BASE (APBPERIPH_BASE + 0x00008000UL)
665#define LPTIM2_BASE (APBPERIPH_BASE + 0x00009400UL)
666#define UCPD1_BASE (APBPERIPH_BASE + 0x0000A000UL)
667#define UCPD2_BASE (APBPERIPH_BASE + 0x0000A400UL)
668#define TAMP_BASE (APBPERIPH_BASE + 0x0000B000UL)
669#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
670#define VREFBUF_BASE (APBPERIPH_BASE + 0x00010030UL)
671#define COMP1_BASE (SYSCFG_BASE + 0x0200UL)
672#define COMP2_BASE (SYSCFG_BASE + 0x0204UL)
673#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
674#define ADC1_COMMON_BASE (APBPERIPH_BASE + 0x00012708UL)
675#define ADC_BASE (ADC1_COMMON_BASE) /* Kept for legacy purpose */
676#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL)
677#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
678#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL)
679#define TIM15_BASE (APBPERIPH_BASE + 0x00014000UL)
680#define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL)
681#define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL)
682#define DBG_BASE (APBPERIPH_BASE + 0x00015800UL)
683
684
685/*!< AHB peripherals */
686#define DMA1_BASE (AHBPERIPH_BASE)
687#define DMAMUX1_BASE (AHBPERIPH_BASE + 0x00000800UL)
688#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
689#define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL)
690#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL)
691#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
692
693
694#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
695#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
696#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
697#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
698#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
699#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
700#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
701
702#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
703#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL)
704#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL)
705#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL)
706#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL)
707#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL)
708#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL)
709
710#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL)
711#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL)
712#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL)
713#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL)
714
715#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL)
716#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL)
717#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC)
718
719/*!< IOPORT */
720#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL)
721#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL)
722#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL)
723#define GPIOD_BASE (IOPORT_BASE + 0x00000C00UL)
724#define GPIOF_BASE (IOPORT_BASE + 0x00001400UL)
725
726/*!< Device Electronic Signature */
727#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */
728#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */
729#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */
730
731/**
732 * @}
733 */
734
735/** @addtogroup Peripheral_declaration
736 * @{
737 */
738#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
739#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
740#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
741#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
742#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
743#define RTC ((RTC_TypeDef *) RTC_BASE)
744#define TAMP ((TAMP_TypeDef *) TAMP_BASE)
745#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
746#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
747#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
748#define USART2 ((USART_TypeDef *) USART2_BASE)
749#define USART3 ((USART_TypeDef *) USART3_BASE)
750#define USART4 ((USART_TypeDef *) USART4_BASE)
751#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
752#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
753#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
754#define PWR ((PWR_TypeDef *) PWR_BASE)
755#define RCC ((RCC_TypeDef *) RCC_BASE)
756#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
757#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
758#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
759#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
760#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
761#define CEC ((CEC_TypeDef *) CEC_BASE)
762#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
763#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
764#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
765#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
766#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
767#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
768#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
769#define USART1 ((USART_TypeDef *) USART1_BASE)
770#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
771#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
772#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
773#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
774
775#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
776#define CRC ((CRC_TypeDef *) CRC_BASE)
777#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
778#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
779#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
780#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
781#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
782#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
783#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
784#define ADC (ADC1_COMMON) /* Kept for legacy purpose */
785
786
787#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE)
788#define UCPD2 ((UCPD_TypeDef *) UCPD2_BASE)
789
790#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
791#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
792#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
793#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
794#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
795#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
796#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
797
798#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
799#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
800#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
801#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
802#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
803#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
804#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
805#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
806
807#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
808#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
809#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
810#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
811
812#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
813#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
814#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE)
815
816#define DBG ((DBG_TypeDef *) DBG_BASE)
817
818/**
819 * @}
820 */
821
822/** @addtogroup Exported_constants
823 * @{
824 */
825
826 /** @addtogroup Peripheral_Registers_Bits_Definition
827 * @{
828 */
829
830/******************************************************************************/
831/* Peripheral Registers Bits Definition */
832/******************************************************************************/
833
834/******************************************************************************/
835/* */
836/* Analog to Digital Converter (ADC) */
837/* */
838/******************************************************************************/
839/******************** Bit definition for ADC_ISR register *******************/
840#define ADC_ISR_ADRDY_Pos (0U)
841#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
842#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
843#define ADC_ISR_EOSMP_Pos (1U)
844#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
845#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
846#define ADC_ISR_EOC_Pos (2U)
847#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
848#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
849#define ADC_ISR_EOS_Pos (3U)
850#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
851#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
852#define ADC_ISR_OVR_Pos (4U)
853#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
854#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
855#define ADC_ISR_AWD1_Pos (7U)
856#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
857#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
858#define ADC_ISR_AWD2_Pos (8U)
859#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
860#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
861#define ADC_ISR_AWD3_Pos (9U)
862#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
863#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
864#define ADC_ISR_EOCAL_Pos (11U)
865#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
866#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */
867#define ADC_ISR_CCRDY_Pos (13U)
868#define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */
869#define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */
870
871/* Legacy defines */
872#define ADC_ISR_EOSEQ (ADC_ISR_EOS)
873
874/******************** Bit definition for ADC_IER register *******************/
875#define ADC_IER_ADRDYIE_Pos (0U)
876#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
877#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
878#define ADC_IER_EOSMPIE_Pos (1U)
879#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
880#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
881#define ADC_IER_EOCIE_Pos (2U)
882#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
883#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
884#define ADC_IER_EOSIE_Pos (3U)
885#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
886#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
887#define ADC_IER_OVRIE_Pos (4U)
888#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
889#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
890#define ADC_IER_AWD1IE_Pos (7U)
891#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
892#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
893#define ADC_IER_AWD2IE_Pos (8U)
894#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
895#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
896#define ADC_IER_AWD3IE_Pos (9U)
897#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
898#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
899#define ADC_IER_EOCALIE_Pos (11U)
900#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
901#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */
902#define ADC_IER_CCRDYIE_Pos (13U)
903#define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */
904#define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */
905
906/* Legacy defines */
907#define ADC_IER_EOSEQIE (ADC_IER_EOSIE)
908
909/******************** Bit definition for ADC_CR register ********************/
910#define ADC_CR_ADEN_Pos (0U)
911#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
912#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
913#define ADC_CR_ADDIS_Pos (1U)
914#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
915#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
916#define ADC_CR_ADSTART_Pos (2U)
917#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
918#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
919#define ADC_CR_ADSTP_Pos (4U)
920#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
921#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
922#define ADC_CR_ADVREGEN_Pos (28U)
923#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
924#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
925#define ADC_CR_ADCAL_Pos (31U)
926#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
927#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
928
929/******************** Bit definition for ADC_CFGR1 register *****************/
930#define ADC_CFGR1_DMAEN_Pos (0U)
931#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
932#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */
933#define ADC_CFGR1_DMACFG_Pos (1U)
934#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
935#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */
936
937#define ADC_CFGR1_SCANDIR_Pos (2U)
938#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
939#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */
940
941#define ADC_CFGR1_RES_Pos (3U)
942#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
943#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */
944#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
945#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
946
947#define ADC_CFGR1_ALIGN_Pos (5U)
948#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
949#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */
950
951#define ADC_CFGR1_EXTSEL_Pos (6U)
952#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
953#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */
954#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
955#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
956#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
957
958#define ADC_CFGR1_EXTEN_Pos (10U)
959#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
960#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */
961#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
962#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
963
964#define ADC_CFGR1_OVRMOD_Pos (12U)
965#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
966#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */
967#define ADC_CFGR1_CONT_Pos (13U)
968#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
969#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */
970#define ADC_CFGR1_WAIT_Pos (14U)
971#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
972#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */
973#define ADC_CFGR1_AUTOFF_Pos (15U)
974#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
975#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */
976#define ADC_CFGR1_DISCEN_Pos (16U)
977#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
978#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
979#define ADC_CFGR1_CHSELRMOD_Pos (21U)
980#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */
981#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */
982
983#define ADC_CFGR1_AWD1SGL_Pos (22U)
984#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
985#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
986#define ADC_CFGR1_AWD1EN_Pos (23U)
987#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
988#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
989
990#define ADC_CFGR1_AWD1CH_Pos (26U)
991#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */
992#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
993#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */
994#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */
995#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */
996#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */
997#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */
998
999/* Legacy defines */
1000#define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT)
1001
1002/******************** Bit definition for ADC_CFGR2 register *****************/
1003#define ADC_CFGR2_OVSE_Pos (0U)
1004#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
1005#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
1006
1007#define ADC_CFGR2_OVSR_Pos (2U)
1008#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
1009#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
1010#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
1011#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
1012#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
1013
1014#define ADC_CFGR2_OVSS_Pos (5U)
1015#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
1016#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
1017#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
1018#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
1019#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
1020#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
1021
1022#define ADC_CFGR2_TOVS_Pos (9U)
1023#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */
1024#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1025
1026#define ADC_CFGR2_LFTRIG_Pos (29U)
1027#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */
1028#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */
1029
1030#define ADC_CFGR2_CKMODE_Pos (30U)
1031#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
1032#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */
1033#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
1034#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
1035
1036/******************** Bit definition for ADC_SMPR register ******************/
1037#define ADC_SMPR_SMP1_Pos (0U)
1038#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */
1039#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */
1040#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */
1041#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */
1042#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */
1043
1044#define ADC_SMPR_SMP2_Pos (4U)
1045#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */
1046#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */
1047#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */
1048#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */
1049#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */
1050
1051#define ADC_SMPR_SMPSEL_Pos (8U)
1052#define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */
1053#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */
1054#define ADC_SMPR_SMPSEL0_Pos (8U)
1055#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */
1056#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */
1057#define ADC_SMPR_SMPSEL1_Pos (9U)
1058#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */
1059#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */
1060#define ADC_SMPR_SMPSEL2_Pos (10U)
1061#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */
1062#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */
1063#define ADC_SMPR_SMPSEL3_Pos (11U)
1064#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */
1065#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */
1066#define ADC_SMPR_SMPSEL4_Pos (12U)
1067#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */
1068#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */
1069#define ADC_SMPR_SMPSEL5_Pos (13U)
1070#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */
1071#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */
1072#define ADC_SMPR_SMPSEL6_Pos (14U)
1073#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */
1074#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */
1075#define ADC_SMPR_SMPSEL7_Pos (15U)
1076#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */
1077#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */
1078#define ADC_SMPR_SMPSEL8_Pos (16U)
1079#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */
1080#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */
1081#define ADC_SMPR_SMPSEL9_Pos (17U)
1082#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */
1083#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */
1084#define ADC_SMPR_SMPSEL10_Pos (18U)
1085#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */
1086#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */
1087#define ADC_SMPR_SMPSEL11_Pos (19U)
1088#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */
1089#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */
1090#define ADC_SMPR_SMPSEL12_Pos (20U)
1091#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */
1092#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */
1093#define ADC_SMPR_SMPSEL13_Pos (21U)
1094#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */
1095#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */
1096#define ADC_SMPR_SMPSEL14_Pos (22U)
1097#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */
1098#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */
1099#define ADC_SMPR_SMPSEL15_Pos (23U)
1100#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */
1101#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */
1102#define ADC_SMPR_SMPSEL16_Pos (24U)
1103#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */
1104#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */
1105#define ADC_SMPR_SMPSEL17_Pos (25U)
1106#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */
1107#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */
1108#define ADC_SMPR_SMPSEL18_Pos (26U)
1109#define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */
1110#define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */
1111
1112/******************** Bit definition for ADC_TR1 register *******************/
1113#define ADC_TR1_LT1_Pos (0U)
1114#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
1115#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
1116#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
1117#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
1118#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
1119#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
1120#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
1121#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
1122#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
1123#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
1124#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
1125#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
1126#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
1127#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
1128
1129#define ADC_TR1_HT1_Pos (16U)
1130#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
1131#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
1132#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
1133#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
1134#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
1135#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
1136#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
1137#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
1138#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
1139#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
1140#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
1141#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
1142#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
1143#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
1144
1145/******************** Bit definition for ADC_TR2 register *******************/
1146#define ADC_TR2_LT2_Pos (0U)
1147#define ADC_TR2_LT2_Msk (0xFFFUL << ADC_TR2_LT2_Pos) /*!< 0x00000FFF */
1148#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
1149#define ADC_TR2_LT2_0 (0x001UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
1150#define ADC_TR2_LT2_1 (0x002UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
1151#define ADC_TR2_LT2_2 (0x004UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
1152#define ADC_TR2_LT2_3 (0x008UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
1153#define ADC_TR2_LT2_4 (0x010UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
1154#define ADC_TR2_LT2_5 (0x020UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
1155#define ADC_TR2_LT2_6 (0x040UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
1156#define ADC_TR2_LT2_7 (0x080UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
1157#define ADC_TR2_LT2_8 (0x100UL << ADC_TR2_LT2_Pos) /*!< 0x00000100 */
1158#define ADC_TR2_LT2_9 (0x200UL << ADC_TR2_LT2_Pos) /*!< 0x00000200 */
1159#define ADC_TR2_LT2_10 (0x400UL << ADC_TR2_LT2_Pos) /*!< 0x00000400 */
1160#define ADC_TR2_LT2_11 (0x800UL << ADC_TR2_LT2_Pos) /*!< 0x00000800 */
1161
1162#define ADC_TR2_HT2_Pos (16U)
1163#define ADC_TR2_HT2_Msk (0xFFFUL << ADC_TR2_HT2_Pos) /*!< 0x0FFF0000 */
1164#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
1165#define ADC_TR2_HT2_0 (0x001UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
1166#define ADC_TR2_HT2_1 (0x002UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
1167#define ADC_TR2_HT2_2 (0x004UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
1168#define ADC_TR2_HT2_3 (0x008UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
1169#define ADC_TR2_HT2_4 (0x010UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
1170#define ADC_TR2_HT2_5 (0x020UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
1171#define ADC_TR2_HT2_6 (0x040UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
1172#define ADC_TR2_HT2_7 (0x080UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
1173#define ADC_TR2_HT2_8 (0x100UL << ADC_TR2_HT2_Pos) /*!< 0x01000000 */
1174#define ADC_TR2_HT2_9 (0x200UL << ADC_TR2_HT2_Pos) /*!< 0x02000000 */
1175#define ADC_TR2_HT2_10 (0x400UL << ADC_TR2_HT2_Pos) /*!< 0x04000000 */
1176#define ADC_TR2_HT2_11 (0x800UL << ADC_TR2_HT2_Pos) /*!< 0x08000000 */
1177
1178/******************** Bit definition for ADC_CHSELR register ****************/
1179#define ADC_CHSELR_CHSEL_Pos (0U)
1180#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
1181#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
1182#define ADC_CHSELR_CHSEL18_Pos (18U)
1183#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
1184#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
1185#define ADC_CHSELR_CHSEL17_Pos (17U)
1186#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
1187#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
1188#define ADC_CHSELR_CHSEL16_Pos (16U)
1189#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */
1190#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
1191#define ADC_CHSELR_CHSEL15_Pos (15U)
1192#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
1193#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
1194#define ADC_CHSELR_CHSEL14_Pos (14U)
1195#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
1196#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
1197#define ADC_CHSELR_CHSEL13_Pos (13U)
1198#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
1199#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
1200#define ADC_CHSELR_CHSEL12_Pos (12U)
1201#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
1202#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
1203#define ADC_CHSELR_CHSEL11_Pos (11U)
1204#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
1205#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
1206#define ADC_CHSELR_CHSEL10_Pos (10U)
1207#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
1208#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
1209#define ADC_CHSELR_CHSEL9_Pos (9U)
1210#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
1211#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
1212#define ADC_CHSELR_CHSEL8_Pos (8U)
1213#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
1214#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
1215#define ADC_CHSELR_CHSEL7_Pos (7U)
1216#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
1217#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
1218#define ADC_CHSELR_CHSEL6_Pos (6U)
1219#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
1220#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
1221#define ADC_CHSELR_CHSEL5_Pos (5U)
1222#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
1223#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
1224#define ADC_CHSELR_CHSEL4_Pos (4U)
1225#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
1226#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
1227#define ADC_CHSELR_CHSEL3_Pos (3U)
1228#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
1229#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
1230#define ADC_CHSELR_CHSEL2_Pos (2U)
1231#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
1232#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
1233#define ADC_CHSELR_CHSEL1_Pos (1U)
1234#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
1235#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
1236#define ADC_CHSELR_CHSEL0_Pos (0U)
1237#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
1238#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
1239
1240#define ADC_CHSELR_SQ_ALL_Pos (0U)
1241#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */
1242#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */
1243
1244#define ADC_CHSELR_SQ8_Pos (28U)
1245#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */
1246#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */
1247#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */
1248#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */
1249#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */
1250#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */
1251
1252#define ADC_CHSELR_SQ7_Pos (24U)
1253#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */
1254#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */
1255#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */
1256#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */
1257#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */
1258#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */
1259
1260#define ADC_CHSELR_SQ6_Pos (20U)
1261#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */
1262#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */
1263#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */
1264#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */
1265#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */
1266#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */
1267
1268#define ADC_CHSELR_SQ5_Pos (16U)
1269#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */
1270#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */
1271#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */
1272#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */
1273#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */
1274#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */
1275
1276#define ADC_CHSELR_SQ4_Pos (12U)
1277#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */
1278#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */
1279#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */
1280#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */
1281#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */
1282#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */
1283
1284#define ADC_CHSELR_SQ3_Pos (8U)
1285#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */
1286#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */
1287#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */
1288#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */
1289#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */
1290#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */
1291
1292#define ADC_CHSELR_SQ2_Pos (4U)
1293#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */
1294#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */
1295#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */
1296#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */
1297#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */
1298#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */
1299
1300#define ADC_CHSELR_SQ1_Pos (0U)
1301#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */
1302#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */
1303#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */
1304#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */
1305#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */
1306#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */
1307
1308/******************** Bit definition for ADC_TR3 register *******************/
1309#define ADC_TR3_LT3_Pos (0U)
1310#define ADC_TR3_LT3_Msk (0xFFFUL << ADC_TR3_LT3_Pos) /*!< 0x00000FFF */
1311#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
1312#define ADC_TR3_LT3_0 (0x001UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
1313#define ADC_TR3_LT3_1 (0x002UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
1314#define ADC_TR3_LT3_2 (0x004UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
1315#define ADC_TR3_LT3_3 (0x008UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
1316#define ADC_TR3_LT3_4 (0x010UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
1317#define ADC_TR3_LT3_5 (0x020UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
1318#define ADC_TR3_LT3_6 (0x040UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
1319#define ADC_TR3_LT3_7 (0x080UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
1320#define ADC_TR3_LT3_8 (0x100UL << ADC_TR3_LT3_Pos) /*!< 0x00000100 */
1321#define ADC_TR3_LT3_9 (0x200UL << ADC_TR3_LT3_Pos) /*!< 0x00000200 */
1322#define ADC_TR3_LT3_10 (0x400UL << ADC_TR3_LT3_Pos) /*!< 0x00000400 */
1323#define ADC_TR3_LT3_11 (0x800UL << ADC_TR3_LT3_Pos) /*!< 0x00000800 */
1324
1325#define ADC_TR3_HT3_Pos (16U)
1326#define ADC_TR3_HT3_Msk (0xFFFUL << ADC_TR3_HT3_Pos) /*!< 0x0FFF0000 */
1327#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
1328#define ADC_TR3_HT3_0 (0x001UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
1329#define ADC_TR3_HT3_1 (0x002UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
1330#define ADC_TR3_HT3_2 (0x004UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
1331#define ADC_TR3_HT3_3 (0x008UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
1332#define ADC_TR3_HT3_4 (0x010UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
1333#define ADC_TR3_HT3_5 (0x020UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
1334#define ADC_TR3_HT3_6 (0x040UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
1335#define ADC_TR3_HT3_7 (0x080UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
1336#define ADC_TR3_HT3_8 (0x100UL << ADC_TR3_HT3_Pos) /*!< 0x01000000 */
1337#define ADC_TR3_HT3_9 (0x200UL << ADC_TR3_HT3_Pos) /*!< 0x02000000 */
1338#define ADC_TR3_HT3_10 (0x400UL << ADC_TR3_HT3_Pos) /*!< 0x04000000 */
1339#define ADC_TR3_HT3_11 (0x800UL << ADC_TR3_HT3_Pos) /*!< 0x08000000 */
1340
1341/******************** Bit definition for ADC_DR register ********************/
1342#define ADC_DR_DATA_Pos (0U)
1343#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
1344#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
1345#define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */
1346#define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */
1347#define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */
1348#define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */
1349#define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */
1350#define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */
1351#define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */
1352#define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */
1353#define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */
1354#define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */
1355#define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */
1356#define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */
1357#define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */
1358#define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */
1359#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */
1360#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */
1361
1362/******************** Bit definition for ADC_AWD2CR register ****************/
1363#define ADC_AWD2CR_AWD2CH_Pos (0U)
1364#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
1365#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
1366#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
1367#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
1368#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
1369#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
1370#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
1371#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
1372#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
1373#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
1374#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
1375#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
1376#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
1377#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
1378#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
1379#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
1380#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
1381#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
1382#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
1383#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
1384#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
1385
1386/******************** Bit definition for ADC_AWD3CR register ****************/
1387#define ADC_AWD3CR_AWD3CH_Pos (0U)
1388#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
1389#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
1390#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
1391#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
1392#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
1393#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
1394#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
1395#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
1396#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
1397#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
1398#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
1399#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
1400#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
1401#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
1402#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
1403#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
1404#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
1405#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
1406#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
1407#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
1408#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
1409
1410/******************** Bit definition for ADC_CALFACT register ***************/
1411#define ADC_CALFACT_CALFACT_Pos (0U)
1412#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
1413#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */
1414#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */
1415#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */
1416#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */
1417#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */
1418#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */
1419#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */
1420#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */
1421
1422/************************* ADC Common registers *****************************/
1423/******************** Bit definition for ADC_CCR register *******************/
1424#define ADC_CCR_PRESC_Pos (18U)
1425#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
1426#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
1427#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
1428#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
1429#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
1430#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
1431
1432#define ADC_CCR_VREFEN_Pos (22U)
1433#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
1434#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
1435#define ADC_CCR_TSEN_Pos (23U)
1436#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
1437#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
1438#define ADC_CCR_VBATEN_Pos (24U)
1439#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
1440#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
1441
1442#define ADC_CCR_LFMEN_Pos (25U)
1443#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
1444#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */
1445
1446/******************************************************************************/
1447/* */
1448/* HDMI-CEC (CEC) */
1449/* */
1450/******************************************************************************/
1451
1452/******************* Bit definition for CEC_CR register *********************/
1453#define CEC_CR_CECEN_Pos (0U)
1454#define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
1455#define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
1456#define CEC_CR_TXSOM_Pos (1U)
1457#define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
1458#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
1459#define CEC_CR_TXEOM_Pos (2U)
1460#define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
1461#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
1462
1463/******************* Bit definition for CEC_CFGR register *******************/
1464#define CEC_CFGR_SFT_Pos (0U)
1465#define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
1466#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
1467#define CEC_CFGR_RXTOL_Pos (3U)
1468#define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
1469#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
1470#define CEC_CFGR_BRESTP_Pos (4U)
1471#define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
1472#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
1473#define CEC_CFGR_BREGEN_Pos (5U)
1474#define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
1475#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
1476#define CEC_CFGR_LBPEGEN_Pos (6U)
1477#define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
1478#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error gener. */
1479#define CEC_CFGR_BRDNOGEN_Pos (7U)
1480#define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
1481#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No Error generation */
1482#define CEC_CFGR_SFTOPT_Pos (8U)
1483#define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
1484#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
1485#define CEC_CFGR_OAR_Pos (16U)
1486#define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
1487#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
1488#define CEC_CFGR_LSTN_Pos (31U)
1489#define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
1490#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
1491
1492/******************* Bit definition for CEC_TXDR register *******************/
1493#define CEC_TXDR_TXD_Pos (0U)
1494#define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
1495#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
1496
1497/******************* Bit definition for CEC_RXDR register *******************/
1498#define CEC_RXDR_RXD_Pos (0U)
1499#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */
1500#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */
1501
1502/******************* Bit definition for CEC_ISR register ********************/
1503#define CEC_ISR_RXBR_Pos (0U)
1504#define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
1505#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
1506#define CEC_ISR_RXEND_Pos (1U)
1507#define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
1508#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
1509#define CEC_ISR_RXOVR_Pos (2U)
1510#define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
1511#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
1512#define CEC_ISR_BRE_Pos (3U)
1513#define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
1514#define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
1515#define CEC_ISR_SBPE_Pos (4U)
1516#define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
1517#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
1518#define CEC_ISR_LBPE_Pos (5U)
1519#define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
1520#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
1521#define CEC_ISR_RXACKE_Pos (6U)
1522#define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
1523#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
1524#define CEC_ISR_ARBLST_Pos (7U)
1525#define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
1526#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
1527#define CEC_ISR_TXBR_Pos (8U)
1528#define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
1529#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
1530#define CEC_ISR_TXEND_Pos (9U)
1531#define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
1532#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
1533#define CEC_ISR_TXUDR_Pos (10U)
1534#define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
1535#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
1536#define CEC_ISR_TXERR_Pos (11U)
1537#define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
1538#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
1539#define CEC_ISR_TXACKE_Pos (12U)
1540#define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
1541#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
1542
1543/******************* Bit definition for CEC_IER register ********************/
1544#define CEC_IER_RXBRIE_Pos (0U)
1545#define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
1546#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
1547#define CEC_IER_RXENDIE_Pos (1U)
1548#define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
1549#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
1550#define CEC_IER_RXOVRIE_Pos (2U)
1551#define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
1552#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
1553#define CEC_IER_BREIE_Pos (3U)
1554#define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
1555#define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
1556#define CEC_IER_SBPEIE_Pos (4U)
1557#define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
1558#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable*/
1559#define CEC_IER_LBPEIE_Pos (5U)
1560#define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
1561#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
1562#define CEC_IER_RXACKEIE_Pos (6U)
1563#define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
1564#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
1565#define CEC_IER_ARBLSTIE_Pos (7U)
1566#define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
1567#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
1568#define CEC_IER_TXBRIE_Pos (8U)
1569#define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
1570#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
1571#define CEC_IER_TXENDIE_Pos (9U)
1572#define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
1573#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
1574#define CEC_IER_TXUDRIE_Pos (10U)
1575#define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
1576#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
1577#define CEC_IER_TXERRIE_Pos (11U)
1578#define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
1579#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
1580#define CEC_IER_TXACKEIE_Pos (12U)
1581#define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
1582#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
1583
1584/******************************************************************************/
1585/* */
1586/* CRC calculation unit */
1587/* */
1588/******************************************************************************/
1589/******************* Bit definition for CRC_DR register *********************/
1590#define CRC_DR_DR_Pos (0U)
1591#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
1592#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
1593
1594/******************* Bit definition for CRC_IDR register ********************/
1595#define CRC_IDR_IDR_Pos (0U)
1596#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
1597#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */
1598
1599/******************** Bit definition for CRC_CR register ********************/
1600#define CRC_CR_RESET_Pos (0U)
1601#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
1602#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
1603#define CRC_CR_POLYSIZE_Pos (3U)
1604#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
1605#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
1606#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
1607#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
1608#define CRC_CR_REV_IN_Pos (5U)
1609#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
1610#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
1611#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
1612#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
1613#define CRC_CR_REV_OUT_Pos (7U)
1614#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
1615#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
1616
1617/******************* Bit definition for CRC_INIT register *******************/
1618#define CRC_INIT_INIT_Pos (0U)
1619#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
1620#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
1621
1622/******************* Bit definition for CRC_POL register ********************/
1623#define CRC_POL_POL_Pos (0U)
1624#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
1625#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
1626
1627
1628/******************************************************************************/
1629/* */
1630/* Digital to Analog Converter */
1631/* */
1632/******************************************************************************/
1633/*
1634* @brief Specific device feature definitions
1635*/
1636#define DAC_ADDITIONAL_TRIGGERS_SUPPORT
1637
1638/******************** Bit definition for DAC_CR register ********************/
1639#define DAC_CR_EN1_Pos (0U)
1640#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
1641#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
1642#define DAC_CR_TEN1_Pos (1U)
1643#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
1644#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
1645
1646#define DAC_CR_TSEL1_Pos (2U)
1647#define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
1648#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
1649#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
1650#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
1651#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
1652#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
1653
1654#define DAC_CR_WAVE1_Pos (6U)
1655#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
1656#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
1657#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
1658#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
1659
1660#define DAC_CR_MAMP1_Pos (8U)
1661#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
1662#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
1663#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
1664#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
1665#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
1666#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
1667
1668#define DAC_CR_DMAEN1_Pos (12U)
1669#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
1670#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
1671#define DAC_CR_DMAUDRIE1_Pos (13U)
1672#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
1673#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
1674#define DAC_CR_CEN1_Pos (14U)
1675#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
1676#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
1677
1678#define DAC_CR_EN2_Pos (16U)
1679#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
1680#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
1681#define DAC_CR_TEN2_Pos (17U)
1682#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
1683#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
1684
1685#define DAC_CR_TSEL2_Pos (18U)
1686#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
1687#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
1688#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
1689#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
1690#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
1691#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
1692
1693#define DAC_CR_WAVE2_Pos (22U)
1694#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
1695#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
1696#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
1697#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
1698
1699#define DAC_CR_MAMP2_Pos (24U)
1700#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
1701#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
1702#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
1703#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
1704#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
1705#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
1706
1707#define DAC_CR_DMAEN2_Pos (28U)
1708#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
1709#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
1710#define DAC_CR_DMAUDRIE2_Pos (29U)
1711#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
1712#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
1713#define DAC_CR_CEN2_Pos (30U)
1714#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
1715#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
1716
1717/***************** Bit definition for DAC_SWTRIGR register ******************/
1718#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
1719#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
1720#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
1721#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
1722#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
1723#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
1724
1725/***************** Bit definition for DAC_DHR12R1 register ******************/
1726#define DAC_DHR12R1_DACC1DHR_Pos (0U)
1727#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
1728#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
1729
1730/***************** Bit definition for DAC_DHR12L1 register ******************/
1731#define DAC_DHR12L1_DACC1DHR_Pos (4U)
1732#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
1733#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
1734
1735/****************** Bit definition for DAC_DHR8R1 register ******************/
1736#define DAC_DHR8R1_DACC1DHR_Pos (0U)
1737#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
1738#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
1739
1740/***************** Bit definition for DAC_DHR12R2 register ******************/
1741#define DAC_DHR12R2_DACC2DHR_Pos (0U)
1742#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
1743#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
1744
1745/***************** Bit definition for DAC_DHR12L2 register ******************/
1746#define DAC_DHR12L2_DACC2DHR_Pos (4U)
1747#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
1748#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
1749
1750/****************** Bit definition for DAC_DHR8R2 register ******************/
1751#define DAC_DHR8R2_DACC2DHR_Pos (0U)
1752#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
1753#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
1754
1755/***************** Bit definition for DAC_DHR12RD register ******************/
1756#define DAC_DHR12RD_DACC1DHR_Pos (0U)
1757#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
1758#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
1759#define DAC_DHR12RD_DACC2DHR_Pos (16U)
1760#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
1761#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
1762
1763/***************** Bit definition for DAC_DHR12LD register ******************/
1764#define DAC_DHR12LD_DACC1DHR_Pos (4U)
1765#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
1766#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
1767#define DAC_DHR12LD_DACC2DHR_Pos (20U)
1768#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
1769#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
1770
1771/****************** Bit definition for DAC_DHR8RD register ******************/
1772#define DAC_DHR8RD_DACC1DHR_Pos (0U)
1773#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
1774#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
1775#define DAC_DHR8RD_DACC2DHR_Pos (8U)
1776#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
1777#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
1778
1779/******************* Bit definition for DAC_DOR1 register *******************/
1780#define DAC_DOR1_DACC1DOR_Pos (0U)
1781#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
1782#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
1783
1784/******************* Bit definition for DAC_DOR2 register *******************/
1785#define DAC_DOR2_DACC2DOR_Pos (0U)
1786#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
1787#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
1788
1789/******************** Bit definition for DAC_SR register ********************/
1790#define DAC_SR_DMAUDR1_Pos (13U)
1791#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
1792#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
1793#define DAC_SR_CAL_FLAG1_Pos (14U)
1794#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
1795#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
1796#define DAC_SR_BWST1_Pos (15U)
1797#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
1798#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
1799
1800#define DAC_SR_DMAUDR2_Pos (29U)
1801#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
1802#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
1803#define DAC_SR_CAL_FLAG2_Pos (30U)
1804#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
1805#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
1806#define DAC_SR_BWST2_Pos (31U)
1807#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
1808#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
1809
1810/******************* Bit definition for DAC_CCR register ********************/
1811#define DAC_CCR_OTRIM1_Pos (0U)
1812#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
1813#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
1814#define DAC_CCR_OTRIM2_Pos (16U)
1815#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
1816#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
1817
1818/******************* Bit definition for DAC_MCR register *******************/
1819#define DAC_MCR_MODE1_Pos (0U)
1820#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
1821#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
1822#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
1823#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
1824#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
1825
1826#define DAC_MCR_MODE2_Pos (16U)
1827#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
1828#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
1829#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
1830#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
1831#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
1832
1833/****************** Bit definition for DAC_SHSR1 register ******************/
1834#define DAC_SHSR1_TSAMPLE1_Pos (0U)
1835#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
1836#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
1837
1838/****************** Bit definition for DAC_SHSR2 register ******************/
1839#define DAC_SHSR2_TSAMPLE2_Pos (0U)
1840#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
1841#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
1842
1843/****************** Bit definition for DAC_SHHR register ******************/
1844#define DAC_SHHR_THOLD1_Pos (0U)
1845#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
1846#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
1847#define DAC_SHHR_THOLD2_Pos (16U)
1848#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
1849#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
1850
1851/****************** Bit definition for DAC_SHRR register ******************/
1852#define DAC_SHRR_TREFRESH1_Pos (0U)
1853#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
1854#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
1855#define DAC_SHRR_TREFRESH2_Pos (16U)
1856#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
1857#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
1858
1859
1860/******************************************************************************/
1861/* */
1862/* Debug MCU */
1863/* */
1864/******************************************************************************/
1865
1866/******************************************************************************/
1867/* */
1868/* DMA Controller (DMA) */
1869/* */
1870/******************************************************************************/
1871
1872/******************* Bit definition for DMA_ISR register ********************/
1873#define DMA_ISR_GIF1_Pos (0U)
1874#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
1875#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
1876#define DMA_ISR_TCIF1_Pos (1U)
1877#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
1878#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
1879#define DMA_ISR_HTIF1_Pos (2U)
1880#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
1881#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
1882#define DMA_ISR_TEIF1_Pos (3U)
1883#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
1884#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
1885#define DMA_ISR_GIF2_Pos (4U)
1886#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
1887#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
1888#define DMA_ISR_TCIF2_Pos (5U)
1889#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
1890#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
1891#define DMA_ISR_HTIF2_Pos (6U)
1892#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
1893#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
1894#define DMA_ISR_TEIF2_Pos (7U)
1895#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
1896#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
1897#define DMA_ISR_GIF3_Pos (8U)
1898#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
1899#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
1900#define DMA_ISR_TCIF3_Pos (9U)
1901#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
1902#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
1903#define DMA_ISR_HTIF3_Pos (10U)
1904#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
1905#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
1906#define DMA_ISR_TEIF3_Pos (11U)
1907#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
1908#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
1909#define DMA_ISR_GIF4_Pos (12U)
1910#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
1911#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
1912#define DMA_ISR_TCIF4_Pos (13U)
1913#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
1914#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
1915#define DMA_ISR_HTIF4_Pos (14U)
1916#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
1917#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
1918#define DMA_ISR_TEIF4_Pos (15U)
1919#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
1920#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
1921#define DMA_ISR_GIF5_Pos (16U)
1922#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
1923#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
1924#define DMA_ISR_TCIF5_Pos (17U)
1925#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
1926#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
1927#define DMA_ISR_HTIF5_Pos (18U)
1928#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
1929#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
1930#define DMA_ISR_TEIF5_Pos (19U)
1931#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
1932#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
1933#define DMA_ISR_GIF6_Pos (20U)
1934#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
1935#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
1936#define DMA_ISR_TCIF6_Pos (21U)
1937#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
1938#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
1939#define DMA_ISR_HTIF6_Pos (22U)
1940#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
1941#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
1942#define DMA_ISR_TEIF6_Pos (23U)
1943#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
1944#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
1945#define DMA_ISR_GIF7_Pos (24U)
1946#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
1947#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
1948#define DMA_ISR_TCIF7_Pos (25U)
1949#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
1950#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
1951#define DMA_ISR_HTIF7_Pos (26U)
1952#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
1953#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
1954#define DMA_ISR_TEIF7_Pos (27U)
1955#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
1956#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
1957
1958/******************* Bit definition for DMA_IFCR register *******************/
1959#define DMA_IFCR_CGIF1_Pos (0U)
1960#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
1961#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
1962#define DMA_IFCR_CTCIF1_Pos (1U)
1963#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
1964#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
1965#define DMA_IFCR_CHTIF1_Pos (2U)
1966#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
1967#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
1968#define DMA_IFCR_CTEIF1_Pos (3U)
1969#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
1970#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
1971#define DMA_IFCR_CGIF2_Pos (4U)
1972#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
1973#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
1974#define DMA_IFCR_CTCIF2_Pos (5U)
1975#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
1976#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
1977#define DMA_IFCR_CHTIF2_Pos (6U)
1978#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
1979#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
1980#define DMA_IFCR_CTEIF2_Pos (7U)
1981#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
1982#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
1983#define DMA_IFCR_CGIF3_Pos (8U)
1984#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
1985#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
1986#define DMA_IFCR_CTCIF3_Pos (9U)
1987#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
1988#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
1989#define DMA_IFCR_CHTIF3_Pos (10U)
1990#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
1991#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
1992#define DMA_IFCR_CTEIF3_Pos (11U)
1993#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
1994#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
1995#define DMA_IFCR_CGIF4_Pos (12U)
1996#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
1997#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
1998#define DMA_IFCR_CTCIF4_Pos (13U)
1999#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
2000#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
2001#define DMA_IFCR_CHTIF4_Pos (14U)
2002#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
2003#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
2004#define DMA_IFCR_CTEIF4_Pos (15U)
2005#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
2006#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
2007#define DMA_IFCR_CGIF5_Pos (16U)
2008#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
2009#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
2010#define DMA_IFCR_CTCIF5_Pos (17U)
2011#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
2012#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
2013#define DMA_IFCR_CHTIF5_Pos (18U)
2014#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
2015#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
2016#define DMA_IFCR_CTEIF5_Pos (19U)
2017#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
2018#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
2019#define DMA_IFCR_CGIF6_Pos (20U)
2020#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
2021#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
2022#define DMA_IFCR_CTCIF6_Pos (21U)
2023#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
2024#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
2025#define DMA_IFCR_CHTIF6_Pos (22U)
2026#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
2027#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
2028#define DMA_IFCR_CTEIF6_Pos (23U)
2029#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
2030#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
2031#define DMA_IFCR_CGIF7_Pos (24U)
2032#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
2033#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
2034#define DMA_IFCR_CTCIF7_Pos (25U)
2035#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
2036#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
2037#define DMA_IFCR_CHTIF7_Pos (26U)
2038#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
2039#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
2040#define DMA_IFCR_CTEIF7_Pos (27U)
2041#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
2042#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
2043
2044/******************* Bit definition for DMA_CCR register ********************/
2045#define DMA_CCR_EN_Pos (0U)
2046#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
2047#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
2048#define DMA_CCR_TCIE_Pos (1U)
2049#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
2050#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
2051#define DMA_CCR_HTIE_Pos (2U)
2052#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
2053#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
2054#define DMA_CCR_TEIE_Pos (3U)
2055#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
2056#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
2057#define DMA_CCR_DIR_Pos (4U)
2058#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
2059#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
2060#define DMA_CCR_CIRC_Pos (5U)
2061#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
2062#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
2063#define DMA_CCR_PINC_Pos (6U)
2064#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
2065#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
2066#define DMA_CCR_MINC_Pos (7U)
2067#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
2068#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
2069
2070#define DMA_CCR_PSIZE_Pos (8U)
2071#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
2072#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
2073#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
2074#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
2075
2076#define DMA_CCR_MSIZE_Pos (10U)
2077#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
2078#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
2079#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
2080#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
2081
2082#define DMA_CCR_PL_Pos (12U)
2083#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
2084#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
2085#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
2086#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
2087
2088#define DMA_CCR_MEM2MEM_Pos (14U)
2089#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
2090#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
2091
2092/****************** Bit definition for DMA_CNDTR register *******************/
2093#define DMA_CNDTR_NDT_Pos (0U)
2094#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
2095#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
2096
2097/****************** Bit definition for DMA_CPAR register ********************/
2098#define DMA_CPAR_PA_Pos (0U)
2099#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
2100#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
2101
2102/****************** Bit definition for DMA_CMAR register ********************/
2103#define DMA_CMAR_MA_Pos (0U)
2104#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
2105#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
2106
2107/******************************************************************************/
2108/* */
2109/* DMAMUX Controller */
2110/* */
2111/******************************************************************************/
2112/******************** Bits definition for DMAMUX_CxCR register **************/
2113#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
2114#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */
2115#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */
2116#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
2117#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
2118#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
2119#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
2120#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
2121#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
2122#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
2123#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
2124#define DMAMUX_CxCR_SOIE_Pos (8U)
2125#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
2126#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */
2127#define DMAMUX_CxCR_EGE_Pos (9U)
2128#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */
2129#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */
2130#define DMAMUX_CxCR_SE_Pos (16U)
2131#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */
2132#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */
2133#define DMAMUX_CxCR_SPOL_Pos (17U)
2134#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
2135#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */
2136#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */
2137#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */
2138#define DMAMUX_CxCR_NBREQ_Pos (19U)
2139#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
2140#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */
2141#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
2142#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
2143#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
2144#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
2145#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
2146#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
2147#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
2148#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */
2149#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
2150#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
2151#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
2152#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
2153#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
2154
2155/******************* Bits definition for DMAMUX_CSR register **************/
2156#define DMAMUX_CSR_SOF0_Pos (0U)
2157#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */
2158#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */
2159#define DMAMUX_CSR_SOF1_Pos (1U)
2160#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */
2161#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */
2162#define DMAMUX_CSR_SOF2_Pos (2U)
2163#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */
2164#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */
2165#define DMAMUX_CSR_SOF3_Pos (3U)
2166#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */
2167#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Synchronization Overrun Flag 3 */
2168#define DMAMUX_CSR_SOF4_Pos (4U)
2169#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */
2170#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Synchronization Overrun Flag 4 */
2171#define DMAMUX_CSR_SOF5_Pos (5U)
2172#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */
2173#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Synchronization Overrun Flag 5 */
2174#define DMAMUX_CSR_SOF6_Pos (6U)
2175#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */
2176#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Synchronization Overrun Flag 6 */
2177
2178/******************** Bits definition for DMAMUX_CFR register **************/
2179#define DMAMUX_CFR_CSOF0_Pos (0U)
2180#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
2181#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */
2182#define DMAMUX_CFR_CSOF1_Pos (1U)
2183#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
2184#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */
2185#define DMAMUX_CFR_CSOF2_Pos (2U)
2186#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
2187#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */
2188#define DMAMUX_CFR_CSOF3_Pos (3U)
2189#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
2190#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Clear Overrun Flag 3 */
2191#define DMAMUX_CFR_CSOF4_Pos (4U)
2192#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
2193#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Clear Overrun Flag 4 */
2194#define DMAMUX_CFR_CSOF5_Pos (5U)
2195#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
2196#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Clear Overrun Flag 5 */
2197#define DMAMUX_CFR_CSOF6_Pos (6U)
2198#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
2199#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Clear Overrun Flag 6 */
2200
2201/******************** Bits definition for DMAMUX_RGxCR register ************/
2202#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
2203#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
2204#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */
2205#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
2206#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
2207#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
2208#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
2209#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
2210#define DMAMUX_RGxCR_OIE_Pos (8U)
2211#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
2212#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */
2213#define DMAMUX_RGxCR_GE_Pos (16U)
2214#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */
2215#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */
2216#define DMAMUX_RGxCR_GPOL_Pos (17U)
2217#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
2218#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */
2219#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
2220#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
2221#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
2222#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
2223#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */
2224#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
2225#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */
2226#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */
2227#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */
2228#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */
2229
2230/******************** Bits definition for DMAMUX_RGSR register **************/
2231#define DMAMUX_RGSR_OF0_Pos (0U)
2232#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */
2233#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */
2234#define DMAMUX_RGSR_OF1_Pos (1U)
2235#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */
2236#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */
2237#define DMAMUX_RGSR_OF2_Pos (2U)
2238#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */
2239#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */
2240#define DMAMUX_RGSR_OF3_Pos (3U)
2241#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */
2242#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */
2243
2244/******************** Bits definition for DMAMUX_RGCFR register **************/
2245#define DMAMUX_RGCFR_COF0_Pos (0U)
2246#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
2247#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */
2248#define DMAMUX_RGCFR_COF1_Pos (1U)
2249#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
2250#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */
2251#define DMAMUX_RGCFR_COF2_Pos (2U)
2252#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
2253#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */
2254#define DMAMUX_RGCFR_COF3_Pos (3U)
2255#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
2256#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */
2257
2258/******************************************************************************/
2259/* */
2260/* External Interrupt/Event Controller */
2261/* */
2262/******************************************************************************/
2263/****************** Bit definition for EXTI_RTSR1 register ******************/
2264#define EXTI_RTSR1_RT0_Pos (0U)
2265#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
2266#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */
2267#define EXTI_RTSR1_RT1_Pos (1U)
2268#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
2269#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */
2270#define EXTI_RTSR1_RT2_Pos (2U)
2271#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
2272#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */
2273#define EXTI_RTSR1_RT3_Pos (3U)
2274#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
2275#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */
2276#define EXTI_RTSR1_RT4_Pos (4U)
2277#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
2278#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */
2279#define EXTI_RTSR1_RT5_Pos (5U)
2280#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
2281#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */
2282#define EXTI_RTSR1_RT6_Pos (6U)
2283#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
2284#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */
2285#define EXTI_RTSR1_RT7_Pos (7U)
2286#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
2287#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */
2288#define EXTI_RTSR1_RT8_Pos (8U)
2289#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
2290#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */
2291#define EXTI_RTSR1_RT9_Pos (9U)
2292#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
2293#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */
2294#define EXTI_RTSR1_RT10_Pos (10U)
2295#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
2296#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */
2297#define EXTI_RTSR1_RT11_Pos (11U)
2298#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
2299#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */
2300#define EXTI_RTSR1_RT12_Pos (12U)
2301#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
2302#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */
2303#define EXTI_RTSR1_RT13_Pos (13U)
2304#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
2305#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */
2306#define EXTI_RTSR1_RT14_Pos (14U)
2307#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
2308#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */
2309#define EXTI_RTSR1_RT15_Pos (15U)
2310#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
2311#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */
2312#define EXTI_RTSR1_RT16_Pos (16U)
2313#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
2314#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger configuration for input line 16 */
2315#define EXTI_RTSR1_RT17_Pos (17U)
2316#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */
2317#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger configuration for input line 17 */
2318#define EXTI_RTSR1_RT18_Pos (18U)
2319#define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */
2320#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger configuration for input line 18 */
2321
2322/****************** Bit definition for EXTI_FTSR1 register ******************/
2323#define EXTI_FTSR1_FT0_Pos (0U)
2324#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
2325#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */
2326#define EXTI_FTSR1_FT1_Pos (1U)
2327#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
2328#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */
2329#define EXTI_FTSR1_FT2_Pos (2U)
2330#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
2331#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */
2332#define EXTI_FTSR1_FT3_Pos (3U)
2333#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
2334#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */
2335#define EXTI_FTSR1_FT4_Pos (4U)
2336#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
2337#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */
2338#define EXTI_FTSR1_FT5_Pos (5U)
2339#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
2340#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */
2341#define EXTI_FTSR1_FT6_Pos (6U)
2342#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
2343#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */
2344#define EXTI_FTSR1_FT7_Pos (7U)
2345#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
2346#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */
2347#define EXTI_FTSR1_FT8_Pos (8U)
2348#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
2349#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */
2350#define EXTI_FTSR1_FT9_Pos (9U)
2351#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
2352#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */
2353#define EXTI_FTSR1_FT10_Pos (10U)
2354#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
2355#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */
2356#define EXTI_FTSR1_FT11_Pos (11U)
2357#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
2358#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */
2359#define EXTI_FTSR1_FT12_Pos (12U)
2360#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
2361#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */
2362#define EXTI_FTSR1_FT13_Pos (13U)
2363#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
2364#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */
2365#define EXTI_FTSR1_FT14_Pos (14U)
2366#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
2367#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */
2368#define EXTI_FTSR1_FT15_Pos (15U)
2369#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
2370#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */
2371#define EXTI_FTSR1_FT16_Pos (16U)
2372#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
2373#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger configuration for input line 16 */
2374#define EXTI_FTSR1_FT17_Pos (17U)
2375#define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) /*!< 0x00020000 */
2376#define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk /*!< Falling trigger configuration for input line 17 */
2377#define EXTI_FTSR1_FT18_Pos (18U)
2378#define EXTI_FTSR1_FT18_Msk (0x1UL << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */
2379#define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger configuration for input line 18 */
2380
2381/****************** Bit definition for EXTI_SWIER1 register *****************/
2382#define EXTI_SWIER1_SWI0_Pos (0U)
2383#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
2384#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
2385#define EXTI_SWIER1_SWI1_Pos (1U)
2386#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
2387#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
2388#define EXTI_SWIER1_SWI2_Pos (2U)
2389#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
2390#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
2391#define EXTI_SWIER1_SWI3_Pos (3U)
2392#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
2393#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
2394#define EXTI_SWIER1_SWI4_Pos (4U)
2395#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
2396#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
2397#define EXTI_SWIER1_SWI5_Pos (5U)
2398#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
2399#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
2400#define EXTI_SWIER1_SWI6_Pos (6U)
2401#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
2402#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
2403#define EXTI_SWIER1_SWI7_Pos (7U)
2404#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
2405#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
2406#define EXTI_SWIER1_SWI8_Pos (8U)
2407#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
2408#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
2409#define EXTI_SWIER1_SWI9_Pos (9U)
2410#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
2411#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
2412#define EXTI_SWIER1_SWI10_Pos (10U)
2413#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
2414#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
2415#define EXTI_SWIER1_SWI11_Pos (11U)
2416#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
2417#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
2418#define EXTI_SWIER1_SWI12_Pos (12U)
2419#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
2420#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
2421#define EXTI_SWIER1_SWI13_Pos (13U)
2422#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
2423#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
2424#define EXTI_SWIER1_SWI14_Pos (14U)
2425#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
2426#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
2427#define EXTI_SWIER1_SWI15_Pos (15U)
2428#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
2429#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
2430#define EXTI_SWIER1_SWI16_Pos (16U)
2431#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
2432#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
2433#define EXTI_SWIER1_SWI17_Pos (17U)
2434#define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) /*!< 0x00020000 */
2435#define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk /*!< Software Interrupt on line 17 */
2436#define EXTI_SWIER1_SWI18_Pos (18U)
2437#define EXTI_SWIER1_SWI18_Msk (0x1UL << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */
2438#define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */
2439
2440/******************* Bit definition for EXTI_RPR1 register ******************/
2441#define EXTI_RPR1_RPIF0_Pos (0U)
2442#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */
2443#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */
2444#define EXTI_RPR1_RPIF1_Pos (1U)
2445#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */
2446#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */
2447#define EXTI_RPR1_RPIF2_Pos (2U)
2448#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */
2449#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */
2450#define EXTI_RPR1_RPIF3_Pos (3U)
2451#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */
2452#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */
2453#define EXTI_RPR1_RPIF4_Pos (4U)
2454#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */
2455#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */
2456#define EXTI_RPR1_RPIF5_Pos (5U)
2457#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */
2458#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */
2459#define EXTI_RPR1_RPIF6_Pos (6U)
2460#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */
2461#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */
2462#define EXTI_RPR1_RPIF7_Pos (7U)
2463#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */
2464#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */
2465#define EXTI_RPR1_RPIF8_Pos (8U)
2466#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */
2467#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */
2468#define EXTI_RPR1_RPIF9_Pos (9U)
2469#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */
2470#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */
2471#define EXTI_RPR1_RPIF10_Pos (10U)
2472#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */
2473#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */
2474#define EXTI_RPR1_RPIF11_Pos (11U)
2475#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */
2476#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */
2477#define EXTI_RPR1_RPIF12_Pos (12U)
2478#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */
2479#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */
2480#define EXTI_RPR1_RPIF13_Pos (13U)
2481#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */
2482#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */
2483#define EXTI_RPR1_RPIF14_Pos (14U)
2484#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */
2485#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */
2486#define EXTI_RPR1_RPIF15_Pos (15U)
2487#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */
2488#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */
2489#define EXTI_RPR1_RPIF16_Pos (16U)
2490#define EXTI_RPR1_RPIF16_Msk (0x1UL << EXTI_RPR1_RPIF16_Pos) /*!< 0x00010000 */
2491#define EXTI_RPR1_RPIF16 EXTI_RPR1_RPIF16_Msk /*!< Rising Pending Interrupt Flag on line 16 */
2492#define EXTI_RPR1_RPIF17_Pos (17U)
2493#define EXTI_RPR1_RPIF17_Msk (0x1UL << EXTI_RPR1_RPIF17_Pos) /*!< 0x00020000 */
2494#define EXTI_RPR1_RPIF17 EXTI_RPR1_RPIF17_Msk /*!< Rising Pending Interrupt Flag on line 17 */
2495#define EXTI_RPR1_RPIF18_Pos (18U)
2496#define EXTI_RPR1_RPIF18_Msk (0x1UL << EXTI_RPR1_RPIF18_Pos) /*!< 0x00040000 */
2497#define EXTI_RPR1_RPIF18 EXTI_RPR1_RPIF18_Msk /*!< Rising Pending Interrupt Flag on line 18 */
2498
2499/******************* Bit definition for EXTI_FPR1 register ******************/
2500#define EXTI_FPR1_FPIF0_Pos (0U)
2501#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */
2502#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */
2503#define EXTI_FPR1_FPIF1_Pos (1U)
2504#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */
2505#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */
2506#define EXTI_FPR1_FPIF2_Pos (2U)
2507#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */
2508#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */
2509#define EXTI_FPR1_FPIF3_Pos (3U)
2510#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */
2511#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */
2512#define EXTI_FPR1_FPIF4_Pos (4U)
2513#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */
2514#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */
2515#define EXTI_FPR1_FPIF5_Pos (5U)
2516#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */
2517#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */
2518#define EXTI_FPR1_FPIF6_Pos (6U)
2519#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */
2520#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */
2521#define EXTI_FPR1_FPIF7_Pos (7U)
2522#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */
2523#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */
2524#define EXTI_FPR1_FPIF8_Pos (8U)
2525#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */
2526#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */
2527#define EXTI_FPR1_FPIF9_Pos (9U)
2528#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */
2529#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */
2530#define EXTI_FPR1_FPIF10_Pos (10U)
2531#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */
2532#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */
2533#define EXTI_FPR1_FPIF11_Pos (11U)
2534#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */
2535#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */
2536#define EXTI_FPR1_FPIF12_Pos (12U)
2537#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */
2538#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */
2539#define EXTI_FPR1_FPIF13_Pos (13U)
2540#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */
2541#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */
2542#define EXTI_FPR1_FPIF14_Pos (14U)
2543#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */
2544#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */
2545#define EXTI_FPR1_FPIF15_Pos (15U)
2546#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */
2547#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */
2548#define EXTI_FPR1_FPIF16_Pos (16U)
2549#define EXTI_FPR1_FPIF16_Msk (0x1UL << EXTI_FPR1_FPIF16_Pos) /*!< 0x00010000 */
2550#define EXTI_FPR1_FPIF16 EXTI_FPR1_FPIF16_Msk /*!< Falling Pending Interrupt Flag on line 16 */
2551#define EXTI_FPR1_FPIF17_Pos (17U)
2552#define EXTI_FPR1_FPIF17_Msk (0x1UL << EXTI_FPR1_FPIF17_Pos) /*!< 0x00020000 */
2553#define EXTI_FPR1_FPIF17 EXTI_FPR1_FPIF17_Msk /*!< Falling Pending Interrupt Flag on line 17 */
2554#define EXTI_FPR1_FPIF18_Pos (18U)
2555#define EXTI_FPR1_FPIF18_Msk (0x1UL << EXTI_FPR1_FPIF18_Pos) /*!< 0x00040000 */
2556#define EXTI_FPR1_FPIF18 EXTI_FPR1_FPIF18_Msk /*!< Falling Pending Interrupt Flag on line 18 */
2557
2558/***************** Bit definition for EXTI_EXTICR1 register **************/
2559#define EXTI_EXTICR1_EXTI0_Pos (0U)
2560#define EXTI_EXTICR1_EXTI0_Msk (0x7UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */
2561#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
2562#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */
2563#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */
2564#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */
2565#define EXTI_EXTICR1_EXTI1_Pos (8U)
2566#define EXTI_EXTICR1_EXTI1_Msk (0x7UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000700 */
2567#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
2568#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */
2569#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */
2570#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */
2571#define EXTI_EXTICR1_EXTI2_Pos (16U)
2572#define EXTI_EXTICR1_EXTI2_Msk (0x7UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00070000 */
2573#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
2574#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */
2575#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */
2576#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */
2577#define EXTI_EXTICR1_EXTI3_Pos (24U)
2578#define EXTI_EXTICR1_EXTI3_Msk (0x7UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x07000000 */
2579#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
2580#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */
2581#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */
2582#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */
2583
2584/***************** Bit definition for EXTI_EXTICR2 register **************/
2585#define EXTI_EXTICR2_EXTI4_Pos (0U)
2586#define EXTI_EXTICR2_EXTI4_Msk (0x7UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */
2587#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
2588#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */
2589#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */
2590#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */
2591#define EXTI_EXTICR2_EXTI5_Pos (8U)
2592#define EXTI_EXTICR2_EXTI5_Msk (0x7UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000700 */
2593#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
2594#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */
2595#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */
2596#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */
2597#define EXTI_EXTICR2_EXTI6_Pos (16U)
2598#define EXTI_EXTICR2_EXTI6_Msk (0x7UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00070000 */
2599#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
2600#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */
2601#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */
2602#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */
2603#define EXTI_EXTICR2_EXTI7_Pos (24U)
2604#define EXTI_EXTICR2_EXTI7_Msk (0x7UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x07000000 */
2605#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
2606#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */
2607#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */
2608#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */
2609
2610/***************** Bit definition for EXTI_EXTICR3 register **************/
2611#define EXTI_EXTICR3_EXTI8_Pos (0U)
2612#define EXTI_EXTICR3_EXTI8_Msk (0x7UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */
2613#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
2614#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */
2615#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */
2616#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */
2617#define EXTI_EXTICR3_EXTI9_Pos (8U)
2618#define EXTI_EXTICR3_EXTI9_Msk (0x7UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000700 */
2619#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
2620#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */
2621#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */
2622#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */
2623#define EXTI_EXTICR3_EXTI10_Pos (16U)
2624#define EXTI_EXTICR3_EXTI10_Msk (0x7UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00070000 */
2625#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
2626#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */
2627#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */
2628#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */
2629#define EXTI_EXTICR3_EXTI11_Pos (24U)
2630#define EXTI_EXTICR3_EXTI11_Msk (0x7UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x07000000 */
2631#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
2632#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */
2633#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */
2634#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */
2635
2636/***************** Bit definition for EXTI_EXTICR4 register **************/
2637#define EXTI_EXTICR4_EXTI12_Pos (0U)
2638#define EXTI_EXTICR4_EXTI12_Msk (0x7UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
2639#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
2640#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */
2641#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */
2642#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */
2643#define EXTI_EXTICR4_EXTI13_Pos (8U)
2644#define EXTI_EXTICR4_EXTI13_Msk (0x7UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000700 */
2645#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
2646#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */
2647#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */
2648#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */
2649#define EXTI_EXTICR4_EXTI14_Pos (16U)
2650#define EXTI_EXTICR4_EXTI14_Msk (0x7UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00070000 */
2651#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
2652#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */
2653#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */
2654#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */
2655#define EXTI_EXTICR4_EXTI15_Pos (24U)
2656#define EXTI_EXTICR4_EXTI15_Msk (0x7UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x07000000 */
2657#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
2658#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */
2659#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */
2660#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */
2661
2662/******************* Bit definition for EXTI_IMR1 register ******************/
2663#define EXTI_IMR1_IM0_Pos (0U)
2664#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
2665#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
2666#define EXTI_IMR1_IM1_Pos (1U)
2667#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
2668#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
2669#define EXTI_IMR1_IM2_Pos (2U)
2670#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
2671#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
2672#define EXTI_IMR1_IM3_Pos (3U)
2673#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
2674#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
2675#define EXTI_IMR1_IM4_Pos (4U)
2676#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
2677#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
2678#define EXTI_IMR1_IM5_Pos (5U)
2679#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
2680#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
2681#define EXTI_IMR1_IM6_Pos (6U)
2682#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
2683#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
2684#define EXTI_IMR1_IM7_Pos (7U)
2685#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
2686#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
2687#define EXTI_IMR1_IM8_Pos (8U)
2688#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
2689#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
2690#define EXTI_IMR1_IM9_Pos (9U)
2691#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
2692#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
2693#define EXTI_IMR1_IM10_Pos (10U)
2694#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
2695#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
2696#define EXTI_IMR1_IM11_Pos (11U)
2697#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
2698#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
2699#define EXTI_IMR1_IM12_Pos (12U)
2700#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
2701#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
2702#define EXTI_IMR1_IM13_Pos (13U)
2703#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
2704#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
2705#define EXTI_IMR1_IM14_Pos (14U)
2706#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
2707#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
2708#define EXTI_IMR1_IM15_Pos (15U)
2709#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
2710#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
2711#define EXTI_IMR1_IM16_Pos (16U)
2712#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
2713#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
2714#define EXTI_IMR1_IM17_Pos (17U)
2715#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
2716#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
2717#define EXTI_IMR1_IM18_Pos (18U)
2718#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
2719#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
2720#define EXTI_IMR1_IM19_Pos (19U)
2721#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
2722#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
2723#define EXTI_IMR1_IM20_Pos (20U)
2724#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
2725#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
2726#define EXTI_IMR1_IM21_Pos (21U)
2727#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
2728#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
2729#define EXTI_IMR1_IM22_Pos (22U)
2730#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
2731#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
2732#define EXTI_IMR1_IM23_Pos (23U)
2733#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
2734#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
2735#define EXTI_IMR1_IM24_Pos (24U)
2736#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
2737#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
2738#define EXTI_IMR1_IM25_Pos (25U)
2739#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
2740#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
2741#define EXTI_IMR1_IM26_Pos (26U)
2742#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
2743#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
2744#define EXTI_IMR1_IM27_Pos (27U)
2745#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
2746#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
2747#define EXTI_IMR1_IM28_Pos (28U)
2748#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
2749#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
2750#define EXTI_IMR1_IM29_Pos (29U)
2751#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
2752#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
2753#define EXTI_IMR1_IM30_Pos (30U)
2754#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
2755#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
2756#define EXTI_IMR1_IM31_Pos (31U)
2757#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
2758#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
2759#define EXTI_IMR1_IM_Pos (0U)
2760#define EXTI_IMR1_IM_Msk (0xFEAFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0xFEAFFFFF */
2761#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
2762
2763/******************* Bit definition for EXTI_IMR2 register ******************/
2764#define EXTI_IMR2_IM32_Pos (0U)
2765#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
2766#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
2767#define EXTI_IMR2_IM33_Pos (1U)
2768#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
2769#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
2770#define EXTI_IMR2_IM_Pos (0U)
2771#define EXTI_IMR2_IM_Msk (0x3UL << EXTI_IMR2_IM_Pos) /*!< 0x00000003 */
2772#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask All */
2773
2774/******************* Bit definition for EXTI_EMR1 register ******************/
2775#define EXTI_EMR1_EM0_Pos (0U)
2776#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
2777#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
2778#define EXTI_EMR1_EM1_Pos (1U)
2779#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
2780#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
2781#define EXTI_EMR1_EM2_Pos (2U)
2782#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
2783#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
2784#define EXTI_EMR1_EM3_Pos (3U)
2785#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
2786#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
2787#define EXTI_EMR1_EM4_Pos (4U)
2788#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
2789#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
2790#define EXTI_EMR1_EM5_Pos (5U)
2791#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
2792#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
2793#define EXTI_EMR1_EM6_Pos (6U)
2794#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
2795#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
2796#define EXTI_EMR1_EM7_Pos (7U)
2797#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
2798#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
2799#define EXTI_EMR1_EM8_Pos (8U)
2800#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
2801#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
2802#define EXTI_EMR1_EM9_Pos (9U)
2803#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
2804#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
2805#define EXTI_EMR1_EM10_Pos (10U)
2806#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
2807#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
2808#define EXTI_EMR1_EM11_Pos (11U)
2809#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
2810#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
2811#define EXTI_EMR1_EM12_Pos (12U)
2812#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
2813#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
2814#define EXTI_EMR1_EM13_Pos (13U)
2815#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
2816#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
2817#define EXTI_EMR1_EM14_Pos (14U)
2818#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
2819#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
2820#define EXTI_EMR1_EM15_Pos (15U)
2821#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
2822#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
2823#define EXTI_EMR1_EM16_Pos (16U)
2824#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
2825#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
2826#define EXTI_EMR1_EM17_Pos (17U)
2827#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
2828#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
2829#define EXTI_EMR1_EM18_Pos (18U)
2830#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
2831#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
2832#define EXTI_EMR1_EM19_Pos (19U)
2833#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
2834#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
2835#define EXTI_EMR1_EM21_Pos (21U)
2836#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
2837#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
2838#define EXTI_EMR1_EM23_Pos (23U)
2839#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
2840#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
2841#define EXTI_EMR1_EM25_Pos (25U)
2842#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
2843#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
2844#define EXTI_EMR1_EM26_Pos (26U)
2845#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
2846#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
2847#define EXTI_EMR1_EM27_Pos (27U)
2848#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
2849#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
2850#define EXTI_EMR1_EM28_Pos (28U)
2851#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
2852#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
2853#define EXTI_EMR1_EM29_Pos (29U)
2854#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
2855#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
2856#define EXTI_EMR1_EM30_Pos (30U)
2857#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
2858#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
2859#define EXTI_EMR1_EM31_Pos (31U)
2860#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
2861#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
2862
2863/******************* Bit definition for EXTI_EMR2 register ******************/
2864#define EXTI_EMR2_EM32_Pos (0U)
2865#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
2866#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32 */
2867#define EXTI_EMR2_EM33_Pos (1U)
2868#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
2869#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
2870
2871
2872/******************************************************************************/
2873/* */
2874/* FLASH */
2875/* */
2876/******************************************************************************/
2877#define GPIO_NRST_CONFIG_SUPPORT /*!< GPIO feature available only on specific devices: Configure NRST pin */
2878#define FLASH_SECURABLE_MEMORY_SUPPORT /*!< Flash feature available only on specific devices: allow to secure memory */
2879#define FLASH_PCROP_SUPPORT /*!< Flash feature available only on specific devices: proprietary code read protection areas selected by option */
2880
2881/******************* Bits definition for FLASH_ACR register *****************/
2882#define FLASH_ACR_LATENCY_Pos (0U)
2883#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
2884#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
2885#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
2886#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
2887#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
2888#define FLASH_ACR_PRFTEN_Pos (8U)
2889#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
2890#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
2891#define FLASH_ACR_ICEN_Pos (9U)
2892#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
2893#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
2894#define FLASH_ACR_ICRST_Pos (11U)
2895#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
2896#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
2897#define FLASH_ACR_PROGEMPTY_Pos (16U)
2898#define FLASH_ACR_PROGEMPTY_Msk (0x1UL << FLASH_ACR_PROGEMPTY_Pos) /*!< 0x00010000 */
2899#define FLASH_ACR_PROGEMPTY FLASH_ACR_PROGEMPTY_Msk
2900#define FLASH_ACR_DBG_SWEN_Pos (18U)
2901#define FLASH_ACR_DBG_SWEN_Msk (0x1UL << FLASH_ACR_DBG_SWEN_Pos) /*!< 0x00040000 */
2902#define FLASH_ACR_DBG_SWEN FLASH_ACR_DBG_SWEN_Msk
2903
2904/******************* Bits definition for FLASH_SR register ******************/
2905#define FLASH_SR_EOP_Pos (0U)
2906#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
2907#define FLASH_SR_EOP FLASH_SR_EOP_Msk
2908#define FLASH_SR_OPERR_Pos (1U)
2909#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
2910#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
2911#define FLASH_SR_PROGERR_Pos (3U)
2912#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
2913#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
2914#define FLASH_SR_WRPERR_Pos (4U)
2915#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
2916#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
2917#define FLASH_SR_PGAERR_Pos (5U)
2918#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
2919#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
2920#define FLASH_SR_SIZERR_Pos (6U)
2921#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
2922#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
2923#define FLASH_SR_PGSERR_Pos (7U)
2924#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
2925#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
2926#define FLASH_SR_MISERR_Pos (8U)
2927#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
2928#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
2929#define FLASH_SR_FASTERR_Pos (9U)
2930#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
2931#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
2932#define FLASH_SR_RDERR_Pos (14U)
2933#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
2934#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
2935#define FLASH_SR_OPTVERR_Pos (15U)
2936#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
2937#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
2938#define FLASH_SR_BSY1_Pos (16U)
2939#define FLASH_SR_BSY1_Msk (0x1UL << FLASH_SR_BSY1_Pos) /*!< 0x00010000 */
2940#define FLASH_SR_BSY1 FLASH_SR_BSY1_Msk
2941#define FLASH_SR_CFGBSY_Pos (18U)
2942#define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */
2943#define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk
2944
2945/******************* Bits definition for FLASH_CR register ******************/
2946#define FLASH_CR_PG_Pos (0U)
2947#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
2948#define FLASH_CR_PG FLASH_CR_PG_Msk
2949#define FLASH_CR_PER_Pos (1U)
2950#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */
2951#define FLASH_CR_PER FLASH_CR_PER_Msk
2952#define FLASH_CR_MER1_Pos (2U)
2953#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
2954#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
2955#define FLASH_CR_PNB_Pos (3U)
2956#define FLASH_CR_PNB_Msk (0x3FUL << FLASH_CR_PNB_Pos) /*!< 0x000001F8 */
2957#define FLASH_CR_PNB FLASH_CR_PNB_Msk
2958#define FLASH_CR_STRT_Pos (16U)
2959#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
2960#define FLASH_CR_STRT FLASH_CR_STRT_Msk
2961#define FLASH_CR_OPTSTRT_Pos (17U)
2962#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
2963#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
2964#define FLASH_CR_FSTPG_Pos (18U)
2965#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
2966#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
2967#define FLASH_CR_EOPIE_Pos (24U)
2968#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
2969#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
2970#define FLASH_CR_ERRIE_Pos (25U)
2971#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
2972#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
2973#define FLASH_CR_RDERRIE_Pos (26U)
2974#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
2975#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
2976#define FLASH_CR_OBL_LAUNCH_Pos (27U)
2977#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
2978#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
2979#define FLASH_CR_SEC_PROT_Pos (28U)
2980#define FLASH_CR_SEC_PROT_Msk (0x1UL << FLASH_CR_SEC_PROT_Pos) /*!< 0x10000000 */
2981#define FLASH_CR_SEC_PROT FLASH_CR_SEC_PROT_Msk
2982#define FLASH_CR_OPTLOCK_Pos (30U)
2983#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
2984#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
2985#define FLASH_CR_LOCK_Pos (31U)
2986#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
2987#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
2988
2989/******************* Bits definition for FLASH_ECCR register ****************/
2990#define FLASH_ECCR_ADDR_ECC_Pos (0U)
2991#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x00003FFF */
2992#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
2993#define FLASH_ECCR_SYSF_ECC_Pos (20U)
2994#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
2995#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
2996#define FLASH_ECCR_ECCCIE_Pos (24U)
2997#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */
2998#define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk
2999#define FLASH_ECCR_ECCC_Pos (30U)
3000#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
3001#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
3002#define FLASH_ECCR_ECCD_Pos (31U)
3003#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
3004#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
3005
3006/******************* Bits definition for FLASH_OPTR register ****************/
3007#define FLASH_OPTR_RDP_Pos (0U)
3008#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
3009#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
3010#define FLASH_OPTR_BOR_EN_Pos (8U)
3011#define FLASH_OPTR_BOR_EN_Msk (0x1UL << FLASH_OPTR_BOR_EN_Pos) /*!< 0x00000100 */
3012#define FLASH_OPTR_BOR_EN FLASH_OPTR_BOR_EN_Msk
3013#define FLASH_OPTR_BORF_LEV_Pos (9U)
3014#define FLASH_OPTR_BORF_LEV_Msk (0x3UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000600 */
3015#define FLASH_OPTR_BORF_LEV FLASH_OPTR_BORF_LEV_Msk
3016#define FLASH_OPTR_BORF_LEV_0 (0x1UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000200 */
3017#define FLASH_OPTR_BORF_LEV_1 (0x2UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000400 */
3018#define FLASH_OPTR_BORR_LEV_Pos (11U)
3019#define FLASH_OPTR_BORR_LEV_Msk (0x3UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00001800 */
3020#define FLASH_OPTR_BORR_LEV FLASH_OPTR_BORR_LEV_Msk
3021#define FLASH_OPTR_BORR_LEV_0 (0x1UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000800 */
3022#define FLASH_OPTR_BORR_LEV_1 (0x2UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00001000 */
3023#define FLASH_OPTR_nRST_STOP_Pos (13U)
3024#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */
3025#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
3026#define FLASH_OPTR_nRST_STDBY_Pos (14U)
3027#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */
3028#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
3029#define FLASH_OPTR_nRST_SHDW_Pos (15U)
3030#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00008000 */
3031#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
3032#define FLASH_OPTR_IWDG_SW_Pos (16U)
3033#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
3034#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
3035#define FLASH_OPTR_IWDG_STOP_Pos (17U)
3036#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
3037#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
3038#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
3039#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
3040#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
3041#define FLASH_OPTR_WWDG_SW_Pos (19U)
3042#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
3043#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
3044#define FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U)
3045#define FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */
3046#define FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk
3047#define FLASH_OPTR_nBOOT_SEL_Pos (24U)
3048#define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */
3049#define FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk
3050#define FLASH_OPTR_nBOOT1_Pos (25U)
3051#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */
3052#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
3053#define FLASH_OPTR_nBOOT0_Pos (26U)
3054#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */
3055#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
3056#define FLASH_OPTR_NRST_MODE_Pos (27U)
3057#define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x18000000 */
3058#define FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk
3059#define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x08000000 */
3060#define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x10000000 */
3061#define FLASH_OPTR_IRHEN_Pos (29U)
3062#define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos) /*!< 0x20000000 */
3063#define FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk
3064
3065/****************** Bits definition for FLASH_PCROP1ASR register ************/
3066#define FLASH_PCROP1ASR_PCROP1A_STRT_Pos (0U)
3067#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0xFFUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x000000FF */
3068#define FLASH_PCROP1ASR_PCROP1A_STRT FLASH_PCROP1ASR_PCROP1A_STRT_Msk
3069
3070/****************** Bits definition for FLASH_PCROP1AER register ************/
3071#define FLASH_PCROP1AER_PCROP1A_END_Pos (0U)
3072#define FLASH_PCROP1AER_PCROP1A_END_Msk (0xFFUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x000000FF */
3073#define FLASH_PCROP1AER_PCROP1A_END FLASH_PCROP1AER_PCROP1A_END_Msk
3074#define FLASH_PCROP1AER_PCROP_RDP_Pos (31U)
3075#define FLASH_PCROP1AER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos) /*!< 0x80000000 */
3076#define FLASH_PCROP1AER_PCROP_RDP FLASH_PCROP1AER_PCROP_RDP_Msk
3077
3078/****************** Bits definition for FLASH_WRP1AR register ***************/
3079#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
3080#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000003F */
3081#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
3082#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
3083#define FLASH_WRP1AR_WRP1A_END_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x003F0000 */
3084#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
3085
3086/****************** Bits definition for FLASH_WRP1BR register ***************/
3087#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
3088#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000003F */
3089#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
3090#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
3091#define FLASH_WRP1BR_WRP1B_END_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x003F0000 */
3092#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
3093
3094/****************** Bits definition for FLASH_PCROP1BSR register ************/
3095#define FLASH_PCROP1BSR_PCROP1B_STRT_Pos (0U)
3096#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0xFFUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x000000FF */
3097#define FLASH_PCROP1BSR_PCROP1B_STRT FLASH_PCROP1BSR_PCROP1B_STRT_Msk
3098
3099/****************** Bits definition for FLASH_PCROP1BER register ************/
3100#define FLASH_PCROP1BER_PCROP1B_END_Pos (0U)
3101#define FLASH_PCROP1BER_PCROP1B_END_Msk (0xFFUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x000000FF */
3102#define FLASH_PCROP1BER_PCROP1B_END FLASH_PCROP1BER_PCROP1B_END_Msk
3103
3104/****************** Bits definition for FLASH_SECR register *****************/
3105#define FLASH_SECR_SEC_SIZE_Pos (0U)
3106#define FLASH_SECR_SEC_SIZE_Msk (0x7FUL << FLASH_SECR_SEC_SIZE_Pos) /*!< 0x0000007F */
3107#define FLASH_SECR_SEC_SIZE FLASH_SECR_SEC_SIZE_Msk
3108#define FLASH_SECR_BOOT_LOCK_Pos (16U)
3109#define FLASH_SECR_BOOT_LOCK_Msk (0x1UL << FLASH_SECR_BOOT_LOCK_Pos) /*!< 0x00010000 */
3110#define FLASH_SECR_BOOT_LOCK FLASH_SECR_BOOT_LOCK_Msk
3111
3112
3113/******************************************************************************/
3114/* */
3115/* General Purpose I/O */
3116/* */
3117/******************************************************************************/
3118/****************** Bits definition for GPIO_MODER register *****************/
3119#define GPIO_MODER_MODE0_Pos (0U)
3120#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
3121#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
3122#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
3123#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
3124#define GPIO_MODER_MODE1_Pos (2U)
3125#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
3126#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
3127#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
3128#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
3129#define GPIO_MODER_MODE2_Pos (4U)
3130#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
3131#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
3132#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
3133#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
3134#define GPIO_MODER_MODE3_Pos (6U)
3135#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
3136#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
3137#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
3138#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
3139#define GPIO_MODER_MODE4_Pos (8U)
3140#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
3141#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
3142#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
3143#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
3144#define GPIO_MODER_MODE5_Pos (10U)
3145#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
3146#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
3147#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
3148#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
3149#define GPIO_MODER_MODE6_Pos (12U)
3150#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
3151#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
3152#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
3153#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
3154#define GPIO_MODER_MODE7_Pos (14U)
3155#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
3156#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
3157#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
3158#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
3159#define GPIO_MODER_MODE8_Pos (16U)
3160#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
3161#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
3162#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
3163#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
3164#define GPIO_MODER_MODE9_Pos (18U)
3165#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
3166#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
3167#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
3168#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
3169#define GPIO_MODER_MODE10_Pos (20U)
3170#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
3171#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
3172#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
3173#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
3174#define GPIO_MODER_MODE11_Pos (22U)
3175#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
3176#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
3177#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
3178#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
3179#define GPIO_MODER_MODE12_Pos (24U)
3180#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
3181#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
3182#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
3183#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
3184#define GPIO_MODER_MODE13_Pos (26U)
3185#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
3186#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
3187#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
3188#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
3189#define GPIO_MODER_MODE14_Pos (28U)
3190#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
3191#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
3192#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
3193#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
3194#define GPIO_MODER_MODE15_Pos (30U)
3195#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
3196#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
3197#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
3198#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
3199
3200/****************** Bits definition for GPIO_OTYPER register ****************/
3201#define GPIO_OTYPER_OT0_Pos (0U)
3202#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
3203#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
3204#define GPIO_OTYPER_OT1_Pos (1U)
3205#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
3206#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
3207#define GPIO_OTYPER_OT2_Pos (2U)
3208#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
3209#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
3210#define GPIO_OTYPER_OT3_Pos (3U)
3211#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
3212#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
3213#define GPIO_OTYPER_OT4_Pos (4U)
3214#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
3215#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
3216#define GPIO_OTYPER_OT5_Pos (5U)
3217#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
3218#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
3219#define GPIO_OTYPER_OT6_Pos (6U)
3220#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
3221#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
3222#define GPIO_OTYPER_OT7_Pos (7U)
3223#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
3224#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
3225#define GPIO_OTYPER_OT8_Pos (8U)
3226#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
3227#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
3228#define GPIO_OTYPER_OT9_Pos (9U)
3229#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
3230#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
3231#define GPIO_OTYPER_OT10_Pos (10U)
3232#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
3233#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
3234#define GPIO_OTYPER_OT11_Pos (11U)
3235#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
3236#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
3237#define GPIO_OTYPER_OT12_Pos (12U)
3238#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
3239#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
3240#define GPIO_OTYPER_OT13_Pos (13U)
3241#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
3242#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
3243#define GPIO_OTYPER_OT14_Pos (14U)
3244#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
3245#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
3246#define GPIO_OTYPER_OT15_Pos (15U)
3247#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
3248#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
3249
3250/****************** Bits definition for GPIO_OSPEEDR register ***************/
3251#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
3252#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
3253#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
3254#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
3255#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
3256#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
3257#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
3258#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
3259#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
3260#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
3261#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
3262#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
3263#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
3264#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
3265#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
3266#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
3267#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
3268#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
3269#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
3270#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
3271#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
3272#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
3273#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
3274#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
3275#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
3276#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
3277#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
3278#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
3279#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
3280#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
3281#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
3282#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
3283#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
3284#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
3285#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
3286#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
3287#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
3288#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
3289#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
3290#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
3291#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
3292#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
3293#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
3294#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
3295#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
3296#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
3297#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
3298#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
3299#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
3300#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
3301#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
3302#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
3303#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
3304#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
3305#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
3306#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
3307#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
3308#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
3309#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
3310#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
3311#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
3312#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
3313#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
3314#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
3315#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
3316#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
3317#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
3318#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
3319#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
3320#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
3321#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
3322#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
3323#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
3324#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
3325#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
3326#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
3327#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
3328#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
3329#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
3330#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
3331
3332/****************** Bits definition for GPIO_PUPDR register *****************/
3333#define GPIO_PUPDR_PUPD0_Pos (0U)
3334#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
3335#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
3336#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
3337#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
3338#define GPIO_PUPDR_PUPD1_Pos (2U)
3339#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
3340#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
3341#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
3342#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
3343#define GPIO_PUPDR_PUPD2_Pos (4U)
3344#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
3345#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
3346#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
3347#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
3348#define GPIO_PUPDR_PUPD3_Pos (6U)
3349#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
3350#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
3351#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
3352#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
3353#define GPIO_PUPDR_PUPD4_Pos (8U)
3354#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
3355#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
3356#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
3357#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
3358#define GPIO_PUPDR_PUPD5_Pos (10U)
3359#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
3360#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
3361#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
3362#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
3363#define GPIO_PUPDR_PUPD6_Pos (12U)
3364#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
3365#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
3366#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
3367#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
3368#define GPIO_PUPDR_PUPD7_Pos (14U)
3369#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
3370#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
3371#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
3372#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
3373#define GPIO_PUPDR_PUPD8_Pos (16U)
3374#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
3375#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
3376#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
3377#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
3378#define GPIO_PUPDR_PUPD9_Pos (18U)
3379#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
3380#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
3381#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
3382#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
3383#define GPIO_PUPDR_PUPD10_Pos (20U)
3384#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
3385#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
3386#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
3387#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
3388#define GPIO_PUPDR_PUPD11_Pos (22U)
3389#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
3390#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
3391#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
3392#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
3393#define GPIO_PUPDR_PUPD12_Pos (24U)
3394#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
3395#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
3396#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
3397#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
3398#define GPIO_PUPDR_PUPD13_Pos (26U)
3399#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
3400#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
3401#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
3402#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
3403#define GPIO_PUPDR_PUPD14_Pos (28U)
3404#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
3405#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
3406#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
3407#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
3408#define GPIO_PUPDR_PUPD15_Pos (30U)
3409#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
3410#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
3411#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
3412#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
3413
3414/****************** Bits definition for GPIO_IDR register *******************/
3415#define GPIO_IDR_ID0_Pos (0U)
3416#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
3417#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
3418#define GPIO_IDR_ID1_Pos (1U)
3419#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
3420#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
3421#define GPIO_IDR_ID2_Pos (2U)
3422#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
3423#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
3424#define GPIO_IDR_ID3_Pos (3U)
3425#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
3426#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
3427#define GPIO_IDR_ID4_Pos (4U)
3428#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
3429#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
3430#define GPIO_IDR_ID5_Pos (5U)
3431#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
3432#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
3433#define GPIO_IDR_ID6_Pos (6U)
3434#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
3435#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
3436#define GPIO_IDR_ID7_Pos (7U)
3437#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
3438#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
3439#define GPIO_IDR_ID8_Pos (8U)
3440#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
3441#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
3442#define GPIO_IDR_ID9_Pos (9U)
3443#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
3444#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
3445#define GPIO_IDR_ID10_Pos (10U)
3446#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
3447#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
3448#define GPIO_IDR_ID11_Pos (11U)
3449#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
3450#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
3451#define GPIO_IDR_ID12_Pos (12U)
3452#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
3453#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
3454#define GPIO_IDR_ID13_Pos (13U)
3455#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
3456#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
3457#define GPIO_IDR_ID14_Pos (14U)
3458#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
3459#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
3460#define GPIO_IDR_ID15_Pos (15U)
3461#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
3462#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
3463
3464/****************** Bits definition for GPIO_ODR register *******************/
3465#define GPIO_ODR_OD0_Pos (0U)
3466#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
3467#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
3468#define GPIO_ODR_OD1_Pos (1U)
3469#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
3470#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
3471#define GPIO_ODR_OD2_Pos (2U)
3472#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
3473#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
3474#define GPIO_ODR_OD3_Pos (3U)
3475#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
3476#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
3477#define GPIO_ODR_OD4_Pos (4U)
3478#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
3479#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
3480#define GPIO_ODR_OD5_Pos (5U)
3481#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
3482#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
3483#define GPIO_ODR_OD6_Pos (6U)
3484#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
3485#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
3486#define GPIO_ODR_OD7_Pos (7U)
3487#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
3488#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
3489#define GPIO_ODR_OD8_Pos (8U)
3490#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
3491#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
3492#define GPIO_ODR_OD9_Pos (9U)
3493#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
3494#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
3495#define GPIO_ODR_OD10_Pos (10U)
3496#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
3497#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
3498#define GPIO_ODR_OD11_Pos (11U)
3499#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
3500#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
3501#define GPIO_ODR_OD12_Pos (12U)
3502#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
3503#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
3504#define GPIO_ODR_OD13_Pos (13U)
3505#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
3506#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
3507#define GPIO_ODR_OD14_Pos (14U)
3508#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
3509#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
3510#define GPIO_ODR_OD15_Pos (15U)
3511#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
3512#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
3513
3514/****************** Bits definition for GPIO_BSRR register ******************/
3515#define GPIO_BSRR_BS0_Pos (0U)
3516#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
3517#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
3518#define GPIO_BSRR_BS1_Pos (1U)
3519#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
3520#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
3521#define GPIO_BSRR_BS2_Pos (2U)
3522#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
3523#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
3524#define GPIO_BSRR_BS3_Pos (3U)
3525#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
3526#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
3527#define GPIO_BSRR_BS4_Pos (4U)
3528#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
3529#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
3530#define GPIO_BSRR_BS5_Pos (5U)
3531#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
3532#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
3533#define GPIO_BSRR_BS6_Pos (6U)
3534#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
3535#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
3536#define GPIO_BSRR_BS7_Pos (7U)
3537#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
3538#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
3539#define GPIO_BSRR_BS8_Pos (8U)
3540#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
3541#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
3542#define GPIO_BSRR_BS9_Pos (9U)
3543#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
3544#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
3545#define GPIO_BSRR_BS10_Pos (10U)
3546#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
3547#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
3548#define GPIO_BSRR_BS11_Pos (11U)
3549#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
3550#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
3551#define GPIO_BSRR_BS12_Pos (12U)
3552#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
3553#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
3554#define GPIO_BSRR_BS13_Pos (13U)
3555#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
3556#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
3557#define GPIO_BSRR_BS14_Pos (14U)
3558#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
3559#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
3560#define GPIO_BSRR_BS15_Pos (15U)
3561#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
3562#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
3563#define GPIO_BSRR_BR0_Pos (16U)
3564#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
3565#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
3566#define GPIO_BSRR_BR1_Pos (17U)
3567#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
3568#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
3569#define GPIO_BSRR_BR2_Pos (18U)
3570#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
3571#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
3572#define GPIO_BSRR_BR3_Pos (19U)
3573#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
3574#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
3575#define GPIO_BSRR_BR4_Pos (20U)
3576#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
3577#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
3578#define GPIO_BSRR_BR5_Pos (21U)
3579#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
3580#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
3581#define GPIO_BSRR_BR6_Pos (22U)
3582#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
3583#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
3584#define GPIO_BSRR_BR7_Pos (23U)
3585#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
3586#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
3587#define GPIO_BSRR_BR8_Pos (24U)
3588#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
3589#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
3590#define GPIO_BSRR_BR9_Pos (25U)
3591#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
3592#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
3593#define GPIO_BSRR_BR10_Pos (26U)
3594#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
3595#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
3596#define GPIO_BSRR_BR11_Pos (27U)
3597#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
3598#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
3599#define GPIO_BSRR_BR12_Pos (28U)
3600#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
3601#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
3602#define GPIO_BSRR_BR13_Pos (29U)
3603#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
3604#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
3605#define GPIO_BSRR_BR14_Pos (30U)
3606#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
3607#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
3608#define GPIO_BSRR_BR15_Pos (31U)
3609#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
3610#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
3611
3612/****************** Bit definition for GPIO_LCKR register *********************/
3613#define GPIO_LCKR_LCK0_Pos (0U)
3614#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
3615#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
3616#define GPIO_LCKR_LCK1_Pos (1U)
3617#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
3618#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
3619#define GPIO_LCKR_LCK2_Pos (2U)
3620#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
3621#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
3622#define GPIO_LCKR_LCK3_Pos (3U)
3623#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
3624#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
3625#define GPIO_LCKR_LCK4_Pos (4U)
3626#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
3627#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
3628#define GPIO_LCKR_LCK5_Pos (5U)
3629#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
3630#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
3631#define GPIO_LCKR_LCK6_Pos (6U)
3632#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
3633#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
3634#define GPIO_LCKR_LCK7_Pos (7U)
3635#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
3636#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
3637#define GPIO_LCKR_LCK8_Pos (8U)
3638#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
3639#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
3640#define GPIO_LCKR_LCK9_Pos (9U)
3641#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
3642#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
3643#define GPIO_LCKR_LCK10_Pos (10U)
3644#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
3645#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
3646#define GPIO_LCKR_LCK11_Pos (11U)
3647#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
3648#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
3649#define GPIO_LCKR_LCK12_Pos (12U)
3650#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
3651#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
3652#define GPIO_LCKR_LCK13_Pos (13U)
3653#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
3654#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
3655#define GPIO_LCKR_LCK14_Pos (14U)
3656#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
3657#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
3658#define GPIO_LCKR_LCK15_Pos (15U)
3659#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
3660#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
3661#define GPIO_LCKR_LCKK_Pos (16U)
3662#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
3663#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
3664
3665/****************** Bit definition for GPIO_AFRL register *********************/
3666#define GPIO_AFRL_AFSEL0_Pos (0U)
3667#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
3668#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
3669#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
3670#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
3671#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
3672#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
3673#define GPIO_AFRL_AFSEL1_Pos (4U)
3674#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
3675#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
3676#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
3677#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
3678#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
3679#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
3680#define GPIO_AFRL_AFSEL2_Pos (8U)
3681#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
3682#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
3683#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
3684#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
3685#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
3686#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
3687#define GPIO_AFRL_AFSEL3_Pos (12U)
3688#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
3689#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
3690#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
3691#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
3692#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
3693#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
3694#define GPIO_AFRL_AFSEL4_Pos (16U)
3695#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
3696#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
3697#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
3698#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
3699#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
3700#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
3701#define GPIO_AFRL_AFSEL5_Pos (20U)
3702#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
3703#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
3704#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
3705#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
3706#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
3707#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
3708#define GPIO_AFRL_AFSEL6_Pos (24U)
3709#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
3710#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
3711#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
3712#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
3713#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
3714#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
3715#define GPIO_AFRL_AFSEL7_Pos (28U)
3716#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
3717#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
3718#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
3719#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
3720#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
3721#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
3722
3723/****************** Bit definition for GPIO_AFRH register *********************/
3724#define GPIO_AFRH_AFSEL8_Pos (0U)
3725#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
3726#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
3727#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
3728#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
3729#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
3730#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
3731#define GPIO_AFRH_AFSEL9_Pos (4U)
3732#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
3733#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
3734#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
3735#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
3736#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
3737#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
3738#define GPIO_AFRH_AFSEL10_Pos (8U)
3739#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
3740#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
3741#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
3742#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
3743#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
3744#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
3745#define GPIO_AFRH_AFSEL11_Pos (12U)
3746#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
3747#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
3748#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
3749#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
3750#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
3751#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
3752#define GPIO_AFRH_AFSEL12_Pos (16U)
3753#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
3754#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
3755#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
3756#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
3757#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
3758#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
3759#define GPIO_AFRH_AFSEL13_Pos (20U)
3760#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
3761#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
3762#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
3763#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
3764#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
3765#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
3766#define GPIO_AFRH_AFSEL14_Pos (24U)
3767