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1/**
2 ******************************************************************************
3 * @file stm32g081xx.h
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
6 * This file contains all the peripheral register's definitions, bits
7 * definitions and memory mapping for stm32g081xx devices.
8 *
9 * This file contains:
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral's registers hardware
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
18 * All rights reserved.</center></h2>
19 *
20 * This software component is licensed by ST under BSD 3-Clause license,
21 * the "License"; You may not use this file except in compliance with the
22 * License. You may obtain a copy of the License at:
23 * opensource.org/licenses/BSD-3-Clause
24 *
25 ******************************************************************************
26 */
27
28/** @addtogroup CMSIS_Device
29 * @{
30 */
31
32/** @addtogroup stm32g081xx
33 * @{
34 */
35
36#ifndef STM32G081xx_H
37#define STM32G081xx_H
38
39#ifdef __cplusplus
40 extern "C" {
41#endif /* __cplusplus */
42
43/** @addtogroup Configuration_section_for_CMSIS
44 * @{
45 */
46
47/**
48 * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
49 */
50#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */
51#define __MPU_PRESENT 1 /*!< STM32G0xx provides an MPU */
52#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */
53#define __NVIC_PRIO_BITS 2 /*!< STM32G0xx uses 2 Bits for the Priority Levels */
54#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
55
56/**
57 * @}
58 */
59
60/** @addtogroup Peripheral_interrupt_number_definition
61 * @{
62 */
63
64/**
65 * @brief stm32g081xx Interrupt Number Definition, according to the selected device
66 * in @ref Library_configuration_section
67 */
68
69/*!< Interrupt Number Definition */
70typedef enum
71{
72/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/
73 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
74 HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
75 SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
76 PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
77 SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
78/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/
79 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
80 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt(EXTI line 16) */
81 RTC_TAMP_IRQn = 2, /*!< RTC interrupt through the EXTI line 19 & 21 */
82 FLASH_IRQn = 3, /*!< FLASH global Interrupt */
83 RCC_IRQn = 4, /*!< RCC global Interrupt */
84 EXTI0_1_IRQn = 5, /*!< EXTI 0 and 1 Interrupts */
85 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
86 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
87 UCPD1_2_IRQn = 8, /*!< UCPD1 and UCPD2 global Interrupt */
88 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
89 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
90 DMA1_Ch4_7_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 and DMAMUX1 Overrun Interrupts */
91 ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts (combined with EXTI 17 & 18) */
92 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
93 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
94 TIM2_IRQn = 15, /*!< TIM2 Interrupt */
95 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
96 TIM6_DAC_LPTIM1_IRQn = 17, /*!< TIM6, DAC and LPTIM1 global Interrupts */
97 TIM7_LPTIM2_IRQn = 18, /*!< TIM7 and LPTIM2 global Interrupt */
98 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
99 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
100 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
101 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
102 I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */
103 I2C2_IRQn = 24, /*!< I2C2 Interrupt */
104 SPI1_IRQn = 25, /*!< SPI1 Interrupt */
105 SPI2_IRQn = 26, /*!< SPI2 Interrupt */
106 USART1_IRQn = 27, /*!< USART1 Interrupt */
107 USART2_IRQn = 28, /*!< USART2 Interrupt */
108 USART3_4_LPUART1_IRQn = 29, /*!< USART3, USART4 and LPUART1 globlal Interrupts (combined with EXTI 28) */
109 CEC_IRQn = 30, /*!< CEC Interrupt(combined with EXTI 27) */
110 AES_RNG_IRQn = 31, /*!< AES & RNG Interrupt */
111} IRQn_Type;
112
113/**
114 * @}
115 */
116
117#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
118#include "system_stm32g0xx.h"
119#include <stdint.h>
120
121/** @addtogroup Peripheral_registers_structures
122 * @{
123 */
124
125/**
126 * @brief Analog to Digital Converter
127 */
128typedef struct
129{
130 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
131 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
132 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
133 __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */
134 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
135 __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */
136 uint32_t RESERVED1; /*!< Reserved, 0x18 */
137 uint32_t RESERVED2; /*!< Reserved, 0x1C */
138 __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
139 __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
140 __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */
141 __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */
142 uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */
143 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
144 uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */
145 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */
146 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */
147 uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */
148 __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */
149} ADC_TypeDef;
150
151typedef struct
152{
153 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
154} ADC_Common_TypeDef;
155
156/**
157 * @brief HDMI-CEC
158 */
159typedef struct
160{
161 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
162 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
163 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
164 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
165 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
166 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
167}CEC_TypeDef;
168
169/**
170 * @brief Comparator
171 */
172typedef struct
173{
174 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
175} COMP_TypeDef;
176
177typedef struct
178{
179 __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */
180 __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */
181} COMP_Common_TypeDef;
182
183/**
184 * @brief CRC calculation unit
185 */
186typedef struct
187{
188 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
189 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
190 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
191 uint32_t RESERVED1; /*!< Reserved, 0x0C */
192 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
193 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
194} CRC_TypeDef;
195
196/**
197 * @brief Digital to Analog Converter
198 */
199typedef struct
200{
201 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
202 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
203 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
204 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
205 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
206 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
207 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
208 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
209 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
210 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
211 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
212 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
213 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
214 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
215 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
216 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
217 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
218 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
219 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
220 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
221} DAC_TypeDef;
222
223/**
224 * @brief Debug MCU
225 */
226typedef struct
227{
228 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
229 __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */
230 __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */
231 __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */
232} DBG_TypeDef;
233
234/**
235 * @brief DMA Controller
236 */
237typedef struct
238{
239 __IO uint32_t CCR; /*!< DMA channel x configuration register */
240 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
241 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
242 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
243} DMA_Channel_TypeDef;
244
245typedef struct
246{
247 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
248 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
249} DMA_TypeDef;
250
251/**
252 * @brief DMA Multiplexer
253 */
254typedef struct
255{
256 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */
257}DMAMUX_Channel_TypeDef;
258
259typedef struct
260{
261 __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */
262 __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */
263}DMAMUX_ChannelStatus_TypeDef;
264
265typedef struct
266{
267 __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */
268}DMAMUX_RequestGen_TypeDef;
269
270typedef struct
271{
272 __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */
273 __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */
274}DMAMUX_RequestGenStatus_TypeDef;
275
276/**
277 * @brief Asynch Interrupt/Event Controller (EXTI)
278 */
279typedef struct
280{
281 __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */
282 __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */
283 __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */
284 __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */
285 __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */
286 uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */
287 uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */
288 uint32_t RESERVED3[11]; /*!< Reserved 3, 0x34 -- 0x5C */
289 __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */
290 uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */
291 __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */
292 __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */
293 uint32_t RESERVED5[2]; /*!< Reserved 5, 0x88 -- 0x8C */
294 __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */
295 __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */
296} EXTI_TypeDef;
297
298/**
299 * @brief FLASH Registers
300 */
301typedef struct
302{
303 __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */
304 uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */
305 __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */
306 __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */
307 __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */
308 __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */
309 __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
310 uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
311 __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */
312 __IO uint32_t PCROP1ASR; /*!< FLASH Bank PCROP area A Start address register, Address offset: 0x24 */
313 __IO uint32_t PCROP1AER; /*!< FLASH Bank PCROP area A End address register, Address offset: 0x28 */
314 __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */
315 __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */
316 __IO uint32_t PCROP1BSR; /*!< FLASH Bank PCROP area B Start address register, Address offset: 0x34 */
317 __IO uint32_t PCROP1BER; /*!< FLASH Bank PCROP area B End address register, Address offset: 0x38 */
318 uint32_t RESERVED3[17];/*!< Reserved3, Address offset: 0x3C */
319 __IO uint32_t SECR; /*!< FLASH security register , Address offset: 0x80 */
320} FLASH_TypeDef;
321
322/**
323 * @brief General Purpose I/O
324 */
325typedef struct
326{
327 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
328 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
329 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
330 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
331 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
332 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
333 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
334 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
335 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
336 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
337} GPIO_TypeDef;
338
339
340/**
341 * @brief Inter-integrated Circuit Interface
342 */
343typedef struct
344{
345 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
346 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
347 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
348 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
349 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
350 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
351 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
352 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
353 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
354 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
355 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
356} I2C_TypeDef;
357
358/**
359 * @brief Independent WATCHDOG
360 */
361typedef struct
362{
363 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
364 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
365 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
366 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
367 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
368} IWDG_TypeDef;
369
370/**
371 * @brief LPTIMER
372 */
373typedef struct
374{
375 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
376 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
377 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
378 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
379 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
380 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
381 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
382 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
383 __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x20 */
384 __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */
385} LPTIM_TypeDef;
386
387
388/**
389 * @brief Power Control
390 */
391typedef struct
392{
393 __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */
394 __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */
395 __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */
396 __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */
397 __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */
398 __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */
399 __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */
400 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
401 __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */
402 __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */
403 __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */
404 __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */
405 __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */
406 __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */
407 __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */
408 __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */
409 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x40 */
410 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x44 */
411 __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */
412 __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */
413} PWR_TypeDef;
414
415/**
416 * @brief Reset and Clock Control
417 */
418typedef struct
419{
420 __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */
421 __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */
422 __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */
423 __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */
424 __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */
425 __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
426 __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */
427 __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */
428 __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */
429 __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */
430 __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */
431 __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */
432 __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */
433 __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */
434 __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */
435 __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */
436 __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */
437 __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */
438 __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */
439 __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */
440 __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */
441 __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */
442 __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */
443 __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x5C */
444 __IO uint32_t CSR; /*!< RCC Unregulated Domain Clock Control and Status Register, Address offset: 0x60 */
445} RCC_TypeDef;
446
447/**
448 * @brief Real-Time Clock
449 */
450typedef struct
451{
452 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
453 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
454 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
455 __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
456 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
457 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
458 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
459 uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */
460 uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */
461 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
462 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
463 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
464 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
465 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
466 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
467 uint32_t RESERVED2; /*!< Reserved Address offset: 0x1C */
468 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
469 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
470 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
471 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
472 __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
473 __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */
474 uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */
475 __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */
476 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */
477} RTC_TypeDef;
478
479/**
480 * @brief Tamper and backup registers
481 */
482typedef struct
483{
484 __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */
485 __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */
486 uint32_t RESERVED0; /*!< Reserved Address offset: 0x08 */
487 __IO uint32_t FLTCR; /*!< Reserved Address offset: 0x0C */
488 uint32_t RESERVED1[7]; /*!< Reserved Address offset: 0x10 -- 0x28 */
489 __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */
490 __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */
491 __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register, Address offset: 0x34 */
492 uint32_t RESERVED2; /*!< Reserved Address offset: 0x38 */
493 __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */
494 uint32_t RESERVED3[48]; /*!< Reserved Address offset: 0x54 -- 0xFC */
495 __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
496 __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
497 __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
498 __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
499 __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
500} TAMP_TypeDef;
501
502 /**
503 * @brief Serial Peripheral Interface
504 */
505typedef struct
506{
507 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
508 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
509 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
510 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
511 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
512 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
513 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
514 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
515 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
516} SPI_TypeDef;
517
518/**
519 * @brief System configuration controller
520 */
521typedef struct
522{
523 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
524 uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */
525 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
526 uint32_t RESERVED1[25]; /*!< Reserved 0x1C */
527 __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */
528} SYSCFG_TypeDef;
529
530/**
531 * @brief TIM
532 */
533typedef struct
534{
535 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
536 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
537 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
538 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
539 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
540 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
541 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
542 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
543 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
544 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
545 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
546 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
547 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
548 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
549 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
550 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
551 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
552 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
553 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
554 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
555 __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */
556 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
557 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
558 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
559 __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */
560 __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */
561 __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
562} TIM_TypeDef;
563
564/**
565 * @brief Universal Synchronous Asynchronous Receiver Transmitter
566 */
567typedef struct
568{
569 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
570 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
571 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
572 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
573 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
574 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
575 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
576 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
577 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
578 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
579 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
580 __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
581} USART_TypeDef;
582
583/**
584 * @brief VREFBUF
585 */
586typedef struct
587{
588 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
589 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
590} VREFBUF_TypeDef;
591
592/**
593 * @brief Window WATCHDOG
594 */
595typedef struct
596{
597 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
598 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
599 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
600} WWDG_TypeDef;
601
602/**
603 * @brief AES hardware accelerator
604 */
605typedef struct
606{
607 __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
608 __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
609 __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
610 __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
611 __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
612 __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
613 __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
614 __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
615 __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
616 __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
617 __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
618 __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
619 __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */
620 __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */
621 __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */
622 __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */
623 __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */
624 __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */
625 __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */
626 __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */
627 __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */
628 __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */
629 __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */
630 __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */
631} AES_TypeDef;
632
633/**
634 * @brief RNG
635 */
636typedef struct
637{
638 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
639 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
640 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
641} RNG_TypeDef;
642
643
644/**
645 * @brief UCPD
646 */
647typedef struct
648{
649 __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */
650 __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */
651 __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */
652 __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */
653 __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */
654 __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */
655 __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */
656 __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */
657 __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */
658 __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */
659 __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */
660 __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */
661 __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */
662 __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */
663 __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
664
665} UCPD_TypeDef;
666
667/**
668 * @}
669 */
670
671/** @addtogroup Peripheral_memory_map
672 * @{
673 */
674#define FLASH_BASE (0x08000000UL) /*!< FLASH base address */
675#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */
676#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
677#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */
678
679#define SRAM_SIZE_MAX (0x00008000UL) /*!< maximum SRAM size (up to 32 KBytes) */
680
681/*!< Peripheral memory map */
682#define APBPERIPH_BASE (PERIPH_BASE)
683#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
684
685/*!< APB peripherals */
686
687#define TIM2_BASE (APBPERIPH_BASE + 0UL)
688#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL)
689#define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL)
690#define TIM7_BASE (APBPERIPH_BASE + 0x00001400UL)
691#define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL)
692#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
693#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
694#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
695#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL)
696#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
697#define USART3_BASE (APBPERIPH_BASE + 0x00004800UL)
698#define USART4_BASE (APBPERIPH_BASE + 0x00004C00UL)
699#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
700#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL)
701#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
702#define DAC1_BASE (APBPERIPH_BASE + 0x00007400UL)
703#define DAC_BASE (APBPERIPH_BASE + 0x00007400UL) /* Kept for legacy purpose */
704#define CEC_BASE (APBPERIPH_BASE + 0x00007800UL)
705#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL)
706#define LPUART1_BASE (APBPERIPH_BASE + 0x00008000UL)
707#define LPTIM2_BASE (APBPERIPH_BASE + 0x00009400UL)
708#define UCPD1_BASE (APBPERIPH_BASE + 0x0000A000UL)
709#define UCPD2_BASE (APBPERIPH_BASE + 0x0000A400UL)
710#define TAMP_BASE (APBPERIPH_BASE + 0x0000B000UL)
711#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
712#define VREFBUF_BASE (APBPERIPH_BASE + 0x00010030UL)
713#define COMP1_BASE (SYSCFG_BASE + 0x0200UL)
714#define COMP2_BASE (SYSCFG_BASE + 0x0204UL)
715#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
716#define ADC1_COMMON_BASE (APBPERIPH_BASE + 0x00012708UL)
717#define ADC_BASE (ADC1_COMMON_BASE) /* Kept for legacy purpose */
718#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL)
719#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
720#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL)
721#define TIM15_BASE (APBPERIPH_BASE + 0x00014000UL)
722#define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL)
723#define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL)
724#define DBG_BASE (APBPERIPH_BASE + 0x00015800UL)
725
726
727/*!< AHB peripherals */
728#define DMA1_BASE (AHBPERIPH_BASE)
729#define DMAMUX1_BASE (AHBPERIPH_BASE + 0x00000800UL)
730#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
731#define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL)
732#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL)
733#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
734
735#define RNG_BASE (AHBPERIPH_BASE + 0x00005000UL)
736#define AES_BASE (AHBPERIPH_BASE + 0x00006000UL)
737
738#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
739#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
740#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
741#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
742#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
743#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
744#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
745
746#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
747#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL)
748#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL)
749#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL)
750#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL)
751#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL)
752#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL)
753
754#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL)
755#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL)
756#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL)
757#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL)
758
759#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL)
760#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL)
761#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC)
762
763/*!< IOPORT */
764#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL)
765#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL)
766#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL)
767#define GPIOD_BASE (IOPORT_BASE + 0x00000C00UL)
768#define GPIOF_BASE (IOPORT_BASE + 0x00001400UL)
769
770/*!< Device Electronic Signature */
771#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */
772#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */
773#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */
774
775/**
776 * @}
777 */
778
779/** @addtogroup Peripheral_declaration
780 * @{
781 */
782#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
783#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
784#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
785#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
786#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
787#define RTC ((RTC_TypeDef *) RTC_BASE)
788#define TAMP ((TAMP_TypeDef *) TAMP_BASE)
789#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
790#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
791#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
792#define USART2 ((USART_TypeDef *) USART2_BASE)
793#define USART3 ((USART_TypeDef *) USART3_BASE)
794#define USART4 ((USART_TypeDef *) USART4_BASE)
795#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
796#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
797#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
798#define PWR ((PWR_TypeDef *) PWR_BASE)
799#define RCC ((RCC_TypeDef *) RCC_BASE)
800#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
801#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
802#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
803#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
804#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
805#define CEC ((CEC_TypeDef *) CEC_BASE)
806#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
807#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
808#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
809#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
810#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
811#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
812#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
813#define USART1 ((USART_TypeDef *) USART1_BASE)
814#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
815#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
816#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
817#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
818
819#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
820#define CRC ((CRC_TypeDef *) CRC_BASE)
821#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
822#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
823#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
824#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
825#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
826#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
827#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
828#define ADC (ADC1_COMMON) /* Kept for legacy purpose */
829
830#define AES ((AES_TypeDef *) AES_BASE)
831#define AES1 ((AES_TypeDef *) AES_BASE)
832#define RNG ((RNG_TypeDef *) RNG_BASE)
833
834#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE)
835#define UCPD2 ((UCPD_TypeDef *) UCPD2_BASE)
836
837#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
838#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
839#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
840#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
841#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
842#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
843#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
844
845#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
846#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
847#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
848#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
849#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
850#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
851#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
852#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
853
854#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
855#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
856#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
857#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
858
859#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
860#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
861#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE)
862
863#define DBG ((DBG_TypeDef *) DBG_BASE)
864
865/**
866 * @}
867 */
868
869/** @addtogroup Exported_constants
870 * @{
871 */
872
873 /** @addtogroup Peripheral_Registers_Bits_Definition
874 * @{
875 */
876
877/******************************************************************************/
878/* Peripheral Registers Bits Definition */
879/******************************************************************************/
880
881/******************************************************************************/
882/* */
883/* Analog to Digital Converter (ADC) */
884/* */
885/******************************************************************************/
886/******************** Bit definition for ADC_ISR register *******************/
887#define ADC_ISR_ADRDY_Pos (0U)
888#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
889#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
890#define ADC_ISR_EOSMP_Pos (1U)
891#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
892#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
893#define ADC_ISR_EOC_Pos (2U)
894#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
895#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
896#define ADC_ISR_EOS_Pos (3U)
897#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
898#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
899#define ADC_ISR_OVR_Pos (4U)
900#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
901#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
902#define ADC_ISR_AWD1_Pos (7U)
903#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
904#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
905#define ADC_ISR_AWD2_Pos (8U)
906#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
907#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
908#define ADC_ISR_AWD3_Pos (9U)
909#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
910#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
911#define ADC_ISR_EOCAL_Pos (11U)
912#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
913#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */
914#define ADC_ISR_CCRDY_Pos (13U)
915#define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */
916#define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */
917
918/* Legacy defines */
919#define ADC_ISR_EOSEQ (ADC_ISR_EOS)
920
921/******************** Bit definition for ADC_IER register *******************/
922#define ADC_IER_ADRDYIE_Pos (0U)
923#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
924#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
925#define ADC_IER_EOSMPIE_Pos (1U)
926#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
927#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
928#define ADC_IER_EOCIE_Pos (2U)
929#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
930#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
931#define ADC_IER_EOSIE_Pos (3U)
932#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
933#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
934#define ADC_IER_OVRIE_Pos (4U)
935#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
936#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
937#define ADC_IER_AWD1IE_Pos (7U)
938#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
939#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
940#define ADC_IER_AWD2IE_Pos (8U)
941#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
942#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
943#define ADC_IER_AWD3IE_Pos (9U)
944#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
945#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
946#define ADC_IER_EOCALIE_Pos (11U)
947#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
948#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */
949#define ADC_IER_CCRDYIE_Pos (13U)
950#define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */
951#define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */
952
953/* Legacy defines */
954#define ADC_IER_EOSEQIE (ADC_IER_EOSIE)
955
956/******************** Bit definition for ADC_CR register ********************/
957#define ADC_CR_ADEN_Pos (0U)
958#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
959#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
960#define ADC_CR_ADDIS_Pos (1U)
961#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
962#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
963#define ADC_CR_ADSTART_Pos (2U)
964#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
965#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
966#define ADC_CR_ADSTP_Pos (4U)
967#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
968#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
969#define ADC_CR_ADVREGEN_Pos (28U)
970#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
971#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
972#define ADC_CR_ADCAL_Pos (31U)
973#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
974#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
975
976/******************** Bit definition for ADC_CFGR1 register *****************/
977#define ADC_CFGR1_DMAEN_Pos (0U)
978#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
979#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */
980#define ADC_CFGR1_DMACFG_Pos (1U)
981#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
982#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */
983
984#define ADC_CFGR1_SCANDIR_Pos (2U)
985#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
986#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */
987
988#define ADC_CFGR1_RES_Pos (3U)
989#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
990#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */
991#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
992#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
993
994#define ADC_CFGR1_ALIGN_Pos (5U)
995#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
996#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */
997
998#define ADC_CFGR1_EXTSEL_Pos (6U)
999#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
1000#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */
1001#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
1002#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
1003#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
1004
1005#define ADC_CFGR1_EXTEN_Pos (10U)
1006#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
1007#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */
1008#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
1009#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
1010
1011#define ADC_CFGR1_OVRMOD_Pos (12U)
1012#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
1013#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */
1014#define ADC_CFGR1_CONT_Pos (13U)
1015#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
1016#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */
1017#define ADC_CFGR1_WAIT_Pos (14U)
1018#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
1019#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */
1020#define ADC_CFGR1_AUTOFF_Pos (15U)
1021#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
1022#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */
1023#define ADC_CFGR1_DISCEN_Pos (16U)
1024#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
1025#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
1026#define ADC_CFGR1_CHSELRMOD_Pos (21U)
1027#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */
1028#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */
1029
1030#define ADC_CFGR1_AWD1SGL_Pos (22U)
1031#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
1032#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1033#define ADC_CFGR1_AWD1EN_Pos (23U)
1034#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
1035#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1036
1037#define ADC_CFGR1_AWD1CH_Pos (26U)
1038#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */
1039#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
1040#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */
1041#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */
1042#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */
1043#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */
1044#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */
1045
1046/* Legacy defines */
1047#define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT)
1048
1049/******************** Bit definition for ADC_CFGR2 register *****************/
1050#define ADC_CFGR2_OVSE_Pos (0U)
1051#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
1052#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
1053
1054#define ADC_CFGR2_OVSR_Pos (2U)
1055#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
1056#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
1057#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
1058#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
1059#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
1060
1061#define ADC_CFGR2_OVSS_Pos (5U)
1062#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
1063#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
1064#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
1065#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
1066#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
1067#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
1068
1069#define ADC_CFGR2_TOVS_Pos (9U)
1070#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */
1071#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1072
1073#define ADC_CFGR2_LFTRIG_Pos (29U)
1074#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */
1075#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */
1076
1077#define ADC_CFGR2_CKMODE_Pos (30U)
1078#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
1079#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */
1080#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
1081#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
1082
1083/******************** Bit definition for ADC_SMPR register ******************/
1084#define ADC_SMPR_SMP1_Pos (0U)
1085#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */
1086#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */
1087#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */
1088#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */
1089#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */
1090
1091#define ADC_SMPR_SMP2_Pos (4U)
1092#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */
1093#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */
1094#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */
1095#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */
1096#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */
1097
1098#define ADC_SMPR_SMPSEL_Pos (8U)
1099#define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */
1100#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */
1101#define ADC_SMPR_SMPSEL0_Pos (8U)
1102#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */
1103#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */
1104#define ADC_SMPR_SMPSEL1_Pos (9U)
1105#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */
1106#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */
1107#define ADC_SMPR_SMPSEL2_Pos (10U)
1108#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */
1109#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */
1110#define ADC_SMPR_SMPSEL3_Pos (11U)
1111#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */
1112#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */
1113#define ADC_SMPR_SMPSEL4_Pos (12U)
1114#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */
1115#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */
1116#define ADC_SMPR_SMPSEL5_Pos (13U)
1117#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */
1118#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */
1119#define ADC_SMPR_SMPSEL6_Pos (14U)
1120#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */
1121#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */
1122#define ADC_SMPR_SMPSEL7_Pos (15U)
1123#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */
1124#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */
1125#define ADC_SMPR_SMPSEL8_Pos (16U)
1126#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */
1127#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */
1128#define ADC_SMPR_SMPSEL9_Pos (17U)
1129#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */
1130#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */
1131#define ADC_SMPR_SMPSEL10_Pos (18U)
1132#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */
1133#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */
1134#define ADC_SMPR_SMPSEL11_Pos (19U)
1135#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */
1136#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */
1137#define ADC_SMPR_SMPSEL12_Pos (20U)
1138#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */
1139#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */
1140#define ADC_SMPR_SMPSEL13_Pos (21U)
1141#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */
1142#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */
1143#define ADC_SMPR_SMPSEL14_Pos (22U)
1144#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */
1145#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */
1146#define ADC_SMPR_SMPSEL15_Pos (23U)
1147#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */
1148#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */
1149#define ADC_SMPR_SMPSEL16_Pos (24U)
1150#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */
1151#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */
1152#define ADC_SMPR_SMPSEL17_Pos (25U)
1153#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */
1154#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */
1155#define ADC_SMPR_SMPSEL18_Pos (26U)
1156#define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */
1157#define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */
1158
1159/******************** Bit definition for ADC_TR1 register *******************/
1160#define ADC_TR1_LT1_Pos (0U)
1161#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
1162#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
1163#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
1164#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
1165#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
1166#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
1167#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
1168#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
1169#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
1170#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
1171#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
1172#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
1173#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
1174#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
1175
1176#define ADC_TR1_HT1_Pos (16U)
1177#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
1178#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
1179#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
1180#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
1181#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
1182#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
1183#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
1184#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
1185#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
1186#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
1187#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
1188#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
1189#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
1190#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
1191
1192/******************** Bit definition for ADC_TR2 register *******************/
1193#define ADC_TR2_LT2_Pos (0U)
1194#define ADC_TR2_LT2_Msk (0xFFFUL << ADC_TR2_LT2_Pos) /*!< 0x00000FFF */
1195#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
1196#define ADC_TR2_LT2_0 (0x001UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
1197#define ADC_TR2_LT2_1 (0x002UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
1198#define ADC_TR2_LT2_2 (0x004UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
1199#define ADC_TR2_LT2_3 (0x008UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
1200#define ADC_TR2_LT2_4 (0x010UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
1201#define ADC_TR2_LT2_5 (0x020UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
1202#define ADC_TR2_LT2_6 (0x040UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
1203#define ADC_TR2_LT2_7 (0x080UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
1204#define ADC_TR2_LT2_8 (0x100UL << ADC_TR2_LT2_Pos) /*!< 0x00000100 */
1205#define ADC_TR2_LT2_9 (0x200UL << ADC_TR2_LT2_Pos) /*!< 0x00000200 */
1206#define ADC_TR2_LT2_10 (0x400UL << ADC_TR2_LT2_Pos) /*!< 0x00000400 */
1207#define ADC_TR2_LT2_11 (0x800UL << ADC_TR2_LT2_Pos) /*!< 0x00000800 */
1208
1209#define ADC_TR2_HT2_Pos (16U)
1210#define ADC_TR2_HT2_Msk (0xFFFUL << ADC_TR2_HT2_Pos) /*!< 0x0FFF0000 */
1211#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
1212#define ADC_TR2_HT2_0 (0x001UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
1213#define ADC_TR2_HT2_1 (0x002UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
1214#define ADC_TR2_HT2_2 (0x004UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
1215#define ADC_TR2_HT2_3 (0x008UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
1216#define ADC_TR2_HT2_4 (0x010UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
1217#define ADC_TR2_HT2_5 (0x020UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
1218#define ADC_TR2_HT2_6 (0x040UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
1219#define ADC_TR2_HT2_7 (0x080UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
1220#define ADC_TR2_HT2_8 (0x100UL << ADC_TR2_HT2_Pos) /*!< 0x01000000 */
1221#define ADC_TR2_HT2_9 (0x200UL << ADC_TR2_HT2_Pos) /*!< 0x02000000 */
1222#define ADC_TR2_HT2_10 (0x400UL << ADC_TR2_HT2_Pos) /*!< 0x04000000 */
1223#define ADC_TR2_HT2_11 (0x800UL << ADC_TR2_HT2_Pos) /*!< 0x08000000 */
1224
1225/******************** Bit definition for ADC_CHSELR register ****************/
1226#define ADC_CHSELR_CHSEL_Pos (0U)
1227#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
1228#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
1229#define ADC_CHSELR_CHSEL18_Pos (18U)
1230#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
1231#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
1232#define ADC_CHSELR_CHSEL17_Pos (17U)
1233#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
1234#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
1235#define ADC_CHSELR_CHSEL16_Pos (16U)
1236#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */
1237#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
1238#define ADC_CHSELR_CHSEL15_Pos (15U)
1239#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
1240#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
1241#define ADC_CHSELR_CHSEL14_Pos (14U)
1242#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
1243#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
1244#define ADC_CHSELR_CHSEL13_Pos (13U)
1245#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
1246#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
1247#define ADC_CHSELR_CHSEL12_Pos (12U)
1248#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
1249#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
1250#define ADC_CHSELR_CHSEL11_Pos (11U)
1251#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
1252#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
1253#define ADC_CHSELR_CHSEL10_Pos (10U)
1254#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
1255#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
1256#define ADC_CHSELR_CHSEL9_Pos (9U)
1257#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
1258#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
1259#define ADC_CHSELR_CHSEL8_Pos (8U)
1260#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
1261#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
1262#define ADC_CHSELR_CHSEL7_Pos (7U)
1263#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
1264#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
1265#define ADC_CHSELR_CHSEL6_Pos (6U)
1266#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
1267#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
1268#define ADC_CHSELR_CHSEL5_Pos (5U)
1269#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
1270#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
1271#define ADC_CHSELR_CHSEL4_Pos (4U)
1272#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
1273#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
1274#define ADC_CHSELR_CHSEL3_Pos (3U)
1275#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
1276#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
1277#define ADC_CHSELR_CHSEL2_Pos (2U)
1278#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
1279#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
1280#define ADC_CHSELR_CHSEL1_Pos (1U)
1281#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
1282#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
1283#define ADC_CHSELR_CHSEL0_Pos (0U)
1284#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
1285#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
1286
1287#define ADC_CHSELR_SQ_ALL_Pos (0U)
1288#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */
1289#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */
1290
1291#define ADC_CHSELR_SQ8_Pos (28U)
1292#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */
1293#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */
1294#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */
1295#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */
1296#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */
1297#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */
1298
1299#define ADC_CHSELR_SQ7_Pos (24U)
1300#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */
1301#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */
1302#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */
1303#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */
1304#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */
1305#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */
1306
1307#define ADC_CHSELR_SQ6_Pos (20U)
1308#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */
1309#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */
1310#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */
1311#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */
1312#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */
1313#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */
1314
1315#define ADC_CHSELR_SQ5_Pos (16U)
1316#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */
1317#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */
1318#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */
1319#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */
1320#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */
1321#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */
1322
1323#define ADC_CHSELR_SQ4_Pos (12U)
1324#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */
1325#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */
1326#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */
1327#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */
1328#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */
1329#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */
1330
1331#define ADC_CHSELR_SQ3_Pos (8U)
1332#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */
1333#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */
1334#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */
1335#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */
1336#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */
1337#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */
1338
1339#define ADC_CHSELR_SQ2_Pos (4U)
1340#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */
1341#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */
1342#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */
1343#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */
1344#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */
1345#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */
1346
1347#define ADC_CHSELR_SQ1_Pos (0U)
1348#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */
1349#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */
1350#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */
1351#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */
1352#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */
1353#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */
1354
1355/******************** Bit definition for ADC_TR3 register *******************/
1356#define ADC_TR3_LT3_Pos (0U)
1357#define ADC_TR3_LT3_Msk (0xFFFUL << ADC_TR3_LT3_Pos) /*!< 0x00000FFF */
1358#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
1359#define ADC_TR3_LT3_0 (0x001UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
1360#define ADC_TR3_LT3_1 (0x002UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
1361#define ADC_TR3_LT3_2 (0x004UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
1362#define ADC_TR3_LT3_3 (0x008UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
1363#define ADC_TR3_LT3_4 (0x010UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
1364#define ADC_TR3_LT3_5 (0x020UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
1365#define ADC_TR3_LT3_6 (0x040UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
1366#define ADC_TR3_LT3_7 (0x080UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
1367#define ADC_TR3_LT3_8 (0x100UL << ADC_TR3_LT3_Pos) /*!< 0x00000100 */
1368#define ADC_TR3_LT3_9 (0x200UL << ADC_TR3_LT3_Pos) /*!< 0x00000200 */
1369#define ADC_TR3_LT3_10 (0x400UL << ADC_TR3_LT3_Pos) /*!< 0x00000400 */
1370#define ADC_TR3_LT3_11 (0x800UL << ADC_TR3_LT3_Pos) /*!< 0x00000800 */
1371
1372#define ADC_TR3_HT3_Pos (16U)
1373#define ADC_TR3_HT3_Msk (0xFFFUL << ADC_TR3_HT3_Pos) /*!< 0x0FFF0000 */
1374#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
1375#define ADC_TR3_HT3_0 (0x001UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
1376#define ADC_TR3_HT3_1 (0x002UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
1377#define ADC_TR3_HT3_2 (0x004UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
1378#define ADC_TR3_HT3_3 (0x008UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
1379#define ADC_TR3_HT3_4 (0x010UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
1380#define ADC_TR3_HT3_5 (0x020UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
1381#define ADC_TR3_HT3_6 (0x040UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
1382#define ADC_TR3_HT3_7 (0x080UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
1383#define ADC_TR3_HT3_8 (0x100UL << ADC_TR3_HT3_Pos) /*!< 0x01000000 */
1384#define ADC_TR3_HT3_9 (0x200UL << ADC_TR3_HT3_Pos) /*!< 0x02000000 */
1385#define ADC_TR3_HT3_10 (0x400UL << ADC_TR3_HT3_Pos) /*!< 0x04000000 */
1386#define ADC_TR3_HT3_11 (0x800UL << ADC_TR3_HT3_Pos) /*!< 0x08000000 */
1387
1388/******************** Bit definition for ADC_DR register ********************/
1389#define ADC_DR_DATA_Pos (0U)
1390#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
1391#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
1392#define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */
1393#define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */
1394#define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */
1395#define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */
1396#define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */
1397#define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */
1398#define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */
1399#define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */
1400#define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */
1401#define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */
1402#define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */
1403#define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */
1404#define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */
1405#define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */
1406#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */
1407#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */
1408
1409/******************** Bit definition for ADC_AWD2CR register ****************/
1410#define ADC_AWD2CR_AWD2CH_Pos (0U)
1411#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
1412#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
1413#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
1414#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
1415#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
1416#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
1417#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
1418#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
1419#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
1420#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
1421#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
1422#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
1423#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
1424#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
1425#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
1426#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
1427#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
1428#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
1429#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
1430#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
1431#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
1432
1433/******************** Bit definition for ADC_AWD3CR register ****************/
1434#define ADC_AWD3CR_AWD3CH_Pos (0U)
1435#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
1436#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
1437#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
1438#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
1439#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
1440#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
1441#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
1442#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
1443#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
1444#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
1445#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
1446#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
1447#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
1448#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
1449#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
1450#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
1451#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
1452#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
1453#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
1454#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
1455#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
1456
1457/******************** Bit definition for ADC_CALFACT register ***************/
1458#define ADC_CALFACT_CALFACT_Pos (0U)
1459#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
1460#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */
1461#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */
1462#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */
1463#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */
1464#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */
1465#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */
1466#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */
1467#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */
1468
1469/************************* ADC Common registers *****************************/
1470/******************** Bit definition for ADC_CCR register *******************/
1471#define ADC_CCR_PRESC_Pos (18U)
1472#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
1473#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
1474#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
1475#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
1476#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
1477#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
1478
1479#define ADC_CCR_VREFEN_Pos (22U)
1480#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
1481#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
1482#define ADC_CCR_TSEN_Pos (23U)
1483#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
1484#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
1485#define ADC_CCR_VBATEN_Pos (24U)
1486#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
1487#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
1488
1489#define ADC_CCR_LFMEN_Pos (25U)
1490#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
1491#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */
1492
1493/******************************************************************************/
1494/* */
1495/* HDMI-CEC (CEC) */
1496/* */
1497/******************************************************************************/
1498
1499/******************* Bit definition for CEC_CR register *********************/
1500#define CEC_CR_CECEN_Pos (0U)
1501#define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
1502#define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
1503#define CEC_CR_TXSOM_Pos (1U)
1504#define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
1505#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
1506#define CEC_CR_TXEOM_Pos (2U)
1507#define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
1508#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
1509
1510/******************* Bit definition for CEC_CFGR register *******************/
1511#define CEC_CFGR_SFT_Pos (0U)
1512#define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
1513#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
1514#define CEC_CFGR_RXTOL_Pos (3U)
1515#define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
1516#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
1517#define CEC_CFGR_BRESTP_Pos (4U)
1518#define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
1519#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
1520#define CEC_CFGR_BREGEN_Pos (5U)
1521#define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
1522#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
1523#define CEC_CFGR_LBPEGEN_Pos (6U)
1524#define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
1525#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error gener. */
1526#define CEC_CFGR_BRDNOGEN_Pos (7U)
1527#define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
1528#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No Error generation */
1529#define CEC_CFGR_SFTOPT_Pos (8U)
1530#define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
1531#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
1532#define CEC_CFGR_OAR_Pos (16U)
1533#define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
1534#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
1535#define CEC_CFGR_LSTN_Pos (31U)
1536#define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
1537#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
1538
1539/******************* Bit definition for CEC_TXDR register *******************/
1540#define CEC_TXDR_TXD_Pos (0U)
1541#define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
1542#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
1543
1544/******************* Bit definition for CEC_RXDR register *******************/
1545#define CEC_RXDR_RXD_Pos (0U)
1546#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */
1547#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */
1548
1549/******************* Bit definition for CEC_ISR register ********************/
1550#define CEC_ISR_RXBR_Pos (0U)
1551#define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
1552#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
1553#define CEC_ISR_RXEND_Pos (1U)
1554#define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
1555#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
1556#define CEC_ISR_RXOVR_Pos (2U)
1557#define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
1558#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
1559#define CEC_ISR_BRE_Pos (3U)
1560#define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
1561#define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
1562#define CEC_ISR_SBPE_Pos (4U)
1563#define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
1564#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
1565#define CEC_ISR_LBPE_Pos (5U)
1566#define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
1567#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
1568#define CEC_ISR_RXACKE_Pos (6U)
1569#define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
1570#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
1571#define CEC_ISR_ARBLST_Pos (7U)
1572#define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
1573#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
1574#define CEC_ISR_TXBR_Pos (8U)
1575#define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
1576#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
1577#define CEC_ISR_TXEND_Pos (9U)
1578#define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
1579#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
1580#define CEC_ISR_TXUDR_Pos (10U)
1581#define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
1582#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
1583#define CEC_ISR_TXERR_Pos (11U)
1584#define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
1585#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
1586#define CEC_ISR_TXACKE_Pos (12U)
1587#define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
1588#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
1589
1590/******************* Bit definition for CEC_IER register ********************/
1591#define CEC_IER_RXBRIE_Pos (0U)
1592#define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
1593#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
1594#define CEC_IER_RXENDIE_Pos (1U)
1595#define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
1596#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
1597#define CEC_IER_RXOVRIE_Pos (2U)
1598#define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
1599#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
1600#define CEC_IER_BREIE_Pos (3U)
1601#define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
1602#define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
1603#define CEC_IER_SBPEIE_Pos (4U)
1604#define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
1605#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable*/
1606#define CEC_IER_LBPEIE_Pos (5U)
1607#define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
1608#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
1609#define CEC_IER_RXACKEIE_Pos (6U)
1610#define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
1611#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
1612#define CEC_IER_ARBLSTIE_Pos (7U)
1613#define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
1614#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
1615#define CEC_IER_TXBRIE_Pos (8U)
1616#define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
1617#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
1618#define CEC_IER_TXENDIE_Pos (9U)
1619#define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
1620#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
1621#define CEC_IER_TXUDRIE_Pos (10U)
1622#define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
1623#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
1624#define CEC_IER_TXERRIE_Pos (11U)
1625#define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
1626#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
1627#define CEC_IER_TXACKEIE_Pos (12U)
1628#define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
1629#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
1630
1631/******************************************************************************/
1632/* */
1633/* CRC calculation unit */
1634/* */
1635/******************************************************************************/
1636/******************* Bit definition for CRC_DR register *********************/
1637#define CRC_DR_DR_Pos (0U)
1638#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
1639#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
1640
1641/******************* Bit definition for CRC_IDR register ********************/
1642#define CRC_IDR_IDR_Pos (0U)
1643#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
1644#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */
1645
1646/******************** Bit definition for CRC_CR register ********************/
1647#define CRC_CR_RESET_Pos (0U)
1648#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
1649#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
1650#define CRC_CR_POLYSIZE_Pos (3U)
1651#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
1652#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
1653#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
1654#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
1655#define CRC_CR_REV_IN_Pos (5U)
1656#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
1657#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
1658#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
1659#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
1660#define CRC_CR_REV_OUT_Pos (7U)
1661#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
1662#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
1663
1664/******************* Bit definition for CRC_INIT register *******************/
1665#define CRC_INIT_INIT_Pos (0U)
1666#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
1667#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
1668
1669/******************* Bit definition for CRC_POL register ********************/
1670#define CRC_POL_POL_Pos (0U)
1671#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
1672#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
1673
1674/******************************************************************************/
1675/* */
1676/* Advanced Encryption Standard (AES) */
1677/* */
1678/******************************************************************************/
1679/******************* Bit definition for AES_CR register *********************/
1680#define AES_CR_EN_Pos (0U)
1681#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */
1682#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */
1683#define AES_CR_DATATYPE_Pos (1U)
1684#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */
1685#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */
1686#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */
1687#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */
1688
1689#define AES_CR_MODE_Pos (3U)
1690#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */
1691#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */
1692#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */
1693#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */
1694
1695#define AES_CR_CHMOD_Pos (5U)
1696#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */
1697#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */
1698#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */
1699#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */
1700#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */
1701
1702#define AES_CR_CCFC_Pos (7U)
1703#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */
1704#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */
1705#define AES_CR_ERRC_Pos (8U)
1706#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */
1707#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */
1708#define AES_CR_CCFIE_Pos (9U)
1709#define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos) /*!< 0x00000200 */
1710#define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */
1711#define AES_CR_ERRIE_Pos (10U)
1712#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */
1713#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */
1714#define AES_CR_DMAINEN_Pos (11U)
1715#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */
1716#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */
1717#define AES_CR_DMAOUTEN_Pos (12U)
1718#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */
1719#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */
1720
1721#define AES_CR_NPBLB_Pos (20U)
1722#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */
1723#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in last block of payload. */
1724#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */
1725#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */
1726#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */
1727#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */
1728
1729#define AES_CR_GCMPH_Pos (13U)
1730#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */
1731#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */
1732#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */
1733#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */
1734
1735#define AES_CR_KEYSIZE_Pos (18U)
1736#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */
1737#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */
1738
1739/******************* Bit definition for AES_SR register *********************/
1740#define AES_SR_CCF_Pos (0U)
1741#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */
1742#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */
1743#define AES_SR_RDERR_Pos (1U)
1744#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */
1745#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */
1746#define AES_SR_WRERR_Pos (2U)
1747#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */
1748#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */
1749#define AES_SR_BUSY_Pos (3U)
1750#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */
1751#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */
1752
1753/******************* Bit definition for AES_DINR register *******************/
1754#define AES_DINR_Pos (0U)
1755#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */
1756#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */
1757
1758/******************* Bit definition for AES_DOUTR register ******************/
1759#define AES_DOUTR_Pos (0U)
1760#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */
1761#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */
1762
1763/******************* Bit definition for AES_KEYR0 register ******************/
1764#define AES_KEYR0_Pos (0U)
1765#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */
1766#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */
1767
1768/******************* Bit definition for AES_KEYR1 register ******************/
1769#define AES_KEYR1_Pos (0U)
1770#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */
1771#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */
1772
1773/******************* Bit definition for AES_KEYR2 register ******************/
1774#define AES_KEYR2_Pos (0U)
1775#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */
1776#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */
1777
1778/******************* Bit definition for AES_KEYR3 register ******************/
1779#define AES_KEYR3_Pos (0U)
1780#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */
1781#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */
1782
1783/******************* Bit definition for AES_KEYR4 register ******************/
1784#define AES_KEYR4_Pos (0U)
1785#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */
1786#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */
1787
1788/******************* Bit definition for AES_KEYR5 register ******************/
1789#define AES_KEYR5_Pos (0U)
1790#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */
1791#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */
1792
1793/******************* Bit definition for AES_KEYR6 register ******************/
1794#define AES_KEYR6_Pos (0U)
1795#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */
1796#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */
1797
1798/******************* Bit definition for AES_KEYR7 register ******************/
1799#define AES_KEYR7_Pos (0U)
1800#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */
1801#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */
1802
1803/******************* Bit definition for AES_IVR0 register ******************/
1804#define AES_IVR0_Pos (0U)
1805#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */
1806#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */
1807
1808/******************* Bit definition for AES_IVR1 register ******************/
1809#define AES_IVR1_Pos (0U)
1810#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */
1811#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */
1812
1813/******************* Bit definition for AES_IVR2 register ******************/
1814#define AES_IVR2_Pos (0U)
1815#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */
1816#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */
1817
1818/******************* Bit definition for AES_IVR3 register ******************/
1819#define AES_IVR3_Pos (0U)
1820#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */
1821#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */
1822
1823/******************* Bit definition for AES_SUSP0R register ******************/
1824#define AES_SUSP0R_Pos (0U)
1825#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */
1826#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */
1827
1828/******************* Bit definition for AES_SUSP1R register ******************/
1829#define AES_SUSP1R_Pos (0U)
1830#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */
1831#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */
1832
1833/******************* Bit definition for AES_SUSP2R register ******************/
1834#define AES_SUSP2R_Pos (0U)
1835#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */
1836#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */
1837
1838/******************* Bit definition for AES_SUSP3R register ******************/
1839#define AES_SUSP3R_Pos (0U)
1840#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */
1841#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */
1842
1843/******************* Bit definition for AES_SUSP4R register ******************/
1844#define AES_SUSP4R_Pos (0U)
1845#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */
1846#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */
1847
1848/******************* Bit definition for AES_SUSP5R register ******************/
1849#define AES_SUSP5R_Pos (0U)
1850#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */
1851#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */
1852
1853/******************* Bit definition for AES_SUSP6R register ******************/
1854#define AES_SUSP6R_Pos (0U)
1855#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */
1856#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */
1857
1858/******************* Bit definition for AES_SUSP7R register ******************/
1859#define AES_SUSP7R_Pos (0U)
1860#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */
1861#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */
1862
1863
1864/******************************************************************************/
1865/* */
1866/* Digital to Analog Converter */
1867/* */
1868/******************************************************************************/
1869/*
1870* @brief Specific device feature definitions
1871*/
1872#define DAC_ADDITIONAL_TRIGGERS_SUPPORT
1873
1874/******************** Bit definition for DAC_CR register ********************/
1875#define DAC_CR_EN1_Pos (0U)
1876#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
1877#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
1878#define DAC_CR_TEN1_Pos (1U)
1879#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
1880#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
1881
1882#define DAC_CR_TSEL1_Pos (2U)
1883#define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
1884#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
1885#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
1886#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
1887#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
1888#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
1889
1890#define DAC_CR_WAVE1_Pos (6U)
1891#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
1892#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
1893#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
1894#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
1895
1896#define DAC_CR_MAMP1_Pos (8U)
1897#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
1898#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
1899#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
1900#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
1901#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
1902#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
1903
1904#define DAC_CR_DMAEN1_Pos (12U)
1905#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
1906#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
1907#define DAC_CR_DMAUDRIE1_Pos (13U)
1908#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
1909#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
1910#define DAC_CR_CEN1_Pos (14U)
1911#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
1912#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
1913
1914#define DAC_CR_EN2_Pos (16U)
1915#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
1916#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
1917#define DAC_CR_TEN2_Pos (17U)
1918#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
1919#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
1920
1921#define DAC_CR_TSEL2_Pos (18U)
1922#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
1923#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
1924#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
1925#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
1926#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
1927#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
1928
1929#define DAC_CR_WAVE2_Pos (22U)
1930#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
1931#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
1932#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
1933#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
1934
1935#define DAC_CR_MAMP2_Pos (24U)
1936#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
1937#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
1938#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
1939#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
1940#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
1941#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
1942
1943#define DAC_CR_DMAEN2_Pos (28U)
1944#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
1945#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
1946#define DAC_CR_DMAUDRIE2_Pos (29U)
1947#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
1948#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
1949#define DAC_CR_CEN2_Pos (30U)
1950#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
1951#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
1952
1953/***************** Bit definition for DAC_SWTRIGR register ******************/
1954#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
1955#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
1956#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
1957#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
1958#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
1959#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
1960
1961/***************** Bit definition for DAC_DHR12R1 register ******************/
1962#define DAC_DHR12R1_DACC1DHR_Pos (0U)
1963#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
1964#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
1965
1966/***************** Bit definition for DAC_DHR12L1 register ******************/
1967#define DAC_DHR12L1_DACC1DHR_Pos (4U)
1968#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
1969#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
1970
1971/****************** Bit definition for DAC_DHR8R1 register ******************/
1972#define DAC_DHR8R1_DACC1DHR_Pos (0U)
1973#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
1974#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
1975
1976/***************** Bit definition for DAC_DHR12R2 register ******************/
1977#define DAC_DHR12R2_DACC2DHR_Pos (0U)
1978#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
1979#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
1980
1981/***************** Bit definition for DAC_DHR12L2 register ******************/
1982#define DAC_DHR12L2_DACC2DHR_Pos (4U)
1983#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
1984#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
1985
1986/****************** Bit definition for DAC_DHR8R2 register ******************/
1987#define DAC_DHR8R2_DACC2DHR_Pos (0U)
1988#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
1989#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
1990
1991/***************** Bit definition for DAC_DHR12RD register ******************/
1992#define DAC_DHR12RD_DACC1DHR_Pos (0U)
1993#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
1994#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
1995#define DAC_DHR12RD_DACC2DHR_Pos (16U)
1996#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
1997#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
1998
1999/***************** Bit definition for DAC_DHR12LD register ******************/
2000#define DAC_DHR12LD_DACC1DHR_Pos (4U)
2001#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
2002#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
2003#define DAC_DHR12LD_DACC2DHR_Pos (20U)
2004#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
2005#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
2006
2007/****************** Bit definition for DAC_DHR8RD register ******************/
2008#define DAC_DHR8RD_DACC1DHR_Pos (0U)
2009#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
2010#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
2011#define DAC_DHR8RD_DACC2DHR_Pos (8U)
2012#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
2013#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
2014
2015/******************* Bit definition for DAC_DOR1 register *******************/
2016#define DAC_DOR1_DACC1DOR_Pos (0U)
2017#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
2018#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
2019
2020/******************* Bit definition for DAC_DOR2 register *******************/
2021#define DAC_DOR2_DACC2DOR_Pos (0U)
2022#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
2023#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
2024
2025/******************** Bit definition for DAC_SR register ********************/
2026#define DAC_SR_DMAUDR1_Pos (13U)
2027#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
2028#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
2029#define DAC_SR_CAL_FLAG1_Pos (14U)
2030#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
2031#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
2032#define DAC_SR_BWST1_Pos (15U)
2033#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
2034#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
2035
2036#define DAC_SR_DMAUDR2_Pos (29U)
2037#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
2038#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
2039#define DAC_SR_CAL_FLAG2_Pos (30U)
2040#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
2041#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
2042#define DAC_SR_BWST2_Pos (31U)
2043#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
2044#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
2045
2046/******************* Bit definition for DAC_CCR register ********************/
2047#define DAC_CCR_OTRIM1_Pos (0U)
2048#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
2049#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
2050#define DAC_CCR_OTRIM2_Pos (16U)
2051#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
2052#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
2053
2054/******************* Bit definition for DAC_MCR register *******************/
2055#define DAC_MCR_MODE1_Pos (0U)
2056#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
2057#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
2058#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
2059#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
2060#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
2061
2062#define DAC_MCR_MODE2_Pos (16U)
2063#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
2064#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
2065#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
2066#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
2067#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
2068
2069/****************** Bit definition for DAC_SHSR1 register ******************/
2070#define DAC_SHSR1_TSAMPLE1_Pos (0U)
2071#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
2072#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
2073
2074/****************** Bit definition for DAC_SHSR2 register ******************/
2075#define DAC_SHSR2_TSAMPLE2_Pos (0U)
2076#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
2077#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
2078
2079/****************** Bit definition for DAC_SHHR register ******************/
2080#define DAC_SHHR_THOLD1_Pos (0U)
2081#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
2082#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
2083#define DAC_SHHR_THOLD2_Pos (16U)
2084#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
2085#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
2086
2087/****************** Bit definition for DAC_SHRR register ******************/
2088#define DAC_SHRR_TREFRESH1_Pos (0U)
2089#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
2090#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
2091#define DAC_SHRR_TREFRESH2_Pos (16U)
2092#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
2093#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
2094
2095
2096/******************************************************************************/
2097/* */
2098/* Debug MCU */
2099/* */
2100/******************************************************************************/
2101
2102/******************************************************************************/
2103/* */
2104/* DMA Controller (DMA) */
2105/* */
2106/******************************************************************************/
2107
2108/******************* Bit definition for DMA_ISR register ********************/
2109#define DMA_ISR_GIF1_Pos (0U)
2110#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
2111#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
2112#define DMA_ISR_TCIF1_Pos (1U)
2113#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
2114#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
2115#define DMA_ISR_HTIF1_Pos (2U)
2116#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
2117#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
2118#define DMA_ISR_TEIF1_Pos (3U)
2119#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
2120#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
2121#define DMA_ISR_GIF2_Pos (4U)
2122#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
2123#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
2124#define DMA_ISR_TCIF2_Pos (5U)
2125#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
2126#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
2127#define DMA_ISR_HTIF2_Pos (6U)
2128#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
2129#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
2130#define DMA_ISR_TEIF2_Pos (7U)
2131#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
2132#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
2133#define DMA_ISR_GIF3_Pos (8U)
2134#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
2135#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
2136#define DMA_ISR_TCIF3_Pos (9U)
2137#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
2138#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
2139#define DMA_ISR_HTIF3_Pos (10U)
2140#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
2141#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
2142#define DMA_ISR_TEIF3_Pos (11U)
2143#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
2144#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
2145#define DMA_ISR_GIF4_Pos (12U)
2146#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
2147#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
2148#define DMA_ISR_TCIF4_Pos (13U)
2149#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
2150#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
2151#define DMA_ISR_HTIF4_Pos (14U)
2152#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
2153#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
2154#define DMA_ISR_TEIF4_Pos (15U)
2155#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
2156#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
2157#define DMA_ISR_GIF5_Pos (16U)
2158#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
2159#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
2160#define DMA_ISR_TCIF5_Pos (17U)
2161#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
2162#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
2163#define DMA_ISR_HTIF5_Pos (18U)
2164#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
2165#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
2166#define DMA_ISR_TEIF5_Pos (19U)
2167#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
2168#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
2169#define DMA_ISR_GIF6_Pos (20U)
2170#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
2171#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
2172#define DMA_ISR_TCIF6_Pos (21U)
2173#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
2174#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
2175#define DMA_ISR_HTIF6_Pos (22U)
2176#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
2177#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
2178#define DMA_ISR_TEIF6_Pos (23U)
2179#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
2180#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
2181#define DMA_ISR_GIF7_Pos (24U)
2182#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
2183#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
2184#define DMA_ISR_TCIF7_Pos (25U)
2185#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
2186#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
2187#define DMA_ISR_HTIF7_Pos (26U)
2188#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
2189#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
2190#define DMA_ISR_TEIF7_Pos (27U)
2191#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
2192#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
2193
2194/******************* Bit definition for DMA_IFCR register *******************/
2195#define DMA_IFCR_CGIF1_Pos (0U)
2196#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
2197#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
2198#define DMA_IFCR_CTCIF1_Pos (1U)
2199#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
2200#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
2201#define DMA_IFCR_CHTIF1_Pos (2U)
2202#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
2203#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
2204#define DMA_IFCR_CTEIF1_Pos (3U)
2205#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
2206#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
2207#define DMA_IFCR_CGIF2_Pos (4U)
2208#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
2209#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
2210#define DMA_IFCR_CTCIF2_Pos (5U)
2211#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
2212#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
2213#define DMA_IFCR_CHTIF2_Pos (6U)
2214#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
2215#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
2216#define DMA_IFCR_CTEIF2_Pos (7U)
2217#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
2218#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
2219#define DMA_IFCR_CGIF3_Pos (8U)
2220#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
2221#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
2222#define DMA_IFCR_CTCIF3_Pos (9U)
2223#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
2224#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
2225#define DMA_IFCR_CHTIF3_Pos (10U)
2226#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
2227#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
2228#define DMA_IFCR_CTEIF3_Pos (11U)
2229#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
2230#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
2231#define DMA_IFCR_CGIF4_Pos (12U)
2232#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
2233#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
2234#define DMA_IFCR_CTCIF4_Pos (13U)
2235#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
2236#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
2237#define DMA_IFCR_CHTIF4_Pos (14U)
2238#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
2239#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
2240#define DMA_IFCR_CTEIF4_Pos (15U)
2241#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
2242#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
2243#define DMA_IFCR_CGIF5_Pos (16U)
2244#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
2245#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
2246#define DMA_IFCR_CTCIF5_Pos (17U)
2247#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
2248#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
2249#define DMA_IFCR_CHTIF5_Pos (18U)
2250#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
2251#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
2252#define DMA_IFCR_CTEIF5_Pos (19U)
2253#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
2254#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
2255#define DMA_IFCR_CGIF6_Pos (20U)
2256#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
2257#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
2258#define DMA_IFCR_CTCIF6_Pos (21U)
2259#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
2260#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
2261#define DMA_IFCR_CHTIF6_Pos (22U)
2262#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
2263#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
2264#define DMA_IFCR_CTEIF6_Pos (23U)
2265#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
2266#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
2267#define DMA_IFCR_CGIF7_Pos (24U)
2268#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
2269#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
2270#define DMA_IFCR_CTCIF7_Pos (25U)
2271#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
2272#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
2273#define DMA_IFCR_CHTIF7_Pos (26U)
2274#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
2275#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
2276#define DMA_IFCR_CTEIF7_Pos (27U)
2277#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
2278#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
2279
2280/******************* Bit definition for DMA_CCR register ********************/
2281#define DMA_CCR_EN_Pos (0U)
2282#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
2283#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
2284#define DMA_CCR_TCIE_Pos (1U)
2285#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
2286#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
2287#define DMA_CCR_HTIE_Pos (2U)
2288#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
2289#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
2290#define DMA_CCR_TEIE_Pos (3U)
2291#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
2292#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
2293#define DMA_CCR_DIR_Pos (4U)
2294#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
2295#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
2296#define DMA_CCR_CIRC_Pos (5U)
2297#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
2298#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
2299#define DMA_CCR_PINC_Pos (6U)
2300#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
2301#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
2302#define DMA_CCR_MINC_Pos (7U)
2303#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
2304#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
2305
2306#define DMA_CCR_PSIZE_Pos (8U)
2307#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
2308#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
2309#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
2310#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
2311
2312#define DMA_CCR_MSIZE_Pos (10U)
2313#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
2314#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
2315#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
2316#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
2317
2318#define DMA_CCR_PL_Pos (12U)
2319#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
2320#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
2321#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
2322#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
2323
2324#define DMA_CCR_MEM2MEM_Pos (14U)
2325#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
2326#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
2327
2328/****************** Bit definition for DMA_CNDTR register *******************/
2329#define DMA_CNDTR_NDT_Pos (0U)
2330#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
2331#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
2332
2333/****************** Bit definition for DMA_CPAR register ********************/
2334#define DMA_CPAR_PA_Pos (0U)
2335#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
2336#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
2337
2338/****************** Bit definition for DMA_CMAR register ********************/
2339#define DMA_CMAR_MA_Pos (0U)
2340#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
2341#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
2342
2343/******************************************************************************/
2344/* */
2345/* DMAMUX Controller */
2346/* */
2347/******************************************************************************/
2348/******************** Bits definition for DMAMUX_CxCR register **************/
2349#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
2350#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */
2351#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */
2352#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
2353#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
2354#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
2355#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
2356#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
2357#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
2358#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
2359#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
2360#define DMAMUX_CxCR_SOIE_Pos (8U)
2361#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
2362#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */
2363#define DMAMUX_CxCR_EGE_Pos (9U)
2364#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */
2365#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */
2366#define DMAMUX_CxCR_SE_Pos (16U)
2367#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */
2368#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */
2369#define DMAMUX_CxCR_SPOL_Pos (17U)
2370#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
2371#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */
2372#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */
2373#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */
2374#define DMAMUX_CxCR_NBREQ_Pos (19U)
2375#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
2376#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */
2377#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
2378#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
2379#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
2380#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
2381#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
2382#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
2383#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
2384#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */
2385#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
2386#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
2387#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
2388#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
2389#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
2390
2391/******************* Bits definition for DMAMUX_CSR register **************/
2392#define DMAMUX_CSR_SOF0_Pos (0U)
2393#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */
2394#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */
2395#define DMAMUX_CSR_SOF1_Pos (1U)
2396#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */
2397#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */
2398#define DMAMUX_CSR_SOF2_Pos (2U)
2399#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */
2400#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */
2401#define DMAMUX_CSR_SOF3_Pos (3U)
2402#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */
2403#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Synchronization Overrun Flag 3 */
2404#define DMAMUX_CSR_SOF4_Pos (4U)
2405#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */
2406#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Synchronization Overrun Flag 4 */
2407#define DMAMUX_CSR_SOF5_Pos (5U)
2408#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */
2409#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Synchronization Overrun Flag 5 */
2410#define DMAMUX_CSR_SOF6_Pos (6U)
2411#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */
2412#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Synchronization Overrun Flag 6 */
2413
2414/******************** Bits definition for DMAMUX_CFR register **************/
2415#define DMAMUX_CFR_CSOF0_Pos (0U)
2416#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
2417#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */
2418#define DMAMUX_CFR_CSOF1_Pos (1U)
2419#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
2420#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */
2421#define DMAMUX_CFR_CSOF2_Pos (2U)
2422#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
2423#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */
2424#define DMAMUX_CFR_CSOF3_Pos (3U)
2425#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
2426#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Clear Overrun Flag 3 */
2427#define DMAMUX_CFR_CSOF4_Pos (4U)
2428#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
2429#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Clear Overrun Flag 4 */
2430#define DMAMUX_CFR_CSOF5_Pos (5U)
2431#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
2432#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Clear Overrun Flag 5 */
2433#define DMAMUX_CFR_CSOF6_Pos (6U)
2434#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
2435#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Clear Overrun Flag 6 */
2436
2437/******************** Bits definition for DMAMUX_RGxCR register ************/
2438#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
2439#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
2440#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */
2441#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
2442#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
2443#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
2444#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
2445#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
2446#define DMAMUX_RGxCR_OIE_Pos (8U)
2447#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
2448#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */
2449#define DMAMUX_RGxCR_GE_Pos (16U)
2450#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */
2451#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */
2452#define DMAMUX_RGxCR_GPOL_Pos (17U)
2453#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
2454#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */
2455#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
2456#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
2457#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
2458#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
2459#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */
2460#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
2461#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */
2462#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */
2463#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */
2464#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */
2465
2466/******************** Bits definition for DMAMUX_RGSR register **************/
2467#define DMAMUX_RGSR_OF0_Pos (0U)
2468#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */
2469#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */
2470#define DMAMUX_RGSR_OF1_Pos (1U)
2471#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */
2472#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */
2473#define DMAMUX_RGSR_OF2_Pos (2U)
2474#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */
2475#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */
2476#define DMAMUX_RGSR_OF3_Pos (3U)
2477#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */
2478#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */
2479
2480/******************** Bits definition for DMAMUX_RGCFR register **************/
2481#define DMAMUX_RGCFR_COF0_Pos (0U)
2482#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
2483#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */
2484#define DMAMUX_RGCFR_COF1_Pos (1U)
2485#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
2486#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */
2487#define DMAMUX_RGCFR_COF2_Pos (2U)
2488#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
2489#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */
2490#define DMAMUX_RGCFR_COF3_Pos (3U)
2491#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
2492#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */
2493
2494/******************************************************************************/
2495/* */
2496/* External Interrupt/Event Controller */
2497/* */
2498/******************************************************************************/
2499/****************** Bit definition for EXTI_RTSR1 register ******************/
2500#define EXTI_RTSR1_RT0_Pos (0U)
2501#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
2502#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */
2503#define EXTI_RTSR1_RT1_Pos (1U)
2504#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
2505#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */
2506#define EXTI_RTSR1_RT2_Pos (2U)
2507#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
2508#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */
2509#define EXTI_RTSR1_RT3_Pos (3U)
2510#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
2511#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */
2512#define EXTI_RTSR1_RT4_Pos (4U)
2513#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
2514#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */
2515#define EXTI_RTSR1_RT5_Pos (5U)
2516#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
2517#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */
2518#define EXTI_RTSR1_RT6_Pos (6U)
2519#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
2520#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */
2521#define EXTI_RTSR1_RT7_Pos (7U)
2522#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
2523#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */
2524#define EXTI_RTSR1_RT8_Pos (8U)
2525#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
2526#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */
2527#define EXTI_RTSR1_RT9_Pos (9U)
2528#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
2529#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */
2530#define EXTI_RTSR1_RT10_Pos (10U)
2531#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
2532#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */
2533#define EXTI_RTSR1_RT11_Pos (11U)
2534#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
2535#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */
2536#define EXTI_RTSR1_RT12_Pos (12U)
2537#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
2538#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */
2539#define EXTI_RTSR1_RT13_Pos (13U)
2540#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
2541#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */
2542#define EXTI_RTSR1_RT14_Pos (14U)
2543#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
2544#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */
2545#define EXTI_RTSR1_RT15_Pos (15U)
2546#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
2547#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */
2548#define EXTI_RTSR1_RT16_Pos (16U)
2549#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
2550#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger configuration for input line 16 */
2551#define EXTI_RTSR1_RT17_Pos (17U)
2552#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */
2553#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger configuration for input line 17 */
2554#define EXTI_RTSR1_RT18_Pos (18U)
2555#define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */
2556#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger configuration for input line 18 */
2557
2558/****************** Bit definition for EXTI_FTSR1 register ******************/
2559#define EXTI_FTSR1_FT0_Pos (0U)
2560#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
2561#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */
2562#define EXTI_FTSR1_FT1_Pos (1U)
2563#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
2564#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */
2565#define EXTI_FTSR1_FT2_Pos (2U)
2566#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
2567#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */
2568#define EXTI_FTSR1_FT3_Pos (3U)
2569#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
2570#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */
2571#define EXTI_FTSR1_FT4_Pos (4U)
2572#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
2573#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */
2574#define EXTI_FTSR1_FT5_Pos (5U)
2575#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
2576#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */
2577#define EXTI_FTSR1_FT6_Pos (6U)
2578#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
2579#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */
2580#define EXTI_FTSR1_FT7_Pos (7U)
2581#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
2582#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */
2583#define EXTI_FTSR1_FT8_Pos (8U)
2584#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
2585#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */
2586#define EXTI_FTSR1_FT9_Pos (9U)
2587#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
2588#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */
2589#define EXTI_FTSR1_FT10_Pos (10U)
2590#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
2591#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */
2592#define EXTI_FTSR1_FT11_Pos (11U)
2593#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
2594#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */
2595#define EXTI_FTSR1_FT12_Pos (12U)
2596#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
2597#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */
2598#define EXTI_FTSR1_FT13_Pos (13U)
2599#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
2600#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */
2601#define EXTI_FTSR1_FT14_Pos (14U)
2602#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
2603#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */
2604#define EXTI_FTSR1_FT15_Pos (15U)
2605#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
2606#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */
2607#define EXTI_FTSR1_FT16_Pos (16U)
2608#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
2609#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger configuration for input line 16 */
2610#define EXTI_FTSR1_FT17_Pos (17U)
2611#define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) /*!< 0x00020000 */
2612#define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk /*!< Falling trigger configuration for input line 17 */
2613#define EXTI_FTSR1_FT18_Pos (18U)
2614#define EXTI_FTSR1_FT18_Msk (0x1UL << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */
2615#define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger configuration for input line 18 */
2616
2617/****************** Bit definition for EXTI_SWIER1 register *****************/
2618#define EXTI_SWIER1_SWI0_Pos (0U)
2619#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
2620#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
2621#define EXTI_SWIER1_SWI1_Pos (1U)
2622#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
2623#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
2624#define EXTI_SWIER1_SWI2_Pos (2U)
2625#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
2626#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
2627#define EXTI_SWIER1_SWI3_Pos (3U)
2628#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
2629#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
2630#define EXTI_SWIER1_SWI4_Pos (4U)
2631#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
2632#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
2633#define EXTI_SWIER1_SWI5_Pos (5U)
2634#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
2635#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
2636#define EXTI_SWIER1_SWI6_Pos (6U)
2637#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
2638#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
2639#define EXTI_SWIER1_SWI7_Pos (7U)
2640#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
2641#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
2642#define EXTI_SWIER1_SWI8_Pos (8U)
2643#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
2644#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
2645#define EXTI_SWIER1_SWI9_Pos (9U)
2646#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
2647#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
2648#define EXTI_SWIER1_SWI10_Pos (10U)
2649#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
2650#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
2651#define EXTI_SWIER1_SWI11_Pos (11U)
2652#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
2653#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
2654#define EXTI_SWIER1_SWI12_Pos (12U)
2655#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
2656#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
2657#define EXTI_SWIER1_SWI13_Pos (13U)
2658#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
2659#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
2660#define EXTI_SWIER1_SWI14_Pos (14U)
2661#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
2662#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
2663#define EXTI_SWIER1_SWI15_Pos (15U)
2664#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
2665#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
2666#define EXTI_SWIER1_SWI16_Pos (16U)
2667#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
2668#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
2669#define EXTI_SWIER1_SWI17_Pos (17U)
2670#define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) /*!< 0x00020000 */
2671#define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk /*!< Software Interrupt on line 17 */
2672#define EXTI_SWIER1_SWI18_Pos (18U)
2673#define EXTI_SWIER1_SWI18_Msk (0x1UL << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */
2674#define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */
2675
2676/******************* Bit definition for EXTI_RPR1 register ******************/
2677#define EXTI_RPR1_RPIF0_Pos (0U)
2678#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */
2679#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */
2680#define EXTI_RPR1_RPIF1_Pos (1U)
2681#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */
2682#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */
2683#define EXTI_RPR1_RPIF2_Pos (2U)
2684#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */
2685#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */
2686#define EXTI_RPR1_RPIF3_Pos (3U)
2687#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */
2688#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */
2689#define EXTI_RPR1_RPIF4_Pos (4U)
2690#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */
2691#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */
2692#define EXTI_RPR1_RPIF5_Pos (5U)
2693#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */
2694#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */
2695#define EXTI_RPR1_RPIF6_Pos (6U)
2696#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */
2697#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */
2698#define EXTI_RPR1_RPIF7_Pos (7U)
2699#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */
2700#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */
2701#define EXTI_RPR1_RPIF8_Pos (8U)
2702#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */
2703#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */
2704#define EXTI_RPR1_RPIF9_Pos (9U)
2705#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */
2706#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */
2707#define EXTI_RPR1_RPIF10_Pos (10U)
2708#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */
2709#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */
2710#define EXTI_RPR1_RPIF11_Pos (11U)
2711#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */
2712#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */
2713#define EXTI_RPR1_RPIF12_Pos (12U)
2714#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */
2715#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */
2716#define EXTI_RPR1_RPIF13_Pos (13U)
2717#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */
2718#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */
2719#define EXTI_RPR1_RPIF14_Pos (14U)
2720#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */
2721#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */
2722#define EXTI_RPR1_RPIF15_Pos (15U)
2723#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */
2724#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */
2725#define EXTI_RPR1_RPIF16_Pos (16U)
2726#define EXTI_RPR1_RPIF16_Msk (0x1UL << EXTI_RPR1_RPIF16_Pos) /*!< 0x00010000 */
2727#define EXTI_RPR1_RPIF16 EXTI_RPR1_RPIF16_Msk /*!< Rising Pending Interrupt Flag on line 16 */
2728#define EXTI_RPR1_RPIF17_Pos (17U)
2729#define EXTI_RPR1_RPIF17_Msk (0x1UL << EXTI_RPR1_RPIF17_Pos) /*!< 0x00020000 */
2730#define EXTI_RPR1_RPIF17 EXTI_RPR1_RPIF17_Msk /*!< Rising Pending Interrupt Flag on line 17 */
2731#define EXTI_RPR1_RPIF18_Pos (18U)
2732#define EXTI_RPR1_RPIF18_Msk (0x1UL << EXTI_RPR1_RPIF18_Pos) /*!< 0x00040000 */
2733#define EXTI_RPR1_RPIF18 EXTI_RPR1_RPIF18_Msk /*!< Rising Pending Interrupt Flag on line 18 */
2734
2735/******************* Bit definition for EXTI_FPR1 register ******************/
2736#define EXTI_FPR1_FPIF0_Pos (0U)
2737#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */
2738#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */
2739#define EXTI_FPR1_FPIF1_Pos (1U)
2740#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */
2741#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */
2742#define EXTI_FPR1_FPIF2_Pos (2U)
2743#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */
2744#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */
2745#define EXTI_FPR1_FPIF3_Pos (3U)
2746#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */
2747#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */
2748#define EXTI_FPR1_FPIF4_Pos (4U)
2749#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */
2750#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */
2751#define EXTI_FPR1_FPIF5_Pos (5U)
2752#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */
2753#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */
2754#define EXTI_FPR1_FPIF6_Pos (6U)
2755#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */
2756#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */
2757#define EXTI_FPR1_FPIF7_Pos (7U)
2758#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */
2759#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */
2760#define EXTI_FPR1_FPIF8_Pos (8U)
2761#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */
2762#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */
2763#define EXTI_FPR1_FPIF9_Pos (9U)
2764#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */
2765#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */
2766#define EXTI_FPR1_FPIF10_Pos (10U)
2767#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */
2768#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */
2769#define EXTI_FPR1_FPIF11_Pos (11U)
2770#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */
2771#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */
2772#define EXTI_FPR1_FPIF12_Pos (12U)
2773#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */
2774#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */
2775#define EXTI_FPR1_FPIF13_Pos (13U)
2776#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */
2777#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */
2778#define EXTI_FPR1_FPIF14_Pos (14U)
2779#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */
2780#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */
2781#define EXTI_FPR1_FPIF15_Pos (15U)
2782#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */
2783#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */
2784#define EXTI_FPR1_FPIF16_Pos (16U)
2785#define EXTI_FPR1_FPIF16_Msk (0x1UL << EXTI_FPR1_FPIF16_Pos) /*!< 0x00010000 */
2786#define EXTI_FPR1_FPIF16 EXTI_FPR1_FPIF16_Msk /*!< Falling Pending Interrupt Flag on line 16 */
2787#define EXTI_FPR1_FPIF17_Pos (17U)
2788#define EXTI_FPR1_FPIF17_Msk (0x1UL << EXTI_FPR1_FPIF17_Pos) /*!< 0x00020000 */
2789#define EXTI_FPR1_FPIF17 EXTI_FPR1_FPIF17_Msk /*!< Falling Pending Interrupt Flag on line 17 */
2790#define EXTI_FPR1_FPIF18_Pos (18U)
2791#define EXTI_FPR1_FPIF18_Msk (0x1UL << EXTI_FPR1_FPIF18_Pos) /*!< 0x00040000 */
2792#define EXTI_FPR1_FPIF18 EXTI_FPR1_FPIF18_Msk /*!< Falling Pending Interrupt Flag on line 18 */
2793
2794/***************** Bit definition for EXTI_EXTICR1 register **************/
2795#define EXTI_EXTICR1_EXTI0_Pos (0U)
2796#define EXTI_EXTICR1_EXTI0_Msk (0x7UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */
2797#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
2798#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */
2799#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */
2800#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */
2801#define EXTI_EXTICR1_EXTI1_Pos (8U)
2802#define EXTI_EXTICR1_EXTI1_Msk (0x7UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000700 */
2803#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
2804#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */
2805#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */
2806#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */
2807#define EXTI_EXTICR1_EXTI2_Pos (16U)
2808#define EXTI_EXTICR1_EXTI2_Msk (0x7UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00070000 */
2809#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
2810#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */
2811#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */
2812#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */
2813#define EXTI_EXTICR1_EXTI3_Pos (24U)
2814#define EXTI_EXTICR1_EXTI3_Msk (0x7UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x07000000 */
2815#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
2816#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */
2817#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */
2818#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */
2819
2820/***************** Bit definition for EXTI_EXTICR2 register **************/
2821#define EXTI_EXTICR2_EXTI4_Pos (0U)
2822#define EXTI_EXTICR2_EXTI4_Msk (0x7UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */
2823#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
2824#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */
2825#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */
2826#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */
2827#define EXTI_EXTICR2_EXTI5_Pos (8U)
2828#define EXTI_EXTICR2_EXTI5_Msk (0x7UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000700 */
2829#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
2830#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */
2831#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */
2832#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */
2833#define EXTI_EXTICR2_EXTI6_Pos (16U)
2834#define EXTI_EXTICR2_EXTI6_Msk (0x7UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00070000 */
2835#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
2836#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */
2837#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */
2838#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */
2839#define EXTI_EXTICR2_EXTI7_Pos (24U)
2840#define EXTI_EXTICR2_EXTI7_Msk (0x7UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x07000000 */
2841#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
2842#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */
2843#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */
2844#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */
2845
2846/***************** Bit definition for EXTI_EXTICR3 register **************/
2847#define EXTI_EXTICR3_EXTI8_Pos (0U)
2848#define EXTI_EXTICR3_EXTI8_Msk (0x7UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */
2849#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
2850#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */
2851#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */
2852#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */
2853#define EXTI_EXTICR3_EXTI9_Pos (8U)
2854#define EXTI_EXTICR3_EXTI9_Msk (0x7UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000700 */
2855#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
2856#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */
2857#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */
2858#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */
2859#define EXTI_EXTICR3_EXTI10_Pos (16U)
2860#define EXTI_EXTICR3_EXTI10_Msk (0x7UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00070000 */
2861#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
2862#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */
2863#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */
2864#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */
2865#define EXTI_EXTICR3_EXTI11_Pos (24U)
2866#define EXTI_EXTICR3_EXTI11_Msk (0x7UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x07000000 */
2867#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
2868#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */
2869#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */
2870#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */
2871
2872/***************** Bit definition for EXTI_EXTICR4 register **************/
2873#define EXTI_EXTICR4_EXTI12_Pos (0U)
2874#define EXTI_EXTICR4_EXTI12_Msk (0x7UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
2875#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
2876#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */
2877#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */
2878#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */
2879#define EXTI_EXTICR4_EXTI13_Pos (8U)
2880#define EXTI_EXTICR4_EXTI13_Msk (0x7UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000700 */
2881#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
2882#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */
2883#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */
2884#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */
2885#define EXTI_EXTICR4_EXTI14_Pos (16U)
2886#define EXTI_EXTICR4_EXTI14_Msk (0x7UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00070000 */
2887#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
2888#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */
2889#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */
2890#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */
2891#define EXTI_EXTICR4_EXTI15_Pos (24U)
2892#define EXTI_EXTICR4_EXTI15_Msk (0x7UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x07000000 */
2893#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
2894#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */
2895#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */
2896#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */
2897
2898/******************* Bit definition for EXTI_IMR1 register ******************/
2899#define EXTI_IMR1_IM0_Pos (0U)
2900#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
2901#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
2902#define EXTI_IMR1_IM1_Pos (1U)
2903#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
2904#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
2905#define EXTI_IMR1_IM2_Pos (2U)
2906#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
2907#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
2908#define EXTI_IMR1_IM3_Pos (3U)
2909#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
2910#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
2911#define EXTI_IMR1_IM4_Pos (4U)
2912#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
2913#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
2914#define EXTI_IMR1_IM5_Pos (5U)
2915#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
2916#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
2917#define EXTI_IMR1_IM6_Pos (6U)
2918#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
2919#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
2920#define EXTI_IMR1_IM7_Pos (7U)
2921#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
2922#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
2923#define EXTI_IMR1_IM8_Pos (8U)
2924#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
2925#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
2926#define EXTI_IMR1_IM9_Pos (9U)
2927#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
2928#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
2929#define EXTI_IMR1_IM10_Pos (10U)
2930#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
2931#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
2932#define EXTI_IMR1_IM11_Pos (11U)
2933#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
2934#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
2935#define EXTI_IMR1_IM12_Pos (12U)
2936#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
2937#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
2938#define EXTI_IMR1_IM13_Pos (13U)
2939#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
2940#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
2941#define EXTI_IMR1_IM14_Pos (14U)
2942#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
2943#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
2944#define EXTI_IMR1_IM15_Pos (15U)
2945#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
2946#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
2947#define EXTI_IMR1_IM16_Pos (16U)
2948#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
2949#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
2950#define EXTI_IMR1_IM17_Pos (17U)
2951#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
2952#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
2953#define EXTI_IMR1_IM18_Pos (18U)
2954#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
2955#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
2956#define EXTI_IMR1_IM19_Pos (19U)
2957#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
2958#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
2959#define EXTI_IMR1_IM20_Pos (20U)
2960#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
2961#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
2962#define EXTI_IMR1_IM21_Pos (21U)
2963#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
2964#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
2965#define EXTI_IMR1_IM22_Pos (22U)
2966#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
2967#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
2968#define EXTI_IMR1_IM23_Pos (23U)
2969#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
2970#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
2971#define EXTI_IMR1_IM24_Pos (24U)
2972#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
2973#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
2974#define EXTI_IMR1_IM25_Pos (25U)
2975#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
2976#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
2977#define EXTI_IMR1_IM26_Pos (26U)
2978#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
2979#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
2980#define EXTI_IMR1_IM27_Pos (27U)
2981#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
2982#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
2983#define EXTI_IMR1_IM28_Pos (28U)
2984#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
2985#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
2986#define EXTI_IMR1_IM29_Pos (29U)
2987#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
2988#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
2989#define EXTI_IMR1_IM30_Pos (30U)
2990#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
2991#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
2992#define EXTI_IMR1_IM31_Pos (31U)
2993#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
2994#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
2995#define EXTI_IMR1_IM_Pos (0U)
2996#define EXTI_IMR1_IM_Msk (0xFEAFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0xFEAFFFFF */
2997#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
2998
2999/******************* Bit definition for EXTI_IMR2 register ******************/
3000#define EXTI_IMR2_IM32_Pos (0U)
3001#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
3002#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
3003#define EXTI_IMR2_IM33_Pos (1U)
3004#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
3005#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
3006#define EXTI_IMR2_IM_Pos (0U)
3007#define EXTI_IMR2_IM_Msk (0x3UL << EXTI_IMR2_IM_Pos) /*!< 0x00000003 */
3008#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask All */
3009
3010/******************* Bit definition for EXTI_EMR1 register ******************/
3011#define EXTI_EMR1_EM0_Pos (0U)
3012#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
3013#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
3014#define EXTI_EMR1_EM1_Pos (1U)
3015#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
3016#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
3017#define EXTI_EMR1_EM2_Pos (2U)
3018#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
3019#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
3020#define EXTI_EMR1_EM3_Pos (3U)
3021#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
3022#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
3023#define EXTI_EMR1_EM4_Pos (4U)
3024#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
3025#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
3026#define EXTI_EMR1_EM5_Pos (5U)
3027#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
3028#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
3029#define EXTI_EMR1_EM6_Pos (6U)
3030#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
3031#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
3032#define EXTI_EMR1_EM7_Pos (7U)
3033#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
3034#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
3035#define EXTI_EMR1_EM8_Pos (8U)
3036#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
3037#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
3038#define EXTI_EMR1_EM9_Pos (9U)
3039#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
3040#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
3041#define EXTI_EMR1_EM10_Pos (10U)
3042#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
3043#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
3044#define EXTI_EMR1_EM11_Pos (11U)
3045#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
3046#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
3047#define EXTI_EMR1_EM12_Pos (12U)
3048#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
3049#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
3050#define EXTI_EMR1_EM13_Pos (13U)
3051#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
3052#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
3053#define EXTI_EMR1_EM14_Pos (14U)
3054#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
3055#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
3056#define EXTI_EMR1_EM15_Pos (15U)
3057#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
3058#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
3059#define EXTI_EMR1_EM16_Pos (16U)
3060#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
3061#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
3062#define EXTI_EMR1_EM17_Pos (17U)
3063#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
3064#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
3065#define EXTI_EMR1_EM18_Pos (18U)
3066#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
3067#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
3068#define EXTI_EMR1_EM19_Pos (19U)
3069#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
3070#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
3071#define EXTI_EMR1_EM21_Pos (21U)
3072#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
3073#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
3074#define EXTI_EMR1_EM23_Pos (23U)
3075#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
3076#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
3077#define EXTI_EMR1_EM25_Pos (25U)
3078#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
3079#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
3080#define EXTI_EMR1_EM26_Pos (26U)
3081#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
3082#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
3083#define EXTI_EMR1_EM27_Pos (27U)
3084#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
3085#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
3086#define EXTI_EMR1_EM28_Pos (28U)
3087#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
3088#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
3089#define EXTI_EMR1_EM29_Pos (29U)
3090#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
3091#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
3092#define EXTI_EMR1_EM30_Pos (30U)
3093#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
3094#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
3095#define EXTI_EMR1_EM31_Pos (31U)
3096#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
3097#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
3098
3099/******************* Bit definition for EXTI_EMR2 register ******************/
3100#define EXTI_EMR2_EM32_Pos (0U)
3101#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
3102#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32 */
3103#define EXTI_EMR2_EM33_Pos (1U)
3104#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
3105#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
3106
3107
3108/******************************************************************************/
3109/* */
3110/* FLASH */
3111/* */
3112/******************************************************************************/
3113#define GPIO_NRST_CONFIG_SUPPORT /*!< GPIO feature available only on specific devices: Configure NRST pin */
3114#define FLASH_SECURABLE_MEMORY_SUPPORT /*!< Flash feature available only on specific devices: allow to secure memory */
3115#define FLASH_PCROP_SUPPORT /*!< Flash feature available only on specific devices: proprietary code read protection areas selected by option */
3116
3117/******************* Bits definition for FLASH_ACR register *****************/
3118#define FLASH_ACR_LATENCY_Pos (0U)
3119#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
3120#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
3121#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
3122#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
3123#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
3124#define FLASH_ACR_PRFTEN_Pos (8U)
3125#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
3126#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
3127#define FLASH_ACR_ICEN_Pos (9U)
3128#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
3129#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
3130#define FLASH_ACR_ICRST_Pos (11U)
3131#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
3132#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
3133#define FLASH_ACR_PROGEMPTY_Pos (16U)
3134#define FLASH_ACR_PROGEMPTY_Msk (0x1UL << FLASH_ACR_PROGEMPTY_Pos) /*!< 0x00010000 */
3135#define FLASH_ACR_PROGEMPTY FLASH_ACR_PROGEMPTY_Msk
3136#define FLASH_ACR_DBG_SWEN_Pos (18U)
3137#define FLASH_ACR_DBG_SWEN_Msk (0x1UL << FLASH_ACR_DBG_SWEN_Pos) /*!< 0x00040000 */
3138#define FLASH_ACR_DBG_SWEN FLASH_ACR_DBG_SWEN_Msk
3139
3140/******************* Bits definition for FLASH_SR register ******************/
3141#define FLASH_SR_EOP_Pos (0U)
3142#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
3143#define FLASH_SR_EOP FLASH_SR_EOP_Msk
3144#define FLASH_SR_OPERR_Pos (1U)
3145#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
3146#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
3147#define FLASH_SR_PROGERR_Pos (3U)
3148#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
3149#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
3150#define FLASH_SR_WRPERR_Pos (4U)
3151#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
3152#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
3153#define FLASH_SR_PGAERR_Pos (5U)
3154#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
3155#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
3156#define FLASH_SR_SIZERR_Pos (6U)
3157#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
3158#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
3159#define FLASH_SR_PGSERR_Pos (7U)
3160#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
3161#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
3162#define FLASH_SR_MISERR_Pos (8U)
3163#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
3164#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
3165#define FLASH_SR_FASTERR_Pos (9U)
3166#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
3167#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
3168#define FLASH_SR_RDERR_Pos (14U)
3169#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
3170#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
3171#define FLASH_SR_OPTVERR_Pos (15U)
3172#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
3173#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
3174#define FLASH_SR_BSY1_Pos (16U)
3175#define FLASH_SR_BSY1_Msk (0x1UL << FLASH_SR_BSY1_Pos) /*!< 0x00010000 */
3176#define FLASH_SR_BSY1 FLASH_SR_BSY1_Msk
3177#define FLASH_SR_CFGBSY_Pos (18U)
3178#define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */
3179#define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk
3180
3181/******************* Bits definition for FLASH_CR register ******************/
3182#define FLASH_CR_PG_Pos (0U)
3183#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
3184#define FLASH_CR_PG FLASH_CR_PG_Msk
3185#define FLASH_CR_PER_Pos (1U)
3186#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */
3187#define FLASH_CR_PER FLASH_CR_PER_Msk
3188#define FLASH_CR_MER1_Pos (2U)
3189#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
3190#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
3191#define FLASH_CR_PNB_Pos (3U)
3192#define FLASH_CR_PNB_Msk (0x3FUL << FLASH_CR_PNB_Pos) /*!< 0x000001F8 */
3193#define FLASH_CR_PNB FLASH_CR_PNB_Msk
3194#define FLASH_CR_STRT_Pos (16U)
3195#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
3196#define FLASH_CR_STRT FLASH_CR_STRT_Msk
3197#define FLASH_CR_OPTSTRT_Pos (17U)
3198#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
3199#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
3200#define FLASH_CR_FSTPG_Pos (18U)
3201#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
3202#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
3203#define FLASH_CR_EOPIE_Pos (24U)
3204#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
3205#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
3206#define FLASH_CR_ERRIE_Pos (25U)
3207#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
3208#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
3209#define FLASH_CR_RDERRIE_Pos (26U)
3210#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
3211#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
3212#define FLASH_CR_OBL_LAUNCH_Pos (27U)
3213#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
3214#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
3215#define FLASH_CR_SEC_PROT_Pos (28U)
3216#define FLASH_CR_SEC_PROT_Msk (0x1UL << FLASH_CR_SEC_PROT_Pos) /*!< 0x10000000 */
3217#define FLASH_CR_SEC_PROT FLASH_CR_SEC_PROT_Msk
3218#define FLASH_CR_OPTLOCK_Pos (30U)
3219#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
3220#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
3221#define FLASH_CR_LOCK_Pos (31U)
3222#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
3223#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
3224
3225/******************* Bits definition for FLASH_ECCR register ****************/
3226#define FLASH_ECCR_ADDR_ECC_Pos (0U)
3227#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x00003FFF */
3228#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
3229#define FLASH_ECCR_SYSF_ECC_Pos (20U)
3230#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
3231#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
3232#define FLASH_ECCR_ECCCIE_Pos (24U)
3233#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */
3234#define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk
3235#define FLASH_ECCR_ECCC_Pos (30U)
3236#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
3237#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
3238#define FLASH_ECCR_ECCD_Pos (31U)
3239#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
3240#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
3241
3242/******************* Bits definition for FLASH_OPTR register ****************/
3243#define FLASH_OPTR_RDP_Pos (0U)
3244#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
3245#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
3246#define FLASH_OPTR_BOR_EN_Pos (8U)
3247#define FLASH_OPTR_BOR_EN_Msk (0x1UL << FLASH_OPTR_BOR_EN_Pos) /*!< 0x00000100 */
3248#define FLASH_OPTR_BOR_EN FLASH_OPTR_BOR_EN_Msk
3249#define FLASH_OPTR_BORF_LEV_Pos (9U)
3250#define FLASH_OPTR_BORF_LEV_Msk (0x3UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000600 */
3251#define FLASH_OPTR_BORF_LEV FLASH_OPTR_BORF_LEV_Msk
3252#define FLASH_OPTR_BORF_LEV_0 (0x1UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000200 */
3253#define FLASH_OPTR_BORF_LEV_1 (0x2UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000400 */
3254#define FLASH_OPTR_BORR_LEV_Pos (11U)
3255#define FLASH_OPTR_BORR_LEV_Msk (0x3UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00001800 */
3256#define FLASH_OPTR_BORR_LEV FLASH_OPTR_BORR_LEV_Msk
3257#define FLASH_OPTR_BORR_LEV_0 (0x1UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000800 */
3258#define FLASH_OPTR_BORR_LEV_1 (0x2UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00001000 */
3259#define FLASH_OPTR_nRST_STOP_Pos (13U)
3260#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */
3261#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
3262#define FLASH_OPTR_nRST_STDBY_Pos (14U)
3263#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */
3264#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
3265#define FLASH_OPTR_nRST_SHDW_Pos (15U)
3266#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00008000 */
3267#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
3268#define FLASH_OPTR_IWDG_SW_Pos (16U)
3269#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
3270#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
3271#define FLASH_OPTR_IWDG_STOP_Pos (17U)
3272#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
3273#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
3274#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
3275#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
3276#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
3277#define FLASH_OPTR_WWDG_SW_Pos (19U)
3278#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
3279#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
3280#define FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U)
3281#define FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */
3282#define FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk
3283#define FLASH_OPTR_nBOOT_SEL_Pos (24U)
3284#define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */
3285#define FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk
3286#define FLASH_OPTR_nBOOT1_Pos (25U)
3287#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */
3288#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
3289#define FLASH_OPTR_nBOOT0_Pos (26U)
3290#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */
3291#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
3292#define FLASH_OPTR_NRST_MODE_Pos (27U)
3293#define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x18000000 */
3294#define FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk
3295#define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x08000000 */
3296#define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x10000000 */
3297#define FLASH_OPTR_IRHEN_Pos (29U)
3298#define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos) /*!< 0x20000000 */
3299#define FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk
3300
3301/****************** Bits definition for FLASH_PCROP1ASR register ************/
3302#define FLASH_PCROP1ASR_PCROP1A_STRT_Pos (0U)
3303#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0xFFUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x000000FF */
3304#define FLASH_PCROP1ASR_PCROP1A_STRT FLASH_PCROP1ASR_PCROP1A_STRT_Msk
3305
3306/****************** Bits definition for FLASH_PCROP1AER register ************/
3307#define FLASH_PCROP1AER_PCROP1A_END_Pos (0U)
3308#define FLASH_PCROP1AER_PCROP1A_END_Msk (0xFFUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x000000FF */
3309#define FLASH_PCROP1AER_PCROP1A_END FLASH_PCROP1AER_PCROP1A_END_Msk
3310#define FLASH_PCROP1AER_PCROP_RDP_Pos (31U)
3311#define FLASH_PCROP1AER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos) /*!< 0x80000000 */
3312#define FLASH_PCROP1AER_PCROP_RDP FLASH_PCROP1AER_PCROP_RDP_Msk
3313
3314/****************** Bits definition for FLASH_WRP1AR register ***************/
3315#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
3316#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000003F */
3317#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
3318#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
3319#define FLASH_WRP1AR_WRP1A_END_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x003F0000 */
3320#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
3321
3322/****************** Bits definition for FLASH_WRP1BR register ***************/
3323#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
3324#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000003F */
3325#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
3326#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
3327#define FLASH_WRP1BR_WRP1B_END_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x003F0000 */
3328#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
3329
3330/****************** Bits definition for FLASH_PCROP1BSR register ************/
3331#define FLASH_PCROP1BSR_PCROP1B_STRT_Pos (0U)
3332#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0xFFUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x000000FF */
3333#define FLASH_PCROP1BSR_PCROP1B_STRT FLASH_PCROP1BSR_PCROP1B_STRT_Msk
3334
3335/****************** Bits definition for FLASH_PCROP1BER register ************/
3336#define FLASH_PCROP1BER_PCROP1B_END_Pos (0U)
3337#define FLASH_PCROP1BER_PCROP1B_END_Msk (0xFFUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x000000FF */
3338#define FLASH_PCROP1BER_PCROP1B_END FLASH_PCROP1BER_PCROP1B_END_Msk
3339
3340/****************** Bits definition for FLASH_SECR register *****************/
3341#define FLASH_SECR_SEC_SIZE_Pos (0U)
3342#define FLASH_SECR_SEC_SIZE_Msk (0x7FUL << FLASH_SECR_SEC_SIZE_Pos) /*!< 0x0000007F */
3343#define FLASH_SECR_SEC_SIZE FLASH_SECR_SEC_SIZE_Msk
3344#define FLASH_SECR_BOOT_LOCK_Pos (16U)
3345#define FLASH_SECR_BOOT_LOCK_Msk (0x1UL << FLASH_SECR_BOOT_LOCK_Pos) /*!< 0x00010000 */
3346#define FLASH_SECR_BOOT_LOCK FLASH_SECR_BOOT_LOCK_Msk
3347
3348
3349/******************************************************************************/
3350/* */
3351/* General Purpose I/O */
3352/* */
3353/******************************************************************************/
3354/****************** Bits definition for GPIO_MODER register *****************/
3355#define GPIO_MODER_MODE0_Pos (0U)
3356#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
3357#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
3358#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
3359#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
3360#define GPIO_MODER_MODE1_Pos (2U)
3361#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
3362#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
3363#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
3364#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
3365#define GPIO_MODER_MODE2_Pos (4U)
3366#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
3367#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
3368#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
3369#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
3370#define GPIO_MODER_MODE3_Pos (6U)
3371#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
3372#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
3373#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
3374#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
3375#define GPIO_MODER_MODE4_Pos (8U)
3376#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
3377#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
3378#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
3379#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
3380#define GPIO_MODER_MODE5_Pos (10U)
3381#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
3382#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
3383#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
3384#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
3385#define GPIO_MODER_MODE6_Pos (12U)
3386#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
3387#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
3388#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
3389#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
3390#define GPIO_MODER_MODE7_Pos (14U)
3391#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
3392#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
3393#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
3394#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
3395#define GPIO_MODER_MODE8_Pos (16U)
3396#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
3397#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
3398#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
3399#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
3400#define GPIO_MODER_MODE9_Pos (18U)
3401#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
3402#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
3403#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
3404#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
3405#define GPIO_MODER_MODE10_Pos (20U)
3406#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
3407#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
3408#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
3409#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
3410#define GPIO_MODER_MODE11_Pos (22U)
3411#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
3412#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
3413#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
3414#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
3415#define GPIO_MODER_MODE12_Pos (24U)
3416#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
3417#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
3418#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
3419#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
3420#define GPIO_MODER_MODE13_Pos (26U)
3421#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
3422#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
3423#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
3424#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
3425#define GPIO_MODER_MODE14_Pos (28U)
3426#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
3427#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
3428#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
3429#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
3430#define GPIO_MODER_MODE15_Pos (30U)
3431#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
3432#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
3433#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
3434#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
3435
3436/****************** Bits definition for GPIO_OTYPER register ****************/
3437#define GPIO_OTYPER_OT0_Pos (0U)
3438#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
3439#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
3440#define GPIO_OTYPER_OT1_Pos (1U)
3441#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
3442#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
3443#define GPIO_OTYPER_OT2_Pos (2U)
3444#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
3445#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
3446#define GPIO_OTYPER_OT3_Pos (3U)
3447#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
3448#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
3449#define GPIO_OTYPER_OT4_Pos (4U)
3450#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
3451#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
3452#define GPIO_OTYPER_OT5_Pos (5U)
3453#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
3454#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
3455#define GPIO_OTYPER_OT6_Pos (6U)
3456#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
3457#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
3458#define GPIO_OTYPER_OT7_Pos (7U)
3459#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
3460#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
3461#define GPIO_OTYPER_OT8_Pos (8U)
3462#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
3463#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
3464#define GPIO_OTYPER_OT9_Pos (9U)
3465#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
3466#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
3467#define GPIO_OTYPER_OT10_Pos (10U)
3468#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
3469#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
3470#define GPIO_OTYPER_OT11_Pos (11U)
3471#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
3472#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
3473#define GPIO_OTYPER_OT12_Pos (12U)
3474#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
3475#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
3476#define GPIO_OTYPER_OT13_Pos (13U)
3477#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
3478#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
3479#define GPIO_OTYPER_OT14_Pos (14U)
3480#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
3481#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
3482#define GPIO_OTYPER_OT15_Pos (15U)
3483#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
3484#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
3485
3486/****************** Bits definition for GPIO_OSPEEDR register ***************/
3487#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
3488#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
3489#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
3490#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
3491#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
3492#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
3493#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
3494#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
3495#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
3496#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
3497#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
3498#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
3499#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
3500#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
3501#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
3502#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
3503#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
3504#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
3505#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
3506#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
3507#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
3508#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
3509#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
3510#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
3511#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
3512#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
3513#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
3514#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
3515#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
3516#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
3517#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
3518#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
3519#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
3520#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
3521#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
3522#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
3523#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
3524#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
3525#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
3526#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
3527#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
3528#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
3529#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
3530#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
3531#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
3532#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
3533#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
3534#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
3535#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
3536#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
3537#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
3538#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
3539#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
3540#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
3541#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
3542#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
3543#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
3544#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
3545#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
3546#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
3547#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
3548#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
3549#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
3550#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
3551#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
3552#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
3553#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
3554#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
3555#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
3556#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
3557#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
3558#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
3559#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
3560#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
3561#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
3562#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
3563#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
3564#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
3565#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
3566#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
3567
3568/****************** Bits definition for GPIO_PUPDR register *****************/
3569#define GPIO_PUPDR_PUPD0_Pos (0U)
3570#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
3571#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
3572#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
3573#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
3574#define GPIO_PUPDR_PUPD1_Pos (2U)
3575#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
3576#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
3577#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
3578#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
3579#define GPIO_PUPDR_PUPD2_Pos (4U)
3580#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
3581#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
3582#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
3583#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
3584#define GPIO_PUPDR_PUPD3_Pos (6U)
3585#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
3586#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
3587#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
3588#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
3589#define GPIO_PUPDR_PUPD4_Pos (8U)
3590#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
3591#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
3592#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
3593#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
3594#define GPIO_PUPDR_PUPD5_Pos (10U)
3595#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
3596#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
3597#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
3598#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
3599#define GPIO_PUPDR_PUPD6_Pos (12U)
3600#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
3601#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
3602#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
3603#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
3604#define GPIO_PUPDR_PUPD7_Pos (14U)
3605#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
3606#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
3607#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
3608#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
3609#define GPIO_PUPDR_PUPD8_Pos (16U)
3610#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
3611#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
3612#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
3613#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
3614#define GPIO_PUPDR_PUPD9_Pos (18U)
3615#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
3616#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
3617#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
3618#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
3619#define GPIO_PUPDR_PUPD10_Pos (20U)
3620#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
3621#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
3622#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
3623#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
3624#define GPIO_PUPDR_PUPD11_Pos (22U)
3625#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
3626#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
3627#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
3628#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
3629#define GPIO_PUPDR_PUPD12_Pos (24U)
3630#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
3631#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
3632#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
3633#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
3634#define GPIO_PUPDR_PUPD13_Pos (26U)
3635#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
3636#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
3637#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
3638#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
3639#define GPIO_PUPDR_PUPD14_Pos (28U)
3640#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
3641#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
3642#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
3643#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
3644#define GPIO_PUPDR_PUPD15_Pos (30U)
3645#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
3646#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
3647#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
3648#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
3649
3650/****************** Bits definition for GPIO_IDR register *******************/
3651#define GPIO_IDR_ID0_Pos (0U)
3652#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
3653#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
3654#define GPIO_IDR_ID1_Pos (1U)
3655#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
3656#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
3657#define GPIO_IDR_ID2_Pos (2U)
3658#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
3659#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
3660#define GPIO_IDR_ID3_Pos (3U)
3661#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
3662#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
3663#define GPIO_IDR_ID4_Pos (4U)
3664#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
3665#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
3666#define GPIO_IDR_ID5_Pos (5U)
3667#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
3668#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
3669#define GPIO_IDR_ID6_Pos (6U)
3670#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
3671#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
3672#define GPIO_IDR_ID7_Pos (7U)
3673#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
3674#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
3675#define GPIO_IDR_ID8_Pos (8U)
3676#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
3677#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
3678#define GPIO_IDR_ID9_Pos (9U)
3679#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
3680#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
3681#define GPIO_IDR_ID10_Pos (10U)
3682#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
3683#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
3684#define GPIO_IDR_ID11_Pos (11U)
3685#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
3686#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
3687#define GPIO_IDR_ID12_Pos (12U)
3688#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
3689#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
3690#define GPIO_IDR_ID13_Pos (13U)
3691#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
3692#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
3693#define GPIO_IDR_ID14_Pos (14U)
3694#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
3695#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
3696#define GPIO_IDR_ID15_Pos (15U)
3697#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
3698#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
3699
3700/****************** Bits definition for GPIO_ODR register *******************/
3701#define GPIO_ODR_OD0_Pos (0U)
3702#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
3703#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
3704#define GPIO_ODR_OD1_Pos (1U)
3705#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
3706#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
3707#define GPIO_ODR_OD2_Pos (2U)
3708#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
3709#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
3710#define GPIO_ODR_OD3_Pos (3U)
3711#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
3712#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
3713#define GPIO_ODR_OD4_Pos (4U)
3714#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
3715#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
3716#define GPIO_ODR_OD5_Pos (5U)
3717#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
3718#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
3719#define GPIO_ODR_OD6_Pos (6U)
3720#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
3721#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
3722#define GPIO_ODR_OD7_Pos (7U)
3723#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
3724#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
3725#define GPIO_ODR_OD8_Pos (8U)
3726#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
3727#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
3728#define GPIO_ODR_OD9_Pos (9U)
3729#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
3730#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
3731#define GPIO_ODR_OD10_Pos (10U)
3732#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
3733#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
3734#define GPIO_ODR_OD11_Pos (11U)
3735#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
3736#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
3737#define GPIO_ODR_OD12_Pos (12U)
3738#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
3739#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
3740#define GPIO_ODR_OD13_Pos (13U)
3741#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
3742#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
3743#define GPIO_ODR_OD14_Pos (14U)
3744#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
3745#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
3746#define GPIO_ODR_OD15_Pos (15U)
3747#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
3748#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
3749
3750/****************** Bits definition for GPIO_BSRR register ******************/
3751#define GPIO_BSRR_BS0_Pos (0U)
3752#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
3753#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
3754#define GPIO_BSRR_BS1_Pos (1U)
3755#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
3756#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
3757#define GPIO_BSRR_BS2_Pos (2U)
3758#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
3759#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
3760#define GPIO_BSRR_BS3_Pos (3U)
3761#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
3762#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
3763#define GPIO_BSRR_BS4_Pos (4U)
3764#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
3765#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
3766#define GPIO_BSRR_BS5_Pos (5U)
3767#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
3768#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
3769#define GPIO_BSRR_BS6_Pos (6U)
3770#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
3771#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
3772#define GPIO_BSRR_BS7_Pos (7U)
3773#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
3774#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
3775#define GPIO_BSRR_BS8_Pos (8U)
3776#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
3777#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
3778#define GPIO_BSRR_BS9_Pos (9U)
3779#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
3780#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
3781#define GPIO_BSRR_BS10_Pos (10U)
3782#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
3783#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
3784#define GPIO_BSRR_BS11_Pos (11U)
3785#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
3786#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
3787#define GPIO_BSRR_BS12_Pos (12U)
3788#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
3789#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
3790#define GPIO_BSRR_BS13_Pos (13U)
3791#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
3792#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
3793#define GPIO_BSRR_BS14_Pos (14U)
3794#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
3795#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
3796#define GPIO_BSRR_BS15_Pos (15U)
3797#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
3798#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
3799#define GPIO_BSRR_BR0_Pos (16U)
3800#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
3801#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
3802#define GPIO_BSRR_BR1_Pos (17U)
3803#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
3804#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
3805#define GPIO_BSRR_BR2_Pos (18U)
3806#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
3807#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
3808#define GPIO_BSRR_BR3_Pos (19U)
3809#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
3810#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
3811#define GPIO_BSRR_BR4_Pos (20U)
3812#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
3813#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
3814#define GPIO_BSRR_BR5_Pos (21U)
3815#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
3816#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
3817#define GPIO_BSRR_BR6_Pos (22U)
3818#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
3819#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
3820#define GPIO_BSRR_BR7_Pos (23U)
3821#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
3822#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
3823#define GPIO_BSRR_BR8_Pos (24U)
3824#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
3825#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
3826#define GPIO_BSRR_BR9_Pos (25U)
3827#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
3828#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
3829#define GPIO_BSRR_BR10_Pos (26U)
3830#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
3831#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
3832#define GPIO_BSRR_BR11_Pos (27U)
3833#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
3834#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
3835#define GPIO_BSRR_BR12_Pos (28U)
3836#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
3837#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
3838#define GPIO_BSRR_BR13_Pos (29U)
3839#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
3840#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
3841#define GPIO_BSRR_BR14_Pos (30U)
3842#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
3843#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
3844#define GPIO_BSRR_BR15_Pos (31U)
3845#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
3846#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
3847
3848/****************** Bit definition for GPIO_LCKR register *********************/
3849#define GPIO_LCKR_LCK0_Pos (0U)
3850#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
3851#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
3852#define GPIO_LCKR_LCK1_Pos (1U)
3853#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
3854#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
3855#define GPIO_LCKR_LCK2_Pos (2U)
3856#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
3857#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
3858#define GPIO_LCKR_LCK3_Pos (3U)
3859#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
3860#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
3861#define GPIO_LCKR_LCK4_Pos (4U)
3862#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
3863#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
3864#define GPIO_LCKR_LCK5_Pos (5U)
3865#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
3866#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
3867#define GPIO_LCKR_LCK6_Pos (6U)
3868#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
3869#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
3870#define GPIO_LCKR_LCK7_Pos (7U)
3871#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
3872#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
3873#define GPIO_LCKR_LCK8_Pos (8U)
3874#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
3875#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
3876#define GPIO_LCKR_LCK9_Pos (9U)
3877#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
3878#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
3879#define GPIO_LCKR_LCK10_Pos (10U)
3880#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
3881#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
3882#define GPIO_LCKR_LCK11_Pos (11U)
3883#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
3884#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
3885#define GPIO_LCKR_LCK12_Pos (12U)
3886#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
3887#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
3888#define GPIO_LCKR_LCK13_Pos (13U)
3889#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
3890#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
3891#define GPIO_LCKR_LCK14_Pos (14U)
3892#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
3893#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
3894#define GPIO_LCKR_LCK15_Pos (15U)
3895#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
3896#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
3897#define GPIO_LCKR_LCKK_Pos (16U)
3898#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
3899#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
3900
3901/****************** Bit definition for GPIO_AFRL register *********************/
3902#define GPIO_AFRL_AFSEL0_Pos (0U)
3903#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
3904#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
3905#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
3906#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
3907#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
3908#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
3909#define GPIO_AFRL_AFSEL1_Pos (4U)
3910#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
3911#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
3912#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
3913#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
3914#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
3915#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
3916#define GPIO_AFRL_AFSEL2_Pos (8U)
3917#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
3918#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
3919#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
3920#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
3921#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
3922#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
3923#define GPIO_AFRL_AFSEL3_Pos (12U)
3924#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
3925#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
3926#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
3927#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
3928#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
3929#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
3930#define GPIO_AFRL_AFSEL4_Pos (16U)
3931#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
3932#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
3933#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
3934#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
3935#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
3936#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
3937#define GPIO_AFRL_AFSEL5_Pos (20U)
3938#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
3939#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
3940#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
3941#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
3942#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
3943#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
3944#define GPIO_AFRL_AFSEL6_Pos (24U)
3945#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
3946#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
3947#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
3948#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
3949#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
3950#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
3951#define GPIO_AFRL_AFSEL7_Pos (28U)
3952#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
3953#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
3954#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
3955#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
3956#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
3957#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
3958
3959/****************** Bit definition for GPIO_AFRH register *********************/
3960#define GPIO_AFRH_AFSEL8_Pos (0U)
3961#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
3962#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
3963#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
3964#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
3965#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
3966#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
3967#define GPIO_AFRH_AFSEL9_Pos (4U)
3968#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
3969#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
3970#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
3971#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
3972#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
3973#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
3974#define GPIO_AFRH_AFSEL10_Pos (8U)
3975#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
3976#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
3977#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
3978#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
3979#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
3980#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
3981#define GPIO_AFRH_AFSEL11_Pos (12U)
3982#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
3983#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
3984#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
3985#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
3986#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
3987#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
3988#define GPIO_AFRH_AFSEL12_Pos (16U)
3989#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
3990#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
3991#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
3992#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
3993#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
3994#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
3995#define GPIO_AFRH_AFSEL13_Pos (20U)
3996#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
3997#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
3998#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
3999#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
4000#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
4001#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
4002#define GPIO_AFRH_AFSEL14_Pos (24U)
4003#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
4004#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
4005#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
4006#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
4007#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
4008#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
4009#define GPIO_AFRH_AFSEL15_Pos (28U)
4010#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
4011#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
4012#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
4013#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
4014#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
4015#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
4016
4017/****************** Bits definition for GPIO_BRR register ******************/
4018#define GPIO_BRR_BR0_Pos (0U)
4019#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
4020#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
4021#define GPIO_BRR_BR1_Pos (1U)
4022#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
4023#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
4024#define GPIO_BRR_BR2_Pos (2U)
4025#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
4026#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
4027#define GPIO_BRR_BR3_Pos (3U)
4028#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
4029#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
4030#define GPIO_BRR_BR4_Pos (4U)
4031#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
4032#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
4033#define GPIO_BRR_BR5_Pos (5U)
4034#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
4035#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
4036#define GPIO_BRR_BR6_Pos (6U)
4037#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
4038#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
4039#define GPIO_BRR_BR7_Pos (7U)
4040#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
4041#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
4042#define GPIO_BRR_BR8_Pos (8U)
4043#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
4044#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
4045#define GPIO_BRR_BR9_Pos (9U)
4046#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
4047#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
4048#define GPIO_BRR_BR10_Pos (10U)
4049#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
4050#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
4051#define GPIO_BRR_BR11_Pos (11U)
4052#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
4053#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
4054#define GPIO_BRR_BR12_Pos (12U)
4055#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
4056#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
4057#define GPIO_BRR_BR13_Pos (13U)
4058#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
4059#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
4060#define GPIO_BRR_BR14_Pos (14U)
4061#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
4062#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
4063#define GPIO_BRR_BR15_Pos (15U)
4064#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
4065#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
4066
4067
4068/******************************************************************************/
4069/* */
4070/* Inter-integrated Circuit Interface (I2C) */
4071/* */
4072/******************************************************************************/
4073/******************* Bit definition for I2C_CR1 register *******************/
4074#define I2C_CR1_PE_Pos (0U)
4075#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
4076#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
4077#define I2C_CR1_TXIE_Pos (1U)
4078#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
4079#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
4080#define I2C_CR1_RXIE_Pos (2U)
4081#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
4082#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
4083#define I2C_CR1_ADDRIE_Pos (3U)
4084#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
4085#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
4086#define I2C_CR1_NACKIE_Pos (4U)
4087#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
4088#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
4089#define I2C_CR1_STOPIE_Pos (5U)
4090#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
4091#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
4092#define I2C_CR1_TCIE_Pos (6U)
4093#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
4094#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
4095#define I2C_CR1_ERRIE_Pos (7U)
4096#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
4097#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
4098#define I2C_CR1_DNF_Pos (8U)
4099#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
4100#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
4101#define I2C_CR1_ANFOFF_Pos (12U)
4102#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
4103#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
4104#define I2C_CR1_SWRST_Pos (13U)
4105#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
4106#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
4107#define I2C_CR1_TXDMAEN_Pos (14U)
4108#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
4109#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
4110#define I2C_CR1_RXDMAEN_Pos (15U)
4111#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
4112#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
4113#define I2C_CR1_SBC_Pos (16U)
4114#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
4115#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
4116#define I2C_CR1_NOSTRETCH_Pos (17U)
4117#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
4118#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
4119#define I2C_CR1_WUPEN_Pos (18U)
4120#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
4121#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
4122#define I2C_CR1_GCEN_Pos (19U)
4123#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
4124#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
4125#define I2C_CR1_SMBHEN_Pos (20U)
4126#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
4127#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
4128#define I2C_CR1_SMBDEN_Pos (21U)
4129#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
4130#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
4131#define I2C_CR1_ALERTEN_Pos (22U)
4132#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
4133#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
4134#define I2C_CR1_PECEN_Pos (23U)
4135#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
4136#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
4137
4138/****************** Bit definition for I2C_CR2 register ********************/
4139#define I2C_CR2_SADD_Pos (0U)
4140#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
4141#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
4142#define I2C_CR2_RD_WRN_Pos (10U)
4143#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
4144#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
4145#define I2C_CR2_ADD10_Pos (11U)
4146#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
4147#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
4148#define I2C_CR2_HEAD10R_Pos (12U)
4149#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
4150#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
4151#define I2C_CR2_START_Pos (13U)
4152#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
4153#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
4154#define I2C_CR2_STOP_Pos (14U)
4155#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
4156#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
4157#define I2C_CR2_NACK_Pos (15U)
4158#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
4159#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
4160#define I2C_CR2_NBYTES_Pos (16U)
4161#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
4162#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
4163#define I2C_CR2_RELOAD_Pos (24U)
4164#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
4165#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
4166#define I2C_CR2_AUTOEND_Pos (25U)
4167#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
4168#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
4169#define I2C_CR2_PECBYTE_Pos (26U)
4170#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
4171#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
4172
4173/******************* Bit definition for I2C_OAR1 register ******************/
4174#define I2C_OAR1_OA1_Pos (0U)
4175#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
4176#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
4177#define I2C_OAR1_OA1MODE_Pos (10U)
4178#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
4179#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
4180#define I2C_OAR1_OA1EN_Pos (15U)
4181#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
4182#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
4183
4184/******************* Bit definition for I2C_OAR2 register ******************/
4185#define I2C_OAR2_OA2_Pos (1U)
4186#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
4187#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
4188#define I2C_OAR2_OA2MSK_Pos (8U)
4189#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
4190#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
4191#define I2C_OAR2_OA2NOMASK (0U) /*!< No mask */
4192#define I2C_OAR2_OA2MASK01_Pos (8U)
4193#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
4194#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
4195#define I2C_OAR2_OA2MASK02_Pos (9U)
4196#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
4197#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
4198#define I2C_OAR2_OA2MASK03_Pos (8U)
4199#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
4200#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
4201#define I2C_OAR2_OA2MASK04_Pos (10U)
4202#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
4203#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
4204#define I2C_OAR2_OA2MASK05_Pos (8U)
4205#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
4206#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
4207#define I2C_OAR2_OA2MASK06_Pos (9U)
4208#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
4209#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
4210#define I2C_OAR2_OA2MASK07_Pos (8U)
4211#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
4212#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
4213#define I2C_OAR2_OA2EN_Pos (15U)
4214#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
4215#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
4216
4217/******************* Bit definition for I2C_TIMINGR register *******************/
4218#define I2C_TIMINGR_SCLL_Pos (0U)
4219#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
4220#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
4221#define I2C_TIMINGR_SCLH_Pos (8U)
4222#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
4223#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
4224#define I2C_TIMINGR_SDADEL_Pos (16U)
4225#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
4226#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
4227#define I2C_TIMINGR_SCLDEL_Pos (20U)
4228#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
4229#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
4230#define I2C_TIMINGR_PRESC_Pos (28U)
4231#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
4232#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
4233
4234/******************* Bit definition for I2C_TIMEOUTR register *******************/
4235#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
4236#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
4237#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
4238#define I2C_TIMEOUTR_TIDLE_Pos (12U)
4239#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
4240#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
4241#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
4242#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
4243#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
4244#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
4245#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
4246#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
4247#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
4248#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
4249#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
4250
4251/****************** Bit definition for I2C_ISR register *********************/
4252#define I2C_ISR_TXE_Pos (0U)
4253#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
4254#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
4255#define I2C_ISR_TXIS_Pos (1U)
4256#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
4257#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
4258#define I2C_ISR_RXNE_Pos (2U)
4259#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
4260#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
4261#define I2C_ISR_ADDR_Pos (3U)
4262#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
4263#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
4264#define I2C_ISR_NACKF_Pos (4U)
4265#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
4266#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
4267#define I2C_ISR_STOPF_Pos (5U)
4268#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
4269#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
4270#define I2C_ISR_TC_Pos (6U)
4271#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
4272#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
4273#define I2C_ISR_TCR_Pos (7U)
4274#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
4275#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
4276#define I2C_ISR_BERR_Pos (8U)
4277#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
4278#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
4279#define I2C_ISR_ARLO_Pos (9U)
4280#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
4281#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
4282#define I2C_ISR_OVR_Pos (10U)
4283#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
4284#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
4285#define I2C_ISR_PECERR_Pos (11U)
4286#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
4287#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
4288#define I2C_ISR_TIMEOUT_Pos (12U)
4289#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
4290#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
4291#define I2C_ISR_ALERT_Pos (13U)
4292#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
4293#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
4294#define I2C_ISR_BUSY_Pos (15U)
4295#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
4296#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
4297#define I2C_ISR_DIR_Pos (16U)
4298#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
4299#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
4300#define I2C_ISR_ADDCODE_Pos (17U)
4301#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
4302#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
4303
4304/****************** Bit definition for I2C_ICR register *********************/
4305#define I2C_ICR_ADDRCF_Pos (3U)
4306#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
4307#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
4308#define I2C_ICR_NACKCF_Pos (4U)
4309#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
4310#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
4311#define I2C_ICR_STOPCF_Pos (5U)
4312#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
4313#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
4314#define I2C_ICR_BERRCF_Pos (8U)
4315#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
4316#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
4317#define I2C_ICR_ARLOCF_Pos (9U)
4318#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
4319#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
4320#define I2C_ICR_OVRCF_Pos (10U)
4321#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
4322#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
4323#define I2C_ICR_PECCF_Pos (11U)
4324#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
4325#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
4326#define I2C_ICR_TIMOUTCF_Pos (12U)
4327#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
4328#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
4329#define I2C_ICR_ALERTCF_Pos (13U)
4330#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
4331#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
4332
4333/****************** Bit definition for I2C_PECR register *********************/
4334#define I2C_PECR_PEC_Pos (0U)
4335#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
4336#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
4337
4338/****************** Bit definition for I2C_RXDR register *********************/
4339#define I2C_RXDR_RXDATA_Pos (0U)
4340#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
4341#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
4342
4343/****************** Bit definition for I2C_TXDR register *********************/
4344#define I2C_TXDR_TXDATA_Pos (0U)
4345#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
4346#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
4347
4348
4349/******************************************************************************/
4350/* */
4351/* Independent WATCHDOG (IWDG) */
4352/* */
4353/******************************************************************************/
4354/******************* Bit definition for IWDG_KR register ********************/
4355#define IWDG_KR_KEY_Pos (0U)
4356#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
4357#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
4358
4359/******************* Bit definition for IWDG_PR register ********************/
4360#define IWDG_PR_PR_Pos (0U)
4361#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
4362#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
4363#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
4364#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
4365#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
4366
4367/******************* Bit definition for IWDG_RLR register *******************/
4368#define IWDG_RLR_RL_Pos (0U)
4369#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
4370#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
4371
4372/******************* Bit definition for IWDG_SR register ********************/
4373#define IWDG_SR_PVU_Pos (0U)
4374#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
4375#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
4376#define IWDG_SR_RVU_Pos (1U)
4377#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
4378#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
4379#define IWDG_SR_WVU_Pos (2U)
4380#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
4381#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
4382
4383/******************* Bit definition for IWDG_KR register ********************/
4384#define IWDG_WINR_WIN_Pos (0U)
4385#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
4386#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
4387
4388
4389/******************************************************************************/
4390/* */
4391/* Power Control */
4392/* */
4393/******************************************************************************/
4394#define PWR_PVD_SUPPORT /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
4395#define PWR_BOR_SUPPORT /*!< PWR feature available only on specific devices: Brown-Out Reset feature */
4396#define PWR_SHDW_SUPPORT /*!< PWR feature available only on specific devices: Shutdown mode */
4397
4398/******************** Bit definition for PWR_CR1 register ********************/
4399#define PWR_CR1_LPMS_Pos (0U)
4400#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
4401#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low Power Mode Selection */
4402#define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
4403#define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
4404#define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */
4405#define PWR_CR1_FPD_STOP_Pos (3U)
4406#define PWR_CR1_FPD_STOP_Msk (0x1UL << PWR_CR1_FPD_STOP_Pos) /*!< 0x00000008 */
4407#define PWR_CR1_FPD_STOP PWR_CR1_FPD_STOP_Msk /*!< Flash power down mode during stop */
4408#define PWR_CR1_FPD_LPRUN_Pos (4U)
4409#define PWR_CR1_FPD_LPRUN_Msk (0x1UL << PWR_CR1_FPD_LPRUN_Pos) /*!< 0x00000010 */
4410#define PWR_CR1_FPD_LPRUN PWR_CR1_FPD_LPRUN_Msk /*!< Flash power down mode during run */
4411#define PWR_CR1_FPD_LPSLP_Pos (5U)
4412#define PWR_CR1_FPD_LPSLP_Msk (0x1UL << PWR_CR1_FPD_LPSLP_Pos) /*!< 0x00000020 */
4413#define PWR_CR1_FPD_LPSLP PWR_CR1_FPD_LPSLP_Msk /*!< Flash power down mode during sleep */
4414#define PWR_CR1_DBP_Pos (8U)
4415#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
4416#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Backup Domain write protection */
4417#define PWR_CR1_VOS_Pos (9U)
4418#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x00000600 */
4419#define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< Voltage scaling */
4420#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< Voltage scaling bit 0 */
4421#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< Voltage scaling bit 1 */
4422#define PWR_CR1_LPR_Pos (14U)
4423#define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
4424#define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator Low-Power Run mode */
4425
4426/******************** Bit definition for PWR_CR2 register ********************/
4427#define PWR_CR2_PVDE_Pos (0U)
4428#define PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */
4429#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Programmable Voltage Detector Enable */
4430#define PWR_CR2_PVDFT_Pos (1U)
4431#define PWR_CR2_PVDFT_Msk (0x7UL << PWR_CR2_PVDFT_Pos) /*!< 0x0000000E */
4432#define PWR_CR2_PVDFT PWR_CR2_PVDFT_Msk /*!< PVD Falling Threshold Selection bit field */
4433#define PWR_CR2_PVDFT_0 (0x1UL << PWR_CR2_PVDFT_Pos) /*!< 0x00000002 */
4434#define PWR_CR2_PVDFT_1 (0x2UL << PWR_CR2_PVDFT_Pos) /*!< 0x00000004 */
4435#define PWR_CR2_PVDFT_2 (0x4UL << PWR_CR2_PVDFT_Pos) /*!< 0x00000008 */
4436#define PWR_CR2_PVDRT_Pos (4U)
4437#define PWR_CR2_PVDRT_Msk (0x7UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000070 */
4438#define PWR_CR2_PVDRT PWR_CR2_PVDRT_Msk /*!< PVD Rising Threshold Selection bit field */
4439#define PWR_CR2_PVDRT_0 (0x1UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000010 */
4440#define PWR_CR2_PVDRT_1 (0x2UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000020 */
4441#define PWR_CR2_PVDRT_2 (0x4UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000040 */
4442
4443/******************** Bit definition for PWR_CR3 register ********************/
4444#define PWR_CR3_EWUP_Pos (0U)
4445#define PWR_CR3_EWUP_Msk (0x3BUL << PWR_CR3_EWUP_Pos) /*!< 0x0000003B */
4446#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable all Wake-Up Pins */
4447#define PWR_CR3_EWUP1_Pos (0U)
4448#define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
4449#define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable WKUP pin 1 */
4450#define PWR_CR3_EWUP2_Pos (1U)
4451#define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
4452#define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable WKUP pin 2 */
4453#define PWR_CR3_EWUP4_Pos (3U)
4454#define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
4455#define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable WKUP pin 4 */
4456#define PWR_CR3_EWUP5_Pos (4U)
4457#define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
4458#define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable WKUP pin 5 */
4459#define PWR_CR3_EWUP6_Pos (5U)
4460#define PWR_CR3_EWUP6_Msk (0x1UL << PWR_CR3_EWUP6_Pos) /*!< 0x00000020 */
4461#define PWR_CR3_EWUP6 PWR_CR3_EWUP6_Msk /*!< Enable WKUP pin 6 */
4462#define PWR_CR3_RRS_Pos (8U)
4463#define PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos) /*!< 0x00000100 */
4464#define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< RAM retention in Standby mode */
4465#define PWR_CR3_ENB_ULP_Pos (9U)
4466#define PWR_CR3_ENB_ULP_Msk (0x1UL << PWR_CR3_ENB_ULP_Pos) /*!< 0x00000200 */
4467#define PWR_CR3_ENB_ULP PWR_CR3_ENB_ULP_Msk /*!< Enable sampling resistor bridge in the LPMU_RESET block */
4468#define PWR_CR3_APC_Pos (10U)
4469#define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */
4470#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
4471#define PWR_CR3_EIWUL_Pos (15U)
4472#define PWR_CR3_EIWUL_Msk (0x1UL << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
4473#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
4474
4475/******************** Bit definition for PWR_CR4 register ********************/
4476#define PWR_CR4_WP_Pos (0U)
4477#define PWR_CR4_WP_Msk (0x3BUL << PWR_CR4_WP_Pos) /*!< 0x0000003B */
4478#define PWR_CR4_WP PWR_CR4_WP_Msk /*!< all Wake-Up Pin polarity */
4479#define PWR_CR4_WP1_Pos (0U)
4480#define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos) /*!< 0x00000001 */
4481#define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */
4482#define PWR_CR4_WP2_Pos (1U)
4483#define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos) /*!< 0x00000002 */
4484#define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */
4485#define PWR_CR4_WP4_Pos (3U)
4486#define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos) /*!< 0x00000008 */
4487#define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */
4488#define PWR_CR4_WP5_Pos (4U)
4489#define PWR_CR4_WP5_Msk (0x1UL << PWR_CR4_WP5_Pos) /*!< 0x00000010 */
4490#define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */
4491#define PWR_CR4_WP6_Pos (5U)
4492#define PWR_CR4_WP6_Msk (0x1UL << PWR_CR4_WP6_Pos) /*!< 0x00000020 */
4493#define PWR_CR4_WP6 PWR_CR4_WP6_Msk /*!< Wake-Up Pin 6 polarity */
4494#define PWR_CR4_VBE_Pos (8U)
4495#define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
4496#define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
4497#define PWR_CR4_VBRS_Pos (9U)
4498#define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
4499#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
4500
4501/******************** Bit definition for PWR_SR1 register ********************/
4502#define PWR_SR1_WUF_Pos (0U)
4503#define PWR_SR1_WUF_Msk (0x3BUL << PWR_SR1_WUF_Pos) /*!< 0x0000003B */
4504#define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wakeup Flags */
4505#define PWR_SR1_WUF1_Pos (0U)
4506#define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
4507#define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wakeup Flag 1 */
4508#define PWR_SR1_WUF2_Pos (1U)
4509#define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
4510#define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wakeup Flag 2 */
4511#define PWR_SR1_WUF4_Pos (3U)
4512#define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
4513#define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wakeup Flag 4 */
4514#define PWR_SR1_WUF5_Pos (4U)
4515#define PWR_SR1_WUF5_Msk (0x1UL << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */
4516#define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wakeup Flag 5 */
4517#define PWR_SR1_WUF6_Pos (5U)
4518#define PWR_SR1_WUF6_Msk (0x1UL << PWR_SR1_WUF6_Pos) /*!< 0x00000020 */
4519#define PWR_SR1_WUF6 PWR_SR1_WUF6_Msk /*!< Wakeup Flag 6 */
4520#define PWR_SR1_SBF_Pos (8U)
4521#define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
4522#define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Standby Flag */
4523#define PWR_SR1_WUFI_Pos (15U)
4524#define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
4525#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wakeup Flag Internal */
4526
4527/******************** Bit definition for PWR_SR2 register ********************/
4528#define PWR_SR2_FLASH_RDY_Pos (7U)
4529#define PWR_SR2_FLASH_RDY_Msk (0x1UL << PWR_SR2_FLASH_RDY_Pos) /*!< 0x00000080 */
4530#define PWR_SR2_FLASH_RDY PWR_SR2_FLASH_RDY_Msk /*!< Flash Ready */
4531#define PWR_SR2_REGLPS_Pos (8U)
4532#define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
4533#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Regulator Low Power started */
4534#define PWR_SR2_REGLPF_Pos (9U)
4535#define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
4536#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Regulator Low Power flag */
4537#define PWR_SR2_VOSF_Pos (10U)
4538#define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
4539#define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
4540#define PWR_SR2_PVDO_Pos (11U)
4541#define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
4542#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power voltage detector output */
4543
4544/******************** Bit definition for PWR_SCR register ********************/
4545#define PWR_SCR_CWUF_Pos (0U)
4546#define PWR_SCR_CWUF_Msk (0x3BUL << PWR_SCR_CWUF_Pos) /*!< 0x0000003B */
4547#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
4548#define PWR_SCR_CWUF1_Pos (0U)
4549#define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
4550#define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
4551#define PWR_SCR_CWUF2_Pos (1U)
4552#define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
4553#define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
4554#define PWR_SCR_CWUF4_Pos (3U)
4555#define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
4556#define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
4557#define PWR_SCR_CWUF5_Pos (4U)
4558#define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
4559#define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */
4560#define PWR_SCR_CWUF6_Pos (5U)
4561#define PWR_SCR_CWUF6_Msk (0x1UL << PWR_SCR_CWUF6_Pos) /*!< 0x00000020 */
4562#define PWR_SCR_CWUF6 PWR_SCR_CWUF6_Msk /*!< Clear Wake-up Flag 6 */
4563#define PWR_SCR_CSBF_Pos (8U)
4564#define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
4565#define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Standby Flag */
4566
4567/******************** Bit definition for PWR_PUCRA register *****************/
4568#define PWR_PUCRA_PU0_Pos (0U)
4569#define PWR_PUCRA_PU0_Msk (0x1UL << PWR_PUCRA_PU0_Pos) /*!< 0x00000001 */
4570#define PWR_PUCRA_PU0 PWR_PUCRA_PU0_Msk /*!< Pin PA0 Pull-Up set */
4571#define PWR_PUCRA_PU1_Pos (1U)
4572#define PWR_PUCRA_PU1_Msk (0x1UL << PWR_PUCRA_PU1_Pos) /*!< 0x00000002 */
4573#define PWR_PUCRA_PU1 PWR_PUCRA_PU1_Msk /*!< Pin PA1 Pull-Up set */
4574#define PWR_PUCRA_PU2_Pos (2U)
4575#define PWR_PUCRA_PU2_Msk (0x1UL << PWR_PUCRA_PU2_Pos) /*!< 0x00000004 */
4576#define PWR_PUCRA_PU2 PWR_PUCRA_PU2_Msk /*!< Pin PA2 Pull-Up set */
4577#define PWR_PUCRA_PU3_Pos (3U)
4578#define PWR_PUCRA_PU3_Msk (0x1UL << PWR_PUCRA_PU3_Pos) /*!< 0x00000008 */
4579#define PWR_PUCRA_PU3 PWR_PUCRA_PU3_Msk /*!< Pin PA3 Pull-Up set */
4580#define PWR_PUCRA_PU4_Pos (4U)
4581#define PWR_PUCRA_PU4_Msk (0x1UL << PWR_PUCRA_PU4_Pos) /*!< 0x00000010 */
4582#define PWR_PUCRA_PU4 PWR_PUCRA_PU4_Msk /*!< Pin PA4 Pull-Up set */
4583#define PWR_PUCRA_PU5_Pos (5U)
4584#define PWR_PUCRA_PU5_Msk (0x1UL << PWR_PUCRA_PU5_Pos) /*!< 0x00000020 */
4585#define PWR_PUCRA_PU5 PWR_PUCRA_PU5_Msk /*!< Pin PA5 Pull-Up set */
4586#define PWR_PUCRA_PU6_Pos (6U)
4587#define PWR_PUCRA_PU6_Msk (0x1UL << PWR_PUCRA_PU6_Pos) /*!< 0x00000040 */
4588#define PWR_PUCRA_PU6 PWR_PUCRA_PU6_Msk /*!< Pin PA6 Pull-Up set */
4589#define PWR_PUCRA_PU7_Pos (7U)
4590#define PWR_PUCRA_PU7_Msk (0x1UL << PWR_PUCRA_PU7_Pos) /*!< 0x00000080 */
4591#define PWR_PUCRA_PU7 PWR_PUCRA_PU7_Msk /*!< Pin PA7 Pull-Up set */
4592#define PWR_PUCRA_PU8_Pos (8U)
4593#define PWR_PUCRA_PU8_Msk (0x1UL << PWR_PUCRA_PU8_Pos) /*!< 0x00000100 */
4594#define PWR_PUCRA_PU8 PWR_PUCRA_PU8_Msk /*!< Pin PA8 Pull-Up set */
4595#define PWR_PUCRA_PU9_Pos (9U)
4596#define PWR_PUCRA_PU9_Msk (0x1UL << PWR_PUCRA_PU9_Pos) /*!< 0x00000200 */
4597#define PWR_PUCRA_PU9 PWR_PUCRA_PU9_Msk /*!< Pin PA9 Pull-Up set */
4598#define PWR_PUCRA_PU10_Pos (10U)
4599#define PWR_PUCRA_PU10_Msk (0x1UL << PWR_PUCRA_PU10_Pos) /*!< 0x00000400 */
4600#define PWR_PUCRA_PU10 PWR_PUCRA_PU10_Msk /*!< Pin PA10 Pull-Up set */
4601#define PWR_PUCRA_PU11_Pos (11U)
4602#define PWR_PUCRA_PU11_Msk (0x1UL << PWR_PUCRA_PU11_Pos) /*!< 0x00000800 */
4603#define PWR_PUCRA_PU11 PWR_PUCRA_PU11_Msk /*!< Pin PA11 Pull-Up set */
4604#define PWR_PUCRA_PU12_Pos (12U)
4605#define PWR_PUCRA_PU12_Msk (0x1UL << PWR_PUCRA_PU12_Pos) /*!< 0x00001000 */
4606#define PWR_PUCRA_PU12 PWR_PUCRA_PU12_Msk /*!< Pin PA12 Pull-Up set */
4607#define PWR_PUCRA_PU13_Pos (13U)
4608#define PWR_PUCRA_PU13_Msk (0x1UL << PWR_PUCRA_PU13_Pos) /*!< 0x00002000 */
4609#define PWR_PUCRA_PU13 PWR_PUCRA_PU13_Msk /*!< Pin PA13 Pull-Up set */
4610#define PWR_PUCRA_PU14_Pos (14U)
4611#define PWR_PUCRA_PU14_Msk (0x1UL << PWR_PUCRA_PU14_Pos) /*!< 0x00004000 */
4612#define PWR_PUCRA_PU14 PWR_PUCRA_PU14_Msk /*!< Pin PA14 Pull-Up set */
4613#define PWR_PUCRA_PU15_Pos (15U)
4614#define PWR_PUCRA_PU15_Msk (0x1UL << PWR_PUCRA_PU15_Pos) /*!< 0x00008000 */
4615#define PWR_PUCRA_PU15 PWR_PUCRA_PU15_Msk /*!< Pin PA15 Pull-Up set */
4616
4617/******************** Bit definition for PWR_PDCRA register *****************/
4618#define PWR_PDCRA_PD0_Pos (0U)
4619#define PWR_PDCRA_PD0_Msk (0x1UL << PWR_PDCRA_PD0_Pos) /*!< 0x00000001 */
4620#define PWR_PDCRA_PD0 PWR_PDCRA_PD0_Msk /*!< Pin PA0 Pull-Down set */
4621#define PWR_PDCRA_PD1_Pos (1U)
4622#define PWR_PDCRA_PD1_Msk (0x1UL << PWR_PDCRA_PD1_Pos) /*!< 0x00000002 */
4623#define PWR_PDCRA_PD1 PWR_PDCRA_PD1_Msk /*!< Pin PA1 Pull-Down set */
4624#define PWR_PDCRA_PD2_Pos (2U)
4625#define PWR_PDCRA_PD2_Msk (0x1UL << PWR_PDCRA_PD2_Pos) /*!< 0x00000004 */
4626#define PWR_PDCRA_PD2 PWR_PDCRA_PD2_Msk /*!< Pin PA2 Pull-Down set */
4627#define PWR_PDCRA_PD3_Pos (3U)
4628#define PWR_PDCRA_PD3_Msk (0x1UL << PWR_PDCRA_PD3_Pos) /*!< 0x00000008 */
4629#define PWR_PDCRA_PD3 PWR_PDCRA_PD3_Msk /*!< Pin PA3 Pull-Down set */
4630#define PWR_PDCRA_PD4_Pos (4U)
4631#define PWR_PDCRA_PD4_Msk (0x1UL << PWR_PDCRA_PD4_Pos) /*!< 0x00000010 */
4632#define PWR_PDCRA_PD4 PWR_PDCRA_PD4_Msk /*!< Pin PA4 Pull-Down set */
4633#define PWR_PDCRA_PD5_Pos (5U)
4634#define PWR_PDCRA_PD5_Msk (0x1UL << PWR_PDCRA_PD5_Pos) /*!< 0x00000020 */
4635#define PWR_PDCRA_PD5 PWR_PDCRA_PD5_Msk /*!< Pin PA5 Pull-Down set */
4636#define PWR_PDCRA_PD6_Pos (6U)
4637#define PWR_PDCRA_PD6_Msk (0x1UL << PWR_PDCRA_PD6_Pos) /*!< 0x00000040 */
4638#define PWR_PDCRA_PD6 PWR_PDCRA_PD6_Msk /*!< Pin PA6 Pull-Down set */
4639#define PWR_PDCRA_PD7_Pos (7U)
4640#define PWR_PDCRA_PD7_Msk (0x1UL << PWR_PDCRA_PD7_Pos) /*!< 0x00000080 */
4641#define PWR_PDCRA_PD7 PWR_PDCRA_PD7_Msk /*!< Pin PA7 Pull-Down set */
4642#define PWR_PDCRA_PD8_Pos (8U)
4643#define PWR_PDCRA_PD8_Msk (0x1UL << PWR_PDCRA_PD8_Pos) /*!< 0x00000100 */
4644#define PWR_PDCRA_PD8 PWR_PDCRA_PD8_Msk /*!< Pin PA8 Pull-Down set */
4645#define PWR_PDCRA_PD9_Pos (9U)
4646#define PWR_PDCRA_PD9_Msk (0x1UL << PWR_PDCRA_PD9_Pos) /*!< 0x00000200 */
4647#define PWR_PDCRA_PD9 PWR_PDCRA_PD9_Msk /*!< Pin PA9 Pull-Down set */
4648#define PWR_PDCRA_PD10_Pos (10U)
4649#define PWR_PDCRA_PD10_Msk (0x1UL << PWR_PDCRA_PD10_Pos) /*!< 0x00000400 */
4650#define PWR_PDCRA_PD10 PWR_PDCRA_PD10_Msk /*!< Pin PA10 Pull-Down set */
4651#define PWR_PDCRA_PD11_Pos (11U)
4652#define PWR_PDCRA_PD11_Msk (0x1UL << PWR_PDCRA_PD11_Pos) /*!< 0x00000800 */
4653#define PWR_PDCRA_PD11 PWR_PDCRA_PD11_Msk /*!< Pin PA11 Pull-Down set */
4654#define PWR_PDCRA_PD12_Pos (12U)
4655#define PWR_PDCRA_PD12_Msk (0x1UL << PWR_PDCRA_PD12_Pos) /*!< 0x00001000 */
4656#define PWR_PDCRA_PD12 PWR_PDCRA_PD12_Msk /*!< Pin PA12 Pull-Down set */
4657#define PWR_PDCRA_PD13_Pos (13U)
4658#define PWR_PDCRA_PD13_Msk (0x1UL << PWR_PDCRA_PD13_Pos) /*!< 0x00002000 */
4659#define PWR_PDCRA_PD13 PWR_PDCRA_PD13_Msk /*!< Pin PA13 Pull-Down set */
4660#define PWR_PDCRA_PD14_Pos (14U)
4661#define PWR_PDCRA_PD14_Msk (0x1UL << PWR_PDCRA_PD14_Pos) /*!< 0x00004000 */
4662#define PWR_PDCRA_PD14 PWR_PDCRA_PD14_Msk /*!< Pin PA14 Pull-Down set */
4663#define PWR_PDCRA_PD15_Pos (15U)
4664#define PWR_PDCRA_PD15_Msk (0x1UL << PWR_PDCRA_PD15_Pos) /*!< 0x00008000 */
4665#define PWR_PDCRA_PD15 PWR_PDCRA_PD15_Msk /*!< Pin PA15 Pull-Down set */
4666
4667/******************** Bit definition for PWR_PUCRB register *****************/
4668#define PWR_PUCRB_PU0_Pos (0U)
4669#define PWR_PUCRB_PU0_Msk (0x1UL << PWR_PUCRB_PU0_Pos) /*!< 0x00000001 */
4670#define PWR_PUCRB_PU0 PWR_PUCRB_PU0_Msk /*!< Pin PB0 Pull-Up set */
4671#define PWR_PUCRB_PU1_Pos (1U)
4672#define PWR_PUCRB_PU1_Msk (0x1UL << PWR_PUCRB_PU1_Pos) /*!< 0x00000002 */
4673#define PWR_PUCRB_PU1 PWR_PUCRB_PU1_Msk /*!< Pin PB1 Pull-Up set */
4674#define PWR_PUCRB_PU2_Pos (2U)
4675#define PWR_PUCRB_PU2_Msk (0x1UL << PWR_PUCRB_PU2_Pos) /*!< 0x00000004 */
4676#define PWR_PUCRB_PU2 PWR_PUCRB_PU2_Msk /*!< Pin PB2 Pull-Up set */
4677#define PWR_PUCRB_PU3_Pos (3U)
4678#define PWR_PUCRB_PU3_Msk (0x1UL << PWR_PUCRB_PU3_Pos) /*!< 0x00000008 */
4679#define PWR_PUCRB_PU3 PWR_PUCRB_PU3_Msk /*!< Pin PB3 Pull-Up set */
4680#define PWR_PUCRB_PU4_Pos (4U)
4681#define PWR_PUCRB_PU4_Msk (0x1UL << PWR_PUCRB_PU4_Pos) /*!< 0x00000010 */
4682#define PWR_PUCRB_PU4 PWR_PUCRB_PU4_Msk /*!< Pin PB4 Pull-Up set */
4683#define PWR_PUCRB_PU5_Pos (5U)
4684#define PWR_PUCRB_PU5_Msk (0x1UL << PWR_PUCRB_PU5_Pos) /*!< 0x00000020 */
4685#define PWR_PUCRB_PU5 PWR_PUCRB_PU5_Msk /*!< Pin PB5 Pull-Up set */
4686#define PWR_PUCRB_PU6_Pos (6U)
4687#define PWR_PUCRB_PU6_Msk (0x1UL << PWR_PUCRB_PU6_Pos) /*!< 0x00000040 */
4688#define PWR_PUCRB_PU6 PWR_PUCRB_PU6_Msk /*!< Pin PB6 Pull-Up set */
4689#define PWR_PUCRB_PU7_Pos (7U)
4690#define PWR_PUCRB_PU7_Msk (0x1UL << PWR_PUCRB_PU7_Pos) /*!< 0x00000080 */
4691#define PWR_PUCRB_PU7 PWR_PUCRB_PU7_Msk /*!< Pin PB7 Pull-Up set */
4692#define PWR_PUCRB_PU8_Pos (8U)
4693#define PWR_PUCRB_PU8_Msk (0x1UL << PWR_PUCRB_PU8_Pos) /*!< 0x00000100 */
4694#define PWR_PUCRB_PU8 PWR_PUCRB_PU8_Msk /*!< Pin PB8 Pull-Up set */
4695#define PWR_PUCRB_PU9_Pos (9U)
4696#define PWR_PUCRB_PU9_Msk (0x1UL << PWR_PUCRB_PU9_Pos) /*!< 0x00000200 */
4697#define PWR_PUCRB_PU9 PWR_PUCRB_PU9_Msk /*!< Pin PB9 Pull-Up set */
4698#define PWR_PUCRB_PU10_Pos (10U)
4699#define PWR_PUCRB_PU10_Msk (0x1UL << PWR_PUCRB_PU10_Pos) /*!< 0x00000400 */
4700#define PWR_PUCRB_PU10 PWR_PUCRB_PU10_Msk /*!< Pin PB10 Pull-Up set */
4701#define PWR_PUCRB_PU11_Pos (11U)
4702#define PWR_PUCRB_PU11_Msk (0x1UL << PWR_PUCRB_PU11_Pos) /*!< 0x00000800 */
4703#define PWR_PUCRB_PU11 PWR_PUCRB_PU11_Msk /*!< Pin PB11 Pull-Up set */
4704#define PWR_PUCRB_PU12_Pos (12U)
4705#define PWR_PUCRB_PU12_Msk (0x1UL << PWR_PUCRB_PU12_Pos) /*!< 0x00001000 */
4706#define PWR_PUCRB_PU12 PWR_PUCRB_PU12_Msk /*!< Pin PB12 Pull-Up set */
4707#define PWR_PUCRB_PU13_Pos (13U)
4708#define PWR_PUCRB_PU13_Msk (0x1UL << PWR_PUCRB_PU13_Pos) /*!< 0x00002000 */
4709#define PWR_PUCRB_PU13 PWR_PUCRB_PU13_Msk /*!< Pin PB13 Pull-Up set */
4710#define PWR_PUCRB_PU14_Pos (14U)
4711#define PWR_PUCRB_PU14_Msk (0x1UL << PWR_PUCRB_PU14_Pos) /*!< 0x00004000 */
4712#define PWR_PUCRB_PU14 PWR_PUCRB_PU14_Msk /*!< Pin PB14 Pull-Up set */
4713#define PWR_PUCRB_PU15_Pos (15U)
4714#define PWR_PUCRB_PU15_Msk (0x1UL << PWR_PUCRB_PU15_Pos) /*!< 0x00008000 */
4715#define PWR_PUCRB_PU15 PWR_PUCRB_PU15_Msk /*!< Pin PB15 Pull-Up set */
4716
4717/******************** Bit definition for PWR_PDCRB register *****************/
4718#define PWR_PDCRB_PD0_Pos (0U)
4719#define PWR_PDCRB_PD0_Msk (0x1UL << PWR_PDCRB_PD0_Pos) /*!< 0x00000001 */
4720#define PWR_PDCRB_PD0 PWR_PDCRB_PD0_Msk /*!< Pin PB0 Pull-Down set */
4721#define PWR_PDCRB_PD1_Pos (1U)
4722#define PWR_PDCRB_PD1_Msk (0x1UL << PWR_PDCRB_PD1_Pos) /*!< 0x00000002 */
4723#define PWR_PDCRB_PD1 PWR_PDCRB_PD1_Msk /*!< Pin PB1 Pull-Down set */
4724#define PWR_PDCRB_PD2_Pos (2U)
4725#define PWR_PDCRB_PD2_Msk (0x1UL << PWR_PDCRB_PD2_Pos) /*!< 0x00000004 */
4726#define PWR_PDCRB_PD2 PWR_PDCRB_PD2_Msk /*!< Pin PB2 Pull-Down set */
4727#define PWR_PDCRB_PD3_Pos (3U)
4728#define PWR_PDCRB_PD3_Msk (0x1UL << PWR_PDCRB_PD3_Pos) /*!< 0x00000008 */
4729#define PWR_PDCRB_PD3 PWR_PDCRB_PD3_Msk /*!< Pin PB3 Pull-Down set */
4730#define PWR_PDCRB_PD4_Pos (4U)
4731#define PWR_PDCRB_PD4_Msk (0x1UL << PWR_PDCRB_PD4_Pos) /*!< 0x00000010 */
4732#define PWR_PDCRB_PD4 PWR_PDCRB_PD4_Msk /*!< Pin PB4 Pull-Down set */
4733#define PWR_PDCRB_PD5_Pos (5U)
4734#define PWR_PDCRB_PD5_Msk (0x1UL << PWR_PDCRB_PD5_Pos) /*!< 0x00000020 */
4735#define PWR_PDCRB_PD5 PWR_PDCRB_PD5_Msk /*!< Pin PB5 Pull-Down set */
4736#define PWR_PDCRB_PD6_Pos (6U)
4737#define PWR_PDCRB_PD6_Msk (0x1UL << PWR_PDCRB_PD6_Pos) /*!< 0x00000040 */
4738#define PWR_PDCRB_PD6 PWR_PDCRB_PD6_Msk /*!< Pin PB6 Pull-Down set */
4739#define PWR_PDCRB_PD7_Pos (7U)
4740#define PWR_PDCRB_PD7_Msk (0x1UL << PWR_PDCRB_PD7_Pos) /*!< 0x00000080 */
4741#define PWR_PDCRB_PD7 PWR_PDCRB_PD7_Msk /*!< Pin PB7 Pull-Down set */
4742#define PWR_PDCRB_PD8_Pos (8U)
4743#define PWR_PDCRB_PD8_Msk (0x1UL << PWR_PDCRB_PD8_Pos) /*!< 0x00000100 */
4744#define PWR_PDCRB_PD8 PWR_PDCRB_PD8_Msk /*!< Pin PB8 Pull-Down set */
4745#define PWR_PDCRB_PD9_Pos (9U)
4746#define PWR_PDCRB_PD9_Msk (0x1UL << PWR_PDCRB_PD9_Pos) /*!< 0x00000200 */
4747#define PWR_PDCRB_PD9 PWR_PDCRB_PD9_Msk /*!< Pin PB9 Pull-Down set */
4748#define PWR_PDCRB_PD10_Pos (10U)
4749#define PWR_PDCRB_PD10_Msk (0x1UL << PWR_PDCRB_PD10_Pos) /*!< 0x00000400 */
4750#define PWR_PDCRB_PD10 PWR_PDCRB_PD10_Msk /*!< Pin PB10 Pull-Down set */
4751#define PWR_PDCRB_PD11_Pos (11U)
4752#define PWR_PDCRB_PD11_Msk (0x1UL << PWR_PDCRB_PD11_Pos) /*!< 0x00000800 */
4753#define PWR_PDCRB_PD11 PWR_PDCRB_PD11_Msk /*!< Pin PB11 Pull-Down set */
4754#define PWR_PDCRB_PD12_Pos (12U)
4755#define PWR_PDCRB_PD12_Msk (0x1UL << PWR_PDCRB_PD12_Pos) /*!< 0x00001000 */
4756#define PWR_PDCRB_PD12 PWR_PDCRB_PD12_Msk /*!< Pin PB12 Pull-Down set */
4757#define PWR_PDCRB_PD13_Pos (13U)
4758#define PWR_PDCRB_PD13_Msk (0x1UL << PWR_PDCRB_PD13_Pos) /*!< 0x00002000 */
4759#define PWR_PDCRB_PD13 PWR_PDCRB_PD13_Msk /*!< Pin PB13 Pull-Down set */
4760#define PWR_PDCRB_PD14_Pos (14U)
4761#define PWR_PDCRB_PD14_Msk (0x1UL << PWR_PDCRB_PD14_Pos) /*!< 0x00004000 */
4762#define PWR_PDCRB_PD14 PWR_PDCRB_PD14_Msk /*!< Pin PB14 Pull-Down set */
4763#define PWR_PDCRB_PD15_Pos (15U)
4764#define PWR_PDCRB_PD15_Msk (0x1UL << PWR_PDCRB_PD15_Pos) /*!< 0x00008000 */
4765#define PWR_PDCRB_PD15 PWR_PDCRB_PD15_Msk /*!< Pin PB15 Pull-Down set */
4766
4767/******************** Bit definition for PWR_PUCRC register *****************/
4768#define PWR_PUCRC_PU0_Pos (0U)
4769#define PWR_PUCRC_PU0_Msk (0x1UL << PWR_PUCRC_PU0_Pos) /*!< 0x00000001 */
4770#define PWR_PUCRC_PU0 PWR_PUCRC_PU0_Msk /*!< Pin PC0 Pull-Up set */
4771#define PWR_PUCRC_PU1_Pos (1U)
4772#define PWR_PUCRC_PU1_Msk (0x1UL << PWR_PUCRC_PU1_Pos) /*!< 0x00000002 */
4773#define PWR_PUCRC_PU1 PWR_PUCRC_PU1_Msk /*!< Pin PC1 Pull-Up set */
4774#define PWR_PUCRC_PU2_Pos (2U)
4775#define PWR_PUCRC_PU2_Msk (0x1UL << PWR_PUCRC_PU2_Pos) /*!< 0x00000004 */
4776#define PWR_PUCRC_PU2 PWR_PUCRC_PU2_Msk /*!< Pin PC2 Pull-Up set */
4777#define PWR_PUCRC_PU3_Pos (3U)
4778#define PWR_PUCRC_PU3_Msk (0x1UL << PWR_PUCRC_PU3_Pos) /*!< 0x00000008 */
4779#define PWR_PUCRC_PU3 PWR_PUCRC_PU3_Msk /*!< Pin PC3 Pull-Up set */
4780#define PWR_PUCRC_PU4_Pos (4U)
4781#define PWR_PUCRC_PU4_Msk (0x1UL << PWR_PUCRC_PU4_Pos) /*!< 0x00000010 */
4782#define PWR_PUCRC_PU4 PWR_PUCRC_PU4_Msk /*!< Pin PC4 Pull-Up set */
4783#define PWR_PUCRC_PU5_Pos (5U)
4784#define PWR_PUCRC_PU5_Msk (0x1UL << PWR_PUCRC_PU5_Pos) /*!< 0x00000020 */
4785#define PWR_PUCRC_PU5 PWR_PUCRC_PU5_Msk /*!< Pin PC5 Pull-Up set */
4786#define PWR_PUCRC_PU6_Pos (6U)
4787#define PWR_PUCRC_PU6_Msk (0x1UL << PWR_PUCRC_PU6_Pos) /*!< 0x00000040 */
4788#define PWR_PUCRC_PU6 PWR_PUCRC_PU6_Msk /*!< Pin PC6 Pull-Up set */
4789#define PWR_PUCRC_PU7_Pos (7U)
4790#define PWR_PUCRC_PU7_Msk (0x1UL << PWR_PUCRC_PU7_Pos) /*!< 0x00000080 */
4791#define PWR_PUCRC_PU7 PWR_PUCRC_PU7_Msk /*!< Pin PC7 Pull-Up set */
4792#define PWR_PUCRC_PU8_Pos (8U)
4793#define PWR_PUCRC_PU8_Msk (0x1UL << PWR_PUCRC_PU8_Pos) /*!< 0x00000100 */
4794#define PWR_PUCRC_PU8 PWR_PUCRC_PU8_Msk /*!< Pin PC8 Pull-Up set */
4795#define PWR_PUCRC_PU9_Pos (9U)
4796#define PWR_PUCRC_PU9_Msk (0x1UL << PWR_PUCRC_PU9_Pos) /*!< 0x00000200 */
4797#define PWR_PUCRC_PU9 PWR_PUCRC_PU9_Msk /*!< Pin PC9 Pull-Up set */
4798#define PWR_PUCRC_PU10_Pos (10U)
4799#define PWR_PUCRC_PU10_Msk (0x1UL << PWR_PUCRC_PU10_Pos) /*!< 0x00000400 */
4800#define PWR_PUCRC_PU10 PWR_PUCRC_PU10_Msk /*!< Pin PC10 Pull-Up set */
4801#define PWR_PUCRC_PU11_Pos (11U)
4802#define PWR_PUCRC_PU11_Msk (0x1UL << PWR_PUCRC_PU11_Pos) /*!< 0x00000800 */
4803#define PWR_PUCRC_PU11 PWR_PUCRC_PU11_Msk /*!< Pin PC11 Pull-Up set */
4804#define PWR_PUCRC_PU12_Pos (12U)
4805#define PWR_PUCRC_PU12_Msk (0x1UL << PWR_PUCRC_PU12_Pos) /*!< 0x00001000 */
4806#define PWR_PUCRC_PU12 PWR_PUCRC_PU12_Msk /*!< Pin PC12 Pull-Up set */
4807#define PWR_PUCRC_PU13_Pos (13U)
4808#define PWR_PUCRC_PU13_Msk (0x1UL << PWR_PUCRC_PU13_Pos) /*!< 0x00002000 */
4809#define PWR_PUCRC_PU13 PWR_PUCRC_PU13_Msk /*!< Pin PC13 Pull-Up set */
4810#define PWR_PUCRC_PU14_Pos (14U)
4811#define PWR_PUCRC_PU14_Msk (0x1UL << PWR_PUCRC_PU14_Pos) /*!< 0x00004000 */
4812#define PWR_PUCRC_PU14 PWR_PUCRC_PU14_Msk /*!< Pin PC14 Pull-Up set */
4813#define PWR_PUCRC_PU15_Pos (15U)
4814#define PWR_PUCRC_PU15_Msk (0x1UL << PWR_PUCRC_PU15_Pos) /*!< 0x00008000 */
4815#define PWR_PUCRC_PU15 PWR_PUCRC_PU15_Msk /*!< Pin PC15 Pull-Up set */
4816
4817/******************** Bit definition for PWR_PDCRC register *****************/
4818#define PWR_PDCRC_PD0_Pos (0U)
4819#define PWR_PDCRC_PD0_Msk (0x1UL << PWR_PDCRC_PD0_Pos) /*!< 0x00000001 */
4820#define PWR_PDCRC_PD0 PWR_PDCRC_PD0_Msk /*!< Pin PC0 Pull-Down set */
4821#define PWR_PDCRC_PD1_Pos (1U)
4822#define PWR_PDCRC_PD1_Msk (0x1UL << PWR_PDCRC_PD1_Pos) /*!< 0x00000002 */
4823#define PWR_PDCRC_PD1 PWR_PDCRC_PD1_Msk /*!< Pin PC1 Pull-Down set */
4824#define PWR_PDCRC_PD2_Pos (2U)
4825#define PWR_PDCRC_PD2_Msk (0x1UL << PWR_PDCRC_PD2_Pos) /*!< 0x00000004 */
4826#define PWR_PDCRC_PD2 PWR_PDCRC_PD2_Msk /*!< Pin PC2 Pull-Down set */
4827#define PWR_PDCRC_PD3_Pos (3U)
4828#define PWR_PDCRC_PD3_Msk (0x1UL << PWR_PDCRC_PD3_Pos) /*!< 0x00000008 */
4829#define PWR_PDCRC_PD3 PWR_PDCRC_PD3_Msk /*!< Pin PC3 Pull-Down set */
4830#define PWR_PDCRC_PD4_Pos (4U)
4831#define PWR_PDCRC_PD4_Msk (0x1UL << PWR_PDCRC_PD4_Pos) /*!< 0x00000010 */
4832#define PWR_PDCRC_PD4 PWR_PDCRC_PD4_Msk /*!< Pin PC4 Pull-Down set */
4833#define PWR_PDCRC_PD5_Pos (5U)
4834#define PWR_PDCRC_PD5_Msk (0x1UL << PWR_PDCRC_PD5_Pos) /*!< 0x00000020 */
4835#define PWR_PDCRC_PD5 PWR_PDCRC_PD5_Msk /*!< Pin PC5 Pull-Down set */
4836#define PWR_PDCRC_PD6_Pos (6U)
4837#define PWR_PDCRC_PD6_Msk (0x1UL << PWR_PDCRC_PD6_Pos) /*!< 0x00000040 */
4838#define PWR_PDCRC_PD6 PWR_PDCRC_PD6_Msk /*!< Pin PC6 Pull-Down set */
4839#define PWR_PDCRC_PD7_Pos (7U)
4840#define PWR_PDCRC_PD7_Msk (0x1UL << PWR_PDCRC_PD7_Pos) /*!< 0x00000080 */
4841#define PWR_PDCRC_PD7 PWR_PDCRC_PD7_Msk /*!< Pin PC7 Pull-Down set */
4842#define PWR_PDCRC_PD8_Pos (8U)
4843#define PWR_PDCRC_PD8_Msk (0x1UL << PWR_PDCRC_PD8_Pos) /*!< 0x00000100 */
4844#define PWR_PDCRC_PD8 PWR_PDCRC_PD8_Msk /*!< Pin PC8 Pull-Down set */
4845#define PWR_PDCRC_PD9_Pos (9U)
4846#define PWR_PDCRC_PD9_Msk (0x1UL << PWR_PDCRC_PD9_Pos) /*!< 0x00000200 */
4847#define PWR_PDCRC_PD9 PWR_PDCRC_PD9_Msk /*!< Pin PC9 Pull-Down set */
4848#define PWR_PDCRC_PD10_Pos (10U)
4849#define PWR_PDCRC_PD10_Msk (0x1UL << PWR_PDCRC_PD10_Pos) /*!< 0x00000400 */
4850#define PWR_PDCRC_PD10 PWR_PDCRC_PD10_Msk /*!< Pin PC10 Pull-Down set */
4851#define PWR_PDCRC_PD11_Pos (11U)
4852#define PWR_PDCRC_PD11_Msk (0x1UL << PWR_PDCRC_PD11_Pos) /*!< 0x00000800 */
4853#define PWR_PDCRC_PD11 PWR_PDCRC_PD11_Msk /*!< Pin PC11 Pull-Down set */
4854#define PWR_PDCRC_PD12_Pos (12U)
4855#define PWR_PDCRC_PD12_Msk (0x1UL << PWR_PDCRC_PD12_Pos) /*!< 0x00001000 */
4856#define PWR_PDCRC_PD12 PWR_PDCRC_PD12_Msk /*!< Pin PC12 Pull-Down set */
4857#define PWR_PDCRC_PD13_Pos (13U)
4858#define PWR_PDCRC_PD13_Msk (0x1UL << PWR_PDCRC_PD13_Pos) /*!< 0x00002000 */
4859#define PWR_PDCRC_PD13 PWR_PDCRC_PD13_Msk /*!< Pin PC13 Pull-Down set */
4860#define PWR_PDCRC_PD14_Pos (14U)
4861#define PWR_PDCRC_PD14_Msk (0x1UL << PWR_PDCRC_PD14_Pos) /*!< 0x00004000 */
4862#define PWR_PDCRC_PD14 PWR_PDCRC_PD14_Msk /*!< Pin PC14 Pull-Down set */
4863#define PWR_PDCRC_PD15_Pos (15U)
4864#define PWR_PDCRC_PD15_Msk (0x1UL << PWR_PDCRC_PD15_Pos) /*!< 0x00008000 */
4865#define PWR_PDCRC_PD15 PWR_PDCRC_PD15_Msk /*!< Pin PC15 Pull-Down set */
4866
4867/******************** Bit definition for PWR_PUCRD register *****************/
4868#define PWR_PUCRD_PU0_Pos (0U)
4869#define PWR_PUCRD_PU0_Msk (0x1UL << PWR_PUCRD_PU0_Pos) /*!< 0x00000001 */
4870#define PWR_PUCRD_PU0 PWR_PUCRD_PU0_Msk /*!< Pin PD0 Pull-Up set */
4871#define PWR_PUCRD_PU1_Pos (1U)
4872#define PWR_PUCRD_PU1_Msk (0x1UL << PWR_PUCRD_PU1_Pos) /*!< 0x00000002 */
4873#define PWR_PUCRD_PU1 PWR_PUCRD_PU1_Msk /*!< Pin PD1 Pull-Up set */
4874#define PWR_PUCRD_PU2_Pos (2U)
4875#define PWR_PUCRD_PU2_Msk (0x1UL << PWR_PUCRD_PU2_Pos) /*!< 0x00000004 */
4876#define PWR_PUCRD_PU2 PWR_PUCRD_PU2_Msk /*!< Pin PD2 Pull-Up set */
4877#define PWR_PUCRD_PU3_Pos (3U)
4878#define PWR_PUCRD_PU3_Msk (0x1UL << PWR_PUCRD_PU3_Pos) /*!< 0x00000008 */
4879#define PWR_PUCRD_PU3 PWR_PUCRD_PU3_Msk /*!< Pin PD3 Pull-Up set */
4880#define PWR_PUCRD_PU4_Pos (4U)
4881#define PWR_PUCRD_PU4_Msk (0x1UL << PWR_PUCRD_PU4_Pos) /*!< 0x00000010 */
4882#define PWR_PUCRD_PU4 PWR_PUCRD_PU4_Msk /*!< Pin PD4 Pull-Up set */
4883#define PWR_PUCRD_PU5_Pos (5U)
4884#define PWR_PUCRD_PU5_Msk (0x1UL << PWR_PUCRD_PU5_Pos) /*!< 0x00000020 */
4885#define PWR_PUCRD_PU5 PWR_PUCRD_PU5_Msk /*!< Pin PD5 Pull-Up set */
4886#define PWR_PUCRD_PU6_Pos (6U)
4887#define PWR_PUCRD_PU6_Msk (0x1UL << PWR_PUCRD_PU6_Pos) /*!< 0x00000040 */
4888#define PWR_PUCRD_PU6 PWR_PUCRD_PU6_Msk /*!< Pin PD6 Pull-Up set */
4889#define PWR_PUCRD_PU8_Pos (8U)
4890#define PWR_PUCRD_PU8_Msk (0x1UL << PWR_PUCRD_PU8_Pos) /*!< 0x00000100 */
4891#define PWR_PUCRD_PU8 PWR_PUCRD_PU8_Msk /*!< Pin PD8 Pull-Up set */
4892#define PWR_PUCRD_PU9_Pos (9U)
4893#define PWR_PUCRD_PU9_Msk (0x1UL << PWR_PUCRD_PU9_Pos) /*!< 0x00000200 */
4894#define PWR_PUCRD_PU9 PWR_PUCRD_PU9_Msk /*!< Pin PD9 Pull-Up set */
4895
4896/******************** Bit definition for PWR_PDCRD register *****************/
4897#define PWR_PDCRD_PD0_Pos (0U)
4898#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
4899#define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Pin PD0 Pull-Down set */
4900#define PWR_PDCRD_PD1_Pos (1U)
4901#define PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */
4902#define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Pin PD1 Pull-Down set */
4903#define PWR_PDCRD_PD2_Pos (2U)
4904#define PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */
4905#define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Pin PD2 Pull-Down set */
4906#define PWR_PDCRD_PD3_Pos (3U)
4907#define PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */
4908#define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Pin PD3 Pull-Down set */
4909#define PWR_PDCRD_PD4_Pos (4U)
4910#define PWR_PDCRD_PD4_Msk (0x1UL << PWR_PDCRD_PD4_Pos) /*!< 0x00000010 */
4911#define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk /*!< Pin PD4 Pull-Down set */
4912#define PWR_PDCRD_PD5_Pos (5U)
4913#define PWR_PDCRD_PD5_Msk (0x1UL << PWR_PDCRD_PD5_Pos) /*!< 0x00000020 */
4914#define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk /*!< Pin PD5 Pull-Down set */
4915#define PWR_PDCRD_PD6_Pos (6U)
4916#define PWR_PDCRD_PD6_Msk (0x1UL << PWR_PDCRD_PD6_Pos) /*!< 0x00000040 */
4917#define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk /*!< Pin PD6 Pull-Down set */
4918#define PWR_PDCRD_PD8_Pos (8U)
4919#define PWR_PDCRD_PD8_Msk (0x1UL << PWR_PDCRD_PD8_Pos) /*!< 0x00000100 */
4920#define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk /*!< Pin PD8 Pull-Down set */
4921#define PWR_PDCRD_PD9_Pos (9U)
4922#define PWR_PDCRD_PD9_Msk (0x1UL << PWR_PDCRD_PD9_Pos) /*!< 0x00000200 */
4923#define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk /*!< Pin PD9 Pull-Down set */
4924
4925/******************** Bit definition for PWR_PUCRF register *****************/
4926#define PWR_PUCRF_PU0_Pos (0U)
4927#define PWR_PUCRF_PU0_Msk (0x1UL << PWR_PUCRF_PU0_Pos) /*!< 0x00000001 */
4928#define PWR_PUCRF_PU0 PWR_PUCRF_PU0_Msk /*!< Pin PF0 Pull-Up set */
4929#define PWR_PUCRF_PU1_Pos (1U)
4930#define PWR_PUCRF_PU1_Msk (0x1UL << PWR_PUCRF_PU1_Pos) /*!< 0x00000002 */
4931#define PWR_PUCRF_PU1 PWR_PUCRF_PU1_Msk /*!< Pin PF1 Pull-Up set */
4932#define PWR_PUCRF_PU2_Pos (2U)
4933#define PWR_PUCRF_PU2_Msk (0x1UL << PWR_PUCRF_PU2_Pos) /*!< 0x00000004 */
4934#define PWR_PUCRF_PU2 PWR_PUCRF_PU2_Msk /*!< Pin PF2 Pull-Up set */
4935#define PWR_PUCRF_PU3_Pos (3U)
4936#define PWR_PUCRF_PU3_Msk (0x1UL << PWR_PUCRF_PU3_Pos) /*!< 0x00000008 */
4937#define PWR_PUCRF_PU3 PWR_PUCRF_PU3_Msk /*!< Pin PF3 Pull-Up set */
4938#define PWR_PUCRF_PU4_Pos (4U)
4939#define PWR_PUCRF_PU4_Msk (0x1UL << PWR_PUCRF_PU4_Pos) /*!< 0x00000010 */
4940#define PWR_PUCRF_PU4 PWR_PUCRF_PU4_Msk /*!< Pin PF4 Pull-Up set */
4941
4942/******************** Bit definition for PWR_PDCRF register *****************/
4943#define PWR_PDCRF_PD0_Pos (0U)
4944#define PWR_PDCRF_PD0_Msk (0x1UL << PWR_PDCRF_PD0_Pos) /*!< 0x00000001 */
4945#define PWR_PDCRF_PD0 PWR_PDCRF_PD0_Msk /*!< Pin PF0 Pull-Down set */
4946#define PWR_PDCRF_PD1_Pos (1U)
4947#define PWR_PDCRF_PD1_Msk (0x1UL << PWR_PDCRF_PD1_Pos) /*!< 0x00000002 */
4948#define PWR_PDCRF_PD1 PWR_PDCRF_PD1_Msk /*!< Pin PF1 Pull-Down set */
4949#define PWR_PDCRF_PD2_Pos (2U)
4950#define PWR_PDCRF_PD2_Msk (0x1UL << PWR_PDCRF_PD2_Pos) /*!< 0x00000004 */
4951#define PWR_PDCRF_PD2 PWR_PDCRF_PD2_Msk /*!< Pin PF2 Pull-Down set */
4952#define PWR_PDCRF_PD3_Pos (3U)
4953#define PWR_PDCRF_PD3_Msk (0x1UL << PWR_PDCRF_PD3_Pos) /*!< 0x00000008 */
4954#define PWR_PDCRF_PD3 PWR_PDCRF_PD3_Msk /*!< Pin PF3 Pull-Down set */
4955#define PWR_PDCRF_PD4_Pos (4U)
4956#define PWR_PDCRF_PD4_Msk (0x1UL << PWR_PDCRF_PD4_Pos) /*!< 0x00000010 */
4957#define PWR_PDCRF_PD4 PWR_PDCRF_PD4_Msk /*!< Pin PF4 Pull-Down set */
4958
4959/******************************************************************************/
4960/* */
4961/* Reset and Clock Control */
4962/* */
4963/******************************************************************************/
4964/*
4965* @brief Specific device feature definitions (not present on all devices in the STM32G0 serie)
4966*/
4967#define RCC_PLLQ_SUPPORT
4968
4969/******************** Bit definition for RCC_CR register *****************/
4970#define RCC_CR_HSION_Pos (8U)
4971#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */
4972#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
4973#define RCC_CR_HSIKERON_Pos (9U)
4974#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
4975#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
4976#define RCC_CR_HSIRDY_Pos (10U)
4977#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
4978#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
4979#define RCC_CR_HSIDIV_Pos (11U)
4980#define RCC_CR_HSIDIV_Msk (0x7UL << RCC_CR_HSIDIV_Pos) /*!< 0x00003800 */
4981#define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk /*!< HSIDIV[13:11] Internal High Speed clock division factor */
4982#define RCC_CR_HSIDIV_0 (0x1UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000800 */
4983#define RCC_CR_HSIDIV_1 (0x2UL << RCC_CR_HSIDIV_Pos) /*!< 0x00001000 */
4984#define RCC_CR_HSIDIV_2 (0x4UL << RCC_CR_HSIDIV_Pos) /*!< 0x00002000 */
4985#define RCC_CR_HSEON_Pos (16U)
4986#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
4987#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
4988#define RCC_CR_HSERDY_Pos (17U)
4989#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
4990#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready */
4991#define RCC_CR_HSEBYP_Pos (18U)
4992#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
4993#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
4994#define RCC_CR_CSSON_Pos (19U)
4995#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
4996#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
4997
4998#define RCC_CR_PLLON_Pos (24U)
4999#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
5000#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
5001#define RCC_CR_PLLRDY_Pos (25U)
5002#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
5003#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
5004
5005/******************** Bit definition for RCC_ICSCR register ***************/
5006/*!< HSICAL configuration */
5007#define RCC_ICSCR_HSICAL_Pos (0U)
5008#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
5009#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
5010#define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000001 */
5011#define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000002 */
5012#define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000004 */
5013#define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000008 */
5014#define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000010 */
5015#define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000020 */
5016#define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000040 */
5017#define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000080 */
5018
5019/*!< HSITRIM configuration */
5020#define RCC_ICSCR_HSITRIM_Pos (8U)
5021#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00007F00 */
5022#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[14:8] bits */
5023#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000100 */
5024#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000200 */
5025#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000400 */
5026#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000800 */
5027#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001000 */
5028#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00002000 */
5029#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00004000 */
5030
5031/******************** Bit definition for RCC_CFGR register ***************/
5032/*!< SW configuration */
5033#define RCC_CFGR_SW_Pos (0U)
5034#define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos) /*!< 0x00000007 */
5035#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[2:0] bits (System clock Switch) */
5036#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
5037#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
5038#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */
5039
5040/*!< SWS configuration */
5041#define RCC_CFGR_SWS_Pos (3U)
5042#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */
5043#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[2:0] bits (System Clock Switch Status) */
5044#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
5045#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */
5046#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */
5047
5048#define RCC_CFGR_SWS_HSI (0UL) /*!< HSI used as system clock */
5049#define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */
5050#define RCC_CFGR_SWS_PLL (0x00000010UL) /*!< PLL used as system clock */
5051#define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */
5052#define RCC_CFGR_SWS_LSE (0x00000020UL) /*!< LSE used as system clock */
5053
5054/*!< HPRE configuration */
5055#define RCC_CFGR_HPRE_Pos (8U)
5056#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */
5057#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
5058#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000100 */
5059#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000200 */
5060#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000400 */
5061#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000800 */
5062
5063/*!< PPRE configuration */
5064#define RCC_CFGR_PPRE_Pos (12U)
5065#define RCC_CFGR_PPRE_Msk (0x7UL << RCC_CFGR_PPRE_Pos) /*!< 0x00007000 */
5066#define RCC_CFGR_PPRE RCC_CFGR_PPRE_Msk /*!< PRE1[2:0] bits (APB prescaler) */
5067#define RCC_CFGR_PPRE_0 (0x1UL << RCC_CFGR_PPRE_Pos) /*!< 0x00001000 */
5068#define RCC_CFGR_PPRE_1 (0x2UL << RCC_CFGR_PPRE_Pos) /*!< 0x00002000 */
5069#define RCC_CFGR_PPRE_2 (0x4UL << RCC_CFGR_PPRE_Pos) /*!< 0x00004000 */
5070
5071/*!< MCOSEL configuration */
5072#define RCC_CFGR_MCOSEL_Pos (24U)
5073#define RCC_CFGR_MCOSEL_Msk (0x7UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
5074#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [2:0] bits (Clock output selection) */
5075#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
5076#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
5077#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
5078
5079/*!< MCO Prescaler configuration */
5080#define RCC_CFGR_MCOPRE_Pos (28U)
5081#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
5082#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler [2:0] */
5083#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
5084#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
5085#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
5086
5087/******************** Bit definition for RCC_PLLCFGR register ***************/
5088#define RCC_PLLCFGR_PLLSRC_Pos (0U)
5089#define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
5090#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
5091#define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
5092#define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
5093
5094#define RCC_PLLCFGR_PLLSRC_NONE (0x00000000UL) /*!< No clock sent to PLL */
5095#define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
5096#define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
5097#define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI source clock selected */
5098#define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
5099#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
5100#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE source clock selected */
5101
5102#define RCC_PLLCFGR_PLLM_Pos (4U)
5103#define RCC_PLLCFGR_PLLM_Msk (0x7UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */
5104#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
5105#define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
5106#define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
5107#define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
5108
5109#define RCC_PLLCFGR_PLLN_Pos (8U)
5110#define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
5111#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
5112#define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
5113#define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
5114#define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
5115#define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
5116#define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
5117#define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
5118#define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
5119
5120#define RCC_PLLCFGR_PLLPEN_Pos (16U)
5121#define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
5122#define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
5123
5124#define RCC_PLLCFGR_PLLP_Pos (17U)
5125#define RCC_PLLCFGR_PLLP_Msk (0x1FUL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x003E0000 */
5126#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
5127#define RCC_PLLCFGR_PLLP_0 (0x01UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
5128#define RCC_PLLCFGR_PLLP_1 (0x02UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00040000 */
5129#define RCC_PLLCFGR_PLLP_2 (0x04UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00080000 */
5130#define RCC_PLLCFGR_PLLP_3 (0x08UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00100000 */
5131#define RCC_PLLCFGR_PLLP_4 (0x10UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00200000 */
5132
5133#define RCC_PLLCFGR_PLLQEN_Pos (24U)
5134#define RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x01000000 */
5135#define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
5136
5137#define RCC_PLLCFGR_PLLQ_Pos (25U)
5138#define RCC_PLLCFGR_PLLQ_Msk (0x7UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0E000000 */
5139#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
5140#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
5141#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
5142#define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
5143
5144#define RCC_PLLCFGR_PLLREN_Pos (28U)
5145#define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x10000000 */
5146#define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
5147
5148#define RCC_PLLCFGR_PLLR_Pos (29U)
5149#define RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0xE0000000 */
5150#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
5151#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
5152#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
5153#define RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x80000000 */
5154
5155/******************** Bit definition for RCC_CIER register ******************/
5156#define RCC_CIER_LSIRDYIE_Pos (0U)
5157#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
5158#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
5159#define RCC_CIER_LSERDYIE_Pos (1U)
5160#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
5161#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
5162#define RCC_CIER_HSIRDYIE_Pos (3U)
5163#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
5164#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
5165#define RCC_CIER_HSERDYIE_Pos (4U)
5166#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
5167#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
5168#define RCC_CIER_PLLRDYIE_Pos (5U)
5169#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
5170#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
5171
5172/******************** Bit definition for RCC_CIFR register ******************/
5173#define RCC_CIFR_LSIRDYF_Pos (0U)
5174#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
5175#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
5176#define RCC_CIFR_LSERDYF_Pos (1U)
5177#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
5178#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
5179#define RCC_CIFR_HSIRDYF_Pos (3U)
5180#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
5181#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
5182#define RCC_CIFR_HSERDYF_Pos (4U)
5183#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
5184#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
5185#define RCC_CIFR_PLLRDYF_Pos (5U)
5186#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
5187#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
5188#define RCC_CIFR_CSSF_Pos (8U)
5189#define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
5190#define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
5191#define RCC_CIFR_LSECSSF_Pos (9U)
5192#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
5193#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
5194
5195/******************** Bit definition for RCC_CICR register ******************/
5196#define RCC_CICR_LSIRDYC_Pos (0U)
5197#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
5198#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
5199#define RCC_CICR_LSERDYC_Pos (1U)
5200#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
5201#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
5202#define RCC_CICR_HSIRDYC_Pos (3U)
5203#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
5204#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
5205#define RCC_CICR_HSERDYC_Pos (4U)
5206#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
5207#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
5208#define RCC_CICR_PLLRDYC_Pos (5U)
5209#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
5210#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
5211#define RCC_CICR_CSSC_Pos (8U)
5212#define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
5213#define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
5214#define RCC_CICR_LSECSSC_Pos (9U)
5215#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
5216#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
5217
5218/******************** Bit definition for RCC_IOPRSTR register ****************/
5219#define RCC_IOPRSTR_GPIOARST_Pos (0U)
5220#define RCC_IOPRSTR_GPIOARST_Msk (0x1UL << RCC_IOPRSTR_GPIOARST_Pos) /*!< 0x00000001 */
5221#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_GPIOARST_Msk
5222#define RCC_IOPRSTR_GPIOBRST_Pos (1U)
5223#define RCC_IOPRSTR_GPIOBRST_Msk (0x1UL << RCC_IOPRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
5224#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_GPIOBRST_Msk
5225#define RCC_IOPRSTR_GPIOCRST_Pos (2U)
5226#define RCC_IOPRSTR_GPIOCRST_Msk (0x1UL << RCC_IOPRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
5227#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_GPIOCRST_Msk
5228#define RCC_IOPRSTR_GPIODRST_Pos (3U)
5229#define RCC_IOPRSTR_GPIODRST_Msk (0x1UL << RCC_IOPRSTR_GPIODRST_Pos) /*!< 0x00000008 */
5230#define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_GPIODRST_Msk
5231#define RCC_IOPRSTR_GPIOFRST_Pos (5U)
5232#define RCC_IOPRSTR_GPIOFRST_Msk (0x1UL << RCC_IOPRSTR_GPIOFRST_Pos) /*!< 0x00000020 */
5233#define RCC_IOPRSTR_GPIOFRST RCC_IOPRSTR_GPIOFRST_Msk
5234
5235/******************** Bit definition for RCC_AHBRSTR register ***************/
5236#define RCC_AHBRSTR_DMA1RST_Pos (0U)
5237#define RCC_AHBRSTR_DMA1RST_Msk (0x1UL << RCC_AHBRSTR_DMA1RST_Pos) /*!< 0x00000001 */
5238#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMA1RST_Msk
5239#define RCC_AHBRSTR_FLASHRST_Pos (8U)
5240#define RCC_AHBRSTR_FLASHRST_Msk (0x1UL << RCC_AHBRSTR_FLASHRST_Pos) /*!< 0x00000100 */
5241#define RCC_AHBRSTR_FLASHRST RCC_AHBRSTR_FLASHRST_Msk
5242#define RCC_AHBRSTR_CRCRST_Pos (12U)
5243#define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
5244#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk
5245#define RCC_AHBRSTR_AESRST_Pos (16U)
5246#define RCC_AHBRSTR_AESRST_Msk (0x1UL << RCC_AHBRSTR_AESRST_Pos) /*!< 0x00010000 */
5247#define RCC_AHBRSTR_AESRST RCC_AHBRSTR_AESRST_Msk
5248#define RCC_AHBRSTR_RNGRST_Pos (18U)
5249#define RCC_AHBRSTR_RNGRST_Msk (0x1UL << RCC_AHBRSTR_RNGRST_Pos) /*!< 0x00040000 */
5250#define RCC_AHBRSTR_RNGRST RCC_AHBRSTR_RNGRST_Msk
5251
5252/******************** Bit definition for RCC_APBRSTR1 register **************/
5253#define RCC_APBRSTR1_TIM2RST_Pos (0U)
5254#define RCC_APBRSTR1_TIM2RST_Msk (0x1UL << RCC_APBRSTR1_TIM2RST_Pos) /*!< 0x00000001 */
5255#define RCC_APBRSTR1_TIM2RST RCC_APBRSTR1_TIM2RST_Msk
5256#define RCC_APBRSTR1_TIM3RST_Pos (1U)
5257#define RCC_APBRSTR1_TIM3RST_Msk (0x1UL << RCC_APBRSTR1_TIM3RST_Pos) /*!< 0x00000002 */
5258#define RCC_APBRSTR1_TIM3RST RCC_APBRSTR1_TIM3RST_Msk
5259#define RCC_APBRSTR1_TIM6RST_Pos (4U)
5260#define RCC_APBRSTR1_TIM6RST_Msk (0x1UL << RCC_APBRSTR1_TIM6RST_Pos) /*!< 0x00000010 */
5261#define RCC_APBRSTR1_TIM6RST RCC_APBRSTR1_TIM6RST_Msk
5262#define RCC_APBRSTR1_TIM7RST_Pos (5U)
5263#define RCC_APBRSTR1_TIM7RST_Msk (0x1UL << RCC_APBRSTR1_TIM7RST_Pos) /*!< 0x00000020 */
5264#define RCC_APBRSTR1_TIM7RST RCC_APBRSTR1_TIM7RST_Msk
5265#define RCC_APBRSTR1_SPI2RST_Pos (14U)
5266#define RCC_APBRSTR1_SPI2RST_Msk (0x1UL << RCC_APBRSTR1_SPI2RST_Pos) /*!< 0x00004000 */
5267#define RCC_APBRSTR1_SPI2RST RCC_APBRSTR1_SPI2RST_Msk
5268#define RCC_APBRSTR1_USART2RST_Pos (17U)
5269#define RCC_APBRSTR1_USART2RST_Msk (0x1UL << RCC_APBRSTR1_USART2RST_Pos) /*!< 0x00020000 */
5270#define RCC_APBRSTR1_USART2RST RCC_APBRSTR1_USART2RST_Msk
5271#define RCC_APBRSTR1_USART3RST_Pos (18U)
5272#define RCC_APBRSTR1_USART3RST_Msk (0x1UL << RCC_APBRSTR1_USART3RST_Pos) /*!< 0x00040000 */
5273#define RCC_APBRSTR1_USART3RST RCC_APBRSTR1_USART3RST_Msk
5274#define RCC_APBRSTR1_USART4RST_Pos (19U)
5275#define RCC_APBRSTR1_USART4RST_Msk (0x1UL << RCC_APBRSTR1_USART4RST_Pos) /*!< 0x00080000 */
5276#define RCC_APBRSTR1_USART4RST RCC_APBRSTR1_USART4RST_Msk
5277#define RCC_APBRSTR1_LPUART1RST_Pos (20U)
5278#define RCC_APBRSTR1_LPUART1RST_Msk (0x1UL << RCC_APBRSTR1_LPUART1RST_Pos) /*!< 0x00100000 */
5279#define RCC_APBRSTR1_LPUART1RST RCC_APBRSTR1_LPUART1RST_Msk
5280#define RCC_APBRSTR1_I2C1RST_Pos (21U)
5281#define RCC_APBRSTR1_I2C1RST_Msk (0x1UL << RCC_APBRSTR1_I2C1RST_Pos) /*!< 0x00200000 */
5282#define RCC_APBRSTR1_I2C1RST RCC_APBRSTR1_I2C1RST_Msk
5283#define RCC_APBRSTR1_I2C2RST_Pos (22U)
5284#define RCC_APBRSTR1_I2C2RST_Msk (0x1UL << RCC_APBRSTR1_I2C2RST_Pos) /*!< 0x00400000 */
5285#define RCC_APBRSTR1_I2C2RST RCC_APBRSTR1_I2C2RST_Msk
5286#define RCC_APBRSTR1_CECRST_Pos (24U)
5287#define RCC_APBRSTR1_CECRST_Msk (0x1UL << RCC_APBRSTR1_CECRST_Pos) /*!< 0x01000000 */
5288#define RCC_APBRSTR1_CECRST RCC_APBRSTR1_CECRST_Msk
5289#define RCC_APBRSTR1_UCPD1RST_Pos (25U)
5290#define RCC_APBRSTR1_UCPD1RST_Msk (0x1UL << RCC_APBRSTR1_UCPD1RST_Pos) /*!< 0x02000000 */
5291#define RCC_APBRSTR1_UCPD1RST RCC_APBRSTR1_UCPD1RST_Msk
5292#define RCC_APBRSTR1_UCPD2RST_Pos (26U)
5293#define RCC_APBRSTR1_UCPD2RST_Msk (0x1UL << RCC_APBRSTR1_UCPD2RST_Pos) /*!< 0x04000000 */
5294#define RCC_APBRSTR1_UCPD2RST RCC_APBRSTR1_UCPD2RST_Msk
5295#define RCC_APBRSTR1_DBGRST_Pos (27U)
5296#define RCC_APBRSTR1_DBGRST_Msk (0x1UL << RCC_APBRSTR1_DBGRST_Pos) /*!< 0x08000000 */
5297#define RCC_APBRSTR1_DBGRST RCC_APBRSTR1_DBGRST_Msk
5298#define RCC_APBRSTR1_PWRRST_Pos (28U)
5299#define RCC_APBRSTR1_PWRRST_Msk (0x1UL << RCC_APBRSTR1_PWRRST_Pos) /*!< 0x10000000 */
5300#define RCC_APBRSTR1_PWRRST RCC_APBRSTR1_PWRRST_Msk
5301#define RCC_APBRSTR1_DAC1RST_Pos (29U)
5302#define RCC_APBRSTR1_DAC1RST_Msk (0x1UL << RCC_APBRSTR1_DAC1RST_Pos) /*!< 0x20000000 */
5303#define RCC_APBRSTR1_DAC1RST RCC_APBRSTR1_DAC1RST_Msk
5304#define RCC_APBRSTR1_LPTIM2RST_Pos (30U)
5305#define RCC_APBRSTR1_LPTIM2RST_Msk (0x1UL << RCC_APBRSTR1_LPTIM2RST_Pos) /*!< 0x40000000 */
5306#define RCC_APBRSTR1_LPTIM2RST RCC_APBRSTR1_LPTIM2RST_Msk
5307#define RCC_APBRSTR1_LPTIM1RST_Pos (31U)
5308#define RCC_APBRSTR1_LPTIM1RST_Msk (0x1UL << RCC_APBRSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
5309#define RCC_APBRSTR1_LPTIM1RST RCC_APBRSTR1_LPTIM1RST_Msk
5310
5311/******************** Bit definition for RCC_APBRSTR2 register **************/
5312#define RCC_APBRSTR2_SYSCFGRST_Pos (0U)
5313#define RCC_APBRSTR2_SYSCFGRST_Msk (0x1UL << RCC_APBRSTR2_SYSCFGRST_Pos) /*!< 0x00000001 */
5314#define RCC_APBRSTR2_SYSCFGRST RCC_APBRSTR2_SYSCFGRST_Msk
5315#define RCC_APBRSTR2_TIM1RST_Pos (11U)
5316#define RCC_APBRSTR2_TIM1RST_Msk (0x1UL << RCC_APBRSTR2_TIM1RST_Pos) /*!< 0x00000800 */
5317#define RCC_APBRSTR2_TIM1RST RCC_APBRSTR2_TIM1RST_Msk
5318#define RCC_APBRSTR2_SPI1RST_Pos (12U)
5319#define RCC_APBRSTR2_SPI1RST_Msk (0x1UL << RCC_APBRSTR2_SPI1RST_Pos) /*!< 0x00001000 */
5320#define RCC_APBRSTR2_SPI1RST RCC_APBRSTR2_SPI1RST_Msk
5321#define RCC_APBRSTR2_USART1RST_Pos (14U)
5322#define RCC_APBRSTR2_USART1RST_Msk (0x1UL << RCC_APBRSTR2_USART1RST_Pos) /*!< 0x00004000 */
5323#define RCC_APBRSTR2_USART1RST RCC_APBRSTR2_USART1RST_Msk
5324#define RCC_APBRSTR2_TIM14RST_Pos (15U)
5325#define RCC_APBRSTR2_TIM14RST_Msk (0x1UL << RCC_APBRSTR2_TIM14RST_Pos) /*!< 0x00008000 */
5326#define RCC_APBRSTR2_TIM14RST RCC_APBRSTR2_TIM14RST_Msk
5327#define RCC_APBRSTR2_TIM15RST_Pos (16U)
5328#define RCC_APBRSTR2_TIM15RST_Msk (0x1UL << RCC_APBRSTR2_TIM15RST_Pos) /*!< 0x00010000 */
5329#define RCC_APBRSTR2_TIM15RST RCC_APBRSTR2_TIM15RST_Msk
5330#define RCC_APBRSTR2_TIM16RST_Pos (17U)
5331#define RCC_APBRSTR2_TIM16RST_Msk (0x1UL << RCC_APBRSTR2_TIM16RST_Pos) /*!< 0x00020000 */
5332#define RCC_APBRSTR2_TIM16RST RCC_APBRSTR2_TIM16RST_Msk
5333#define RCC_APBRSTR2_TIM17RST_Pos (18U)
5334#define RCC_APBRSTR2_TIM17RST_Msk (0x1UL << RCC_APBRSTR2_TIM17RST_Pos) /*!< 0x00040000 */
5335#define RCC_APBRSTR2_TIM17RST RCC_APBRSTR2_TIM17RST_Msk
5336#define RCC_APBRSTR2_ADCRST_Pos (20U)
5337#define RCC_APBRSTR2_ADCRST_Msk (0x1UL << RCC_APBRSTR2_ADCRST_Pos) /*!< 0x00100000 */
5338#define RCC_APBRSTR2_ADCRST RCC_APBRSTR2_ADCRST_Msk
5339
5340/******************** Bit definition for RCC_IOPENR register ****************/
5341#define RCC_IOPENR_GPIOAEN_Pos (0U)
5342#define RCC_IOPENR_GPIOAEN_Msk (0x1UL << RCC_IOPENR_GPIOAEN_Pos) /*!< 0x00000001 */
5343#define RCC_IOPENR_GPIOAEN RCC_IOPENR_GPIOAEN_Msk
5344#define RCC_IOPENR_GPIOBEN_Pos (1U)
5345#define RCC_IOPENR_GPIOBEN_Msk (0x1UL << RCC_IOPENR_GPIOBEN_Pos) /*!< 0x00000002 */
5346#define RCC_IOPENR_GPIOBEN RCC_IOPENR_GPIOBEN_Msk
5347#define RCC_IOPENR_GPIOCEN_Pos (2U)
5348#define RCC_IOPENR_GPIOCEN_Msk (0x1UL << RCC_IOPENR_GPIOCEN_Pos) /*!< 0x00000004 */
5349#define RCC_IOPENR_GPIOCEN RCC_IOPENR_GPIOCEN_Msk
5350#define RCC_IOPENR_GPIODEN_Pos (3U)
5351#define RCC_IOPENR_GPIODEN_Msk (0x1UL << RCC_IOPENR_GPIODEN_Pos) /*!< 0x00000008 */
5352#define RCC_IOPENR_GPIODEN RCC_IOPENR_GPIODEN_Msk
5353#define RCC_IOPENR_GPIOFEN_Pos (5U)
5354#define RCC_IOPENR_GPIOFEN_Msk (0x1UL << RCC_IOPENR_GPIOFEN_Pos) /*!< 0x00000020 */
5355#define RCC_IOPENR_GPIOFEN RCC_IOPENR_GPIOFEN_Msk
5356
5357/******************** Bit definition for RCC_AHBENR register ****************/
5358#define RCC_AHBENR_DMA1EN_Pos (0U)
5359#define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
5360#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk
5361#define RCC_AHBENR_FLASHEN_Pos (8U)
5362#define RCC_AHBENR_FLASHEN_Msk (0x1UL << RCC_AHBENR_FLASHEN_Pos) /*!< 0x00000100 */
5363#define RCC_AHBENR_FLASHEN RCC_AHBENR_FLASHEN_Msk
5364#define RCC_AHBENR_CRCEN_Pos (12U)
5365#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
5366#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk
5367#define RCC_AHBENR_AESEN_Pos (16U)
5368#define RCC_AHBENR_AESEN_Msk (0x1UL << RCC_AHBENR_AESEN_Pos) /*!< 0x00010000 */
5369#define RCC_AHBENR_AESEN RCC_AHBENR_AESEN_Msk
5370#define RCC_AHBENR_RNGEN_Pos (18U)
5371#define RCC_AHBENR_RNGEN_Msk (0x1UL << RCC_AHBENR_RNGEN_Pos) /*!< 0x00040000 */
5372#define RCC_AHBENR_RNGEN RCC_AHBENR_RNGEN_Msk
5373
5374/******************** Bit definition for RCC_APBENR1 register ***************/
5375#define RCC_APBENR1_TIM2EN_Pos (0U)
5376#define RCC_APBENR1_TIM2EN_Msk (0x1UL << RCC_APBENR1_TIM2EN_Pos) /*!< 0x00000001 */
5377#define RCC_APBENR1_TIM2EN RCC_APBENR1_TIM2EN_Msk
5378#define RCC_APBENR1_TIM3EN_Pos (1U)
5379#define RCC_APBENR1_TIM3EN_Msk (0x1UL << RCC_APBENR1_TIM3EN_Pos) /*!< 0x00000002 */
5380#define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk
5381#define RCC_APBENR1_TIM6EN_Pos (4U)
5382#define RCC_APBENR1_TIM6EN_Msk (0x1UL << RCC_APBENR1_TIM6EN_Pos) /*!< 0x00000010 */
5383#define RCC_APBENR1_TIM6EN RCC_APBENR1_TIM6EN_Msk
5384#define RCC_APBENR1_TIM7EN_Pos (5U)
5385#define RCC_APBENR1_TIM7EN_Msk (0x1UL << RCC_APBENR1_TIM7EN_Pos) /*!< 0x00000020 */
5386#define RCC_APBENR1_TIM7EN RCC_APBENR1_TIM7EN_Msk
5387#define RCC_APBENR1_RTCAPBEN_Pos (10U)
5388#define RCC_APBENR1_RTCAPBEN_Msk (0x1UL << RCC_APBENR1_RTCAPBEN_Pos) /*!< 0x00000400 */
5389#define RCC_APBENR1_RTCAPBEN RCC_APBENR1_RTCAPBEN_Msk
5390#define RCC_APBENR1_WWDGEN_Pos (11U)
5391#define RCC_APBENR1_WWDGEN_Msk (0x1UL << RCC_APBENR1_WWDGEN_Pos) /*!< 0x00000800 */
5392#define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk
5393#define RCC_APBENR1_SPI2EN_Pos (14U)
5394#define RCC_APBENR1_SPI2EN_Msk (0x1UL << RCC_APBENR1_SPI2EN_Pos) /*!< 0x00004000 */
5395#define RCC_APBENR1_SPI2EN RCC_APBENR1_SPI2EN_Msk
5396#define RCC_APBENR1_USART2EN_Pos (17U)
5397#define RCC_APBENR1_USART2EN_Msk (0x1UL << RCC_APBENR1_USART2EN_Pos) /*!< 0x00020000 */
5398#define RCC_APBENR1_USART2EN RCC_APBENR1_USART2EN_Msk
5399#define RCC_APBENR1_USART3EN_Pos (18U)
5400#define RCC_APBENR1_USART3EN_Msk (0x1UL << RCC_APBENR1_USART3EN_Pos) /*!< 0x00040000 */
5401#define RCC_APBENR1_USART3EN RCC_APBENR1_USART3EN_Msk
5402#define RCC_APBENR1_USART4EN_Pos (19U)
5403#define RCC_APBENR1_USART4EN_Msk (0x1UL << RCC_APBENR1_USART4EN_Pos) /*!< 0x00080000 */
5404#define RCC_APBENR1_USART4EN RCC_APBENR1_USART4EN_Msk
5405#define RCC_APBENR1_LPUART1EN_Pos (20U)
5406#define RCC_APBENR1_LPUART1EN_Msk (0x1UL << RCC_APBENR1_LPUART1EN_Pos) /*!< 0x00100000 */
5407#define RCC_APBENR1_LPUART1EN RCC_APBENR1_LPUART1EN_Msk
5408#define RCC_APBENR1_I2C1EN_Pos (21U)
5409#define RCC_APBENR1_I2C1EN_Msk (0x1UL << RCC_APBENR1_I2C1EN_Pos) /*!< 0x00200000 */
5410#define RCC_APBENR1_I2C1EN RCC_APBENR1_I2C1EN_Msk
5411#define RCC_APBENR1_I2C2EN_Pos (22U)
5412#define RCC_APBENR1_I2C2EN_Msk (0x1UL << RCC_APBENR1_I2C2EN_Pos) /*!< 0x00400000 */
5413#define RCC_APBENR1_I2C2EN RCC_APBENR1_I2C2EN_Msk
5414#define RCC_APBENR1_CECEN_Pos (24U)
5415#define RCC_APBENR1_CECEN_Msk (0x1UL << RCC_APBENR1_CECEN_Pos) /*!< 0x01000000 */
5416#define RCC_APBENR1_CECEN RCC_APBENR1_CECEN_Msk
5417#define RCC_APBENR1_UCPD1EN_Pos (25U)
5418#define RCC_APBENR1_UCPD1EN_Msk (0x1UL << RCC_APBENR1_UCPD1EN_Pos) /*!< 0x02000000 */
5419#define RCC_APBENR1_UCPD1EN RCC_APBENR1_UCPD1EN_Msk
5420#define RCC_APBENR1_UCPD2EN_Pos (26U)
5421#define RCC_APBENR1_UCPD2EN_Msk (0x1UL << RCC_APBENR1_UCPD2EN_Pos) /*!< 0x04000000 */
5422#define RCC_APBENR1_UCPD2EN RCC_APBENR1_UCPD2EN_Msk
5423#define RCC_APBENR1_DBGEN_Pos (27U)
5424#define RCC_APBENR1_DBGEN_Msk (0x1UL << RCC_APBENR1_DBGEN_Pos) /*!< 0x08000000 */
5425#define RCC_APBENR1_DBGEN RCC_APBENR1_DBGEN_Msk
5426#define RCC_APBENR1_PWREN_Pos (28U)
5427#define RCC_APBENR1_PWREN_Msk (0x1UL << RCC_APBENR1_PWREN_Pos) /*!< 0x10000000 */
5428#define RCC_APBENR1_PWREN RCC_APBENR1_PWREN_Msk
5429#define RCC_APBENR1_DAC1EN_Pos (29U)
5430#define RCC_APBENR1_DAC1EN_Msk (0x1UL << RCC_APBENR1_DAC1EN_Pos) /*!< 0x20000000 */
5431#define RCC_APBENR1_DAC1EN RCC_APBENR1_DAC1EN_Msk
5432#define RCC_APBENR1_LPTIM2EN_Pos (30U)
5433#define RCC_APBENR1_LPTIM2EN_Msk (0x1UL << RCC_APBENR1_LPTIM2EN_Pos) /*!< 0x40000000 */
5434#define RCC_APBENR1_LPTIM2EN RCC_APBENR1_LPTIM2EN_Msk
5435#define RCC_APBENR1_LPTIM1EN_Pos (31U)
5436#define RCC_APBENR1_LPTIM1EN_Msk (0x1UL << RCC_APBENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
5437#define RCC_APBENR1_LPTIM1EN RCC_APBENR1_LPTIM1EN_Msk
5438
5439/******************** Bit definition for RCC_APBENR2 register **************/
5440#define RCC_APBENR2_SYSCFGEN_Pos (0U)
5441#define RCC_APBENR2_SYSCFGEN_Msk (0x1UL << RCC_APBENR2_SYSCFGEN_Pos) /*!< 0x00000001 */
5442#define RCC_APBENR2_SYSCFGEN RCC_APBENR2_SYSCFGEN_Msk
5443#define RCC_APBENR2_TIM1EN_Pos (11U)
5444#define RCC_APBENR2_TIM1EN_Msk (0x1UL << RCC_APBENR2_TIM1EN_Pos) /*!< 0x00000800 */
5445#define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk
5446#define RCC_APBENR2_SPI1EN_Pos (12U)
5447#define RCC_APBENR2_SPI1EN_Msk (0x1UL << RCC_APBENR2_SPI1EN_Pos) /*!< 0x00001000 */
5448#define RCC_APBENR2_SPI1EN RCC_APBENR2_SPI1EN_Msk
5449#define RCC_APBENR2_USART1EN_Pos (14U)
5450#define RCC_APBENR2_USART1EN_Msk (0x1UL << RCC_APBENR2_USART1EN_Pos) /*!< 0x00004000 */
5451#define RCC_APBENR2_USART1EN RCC_APBENR2_USART1EN_Msk
5452#define RCC_APBENR2_TIM14EN_Pos (15U)
5453#define RCC_APBENR2_TIM14EN_Msk (0x1UL << RCC_APBENR2_TIM14EN_Pos) /*!< 0x00008000 */
5454#define RCC_APBENR2_TIM14EN RCC_APBENR2_TIM14EN_Msk
5455#define RCC_APBENR2_TIM15EN_Pos (16U)
5456#define RCC_APBENR2_TIM15EN_Msk (0x1UL << RCC_APBENR2_TIM15EN_Pos) /*!< 0x00010000 */
5457#define RCC_APBENR2_TIM15EN RCC_APBENR2_TIM15EN_Msk
5458#define RCC_APBENR2_TIM16EN_Pos (17U)
5459#define RCC_APBENR2_TIM16EN_Msk (0x1UL << RCC_APBENR2_TIM16EN_Pos) /*!< 0x00020000 */
5460#define RCC_APBENR2_TIM16EN RCC_APBENR2_TIM16EN_Msk
5461#define RCC_APBENR2_TIM17EN_Pos (18U)
5462#define RCC_APBENR2_TIM17EN_Msk (0x1UL << RCC_APBENR2_TIM17EN_Pos) /*!< 0x00040000 */
5463#define RCC_APBENR2_TIM17EN RCC_APBENR2_TIM17EN_Msk
5464#define RCC_APBENR2_ADCEN_Pos (20U)
5465#define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos) /*!< 0x00100000 */
5466#define RCC_APBENR2_ADCEN RCC_APBENR2_ADCEN_Msk
5467
5468/******************** Bit definition for RCC_IOPSMENR register *************/
5469#define RCC_IOPSMENR_GPIOASMEN_Pos (0U)
5470#define RCC_IOPSMENR_GPIOASMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
5471#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_GPIOASMEN_Msk
5472#define RCC_IOPSMENR_GPIOBSMEN_Pos (1U)
5473#define RCC_IOPSMENR_GPIOBSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
5474#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_GPIOBSMEN_Msk
5475#define RCC_IOPSMENR_GPIOCSMEN_Pos (2U)
5476#define RCC_IOPSMENR_GPIOCSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
5477#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_GPIOCSMEN_Msk
5478#define RCC_IOPSMENR_GPIODSMEN_Pos (3U)
5479#define RCC_IOPSMENR_GPIODSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIODSMEN_Pos) /*!< 0x00000008 */
5480#define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_GPIODSMEN_Msk
5481#define RCC_IOPSMENR_GPIOFSMEN_Pos (5U)
5482#define RCC_IOPSMENR_GPIOFSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOFSMEN_Pos) /*!< 0x00000020 */
5483#define RCC_IOPSMENR_GPIOFSMEN RCC_IOPSMENR_GPIOFSMEN_Msk
5484
5485/******************** Bit definition for RCC_AHBSMENR register *************/
5486#define RCC_AHBSMENR_DMA1SMEN_Pos (0U)
5487#define RCC_AHBSMENR_DMA1SMEN_Msk (0x1UL << RCC_AHBSMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
5488#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMA1SMEN_Msk
5489#define RCC_AHBSMENR_FLASHSMEN_Pos (8U)
5490#define RCC_AHBSMENR_FLASHSMEN_Msk (0x1UL << RCC_AHBSMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
5491#define RCC_AHBSMENR_FLASHSMEN RCC_AHBSMENR_FLASHSMEN_Msk
5492#define RCC_AHBSMENR_SRAMSMEN_Pos (9U)
5493#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */
5494#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk
5495#define RCC_AHBSMENR_CRCSMEN_Pos (12U)
5496#define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */
5497#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk
5498#define RCC_AHBSMENR_AESSMEN_Pos (16U)
5499#define RCC_AHBSMENR_AESSMEN_Msk (0x1UL << RCC_AHBSMENR_AESSMEN_Pos) /*!< 0x00010000 */
5500#define RCC_AHBSMENR_AESSMEN RCC_AHBSMENR_AESSMEN_Msk
5501#define RCC_AHBSMENR_RNGSMEN_Pos (18U)
5502#define RCC_AHBSMENR_RNGSMEN_Msk (0x1UL << RCC_AHBSMENR_RNGSMEN_Pos) /*!< 0x00040000 */
5503#define RCC_AHBSMENR_RNGSMEN RCC_AHBSMENR_RNGSMEN_Msk
5504
5505/******************** Bit definition for RCC_APBSMENR1 register *************/
5506#define RCC_APBSMENR1_TIM2SMEN_Pos (0U)
5507#define RCC_APBSMENR1_TIM2SMEN_Msk (0x1UL << RCC_APBSMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
5508#define RCC_APBSMENR1_TIM2SMEN RCC_APBSMENR1_TIM2SMEN_Msk
5509#define RCC_APBSMENR1_TIM3SMEN_Pos (1U)
5510#define RCC_APBSMENR1_TIM3SMEN_Msk (0x1UL << RCC_APBSMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */
5511#define RCC_APBSMENR1_TIM3SMEN RCC_APBSMENR1_TIM3SMEN_Msk
5512#define RCC_APBSMENR1_TIM6SMEN_Pos (4U)
5513#define RCC_APBSMENR1_TIM6SMEN_Msk (0x1UL << RCC_APBSMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
5514#define RCC_APBSMENR1_TIM6SMEN RCC_APBSMENR1_TIM6SMEN_Msk
5515#define RCC_APBSMENR1_TIM7SMEN_Pos (5U)
5516#define RCC_APBSMENR1_TIM7SMEN_Msk (0x1UL << RCC_APBSMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */
5517#define RCC_APBSMENR1_TIM7SMEN RCC_APBSMENR1_TIM7SMEN_Msk
5518#define RCC_APBSMENR1_RTCAPBSMEN_Pos (10U)
5519#define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
5520#define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk
5521#define RCC_APBSMENR1_WWDGSMEN_Pos (11U)
5522#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
5523#define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk
5524#define RCC_APBSMENR1_SPI2SMEN_Pos (14U)
5525#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
5526#define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk
5527#define RCC_APBSMENR1_USART2SMEN_Pos (17U)
5528#define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
5529#define RCC_APBSMENR1_USART2SMEN RCC_APBSMENR1_USART2SMEN_Msk
5530#define RCC_APBSMENR1_USART3SMEN_Pos (18U)
5531#define RCC_APBSMENR1_USART3SMEN_Msk (0x1UL << RCC_APBSMENR1_USART3SMEN_Pos) /*!< 0x00040000 */
5532#define RCC_APBSMENR1_USART3SMEN RCC_APBSMENR1_USART3SMEN_Msk
5533#define RCC_APBSMENR1_USART4SMEN_Pos (19U)
5534#define RCC_APBSMENR1_USART4SMEN_Msk (0x1UL << RCC_APBSMENR1_USART4SMEN_Pos) /*!< 0x00080000 */
5535#define RCC_APBSMENR1_USART4SMEN RCC_APBSMENR1_USART4SMEN_Msk
5536#define RCC_APBSMENR1_LPUART1SMEN_Pos (20U)
5537#define RCC_APBSMENR1_LPUART1SMEN_Msk (0x1UL << RCC_APBSMENR1_LPUART1SMEN_Pos) /*!< 0x00100000 */
5538#define RCC_APBSMENR1_LPUART1SMEN RCC_APBSMENR1_LPUART1SMEN_Msk
5539#define RCC_APBSMENR1_I2C1SMEN_Pos (21U)
5540#define RCC_APBSMENR1_I2C1SMEN_Msk (0x1UL << RCC_APBSMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
5541#define RCC_APBSMENR1_I2C1SMEN RCC_APBSMENR1_I2C1SMEN_Msk
5542#define RCC_APBSMENR1_I2C2SMEN_Pos (22U)
5543#define RCC_APBSMENR1_I2C2SMEN_Msk (0x1UL << RCC_APBSMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */
5544#define RCC_APBSMENR1_I2C2SMEN RCC_APBSMENR1_I2C2SMEN_Msk
5545#define RCC_APBSMENR1_CECSMEN_Pos (24U)
5546#define RCC_APBSMENR1_CECSMEN_Msk (0x1UL << RCC_APBSMENR1_CECSMEN_Pos) /*!< 0x01000000 */
5547#define RCC_APBSMENR1_CECSMEN RCC_APBSMENR1_CECSMEN_Msk
5548#define RCC_APBSMENR1_UCPD1SMEN_Pos (25U)
5549#define RCC_APBSMENR1_UCPD1SMEN_Msk (0x1UL << RCC_APBSMENR1_UCPD1SMEN_Pos) /*!< 0x02000000 */
5550#define RCC_APBSMENR1_UCPD1SMEN RCC_APBSMENR1_UCPD1SMEN_Msk
5551#define RCC_APBSMENR1_UCPD2SMEN_Pos (26U)
5552#define RCC_APBSMENR1_UCPD2SMEN_Msk (0x1UL << RCC_APBSMENR1_UCPD2SMEN_Pos) /*!< 0x04000000 */
5553#define RCC_APBSMENR1_UCPD2SMEN RCC_APBSMENR1_UCPD2SMEN_Msk
5554#define RCC_APBSMENR1_DBGSMEN_Pos (27U)
5555#define RCC_APBSMENR1_DBGSMEN_Msk (0x1UL << RCC_APBSMENR1_DBGSMEN_Pos) /*!< 0x08000000 */
5556#define RCC_APBSMENR1_DBGSMEN RCC_APBSMENR1_DBGSMEN_Msk
5557#define RCC_APBSMENR1_PWRSMEN_Pos (28U)
5558#define RCC_APBSMENR1_PWRSMEN_Msk (0x1UL << RCC_APBSMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
5559#define RCC_APBSMENR1_PWRSMEN RCC_APBSMENR1_PWRSMEN_Msk
5560#define RCC_APBSMENR1_DAC1SMEN_Pos (29U)
5561#define RCC_APBSMENR1_DAC1SMEN_Msk (0x1UL << RCC_APBSMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */
5562#define RCC_APBSMENR1_DAC1SMEN RCC_APBSMENR1_DAC1SMEN_Msk
5563#define RCC_APBSMENR1_LPTIM2SMEN_Pos (30U)
5564#define RCC_APBSMENR1_LPTIM2SMEN_Msk (0x1UL << RCC_APBSMENR1_LPTIM2SMEN_Pos) /*!< 0x40000000 */
5565#define RCC_APBSMENR1_LPTIM2SMEN RCC_APBSMENR1_LPTIM2SMEN_Msk
5566#define RCC_APBSMENR1_LPTIM1SMEN_Pos (31U)
5567#define RCC_APBSMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APBSMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
5568#define RCC_APBSMENR1_LPTIM1SMEN RCC_APBSMENR1_LPTIM1SMEN_Msk
5569
5570/******************** Bit definition for RCC_APBSMENR2 register *************/
5571#define RCC_APBSMENR2_SYSCFGSMEN_Pos (0U)
5572#define RCC_APBSMENR2_SYSCFGSMEN_Msk (0x1UL << RCC_APBSMENR2_SYSCFGSMEN_Pos) /*!< 0x00000001 */
5573#define RCC_APBSMENR2_SYSCFGSMEN RCC_APBSMENR2_SYSCFGSMEN_Msk
5574#define RCC_APBSMENR2_TIM1SMEN_Pos (11U)
5575#define RCC_APBSMENR2_TIM1SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM1SMEN_Pos) /*!< 0x00000800 */
5576#define RCC_APBSMENR2_TIM1SMEN RCC_APBSMENR2_TIM1SMEN_Msk
5577#define RCC_APBSMENR2_SPI1SMEN_Pos (12U)
5578#define RCC_APBSMENR2_SPI1SMEN_Msk (0x1UL << RCC_APBSMENR2_SPI1SMEN_Pos) /*!< 0x00001000 */
5579#define RCC_APBSMENR2_SPI1SMEN RCC_APBSMENR2_SPI1SMEN_Msk
5580#define RCC_APBSMENR2_USART1SMEN_Pos (14U)
5581#define RCC_APBSMENR2_USART1SMEN_Msk (0x1UL << RCC_APBSMENR2_USART1SMEN_Pos) /*!< 0x00004000 */
5582#define RCC_APBSMENR2_USART1SMEN RCC_APBSMENR2_USART1SMEN_Msk
5583#define RCC_APBSMENR2_TIM14SMEN_Pos (15U)
5584#define RCC_APBSMENR2_TIM14SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM14SMEN_Pos) /*!< 0x00008000 */
5585#define RCC_APBSMENR2_TIM14SMEN RCC_APBSMENR2_TIM14SMEN_Msk
5586#define RCC_APBSMENR2_TIM15SMEN_Pos (16U)
5587#define RCC_APBSMENR2_TIM15SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM15SMEN_Pos) /*!< 0x00010000 */
5588#define RCC_APBSMENR2_TIM15SMEN RCC_APBSMENR2_TIM15SMEN_Msk
5589#define RCC_APBSMENR2_TIM16SMEN_Pos (17U)
5590#define RCC_APBSMENR2_TIM16SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM16SMEN_Pos) /*!< 0x00020000 */
5591#define RCC_APBSMENR2_TIM16SMEN RCC_APBSMENR2_TIM16SMEN_Msk
5592#define RCC_APBSMENR2_TIM17SMEN_Pos (18U)
5593#define RCC_APBSMENR2_TIM17SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM17SMEN_Pos) /*!< 0x00040000 */
5594#define RCC_APBSMENR2_TIM17SMEN RCC_APBSMENR2_TIM17SMEN_Msk
5595#define RCC_APBSMENR2_ADCSMEN_Pos (20U)
5596#define RCC_APBSMENR2_ADCSMEN_Msk (0x1UL << RCC_APBSMENR2_ADCSMEN_Pos) /*!< 0x00100000 */
5597#define RCC_APBSMENR2_ADCSMEN RCC_APBSMENR2_ADCSMEN_Msk
5598
5599/******************** Bit definition for RCC_CCIPR register ******************/
5600#define RCC_CCIPR_USART1SEL_Pos (0U)
5601#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
5602#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
5603#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
5604#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
5605
5606#define RCC_CCIPR_USART2SEL_Pos (2U)
5607#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
5608#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
5609#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
5610#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
5611
5612#define RCC_CCIPR_CECSEL_Pos (6U)
5613#define RCC_CCIPR_CECSEL_Msk (0x1UL << RCC_CCIPR_CECSEL_Pos) /*!< 0x00000040 */
5614#define RCC_CCIPR_CECSEL RCC_CCIPR_CECSEL_Msk
5615
5616#define RCC_CCIPR_LPUART1SEL_Pos (10U)
5617#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
5618#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
5619#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
5620#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
5621
5622#define RCC_CCIPR_I2C1SEL_Pos (12U)
5623#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
5624#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
5625#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
5626#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
5627
5628#define RCC_CCIPR_I2S1SEL_Pos (14U)
5629#define RCC_CCIPR_I2S1SEL_Msk (0x3UL << RCC_CCIPR_I2S1SEL_Pos) /*!< 0x0000C000 */
5630#define RCC_CCIPR_I2S1SEL RCC_CCIPR_I2S1SEL_Msk
5631#define RCC_CCIPR_I2S1SEL_0 (0x1UL << RCC_CCIPR_I2S1SEL_Pos) /*!< 0x00004000 */
5632#define RCC_CCIPR_I2S1SEL_1 (0x2UL << RCC_CCIPR_I2S1SEL_Pos) /*!< 0x00008000 */
5633
5634#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
5635#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
5636#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
5637#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
5638#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
5639
5640#define RCC_CCIPR_LPTIM2SEL_Pos (20U)
5641#define RCC_CCIPR_LPTIM2SEL_Msk (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
5642#define RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk
5643#define RCC_CCIPR_LPTIM2SEL_0 (0x1UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
5644#define RCC_CCIPR_LPTIM2SEL_1 (0x2UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
5645
5646#define RCC_CCIPR_TIM1SEL_Pos (22U)
5647#define RCC_CCIPR_TIM1SEL_Msk (0x1UL << RCC_CCIPR_TIM1SEL_Pos) /*!< 0x00400000 */
5648#define RCC_CCIPR_TIM1SEL RCC_CCIPR_TIM1SEL_Msk
5649
5650#define RCC_CCIPR_TIM15SEL_Pos (24U)
5651#define RCC_CCIPR_TIM15SEL_Msk (0x1UL << RCC_CCIPR_TIM15SEL_Pos) /*!< 0x01000000 */
5652#define RCC_CCIPR_TIM15SEL RCC_CCIPR_TIM15SEL_Msk
5653
5654#define RCC_CCIPR_RNGSEL_Pos (26U)
5655#define RCC_CCIPR_RNGSEL_Msk (0x3UL << RCC_CCIPR_RNGSEL_Pos) /*!< 0x0C000000 */
5656#define RCC_CCIPR_RNGSEL RCC_CCIPR_RNGSEL_Msk
5657#define RCC_CCIPR_RNGSEL_0 (0x1UL << RCC_CCIPR_RNGSEL_Pos) /*!< 0x04000000 */
5658#define RCC_CCIPR_RNGSEL_1 (0x2UL << RCC_CCIPR_RNGSEL_Pos) /*!< 0x08000000 */
5659
5660#define RCC_CCIPR_RNGDIV_Pos (28U)
5661#define RCC_CCIPR_RNGDIV_Msk (0x3UL << RCC_CCIPR_RNGDIV_Pos) /*!< 0x30000000 */
5662#define RCC_CCIPR_RNGDIV RCC_CCIPR_RNGDIV_Msk
5663#define RCC_CCIPR_RNGDIV_0 (0x1UL << RCC_CCIPR_RNGDIV_Pos) /*!< 0x10000000 */
5664#define RCC_CCIPR_RNGDIV_1 (0x2UL << RCC_CCIPR_RNGDIV_Pos) /*!< 0x20000000 */
5665
5666#define RCC_CCIPR_ADCSEL_Pos (30U)
5667#define RCC_CCIPR_ADCSEL_Msk (0x3UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0xC0000000 */
5668#define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk
5669#define RCC_CCIPR_ADCSEL_0 (0x1UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x40000000 */
5670#define RCC_CCIPR_ADCSEL_1 (0x2UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x80000000 */
5671
5672/******************** Bit definition for RCC_BDCR register ******************/
5673#define RCC_BDCR_LSEON_Pos (0U)
5674#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
5675#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
5676#define RCC_BDCR_LSERDY_Pos (1U)
5677#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
5678#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
5679#define RCC_BDCR_LSEBYP_Pos (2U)
5680#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
5681#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
5682
5683#define RCC_BDCR_LSEDRV_Pos (3U)
5684#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
5685#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
5686#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
5687#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
5688
5689#define RCC_BDCR_LSECSSON_Pos (5U)
5690#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
5691#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
5692#define RCC_BDCR_LSECSSD_Pos (6U)
5693#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
5694#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
5695
5696#define RCC_BDCR_RTCSEL_Pos (8U)
5697#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
5698#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
5699#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
5700#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
5701
5702#define RCC_BDCR_RTCEN_Pos (15U)
5703#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
5704#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
5705#define RCC_BDCR_BDRST_Pos (16U)
5706#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
5707#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
5708
5709#define RCC_BDCR_LSCOEN_Pos (24U)
5710#define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
5711#define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
5712#define RCC_BDCR_LSCOSEL_Pos (25U)
5713#define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
5714#define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
5715
5716/******************** Bit definition for RCC_CSR register *******************/
5717#define RCC_CSR_LSION_Pos (0U)
5718#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
5719#define RCC_CSR_LSION RCC_CSR_LSION_Msk
5720#define RCC_CSR_LSIRDY_Pos (1U)
5721#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
5722#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
5723
5724#define RCC_CSR_RMVF_Pos (23U)
5725#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
5726#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
5727#define RCC_CSR_OBLRSTF_Pos (25U)
5728#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
5729#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
5730#define RCC_CSR_PINRSTF_Pos (26U)
5731#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
5732#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
5733#define RCC_CSR_PWRRSTF_Pos (27U)
5734#define RCC_CSR_PWRRSTF_Msk (0x1UL << RCC_CSR_PWRRSTF_Pos) /*!< 0x08000000 */
5735#define RCC_CSR_PWRRSTF RCC_CSR_PWRRSTF_Msk
5736#define RCC_CSR_SFTRSTF_Pos (28U)
5737#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
5738#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
5739#define RCC_CSR_IWDGRSTF_Pos (29U)
5740#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
5741#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
5742#define RCC_CSR_WWDGRSTF_Pos (30U)
5743#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
5744#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
5745#define RCC_CSR_LPWRRSTF_Pos (31U)
5746#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
5747#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
5748
5749/******************************************************************************/
5750/* */
5751/* RNG */
5752/* */
5753/******************************************************************************/
5754/******************** Bits definition for RNG_CR register *******************/
5755#define RNG_CR_RNGEN_Pos (2U)
5756#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
5757#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
5758#define RNG_CR_IE_Pos (3U)
5759#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
5760#define RNG_CR_IE RNG_CR_IE_Msk
5761#define RNG_CR_CED_Pos (5U)
5762#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
5763#define RNG_CR_CED RNG_CR_CED_Msk
5764
5765/******************** Bits definition for RNG_SR register *******************/
5766#define RNG_SR_DRDY_Pos (0U)
5767#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
5768#define RNG_SR_DRDY RNG_SR_DRDY_Msk
5769#define RNG_SR_CECS_Pos (1U)
5770#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
5771#define RNG_SR_CECS RNG_SR_CECS_Msk
5772#define RNG_SR_SECS_Pos (2U)
5773#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
5774#define RNG_SR_SECS RNG_SR_SECS_Msk
5775#define RNG_SR_CEIS_Pos (5U)
5776#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
5777#define RNG_SR_CEIS RNG_SR_CEIS_Msk
5778#define RNG_SR_SEIS_Pos (6U)
5779#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
5780#define RNG_SR_SEIS RNG_SR_SEIS_Msk
5781
5782/******************************************************************************/
5783/* */
5784/* Real-Time Clock (RTC) */
5785/* */
5786/******************************************************************************/
5787/*
5788* @brief Specific device feature definitions
5789*/
5790#define RTC_WAKEUP_SUPPORT
5791#define RTC_BACKUP_SUPPORT
5792
5793/******************** Bits definition for RTC_TR register *******************/
5794#define RTC_TR_PM_Pos (22U)
5795#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
5796#define RTC_TR_PM RTC_TR_PM_Msk
5797#define RTC_TR_HT_Pos (20U)
5798#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
5799#define RTC_TR_HT RTC_TR_HT_Msk
5800#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
5801#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
5802#define RTC_TR_HU_Pos (16U)
5803#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
5804#define RTC_TR_HU RTC_TR_HU_Msk
5805#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
5806#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
5807#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
5808#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
5809#define RTC_TR_MNT_Pos (12U)
5810#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
5811#define RTC_TR_MNT RTC_TR_MNT_Msk
5812#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
5813#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
5814#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
5815#define RTC_TR_MNU_Pos (8U)
5816#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
5817#define RTC_TR_MNU RTC_TR_MNU_Msk
5818#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
5819#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
5820#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
5821#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
5822#define RTC_TR_ST_Pos (4U)
5823#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
5824#define RTC_TR_ST RTC_TR_ST_Msk
5825#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
5826#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
5827#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
5828#define RTC_TR_SU_Pos (0U)
5829#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
5830#define RTC_TR_SU RTC_TR_SU_Msk
5831#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
5832#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
5833#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
5834#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
5835
5836/******************** Bits definition for RTC_DR register *******************/
5837#define RTC_DR_YT_Pos (20U)
5838#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
5839#define RTC_DR_YT RTC_DR_YT_Msk
5840#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
5841#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
5842#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
5843#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
5844#define RTC_DR_YU_Pos (16U)
5845#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
5846#define RTC_DR_YU RTC_DR_YU_Msk
5847#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
5848#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
5849#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
5850#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
5851#define RTC_DR_WDU_Pos (13U)
5852#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
5853#define RTC_DR_WDU RTC_DR_WDU_Msk
5854#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
5855#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
5856#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
5857#define RTC_DR_MT_Pos (12U)
5858#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
5859#define RTC_DR_MT RTC_DR_MT_Msk
5860#define RTC_DR_MU_Pos (8U)
5861#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
5862#define RTC_DR_MU RTC_DR_MU_Msk
5863#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
5864#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
5865#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
5866#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
5867#define RTC_DR_DT_Pos (4U)
5868#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
5869#define RTC_DR_DT RTC_DR_DT_Msk
5870#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
5871#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
5872#define RTC_DR_DU_Pos (0U)
5873#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
5874#define RTC_DR_DU RTC_DR_DU_Msk
5875#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
5876#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
5877#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
5878#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
5879
5880/******************** Bits definition for RTC_SSR register ******************/
5881#define RTC_SSR_SS_Pos (0U)
5882#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
5883#define RTC_SSR_SS RTC_SSR_SS_Msk
5884
5885/******************** Bits definition for RTC_ICSR register ******************/
5886#define RTC_ICSR_RECALPF_Pos (16U)
5887#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */
5888#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk
5889#define RTC_ICSR_INIT_Pos (7U)
5890#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */
5891#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk
5892#define RTC_ICSR_INITF_Pos (6U)
5893#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */
5894#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk
5895#define RTC_ICSR_RSF_Pos (5U)
5896#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */
5897#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk
5898#define RTC_ICSR_INITS_Pos (4U)
5899#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */
5900#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk
5901#define RTC_ICSR_SHPF_Pos (3U)
5902#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */
5903#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk
5904#define RTC_ICSR_WUTWF_Pos (2U)
5905#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */
5906#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk /*!< Wakeup timer write flag > */
5907#define RTC_ICSR_ALRBWF_Pos (1U)
5908#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */
5909#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk
5910#define RTC_ICSR_ALRAWF_Pos (0U)
5911#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */
5912#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk
5913
5914/******************** Bits definition for RTC_PRER register *****************/
5915#define RTC_PRER_PREDIV_A_Pos (16U)
5916#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
5917#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
5918#define RTC_PRER_PREDIV_S_Pos (0U)
5919#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
5920#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
5921
5922/******************** Bits definition for RTC_WUTR register *****************/
5923#define RTC_WUTR_WUT_Pos (0U)
5924#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
5925#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wakeup auto-reload value bits > */
5926
5927/******************** Bits definition for RTC_CR register *******************/
5928#define RTC_CR_OUT2EN_Pos (31U)
5929#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */
5930#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!< RTC_OUT2 output enable */
5931#define RTC_CR_TAMPALRM_TYPE_Pos (30U)
5932#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */
5933#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!< TAMPALARM output type */
5934#define RTC_CR_TAMPALRM_PU_Pos (29U)
5935#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */
5936#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!< TAMPALARM output pull-up config */
5937#define RTC_CR_TAMPOE_Pos (26U)
5938#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */
5939#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!< Tamper detection output enable on TAMPALARM */
5940#define RTC_CR_TAMPTS_Pos (25U)
5941#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */
5942#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!< Activate timestamp on tamper detection event */
5943#define RTC_CR_ITSE_Pos (24U)
5944#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
5945#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!< Timestamp on internal event enable */
5946#define RTC_CR_COE_Pos (23U)
5947#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
5948#define RTC_CR_COE RTC_CR_COE_Msk
5949#define RTC_CR_OSEL_Pos (21U)
5950#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
5951#define RTC_CR_OSEL RTC_CR_OSEL_Msk
5952#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
5953#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
5954#define RTC_CR_POL_Pos (20U)
5955#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
5956#define RTC_CR_POL RTC_CR_POL_Msk
5957#define RTC_CR_COSEL_Pos (19U)
5958#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
5959#define RTC_CR_COSEL RTC_CR_COSEL_Msk
5960#define RTC_CR_BKP_Pos (18U)
5961#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
5962#define RTC_CR_BKP RTC_CR_BKP_Msk
5963#define RTC_CR_SUB1H_Pos (17U)
5964#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
5965#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
5966#define RTC_CR_ADD1H_Pos (16U)
5967#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
5968#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
5969#define RTC_CR_TSIE_Pos (15U)
5970#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
5971#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable > */
5972#define RTC_CR_WUTIE_Pos (14U)
5973#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
5974#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wakeup timer interrupt enable > */
5975#define RTC_CR_ALRBIE_Pos (13U)
5976#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
5977#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
5978#define RTC_CR_ALRAIE_Pos (12U)
5979#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
5980#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
5981#define RTC_CR_TSE_Pos (11U)
5982#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
5983#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable > */
5984#define RTC_CR_WUTE_Pos (10U)
5985#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
5986#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wakeup timer enable > */
5987#define RTC_CR_ALRBE_Pos (9U)
5988#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
5989#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
5990#define RTC_CR_ALRAE_Pos (8U)
5991#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
5992#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
5993#define RTC_CR_FMT_Pos (6U)
5994#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
5995#define RTC_CR_FMT RTC_CR_FMT_Msk
5996#define RTC_CR_BYPSHAD_Pos (5U)
5997#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
5998#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
5999#define RTC_CR_REFCKON_Pos (4U)
6000#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
6001#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
6002#define RTC_CR_TSEDGE_Pos (3U)
6003#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
6004#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge > */
6005#define RTC_CR_WUCKSEL_Pos (0U)
6006#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
6007#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< Wakeup clock selection > */
6008#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
6009#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
6010#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
6011
6012/******************** Bits definition for RTC_WPR register ******************/
6013#define RTC_WPR_KEY_Pos (0U)
6014#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
6015#define RTC_WPR_KEY RTC_WPR_KEY_Msk
6016
6017/******************** Bits definition for RTC_CALR register *****************/
6018#define RTC_CALR_CALP_Pos (15U)
6019#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
6020#define RTC_CALR_CALP RTC_CALR_CALP_Msk
6021#define RTC_CALR_CALW8_Pos (14U)
6022#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
6023#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
6024#define RTC_CALR_CALW16_Pos (13U)
6025#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
6026#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
6027#define RTC_CALR_CALM_Pos (0U)
6028#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
6029#define RTC_CALR_CALM RTC_CALR_CALM_Msk
6030#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
6031#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
6032#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
6033#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
6034#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
6035#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
6036#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
6037#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
6038#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
6039
6040/******************** Bits definition for RTC_SHIFTR register ***************/
6041#define RTC_SHIFTR_SUBFS_Pos (0U)
6042#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
6043#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
6044#define RTC_SHIFTR_ADD1S_Pos (31U)
6045#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
6046#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
6047
6048/******************** Bits definition for RTC_TSTR register *****************/
6049#define RTC_TSTR_PM_Pos (22U)
6050#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
6051#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< AM-PM notation > */
6052#define RTC_TSTR_HT_Pos (20U)
6053#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
6054#define RTC_TSTR_HT RTC_TSTR_HT_Msk
6055#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
6056#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
6057#define RTC_TSTR_HU_Pos (16U)
6058#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
6059#define RTC_TSTR_HU RTC_TSTR_HU_Msk
6060#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
6061#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
6062#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
6063#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
6064#define RTC_TSTR_MNT_Pos (12U)
6065#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
6066#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
6067#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
6068#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
6069#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
6070#define RTC_TSTR_MNU_Pos (8U)
6071#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
6072#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
6073#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
6074#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
6075#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
6076#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
6077#define RTC_TSTR_ST_Pos (4U)
6078#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
6079#define RTC_TSTR_ST RTC_TSTR_ST_Msk
6080#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
6081#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
6082#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
6083#define RTC_TSTR_SU_Pos (0U)
6084#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
6085#define RTC_TSTR_SU RTC_TSTR_SU_Msk
6086#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
6087#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
6088#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
6089#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
6090
6091/******************** Bits definition for RTC_TSDR register *****************/
6092#define RTC_TSDR_WDU_Pos (13U)
6093#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
6094#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Week day units > */
6095#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
6096#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
6097#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
6098#define RTC_TSDR_MT_Pos (12U)
6099#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
6100#define RTC_TSDR_MT RTC_TSDR_MT_Msk
6101#define RTC_TSDR_MU_Pos (8U)
6102#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
6103#define RTC_TSDR_MU RTC_TSDR_MU_Msk
6104#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
6105#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
6106#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
6107#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
6108#define RTC_TSDR_DT_Pos (4U)
6109#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
6110#define RTC_TSDR_DT RTC_TSDR_DT_Msk
6111#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
6112#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
6113#define RTC_TSDR_DU_Pos (0U)
6114#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
6115#define RTC_TSDR_DU RTC_TSDR_DU_Msk
6116#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
6117#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
6118#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
6119#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
6120
6121/******************** Bits definition for RTC_TSSSR register ****************/
6122#define RTC_TSSSR_SS_Pos (0U)
6123#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
6124#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Sub second value > */
6125
6126/******************** Bits definition for RTC_ALRMAR register ***************/
6127#define RTC_ALRMAR_MSK4_Pos (31U)
6128#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
6129#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
6130#define RTC_ALRMAR_WDSEL_Pos (30U)
6131#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
6132#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
6133#define RTC_ALRMAR_DT_Pos (28U)
6134#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
6135#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
6136#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
6137#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
6138#define RTC_ALRMAR_DU_Pos (24U)
6139#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
6140#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
6141#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
6142#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
6143#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
6144#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
6145#define RTC_ALRMAR_MSK3_Pos (23U)
6146#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
6147#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
6148#define RTC_ALRMAR_PM_Pos (22U)
6149#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
6150#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
6151#define RTC_ALRMAR_HT_Pos (20U)
6152#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
6153#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
6154#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
6155#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
6156#define RTC_ALRMAR_HU_Pos (16U)
6157#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
6158#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
6159#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
6160#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
6161#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
6162#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
6163#define RTC_ALRMAR_MSK2_Pos (15U)
6164#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
6165#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
6166#define RTC_ALRMAR_MNT_Pos (12U)
6167#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
6168#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
6169#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
6170#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
6171#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
6172#define RTC_ALRMAR_MNU_Pos (8U)
6173#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
6174#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
6175#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
6176#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
6177#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
6178#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
6179#define RTC_ALRMAR_MSK1_Pos (7U)
6180#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
6181#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
6182#define RTC_ALRMAR_ST_Pos (4U)
6183#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
6184#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
6185#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
6186#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
6187#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
6188#define RTC_ALRMAR_SU_Pos (0U)
6189#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
6190#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
6191#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
6192#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
6193#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
6194#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
6195
6196/******************** Bits definition for RTC_ALRMASSR register *************/
6197#define RTC_ALRMASSR_MASKSS_Pos (24U)
6198#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
6199#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
6200#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
6201#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
6202#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
6203#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
6204#define RTC_ALRMASSR_SS_Pos (0U)
6205#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
6206#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
6207
6208/******************** Bits definition for RTC_ALRMBR register ***************/
6209#define RTC_ALRMBR_MSK4_Pos (31U)
6210#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
6211#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
6212#define RTC_ALRMBR_WDSEL_Pos (30U)
6213#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
6214#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
6215#define RTC_ALRMBR_DT_Pos (28U)
6216#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
6217#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
6218#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
6219#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
6220#define RTC_ALRMBR_DU_Pos (24U)
6221#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
6222#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
6223#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
6224#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
6225#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
6226#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
6227#define RTC_ALRMBR_MSK3_Pos (23U)
6228#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
6229#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
6230#define RTC_ALRMBR_PM_Pos (22U)
6231#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
6232#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
6233#define RTC_ALRMBR_HT_Pos (20U)
6234#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
6235#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
6236#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
6237#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
6238#define RTC_ALRMBR_HU_Pos (16U)
6239#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
6240#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
6241#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
6242#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
6243#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
6244#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
6245#define RTC_ALRMBR_MSK2_Pos (15U)
6246#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
6247#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
6248#define RTC_ALRMBR_MNT_Pos (12U)
6249#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
6250#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
6251#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
6252#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
6253#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
6254#define RTC_ALRMBR_MNU_Pos (8U)
6255#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
6256#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
6257#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
6258#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
6259#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
6260#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
6261#define RTC_ALRMBR_MSK1_Pos (7U)
6262#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
6263#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
6264#define RTC_ALRMBR_ST_Pos (4U)
6265#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
6266#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
6267#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
6268#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
6269#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
6270#define RTC_ALRMBR_SU_Pos (0U)
6271#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
6272#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
6273#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
6274#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
6275#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
6276#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
6277
6278/******************** Bits definition for RTC_ALRMASSR register *************/
6279#define RTC_ALRMBSSR_MASKSS_Pos (24U)
6280#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
6281#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
6282#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
6283#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
6284#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
6285#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
6286#define RTC_ALRMBSSR_SS_Pos (0U)
6287#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
6288#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
6289
6290/******************** Bits definition for RTC_SR register *******************/
6291#define RTC_SR_ITSF_Pos (5U)
6292#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */
6293#define RTC_SR_ITSF RTC_SR_ITSF_Msk
6294#define RTC_SR_TSOVF_Pos (4U)
6295#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */
6296#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk /*!< Timestamp overflow flag > */
6297#define RTC_SR_TSF_Pos (3U)
6298#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */
6299#define RTC_SR_TSF RTC_SR_TSF_Msk /*!< Timestamp flag > */
6300#define RTC_SR_WUTF_Pos (2U)
6301#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */
6302#define RTC_SR_WUTF RTC_SR_WUTF_Msk /*!< Wakeup timer flag > */
6303#define RTC_SR_ALRBF_Pos (1U)
6304#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */
6305#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk
6306#define RTC_SR_ALRAF_Pos (0U)
6307#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */
6308#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk
6309
6310/******************** Bits definition for RTC_MISR register *****************/
6311#define RTC_MISR_ITSMF_Pos (5U)
6312#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */
6313#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk
6314#define RTC_MISR_TSOVMF_Pos (4U)
6315#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */
6316#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk /*!< Timestamp overflow masked flag > */
6317#define RTC_MISR_TSMF_Pos (3U)
6318#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */
6319#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk /*!< Timestamp masked flag > */
6320#define RTC_MISR_WUTMF_Pos (2U)
6321#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */
6322#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk /*!< Wakeup timer masked flag > */
6323#define RTC_MISR_ALRBMF_Pos (1U)
6324#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */
6325#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk
6326#define RTC_MISR_ALRAMF_Pos (0U)
6327#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */
6328#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk
6329
6330/******************** Bits definition for RTC_SCR register ******************/
6331#define RTC_SCR_CITSF_Pos (5U)
6332#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */
6333#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk
6334#define RTC_SCR_CTSOVF_Pos (4U)
6335#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */
6336#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk /*!< Clear timestamp overflow flag > */
6337#define RTC_SCR_CTSF_Pos (3U)
6338#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */
6339#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk /*!< Clear timestamp flag > */
6340#define RTC_SCR_CWUTF_Pos (2U)
6341#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */
6342#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk /*!< Clear wakeup timer flag > */
6343#define RTC_SCR_CALRBF_Pos (1U)
6344#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */
6345#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk
6346#define RTC_SCR_CALRAF_Pos (0U)
6347#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
6348#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
6349
6350
6351/******************************************************************************/
6352/* */
6353/* Tamper and backup register (TAMP) */
6354/* */
6355/******************************************************************************/
6356/******************** Bits definition for TAMP_CR1 register *****************/
6357#define TAMP_CR1_TAMP1E_Pos (0U)
6358#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */
6359#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk
6360#define TAMP_CR1_TAMP2E_Pos (1U)
6361#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */
6362#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk
6363#define TAMP_CR1_ITAMP3E_Pos (18U)
6364#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */
6365#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk
6366#define TAMP_CR1_ITAMP4E_Pos (19U)
6367#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */
6368#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk
6369#define TAMP_CR1_ITAMP5E_Pos (20U)
6370#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */
6371#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk
6372#define TAMP_CR1_ITAMP6E_Pos (21U)
6373#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */
6374#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk
6375
6376/******************** Bits definition for TAMP_CR2 register *****************/
6377#define TAMP_CR2_TAMP1NOERASE_Pos (0U)
6378#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */
6379#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk
6380#define TAMP_CR2_TAMP2NOERASE_Pos (1U)
6381#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */
6382#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk
6383#define TAMP_CR2_TAMP1MSK_Pos (16U)
6384#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */
6385#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk
6386#define TAMP_CR2_TAMP2MSK_Pos (17U)
6387#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */
6388#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk
6389#define TAMP_CR2_TAMP1TRG_Pos (24U)
6390#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */
6391#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk
6392#define TAMP_CR2_TAMP2TRG_Pos (25U)
6393#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */
6394#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk
6395
6396/******************** Bits definition for TAMP_FLTCR register ***************/
6397#define TAMP_FLTCR_TAMPFREQ_0 0x00000001U
6398#define TAMP_FLTCR_TAMPFREQ_1 0x00000002U
6399#define TAMP_FLTCR_TAMPFREQ_2 0x00000004U
6400#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
6401#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
6402#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
6403#define TAMP_FLTCR_TAMPFLT_0 0x00000008U
6404#define TAMP_FLTCR_TAMPFLT_1 0x00000010U
6405#define TAMP_FLTCR_TAMPFLT_Pos (3U)
6406#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
6407#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
6408#define TAMP_FLTCR_TAMPPRCH_0 0x00000020U
6409#define TAMP_FLTCR_TAMPPRCH_1 0x00000040U
6410#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
6411#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
6412#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
6413#define TAMP_FLTCR_TAMPPUDIS_Pos (7U)
6414#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */
6415#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk
6416
6417/******************** Bits definition for TAMP_IER register *****************/
6418#define TAMP_IER_TAMP1IE_Pos (0U)
6419#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */
6420#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk
6421#define TAMP_IER_TAMP2IE_Pos (1U)
6422#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */
6423#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk
6424#define TAMP_IER_ITAMP3IE_Pos (18U)
6425#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */
6426#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk
6427#define TAMP_IER_ITAMP4IE_Pos (19U)
6428#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */
6429#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk
6430#define TAMP_IER_ITAMP5IE_Pos (20U)
6431#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */
6432#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk
6433#define TAMP_IER_ITAMP6IE_Pos (21U)
6434#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */
6435#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk
6436
6437/******************** Bits definition for TAMP_SR register ******************/
6438#define TAMP_SR_TAMP1F_Pos (0U)
6439#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */
6440#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk
6441#define TAMP_SR_TAMP2F_Pos (1U)
6442#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */
6443#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk
6444#define TAMP_SR_ITAMP3F_Pos (18U)
6445#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */
6446#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk
6447#define TAMP_SR_ITAMP4F_Pos (19U)
6448#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */
6449#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk
6450#define TAMP_SR_ITAMP5F_Pos (20U)
6451#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */
6452#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk
6453#define TAMP_SR_ITAMP6F_Pos (21U)
6454#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */
6455#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk
6456
6457/******************** Bits definition for TAMP_MISR register ****************/
6458#define TAMP_MISR_TAMP1MF_Pos (0U)
6459#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */
6460#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk
6461#define TAMP_MISR_TAMP2MF_Pos (1U)
6462#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */
6463#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk
6464#define TAMP_MISR_ITAMP3MF_Pos (18U)
6465#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */
6466#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk
6467#define TAMP_MISR_ITAMP4MF_Pos (19U)
6468#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */
6469#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk
6470#define TAMP_MISR_ITAMP5MF_Pos (20U)
6471#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */
6472#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk
6473#define TAMP_MISR_ITAMP6MF_Pos (21U)
6474#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */
6475#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk
6476
6477/******************** Bits definition for TAMP_SCR register *****************/
6478#define TAMP_SCR_CTAMP1F_Pos (0U)
6479#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */
6480#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk
6481#define TAMP_SCR_CTAMP2F_Pos (1U)
6482#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */
6483#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk
6484#define TAMP_SCR_CITAMP3F_Pos (18U)
6485#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */
6486#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk
6487#define TAMP_SCR_CITAMP4F_Pos (19U)
6488#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */
6489#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk
6490#define TAMP_SCR_CITAMP5F_Pos (20U)
6491#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */
6492#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk
6493#define TAMP_SCR_CITAMP6F_Pos (21U)
6494#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */
6495#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk
6496
6497/******************** Bits definition for TAMP_BKP0R register ***************/
6498#define TAMP_BKP0R_Pos (0U)
6499#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */
6500#define TAMP_BKP0R TAMP_BKP0R_Msk
6501
6502/******************** Bits definition for TAMP_BKP1R register ***************/
6503#define TAMP_BKP1R_Pos (0U)
6504#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */
6505#define TAMP_BKP1R TAMP_BKP1R_Msk
6506
6507/******************** Bits definition for TAMP_BKP2R register ***************/
6508#define TAMP_BKP2R_Pos (0U)
6509#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */
6510#define TAMP_BKP2R TAMP_BKP2R_Msk
6511
6512/******************** Bits definition for TAMP_BKP3R register ***************/
6513#define TAMP_BKP3R_Pos (0U)
6514#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */
6515#define TAMP_BKP3R TAMP_BKP3R_Msk
6516
6517/******************** Bits definition for TAMP_BKP4R register ***************/
6518#define TAMP_BKP4R_Pos (0U)
6519#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
6520#define TAMP_BKP4R TAMP_BKP4R_Msk
6521
6522
6523/******************************************************************************/
6524/* */
6525/* Serial Peripheral Interface (SPI) */
6526/* */
6527/******************************************************************************/
6528/*
6529 * @brief Specific device feature definitions (not present on all devices in the STM32G0 serie)
6530 */
6531#define SPI_I2S_SUPPORT /*!< I2S support */
6532
6533/******************* Bit definition for SPI_CR1 register ********************/
6534#define SPI_CR1_CPHA_Pos (0U)
6535#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
6536#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
6537#define SPI_CR1_CPOL_Pos (1U)
6538#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
6539#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
6540#define SPI_CR1_MSTR_Pos (2U)
6541#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
6542#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
6543
6544#define SPI_CR1_BR_Pos (3U)
6545#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
6546#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
6547#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
6548#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
6549#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
6550
6551#define SPI_CR1_SPE_Pos (6U)
6552#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
6553#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
6554#define SPI_CR1_LSBFIRST_Pos (7U)
6555#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
6556#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
6557#define SPI_CR1_SSI_Pos (8U)
6558#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
6559#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
6560#define SPI_CR1_SSM_Pos (9U)
6561#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
6562#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
6563#define SPI_CR1_RXONLY_Pos (10U)
6564#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
6565#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
6566#define SPI_CR1_CRCL_Pos (11U)
6567#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
6568#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
6569#define SPI_CR1_CRCNEXT_Pos (12U)
6570#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
6571#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
6572#define SPI_CR1_CRCEN_Pos (13U)
6573#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
6574#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
6575#define SPI_CR1_BIDIOE_Pos (14U)
6576#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
6577#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
6578#define SPI_CR1_BIDIMODE_Pos (15U)
6579#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
6580#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
6581
6582/******************* Bit definition for SPI_CR2 register ********************/
6583#define SPI_CR2_RXDMAEN_Pos (0U)
6584#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
6585#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
6586#define SPI_CR2_TXDMAEN_Pos (1U)
6587#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
6588#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
6589#define SPI_CR2_SSOE_Pos (2U)
6590#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
6591#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
6592#define SPI_CR2_NSSP_Pos (3U)
6593#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
6594#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
6595#define SPI_CR2_FRF_Pos (4U)
6596#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
6597#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
6598#define SPI_CR2_ERRIE_Pos (5U)
6599#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
6600#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
6601#define SPI_CR2_RXNEIE_Pos (6U)
6602#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
6603#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
6604#define SPI_CR2_TXEIE_Pos (7U)
6605#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
6606#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
6607#define SPI_CR2_DS_Pos (8U)
6608#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
6609#define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
6610#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */
6611#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */
6612#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */
6613#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */
6614#define SPI_CR2_FRXTH_Pos (12U)
6615#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
6616#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
6617#define SPI_CR2_LDMARX_Pos (13U)
6618#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
6619#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
6620#define SPI_CR2_LDMATX_Pos (14U)
6621#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
6622#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
6623
6624/******************** Bit definition for SPI_SR register ********************/
6625#define SPI_SR_RXNE_Pos (0U)
6626#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
6627#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
6628#define SPI_SR_TXE_Pos (1U)
6629#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
6630#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
6631#define SPI_SR_CHSIDE_Pos (2U)
6632#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
6633#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
6634#define SPI_SR_UDR_Pos (3U)
6635#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
6636#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
6637#define SPI_SR_CRCERR_Pos (4U)
6638#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
6639#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
6640#define SPI_SR_MODF_Pos (5U)
6641#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
6642#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
6643#define SPI_SR_OVR_Pos (6U)
6644#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
6645#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
6646#define SPI_SR_BSY_Pos (7U)
6647#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
6648#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
6649#define SPI_SR_FRE_Pos (8U)
6650#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
6651#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
6652#define SPI_SR_FRLVL_Pos (9U)
6653#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
6654#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
6655#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
6656#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
6657#define SPI_SR_FTLVL_Pos (11U)
6658#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
6659#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
6660#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
6661#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
6662
6663/******************** Bit definition for SPI_DR register ********************/
6664#define SPI_DR_DR_Pos (0U)
6665#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
6666#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
6667
6668/******************* Bit definition for SPI_CRCPR register ******************/
6669#define SPI_CRCPR_CRCPOLY_Pos (0U)
6670#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
6671#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
6672
6673/****************** Bit definition for SPI_RXCRCR register ******************/
6674#define SPI_RXCRCR_RXCRC_Pos (0U)
6675#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
6676#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
6677
6678/****************** Bit definition for SPI_TXCRCR register ******************/
6679#define SPI_TXCRCR_TXCRC_Pos (0U)
6680#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
6681#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
6682
6683/****************** Bit definition for SPI_I2SCFGR register *****************/
6684#define SPI_I2SCFGR_CHLEN_Pos (0U)
6685#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
6686#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
6687#define SPI_I2SCFGR_DATLEN_Pos (1U)
6688#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
6689#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
6690#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
6691#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
6692#define SPI_I2SCFGR_CKPOL_Pos (3U)
6693#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
6694#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
6695#define SPI_I2SCFGR_I2SSTD_Pos (4U)
6696#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
6697#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
6698#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
6699#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
6700#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
6701#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
6702#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
6703#define SPI_I2SCFGR_I2SCFG_Pos (8U)
6704#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
6705#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
6706#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
6707#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
6708#define SPI_I2SCFGR_I2SE_Pos (10U)
6709#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
6710#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
6711#define SPI_I2SCFGR_I2SMOD_Pos (11U)
6712#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
6713#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
6714#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
6715#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
6716#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
6717
6718/****************** Bit definition for SPI_I2SPR register *******************/
6719#define SPI_I2SPR_I2SDIV_Pos (0U)
6720#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
6721#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
6722#define SPI_I2SPR_ODD_Pos (8U)
6723#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
6724#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
6725#define SPI_I2SPR_MCKOE_Pos (9U)
6726#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
6727#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
6728
6729/******************************************************************************/
6730/* */
6731/* SYSCFG */
6732/* */
6733/******************************************************************************/
6734/***************** Bit definition for SYSCFG_CFGR1 register ****************/
6735#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
6736#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
6737#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
6738#define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
6739#define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
6740#define SYSCFG_CFGR1_PA11_RMP_Pos (3U)
6741#define SYSCFG_CFGR1_PA11_RMP_Msk (0x1UL << SYSCFG_CFGR1_PA11_RMP_Pos) /*!< 0x00000008 */
6742#define SYSCFG_CFGR1_PA11_RMP SYSCFG_CFGR1_PA11_RMP_Msk /*!< PA11 Remap */
6743#define SYSCFG_CFGR1_PA12_RMP_Pos (4U)
6744#define SYSCFG_CFGR1_PA12_RMP_Msk (0x1UL << SYSCFG_CFGR1_PA12_RMP_Pos) /*!< 0x00000010 */
6745#define SYSCFG_CFGR1_PA12_RMP SYSCFG_CFGR1_PA12_RMP_Msk /*!< PA12 Remap */
6746#define SYSCFG_CFGR1_IR_POL_Pos (5U)
6747#define SYSCFG_CFGR1_IR_POL_Msk (0x1UL << SYSCFG_CFGR1_IR_POL_Pos) /*!< 0x00000020 */
6748#define SYSCFG_CFGR1_IR_POL SYSCFG_CFGR1_IR_POL_Msk /*!< IROut Polarity Selection */
6749#define SYSCFG_CFGR1_IR_MOD_Pos (6U)
6750#define SYSCFG_CFGR1_IR_MOD_Msk (0x3UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x000000C0 */
6751#define SYSCFG_CFGR1_IR_MOD SYSCFG_CFGR1_IR_MOD_Msk /*!< IRDA Modulation Envelope signal source selection */
6752#define SYSCFG_CFGR1_IR_MOD_0 (0x1UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000040 */
6753#define SYSCFG_CFGR1_IR_MOD_1 (0x2UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000080 */
6754#define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
6755#define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
6756#define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
6757#define SYSCFG_CFGR1_UCPD1_STROBE_Pos (9U)
6758#define SYSCFG_CFGR1_UCPD1_STROBE_Msk (0x1UL << SYSCFG_CFGR1_UCPD1_STROBE_Pos) /*!< 0x00000200 */
6759#define SYSCFG_CFGR1_UCPD1_STROBE SYSCFG_CFGR1_UCPD1_STROBE_Msk /*!< Strobe signal bit for UCPD1 */
6760#define SYSCFG_CFGR1_UCPD2_STROBE_Pos (10U)
6761#define SYSCFG_CFGR1_UCPD2_STROBE_Msk (0x1UL << SYSCFG_CFGR1_UCPD2_STROBE_Pos) /*!< 0x00000400 */
6762#define SYSCFG_CFGR1_UCPD2_STROBE SYSCFG_CFGR1_UCPD2_STROBE_Msk /*!< Strobe signal bit for UCPD2 */
6763#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
6764#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
6765#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
6766#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
6767#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
6768#define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
6769#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
6770#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
6771#define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
6772#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
6773#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
6774#define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
6775#define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
6776#define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
6777#define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
6778#define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
6779#define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
6780#define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< Enable I2C2 Fast mode plus */
6781#define SYSCFG_CFGR1_I2C_PA9_FMP_Pos (22U)
6782#define SYSCFG_CFGR1_I2C_PA9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PA9_FMP_Pos) /*!< 0x00400000 */
6783#define SYSCFG_CFGR1_I2C_PA9_FMP SYSCFG_CFGR1_I2C_PA9_FMP_Msk /*!< Enable Fast Mode Plus on PA9 */
6784#define SYSCFG_CFGR1_I2C_PA10_FMP_Pos (23U)
6785#define SYSCFG_CFGR1_I2C_PA10_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PA10_FMP_Pos) /*!< 0x00800000 */
6786#define SYSCFG_CFGR1_I2C_PA10_FMP SYSCFG_CFGR1_I2C_PA10_FMP_Msk /*!< Enable Fast Mode Plus on PA10 */
6787
6788/****************** Bit definition for SYSCFG_CFGR2 register ****************/
6789#define SYSCFG_CFGR2_CLL_Pos (0U)
6790#define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
6791#define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
6792#define SYSCFG_CFGR2_SPL_Pos (1U)
6793#define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
6794#define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
6795#define SYSCFG_CFGR2_PVDL_Pos (2U)
6796#define SYSCFG_CFGR2_PVDL_Msk (0x1UL << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */
6797#define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
6798#define SYSCFG_CFGR2_ECCL_Pos (3U)
6799#define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
6800#define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECCL */
6801#define SYSCFG_CFGR2_SPF_Pos (8U)
6802#define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
6803#define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity error flag */
6804#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SPF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
6805
6806/***************** Bit definition for SYSCFG_ITLINEx ISR Wrapper register ****************/
6807#define SYSCFG_ITLINE0_SR_EWDG_Pos (0U)
6808#define SYSCFG_ITLINE0_SR_EWDG_Msk (0x1UL << SYSCFG_ITLINE0_SR_EWDG_Pos) /*!< 0x00000001 */
6809#define SYSCFG_ITLINE0_SR_EWDG SYSCFG_ITLINE0_SR_EWDG_Msk /*!< EWDG interrupt */
6810#define SYSCFG_ITLINE1_SR_PVDOUT_Pos (0U)
6811#define SYSCFG_ITLINE1_SR_PVDOUT_Msk (0x1UL << SYSCFG_ITLINE1_SR_PVDOUT_Pos) /*!< 0x00000001 */
6812#define SYSCFG_ITLINE1_SR_PVDOUT SYSCFG_ITLINE1_SR_PVDOUT_Msk /*!< Power voltage detection -> exti[16] Interrupt */
6813#define SYSCFG_ITLINE2_SR_TAMPER_Pos (0U)
6814#define SYSCFG_ITLINE2_SR_TAMPER_Msk (0x1UL << SYSCFG_ITLINE2_SR_TAMPER_Pos) /*!< 0x00000001 */
6815#define SYSCFG_ITLINE2_SR_TAMPER SYSCFG_ITLINE2_SR_TAMPER_Msk /*!< TAMPER -> exti[21] interrupt */
6816#define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos (1U)
6817#define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk (0x1UL << SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos) /*!< 0x00000002 */
6818#define SYSCFG_ITLINE2_SR_RTC_WAKEUP SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk /*!< RTC_WAKEUP -> exti[19] interrupt .... */
6819#define SYSCFG_ITLINE3_SR_FLASH_ECC_Pos (0U)
6820#define SYSCFG_ITLINE3_SR_FLASH_ECC_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ECC_Pos) /*!< 0x00000001 */
6821#define SYSCFG_ITLINE3_SR_FLASH_ECC SYSCFG_ITLINE3_SR_FLASH_ECC_Msk /*!< Flash ITF ECC interrupt */
6822#define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos (1U)
6823#define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000002 */
6824#define SYSCFG_ITLINE3_SR_FLASH_ITF SYSCFG_ITLINE3_SR_FLASH_ITF_Msk /*!< FLASH ITF interrupt */
6825#define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos (0U)
6826#define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk (0x1UL << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos) /*!< 0x00000001 */
6827#define SYSCFG_ITLINE4_SR_CLK_CTRL SYSCFG_ITLINE4_SR_CLK_CTRL_Msk /*!< RCC interrupt */
6828#define SYSCFG_ITLINE5_SR_EXTI0_Pos (0U)
6829#define SYSCFG_ITLINE5_SR_EXTI0_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */
6830#define SYSCFG_ITLINE5_SR_EXTI0 SYSCFG_ITLINE5_SR_EXTI0_Msk /*!< External Interrupt 0 */
6831#define SYSCFG_ITLINE5_SR_EXTI1_Pos (1U)
6832#define SYSCFG_ITLINE5_SR_EXTI1_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI1_Pos) /*!< 0x00000002 */
6833#define SYSCFG_ITLINE5_SR_EXTI1 SYSCFG_ITLINE5_SR_EXTI1_Msk /*!< External Interrupt 1 */
6834#define SYSCFG_ITLINE6_SR_EXTI2_Pos (0U)
6835#define SYSCFG_ITLINE6_SR_EXTI2_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI2_Pos) /*!< 0x00000001 */
6836#define SYSCFG_ITLINE6_SR_EXTI2 SYSCFG_ITLINE6_SR_EXTI2_Msk /*!< External Interrupt 2 */
6837#define SYSCFG_ITLINE6_SR_EXTI3_Pos (1U)
6838#define SYSCFG_ITLINE6_SR_EXTI3_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI3_Pos) /*!< 0x00000002 */
6839#define SYSCFG_ITLINE6_SR_EXTI3 SYSCFG_ITLINE6_SR_EXTI3_Msk /*!< External Interrupt 3 */
6840#define SYSCFG_ITLINE7_SR_EXTI4_Pos (0U)
6841#define SYSCFG_ITLINE7_SR_EXTI4_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI4_Pos) /*!< 0x00000001 */
6842#define SYSCFG_ITLINE7_SR_EXTI4 SYSCFG_ITLINE7_SR_EXTI4_Msk /*!< External Interrupt 4 */
6843#define SYSCFG_ITLINE7_SR_EXTI5_Pos (1U)
6844#define SYSCFG_ITLINE7_SR_EXTI5_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI5_Pos) /*!< 0x00000002 */
6845#define SYSCFG_ITLINE7_SR_EXTI5 SYSCFG_ITLINE7_SR_EXTI5_Msk /*!< External Interrupt 5 */
6846#define SYSCFG_ITLINE7_SR_EXTI6_Pos (2U)
6847#define SYSCFG_ITLINE7_SR_EXTI6_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI6_Pos) /*!< 0x00000004 */
6848#define SYSCFG_ITLINE7_SR_EXTI6 SYSCFG_ITLINE7_SR_EXTI6_Msk /*!< External Interrupt 6 */
6849#define SYSCFG_ITLINE7_SR_EXTI7_Pos (3U)
6850#define SYSCFG_ITLINE7_SR_EXTI7_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI7_Pos) /*!< 0x00000008 */
6851#define SYSCFG_ITLINE7_SR_EXTI7 SYSCFG_ITLINE7_SR_EXTI7_Msk /*!< External Interrupt 7 */
6852#define SYSCFG_ITLINE7_SR_EXTI8_Pos (4U)
6853#define SYSCFG_ITLINE7_SR_EXTI8_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI8_Pos) /*!< 0x00000010 */
6854#define SYSCFG_ITLINE7_SR_EXTI8 SYSCFG_ITLINE7_SR_EXTI8_Msk /*!< External Interrupt 8 */
6855#define SYSCFG_ITLINE7_SR_EXTI9_Pos (5U)
6856#define SYSCFG_ITLINE7_SR_EXTI9_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI9_Pos) /*!< 0x00000020 */
6857#define SYSCFG_ITLINE7_SR_EXTI9 SYSCFG_ITLINE7_SR_EXTI9_Msk /*!< External Interrupt 9 */
6858#define SYSCFG_ITLINE7_SR_EXTI10_Pos (6U)
6859#define SYSCFG_ITLINE7_SR_EXTI10_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI10_Pos) /*!< 0x00000040 */
6860#define SYSCFG_ITLINE7_SR_EXTI10 SYSCFG_ITLINE7_SR_EXTI10_Msk /*!< External Interrupt 10 */
6861#define SYSCFG_ITLINE7_SR_EXTI11_Pos (7U)
6862#define SYSCFG_ITLINE7_SR_EXTI11_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI11_Pos) /*!< 0x00000080 */
6863#define SYSCFG_ITLINE7_SR_EXTI11 SYSCFG_ITLINE7_SR_EXTI11_Msk /*!< External Interrupt 11 */
6864#define SYSCFG_ITLINE7_SR_EXTI12_Pos (8U)
6865#define SYSCFG_ITLINE7_SR_EXTI12_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI12_Pos) /*!< 0x00000100 */
6866#define SYSCFG_ITLINE7_SR_EXTI12 SYSCFG_ITLINE7_SR_EXTI12_Msk /*!< External Interrupt 12 */
6867#define SYSCFG_ITLINE7_SR_EXTI13_Pos (9U)
6868#define SYSCFG_ITLINE7_SR_EXTI13_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI13_Pos) /*!< 0x00000200 */
6869#define SYSCFG_ITLINE7_SR_EXTI13 SYSCFG_ITLINE7_SR_EXTI13_Msk /*!< External Interrupt 13 */
6870#define SYSCFG_ITLINE7_SR_EXTI14_Pos (10U)
6871#define SYSCFG_ITLINE7_SR_EXTI14_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI14_Pos) /*!< 0x00000400 */
6872#define SYSCFG_ITLINE7_SR_EXTI14 SYSCFG_ITLINE7_SR_EXTI14_Msk /*!< External Interrupt 14 */
6873#define SYSCFG_ITLINE7_SR_EXTI15_Pos (11U)
6874#define SYSCFG_ITLINE7_SR_EXTI15_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI15_Pos) /*!< 0x00000800 */
6875#define SYSCFG_ITLINE7_SR_EXTI15 SYSCFG_ITLINE7_SR_EXTI15_Msk /*!< External Interrupt 15 */
6876#define SYSCFG_ITLINE8_SR_UCPD1_Pos (0U)
6877#define SYSCFG_ITLINE8_SR_UCPD1_Msk (0x1UL << SYSCFG_ITLINE8_SR_UCPD1_Pos) /*!< 0x00000001 */
6878#define SYSCFG_ITLINE8_SR_UCPD1 SYSCFG_ITLINE8_SR_UCPD1_Msk /*!< UCPD1 -> exti[32] Interrupt */
6879#define SYSCFG_ITLINE8_SR_UCPD2_Pos (1U)
6880#define SYSCFG_ITLINE8_SR_UCPD2_Msk (0x1UL << SYSCFG_ITLINE8_SR_UCPD2_Pos) /*!< 0x00000002 */
6881#define SYSCFG_ITLINE8_SR_UCPD2 SYSCFG_ITLINE8_SR_UCPD2_Msk /*!< UCPD2 -> exti[33] Interrupt */
6882#define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos (0U)
6883#define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk (0x1UL << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos) /*!< 0x00000001 */
6884#define SYSCFG_ITLINE9_SR_DMA1_CH1 SYSCFG_ITLINE9_SR_DMA1_CH1_Msk /*!< DMA1 Channel 1 Interrupt */
6885#define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos (0U)
6886#define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos) /*!< 0x00000001 */
6887#define SYSCFG_ITLINE10_SR_DMA1_CH2 SYSCFG_ITLINE10_SR_DMA1_CH2_Msk /*!< DMA1 Channel 2 Interrupt */
6888#define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U)
6889#define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */
6890#define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA2 Channel 3 Interrupt */
6891#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U)
6892#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */
6893#define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */
6894#define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos (1U)
6895#define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000002 */
6896#define SYSCFG_ITLINE11_SR_DMA1_CH4 SYSCFG_ITLINE11_SR_DMA1_CH4_Msk /*!< DMA1 Channel 4 Interrupt */
6897#define SYSCFG_ITLINE11_SR_DMA1_CH5_Pos (2U)
6898#define SYSCFG_ITLINE11_SR_DMA1_CH5_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos) /*!< 0x00000004 */
6899#define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 Interrupt */
6900#define SYSCFG_ITLINE11_SR_DMA1_CH6_Pos (3U)
6901#define SYSCFG_ITLINE11_SR_DMA1_CH6_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH6_Pos) /*!< 0x00000008 */
6902#define SYSCFG_ITLINE11_SR_DMA1_CH6 SYSCFG_ITLINE11_SR_DMA1_CH6_Msk /*!< DMA1 Channel 6 Interrupt */
6903#define SYSCFG_ITLINE11_SR_DMA1_CH7_Pos (4U)
6904#define SYSCFG_ITLINE11_SR_DMA1_CH7_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH7_Pos) /*!< 0x00000010 */
6905#define SYSCFG_ITLINE11_SR_DMA1_CH7 SYSCFG_ITLINE11_SR_DMA1_CH7_Msk /*!< DMA1 Channel 7 Interrupt */
6906#define SYSCFG_ITLINE12_SR_ADC_Pos (0U)
6907#define SYSCFG_ITLINE12_SR_ADC_Msk (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */
6908#define SYSCFG_ITLINE12_SR_ADC SYSCFG_ITLINE12_SR_ADC_Msk /*!< ADC Interrupt */
6909#define SYSCFG_ITLINE12_SR_COMP1_Pos (1U)
6910#define SYSCFG_ITLINE12_SR_COMP1_Msk (0x1UL << SYSCFG_ITLINE12_SR_COMP1_Pos) /*!< 0x00000002 */
6911#define SYSCFG_ITLINE12_SR_COMP1 SYSCFG_ITLINE12_SR_COMP1_Msk /*!< COMP1 Interrupt -> exti[17] */
6912#define SYSCFG_ITLINE12_SR_COMP2_Pos (2U)
6913#define SYSCFG_ITLINE12_SR_COMP2_Msk (0x1UL << SYSCFG_ITLINE12_SR_COMP2_Pos) /*!< 0x00000004 */
6914#define SYSCFG_ITLINE12_SR_COMP2 SYSCFG_ITLINE12_SR_COMP2_Msk /*!< COMP2 Interrupt -> exti[18] */
6915#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0U)
6916#define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */
6917#define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */
6918#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1U)
6919#define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */
6920#define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */
6921#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2U)
6922#define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */
6923#define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */
6924#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3U)
6925#define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */
6926#define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */
6927#define SYSCFG_ITLINE14_SR_TIM1_CC_Pos (0U)
6928#define SYSCFG_ITLINE14_SR_TIM1_CC_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC_Pos) /*!< 0x00000001 */
6929#define SYSCFG_ITLINE14_SR_TIM1_CC SYSCFG_ITLINE14_SR_TIM1_CC_Msk /*!< TIM1 CC Interrupt */
6930#define SYSCFG_ITLINE15_SR_TIM2_GLB_Pos (0U)
6931#define SYSCFG_ITLINE15_SR_TIM2_GLB_Msk (0x1UL << SYSCFG_ITLINE15_SR_TIM2_GLB_Pos) /*!< 0x00000001 */
6932#define SYSCFG_ITLINE15_SR_TIM2_GLB SYSCFG_ITLINE15_SR_TIM2_GLB_Msk /*!< TIM2 GLB Interrupt */
6933#define SYSCFG_ITLINE16_SR_TIM3_GLB_Pos (0U)
6934#define SYSCFG_ITLINE16_SR_TIM3_GLB_Msk (0x1UL << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos) /*!< 0x00000001 */
6935#define SYSCFG_ITLINE16_SR_TIM3_GLB SYSCFG_ITLINE16_SR_TIM3_GLB_Msk /*!< TIM3 GLB Interrupt */
6936#define SYSCFG_ITLINE17_SR_TIM6_GLB_Pos (0U)
6937#define SYSCFG_ITLINE17_SR_TIM6_GLB_Msk (0x1UL << SYSCFG_ITLINE17_SR_TIM6_GLB_Pos) /*!< 0x00000001 */
6938#define SYSCFG_ITLINE17_SR_TIM6_GLB SYSCFG_ITLINE17_SR_TIM6_GLB_Msk /*!< TIM6 GLB Interrupt */
6939#define SYSCFG_ITLINE17_SR_DAC_Pos (1U)
6940#define SYSCFG_ITLINE17_SR_DAC_Msk (0x1UL << SYSCFG_ITLINE17_SR_DAC_Pos) /*!< 0x00000002 */
6941#define SYSCFG_ITLINE17_SR_DAC SYSCFG_ITLINE17_SR_DAC_Msk /*!< DAC Interrupt */
6942#define SYSCFG_ITLINE17_SR_LPTIM1_GLB_Pos (2U)
6943#define SYSCFG_ITLINE17_SR_LPTIM1_GLB_Msk (0x1UL << SYSCFG_ITLINE17_SR_LPTIM1_GLB_Pos) /*!< 0x00000004 */
6944#define SYSCFG_ITLINE17_SR_LPTIM1_GLB SYSCFG_ITLINE17_SR_LPTIM1_GLB_Msk /*!< LPTIM1 -> exti[29] Interrupt */
6945#define SYSCFG_ITLINE18_SR_TIM7_GLB_Pos (0U)
6946#define SYSCFG_ITLINE18_SR_TIM7_GLB_Msk (0x1UL << SYSCFG_ITLINE18_SR_TIM7_GLB_Pos) /*!< 0x00000001 */
6947#define SYSCFG_ITLINE18_SR_TIM7_GLB SYSCFG_ITLINE18_SR_TIM7_GLB_Msk /*!< TIM7 GLB Interrupt */
6948#define SYSCFG_ITLINE18_SR_LPTIM2_GLB_Pos (1U)
6949#define SYSCFG_ITLINE18_SR_LPTIM2_GLB_Msk (0x1UL << SYSCFG_ITLINE18_SR_LPTIM2_GLB_Pos) /*!< 0x00000002 */
6950#define SYSCFG_ITLINE18_SR_LPTIM2_GLB SYSCFG_ITLINE18_SR_LPTIM2_GLB_Msk /*!< LPTIM2 -> exti[30] Interrupt */
6951#define SYSCFG_ITLINE19_SR_TIM14_GLB_Pos (0U)
6952#define SYSCFG_ITLINE19_SR_TIM14_GLB_Msk (0x1UL << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos) /*!< 0x00000001 */
6953#define SYSCFG_ITLINE19_SR_TIM14_GLB SYSCFG_ITLINE19_SR_TIM14_GLB_Msk /*!< TIM14 GLB Interrupt */
6954#define SYSCFG_ITLINE20_SR_TIM15_GLB_Pos (0U)
6955#define SYSCFG_ITLINE20_SR_TIM15_GLB_Msk (0x1UL << SYSCFG_ITLINE20_SR_TIM15_GLB_Pos) /*!< 0x00000001 */
6956#define SYSCFG_ITLINE20_SR_TIM15_GLB SYSCFG_ITLINE20_SR_TIM15_GLB_Msk /*!< TIM15 GLB Interrupt */
6957#define SYSCFG_ITLINE21_SR_TIM16_GLB_Pos (0U)
6958#define SYSCFG_ITLINE21_SR_TIM16_GLB_Msk (0x1UL << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos) /*!< 0x00000001 */
6959#define SYSCFG_ITLINE21_SR_TIM16_GLB SYSCFG_ITLINE21_SR_TIM16_GLB_Msk /*!< TIM16 GLB Interrupt */
6960#define SYSCFG_ITLINE22_SR_TIM17_GLB_Pos (0U)
6961#define SYSCFG_ITLINE22_SR_TIM17_GLB_Msk (0x1UL << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos) /*!< 0x00000001 */
6962#define SYSCFG_ITLINE22_SR_TIM17_GLB SYSCFG_ITLINE22_SR_TIM17_GLB_Msk /*!< TIM17 GLB Interrupt */
6963#define SYSCFG_ITLINE23_SR_I2C1_GLB_Pos (0U)
6964#define SYSCFG_ITLINE23_SR_I2C1_GLB_Msk (0x1UL << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos) /*!< 0x00000001 */
6965#define SYSCFG_ITLINE23_SR_I2C1_GLB SYSCFG_ITLINE23_SR_I2C1_GLB_Msk /*!< I2C1 GLB Interrupt -> exti[23] */
6966#define SYSCFG_ITLINE24_SR_I2C2_GLB_Pos (0U)
6967#define SYSCFG_ITLINE24_SR_I2C2_GLB_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C2_GLB_Pos) /*!< 0x00000001 */
6968#define SYSCFG_ITLINE24_SR_I2C2_GLB SYSCFG_ITLINE24_SR_I2C2_GLB_Msk /*!< I2C2 GLB Interrupt */
6969#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U)
6970#define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */
6971#define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */
6972#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U)
6973#define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */
6974#define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */
6975#define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U)
6976#define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */
6977#define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt -> exti[25] */
6978#define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U)
6979#define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */
6980#define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt -> exti[26] */
6981#define SYSCFG_ITLINE29_SR_USART3_GLB_Pos (0U)
6982#define SYSCFG_ITLINE29_SR_USART3_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART3_GLB_Pos) /*!< 0x00000001 */
6983#define SYSCFG_ITLINE29_SR_USART3_GLB SYSCFG_ITLINE29_SR_USART3_GLB_Msk /*!< USART3 GLB Interrupt */
6984#define SYSCFG_ITLINE29_SR_USART4_GLB_Pos (1U)
6985#define SYSCFG_ITLINE29_SR_USART4_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART4_GLB_Pos) /*!< 0x00000002 */
6986#define SYSCFG_ITLINE29_SR_USART4_GLB SYSCFG_ITLINE29_SR_USART4_GLB_Msk /*!< USART4 GLB Interrupt */
6987#define SYSCFG_ITLINE29_SR_LPUART1_GLB_Pos (2U)
6988#define SYSCFG_ITLINE29_SR_LPUART1_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_LPUART1_GLB_Pos) /*!< 0x00000004 */
6989#define SYSCFG_ITLINE29_SR_LPUART1_GLB SYSCFG_ITLINE29_SR_LPUART1_GLB_Msk /*!< LPUART1 GLB Interrupt -> exti[28] */
6990#define SYSCFG_ITLINE30_SR_CEC_Pos (0U)
6991#define SYSCFG_ITLINE30_SR_CEC_Msk (0x1UL << SYSCFG_ITLINE30_SR_CEC_Pos) /*!< 0x00000001 */
6992#define SYSCFG_ITLINE30_SR_CEC SYSCFG_ITLINE30_SR_CEC_Msk /*!< CEC Interrupt-> exti[27] */
6993#define SYSCFG_ITLINE31_SR_RNG_Pos (0U)
6994#define SYSCFG_ITLINE31_SR_RNG_Msk (0x1UL << SYSCFG_ITLINE31_SR_RNG_Pos) /*!< 0x00000001 */
6995#define SYSCFG_ITLINE31_SR_RNG SYSCFG_ITLINE31_SR_RNG_Msk /*!< RNG Interrupt */
6996#define SYSCFG_ITLINE31_SR_AES_Pos (1U)
6997#define SYSCFG_ITLINE31_SR_AES_Msk (0x1UL << SYSCFG_ITLINE31_SR_AES_Pos) /*!< 0x00000002 */
6998#define SYSCFG_ITLINE31_SR_AES SYSCFG_ITLINE31_SR_AES_Msk /*!< AES Interrupt */
6999
7000/******************************************************************************/
7001/* */
7002/* TIM */
7003/* */
7004/******************************************************************************/
7005/******************* Bit definition for TIM_CR1 register ********************/
7006#define TIM_CR1_CEN_Pos (0U)
7007#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
7008#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
7009#define TIM_CR1_UDIS_Pos (1U)
7010#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
7011#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
7012#define TIM_CR1_URS_Pos (2U)
7013#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
7014#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
7015#define TIM_CR1_OPM_Pos (3U)
7016#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
7017#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
7018#define TIM_CR1_DIR_Pos (4U)
7019#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
7020#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
7021
7022#define TIM_CR1_CMS_Pos (5U)
7023#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
7024#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
7025#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
7026#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
7027
7028#define TIM_CR1_ARPE_Pos (7U)
7029#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
7030#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
7031
7032#define TIM_CR1_CKD_Pos (8U)
7033#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
7034#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
7035#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
7036#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
7037
7038#define TIM_CR1_UIFREMAP_Pos (11U)
7039#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
7040#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
7041
7042/******************* Bit definition for TIM_CR2 register ********************/
7043#define TIM_CR2_CCPC_Pos (0U)
7044#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
7045#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
7046#define TIM_CR2_CCUS_Pos (2U)
7047#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
7048#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
7049#define TIM_CR2_CCDS_Pos (3U)
7050#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
7051#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
7052
7053#define TIM_CR2_MMS_Pos (4U)
7054#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
7055#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
7056#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
7057#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
7058#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
7059
7060#define TIM_CR2_TI1S_Pos (7U)
7061#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
7062#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
7063#define TIM_CR2_OIS1_Pos (8U)
7064#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
7065#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
7066#define TIM_CR2_OIS1N_Pos (9U)
7067#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
7068#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
7069#define TIM_CR2_OIS2_Pos (10U)
7070#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
7071#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
7072#define TIM_CR2_OIS2N_Pos (11U)
7073#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
7074#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
7075#define TIM_CR2_OIS3_Pos (12U)
7076#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
7077#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
7078#define TIM_CR2_OIS3N_Pos (13U)
7079#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
7080#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
7081#define TIM_CR2_OIS4_Pos (14U)
7082#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
7083#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
7084#define TIM_CR2_OIS5_Pos (16U)
7085#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
7086#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
7087#define TIM_CR2_OIS6_Pos (18U)
7088#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
7089#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
7090
7091#define TIM_CR2_MMS2_Pos (20U)
7092#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
7093#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
7094#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
7095#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
7096#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
7097#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
7098
7099/******************* Bit definition for TIM_SMCR register *******************/
7100#define TIM_SMCR_SMS_Pos (0U)
7101#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
7102#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
7103#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
7104#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
7105#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
7106#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
7107
7108#define TIM_SMCR_OCCS_Pos (3U)
7109#define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
7110#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
7111
7112#define TIM_SMCR_TS_Pos (4U)
7113#define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */
7114#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
7115#define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
7116#define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
7117#define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
7118#define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */
7119#define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */
7120
7121#define TIM_SMCR_MSM_Pos (7U)
7122#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
7123#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
7124
7125#define TIM_SMCR_ETF_Pos (8U)
7126#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
7127#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
7128#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
7129#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
7130#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
7131#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
7132
7133#define TIM_SMCR_ETPS_Pos (12U)
7134#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
7135#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
7136#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
7137#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
7138
7139#define TIM_SMCR_ECE_Pos (14U)
7140#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
7141#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
7142#define TIM_SMCR_ETP_Pos (15U)
7143#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
7144#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
7145
7146/******************* Bit definition for TIM_DIER register *******************/
7147#define TIM_DIER_UIE_Pos (0U)
7148#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
7149#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
7150#define TIM_DIER_CC1IE_Pos (1U)
7151#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
7152#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
7153#define TIM_DIER_CC2IE_Pos (2U)
7154#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
7155#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
7156#define TIM_DIER_CC3IE_Pos (3U)
7157#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
7158#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
7159#define TIM_DIER_CC4IE_Pos (4U)
7160#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
7161#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
7162#define TIM_DIER_COMIE_Pos (5U)
7163#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
7164#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
7165#define TIM_DIER_TIE_Pos (6U)
7166#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
7167#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
7168#define TIM_DIER_BIE_Pos (7U)
7169#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
7170#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
7171#define TIM_DIER_UDE_Pos (8U)
7172#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
7173#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
7174#define TIM_DIER_CC1DE_Pos (9U)
7175#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
7176#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
7177#define TIM_DIER_CC2DE_Pos (10U)
7178#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
7179#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
7180#define TIM_DIER_CC3DE_Pos (11U)
7181#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
7182#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
7183#define TIM_DIER_CC4DE_Pos (12U)
7184#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
7185#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
7186#define TIM_DIER_COMDE_Pos (13U)
7187#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
7188#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
7189#define TIM_DIER_TDE_Pos (14U)
7190#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
7191#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
7192
7193/******************** Bit definition for TIM_SR register ********************/
7194#define TIM_SR_UIF_Pos (0U)
7195#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
7196#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
7197#define TIM_SR_CC1IF_Pos (1U)
7198#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
7199#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
7200#define TIM_SR_CC2IF_Pos (2U)
7201#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
7202#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
7203#define TIM_SR_CC3IF_Pos (3U)
7204#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
7205#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
7206#define TIM_SR_CC4IF_Pos (4U)
7207#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
7208#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
7209#define TIM_SR_COMIF_Pos (5U)
7210#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
7211#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
7212#define TIM_SR_TIF_Pos (6U)
7213#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
7214#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
7215#define TIM_SR_BIF_Pos (7U)
7216#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
7217#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
7218#define TIM_SR_B2IF_Pos (8U)
7219#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
7220#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
7221#define TIM_SR_CC1OF_Pos (9U)
7222#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
7223#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
7224#define TIM_SR_CC2OF_Pos (10U)
7225#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
7226#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
7227#define TIM_SR_CC3OF_Pos (11U)
7228#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
7229#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
7230#define TIM_SR_CC4OF_Pos (12U)
7231#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
7232#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
7233#define TIM_SR_SBIF_Pos (13U)
7234#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
7235#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
7236#define TIM_SR_CC5IF_Pos (16U)
7237#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
7238#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
7239#define TIM_SR_CC6IF_Pos (17U)
7240#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
7241#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
7242
7243
7244/******************* Bit definition for TIM_EGR register ********************/
7245#define TIM_EGR_UG_Pos (0U)
7246#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
7247#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
7248#define TIM_EGR_CC1G_Pos (1U)
7249#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
7250#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
7251#define TIM_EGR_CC2G_Pos (2U)
7252#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
7253#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
7254#define TIM_EGR_CC3G_Pos (3U)
7255#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
7256#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
7257#define TIM_EGR_CC4G_Pos (4U)
7258#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
7259#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
7260#define TIM_EGR_COMG_Pos (5U)
7261#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
7262#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
7263#define TIM_EGR_TG_Pos (6U)
7264#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
7265#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
7266#define TIM_EGR_BG_Pos (7U)
7267#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
7268#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
7269#define TIM_EGR_B2G_Pos (8U)
7270#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
7271#define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
7272
7273
7274/****************** Bit definition for TIM_CCMR1 register *******************/
7275#define TIM_CCMR1_CC1S_Pos (0U)
7276#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
7277#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
7278#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
7279#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
7280
7281#define TIM_CCMR1_OC1FE_Pos (2U)
7282#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
7283#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
7284#define TIM_CCMR1_OC1PE_Pos (3U)
7285#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
7286#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
7287
7288#define TIM_CCMR1_OC1M_Pos (4U)
7289#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
7290#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
7291#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
7292#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
7293#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
7294#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
7295
7296#define TIM_CCMR1_OC1CE_Pos (7U)
7297#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
7298#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
7299
7300#define TIM_CCMR1_CC2S_Pos (8U)
7301#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
7302#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
7303#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
7304#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
7305
7306#define TIM_CCMR1_OC2FE_Pos (10U)
7307#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
7308#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
7309#define TIM_CCMR1_OC2PE_Pos (11U)
7310#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
7311#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
7312
7313#define TIM_CCMR1_OC2M_Pos (12U)
7314#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
7315#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
7316#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
7317#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
7318#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
7319#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
7320
7321#define TIM_CCMR1_OC2CE_Pos (15U)
7322#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
7323#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
7324
7325/*----------------------------------------------------------------------------*/
7326#define TIM_CCMR1_IC1PSC_Pos (2U)
7327#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
7328#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
7329#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
7330#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
7331
7332#define TIM_CCMR1_IC1F_Pos (4U)
7333#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
7334#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
7335#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
7336#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
7337#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
7338#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
7339
7340#define TIM_CCMR1_IC2PSC_Pos (10U)
7341#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
7342#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
7343#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
7344#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
7345
7346#define TIM_CCMR1_IC2F_Pos (12U)
7347#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
7348#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
7349#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
7350#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
7351#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
7352#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
7353
7354/****************** Bit definition for TIM_CCMR2 register *******************/
7355#define TIM_CCMR2_CC3S_Pos (0U)
7356#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
7357#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
7358#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
7359#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
7360
7361#define TIM_CCMR2_OC3FE_Pos (2U)
7362#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
7363#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
7364#define TIM_CCMR2_OC3PE_Pos (3U)
7365#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
7366#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
7367
7368#define TIM_CCMR2_OC3M_Pos (4U)
7369#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
7370#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
7371#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
7372#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
7373#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
7374#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
7375
7376#define TIM_CCMR2_OC3CE_Pos (7U)
7377#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
7378#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
7379
7380#define TIM_CCMR2_CC4S_Pos (8U)
7381#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
7382#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
7383#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
7384#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
7385
7386#define TIM_CCMR2_OC4FE_Pos (10U)
7387#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
7388#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
7389#define TIM_CCMR2_OC4PE_Pos (11U)
7390#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
7391#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
7392
7393#define TIM_CCMR2_OC4M_Pos (12U)
7394#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
7395#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
7396#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
7397#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
7398#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
7399#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
7400
7401#define TIM_CCMR2_OC4CE_Pos (15U)
7402#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
7403#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
7404
7405/*----------------------------------------------------------------------------*/
7406#define TIM_CCMR2_IC3PSC_Pos (2U)
7407#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
7408#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
7409#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
7410#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
7411
7412#define TIM_CCMR2_IC3F_Pos (4U)
7413#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
7414#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
7415#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
7416#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
7417#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
7418#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
7419
7420#define TIM_CCMR2_IC4PSC_Pos (10U)
7421#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
7422#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
7423#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
7424#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
7425
7426#define TIM_CCMR2_IC4F_Pos (12U)
7427#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
7428#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
7429#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
7430#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
7431#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
7432#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
7433
7434/****************** Bit definition for TIM_CCMR3 register *******************/
7435#define TIM_CCMR3_OC5FE_Pos (2U)
7436#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
7437#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
7438#define TIM_CCMR3_OC5PE_Pos (3U)
7439#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
7440#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
7441
7442#define TIM_CCMR3_OC5M_Pos (4U)
7443#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
7444#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
7445#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
7446#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
7447#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
7448#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
7449
7450#define TIM_CCMR3_OC5CE_Pos (7U)
7451#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
7452#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
7453
7454#define TIM_CCMR3_OC6FE_Pos (10U)
7455#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
7456#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
7457#define TIM_CCMR3_OC6PE_Pos (11U)
7458#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
7459#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
7460
7461#define TIM_CCMR3_OC6M_Pos (12U)
7462#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
7463#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
7464#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
7465#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
7466#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
7467#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
7468
7469#define TIM_CCMR3_OC6CE_Pos (15U)
7470#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
7471#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
7472
7473/******************* Bit definition for TIM_CCER register *******************/
7474#define TIM_CCER_CC1E_Pos (0U)
7475#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
7476#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
7477#define TIM_CCER_CC1P_Pos (1U)
7478#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
7479#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
7480#define TIM_CCER_CC1NE_Pos (2U)
7481#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
7482#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
7483#define TIM_CCER_CC1NP_Pos (3U)
7484#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
7485#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
7486#define TIM_CCER_CC2E_Pos (4U)
7487#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
7488#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
7489#define TIM_CCER_CC2P_Pos (5U)
7490#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
7491#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
7492#define TIM_CCER_CC2NE_Pos (6U)
7493#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
7494#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
7495#define TIM_CCER_CC2NP_Pos (7U)
7496#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
7497#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
7498#define TIM_CCER_CC3E_Pos (8U)
7499#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
7500#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
7501#define TIM_CCER_CC3P_Pos (9U)
7502#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
7503#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
7504#define TIM_CCER_CC3NE_Pos (10U)
7505#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
7506#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
7507#define TIM_CCER_CC3NP_Pos (11U)
7508#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
7509#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
7510#define TIM_CCER_CC4E_Pos (12U)
7511#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
7512#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
7513#define TIM_CCER_CC4P_Pos (13U)
7514#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
7515#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
7516#define TIM_CCER_CC4NP_Pos (15U)
7517#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
7518#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
7519#define TIM_CCER_CC5E_Pos (16U)
7520#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
7521#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
7522#define TIM_CCER_CC5P_Pos (17U)
7523#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
7524#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
7525#define TIM_CCER_CC6E_Pos (20U)
7526#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
7527#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
7528#define TIM_CCER_CC6P_Pos (21U)
7529#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
7530#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
7531
7532/******************* Bit definition for TIM_CNT register ********************/
7533#define TIM_CNT_CNT_Pos (0U)
7534#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
7535#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
7536#define TIM_CNT_UIFCPY_Pos (31U)
7537#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
7538#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
7539
7540/******************* Bit definition for TIM_PSC register ********************/
7541#define TIM_PSC_PSC_Pos (0U)
7542#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
7543#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
7544
7545/******************* Bit definition for TIM_ARR register ********************/
7546#define TIM_ARR_ARR_Pos (0U)
7547#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
7548#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
7549
7550/******************* Bit definition for TIM_RCR register ********************/
7551#define TIM_RCR_REP_Pos (0U)
7552#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
7553#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
7554
7555/******************* Bit definition for TIM_CCR1 register *******************/
7556#define TIM_CCR1_CCR1_Pos (0U)
7557#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
7558#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
7559
7560/******************* Bit definition for TIM_CCR2 register *******************/
7561#define TIM_CCR2_CCR2_Pos (0U)
7562#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
7563#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
7564
7565/******************* Bit definition for TIM_CCR3 register *******************/
7566#define TIM_CCR3_CCR3_Pos (0U)
7567#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
7568#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
7569
7570/******************* Bit definition for TIM_CCR4 register *******************/
7571#define TIM_CCR4_CCR4_Pos (0U)
7572#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
7573#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
7574
7575/******************* Bit definition for TIM_CCR5 register *******************/
7576#define TIM_CCR5_CCR5_Pos (0U)
7577#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
7578#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
7579#define TIM_CCR5_GC5C1_Pos (29U)
7580#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
7581#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
7582#define TIM_CCR5_GC5C2_Pos (30U)
7583#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
7584#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
7585#define TIM_CCR5_GC5C3_Pos (31U)
7586#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
7587#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
7588
7589/******************* Bit definition for TIM_CCR6 register *******************/
7590#define TIM_CCR6_CCR6_Pos (0U)
7591#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
7592#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
7593
7594/******************* Bit definition for TIM_BDTR register *******************/
7595#define TIM_BDTR_DTG_Pos (0U)
7596#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
7597#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
7598#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
7599#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
7600#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
7601#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
7602#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
7603#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
7604#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
7605#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
7606
7607#define TIM_BDTR_LOCK_Pos (8U)
7608#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
7609#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
7610#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
7611#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
7612
7613#define TIM_BDTR_OSSI_Pos (10U)
7614#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
7615#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
7616#define TIM_BDTR_OSSR_Pos (11U)
7617#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
7618#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
7619#define TIM_BDTR_BKE_Pos (12U)
7620#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
7621#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
7622#define TIM_BDTR_BKP_Pos (13U)
7623#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
7624#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
7625#define TIM_BDTR_AOE_Pos (14U)
7626#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
7627#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
7628#define TIM_BDTR_MOE_Pos (15U)
7629#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
7630#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
7631
7632#define TIM_BDTR_BKF_Pos (16U)
7633#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
7634#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
7635#define TIM_BDTR_BK2F_Pos (20U)
7636#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
7637#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
7638
7639#define TIM_BDTR_BK2E_Pos (24U)
7640#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
7641#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
7642#define TIM_BDTR_BK2P_Pos (25U)
7643#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
7644#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
7645
7646#define TIM_BDTR_BKDSRM_Pos (26U)
7647#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
7648#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
7649#define TIM_BDTR_BK2DSRM_Pos (27U)
7650#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
7651#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
7652
7653#define TIM_BDTR_BKBID_Pos (28U)
7654#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
7655#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break BIDirectional */
7656#define TIM_BDTR_BK2BID_Pos (29U)
7657#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
7658#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 BIDirectional */
7659
7660/******************* Bit definition for TIM_DCR register ********************/
7661#define TIM_DCR_DBA_Pos (0U)
7662#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
7663#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
7664#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
7665#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
7666#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
7667#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
7668#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
7669
7670#define TIM_DCR_DBL_Pos (8U)
7671#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
7672#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
7673#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
7674#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
7675#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
7676#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
7677#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
7678
7679/******************* Bit definition for TIM_DMAR register *******************/
7680#define TIM_DMAR_DMAB_Pos (0U)
7681#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
7682#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
7683
7684/******************* Bit definition for TIM1_OR1 register *******************/
7685#define TIM1_OR1_OCREF_CLR_Pos (0U)
7686#define TIM1_OR1_OCREF_CLR_Msk (0x1UL << TIM1_OR1_OCREF_CLR_Pos) /*!< 0x00000001 */
7687#define TIM1_OR1_OCREF_CLR TIM1_OR1_OCREF_CLR_Msk /*!<OCREF clear input selection */
7688
7689/******************* Bit definition for TIM1_AF1 register *******************/
7690#define TIM1_AF1_BKINE_Pos (0U)
7691#define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
7692#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BRK BKIN input enable */
7693#define TIM1_AF1_BKCMP1E_Pos (1U)
7694#define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
7695#define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */
7696#define TIM1_AF1_BKCMP2E_Pos (2U)
7697#define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
7698#define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */
7699#define TIM1_AF1_BKINP_Pos (9U)
7700#define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
7701#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
7702#define TIM1_AF1_BKCMP1P_Pos (10U)
7703#define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
7704#define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
7705#define TIM1_AF1_BKCMP2P_Pos (11U)
7706#define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
7707#define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
7708
7709#define TIM1_AF1_ETRSEL_Pos (14U)
7710#define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
7711#define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
7712#define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */
7713#define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */
7714#define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */
7715#define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */
7716
7717/******************* Bit definition for TIM1_AF2 register *******************/
7718#define TIM1_AF2_BK2INE_Pos (0U)
7719#define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
7720#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
7721#define TIM1_AF2_BK2CMP1E_Pos (1U)
7722#define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
7723#define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
7724#define TIM1_AF2_BK2CMP2E_Pos (2U)
7725#define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
7726#define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
7727#define TIM1_AF2_BK2INP_Pos (9U)
7728#define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
7729#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */
7730#define TIM1_AF2_BK2CMP1P_Pos (10U)
7731#define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
7732#define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
7733#define TIM1_AF2_BK2CMP2P_Pos (11U)
7734#define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
7735#define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
7736
7737/******************* Bit definition for TIM2_OR1 register *******************/
7738#define TIM2_OR1_OCREF_CLR_Pos (0U)
7739#define TIM2_OR1_OCREF_CLR_Msk (0x1UL << TIM2_OR1_OCREF_CLR_Pos) /*!< 0x00000001 */
7740#define TIM2_OR1_OCREF_CLR TIM2_OR1_OCREF_CLR_Msk /*!<OCREF clear input selection */
7741
7742/******************* Bit definition for TIM2_AF1 register *******************/
7743#define TIM2_AF1_ETRSEL_Pos (14U)
7744#define TIM2_AF1_ETRSEL_Msk (0xFUL << TIM2_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
7745#define TIM2_AF1_ETRSEL TIM2_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM2 ETR source selection) */
7746#define TIM2_AF1_ETRSEL_0 (0x1UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00004000 */
7747#define TIM2_AF1_ETRSEL_1 (0x2UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00008000 */
7748#define TIM2_AF1_ETRSEL_2 (0x4UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00010000 */
7749#define TIM2_AF1_ETRSEL_3 (0x8UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00020000 */
7750
7751/******************* Bit definition for TIM3_OR1 register *******************/
7752#define TIM3_OR1_OCREF_CLR_Pos (0U)
7753#define TIM3_OR1_OCREF_CLR_Msk (0x1UL << TIM3_OR1_OCREF_CLR_Pos) /*!< 0x00000001 */
7754#define TIM3_OR1_OCREF_CLR TIM3_OR1_OCREF_CLR_Msk /*!<OCREF clear input selection */
7755
7756/******************* Bit definition for TIM3_AF1 register *******************/
7757#define TIM3_AF1_ETRSEL_Pos (14U)
7758#define TIM3_AF1_ETRSEL_Msk (0xFUL << TIM3_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
7759#define TIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM3 ETR source selection) */
7760#define TIM3_AF1_ETRSEL_0 (0x1UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00004000 */
7761#define TIM3_AF1_ETRSEL_1 (0x2UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00008000 */
7762#define TIM3_AF1_ETRSEL_2 (0x4UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00010000 */
7763#define TIM3_AF1_ETRSEL_3 (0x8UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00020000 */
7764
7765/******************* Bit definition for TIM14_AF1 register *******************/
7766#define TIM14_AF1_ETRSEL_Pos (14U)
7767#define TIM14_AF1_ETRSEL_Msk (0xFUL << TIM14_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
7768#define TIM14_AF1_ETRSEL TIM14_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM3 ETR source selection) */
7769#define TIM14_AF1_ETRSEL_0 (0x1UL << TIM14_AF1_ETRSEL_Pos) /*!< 0x00004000 */
7770#define TIM14_AF1_ETRSEL_1 (0x2UL << TIM14_AF1_ETRSEL_Pos) /*!< 0x00008000 */
7771#define TIM14_AF1_ETRSEL_2 (0x4UL << TIM14_AF1_ETRSEL_Pos) /*!< 0x00010000 */
7772#define TIM14_AF1_ETRSEL_3 (0x8UL << TIM14_AF1_ETRSEL_Pos) /*!< 0x00020000 */
7773
7774/******************* Bit definition for TIM15_AF1 register ******************/
7775#define TIM15_AF1_BKINE_Pos (0U)
7776#define TIM15_AF1_BKINE_Msk (0x1UL << TIM15_AF1_BKINE_Pos) /*!< 0x00000001 */
7777#define TIM15_AF1_BKINE TIM15_AF1_BKINE_Msk /*!<BRK BKIN input enable */
7778#define TIM15_AF1_BKCMP1E_Pos (1U)
7779#define TIM15_AF1_BKCMP1E_Msk (0x1UL << TIM15_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
7780#define TIM15_AF1_BKCMP1E TIM15_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */
7781#define TIM15_AF1_BKCMP2E_Pos (2U)
7782#define TIM15_AF1_BKCMP2E_Msk (0x1UL << TIM15_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
7783#define TIM15_AF1_BKCMP2E TIM15_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */
7784#define TIM15_AF1_BKINP_Pos (9U)
7785#define TIM15_AF1_BKINP_Msk (0x1UL << TIM15_AF1_BKINP_Pos) /*!< 0x00000200 */
7786#define TIM15_AF1_BKINP TIM15_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
7787#define TIM15_AF1_BKCMP1P_Pos (10U)
7788#define TIM15_AF1_BKCMP1P_Msk (0x1UL << TIM15_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
7789#define TIM15_AF1_BKCMP1P TIM15_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
7790#define TIM15_AF1_BKCMP2P_Pos (11U)
7791#define TIM15_AF1_BKCMP2P_Msk (0x1UL << TIM15_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
7792#define TIM15_AF1_BKCMP2P TIM15_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
7793
7794/******************* Bit definition for TIM16_AF1 register ******************/
7795#define TIM16_AF1_BKINE_Pos (0U)
7796#define TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos) /*!< 0x00000001 */
7797#define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk /*!<BRK BKIN input enable */
7798#define TIM16_AF1_BKCMP1E_Pos (1U)
7799#define TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
7800#define TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */
7801#define TIM16_AF1_BKCMP2E_Pos (2U)
7802#define TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
7803#define TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */
7804#define TIM16_AF1_BKINP_Pos (9U)
7805#define TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos) /*!< 0x00000200 */
7806#define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
7807#define TIM16_AF1_BKCMP1P_Pos (10U)
7808#define TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
7809#define TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
7810#define TIM16_AF1_BKCMP2P_Pos (11U)
7811#define TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
7812#define TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
7813
7814/******************* Bit definition for TIM17_AF1 register ******************/
7815#define TIM17_AF1_BKINE_Pos (0U)
7816#define TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos) /*!< 0x00000001 */
7817#define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk /*!<BRK BKIN input enable */
7818#define TIM17_AF1_BKCMP1E_Pos (1U)
7819#define TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
7820#define TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */
7821#define TIM17_AF1_BKCMP2E_Pos (2U)
7822#define TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
7823#define TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */
7824#define TIM17_AF1_BKINP_Pos (9U)
7825#define TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos) /*!< 0x00000200 */
7826#define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
7827#define TIM17_AF1_BKCMP1P_Pos (10U)
7828#define TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
7829#define TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
7830#define TIM17_AF1_BKCMP2P_Pos (11U)
7831#define TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
7832#define TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
7833
7834/******************* Bit definition for TIM_TISEL register *********************/
7835#define TIM_TISEL_TI1SEL_Pos (0U)
7836#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
7837#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
7838#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
7839#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
7840#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
7841#define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
7842
7843#define TIM_TISEL_TI2SEL_Pos (8U)
7844#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
7845#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
7846#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
7847#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
7848#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
7849#define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
7850
7851#define TIM_TISEL_TI3SEL_Pos (16U)
7852#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
7853#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
7854#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
7855#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
7856#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
7857#define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
7858
7859#define TIM_TISEL_TI4SEL_Pos (24U)
7860#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
7861#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
7862#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
7863#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
7864#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
7865#define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
7866
7867/******************************************************************************/
7868/* */
7869/* Low Power Timer (LPTIM) */
7870/* */
7871/******************************************************************************/
7872/****************** Bit definition for LPTIM_ISR register *******************/
7873#define LPTIM_ISR_CMPM_Pos (0U)
7874#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
7875#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
7876#define LPTIM_ISR_ARRM_Pos (1U)
7877#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
7878#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
7879#define LPTIM_ISR_EXTTRIG_Pos (2U)
7880#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
7881#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
7882#define LPTIM_ISR_CMPOK_Pos (3U)
7883#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
7884#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
7885#define LPTIM_ISR_ARROK_Pos (4U)
7886#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
7887#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
7888#define LPTIM_ISR_UP_Pos (5U)
7889#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
7890#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
7891#define LPTIM_ISR_DOWN_Pos (6U)
7892#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
7893#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
7894
7895/****************** Bit definition for LPTIM_ICR register *******************/
7896#define LPTIM_ICR_CMPMCF_Pos (0U)
7897#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
7898#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
7899#define LPTIM_ICR_ARRMCF_Pos (1U)
7900#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
7901#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
7902#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
7903#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
7904#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
7905#define LPTIM_ICR_CMPOKCF_Pos (3U)
7906#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
7907#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
7908#define LPTIM_ICR_ARROKCF_Pos (4U)
7909#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
7910#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
7911#define LPTIM_ICR_UPCF_Pos (5U)
7912#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
7913#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
7914#define LPTIM_ICR_DOWNCF_Pos (6U)
7915#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
7916#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
7917
7918/****************** Bit definition for LPTIM_IER register ********************/
7919#define LPTIM_IER_CMPMIE_Pos (0U)
7920#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
7921#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
7922#define LPTIM_IER_ARRMIE_Pos (1U)
7923#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
7924#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
7925#define LPTIM_IER_EXTTRIGIE_Pos (2U)
7926#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
7927#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
7928#define LPTIM_IER_CMPOKIE_Pos (3U)
7929#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
7930#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
7931#define LPTIM_IER_ARROKIE_Pos (4U)
7932#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
7933#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
7934#define LPTIM_IER_UPIE_Pos (5U)
7935#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
7936#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
7937#define LPTIM_IER_DOWNIE_Pos (6U)
7938#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
7939#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
7940
7941/****************** Bit definition for LPTIM_CFGR register *******************/
7942#define LPTIM_CFGR_CKSEL_Pos (0U)
7943#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
7944#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
7945
7946#define LPTIM_CFGR_CKPOL_Pos (1U)
7947#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
7948#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
7949#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
7950#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
7951
7952#define LPTIM_CFGR_CKFLT_Pos (3U)
7953#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
7954#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
7955#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
7956#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
7957
7958#define LPTIM_CFGR_TRGFLT_Pos (6U)
7959#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
7960#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
7961#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
7962#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
7963
7964#define LPTIM_CFGR_PRESC_Pos (9U)
7965#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
7966#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
7967#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
7968#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
7969#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
7970
7971#define LPTIM_CFGR_TRIGSEL_Pos (13U)
7972#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
7973#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
7974#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
7975#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
7976#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
7977
7978#define LPTIM_CFGR_TRIGEN_Pos (17U)
7979#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
7980#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
7981#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
7982#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
7983
7984#define LPTIM_CFGR_TIMOUT_Pos (19U)
7985#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
7986#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
7987#define LPTIM_CFGR_WAVE_Pos (20U)
7988#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
7989#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
7990#define LPTIM_CFGR_WAVPOL_Pos (21U)
7991#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
7992#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
7993#define LPTIM_CFGR_PRELOAD_Pos (22U)
7994#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
7995#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
7996#define LPTIM_CFGR_COUNTMODE_Pos (23U)
7997#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
7998#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
7999#define LPTIM_CFGR_ENC_Pos (24U)
8000#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
8001#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
8002
8003/****************** Bit definition for LPTIM_CR register ********************/
8004#define LPTIM_CR_ENABLE_Pos (0U)
8005#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
8006#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
8007#define LPTIM_CR_SNGSTRT_Pos (1U)
8008#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
8009#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
8010#define LPTIM_CR_CNTSTRT_Pos (2U)
8011#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
8012#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
8013#define LPTIM_CR_COUNTRST_Pos (3U)
8014#define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
8015#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Counter reset */
8016#define LPTIM_CR_RSTARE_Pos (4U)
8017#define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
8018#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Reset after read enable */
8019
8020/****************** Bit definition for LPTIM_CMP register *******************/
8021#define LPTIM_CMP_CMP_Pos (0U)
8022#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
8023#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
8024
8025/****************** Bit definition for LPTIM_ARR register *******************/
8026#define LPTIM_ARR_ARR_Pos (0U)
8027#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
8028#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
8029
8030/****************** Bit definition for LPTIM_CNT register *******************/
8031#define LPTIM_CNT_CNT_Pos (0U)
8032#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
8033#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
8034
8035/****************** Bit definition for LPTIM_CFGR2 register *******************/
8036#define LPTIM_CFGR2_IN1SEL_Pos (0U)
8037#define LPTIM_CFGR2_IN1SEL_Msk (0xFUL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x0000000F */
8038#define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< CFGR2[3:0] bits (INPUT1 selection) */
8039#define LPTIM_CFGR2_IN1SEL_0 (0x1UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000001 */
8040#define LPTIM_CFGR2_IN1SEL_1 (0x2UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000002 */
8041#define LPTIM_CFGR2_IN1SEL_2 (0x4UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000004 */
8042#define LPTIM_CFGR2_IN1SEL_3 (0x8UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000008 */
8043
8044#define LPTIM_CFGR2_IN2SEL_Pos (4U)
8045#define LPTIM_CFGR2_IN2SEL_Msk (0xFUL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x000000F0 */
8046#define LPTIM_CFGR2_IN2SEL LPTIM_CFGR2_IN2SEL_Msk /*!< CFGR2[7:4] bits (INPUT2 selection) */
8047#define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
8048#define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */
8049#define LPTIM_CFGR2_IN2SEL_2 (0x4UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000040 */
8050#define LPTIM_CFGR2_IN2SEL_3 (0x8UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000080 */
8051
8052/******************************************************************************/
8053/* */
8054/* Analog Comparators (COMP) */
8055/* */
8056/******************************************************************************/
8057/********************** Bit definition for COMP_CSR register ****************/
8058#define COMP_CSR_EN_Pos (0U)
8059#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */
8060#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
8061
8062#define COMP_CSR_INMSEL_Pos (4U)
8063#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x000000F0 */
8064#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
8065#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */
8066#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */
8067#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */
8068#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */
8069
8070#define COMP_CSR_INPSEL_Pos (8U)
8071#define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000300 */
8072#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator plus minus selection */
8073#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */
8074#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000200 */
8075
8076#define COMP_CSR_WINMODE_Pos (11U)
8077#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000800 */
8078#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
8079#define COMP_CSR_WINOUT_Pos (14U)
8080#define COMP_CSR_WINOUT_Msk (0x1UL << COMP_CSR_WINOUT_Pos) /*!< 0x00004000 */
8081#define COMP_CSR_WINOUT COMP_CSR_WINOUT_Msk /*!< Pair of comparators window output level. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
8082
8083#define COMP_CSR_POLARITY_Pos (15U)
8084#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
8085#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
8086
8087#define COMP_CSR_HYST_Pos (16U)
8088#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00030000 */
8089#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator input hysteresis */
8090#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
8091#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */
8092
8093#define COMP_CSR_PWRMODE_Pos (18U)
8094#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x000C0000 */
8095#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */
8096#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00040000 */
8097#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00080000 */
8098
8099#define COMP_CSR_BLANKING_Pos (20U)
8100#define COMP_CSR_BLANKING_Msk (0x1FUL << COMP_CSR_BLANKING_Pos) /*!< 0x01F00000 */
8101#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */
8102#define COMP_CSR_BLANKING_0 (0x01UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
8103#define COMP_CSR_BLANKING_1 (0x02UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */
8104#define COMP_CSR_BLANKING_2 (0x04UL << COMP_CSR_BLANKING_Pos) /*!< 0x00400000 */
8105#define COMP_CSR_BLANKING_3 (0x08UL << COMP_CSR_BLANKING_Pos) /*!< 0x00800000 */
8106#define COMP_CSR_BLANKING_4 (0x10UL << COMP_CSR_BLANKING_Pos) /*!< 0x01000000 */
8107
8108#define COMP_CSR_VALUE_Pos (30U)
8109#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
8110#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */
8111
8112#define COMP_CSR_LOCK_Pos (31U)
8113#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */
8114#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */
8115
8116/******************************************************************************/
8117/* */
8118/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
8119/* */
8120/******************************************************************************/
8121/****************** Bit definition for USART_CR1 register *******************/
8122#define USART_CR1_UE_Pos (0U)
8123#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
8124#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
8125#define USART_CR1_UESM_Pos (1U)
8126#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
8127#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
8128#define USART_CR1_RE_Pos (2U)
8129#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
8130#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
8131#define USART_CR1_TE_Pos (3U)
8132#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
8133#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
8134#define USART_CR1_IDLEIE_Pos (4U)
8135#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
8136#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
8137#define USART_CR1_RXNEIE_RXFNEIE_Pos (5U)
8138#define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
8139#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk /*!< RXNE/RXFIFO not empty Interrupt Enable */
8140#define USART_CR1_TCIE_Pos (6U)
8141#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
8142#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
8143#define USART_CR1_TXEIE_TXFNFIE_Pos (7U)
8144#define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */
8145#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk /*!< TXE/TXFIFO not full Interrupt Enable */
8146#define USART_CR1_PEIE_Pos (8U)
8147#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
8148#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
8149#define USART_CR1_PS_Pos (9U)
8150#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
8151#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
8152#define USART_CR1_PCE_Pos (10U)
8153#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
8154#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
8155#define USART_CR1_WAKE_Pos (11U)
8156#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
8157#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
8158#define USART_CR1_M_Pos (12U)
8159#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
8160#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
8161#define USART_CR1_M0_Pos (12U)
8162#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
8163#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
8164#define USART_CR1_MME_Pos (13U)
8165#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
8166#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
8167#define USART_CR1_CMIE_Pos (14U)
8168#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
8169#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
8170#define USART_CR1_OVER8_Pos (15U)
8171#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
8172#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
8173#define USART_CR1_DEDT_Pos (16U)
8174#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
8175#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
8176#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
8177#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
8178#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
8179#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
8180#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
8181#define USART_CR1_DEAT_Pos (21U)
8182#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
8183#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
8184#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
8185#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
8186#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
8187#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
8188#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
8189#define USART_CR1_RTOIE_Pos (26U)
8190#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
8191#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
8192#define USART_CR1_EOBIE_Pos (27U)
8193#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
8194#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
8195#define USART_CR1_M1_Pos (28U)
8196#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
8197#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
8198#define USART_CR1_FIFOEN_Pos (29U)
8199#define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
8200#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
8201#define USART_CR1_TXFEIE_Pos (30U)
8202#define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
8203#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */
8204#define USART_CR1_RXFFIE_Pos (31U)
8205#define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
8206#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */
8207
8208/****************** Bit definition for USART_CR2 register *******************/
8209#define USART_CR2_SLVEN_Pos (0U)
8210#define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
8211#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */
8212#define USART_CR2_DIS_NSS_Pos (3U)
8213#define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
8214#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< NSS input pin disable for SPI slave selection */
8215#define USART_CR2_ADDM7_Pos (4U)
8216#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
8217#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
8218#define USART_CR2_LBDL_Pos (5U)
8219#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
8220#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
8221#define USART_CR2_LBDIE_Pos (6U)
8222#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
8223#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
8224#define USART_CR2_LBCL_Pos (8U)
8225#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
8226#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
8227#define USART_CR2_CPHA_Pos (9U)
8228#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
8229#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
8230#define USART_CR2_CPOL_Pos (10U)
8231#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
8232#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
8233#define USART_CR2_CLKEN_Pos (11U)
8234#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
8235#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
8236#define USART_CR2_STOP_Pos (12U)
8237#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
8238#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
8239#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
8240#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
8241#define USART_CR2_LINEN_Pos (14U)
8242#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
8243#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
8244#define USART_CR2_SWAP_Pos (15U)
8245#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
8246#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
8247#define USART_CR2_RXINV_Pos (16U)
8248#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
8249#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
8250#define USART_CR2_TXINV_Pos (17U)
8251#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
8252#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
8253#define USART_CR2_DATAINV_Pos (18U)
8254#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
8255#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
8256#define USART_CR2_MSBFIRST_Pos (19U)
8257#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
8258#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
8259#define USART_CR2_ABREN_Pos (20U)
8260#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
8261#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
8262#define USART_CR2_ABRMODE_Pos (21U)
8263#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
8264#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
8265#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
8266#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
8267#define USART_CR2_RTOEN_Pos (23U)
8268#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
8269#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
8270#define USART_CR2_ADD_Pos (24U)
8271#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
8272#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
8273
8274/****************** Bit definition for USART_CR3 register *******************/
8275#define USART_CR3_EIE_Pos (0U)
8276#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
8277#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
8278#define USART_CR3_IREN_Pos (1U)
8279#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
8280#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
8281#define USART_CR3_IRLP_Pos (2U)
8282#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
8283#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
8284#define USART_CR3_HDSEL_Pos (3U)
8285#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
8286#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
8287#define USART_CR3_NACK_Pos (4U)
8288#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
8289#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
8290#define USART_CR3_SCEN_Pos (5U)
8291#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
8292#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
8293#define USART_CR3_DMAR_Pos (6U)
8294#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
8295#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
8296#define USART_CR3_DMAT_Pos (7U)
8297#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
8298#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
8299#define USART_CR3_RTSE_Pos (8U)
8300#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
8301#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
8302#define USART_CR3_CTSE_Pos (9U)
8303#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
8304#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
8305#define USART_CR3_CTSIE_Pos (10U)
8306#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
8307#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
8308#define USART_CR3_ONEBIT_Pos (11U)
8309#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
8310#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
8311#define USART_CR3_OVRDIS_Pos (12U)
8312#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
8313#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
8314#define USART_CR3_DDRE_Pos (13U)
8315#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
8316#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
8317#define USART_CR3_DEM_Pos (14U)
8318#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
8319#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
8320#define USART_CR3_DEP_Pos (15U)
8321#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
8322#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
8323#define USART_CR3_SCARCNT_Pos (17U)
8324#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
8325#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
8326#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
8327#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
8328#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
8329#define USART_CR3_WUS_Pos (20U)
8330#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
8331#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
8332#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
8333#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
8334#define USART_CR3_WUFIE_Pos (22U)
8335#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
8336#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
8337#define USART_CR3_TXFTIE_Pos (23U)
8338#define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */
8339#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */
8340#define USART_CR3_TCBGTIE_Pos (24U)
8341#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
8342#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
8343#define USART_CR3_RXFTCFG_Pos (25U)
8344#define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
8345#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFIFO FIFO threshold configuration */
8346#define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
8347#define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
8348#define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
8349#define USART_CR3_RXFTIE_Pos (28U)
8350#define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */
8351#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */
8352#define USART_CR3_TXFTCFG_Pos (29U)
8353#define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
8354#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO threshold configuration */
8355#define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
8356#define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
8357#define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
8358
8359/****************** Bit definition for USART_BRR register *******************/
8360#define USART_BRR_LPUART_Pos (0U)
8361#define USART_BRR_LPUART_Msk (0xFFFFFUL << USART_BRR_LPUART_Pos) /*!< 0x000FFFFF */
8362#define USART_BRR_LPUART USART_BRR_LPUART_Msk /*!< LPUART Baud rate register [19:0] */
8363#define USART_BRR_BRR ((uint16_t)0xFFFF) /*!< USART Baud rate register [15:0] */
8364
8365/****************** Bit definition for USART_GTPR register ******************/
8366#define USART_GTPR_PSC_Pos (0U)
8367#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
8368#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
8369#define USART_GTPR_GT_Pos (8U)
8370#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
8371#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
8372
8373/******************* Bit definition for USART_RTOR register *****************/
8374#define USART_RTOR_RTO_Pos (0U)
8375#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
8376#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
8377#define USART_RTOR_BLEN_Pos (24U)
8378#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
8379#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
8380
8381/******************* Bit definition for USART_RQR register ******************/
8382#define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate Request */
8383#define USART_RQR_SBKRQ ((uint16_t)0x0002) /*!< Send Break Request */
8384#define USART_RQR_MMRQ ((uint16_t)0x0004) /*!< Mute Mode Request */
8385#define USART_RQR_RXFRQ ((uint16_t)0x0008) /*!< Receive Data flush Request */
8386#define USART_RQR_TXFRQ ((uint16_t)0x0010) /*!< Transmit data flush Request */
8387
8388/******************* Bit definition for USART_ISR register ******************/
8389#define USART_ISR_PE_Pos (0U)
8390#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
8391#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
8392#define USART_ISR_FE_Pos (1U)
8393#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
8394#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
8395#define USART_ISR_NE_Pos (2U)
8396#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
8397#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
8398#define USART_ISR_ORE_Pos (3U)
8399#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
8400#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
8401#define USART_ISR_IDLE_Pos (4U)
8402#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
8403#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
8404#define USART_ISR_RXNE_RXFNE_Pos (5U)
8405#define USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos) /*!< 0x00000020 */
8406#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk /*!< Read Data Register Not Empty/RXFIFO Not Empty */
8407#define USART_ISR_TC_Pos (6U)
8408#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
8409#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
8410#define USART_ISR_TXE_TXFNF_Pos (7U)
8411#define USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos) /*!< 0x00000080 */
8412#define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk /*!< Transmit Data Register Empty/TXFIFO Not Full */
8413#define USART_ISR_LBDF_Pos (8U)
8414#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
8415#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
8416#define USART_ISR_CTSIF_Pos (9U)
8417#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
8418#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
8419#define USART_ISR_CTS_Pos (10U)
8420#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
8421#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
8422#define USART_ISR_RTOF_Pos (11U)
8423#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
8424#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
8425#define USART_ISR_EOBF_Pos (12U)
8426#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
8427#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
8428#define USART_ISR_UDR_Pos (13U)
8429#define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */
8430#define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI Slave Underrun Error Flag */
8431#define USART_ISR_ABRE_Pos (14U)
8432#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
8433#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
8434#define USART_ISR_ABRF_Pos (15U)
8435#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
8436#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
8437#define USART_ISR_BUSY_Pos (16U)
8438#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
8439#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
8440#define USART_ISR_CMF_Pos (17U)
8441#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
8442#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
8443#define USART_ISR_SBKF_Pos (18U)
8444#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
8445#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
8446#define USART_ISR_RWU_Pos (19U)
8447#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
8448#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
8449#define USART_ISR_WUF_Pos (20U)
8450#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
8451#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
8452#define USART_ISR_TEACK_Pos (21U)
8453#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
8454#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
8455#define USART_ISR_REACK_Pos (22U)
8456#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
8457#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
8458#define USART_ISR_TXFE_Pos (23U)
8459#define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
8460#define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty Flag */
8461#define USART_ISR_RXFF_Pos (24U)
8462#define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */
8463#define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full Flag */
8464#define USART_ISR_TCBGT_Pos (25U)
8465#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
8466#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time Completion Flag */
8467#define USART_ISR_RXFT_Pos (26U)
8468#define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
8469#define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO Threshold Flag */
8470#define USART_ISR_TXFT_Pos (27U)
8471#define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
8472#define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO Threshold Flag */
8473
8474/******************* Bit definition for USART_ICR register ******************/
8475#define USART_ICR_PECF_Pos (0U)
8476#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
8477#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
8478#define USART_ICR_FECF_Pos (1U)
8479#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
8480#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
8481#define USART_ICR_NECF_Pos (2U)
8482#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */
8483#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
8484#define USART_ICR_ORECF_Pos (3U)
8485#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
8486#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
8487#define USART_ICR_IDLECF_Pos (4U)
8488#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
8489#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
8490#define USART_ICR_TXFECF_Pos (5U)
8491#define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
8492#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO Empty Clear Flag */
8493#define USART_ICR_TCCF_Pos (6U)
8494#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
8495#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
8496#define USART_ICR_TCBGTCF_Pos (7U)
8497#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
8498#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
8499#define USART_ICR_LBDCF_Pos (8U)
8500#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
8501#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
8502#define USART_ICR_CTSCF_Pos (9U)
8503#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
8504#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
8505#define USART_ICR_RTOCF_Pos (11U)
8506#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
8507#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
8508#define USART_ICR_EOBCF_Pos (12U)
8509#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
8510#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
8511#define USART_ICR_UDRCF_Pos (13U)
8512#define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
8513#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */
8514#define USART_ICR_CMCF_Pos (17U)
8515#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
8516#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
8517#define USART_ICR_WUCF_Pos (20U)
8518#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
8519#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
8520
8521/******************* Bit definition for USART_RDR register ******************/
8522#define USART_RDR_RDR_Pos (0U)
8523#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
8524#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
8525
8526/******************* Bit definition for USART_TDR register ******************/
8527#define USART_TDR_TDR_Pos (0U)
8528#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
8529#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
8530
8531/******************* Bit definition for USART_PRESC register ****************/
8532#define USART_PRESC_PRESCALER_Pos (0U)
8533#define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
8534#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
8535#define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
8536#define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
8537#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
8538#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
8539
8540
8541/******************************************************************************/
8542/* */
8543/* VREFBUF */
8544/* */
8545/******************************************************************************/
8546/******************* Bit definition for VREFBUF_CSR register ****************/
8547#define VREFBUF_CSR_ENVR_Pos (0U)
8548#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
8549#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
8550#define VREFBUF_CSR_HIZ_Pos (1U)
8551#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
8552#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
8553#define VREFBUF_CSR_VRS_Pos (2U)
8554#define VREFBUF_CSR_VRS_Msk (0x1UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000004 */
8555#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
8556#define VREFBUF_CSR_VRR_Pos (3U)
8557#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
8558#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
8559
8560/******************* Bit definition for VREFBUF_CCR register ******************/
8561#define VREFBUF_CCR_TRIM_Pos (0U)
8562#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
8563#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
8564
8565/******************************************************************************/
8566/* */
8567/* Window WATCHDOG */
8568/* */
8569/******************************************************************************/
8570/******************* Bit definition for WWDG_CR register ********************/
8571#define WWDG_CR_T_Pos (0U)
8572#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
8573#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
8574#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
8575#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
8576#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
8577#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
8578#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
8579#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
8580#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
8581
8582#define WWDG_CR_WDGA_Pos (7U)
8583#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
8584#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
8585
8586/******************* Bit definition for WWDG_CFR register *******************/
8587#define WWDG_CFR_W_Pos (0U)
8588#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
8589#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
8590#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
8591#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
8592#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
8593#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
8594#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
8595#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
8596#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
8597
8598#define WWDG_CFR_WDGTB_Pos (11U)
8599#define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */
8600#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */
8601#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */
8602#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */
8603#define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */
8604
8605#define WWDG_CFR_EWI_Pos (9U)
8606#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
8607#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
8608
8609/******************* Bit definition for WWDG_SR register ********************/
8610#define WWDG_SR_EWIF_Pos (0U)
8611#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
8612#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
8613
8614/******************************************************************************/
8615/* */
8616/* Debug MCU */
8617/* */
8618/******************************************************************************/
8619/******************** Bit definition for DBG_IDCODE register *************/
8620#define DBG_IDCODE_DEV_ID_Pos (0U)
8621#define DBG_IDCODE_DEV_ID_Msk (0xFFFUL << DBG_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
8622#define DBG_IDCODE_DEV_ID DBG_IDCODE_DEV_ID_Msk
8623#define DBG_IDCODE_REV_ID_Pos (16U)
8624#define DBG_IDCODE_REV_ID_Msk (0xFFFFUL << DBG_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
8625#define DBG_IDCODE_REV_ID DBG_IDCODE_REV_ID_Msk
8626
8627/******************** Bit definition for DBG_CR register *****************/
8628#define DBG_CR_DBG_STOP_Pos (1U)
8629#define DBG_CR_DBG_STOP_Msk (0x1UL << DBG_CR_DBG_STOP_Pos) /*!< 0x00000002 */
8630#define DBG_CR_DBG_STOP DBG_CR_DBG_STOP_Msk
8631#define DBG_CR_DBG_STANDBY_Pos (2U)
8632#define DBG_CR_DBG_STANDBY_Msk (0x1UL << DBG_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
8633#define DBG_CR_DBG_STANDBY DBG_CR_DBG_STANDBY_Msk
8634
8635
8636/******************** Bit definition for DBG_APB_FZ1 register ***********/
8637#define DBG_APB_FZ1_DBG_TIM2_STOP_Pos (0U)
8638#define DBG_APB_FZ1_DBG_TIM2_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
8639#define DBG_APB_FZ1_DBG_TIM2_STOP DBG_APB_FZ1_DBG_TIM2_STOP_Msk
8640#define DBG_APB_FZ1_DBG_TIM3_STOP_Pos (1U)
8641#define DBG_APB_FZ1_DBG_TIM3_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
8642#define DBG_APB_FZ1_DBG_TIM3_STOP DBG_APB_FZ1_DBG_TIM3_STOP_Msk
8643#define DBG_APB_FZ1_DBG_TIM6_STOP_Pos (4U)
8644#define DBG_APB_FZ1_DBG_TIM6_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
8645#define DBG_APB_FZ1_DBG_TIM6_STOP DBG_APB_FZ1_DBG_TIM6_STOP_Msk
8646#define DBG_APB_FZ1_DBG_TIM7_STOP_Pos (5U)
8647#define DBG_APB_FZ1_DBG_TIM7_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
8648#define DBG_APB_FZ1_DBG_TIM7_STOP DBG_APB_FZ1_DBG_TIM7_STOP_Msk
8649#define DBG_APB_FZ1_DBG_RTC_STOP_Pos (10U)
8650#define DBG_APB_FZ1_DBG_RTC_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
8651#define DBG_APB_FZ1_DBG_RTC_STOP DBG_APB_FZ1_DBG_RTC_STOP_Msk
8652#define DBG_APB_FZ1_DBG_WWDG_STOP_Pos (11U)
8653#define DBG_APB_FZ1_DBG_WWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
8654#define DBG_APB_FZ1_DBG_WWDG_STOP DBG_APB_FZ1_DBG_WWDG_STOP_Msk
8655#define DBG_APB_FZ1_DBG_IWDG_STOP_Pos (12U)
8656#define DBG_APB_FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
8657#define DBG_APB_FZ1_DBG_IWDG_STOP DBG_APB_FZ1_DBG_IWDG_STOP_Msk
8658#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos (21U)
8659#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos) /*!< 0x00200000 */
8660#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk
8661#define DBG_APB_FZ1_DBG_LPTIM2_STOP_Pos (30U)
8662#define DBG_APB_FZ1_DBG_LPTIM2_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_LPTIM2_STOP_Pos) /*!< 0x40000000 */
8663#define DBG_APB_FZ1_DBG_LPTIM2_STOP DBG_APB_FZ1_DBG_LPTIM2_STOP_Msk
8664#define DBG_APB_FZ1_DBG_LPTIM1_STOP_Pos (31U)
8665#define DBG_APB_FZ1_DBG_LPTIM1_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
8666#define DBG_APB_FZ1_DBG_LPTIM1_STOP DBG_APB_FZ1_DBG_LPTIM1_STOP_Msk
8667
8668/******************** Bit definition for DBG_APB_FZ2 register ************/
8669#define DBG_APB_FZ2_DBG_TIM1_STOP_Pos (11U)
8670#define DBG_APB_FZ2_DBG_TIM1_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
8671#define DBG_APB_FZ2_DBG_TIM1_STOP DBG_APB_FZ2_DBG_TIM1_STOP_Msk
8672#define DBG_APB_FZ2_DBG_TIM14_STOP_Pos (15U)
8673#define DBG_APB_FZ2_DBG_TIM14_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM14_STOP_Pos) /*!< 0x00008000 */
8674#define DBG_APB_FZ2_DBG_TIM14_STOP DBG_APB_FZ2_DBG_TIM14_STOP_Msk
8675#define DBG_APB_FZ2_DBG_TIM15_STOP_Pos (16U)
8676#define DBG_APB_FZ2_DBG_TIM15_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
8677#define DBG_APB_FZ2_DBG_TIM15_STOP DBG_APB_FZ2_DBG_TIM15_STOP_Msk
8678#define DBG_APB_FZ2_DBG_TIM16_STOP_Pos (17U)
8679#define DBG_APB_FZ2_DBG_TIM16_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
8680#define DBG_APB_FZ2_DBG_TIM16_STOP DBG_APB_FZ2_DBG_TIM16_STOP_Msk
8681#define DBG_APB_FZ2_DBG_TIM17_STOP_Pos (18U)
8682#define DBG_APB_FZ2_DBG_TIM17_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
8683#define DBG_APB_FZ2_DBG_TIM17_STOP DBG_APB_FZ2_DBG_TIM17_STOP_Msk
8684
8685/******************************************************************************/
8686/* */
8687/* UCPD */
8688/* */
8689/******************************************************************************/
8690/******************** Bits definition for UCPD_CFG1 register *******************/
8691#define UCPD_CFG1_HBITCLKDIV_Pos (0U)
8692#define UCPD_CFG1_HBITCLKDIV_Msk (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */
8693#define UCPD_CFG1_HBITCLKDIV UCPD_CFG1_HBITCLKDIV_Msk /*!< Number of cycles (minus 1) for a half bit clock */
8694#define UCPD_CFG1_HBITCLKDIV_0 (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */
8695#define UCPD_CFG1_HBITCLKDIV_1 (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */
8696#define UCPD_CFG1_HBITCLKDIV_2 (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */
8697#define UCPD_CFG1_HBITCLKDIV_3 (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */
8698#define UCPD_CFG1_HBITCLKDIV_4 (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */
8699#define UCPD_CFG1_HBITCLKDIV_5 (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */
8700#define UCPD_CFG1_IFRGAP_Pos (6U)
8701#define UCPD_CFG1_IFRGAP_Msk (0x1FUL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x000007C0 */
8702#define UCPD_CFG1_IFRGAP UCPD_CFG1_IFRGAP_Msk /*!< Clock divider value to generates Interframe gap */
8703#define UCPD_CFG1_IFRGAP_0 (0x01UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000040 */
8704#define UCPD_CFG1_IFRGAP_1 (0x02UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000080 */
8705#define UCPD_CFG1_IFRGAP_2 (0x04UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000100 */
8706#define UCPD_CFG1_IFRGAP_3 (0x08UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000200 */
8707#define UCPD_CFG1_IFRGAP_4 (0x10UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000400 */
8708#define UCPD_CFG1_TRANSWIN_Pos (11U)
8709#define UCPD_CFG1_TRANSWIN_Msk (0x1FUL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x0000F800 */
8710#define UCPD_CFG1_TRANSWIN UCPD_CFG1_TRANSWIN_Msk /*!< Number of cycles (minus 1) of the half bit clock */
8711#define UCPD_CFG1_TRANSWIN_0 (0x01UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00000800 */
8712#define UCPD_CFG1_TRANSWIN_1 (0x02UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00001000 */
8713#define UCPD_CFG1_TRANSWIN_2 (0x04UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00002000 */
8714#define UCPD_CFG1_TRANSWIN_3 (0x08UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00004000 */
8715#define UCPD_CFG1_TRANSWIN_4 (0x10UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00008000 */
8716#define UCPD_CFG1_PSC_UCPDCLK_Pos (17U)
8717#define UCPD_CFG1_PSC_UCPDCLK_Msk (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */
8718#define UCPD_CFG1_PSC_UCPDCLK UCPD_CFG1_PSC_UCPDCLK_Msk /*!< Prescaler for UCPDCLK */
8719#define UCPD_CFG1_PSC_UCPDCLK_0 (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */
8720#define UCPD_CFG1_PSC_UCPDCLK_1 (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */
8721#define UCPD_CFG1_PSC_UCPDCLK_2 (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */
8722#define UCPD_CFG1_RXORDSETEN_Pos (20U)
8723#define UCPD_CFG1_RXORDSETEN_Msk (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x1FF00000 */
8724#define UCPD_CFG1_RXORDSETEN UCPD_CFG1_RXORDSETEN_Msk /*!< Receiver ordered set detection enable */
8725#define UCPD_CFG1_RXORDSETEN_0 (0x001UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00100000 */
8726#define UCPD_CFG1_RXORDSETEN_1 (0x002UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00200000 */
8727#define UCPD_CFG1_RXORDSETEN_2 (0x004UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00400000 */
8728#define UCPD_CFG1_RXORDSETEN_3 (0x008UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00800000 */
8729#define UCPD_CFG1_RXORDSETEN_4 (0x010UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x01000000 */
8730#define UCPD_CFG1_RXORDSETEN_5 (0x020UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x02000000 */
8731#define UCPD_CFG1_RXORDSETEN_6 (0x040UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x04000000 */
8732#define UCPD_CFG1_RXORDSETEN_7 (0x080UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x08000000 */
8733#define UCPD_CFG1_RXORDSETEN_8 (0x100UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x10000000 */
8734#define UCPD_CFG1_TXDMAEN_Pos (29U)
8735#define UCPD_CFG1_TXDMAEN_Msk (0x1UL << UCPD_CFG1_TXDMAEN_Pos) /*!< 0x20000000 */
8736#define UCPD_CFG1_TXDMAEN UCPD_CFG1_TXDMAEN_Msk /*!< DMA transmission requests enable */
8737#define UCPD_CFG1_RXDMAEN_Pos (30U)
8738#define UCPD_CFG1_RXDMAEN_Msk (0x1UL << UCPD_CFG1_RXDMAEN_Pos) /*!< 0x40000000 */
8739#define UCPD_CFG1_RXDMAEN UCPD_CFG1_RXDMAEN_Msk /*!< DMA reception requests enable */
8740#define UCPD_CFG1_UCPDEN_Pos (31U)
8741#define UCPD_CFG1_UCPDEN_Msk (0x1UL << UCPD_CFG1_UCPDEN_Pos) /*!< 0x80000000 */
8742#define UCPD_CFG1_UCPDEN UCPD_CFG1_UCPDEN_Msk /*!< USB Power Delivery Block Enable */
8743
8744/******************** Bits definition for UCPD_CFG2 register *******************/
8745#define UCPD_CFG2_RXFILTDIS_Pos (0U)
8746#define UCPD_CFG2_RXFILTDIS_Msk (0x1UL << UCPD_CFG2_RXFILTDIS_Pos) /*!< 0x00000001 */
8747#define UCPD_CFG2_RXFILTDIS UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC decoder */
8748#define UCPD_CFG2_RXFILT2N3_Pos (1U)
8749#define UCPD_CFG2_RXFILT2N3_Msk (0x1UL << UCPD_CFG2_RXFILT2N3_Pos) /*!< 0x00000002 */
8750#define UCPD_CFG2_RXFILT2N3 UCPD_CFG2_RXFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */
8751#define UCPD_CFG2_FORCECLK_Pos (2U)
8752#define UCPD_CFG2_FORCECLK_Msk (0x1UL << UCPD_CFG2_FORCECLK_Pos) /*!< 0x00000004 */
8753#define UCPD_CFG2_FORCECLK UCPD_CFG2_FORCECLK_Msk /*!< Controls forcing of the clock request UCPDCLK_REQ */
8754#define UCPD_CFG2_WUPEN_Pos (3U)
8755#define UCPD_CFG2_WUPEN_Msk (0x1UL << UCPD_CFG2_WUPEN_Pos) /*!< 0x00000008 */
8756#define UCPD_CFG2_WUPEN UCPD_CFG2_WUPEN_Msk /*!< Wakeup from STOP enable */
8757
8758/******************** Bits definition for UCPD_CR register ********************/
8759#define UCPD_CR_TXMODE_Pos (0U)
8760#define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000003 */
8761#define UCPD_CR_TXMODE UCPD_CR_TXMODE_Msk /*!< Type of Tx packet */
8762#define UCPD_CR_TXMODE_0 (0x1UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000001 */
8763#define UCPD_CR_TXMODE_1 (0x2UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000002 */
8764#define UCPD_CR_TXSEND_Pos (2U)
8765#define UCPD_CR_TXSEND_Msk (0x1UL << UCPD_CR_TXSEND_Pos) /*!< 0x00000004 */
8766#define UCPD_CR_TXSEND UCPD_CR_TXSEND_Msk /*!< Type of Tx packet */
8767#define UCPD_CR_TXHRST_Pos (3U)
8768#define UCPD_CR_TXHRST_Msk (0x1UL << UCPD_CR_TXHRST_Pos) /*!< 0x00000008 */
8769#define UCPD_CR_TXHRST UCPD_CR_TXHRST_Msk /*!< Command to send a Tx Hard Reset */
8770#define UCPD_CR_RXMODE_Pos (4U)
8771#define UCPD_CR_RXMODE_Msk (0x1UL << UCPD_CR_RXMODE_Pos) /*!< 0x00000010 */
8772#define UCPD_CR_RXMODE UCPD_CR_RXMODE_Msk /*!< Receiver mode */
8773#define UCPD_CR_PHYRXEN_Pos (5U)
8774#define UCPD_CR_PHYRXEN_Msk (0x1UL << UCPD_CR_PHYRXEN_Pos) /*!< 0x00000020 */
8775#define UCPD_CR_PHYRXEN UCPD_CR_PHYRXEN_Msk /*!< Controls enable of USB Power Delivery receiver */
8776#define UCPD_CR_PHYCCSEL_Pos (6U)
8777#define UCPD_CR_PHYCCSEL_Msk (0x1UL << UCPD_CR_PHYCCSEL_Pos) /*!< 0x00000040 */
8778#define UCPD_CR_PHYCCSEL UCPD_CR_PHYCCSEL_Msk /*!< */
8779#define UCPD_CR_ANASUBMODE_Pos (7U)
8780#define UCPD_CR_ANASUBMODE_Msk (0x3UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000180 */
8781#define UCPD_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */
8782#define UCPD_CR_ANASUBMODE_0 (0x1UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000080 */
8783#define UCPD_CR_ANASUBMODE_1 (0x2UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000100 */
8784#define UCPD_CR_ANAMODE_Pos (9U)
8785#define UCPD_CR_ANAMODE_Msk (0x1UL << UCPD_CR_ANAMODE_Pos) /*!< 0x00000200 */
8786#define UCPD_CR_ANAMODE UCPD_CR_ANAMODE_Msk /*!< Analog PHY working mode */
8787#define UCPD_CR_CCENABLE_Pos (10U)
8788#define UCPD_CR_CCENABLE_Msk (0x3UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000C00 */
8789#define UCPD_CR_CCENABLE UCPD_CR_CCENABLE_Msk /*!< */
8790#define UCPD_CR_CCENABLE_0 (0x1UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000400 */
8791#define UCPD_CR_CCENABLE_1 (0x2UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000800 */
8792#define UCPD_CR_FRSRXEN_Pos (16U)
8793#define UCPD_CR_FRSRXEN_Msk (0x1UL << UCPD_CR_FRSRXEN_Pos) /*!< 0x00010000 */
8794#define UCPD_CR_FRSRXEN UCPD_CR_FRSRXEN_Msk /*!< Enable FRS request detection function */
8795#define UCPD_CR_FRSTX_Pos (17U)
8796#define UCPD_CR_FRSTX_Msk (0x1UL << UCPD_CR_FRSTX_Pos) /*!< 0x00020000 */
8797#define UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk /*!< Signal Fast Role Swap request */
8798#define UCPD_CR_RDCH_Pos (18U)
8799#define UCPD_CR_RDCH_Msk (0x1UL << UCPD_CR_RDCH_Pos) /*!< 0x00040000 */
8800#define UCPD_CR_RDCH UCPD_CR_RDCH_Msk /*!< */
8801#define UCPD_CR_CC1TCDIS_Pos (20U)
8802#define UCPD_CR_CC1TCDIS_Msk (0x1UL << UCPD_CR_CC1TCDIS_Pos) /*!< 0x00100000 */
8803#define UCPD_CR_CC1TCDIS UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to be disabled. */
8804#define UCPD_CR_CC2TCDIS_Pos (21U)
8805#define UCPD_CR_CC2TCDIS_Msk (0x1UL << UCPD_CR_CC2TCDIS_Pos) /*!< 0x00200000 */
8806#define UCPD_CR_CC2TCDIS UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to be disabled. */
8807
8808/******************** Bits definition for UCPD_IMR register *******************/
8809#define UCPD_IMR_TXISIE_Pos (0U)
8810#define UCPD_IMR_TXISIE_Msk (0x1UL << UCPD_IMR_TXISIE_Pos) /*!< 0x00000001 */
8811#define UCPD_IMR_TXISIE UCPD_IMR_TXISIE_Msk /*!< Enable TXIS interrupt */
8812#define UCPD_IMR_TXMSGDISCIE_Pos (1U)
8813#define UCPD_IMR_TXMSGDISCIE_Msk (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos) /*!< 0x00000002 */
8814#define UCPD_IMR_TXMSGDISCIE UCPD_IMR_TXMSGDISCIE_Msk /*!< Enable TXMSGDISC interrupt */
8815#define UCPD_IMR_TXMSGSENTIE_Pos (2U)
8816#define UCPD_IMR_TXMSGSENTIE_Msk (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos) /*!< 0x00000004 */
8817#define UCPD_IMR_TXMSGSENTIE UCPD_IMR_TXMSGSENTIE_Msk /*!< Enable TXMSGSENT interrupt */
8818#define UCPD_IMR_TXMSGABTIE_Pos (3U)
8819#define UCPD_IMR_TXMSGABTIE_Msk (0x1UL << UCPD_IMR_TXMSGABTIE_Pos) /*!< 0x00000008 */
8820#define UCPD_IMR_TXMSGABTIE UCPD_IMR_TXMSGABTIE_Msk /*!< Enable TXMSGABT interrupt */
8821#define UCPD_IMR_HRSTDISCIE_Pos (4U)
8822#define UCPD_IMR_HRSTDISCIE_Msk (0x1UL << UCPD_IMR_HRSTDISCIE_Pos) /*!< 0x00000010 */
8823#define UCPD_IMR_HRSTDISCIE UCPD_IMR_HRSTDISCIE_Msk /*!< Enable HRSTDISC interrupt */
8824#define UCPD_IMR_HRSTSENTIE_Pos (5U)
8825#define UCPD_IMR_HRSTSENTIE_Msk (0x1UL << UCPD_IMR_HRSTSENTIE_Pos) /*!< 0x00000020 */
8826#define UCPD_IMR_HRSTSENTIE UCPD_IMR_HRSTSENTIE_Msk /*!< Enable HRSTSENT interrupt */
8827#define UCPD_IMR_TXUNDIE_Pos (6U)
8828#define UCPD_IMR_TXUNDIE_Msk (0x1UL << UCPD_IMR_TXUNDIE_Pos) /*!< 0x00000040 */
8829#define UCPD_IMR_TXUNDIE UCPD_IMR_TXUNDIE_Msk /*!< Enable TXUND interrupt */
8830#define UCPD_IMR_RXNEIE_Pos (8U)
8831#define UCPD_IMR_RXNEIE_Msk (0x1UL << UCPD_IMR_RXNEIE_Pos) /*!< 0x00000100 */
8832#define UCPD_IMR_RXNEIE UCPD_IMR_RXNEIE_Msk /*!< Enable RXNE interrupt */
8833#define UCPD_IMR_RXORDDETIE_Pos (9U)
8834#define UCPD_IMR_RXORDDETIE_Msk (0x1UL << UCPD_IMR_RXORDDETIE_Pos) /*!< 0x00000200 */
8835#define UCPD_IMR_RXORDDETIE UCPD_IMR_RXORDDETIE_Msk /*!< Enable RXORDDET interrupt */
8836#define UCPD_IMR_RXHRSTDETIE_Pos (10U)
8837#define UCPD_IMR_RXHRSTDETIE_Msk (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos) /*!< 0x00000400 */
8838#define UCPD_IMR_RXHRSTDETIE UCPD_IMR_RXHRSTDETIE_Msk /*!< Enable RXHRSTDET interrupt */
8839#define UCPD_IMR_RXOVRIE_Pos (11U)
8840#define UCPD_IMR_RXOVRIE_Msk (0x1UL << UCPD_IMR_RXOVRIE_Pos) /*!< 0x00000800 */
8841#define UCPD_IMR_RXOVRIE UCPD_IMR_RXOVRIE_Msk /*!< Enable RXOVR interrupt */
8842#define UCPD_IMR_RXMSGENDIE_Pos (12U)
8843#define UCPD_IMR_RXMSGENDIE_Msk (0x1UL << UCPD_IMR_RXMSGENDIE_Pos) /*!< 0x00001000 */
8844#define UCPD_IMR_RXMSGENDIE UCPD_IMR_RXMSGENDIE_Msk /*!< Enable RXMSGEND interrupt */
8845#define UCPD_IMR_TYPECEVT1IE_Pos (14U)
8846#define UCPD_IMR_TYPECEVT1IE_Msk (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos) /*!< 0x00004000 */
8847#define UCPD_IMR_TYPECEVT1IE UCPD_IMR_TYPECEVT1IE_Msk /*!< Enable TYPECEVT1IE interrupt */
8848#define UCPD_IMR_TYPECEVT2IE_Pos (15U)
8849#define UCPD_IMR_TYPECEVT2IE_Msk (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos) /*!< 0x00008000 */
8850#define UCPD_IMR_TYPECEVT2IE UCPD_IMR_TYPECEVT2IE_Msk /*!< Enable TYPECEVT2IE interrupt */
8851#define UCPD_IMR_FRSEVTIE_Pos (20U)
8852#define UCPD_IMR_FRSEVTIE_Msk (0x1UL << UCPD_IMR_FRSEVTIE_Pos) /*!< 0x00100000 */
8853#define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk /*!< Fast Role Swap interrupt */
8854
8855/******************** Bits definition for UCPD_SR register ********************/
8856#define UCPD_SR_TXIS_Pos (0U)
8857#define UCPD_SR_TXIS_Msk (0x1UL << UCPD_SR_TXIS_Pos) /*!< 0x00000001 */
8858#define UCPD_SR_TXIS UCPD_SR_TXIS_Msk /*!< Transmit interrupt status */
8859#define UCPD_SR_TXMSGDISC_Pos (1U)
8860#define UCPD_SR_TXMSGDISC_Msk (0x1UL << UCPD_SR_TXMSGDISC_Pos) /*!< 0x00000002 */
8861#define UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC_Msk /*!< Transmit message discarded interrupt */
8862#define UCPD_SR_TXMSGSENT_Pos (2U)
8863#define UCPD_SR_TXMSGSENT_Msk (0x1UL << UCPD_SR_TXMSGSENT_Pos) /*!< 0x00000004 */
8864#define UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT_Msk /*!< Transmit message sent interrupt */
8865#define UCPD_SR_TXMSGABT_Pos (3U)
8866#define UCPD_SR_TXMSGABT_Msk (0x1UL << UCPD_SR_TXMSGABT_Pos) /*!< 0x00000008 */
8867#define UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT_Msk /*!< Transmit message abort interrupt */
8868#define UCPD_SR_HRSTDISC_Pos (4U)
8869#define UCPD_SR_HRSTDISC_Msk (0x1UL << UCPD_SR_HRSTDISC_Pos) /*!< 0x00000010 */
8870#define UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC_Msk /*!< HRST discarded interrupt */
8871#define UCPD_SR_HRSTSENT_Pos (5U)
8872#define UCPD_SR_HRSTSENT_Msk (0x1UL << UCPD_SR_HRSTSENT_Pos) /*!< 0x00000020 */
8873#define UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT_Msk /*!< HRST sent interrupt */
8874#define UCPD_SR_TXUND_Pos (6U)
8875#define UCPD_SR_TXUND_Msk (0x1UL << UCPD_SR_TXUND_Pos) /*!< 0x00000040 */
8876#define UCPD_SR_TXUND UCPD_SR_TXUND_Msk /*!< Tx data underrun condition interrupt */
8877#define UCPD_SR_RXNE_Pos (8U)
8878#define UCPD_SR_RXNE_Msk (0x1UL << UCPD_SR_RXNE_Pos) /*!< 0x00000100 */
8879#define UCPD_SR_RXNE UCPD_SR_RXNE_Msk /*!< Receive data register not empty interrupt */
8880#define UCPD_SR_RXORDDET_Pos (9U)
8881#define UCPD_SR_RXORDDET_Msk (0x1UL << UCPD_SR_RXORDDET_Pos) /*!< 0x00000200 */
8882#define UCPD_SR_RXORDDET UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected interrupt */
8883#define UCPD_SR_RXHRSTDET_Pos (10U)
8884#define UCPD_SR_RXHRSTDET_Msk (0x1UL << UCPD_SR_RXHRSTDET_Pos) /*!< 0x00000400 */
8885#define UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET_Msk /*!< Rx Hard Reset detect interrupt */
8886#define UCPD_SR_RXOVR_Pos (11U)
8887#define UCPD_SR_RXOVR_Msk (0x1UL << UCPD_SR_RXOVR_Pos) /*!< 0x00000800 */
8888#define UCPD_SR_RXOVR UCPD_SR_RXOVR_Msk /*!< Rx data overflow interrupt */
8889#define UCPD_SR_RXMSGEND_Pos (12U)
8890#define UCPD_SR_RXMSGEND_Msk (0x1UL << UCPD_SR_RXMSGEND_Pos) /*!< 0x00001000 */
8891#define UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND_Msk /*!< Rx message received */
8892#define UCPD_SR_RXERR_Pos (13U)
8893#define UCPD_SR_RXERR_Msk (0x1UL << UCPD_SR_RXERR_Pos) /*!< 0x00002000 */
8894#define UCPD_SR_RXERR UCPD_SR_RXERR_Msk /*!< RX Error */
8895#define UCPD_SR_TYPECEVT1_Pos (14U)
8896#define UCPD_SR_TYPECEVT1_Msk (0x1UL << UCPD_SR_TYPECEVT1_Pos) /*!< 0x00004000 */
8897#define UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1_Msk /*!< Type C voltage level event on CC1 */
8898#define UCPD_SR_TYPECEVT2_Pos (15U)
8899#define UCPD_SR_TYPECEVT2_Msk (0x1UL << UCPD_SR_TYPECEVT2_Pos) /*!< 0x00008000 */
8900#define UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2_Msk /*!< Type C voltage level event on CC2 */
8901#define UCPD_SR_TYPEC_VSTATE_CC1_Pos (16U)
8902#define UCPD_SR_TYPEC_VSTATE_CC1_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00030000 */
8903#define UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1_Msk /*!< Status of DC level on CC1 pin */
8904#define UCPD_SR_TYPEC_VSTATE_CC1_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00010000 */
8905#define UCPD_SR_TYPEC_VSTATE_CC1_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00020000 */
8906#define UCPD_SR_TYPEC_VSTATE_CC2_Pos (18U)
8907#define UCPD_SR_TYPEC_VSTATE_CC2_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos) /*!< 0x000C0000 */
8908#define UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2_Msk /*!<Status of DC level on CC2 pin */
8909#define UCPD_SR_TYPEC_VSTATE_CC2_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos) /*!< 0x00040000 */
8910#define UCPD_SR_TYPEC_VSTATE_CC2_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos) /*!< 0x00080000 */
8911#define UCPD_SR_FRSEVT_Pos (20U)
8912#define UCPD_SR_FRSEVT_Msk (0x1UL << UCPD_SR_FRSEVT_Pos) /*!< 0x00100000 */
8913#define UCPD_SR_FRSEVT UCPD_SR_FRSEVT_Msk /*!< Fast Role Swap detection event */
8914
8915/******************** Bits definition for UCPD_ICR register *******************/
8916#define UCPD_ICR_TXMSGDISCCF_Pos (1U)
8917#define UCPD_ICR_TXMSGDISCCF_Msk (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos) /*!< 0x00000002 */
8918#define UCPD_ICR_TXMSGDISCCF UCPD_ICR_TXMSGDISCCF_Msk /*!< Tx message discarded flag (TXMSGDISC) clear */
8919#define UCPD_ICR_TXMSGSENTCF_Pos (2U)
8920#define UCPD_ICR_TXMSGSENTCF_Msk (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos) /*!< 0x00000004 */
8921#define UCPD_ICR_TXMSGSENTCF UCPD_ICR_TXMSGSENTCF_Msk /*!< Tx message sent flag (TXMSGSENT) clear */
8922#define UCPD_ICR_TXMSGABTCF_Pos (3U)
8923#define UCPD_ICR_TXMSGABTCF_Msk (0x1UL << UCPD_ICR_TXMSGABTCF_Pos) /*!< 0x00000008 */
8924#define UCPD_ICR_TXMSGABTCF UCPD_ICR_TXMSGABTCF_Msk /*!< Tx message abort flag (TXMSGABT) clear */
8925#define UCPD_ICR_HRSTDISCCF_Pos (4U)
8926#define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */
8927#define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset discarded flag (HRSTDISC) clear */
8928#define UCPD_ICR_HRSTSENTCF_Pos (5U)
8929#define UCPD_ICR_HRSTSENTCF_Msk (0x1UL << UCPD_ICR_HRSTSENTCF_Pos) /*!< 0x00000020 */
8930#define UCPD_ICR_HRSTSENTCF UCPD_ICR_HRSTSENTCF_Msk /*!< Hard reset sent flag (HRSTSENT) clear */
8931#define UCPD_ICR_TXUNDCF_Pos (6U)
8932#define UCPD_ICR_TXUNDCF_Msk (0x1UL << UCPD_ICR_TXUNDCF_Pos) /*!< 0x00000040 */
8933#define UCPD_ICR_TXUNDCF UCPD_ICR_TXUNDCF_Msk /*!< Tx underflow flag (TXUND) clear */
8934#define UCPD_ICR_RXORDDETCF_Pos (9U)
8935#define UCPD_ICR_RXORDDETCF_Msk (0x1UL << UCPD_ICR_RXORDDETCF_Pos) /*!< 0x00000200 */
8936#define UCPD_ICR_RXORDDETCF UCPD_ICR_RXORDDETCF_Msk /*!< Rx ordered set detect flag (RXORDDET) clear */
8937#define UCPD_ICR_RXHRSTDETCF_Pos (10U)
8938#define UCPD_ICR_RXHRSTDETCF_Msk (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos) /*!< 0x00000400 */
8939#define UCPD_ICR_RXHRSTDETCF UCPD_ICR_RXHRSTDETCF_Msk /*!< Rx Hard Reset detected flag (RXHRSTDET) clear */
8940#define UCPD_ICR_RXOVRCF_Pos (11U)
8941#define UCPD_ICR_RXOVRCF_Msk (0x1UL << UCPD_ICR_RXOVRCF_Pos) /*!< 0x00000800 */
8942#define UCPD_ICR_RXOVRCF UCPD_ICR_RXOVRCF_Msk /*!< Rx overflow flag (RXOVR) clear */
8943#define UCPD_ICR_RXMSGENDCF_Pos (12U)
8944#define UCPD_ICR_RXMSGENDCF_Msk (0x1UL << UCPD_ICR_RXMSGENDCF_Pos) /*!< 0x00001000 */
8945#define UCPD_ICR_RXMSGENDCF UCPD_ICR_RXMSGENDCF_Msk /*!< Rx message received flag (RXMSGEND) clear */
8946#define UCPD_ICR_TYPECEVT1CF_Pos (14U)
8947#define UCPD_ICR_TYPECEVT1CF_Msk (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos) /*!< 0x00004000 */
8948#define UCPD_ICR_TYPECEVT1CF UCPD_ICR_TYPECEVT1CF_Msk /*!< TypeC event (CC1) flag (TYPECEVT1) clear */
8949#define UCPD_ICR_TYPECEVT2CF_Pos (15U)
8950#define UCPD_ICR_TYPECEVT2CF_Msk (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos) /*!< 0x00008000 */
8951#define UCPD_ICR_TYPECEVT2CF UCPD_ICR_TYPECEVT2CF_Msk /*!< TypeC event (CC2) flag (TYPECEVT2) clear */
8952#define UCPD_ICR_FRSEVTCF_Pos (20U)
8953#define UCPD_ICR_FRSEVTCF_Msk (0x1UL << UCPD_ICR_FRSEVTCF_Pos) /*!< 0x00100000 */
8954#define UCPD_ICR_FRSEVTCF UCPD_ICR_FRSEVTCF_Msk /*!< Fast Role Swap event flag clear */
8955
8956/******************** Bits definition for UCPD_TXORDSET register **************/
8957#define UCPD_TX_ORDSET_TXORDSET_Pos (0U)
8958#define UCPD_TX_ORDSET_TXORDSET_Msk (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos) /*!< 0x000FFFFF */
8959#define UCPD_TX_ORDSET_TXORDSET UCPD_TX_ORDSET_TXORDSET_Msk /*!< Tx Ordered Set */
8960
8961/******************** Bits definition for UCPD_TXPAYSZ register ****************/
8962#define UCPD_TX_PAYSZ_TXPAYSZ_Pos (0U)
8963#define UCPD_TX_PAYSZ_TXPAYSZ_Msk (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos) /*!< 0x000003FF */
8964#define UCPD_TX_PAYSZ_TXPAYSZ UCPD_TX_PAYSZ_TXPAYSZ_Msk /*!< Tx payload size in bytes */
8965
8966/******************** Bits definition for UCPD_TXDR register *******************/
8967#define UCPD_TXDR_TXDATA_Pos (0U)
8968#define UCPD_TXDR_TXDATA_Msk (0xFFUL << UCPD_TXDR_TXDATA_Pos) /*!< 0x000000FF */
8969#define UCPD_TXDR_TXDATA UCPD_TXDR_TXDATA_Msk /*!< Tx Data Register */
8970
8971/******************** Bits definition for UCPD_RXORDSET register **************/
8972#define UCPD_RX_ORDSET_RXORDSET_Pos (0U)
8973#define UCPD_RX_ORDSET_RXORDSET_Msk (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000007 */
8974#define UCPD_RX_ORDSET_RXORDSET UCPD_RX_ORDSET_RXORDSET_Msk /*!< Rx Ordered Set Code detected */
8975#define UCPD_RX_ORDSET_RXORDSET_0 (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000001 */
8976#define UCPD_RX_ORDSET_RXORDSET_1 (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000002 */
8977#define UCPD_RX_ORDSET_RXORDSET_2 (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000004 */
8978#define UCPD_RX_ORDSET_RXSOP3OF4_Pos (3U)
8979#define UCPD_RX_ORDSET_RXSOP3OF4_Msk (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos) /*!< 0x00000008 */
8980#define UCPD_RX_ORDSET_RXSOP3OF4 UCPD_RX_ORDSET_RXSOP3OF4_Msk /*!< Rx Ordered Set Debug indication */
8981#define UCPD_RX_ORDSET_RXSOPKINVALID_Pos (4U)
8982#define UCPD_RX_ORDSET_RXSOPKINVALID_Msk (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos) /*!< 0x00000070 */
8983#define UCPD_RX_ORDSET_RXSOPKINVALID UCPD_RX_ORDSET_RXSOPKINVALID_Msk /*!< Rx Ordered Set corrupted K-Codes (Debug) */
8984
8985/******************** Bits definition for UCPD_RXPAYSZ register ****************/
8986#define UCPD_RX_PAYSZ_RXPAYSZ_Pos (0U)
8987#define UCPD_RX_PAYSZ_RXPAYSZ_Msk (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos) /*!< 0x000003FF */
8988#define UCPD_RX_PAYSZ_RXPAYSZ UCPD_RX_PAYSZ_RXPAYSZ_Msk /*!< Rx payload size in bytes */
8989
8990/******************** Bits definition for UCPD_RXDR register *******************/
8991#define UCPD_RXDR_RXDATA_Pos (0U)
8992#define UCPD_RXDR_RXDATA_Msk (0xFFUL << UCPD_RXDR_RXDATA_Pos) /*!< 0x000000FF */
8993#define UCPD_RXDR_RXDATA UCPD_RXDR_RXDATA_Msk /*!< 8-bit receive data */
8994
8995/******************** Bits definition for UCPD_RXORDEXT1 register **************/
8996#define UCPD_RX_ORDEXT1_RXSOPX1_Pos (0U)
8997#define UCPD_RX_ORDEXT1_RXSOPX1_Msk (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos) /*!< 0x000FFFFF */
8998#define UCPD_RX_ORDEXT1_RXSOPX1 UCPD_RX_ORDEXT1_RXSOPX1_Msk /*!< RX Ordered Set Extension Register 1 */
8999
9000/******************** Bits definition for UCPD_RXORDEXT2 register **************/
9001#define UCPD_RX_ORDEXT2_RXSOPX2_Pos (0U)
9002#define UCPD_RX_ORDEXT2_RXSOPX2_Msk (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos) /*!< 0x000FFFFF */
9003#define UCPD_RX_ORDEXT2_RXSOPX2 UCPD_RX_ORDEXT2_RXSOPX2_Msk /*!< RX Ordered Set Extension Register 1 */
9004
9005
9006/** @addtogroup Exported_macros
9007 * @{
9008 */
9009
9010/******************************* ADC Instances ********************************/
9011#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
9012
9013#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
9014
9015/******************************* AES Instances ********************************/
9016#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
9017
9018/****************************** CEC Instances *********************************/
9019#define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
9020
9021/******************************** COMP Instances ******************************/
9022#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
9023 ((INSTANCE) == COMP2))
9024
9025#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
9026
9027/******************** COMP Instances with window mode capability **************/
9028#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
9029
9030/******************************* CRC Instances ********************************/
9031#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
9032
9033/******************************* DAC Instances ********************************/
9034#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
9035
9036/******************************** DMA Instances *******************************/
9037#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
9038 ((INSTANCE) == DMA1_Channel2) || \
9039 ((INSTANCE) == DMA1_Channel3) || \
9040 ((INSTANCE) == DMA1_Channel4) || \
9041 ((INSTANCE) == DMA1_Channel5) || \
9042 ((INSTANCE) == DMA1_Channel6) || \
9043 ((INSTANCE) == DMA1_Channel7))
9044
9045/******************************** DMAMUX Instances ****************************/
9046#define IS_DMAMUX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMAMUX1)
9047
9048#define IS_DMAMUX_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
9049 ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
9050 ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
9051 ((INSTANCE) == DMAMUX1_RequestGenerator3))
9052
9053/******************************* GPIO Instances *******************************/
9054#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
9055 ((INSTANCE) == GPIOB) || \
9056 ((INSTANCE) == GPIOC) || \
9057 ((INSTANCE) == GPIOD) || \
9058 ((INSTANCE) == GPIOF))
9059
9060/******************************* GPIO AF Instances ****************************/
9061#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
9062
9063/**************************** GPIO Lock Instances *****************************/
9064#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
9065 ((INSTANCE) == GPIOB) || \
9066 ((INSTANCE) == GPIOC))
9067
9068/******************************** I2C Instances *******************************/
9069#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
9070 ((INSTANCE) == I2C2))
9071
9072/******************************* RNG Instances ********************************/
9073#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
9074
9075/****************************** RTC Instances *********************************/
9076#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
9077
9078/****************************** SMBUS Instances *******************************/
9079#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
9080
9081/****************************** WAKEUP_FROMSTOP Instances *******************************/
9082#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
9083
9084/******************************** SPI Instances *******************************/
9085#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
9086 ((INSTANCE) == SPI2))
9087/******************************** SPI Instances *******************************/
9088#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
9089
9090/****************** LPTIM Instances : All supported instances *****************/
9091#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
9092 ((INSTANCE) == LPTIM2))
9093
9094/****************** LPTIM Instances : All supported instances *****************/
9095#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
9096
9097/****************** TIM Instances : All supported instances *******************/
9098#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9099 ((INSTANCE) == TIM2) || \
9100 ((INSTANCE) == TIM3) || \
9101 ((INSTANCE) == TIM6) || \
9102 ((INSTANCE) == TIM7) || \
9103 ((INSTANCE) == TIM14) || \
9104 ((INSTANCE) == TIM15) || \
9105 ((INSTANCE) == TIM16) || \
9106 ((INSTANCE) == TIM17))
9107
9108/****************** TIM Instances : supporting 32 bits counter ****************/
9109#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
9110
9111/****************** TIM Instances : supporting the break function *************/
9112#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9113 ((INSTANCE) == TIM15) || \
9114 ((INSTANCE) == TIM16) || \
9115 ((INSTANCE) == TIM17))
9116
9117/************** TIM Instances : supporting Break source selection *************/
9118#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9119 ((INSTANCE) == TIM15) || \
9120 ((INSTANCE) == TIM16) || \
9121 ((INSTANCE) == TIM17))
9122
9123/****************** TIM Instances : supporting 2 break inputs *****************/
9124#define IS_TIM_BKIN2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
9125
9126/************* TIM Instances : at least 1 capture/compare channel *************/
9127#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9128 ((INSTANCE) == TIM2) || \
9129 ((INSTANCE) == TIM3) || \
9130 ((INSTANCE) == TIM14) || \
9131 ((INSTANCE) == TIM15) || \
9132 ((INSTANCE) == TIM16) || \
9133 ((INSTANCE) == TIM17))
9134
9135/************ TIM Instances : at least 2 capture/compare channels *************/
9136#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9137 ((INSTANCE) == TIM2) || \
9138 ((INSTANCE) == TIM3) || \
9139 ((INSTANCE) == TIM15))
9140
9141/************ TIM Instances : at least 3 capture/compare channels *************/
9142#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9143 ((INSTANCE) == TIM2) || \
9144 ((INSTANCE) == TIM3))
9145
9146/************ TIM Instances : at least 4 capture/compare channels *************/
9147#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9148 ((INSTANCE) == TIM2) || \
9149 ((INSTANCE) == TIM3))
9150
9151/****************** TIM Instances : at least 5 capture/compare channels *******/
9152#define IS_TIM_CC5_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
9153
9154/****************** TIM Instances : at least 6 capture/compare channels *******/
9155#define IS_TIM_CC6_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
9156
9157/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
9158#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9159 ((INSTANCE) == TIM15) || \
9160 ((INSTANCE) == TIM16) || \
9161 ((INSTANCE) == TIM17))
9162
9163/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
9164#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9165 ((INSTANCE) == TIM2) || \
9166 ((INSTANCE) == TIM3) || \
9167 ((INSTANCE) == TIM6) || \
9168 ((INSTANCE) == TIM7) || \
9169 ((INSTANCE) == TIM15) || \
9170 ((INSTANCE) == TIM16) || \
9171 ((INSTANCE) == TIM17))
9172
9173/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
9174#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9175 ((INSTANCE) == TIM2) || \
9176 ((INSTANCE) == TIM3) || \
9177 ((INSTANCE) == TIM14) || \
9178 ((INSTANCE) == TIM15) || \
9179 ((INSTANCE) == TIM16) || \
9180 ((INSTANCE) == TIM17))
9181
9182/******************** TIM Instances : DMA burst feature ***********************/
9183#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9184 ((INSTANCE) == TIM2) || \
9185 ((INSTANCE) == TIM3) || \
9186 ((INSTANCE) == TIM15) || \
9187 ((INSTANCE) == TIM16) || \
9188 ((INSTANCE) == TIM17))
9189
9190/******************* TIM Instances : output(s) available **********************/
9191#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
9192 ((((INSTANCE) == TIM1) && \
9193 (((CHANNEL) == TIM_CHANNEL_1) || \
9194 ((CHANNEL) == TIM_CHANNEL_2) || \
9195 ((CHANNEL) == TIM_CHANNEL_3) || \
9196 ((CHANNEL) == TIM_CHANNEL_4) || \
9197 ((CHANNEL) == TIM_CHANNEL_5) || \
9198 ((CHANNEL) == TIM_CHANNEL_6))) \
9199 || \
9200 (((INSTANCE) == TIM2) && \
9201 (((CHANNEL) == TIM_CHANNEL_1) || \
9202 ((CHANNEL) == TIM_CHANNEL_2) || \
9203 ((CHANNEL) == TIM_CHANNEL_3) || \
9204 ((CHANNEL) == TIM_CHANNEL_4))) \
9205 || \
9206 (((INSTANCE) == TIM3) && \
9207 (((CHANNEL) == TIM_CHANNEL_1) || \
9208 ((CHANNEL) == TIM_CHANNEL_2) || \
9209 ((CHANNEL) == TIM_CHANNEL_3) || \
9210 ((CHANNEL) == TIM_CHANNEL_4))) \
9211 || \
9212 (((INSTANCE) == TIM14) && \
9213 (((CHANNEL) == TIM_CHANNEL_1))) \
9214 || \
9215 (((INSTANCE) == TIM15) && \
9216 (((CHANNEL) == TIM_CHANNEL_1) || \
9217 ((CHANNEL) == TIM_CHANNEL_2))) \
9218 || \
9219 (((INSTANCE) == TIM16) && \
9220 (((CHANNEL) == TIM_CHANNEL_1))) \
9221 || \
9222 (((INSTANCE) == TIM17) && \
9223 (((CHANNEL) == TIM_CHANNEL_1))))
9224
9225/****************** TIM Instances : supporting complementary output(s) ********/
9226#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
9227 ((((INSTANCE) == TIM1) && \
9228 (((CHANNEL) == TIM_CHANNEL_1) || \
9229 ((CHANNEL) == TIM_CHANNEL_2) || \
9230 ((CHANNEL) == TIM_CHANNEL_3))) \
9231 || \
9232 (((INSTANCE) == TIM15) && \
9233 ((CHANNEL) == TIM_CHANNEL_1)) \
9234 || \
9235 (((INSTANCE) == TIM16) && \
9236 ((CHANNEL) == TIM_CHANNEL_1)) \
9237 || \
9238 (((INSTANCE) == TIM17) && \
9239 ((CHANNEL) == TIM_CHANNEL_1)))
9240
9241/****************** TIM Instances : supporting clock division *****************/
9242#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9243 ((INSTANCE) == TIM2) || \
9244 ((INSTANCE) == TIM3) || \
9245 ((INSTANCE) == TIM14) || \
9246 ((INSTANCE) == TIM15) || \
9247 ((INSTANCE) == TIM16) || \
9248 ((INSTANCE) == TIM17))
9249
9250/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
9251#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9252 ((INSTANCE) == TIM2) || \
9253 ((INSTANCE) == TIM3))
9254
9255/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
9256#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9257 ((INSTANCE) == TIM2) || \
9258 ((INSTANCE) == TIM3))
9259
9260/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
9261#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9262 ((INSTANCE) == TIM2) || \
9263 ((INSTANCE) == TIM3) || \
9264 ((INSTANCE) == TIM15))
9265
9266/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
9267#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9268 ((INSTANCE) == TIM2) || \
9269 ((INSTANCE) == TIM3) || \
9270 ((INSTANCE) == TIM15))
9271
9272/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
9273#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
9274
9275/****************** TIM Instances : supporting commutation event generation ***/
9276#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9277 ((INSTANCE) == TIM15) || \
9278 ((INSTANCE) == TIM16) || \
9279 ((INSTANCE) == TIM17))
9280
9281/****************** TIM Instances : supporting counting mode selection ********/
9282#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9283 ((INSTANCE) == TIM2) || \
9284 ((INSTANCE) == TIM3))
9285
9286/****************** TIM Instances : supporting encoder interface **************/
9287#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9288 ((INSTANCE) == TIM2) || \
9289 ((INSTANCE) == TIM3))
9290
9291/****************** TIM Instances : supporting Hall sensor interface **********/
9292#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9293 ((INSTANCE) == TIM2) || \
9294 ((INSTANCE) == TIM3))
9295
9296/**************** TIM Instances : external trigger input available ************/
9297#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9298 ((INSTANCE) == TIM2) || \
9299 ((INSTANCE) == TIM3))
9300
9301/************* TIM Instances : supporting ETR source selection ***************/
9302#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9303 ((INSTANCE) == TIM2) || \
9304 ((INSTANCE) == TIM3))
9305
9306/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
9307#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9308 ((INSTANCE) == TIM2) || \
9309 ((INSTANCE) == TIM3) || \
9310 ((INSTANCE) == TIM6) || \
9311 ((INSTANCE) == TIM7) || \
9312 ((INSTANCE) == TIM15))
9313
9314/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
9315#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9316 ((INSTANCE) == TIM2) || \
9317 ((INSTANCE) == TIM3) || \
9318 ((INSTANCE) == TIM15))
9319
9320/****************** TIM Instances : supporting OCxREF clear *******************/
9321#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9322 ((INSTANCE) == TIM2) || \
9323 ((INSTANCE) == TIM3))
9324
9325/****************** TIM Instances : remapping capability **********************/
9326#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9327 ((INSTANCE) == TIM2) || \
9328 ((INSTANCE) == TIM3))
9329
9330/****************** TIM Instances : supporting repetition counter *************/
9331#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9332 ((INSTANCE) == TIM15) || \
9333 ((INSTANCE) == TIM16) || \
9334 ((INSTANCE) == TIM17))
9335
9336/****************** TIM Instances : supporting synchronization ****************/
9337#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
9338
9339/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
9340#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
9341
9342/******************* TIM Instances : Timer input XOR function *****************/
9343#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9344 ((INSTANCE) == TIM2) || \
9345 ((INSTANCE) == TIM3) || \
9346 ((INSTANCE) == TIM15))
9347
9348/******************* TIM Instances : Timer input selection ********************/
9349#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9350 ((INSTANCE) == TIM2) || \
9351 ((INSTANCE) == TIM3) || \
9352 ((INSTANCE) == TIM14) || \
9353 ((INSTANCE) == TIM15) || \
9354 ((INSTANCE) == TIM16) || \
9355 ((INSTANCE) == TIM17))
9356
9357/************ TIM Instances : Advanced timers ********************************/
9358#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
9359
9360/******************** UART Instances : Asynchronous mode **********************/
9361#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9362 ((INSTANCE) == USART2) || \
9363 ((INSTANCE) == USART3) || \
9364 ((INSTANCE) == USART4))
9365
9366
9367/******************** USART Instances : Synchronous mode **********************/
9368#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9369 ((INSTANCE) == USART2) || \
9370 ((INSTANCE) == USART3) || \
9371 ((INSTANCE) == USART4))
9372
9373/****************** UART Instances : Hardware Flow control ********************/
9374#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9375 ((INSTANCE) == USART2) || \
9376 ((INSTANCE) == USART3) || \
9377 ((INSTANCE) == USART4) || \
9378 ((INSTANCE) == LPUART1))
9379
9380
9381/********************* USART Instances : Smard card mode ***********************/
9382#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9383 ((INSTANCE) == USART2))
9384
9385/****************** UART Instances : Auto Baud Rate detection ****************/
9386#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9387 ((INSTANCE) == USART2))
9388
9389/******************** UART Instances : Half-Duplex mode **********************/
9390#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9391 ((INSTANCE) == USART2) || \
9392 ((INSTANCE) == USART3) || \
9393 ((INSTANCE) == USART4) || \
9394 ((INSTANCE) == LPUART1))
9395
9396/******************** UART Instances : LIN mode **********************/
9397#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9398 ((INSTANCE) == USART2))
9399
9400/******************** UART Instances : Wake-up from Stop mode **********************/
9401#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9402 ((INSTANCE) == USART2) || \
9403 ((INSTANCE) == LPUART1))
9404
9405/****************** UART Instances : Driver Enable *****************/
9406#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9407 ((INSTANCE) == USART2) || \
9408 ((INSTANCE) == USART3) || \
9409 ((INSTANCE) == USART4) || \
9410 ((INSTANCE) == LPUART1))
9411
9412
9413/****************** UART Instances : SPI Slave selection mode ***************/
9414#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9415 ((INSTANCE) == USART2) || \
9416 ((INSTANCE) == USART3) || \
9417 ((INSTANCE) == USART4))
9418
9419
9420/****************** UART Instances : Driver Enable *****************/
9421#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9422 ((INSTANCE) == USART2) || \
9423 ((INSTANCE) == LPUART1))
9424
9425/*********************** UART Instances : IRDA mode ***************************/
9426#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9427 ((INSTANCE) == USART2))
9428
9429/******************** LPUART Instance *****************************************/
9430#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
9431
9432/****************************** IWDG Instances ********************************/
9433#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
9434
9435/****************************** WWDG Instances ********************************/
9436#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
9437
9438/****************************** UCPD Instances ********************************/
9439#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1) || \
9440 ((INSTANCE) == UCPD2))
9441
9442/**
9443 * @}
9444 */
9445
9446 /**
9447 * @}
9448 */
9449
9450/**
9451 * @}
9452 */
9453
9454#ifdef __cplusplus
9455}
9456#endif /* __cplusplus */
9457
9458#endif /* STM32G081xx_H */
9459
9460/**
9461 * @}
9462 */
9463
9464 /**
9465 * @}
9466 */
9467
9468/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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