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diff --git a/lib/chibios/os/common/ext/ST/STM32H7xx/stm32h747xx.h b/lib/chibios/os/common/ext/ST/STM32H7xx/stm32h747xx.h
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1/**
2 ******************************************************************************
3 * @file stm32h747xx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32H747xx Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
16 * All rights reserved.</center></h2>
17 *
18 * This software component is licensed by ST under BSD 3-Clause license,
19 * the "License"; You may not use this file except in compliance with the
20 * License. You may obtain a copy of the License at:
21 * opensource.org/licenses/BSD-3-Clause
22 *
23 ******************************************************************************
24 */
25
26/** @addtogroup CMSIS_Device
27 * @{
28 */
29
30/** @addtogroup stm32h747xx
31 * @{
32 */
33
34#ifndef STM32H747xx_H
35#define STM32H747xx_H
36
37#ifdef __cplusplus
38 extern "C" {
39#endif /* __cplusplus */
40
41/** @addtogroup Peripheral_interrupt_number_definition
42 * @{
43 */
44
45/**
46 * @brief STM32H7XX Interrupt Number Definition, according to the selected device
47 * in @ref Library_configuration_section
48 */
49typedef enum
50{
51/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
52 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
53 HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
54 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
55 BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
56 UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
57 SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
58 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */
59 PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
60 SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
61/****** STM32 specific Interrupt Numbers **********************************************************************/
62 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
63 PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */
64 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
65 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
66 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
67 RCC_IRQn = 5, /*!< RCC global Interrupt */
68 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
69 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
70 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
71 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
72 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
73 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
74 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
75 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
76 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
77 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
78 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
79 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
80 ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */
81 FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */
82 FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */
83 FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */
84 FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */
85 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
86 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
87 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
88 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
89 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
90 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
91 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
92 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
93 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
94 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
95 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
96 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
97 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
98 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
99 USART1_IRQn = 37, /*!< USART1 global Interrupt */
100 USART2_IRQn = 38, /*!< USART2 global Interrupt */
101 USART3_IRQn = 39, /*!< USART3 global Interrupt */
102 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
103 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
104 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
105 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
106 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
107 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
108 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
109 FMC_IRQn = 48, /*!< FMC global Interrupt */
110 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
111 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
112 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
113 UART4_IRQn = 52, /*!< UART4 global Interrupt */
114 UART5_IRQn = 53, /*!< UART5 global Interrupt */
115 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
116 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
117 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
118 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
119 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
120 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
121 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
122 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
123 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
124 FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */
125 CM7_SEV_IRQn = 64, /*!< CM7 Send event interrupt for CM4 */
126 CM4_SEV_IRQn = 65, /*!< CM4 Send event interrupt for CM7 */
127 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
128 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
129 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
130 USART6_IRQn = 71, /*!< USART6 global interrupt */
131 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
132 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
133 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
134 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
135 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
136 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
137 DCMI_IRQn = 78, /*!< DCMI global interrupt */
138 RNG_IRQn = 80, /*!< RNG global interrupt */
139 FPU_IRQn = 81, /*!< FPU global interrupt */
140 UART7_IRQn = 82, /*!< UART7 global interrupt */
141 UART8_IRQn = 83, /*!< UART8 global interrupt */
142 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
143 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
144 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
145 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
146 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
147 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
148 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
149 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
150 QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
151 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
152 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
153 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
154 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
155 SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
156 OTG_FS_EP1_OUT_IRQn = 98, /*!< USB OTG HS2 global interrupt */
157 OTG_FS_EP1_IN_IRQn = 99, /*!< USB OTG HS2 End Point 1 Out global interrupt */
158 OTG_FS_WKUP_IRQn = 100, /*!< USB OTG HS2 End Point 1 In global interrupt */
159 OTG_FS_IRQn = 101, /*!< USB OTG HS2 Wakeup through EXTI interrupt */
160 DMAMUX1_OVR_IRQn = 102, /*!<DMAMUX1 Overrun interrupt */
161 HRTIM1_Master_IRQn = 103, /*!< HRTIM Master Timer global Interrupts */
162 HRTIM1_TIMA_IRQn = 104, /*!< HRTIM Timer A global Interrupt */
163 HRTIM1_TIMB_IRQn = 105, /*!< HRTIM Timer B global Interrupt */
164 HRTIM1_TIMC_IRQn = 106, /*!< HRTIM Timer C global Interrupt */
165 HRTIM1_TIMD_IRQn = 107, /*!< HRTIM Timer D global Interrupt */
166 HRTIM1_TIME_IRQn = 108, /*!< HRTIM Timer E global Interrupt */
167 HRTIM1_FLT_IRQn = 109, /*!< HRTIM Fault global Interrupt */
168 DFSDM1_FLT0_IRQn = 110, /*!<DFSDM Filter1 Interrupt */
169 DFSDM1_FLT1_IRQn = 111, /*!<DFSDM Filter2 Interrupt */
170 DFSDM1_FLT2_IRQn = 112, /*!<DFSDM Filter3 Interrupt */
171 DFSDM1_FLT3_IRQn = 113, /*!<DFSDM Filter4 Interrupt */
172 SAI3_IRQn = 114, /*!< SAI3 global Interrupt */
173 SWPMI1_IRQn = 115, /*!< Serial Wire Interface 1 global interrupt */
174 TIM15_IRQn = 116, /*!< TIM15 global Interrupt */
175 TIM16_IRQn = 117, /*!< TIM16 global Interrupt */
176 TIM17_IRQn = 118, /*!< TIM17 global Interrupt */
177 MDIOS_WKUP_IRQn = 119, /*!< MDIOS Wakeup Interrupt */
178 MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */
179 JPEG_IRQn = 121, /*!< JPEG global Interrupt */
180 MDMA_IRQn = 122, /*!< MDMA global Interrupt */
181 DSI_IRQn = 123, /*!< DSI global Interrupt */
182 SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */
183 HSEM1_IRQn = 125, /*!< HSEM1 global Interrupt */
184 HSEM2_IRQn = 126, /*!< HSEM2 global Interrupt */
185 ADC3_IRQn = 127, /*!< ADC3 global Interrupt */
186 DMAMUX2_OVR_IRQn = 128, /*!<DMAMUX2 Overrun interrupt */
187 BDMA_Channel0_IRQn = 129, /*!< BDMA Channel 0 global Interrupt */
188 BDMA_Channel1_IRQn = 130, /*!< BDMA Channel 1 global Interrupt */
189 BDMA_Channel2_IRQn = 131, /*!< BDMA Channel 2 global Interrupt */
190 BDMA_Channel3_IRQn = 132, /*!< BDMA Channel 3 global Interrupt */
191 BDMA_Channel4_IRQn = 133, /*!< BDMA Channel 4 global Interrupt */
192 BDMA_Channel5_IRQn = 134, /*!< BDMA Channel 5 global Interrupt */
193 BDMA_Channel6_IRQn = 135, /*!< BDMA Channel 6 global Interrupt */
194 BDMA_Channel7_IRQn = 136, /*!< BDMA Channel 7 global Interrupt */
195 COMP_IRQn = 137 , /*!< COMP global Interrupt */
196 LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */
197 LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */
198 LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */
199 LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */
200 LPUART1_IRQn = 142, /*!< LP UART1 interrupt */
201 WWDG_RST_IRQn = 143, /*!<Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */
202 CRS_IRQn = 144, /*!< Clock Recovery Global Interrupt */
203 ECC_IRQn = 145, /*!< ECC diagnostic Global Interrupt */
204 SAI4_IRQn = 146, /*!< SAI4 global interrupt */
205 HOLD_CORE_IRQn = 148, /*!< Hold core interrupt */
206 WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */
207} IRQn_Type;
208
209/**
210 * @}
211 */
212
213/** @addtogroup Configuration_section_for_CMSIS
214 * @{
215 */
216#define DUAL_CORE /*!< Dual core line feature */
217
218#define SMPS /*!< Switched mode power supply feature */
219
220
221
222/**
223 * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals
224 */
225#ifdef CORE_CM4
226#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
227#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */
228#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */
229#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
230#define __FPU_PRESENT 1 /*!< FPU present */
231
232#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
233#else /* CORE_CM7 */
234#ifdef CORE_CM7
235#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
236#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
237#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
238#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
239#define __FPU_PRESENT 1 /*!< FPU present */
240#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
241#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
242#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
243#else /* UNKNOWN_CORE */
244#error Please #define CORE_CM4 or CORE_CM7
245#endif /* CORE_CM7 */
246#endif /* CORE_CM4 */
247
248/**
249 * @}
250 */
251
252
253
254
255
256#include "system_stm32h7xx.h"
257#include <stdint.h>
258
259/** @addtogroup Peripheral_registers_structures
260 * @{
261 */
262
263/**
264 * @brief Analog to Digital Converter
265 */
266
267typedef struct
268{
269 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
270 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
271 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
272 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
273 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
274 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
275 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
276 __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */
277 __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
278 __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
279 uint32_t RESERVED1; /*!< Reserved, 0x028 */
280 uint32_t RESERVED2; /*!< Reserved, 0x02C */
281 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
282 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
283 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
284 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
285 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
286 uint32_t RESERVED3; /*!< Reserved, 0x044 */
287 uint32_t RESERVED4; /*!< Reserved, 0x048 */
288 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
289 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
290 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
291 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
292 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
293 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
294 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
295 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
296 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
297 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
298 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
299 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
300 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
301 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
302 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
303 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
304 __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */
305 __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */
306 __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */
307 __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */
308 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */
309 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */
310 __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */
311} ADC_TypeDef;
312
313
314typedef struct
315{
316__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
317uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
318__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
319__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
320__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
321
322} ADC_Common_TypeDef;
323
324/**
325 * @brief ART
326 */
327
328typedef struct
329{
330 __IO uint32_t CTR; /*!< ART accelerator - control register */
331}ART_TypeDef;
332
333/**
334 * @brief VREFBUF
335 */
336
337typedef struct
338{
339 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
340 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
341} VREFBUF_TypeDef;
342
343
344/**
345 * @brief FD Controller Area Network
346 */
347
348typedef struct
349{
350 __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
351 __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
352 __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */
353 __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
354 __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
355 __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
356 __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
357 __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
358 __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
359 __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
360 __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
361 __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
362 __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
363 __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
364 __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
365 __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
366 __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */
367 __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
368 __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
369 __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
370 __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
371 __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
372 __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
373 __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */
374 __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */
375 __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */
376 __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */
377 __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */
378 __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */
379 __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */
380 __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */
381 __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */
382 __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */
383 __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */
384 __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */
385 __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */
386 __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */
387 __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */
388 __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
389 __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
390 __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */
391 __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */
392 __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */
393 __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */
394 __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */
395 __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */
396 __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */
397 __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
398 __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */
399 __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */
400 __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */
401 __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */
402 __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */
403} FDCAN_GlobalTypeDef;
404
405/**
406 * @brief TTFD Controller Area Network
407 */
408
409typedef struct
410{
411 __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */
412 __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */
413 __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */
414 __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */
415 __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */
416 __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */
417 __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */
418 __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */
419 __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */
420 __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */
421 __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */
422 __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */
423 __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */
424 __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */
425 __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */
426 __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */
427 __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */
428 __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */
429 __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */
430} TTCAN_TypeDef;
431
432/**
433 * @brief FD Controller Area Network
434 */
435
436typedef struct
437{
438 __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
439 __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */
440 __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */
441 __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */
442 __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */
443 __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */
444} FDCAN_ClockCalibrationUnit_TypeDef;
445
446
447/**
448 * @brief Consumer Electronics Control
449 */
450
451typedef struct
452{
453 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
454 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
455 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
456 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
457 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
458 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
459}CEC_TypeDef;
460
461/**
462 * @brief CRC calculation unit
463 */
464
465typedef struct
466{
467 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
468 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
469 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
470 uint32_t RESERVED2; /*!< Reserved, 0x0C */
471 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
472 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
473} CRC_TypeDef;
474
475
476/**
477 * @brief Clock Recovery System
478 */
479typedef struct
480{
481__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
482__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
483__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
484__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
485} CRS_TypeDef;
486
487
488/**
489 * @brief Digital to Analog Converter
490 */
491
492typedef struct
493{
494 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
495 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
496 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
497 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
498 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
499 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
500 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
501 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
502 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
503 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
504 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
505 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
506 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
507 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
508 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
509 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
510 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
511 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
512 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
513 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
514} DAC_TypeDef;
515
516/**
517 * @brief DFSDM module registers
518 */
519typedef struct
520{
521 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
522 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
523 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
524 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
525 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
526 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
527 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
528 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
529 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
530 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
531 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
532 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
533 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
534 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
535 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
536} DFSDM_Filter_TypeDef;
537
538/**
539 * @brief DFSDM channel configuration registers
540 */
541typedef struct
542{
543 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
544 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
545 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
546 short circuit detector register, Address offset: 0x08 */
547 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
548 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
549} DFSDM_Channel_TypeDef;
550
551/**
552 * @brief Debug MCU
553 */
554typedef struct
555{
556 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
557 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
558 __IO uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */
559 __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */
560 __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register, Address offset: 0x38 */
561 __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */
562 __IO uint32_t APB1LFZ2; /*!< Debug MCU APB1LFZ2 freeze register, Address offset: 0x40 */
563 __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */
564 __IO uint32_t APB1HFZ2; /*!< Debug MCU APB1LFZ2 freeze register, Address offset: 0x48 */
565 __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */
566 __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register, Address offset: 0x50 */
567 __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */
568 __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register, Address offset: 0x58 */
569
570}DBGMCU_TypeDef;
571/**
572 * @brief DCMI
573 */
574
575typedef struct
576{
577 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
578 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
579 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
580 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
581 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
582 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
583 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
584 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
585 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
586 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
587 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
588} DCMI_TypeDef;
589
590/**
591 * @brief DMA Controller
592 */
593
594typedef struct
595{
596 __IO uint32_t CR; /*!< DMA stream x configuration register */
597 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
598 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
599 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
600 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
601 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
602} DMA_Stream_TypeDef;
603
604typedef struct
605{
606 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
607 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
608 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
609 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
610} DMA_TypeDef;
611
612typedef struct
613{
614 __IO uint32_t CCR; /*!< DMA channel x configuration register */
615 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
616 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
617 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */
618 __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */
619} BDMA_Channel_TypeDef;
620
621typedef struct
622{
623 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
624 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
625} BDMA_TypeDef;
626
627typedef struct
628{
629 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */
630}DMAMUX_Channel_TypeDef;
631
632typedef struct
633{
634 __IO uint32_t CSR; /*!< DMA Channel Status Register */
635 __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */
636}DMAMUX_ChannelStatus_TypeDef;
637
638typedef struct
639{
640 __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */
641}DMAMUX_RequestGen_TypeDef;
642
643typedef struct
644{
645 __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */
646 __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */
647}DMAMUX_RequestGenStatus_TypeDef;
648
649/**
650 * @brief MDMA Controller
651 */
652typedef struct
653{
654 __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */
655}MDMA_TypeDef;
656
657typedef struct
658{
659 __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */
660 __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */
661 __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */
662 __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */
663 __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */
664 __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */
665 __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */
666 __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */
667 __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
668 __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
669 __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
670 uint32_t RESERVED0; /*!< Reserved, 0x68 */
671 __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
672 __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
673}MDMA_Channel_TypeDef;
674
675/**
676 * @brief DMA2D Controller
677 */
678
679typedef struct
680{
681 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
682 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
683 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
684 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
685 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
686 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
687 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
688 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
689 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
690 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
691 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
692 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
693 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
694 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
695 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
696 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
697 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
698 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
699 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
700 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
701 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
702 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
703 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
704} DMA2D_TypeDef;
705
706/**
707 * @brief DSI Controller
708 */
709
710typedef struct
711{
712 __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */
713 __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */
714 __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */
715 __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */
716 __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */
717 __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */
718 __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */
719 uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */
720 __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */
721 __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */
722 __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */
723 __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */
724 __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */
725 __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */
726 __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */
727 __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */
728 __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */
729 __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */
730 __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */
731 __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */
732 __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */
733 __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */
734 __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */
735 __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */
736 __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */
737 __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */
738 __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */
739 __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
740 __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */
741 __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */
742 __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */
743 __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */
744 __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */
745 __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */
746 __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */
747 __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */
748 __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */
749 uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */
750 __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
751 __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
752 uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */
753 __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
754 uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */
755 __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */
756 uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */
757 __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */
758 __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */
759 uint32_t RESERVED5; /*!< Reserved, 0x114 */
760 __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */
761 uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
762 __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
763 __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
764 __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
765 __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
766 __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
767 __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
768 __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */
769 __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */
770 __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */
771 __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */
772 __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */
773 uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */
774 __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */
775 uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */
776 __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */
777 __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */
778 __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */
779 __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */
780 __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */
781 uint32_t RESERVED9; /*!< Reserved, 0x414 */
782 __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */
783 uint32_t RESERVED10; /*!< Reserved, 0x42C */
784 __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */
785} DSI_TypeDef;
786
787/**
788 * @brief Ethernet MAC
789 */
790typedef struct
791{
792 __IO uint32_t MACCR;
793 __IO uint32_t MACECR;
794 __IO uint32_t MACPFR;
795 __IO uint32_t MACWTR;
796 __IO uint32_t MACHT0R;
797 __IO uint32_t MACHT1R;
798 uint32_t RESERVED1[14];
799 __IO uint32_t MACVTR;
800 uint32_t RESERVED2;
801 __IO uint32_t MACVHTR;
802 uint32_t RESERVED3;
803 __IO uint32_t MACVIR;
804 __IO uint32_t MACIVIR;
805 uint32_t RESERVED4[2];
806 __IO uint32_t MACTFCR;
807 uint32_t RESERVED5[7];
808 __IO uint32_t MACRFCR;
809 uint32_t RESERVED6[7];
810 __IO uint32_t MACISR;
811 __IO uint32_t MACIER;
812 __IO uint32_t MACRXTXSR;
813 uint32_t RESERVED7;
814 __IO uint32_t MACPCSR;
815 __IO uint32_t MACRWKPFR;
816 uint32_t RESERVED8[2];
817 __IO uint32_t MACLCSR;
818 __IO uint32_t MACLTCR;
819 __IO uint32_t MACLETR;
820 __IO uint32_t MAC1USTCR;
821 uint32_t RESERVED9[12];
822 __IO uint32_t MACVR;
823 __IO uint32_t MACDR;
824 uint32_t RESERVED10;
825 __IO uint32_t MACHWF0R;
826 __IO uint32_t MACHWF1R;
827 __IO uint32_t MACHWF2R;
828 uint32_t RESERVED11[54];
829 __IO uint32_t MACMDIOAR;
830 __IO uint32_t MACMDIODR;
831 uint32_t RESERVED12[2];
832 __IO uint32_t MACARPAR;
833 uint32_t RESERVED13[59];
834 __IO uint32_t MACA0HR;
835 __IO uint32_t MACA0LR;
836 __IO uint32_t MACA1HR;
837 __IO uint32_t MACA1LR;
838 __IO uint32_t MACA2HR;
839 __IO uint32_t MACA2LR;
840 __IO uint32_t MACA3HR;
841 __IO uint32_t MACA3LR;
842 uint32_t RESERVED14[248];
843 __IO uint32_t MMCCR;
844 __IO uint32_t MMCRIR;
845 __IO uint32_t MMCTIR;
846 __IO uint32_t MMCRIMR;
847 __IO uint32_t MMCTIMR;
848 uint32_t RESERVED15[14];
849 __IO uint32_t MMCTSCGPR;
850 __IO uint32_t MMCTMCGPR;
851 uint32_t RESERVED16[5];
852 __IO uint32_t MMCTPCGR;
853 uint32_t RESERVED17[10];
854 __IO uint32_t MMCRCRCEPR;
855 __IO uint32_t MMCRAEPR;
856 uint32_t RESERVED18[10];
857 __IO uint32_t MMCRUPGR;
858 uint32_t RESERVED19[9];
859 __IO uint32_t MMCTLPIMSTR;
860 __IO uint32_t MMCTLPITCR;
861 __IO uint32_t MMCRLPIMSTR;
862 __IO uint32_t MMCRLPITCR;
863 uint32_t RESERVED20[65];
864 __IO uint32_t MACL3L4C0R;
865 __IO uint32_t MACL4A0R;
866 uint32_t RESERVED21[2];
867 __IO uint32_t MACL3A0R0R;
868 __IO uint32_t MACL3A1R0R;
869 __IO uint32_t MACL3A2R0R;
870 __IO uint32_t MACL3A3R0R;
871 uint32_t RESERVED22[4];
872 __IO uint32_t MACL3L4C1R;
873 __IO uint32_t MACL4A1R;
874 uint32_t RESERVED23[2];
875 __IO uint32_t MACL3A0R1R;
876 __IO uint32_t MACL3A1R1R;
877 __IO uint32_t MACL3A2R1R;
878 __IO uint32_t MACL3A3R1R;
879 uint32_t RESERVED24[108];
880 __IO uint32_t MACTSCR;
881 __IO uint32_t MACSSIR;
882 __IO uint32_t MACSTSR;
883 __IO uint32_t MACSTNR;
884 __IO uint32_t MACSTSUR;
885 __IO uint32_t MACSTNUR;
886 __IO uint32_t MACTSAR;
887 uint32_t RESERVED25;
888 __IO uint32_t MACTSSR;
889 uint32_t RESERVED26[3];
890 __IO uint32_t MACTTSSNR;
891 __IO uint32_t MACTTSSSR;
892 uint32_t RESERVED27[2];
893 __IO uint32_t MACACR;
894 uint32_t RESERVED28;
895 __IO uint32_t MACATSNR;
896 __IO uint32_t MACATSSR;
897 __IO uint32_t MACTSIACR;
898 __IO uint32_t MACTSEACR;
899 __IO uint32_t MACTSICNR;
900 __IO uint32_t MACTSECNR;
901 uint32_t RESERVED29[4];
902 __IO uint32_t MACPPSCR;
903 uint32_t RESERVED30[3];
904 __IO uint32_t MACPPSTTSR;
905 __IO uint32_t MACPPSTTNR;
906 __IO uint32_t MACPPSIR;
907 __IO uint32_t MACPPSWR;
908 uint32_t RESERVED31[12];
909 __IO uint32_t MACPOCR;
910 __IO uint32_t MACSPI0R;
911 __IO uint32_t MACSPI1R;
912 __IO uint32_t MACSPI2R;
913 __IO uint32_t MACLMIR;
914 uint32_t RESERVED32[11];
915 __IO uint32_t MTLOMR;
916 uint32_t RESERVED33[7];
917 __IO uint32_t MTLISR;
918 uint32_t RESERVED34[55];
919 __IO uint32_t MTLTQOMR;
920 __IO uint32_t MTLTQUR;
921 __IO uint32_t MTLTQDR;
922 uint32_t RESERVED35[8];
923 __IO uint32_t MTLQICSR;
924 __IO uint32_t MTLRQOMR;
925 __IO uint32_t MTLRQMPOCR;
926 __IO uint32_t MTLRQDR;
927 uint32_t RESERVED36[177];
928 __IO uint32_t DMAMR;
929 __IO uint32_t DMASBMR;
930 __IO uint32_t DMAISR;
931 __IO uint32_t DMADSR;
932 uint32_t RESERVED37[60];
933 __IO uint32_t DMACCR;
934 __IO uint32_t DMACTCR;
935 __IO uint32_t DMACRCR;
936 uint32_t RESERVED38[2];
937 __IO uint32_t DMACTDLAR;
938 uint32_t RESERVED39;
939 __IO uint32_t DMACRDLAR;
940 __IO uint32_t DMACTDTPR;
941 uint32_t RESERVED40;
942 __IO uint32_t DMACRDTPR;
943 __IO uint32_t DMACTDRLR;
944 __IO uint32_t DMACRDRLR;
945 __IO uint32_t DMACIER;
946 __IO uint32_t DMACRIWTR;
947__IO uint32_t DMACSFCSR;
948 uint32_t RESERVED41;
949 __IO uint32_t DMACCATDR;
950 uint32_t RESERVED42;
951 __IO uint32_t DMACCARDR;
952 uint32_t RESERVED43;
953 __IO uint32_t DMACCATBR;
954 uint32_t RESERVED44;
955 __IO uint32_t DMACCARBR;
956 __IO uint32_t DMACSR;
957uint32_t RESERVED45[2];
958__IO uint32_t DMACMFCR;
959}ETH_TypeDef;
960/**
961 * @brief External Interrupt/Event Controller
962 */
963
964typedef struct
965{
966__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */
967__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */
968__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */
969__IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */
970__IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */
971__IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */
972uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */
973__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */
974__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */
975__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */
976__IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */
977__IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */
978__IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */
979uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */
980__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */
981__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */
982__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */
983__IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */
984__IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */
985__IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */
986uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */
987__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */
988__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */
989__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */
990uint32_t RESERVED4; /*!< Reserved, 0x8C */
991__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */
992__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */
993__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */
994uint32_t RESERVED5; /*!< Reserved, 0x9C */
995__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */
996__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */
997__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
998uint32_t RESERVED6[5]; /*!< Reserved, 0xAC to 0xBC */
999__IO uint32_t C2IMR1; /*!< EXTI Interrupt mask register, Address offset: 0xC0 */
1000__IO uint32_t C2EMR1; /*!< EXTI Event mask register, Address offset: 0xC4 */
1001__IO uint32_t C2PR1; /*!< EXTI Pending register, Address offset: 0xC8 */
1002uint32_t RESERVED7; /*!< Reserved, 0xCC */
1003__IO uint32_t C2IMR2; /*!< EXTI Interrupt mask register, Address offset: 0xD0 */
1004__IO uint32_t C2EMR2; /*!< EXTI Event mask register, Address offset: 0xD4 */
1005__IO uint32_t C2PR2; /*!< EXTI Pending register, Address offset: 0xD8 */
1006uint32_t RESERVED8; /*!< Reserved, 0xDC */
1007__IO uint32_t C2IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xE0 */
1008__IO uint32_t C2EMR3; /*!< EXTI Event mask register, Address offset: 0xE4 */
1009__IO uint32_t C2PR3; /*!< EXTI Pending register, Address offset: 0xE8 */
1010
1011}EXTI_TypeDef;
1012
1013typedef struct
1014{
1015__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
1016__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */
1017__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */
1018uint32_t RESERVED1; /*!< Reserved, 0x0C */
1019__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */
1020__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */
1021__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */
1022uint32_t RESERVED2; /*!< Reserved, 0x1C */
1023__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
1024__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */
1025__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */
1026}EXTI_Core_TypeDef;
1027
1028
1029/**
1030 * @brief FLASH Registers
1031 */
1032
1033typedef struct
1034{
1035 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
1036 __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */
1037 __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */
1038 __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */
1039 __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */
1040 __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */
1041 __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */
1042 __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */
1043 __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */
1044 __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */
1045 __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */
1046 __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */
1047 __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */
1048 __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */
1049 __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */
1050 __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */
1051 __IO uint32_t BOOT7_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */
1052 __IO uint32_t BOOT7_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */
1053 __IO uint32_t BOOT4_CUR; /*!< Flash Current Boot Address for M4 Core Register, Address offset: 0x48 */
1054 __IO uint32_t BOOT4_PRG; /*!< Flash Boot Address to Program for M4 Core Register, Address offset: 0x4C */
1055 __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */
1056 __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */
1057 __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */
1058 __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */
1059 __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */
1060 uint32_t RESERVED1[40]; /*!< Reserved, 0x64 to 0x100 */
1061 __IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */
1062 uint32_t RESERVED2; /*!< Reserved, 0x108 */
1063 __IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */
1064 __IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */
1065 __IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */
1066 uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */
1067 __IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */
1068 __IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */
1069 __IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */
1070 __IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */
1071 __IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */
1072 __IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */
1073 uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */
1074 __IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */
1075 __IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */
1076 __IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */
1077 __IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */
1078 __IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */
1079} FLASH_TypeDef;
1080
1081/**
1082 * @brief Flexible Memory Controller
1083 */
1084
1085typedef struct
1086{
1087 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
1088} FMC_Bank1_TypeDef;
1089
1090/**
1091 * @brief Flexible Memory Controller Bank1E
1092 */
1093
1094typedef struct
1095{
1096 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
1097} FMC_Bank1E_TypeDef;
1098
1099/**
1100 * @brief Flexible Memory Controller Bank2
1101 */
1102
1103typedef struct
1104{
1105 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
1106 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
1107 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
1108 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
1109 uint32_t RESERVED0; /*!< Reserved, 0x70 */
1110 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
1111} FMC_Bank2_TypeDef;
1112
1113/**
1114 * @brief Flexible Memory Controller Bank3
1115 */
1116
1117typedef struct
1118{
1119 __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */
1120 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
1121 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
1122 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
1123 uint32_t RESERVED; /*!< Reserved, 0x90 */
1124 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
1125} FMC_Bank3_TypeDef;
1126
1127/**
1128 * @brief Flexible Memory Controller Bank5 and 6
1129 */
1130
1131
1132typedef struct
1133{
1134 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
1135 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
1136 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
1137 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
1138 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
1139} FMC_Bank5_6_TypeDef;
1140
1141/**
1142 * @brief General Purpose I/O
1143 */
1144
1145typedef struct
1146{
1147 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
1148 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
1149 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
1150 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
1151 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
1152 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
1153 __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */
1154 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
1155 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
1156} GPIO_TypeDef;
1157
1158/**
1159 * @brief Operational Amplifier (OPAMP)
1160 */
1161
1162typedef struct
1163{
1164 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
1165 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
1166 __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
1167} OPAMP_TypeDef;
1168
1169/**
1170 * @brief System configuration controller
1171 */
1172
1173typedef struct
1174{
1175 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */
1176 __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
1177 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
1178 __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */
1179 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
1180 __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */
1181 __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */
1182 __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */
1183 __IO uint32_t PWRCR; /*!< PWR control register, Address offset: 0x2C */
1184 uint32_t RESERVED3[61]; /*!< Reserved, 0x30-0x120 */
1185 __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */
1186 uint32_t RESERVED4[118]; /*!< Reserved, 0x128-0x2FC */
1187 __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */
1188 __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */
1189 __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */
1190 __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */
1191 __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */
1192 __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */
1193 __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */
1194 __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */
1195 __IO uint32_t UR8; /*!< SYSCFG user register 8, Address offset: 0x320 */
1196 __IO uint32_t UR9; /*!< SYSCFG user register 9, Address offset: 0x324 */
1197 __IO uint32_t UR10; /*!< SYSCFG user register 10, Address offset: 0x328 */
1198 __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */
1199 __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */
1200 __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */
1201 __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */
1202 __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */
1203 __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */
1204 __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */
1205
1206} SYSCFG_TypeDef;
1207
1208/**
1209 * @brief Inter-integrated Circuit Interface
1210 */
1211
1212typedef struct
1213{
1214 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
1215 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
1216 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
1217 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
1218 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
1219 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
1220 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
1221 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
1222 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
1223 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
1224 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
1225} I2C_TypeDef;
1226
1227/**
1228 * @brief Independent WATCHDOG
1229 */
1230
1231typedef struct
1232{
1233 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
1234 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
1235 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
1236 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
1237 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
1238} IWDG_TypeDef;
1239
1240
1241/**
1242 * @brief JPEG Codec
1243 */
1244typedef struct
1245{
1246 __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
1247 __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
1248 __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
1249 __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
1250 __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
1251 __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
1252 __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
1253 __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
1254 uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
1255 __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
1256 __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
1257 __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
1258 uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
1259 __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
1260 __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
1261 uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
1262 __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
1263 __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
1264 __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
1265 __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
1266 __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
1267 __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
1268 __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
1269 __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
1270 uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
1271 __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
1272 __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
1273 __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
1274 __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
1275
1276} JPEG_TypeDef;
1277
1278/**
1279 * @brief LCD-TFT Display Controller
1280 */
1281
1282typedef struct
1283{
1284 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
1285 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
1286 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
1287 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
1288 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
1289 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
1290 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
1291 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
1292 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
1293 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
1294 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
1295 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
1296 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
1297 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
1298 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
1299 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
1300 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
1301} LTDC_TypeDef;
1302
1303/**
1304 * @brief LCD-TFT Display layer x Controller
1305 */
1306
1307typedef struct
1308{
1309 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
1310 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
1311 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
1312 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
1313 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
1314 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
1315 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
1316 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
1317 uint32_t RESERVED0[2]; /*!< Reserved */
1318 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
1319 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
1320 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
1321 uint32_t RESERVED1[3]; /*!< Reserved */
1322 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
1323
1324} LTDC_Layer_TypeDef;
1325
1326/**
1327 * @brief Power Control
1328 */
1329
1330typedef struct
1331{
1332 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
1333 __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */
1334 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
1335 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */
1336 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */
1337 __IO uint32_t CPU2CR; /*!< PWR CPU2 control register, Address offset: 0x14 */
1338 __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */
1339 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
1340 __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */
1341 __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */
1342 __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
1343} PWR_TypeDef;
1344
1345/**
1346 * @brief Reset and Clock Control
1347 */
1348
1349typedef struct
1350{
1351 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
1352 __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */
1353 __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */
1354 __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */
1355 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */
1356 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
1357 __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */
1358 __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */
1359 __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */
1360 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
1361 __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */
1362 __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */
1363 __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */
1364 __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */
1365 __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */
1366 __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */
1367 __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */
1368 __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */
1369 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
1370 __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */
1371 __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */
1372 __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */
1373 __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */
1374 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */
1375 __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */
1376 __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */
1377 __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */
1378 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */
1379 __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */
1380 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
1381 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */
1382 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */
1383 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */
1384 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */
1385 __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */
1386 __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */
1387 __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */
1388 __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */
1389 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */
1390 __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */
1391 __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */
1392 uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */
1393 __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */
1394 uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */
1395 __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */
1396 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */
1397 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */
1398 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */
1399 __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */
1400 __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */
1401 __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */
1402 __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */
1403 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */
1404 __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */
1405 uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */
1406 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */
1407 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */
1408 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */
1409 __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */
1410 __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */
1411 __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */
1412 __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */
1413 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */
1414 __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */
1415 uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */
1416
1417} RCC_TypeDef;
1418
1419typedef struct
1420{
1421 __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0x00 */
1422 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x04 */
1423 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x08 */
1424 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x0C */
1425 __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0x10 */
1426 __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0x14 */
1427 __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0x18 */
1428 __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0x1C */
1429 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0x20 */
1430 __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0x24 */
1431 uint32_t RESERVED9; /*!< Reserved, Address offset: 0x28 */
1432 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0x3C */
1433 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x40 */
1434 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x44 */
1435 __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x48 */
1436 __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x4C */
1437 __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x50 */
1438 __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x54 */
1439 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x58 */
1440 __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x5C */
1441 uint32_t RESERVED10[4]; /*!< Reserved, 0x60-0x6C Address offset: 0x60 */
1442
1443} RCC_Core_TypeDef;
1444
1445/**
1446 * @brief Real-Time Clock
1447 */
1448typedef struct
1449{
1450 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
1451 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
1452 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
1453 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
1454 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
1455 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
1456 uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
1457 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
1458 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
1459 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
1460 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
1461 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
1462 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
1463 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
1464 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
1465 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
1466 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
1467 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
1468 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
1469 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
1470 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
1471 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
1472 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
1473 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
1474 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
1475 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
1476 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
1477 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
1478 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
1479 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
1480 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
1481 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
1482 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
1483 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
1484 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
1485 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
1486 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
1487 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
1488 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
1489 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
1490 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
1491 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
1492 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
1493 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
1494 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
1495 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
1496 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
1497 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
1498 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
1499 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
1500 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
1501 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
1502} RTC_TypeDef;
1503
1504/**
1505 * @brief Serial Audio Interface
1506 */
1507
1508typedef struct
1509{
1510 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
1511 uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
1512 __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
1513 __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
1514} SAI_TypeDef;
1515
1516typedef struct
1517{
1518 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
1519 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
1520 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
1521 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
1522 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
1523 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
1524 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
1525 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
1526} SAI_Block_TypeDef;
1527
1528/**
1529 * @brief SPDIF-RX Interface
1530 */
1531
1532typedef struct
1533{
1534 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
1535 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
1536 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
1537 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
1538 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
1539 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
1540 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
1541 uint32_t RESERVED2; /*!< Reserved, 0x1A */
1542} SPDIFRX_TypeDef;
1543
1544
1545/**
1546 * @brief Secure digital input/output Interface
1547 */
1548
1549typedef struct
1550{
1551 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
1552 __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
1553 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
1554 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
1555 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
1556 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
1557 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
1558 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
1559 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
1560 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
1561 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
1562 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
1563 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
1564 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
1565 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
1566 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
1567 __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
1568 uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
1569 __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
1570 __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
1571 __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
1572 __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
1573 uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
1574 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
1575 uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */
1576 __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */
1577} SDMMC_TypeDef;
1578
1579
1580/**
1581 * @brief Delay Block DLYB
1582 */
1583
1584typedef struct
1585{
1586 __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */
1587 __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */
1588} DLYB_TypeDef;
1589
1590/**
1591 * @brief HW Semaphore HSEM
1592 */
1593
1594typedef struct
1595{
1596 __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */
1597 __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */
1598 __IO uint32_t C1IER; /*!< HSEM Interrupt 0 enable register , Address offset: 100h */
1599 __IO uint32_t C1ICR; /*!< HSEM Interrupt 0 clear register , Address offset: 104h */
1600 __IO uint32_t C1ISR; /*!< HSEM Interrupt 0 Status register , Address offset: 108h */
1601 __IO uint32_t C1MISR; /*!< HSEM Interrupt 0 Masked Status register , Address offset: 10Ch */
1602 __IO uint32_t C2IER; /*!< HSEM Interrupt 1 enable register , Address offset: 110h */
1603 __IO uint32_t C2ICR; /*!< HSEM Interrupt 1 clear register , Address offset: 114h */
1604 __IO uint32_t C2ISR; /*!< HSEM Interrupt 1 Status register , Address offset: 118h */
1605 __IO uint32_t C2MISR; /*!< HSEM Interrupt 1 Masked Status register , Address offset: 11Ch */
1606 uint32_t Reserved[8]; /* Reserved Address offset: 120h-13Ch*/
1607 __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */
1608 __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */
1609
1610} HSEM_TypeDef;
1611
1612typedef struct
1613{
1614 __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */
1615 __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */
1616 __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */
1617 __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */
1618} HSEM_Common_TypeDef;
1619
1620/**
1621 * @brief Serial Peripheral Interface
1622 */
1623
1624typedef struct
1625{
1626 __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */
1627 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
1628 __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */
1629 __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */
1630 __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */
1631 __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */
1632 __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */
1633 uint32_t RESERVED0; /*!< Reserved, 0x1C */
1634 __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */
1635 uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */
1636 __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */
1637 uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
1638 __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */
1639 __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */
1640 __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */
1641 __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */
1642 __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */
1643
1644} SPI_TypeDef;
1645/**
1646 * @brief QUAD Serial Peripheral Interface
1647 */
1648
1649typedef struct
1650{
1651 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
1652 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
1653 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
1654 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
1655 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
1656 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
1657 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
1658 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
1659 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
1660 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
1661 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
1662 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
1663 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
1664} QUADSPI_TypeDef;
1665
1666/**
1667 * @brief TIM
1668 */
1669
1670typedef struct
1671{
1672 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
1673 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
1674 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
1675 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
1676 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
1677 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
1678 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
1679 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
1680 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
1681 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
1682 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
1683 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
1684 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
1685 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
1686 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
1687 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
1688 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
1689 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
1690 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
1691 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
1692 uint32_t RESERVED1; /*!< Reserved, 0x50 */
1693 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
1694 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
1695 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
1696 __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
1697 __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
1698 __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
1699} TIM_TypeDef;
1700
1701/**
1702 * @brief LPTIMIMER
1703 */
1704typedef struct
1705{
1706 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
1707 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
1708 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
1709 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
1710 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
1711 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
1712 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
1713 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
1714 uint32_t RESERVED1; /*!< Reserved, 0x20 */
1715 __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */
1716} LPTIM_TypeDef;
1717
1718/**
1719 * @brief Comparator
1720 */
1721typedef struct
1722{
1723 __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */
1724 __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */
1725 __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */
1726} COMPOPT_TypeDef;
1727
1728typedef struct
1729{
1730 __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */
1731} COMP_TypeDef;
1732
1733typedef struct
1734{
1735 __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
1736} COMP_Common_TypeDef;
1737/**
1738 * @brief Universal Synchronous Asynchronous Receiver Transmitter
1739 */
1740
1741typedef struct
1742{
1743 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
1744 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
1745 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
1746 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
1747 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
1748 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
1749 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
1750 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
1751 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
1752 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
1753 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
1754 __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */
1755} USART_TypeDef;
1756
1757/**
1758 * @brief Single Wire Protocol Master Interface SPWMI
1759 */
1760typedef struct
1761{
1762 __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
1763 __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
1764 uint32_t RESERVED1; /*!< Reserved, 0x08 */
1765 __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
1766 __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
1767 __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
1768 __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
1769 __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
1770 __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
1771 __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
1772} SWPMI_TypeDef;
1773
1774/**
1775 * @brief Window WATCHDOG
1776 */
1777
1778typedef struct
1779{
1780 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
1781 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
1782 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
1783} WWDG_TypeDef;
1784
1785
1786/**
1787 * @brief RAM_ECC_Specific_Registers
1788 */
1789typedef struct
1790{
1791 __IO uint32_t CR; /*!< RAMECC monitor configuration register */
1792 __IO uint32_t SR; /*!< RAMECC monitor status register */
1793 __IO uint32_t FAR; /*!< RAMECC monitor failing address register */
1794 __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */
1795 __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */
1796 __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */
1797} RAMECC_MonitorTypeDef;
1798
1799typedef struct
1800{
1801 __IO uint32_t IER; /*!< RAMECC interrupt enable register */
1802} RAMECC_TypeDef;
1803/**
1804 * @}
1805 */
1806
1807
1808
1809/**
1810 * @brief High resolution Timer (HRTIM)
1811 */
1812/* HRTIM master registers definition */
1813typedef struct
1814{
1815 __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
1816 __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
1817 __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
1818 __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
1819 __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
1820 __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
1821 __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */
1822 __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */
1823 uint32_t RESERVED0; /*!< Reserved, 0x20 */
1824 __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */
1825 __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */
1826 __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */
1827 uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */
1828}HRTIM_Master_TypeDef;
1829
1830/* HRTIM Timer A to E registers definition */
1831typedef struct
1832{
1833 __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */
1834 __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */
1835 __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */
1836 __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */
1837 __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */
1838 __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */
1839 __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */
1840 __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */
1841 __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */
1842 __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */
1843 __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */
1844 __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */
1845 __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */
1846 __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */
1847 __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */
1848 __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */
1849 __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */
1850 __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */
1851 __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */
1852 __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */
1853 __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */
1854 __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */
1855 __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */
1856 __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */
1857 __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */
1858 __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */
1859 __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */
1860 uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */
1861}HRTIM_Timerx_TypeDef;
1862
1863/* HRTIM common register definition */
1864typedef struct
1865{
1866 __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */
1867 __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */
1868 __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */
1869 __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */
1870 __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */
1871 __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */
1872 __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
1873 __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
1874 __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
1875 __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
1876 __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
1877 __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
1878 __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
1879 __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */
1880 __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */
1881 __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */
1882 __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */
1883 __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */
1884 __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */
1885 __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x4C */
1886 __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */
1887 __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */
1888 __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */
1889 __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */
1890 __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */
1891 __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */
1892 __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */
1893 __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */
1894 __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */
1895}HRTIM_Common_TypeDef;
1896
1897/* HRTIM register definition */
1898typedef struct {
1899 HRTIM_Master_TypeDef sMasterRegs;
1900 HRTIM_Timerx_TypeDef sTimerxRegs[5];
1901 uint32_t RESERVED0[32];
1902 HRTIM_Common_TypeDef sCommonRegs;
1903}HRTIM_TypeDef;
1904/**
1905 * @brief RNG
1906 */
1907
1908typedef struct
1909{
1910 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
1911 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
1912 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
1913} RNG_TypeDef;
1914
1915/**
1916 * @brief MDIOS
1917 */
1918
1919typedef struct
1920{
1921 __IO uint32_t CR;
1922 __IO uint32_t WRFR;
1923 __IO uint32_t CWRFR;
1924 __IO uint32_t RDFR;
1925 __IO uint32_t CRDFR;
1926 __IO uint32_t SR;
1927 __IO uint32_t CLRFR;
1928 uint32_t RESERVED[57];
1929 __IO uint32_t DINR0;
1930 __IO uint32_t DINR1;
1931 __IO uint32_t DINR2;
1932 __IO uint32_t DINR3;
1933 __IO uint32_t DINR4;
1934 __IO uint32_t DINR5;
1935 __IO uint32_t DINR6;
1936 __IO uint32_t DINR7;
1937 __IO uint32_t DINR8;
1938 __IO uint32_t DINR9;
1939 __IO uint32_t DINR10;
1940 __IO uint32_t DINR11;
1941 __IO uint32_t DINR12;
1942 __IO uint32_t DINR13;
1943 __IO uint32_t DINR14;
1944 __IO uint32_t DINR15;
1945 __IO uint32_t DINR16;
1946 __IO uint32_t DINR17;
1947 __IO uint32_t DINR18;
1948 __IO uint32_t DINR19;
1949 __IO uint32_t DINR20;
1950 __IO uint32_t DINR21;
1951 __IO uint32_t DINR22;
1952 __IO uint32_t DINR23;
1953 __IO uint32_t DINR24;
1954 __IO uint32_t DINR25;
1955 __IO uint32_t DINR26;
1956 __IO uint32_t DINR27;
1957 __IO uint32_t DINR28;
1958 __IO uint32_t DINR29;
1959 __IO uint32_t DINR30;
1960 __IO uint32_t DINR31;
1961 __IO uint32_t DOUTR0;
1962 __IO uint32_t DOUTR1;
1963 __IO uint32_t DOUTR2;
1964 __IO uint32_t DOUTR3;
1965 __IO uint32_t DOUTR4;
1966 __IO uint32_t DOUTR5;
1967 __IO uint32_t DOUTR6;
1968 __IO uint32_t DOUTR7;
1969 __IO uint32_t DOUTR8;
1970 __IO uint32_t DOUTR9;
1971 __IO uint32_t DOUTR10;
1972 __IO uint32_t DOUTR11;
1973 __IO uint32_t DOUTR12;
1974 __IO uint32_t DOUTR13;
1975 __IO uint32_t DOUTR14;
1976 __IO uint32_t DOUTR15;
1977 __IO uint32_t DOUTR16;
1978 __IO uint32_t DOUTR17;
1979 __IO uint32_t DOUTR18;
1980 __IO uint32_t DOUTR19;
1981 __IO uint32_t DOUTR20;
1982 __IO uint32_t DOUTR21;
1983 __IO uint32_t DOUTR22;
1984 __IO uint32_t DOUTR23;
1985 __IO uint32_t DOUTR24;
1986 __IO uint32_t DOUTR25;
1987 __IO uint32_t DOUTR26;
1988 __IO uint32_t DOUTR27;
1989 __IO uint32_t DOUTR28;
1990 __IO uint32_t DOUTR29;
1991 __IO uint32_t DOUTR30;
1992 __IO uint32_t DOUTR31;
1993} MDIOS_TypeDef;
1994
1995
1996/**
1997 * @brief USB_OTG_Core_Registers
1998 */
1999typedef struct
2000{
2001 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
2002 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
2003 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
2004 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
2005 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
2006 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
2007 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
2008 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
2009 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
2010 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
2011 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
2012 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
2013 uint32_t Reserved30[2]; /*!< Reserved 030h */
2014 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
2015 __IO uint32_t CID; /*!< User ID Register 03Ch */
2016 __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
2017 __IO uint32_t GHWCFG1; /* User HW config1 044h*/
2018 __IO uint32_t GHWCFG2; /* User HW config2 048h*/
2019 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
2020 uint32_t Reserved6; /*!< Reserved 050h */
2021 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
2022 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
2023 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
2024 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
2025 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
2026 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
2027 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
2028} USB_OTG_GlobalTypeDef;
2029
2030
2031/**
2032 * @brief USB_OTG_device_Registers
2033 */
2034typedef struct
2035{
2036 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
2037 __IO uint32_t DCTL; /*!< dev Control Register 804h */
2038 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
2039 uint32_t Reserved0C; /*!< Reserved 80Ch */
2040 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
2041 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
2042 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
2043 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
2044 uint32_t Reserved20; /*!< Reserved 820h */
2045 uint32_t Reserved9; /*!< Reserved 824h */
2046 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
2047 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
2048 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
2049 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
2050 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
2051 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
2052 uint32_t Reserved40; /*!< dedicated EP mask 840h */
2053 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
2054 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
2055 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
2056} USB_OTG_DeviceTypeDef;
2057
2058
2059/**
2060 * @brief USB_OTG_IN_Endpoint-Specific_Register
2061 */
2062typedef struct
2063{
2064 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
2065 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
2066 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
2067 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
2068 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
2069 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
2070 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
2071 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
2072} USB_OTG_INEndpointTypeDef;
2073
2074
2075/**
2076 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
2077 */
2078typedef struct
2079{
2080 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
2081 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
2082 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
2083 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
2084 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
2085 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
2086 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
2087} USB_OTG_OUTEndpointTypeDef;
2088
2089
2090/**
2091 * @brief USB_OTG_Host_Mode_Register_Structures
2092 */
2093typedef struct
2094{
2095 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
2096 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
2097 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
2098 uint32_t Reserved40C; /*!< Reserved 40Ch */
2099 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
2100 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
2101 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
2102} USB_OTG_HostTypeDef;
2103
2104/**
2105 * @brief USB_OTG_Host_Channel_Specific_Registers
2106 */
2107typedef struct
2108{
2109 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
2110 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
2111 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
2112 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
2113 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
2114 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
2115 uint32_t Reserved[2]; /*!< Reserved */
2116} USB_OTG_HostChannelTypeDef;
2117/**
2118 * @}
2119 */
2120
2121
2122/** @addtogroup Peripheral_memory_map
2123 * @{
2124 */
2125#define D1_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */
2126#define D1_ITCMICP_BASE (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */
2127#define D1_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM */
2128#define D1_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
2129#define D1_AXIICP_BASE (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */
2130#define D1_AXISRAM_BASE (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI */
2131
2132#define D2_AXISRAM_BASE (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI */
2133#define D2_AHBSRAM_BASE (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge */
2134
2135#define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */
2136#define D3_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */
2137
2138#define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/APB Peripherals */
2139#define QSPI_BASE (0x90000000UL) /*!< Base address of : QSPI memories accessible over AXI */
2140
2141#define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */
2142#define FLASH_BANK2_BASE (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI */
2143#define FLASH_END (0x081FFFFFUL) /*!< FLASH end address */
2144
2145/* Legacy define */
2146#define FLASH_BASE FLASH_BANK1_BASE
2147
2148/*!< Device electronic signature memory map */
2149#define UID_BASE (0x1FF1E800UL) /*!< Unique device ID register base address */
2150#define FLASHSIZE_BASE (0x1FF1E880UL) /*!< FLASH Size register base address */
2151
2152
2153/*!< Peripheral memory map */
2154#define D2_APB1PERIPH_BASE PERIPH_BASE
2155#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
2156#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
2157#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL)
2158
2159#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
2160#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL)
2161
2162#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL)
2163#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL)
2164
2165/*!< Legacy Peripheral memory map */
2166#define APB1PERIPH_BASE PERIPH_BASE
2167#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
2168#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
2169#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
2170
2171
2172/*!< D1_AHB1PERIPH peripherals */
2173
2174#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL)
2175#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL)
2176#define JPGDEC_BASE (D1_AHB1PERIPH_BASE + 0x3000UL)
2177#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL)
2178#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL)
2179#define QSPI_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL)
2180#define DLYB_QSPI_BASE (D1_AHB1PERIPH_BASE + 0x6000UL)
2181#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL)
2182#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL)
2183#define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL)
2184
2185/*!< D2_AHB1PERIPH peripherals */
2186
2187#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL)
2188#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL)
2189#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL)
2190#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL)
2191#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL)
2192#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL)
2193#define ART_BASE (D2_AHB1PERIPH_BASE + 0x4400UL)
2194#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL)
2195#define ETH_MAC_BASE (ETH_BASE)
2196
2197/*!< USB registers base address */
2198#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL)
2199#define USB2_OTG_FS_PERIPH_BASE (0x40080000UL)
2200#define USB_OTG_GLOBAL_BASE (0x000UL)
2201#define USB_OTG_DEVICE_BASE (0x800UL)
2202#define USB_OTG_IN_ENDPOINT_BASE (0x900UL)
2203#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL)
2204#define USB_OTG_EP_REG_SIZE (0x20UL)
2205#define USB_OTG_HOST_BASE (0x400UL)
2206#define USB_OTG_HOST_PORT_BASE (0x440UL)
2207#define USB_OTG_HOST_CHANNEL_BASE (0x500UL)
2208#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL)
2209#define USB_OTG_PCGCCTL_BASE (0xE00UL)
2210#define USB_OTG_FIFO_BASE (0x1000UL)
2211#define USB_OTG_FIFO_SIZE (0x1000UL)
2212
2213/*!< D2_AHB2PERIPH peripherals */
2214
2215#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL)
2216#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL)
2217#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL)
2218#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL)
2219#define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL)
2220
2221/*!< D3_AHB1PERIPH peripherals */
2222#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL)
2223#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL)
2224#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL)
2225#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL)
2226#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL)
2227#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL)
2228#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL)
2229#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL)
2230#define GPIOI_BASE (D3_AHB1PERIPH_BASE + 0x2000UL)
2231#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL)
2232#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL)
2233#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL)
2234#define RCC_C1_BASE (RCC_BASE + 0x130UL)
2235#define RCC_C2_BASE (RCC_BASE + 0x190UL)
2236#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL)
2237#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL)
2238#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL)
2239#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL)
2240#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL)
2241#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL)
2242#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL)
2243#define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL)
2244
2245/*!< D1_APB1PERIPH peripherals */
2246#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL)
2247#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)
2248#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)
2249#define DSI_BASE (D1_APB1PERIPH_BASE)
2250#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL)
2251
2252/*!< D2_APB1PERIPH peripherals */
2253#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL)
2254#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL)
2255#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL)
2256#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL)
2257#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL)
2258#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL)
2259#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL)
2260#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL)
2261#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL)
2262#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL)
2263
2264#define WWDG2_BASE (D2_APB1PERIPH_BASE + 0x2C00UL)
2265
2266#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL)
2267#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL)
2268#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL)
2269#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL)
2270#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL)
2271#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL)
2272#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL)
2273#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL)
2274#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL)
2275#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL)
2276#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL)
2277#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL)
2278#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL)
2279#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL)
2280#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL)
2281#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL)
2282#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
2283#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
2284#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL)
2285#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL)
2286#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL)
2287#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL)
2288#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL)
2289#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL)
2290
2291/*!< D2_APB2PERIPH peripherals */
2292
2293#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL)
2294#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL)
2295#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL)
2296#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL)
2297#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL)
2298#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL)
2299#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL)
2300#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL)
2301#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL)
2302#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL)
2303#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL)
2304#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
2305#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
2306#define SAI2_BASE (D2_APB2PERIPH_BASE + 0x5C00UL)
2307#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
2308#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
2309#define SAI3_BASE (D2_APB2PERIPH_BASE + 0x6000UL)
2310#define SAI3_Block_A_BASE (SAI3_BASE + 0x004UL)
2311#define SAI3_Block_B_BASE (SAI3_BASE + 0x024UL)
2312#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7000UL)
2313#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
2314#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
2315#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
2316#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
2317#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)
2318#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)
2319#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)
2320#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)
2321#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
2322#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
2323#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)
2324#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)
2325#define HRTIM1_BASE (D2_APB2PERIPH_BASE + 0x7400UL)
2326#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080UL)
2327#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100UL)
2328#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180UL)
2329#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200UL)
2330#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280UL)
2331#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380UL)
2332
2333
2334/*!< D3_APB1PERIPH peripherals */
2335#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL)
2336#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL)
2337#define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL)
2338#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL)
2339#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL)
2340#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL)
2341#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL)
2342#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL)
2343#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL)
2344#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL)
2345#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL)
2346#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL)
2347#define COMP1_BASE (COMP12_BASE + 0x0CUL)
2348#define COMP2_BASE (COMP12_BASE + 0x10UL)
2349#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL)
2350#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL)
2351#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL)
2352
2353#define IWDG2_BASE (D3_APB1PERIPH_BASE + 0x4C00UL)
2354
2355#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL)
2356#define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL)
2357#define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL)
2358
2359
2360
2361
2362#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL)
2363#define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL)
2364#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL)
2365#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL)
2366#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL)
2367#define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL)
2368#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL)
2369#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL)
2370
2371#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE)
2372#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL)
2373#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL)
2374#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL)
2375#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL)
2376#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL)
2377#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL)
2378#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL)
2379
2380#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL)
2381#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL)
2382#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL)
2383#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL)
2384#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL)
2385#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL)
2386#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL)
2387#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL)
2388
2389#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL)
2390#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL)
2391
2392#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
2393#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
2394#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
2395#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
2396#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
2397#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
2398#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
2399#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
2400
2401#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
2402#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
2403#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
2404#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
2405#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
2406#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
2407#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
2408#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
2409
2410#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
2411#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
2412#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
2413#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
2414#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
2415#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
2416#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
2417#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
2418#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
2419#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
2420#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
2421#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
2422#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
2423#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
2424#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
2425#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
2426
2427#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
2428#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
2429#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
2430#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
2431#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL)
2432#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL)
2433#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL)
2434#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL)
2435
2436#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
2437#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
2438
2439/*!< FMC Banks registers base address */
2440#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
2441#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
2442#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL)
2443#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
2444#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
2445
2446/* Debug MCU registers base address */
2447#define DBGMCU_BASE (0x5C001000UL)
2448
2449#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL)
2450#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL)
2451#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL)
2452#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL)
2453#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL)
2454#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL)
2455#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL)
2456#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL)
2457#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL)
2458#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL)
2459#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL)
2460#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL)
2461#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL)
2462#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
2463#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
2464#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
2465
2466#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)
2467#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)
2468#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)
2469#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)
2470#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)
2471
2472#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)
2473#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)
2474#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)
2475#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)
2476#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)
2477
2478#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)
2479#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
2480
2481
2482/**
2483 * @}
2484 */
2485
2486/** @addtogroup Peripheral_declaration
2487 * @{
2488 */
2489#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
2490#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
2491#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
2492#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
2493#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
2494#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
2495#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
2496#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
2497#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
2498#define RTC ((RTC_TypeDef *) RTC_BASE)
2499#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)
2500
2501#define WWDG2 ((WWDG_TypeDef *) WWDG2_BASE)
2502#define IWDG2 ((IWDG_TypeDef *) IWDG2_BASE)
2503
2504#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)
2505#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
2506#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
2507#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
2508#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
2509#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
2510#define USART2 ((USART_TypeDef *) USART2_BASE)
2511#define USART3 ((USART_TypeDef *) USART3_BASE)
2512#define USART6 ((USART_TypeDef *) USART6_BASE)
2513#define UART7 ((USART_TypeDef *) UART7_BASE)
2514#define UART8 ((USART_TypeDef *) UART8_BASE)
2515#define CRS ((CRS_TypeDef *) CRS_BASE)
2516#define UART4 ((USART_TypeDef *) UART4_BASE)
2517#define UART5 ((USART_TypeDef *) UART5_BASE)
2518#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
2519#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
2520#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
2521#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
2522#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
2523#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
2524#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
2525#define CEC ((CEC_TypeDef *) CEC_BASE)
2526#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
2527#define PWR ((PWR_TypeDef *) PWR_BASE)
2528#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
2529#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
2530#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
2531#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
2532#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)
2533#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)
2534#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)
2535
2536#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
2537#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)
2538#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
2539#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
2540#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
2541#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
2542#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
2543#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
2544
2545
2546#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
2547#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
2548#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
2549#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
2550#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
2551#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
2552#define USART1 ((USART_TypeDef *) USART1_BASE)
2553#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
2554#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
2555#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
2556#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
2557#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
2558#define HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)
2559#define HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)
2560#define HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)
2561#define HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)
2562#define HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)
2563#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
2564#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
2565#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
2566#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
2567#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
2568#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
2569#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
2570#define SAI3 ((SAI_TypeDef *) SAI3_BASE)
2571#define SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)
2572#define SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)
2573#define SAI4 ((SAI_TypeDef *) SAI4_BASE)
2574#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
2575#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
2576
2577#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
2578#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
2579#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
2580#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
2581#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
2582#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
2583#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
2584#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
2585#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
2586#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
2587#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
2588#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
2589#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
2590#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)
2591#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
2592#define RCC ((RCC_TypeDef *) RCC_BASE)
2593#define RCC_C1 ((RCC_Core_TypeDef *) RCC_C1_BASE)
2594#define RCC_C2 ((RCC_Core_TypeDef *) RCC_C2_BASE)
2595
2596#define ART ((ART_TypeDef *) ART_BASE)
2597#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
2598#define CRC ((CRC_TypeDef *) CRC_BASE)
2599
2600#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
2601#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
2602#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
2603#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
2604#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
2605#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
2606#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
2607#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
2608#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
2609#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
2610#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
2611
2612#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
2613#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
2614#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
2615#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)
2616#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
2617
2618#define RNG ((RNG_TypeDef *) RNG_BASE)
2619#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
2620#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
2621
2622#define BDMA ((BDMA_TypeDef *) BDMA_BASE)
2623#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)
2624#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)
2625#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)
2626#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)
2627#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)
2628#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)
2629#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)
2630#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)
2631
2632#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)
2633#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)
2634#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)
2635#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)
2636#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)
2637#define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)
2638
2639#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)
2640#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)
2641#define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)
2642#define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)
2643#define RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)
2644#define RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)
2645
2646#define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)
2647#define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)
2648#define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)
2649
2650#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
2651#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
2652#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
2653#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
2654#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
2655#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
2656#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
2657#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
2658#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
2659
2660
2661#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
2662#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
2663#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
2664#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
2665#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
2666#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
2667#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
2668#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
2669
2670#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
2671#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
2672
2673#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
2674#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
2675#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
2676#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
2677#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
2678#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
2679#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
2680#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
2681#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
2682
2683#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
2684#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
2685#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
2686#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
2687#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
2688#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
2689#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
2690#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
2691#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
2692
2693
2694#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
2695#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
2696#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
2697#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
2698#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
2699#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
2700#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
2701#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
2702#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
2703#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
2704#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
2705#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
2706#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
2707#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
2708#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
2709#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
2710#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
2711
2712#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
2713#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
2714#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
2715#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
2716#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
2717#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
2718#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
2719#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
2720
2721#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
2722#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
2723
2724
2725#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
2726#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
2727#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
2728#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
2729#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
2730
2731
2732#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
2733#define DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)
2734#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
2735#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
2736
2737#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
2738
2739#define JPEG ((JPEG_TypeDef *) JPGDEC_BASE)
2740#define HSEM ((HSEM_TypeDef *) HSEM_BASE)
2741#if defined(CORE_CM4)
2742#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x110UL))
2743#else /* CORE_CM7 */
2744#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
2745#endif /* CORE_CM4 */
2746
2747#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
2748#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
2749#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
2750#define DSI ((DSI_TypeDef *)DSI_BASE)
2751
2752#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
2753
2754#define ETH ((ETH_TypeDef *)ETH_BASE)
2755#define MDMA ((MDMA_TypeDef *)MDMA_BASE)
2756#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
2757#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
2758#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
2759#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
2760#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
2761#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
2762#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
2763#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
2764#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
2765#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
2766#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
2767#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
2768#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
2769#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
2770#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
2771#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
2772
2773
2774#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
2775#define USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)
2776
2777/* Legacy defines */
2778#define USB_OTG_HS USB1_OTG_HS
2779#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
2780#define USB_OTG_FS USB2_OTG_FS
2781#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
2782
2783/**
2784 * @}
2785 */
2786
2787/** @addtogroup Exported_constants
2788 * @{
2789 */
2790
2791 /** @addtogroup Peripheral_Registers_Bits_Definition
2792 * @{
2793 */
2794
2795/******************************************************************************/
2796/* Peripheral Registers_Bits_Definition */
2797/******************************************************************************/
2798
2799/******************************************************************************/
2800/* */
2801/* Analog to Digital Converter */
2802/* */
2803/******************************************************************************/
2804/******************************* ADC VERSION ********************************/
2805#define ADC_VER_V5_X
2806/******************** Bit definition for ADC_ISR register ********************/
2807#define ADC_ISR_ADRDY_Pos (0U)
2808#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
2809#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */
2810#define ADC_ISR_EOSMP_Pos (1U)
2811#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
2812#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */
2813#define ADC_ISR_EOC_Pos (2U)
2814#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
2815#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */
2816#define ADC_ISR_EOS_Pos (3U)
2817#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
2818#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */
2819#define ADC_ISR_OVR_Pos (4U)
2820#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
2821#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */
2822#define ADC_ISR_JEOC_Pos (5U)
2823#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
2824#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */
2825#define ADC_ISR_JEOS_Pos (6U)
2826#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
2827#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */
2828#define ADC_ISR_AWD1_Pos (7U)
2829#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
2830#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */
2831#define ADC_ISR_AWD2_Pos (8U)
2832#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
2833#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */
2834#define ADC_ISR_AWD3_Pos (9U)
2835#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
2836#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */
2837#define ADC_ISR_JQOVF_Pos (10U)
2838#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
2839#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
2840
2841/******************** Bit definition for ADC_IER register ********************/
2842#define ADC_IER_ADRDYIE_Pos (0U)
2843#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
2844#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */
2845#define ADC_IER_EOSMPIE_Pos (1U)
2846#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
2847#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */
2848#define ADC_IER_EOCIE_Pos (2U)
2849#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
2850#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */
2851#define ADC_IER_EOSIE_Pos (3U)
2852#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
2853#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */
2854#define ADC_IER_OVRIE_Pos (4U)
2855#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
2856#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */
2857#define ADC_IER_JEOCIE_Pos (5U)
2858#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
2859#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */
2860#define ADC_IER_JEOSIE_Pos (6U)
2861#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
2862#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */
2863#define ADC_IER_AWD1IE_Pos (7U)
2864#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
2865#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */
2866#define ADC_IER_AWD2IE_Pos (8U)
2867#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
2868#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */
2869#define ADC_IER_AWD3IE_Pos (9U)
2870#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
2871#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */
2872#define ADC_IER_JQOVFIE_Pos (10U)
2873#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
2874#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */
2875
2876/******************** Bit definition for ADC_CR register ********************/
2877#define ADC_CR_ADEN_Pos (0U)
2878#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
2879#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */
2880#define ADC_CR_ADDIS_Pos (1U)
2881#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
2882#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */
2883#define ADC_CR_ADSTART_Pos (2U)
2884#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
2885#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */
2886#define ADC_CR_JADSTART_Pos (3U)
2887#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
2888#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */
2889#define ADC_CR_ADSTP_Pos (4U)
2890#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
2891#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */
2892#define ADC_CR_JADSTP_Pos (5U)
2893#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
2894#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */
2895#define ADC_CR_BOOST_Pos (8U)
2896#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */
2897#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */
2898#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */
2899#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */
2900#define ADC_CR_ADCALLIN_Pos (16U)
2901#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */
2902#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */
2903#define ADC_CR_LINCALRDYW1_Pos (22U)
2904#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */
2905#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */
2906#define ADC_CR_LINCALRDYW2_Pos (23U)
2907#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */
2908#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */
2909#define ADC_CR_LINCALRDYW3_Pos (24U)
2910#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */
2911#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */
2912#define ADC_CR_LINCALRDYW4_Pos (25U)
2913#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */
2914#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */
2915#define ADC_CR_LINCALRDYW5_Pos (26U)
2916#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */
2917#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */
2918#define ADC_CR_LINCALRDYW6_Pos (27U)
2919#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */
2920#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */
2921#define ADC_CR_ADVREGEN_Pos (28U)
2922#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
2923#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */
2924#define ADC_CR_DEEPPWD_Pos (29U)
2925#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
2926#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */
2927#define ADC_CR_ADCALDIF_Pos (30U)
2928#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
2929#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */
2930#define ADC_CR_ADCAL_Pos (31U)
2931#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
2932#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */
2933
2934/******************** Bit definition for ADC_CFGR register ********************/
2935#define ADC_CFGR_DMNGT_Pos (0U)
2936#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */
2937#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */
2938#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */
2939#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */
2940
2941#define ADC_CFGR_RES_Pos (2U)
2942#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */
2943#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */
2944#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */
2945#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
2946#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
2947
2948#define ADC_CFGR_EXTSEL_Pos (5U)
2949#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
2950#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */
2951#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
2952#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
2953#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
2954#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
2955#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
2956
2957#define ADC_CFGR_EXTEN_Pos (10U)
2958#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
2959#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */
2960#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
2961#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
2962
2963#define ADC_CFGR_OVRMOD_Pos (12U)
2964#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
2965#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */
2966#define ADC_CFGR_CONT_Pos (13U)
2967#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
2968#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */
2969#define ADC_CFGR_AUTDLY_Pos (14U)
2970#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
2971#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */
2972
2973#define ADC_CFGR_DISCEN_Pos (16U)
2974#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
2975#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */
2976
2977#define ADC_CFGR_DISCNUM_Pos (17U)
2978#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
2979#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
2980#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
2981#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
2982#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
2983
2984#define ADC_CFGR_JDISCEN_Pos (20U)
2985#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
2986#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
2987#define ADC_CFGR_JQM_Pos (21U)
2988#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
2989#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */
2990#define ADC_CFGR_AWD1SGL_Pos (22U)
2991#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
2992#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */
2993#define ADC_CFGR_AWD1EN_Pos (23U)
2994#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
2995#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */
2996#define ADC_CFGR_JAWD1EN_Pos (24U)
2997#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
2998#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */
2999#define ADC_CFGR_JAUTO_Pos (25U)
3000#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
3001#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */
3002
3003#define ADC_CFGR_AWD1CH_Pos (26U)
3004#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
3005#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */
3006#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
3007#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
3008#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
3009#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
3010#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
3011
3012#define ADC_CFGR_JQDIS_Pos (31U)
3013#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
3014#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */
3015
3016/******************** Bit definition for ADC_CFGR2 register ********************/
3017#define ADC_CFGR2_ROVSE_Pos (0U)
3018#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
3019#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */
3020#define ADC_CFGR2_JOVSE_Pos (1U)
3021#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
3022#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */
3023
3024#define ADC_CFGR2_OVSS_Pos (5U)
3025#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
3026#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */
3027#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
3028#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
3029#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
3030#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
3031
3032#define ADC_CFGR2_TROVS_Pos (9U)
3033#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
3034#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */
3035#define ADC_CFGR2_ROVSM_Pos (10U)
3036#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
3037#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */
3038
3039#define ADC_CFGR2_RSHIFT1_Pos (11U)
3040#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */
3041#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */
3042#define ADC_CFGR2_RSHIFT2_Pos (12U)
3043#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */
3044#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */
3045#define ADC_CFGR2_RSHIFT3_Pos (13U)
3046#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */
3047#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */
3048#define ADC_CFGR2_RSHIFT4_Pos (14U)
3049#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */
3050#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */
3051
3052#define ADC_CFGR2_OVSR_Pos (16U)
3053#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */
3054#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */
3055#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */
3056#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */
3057#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */
3058#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */
3059#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */
3060#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */
3061#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */
3062#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */
3063#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */
3064#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */
3065
3066#define ADC_CFGR2_LSHIFT_Pos (28U)
3067#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */
3068#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */
3069#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */
3070#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */
3071#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */
3072#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */
3073
3074/******************** Bit definition for ADC_SMPR1 register ********************/
3075#define ADC_SMPR1_SMP0_Pos (0U)
3076#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
3077#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */
3078#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
3079#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
3080#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
3081
3082#define ADC_SMPR1_SMP1_Pos (3U)
3083#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
3084#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */
3085#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
3086#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
3087#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
3088
3089#define ADC_SMPR1_SMP2_Pos (6U)
3090#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
3091#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */
3092#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
3093#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
3094#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
3095
3096#define ADC_SMPR1_SMP3_Pos (9U)
3097#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
3098#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */
3099#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
3100#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
3101#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
3102
3103#define ADC_SMPR1_SMP4_Pos (12U)
3104#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
3105#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */
3106#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
3107#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
3108#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
3109
3110#define ADC_SMPR1_SMP5_Pos (15U)
3111#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
3112#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */
3113#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
3114#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
3115#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
3116
3117#define ADC_SMPR1_SMP6_Pos (18U)
3118#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
3119#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */
3120#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
3121#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
3122#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
3123
3124#define ADC_SMPR1_SMP7_Pos (21U)
3125#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
3126#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */
3127#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
3128#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
3129#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
3130
3131#define ADC_SMPR1_SMP8_Pos (24U)
3132#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
3133#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */
3134#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
3135#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
3136#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
3137
3138#define ADC_SMPR1_SMP9_Pos (27U)
3139#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
3140#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */
3141#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
3142#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
3143#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
3144
3145/******************** Bit definition for ADC_SMPR2 register ********************/
3146#define ADC_SMPR2_SMP10_Pos (0U)
3147#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
3148#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */
3149#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
3150#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
3151#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
3152
3153#define ADC_SMPR2_SMP11_Pos (3U)
3154#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
3155#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */
3156#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
3157#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
3158#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
3159
3160#define ADC_SMPR2_SMP12_Pos (6U)
3161#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
3162#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */
3163#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
3164#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
3165#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
3166
3167#define ADC_SMPR2_SMP13_Pos (9U)
3168#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
3169#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */
3170#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
3171#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
3172#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
3173
3174#define ADC_SMPR2_SMP14_Pos (12U)
3175#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
3176#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */
3177#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
3178#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
3179#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
3180
3181#define ADC_SMPR2_SMP15_Pos (15U)
3182#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
3183#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */
3184#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
3185#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
3186#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
3187
3188#define ADC_SMPR2_SMP16_Pos (18U)
3189#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
3190#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */
3191#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
3192#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
3193#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
3194
3195#define ADC_SMPR2_SMP17_Pos (21U)
3196#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
3197#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */
3198#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
3199#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
3200#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
3201
3202#define ADC_SMPR2_SMP18_Pos (24U)
3203#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
3204#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */
3205#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
3206#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
3207#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
3208
3209#define ADC_SMPR2_SMP19_Pos (27U)
3210#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
3211#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */
3212#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
3213#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
3214#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
3215
3216/******************** Bit definition for ADC_PCSEL register ********************/
3217#define ADC_PCSEL_PCSEL_Pos (0U)
3218#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */
3219#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */
3220#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */
3221#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */
3222#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */
3223#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */
3224#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */
3225#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */
3226#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */
3227#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */
3228#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */
3229#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */
3230#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */
3231#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */
3232#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */
3233#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */
3234#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */
3235#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */
3236#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */
3237#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */
3238#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */
3239#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */
3240
3241/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/
3242#define ADC_LTR_LT_Pos (0U)
3243#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */
3244#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */
3245
3246/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/
3247#define ADC_HTR_HT_Pos (0U)
3248#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */
3249#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */
3250
3251
3252/******************** Bit definition for ADC_SQR1 register ********************/
3253#define ADC_SQR1_L_Pos (0U)
3254#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
3255#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
3256#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
3257#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
3258#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
3259#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
3260
3261#define ADC_SQR1_SQ1_Pos (6U)
3262#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
3263#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */
3264#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
3265#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
3266#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
3267#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
3268#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
3269
3270#define ADC_SQR1_SQ2_Pos (12U)
3271#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
3272#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */
3273#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
3274#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
3275#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
3276#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
3277#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
3278
3279#define ADC_SQR1_SQ3_Pos (18U)
3280#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
3281#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */
3282#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
3283#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
3284#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
3285#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
3286#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
3287
3288#define ADC_SQR1_SQ4_Pos (24U)
3289#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
3290#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */
3291#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
3292#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
3293#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
3294#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
3295#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
3296
3297/******************** Bit definition for ADC_SQR2 register ********************/
3298#define ADC_SQR2_SQ5_Pos (0U)
3299#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
3300#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */
3301#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
3302#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
3303#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
3304#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
3305#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
3306
3307#define ADC_SQR2_SQ6_Pos (6U)
3308#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
3309#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */
3310#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
3311#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
3312#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
3313#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
3314#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
3315
3316#define ADC_SQR2_SQ7_Pos (12U)
3317#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
3318#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */
3319#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
3320#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
3321#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
3322#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
3323#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
3324
3325#define ADC_SQR2_SQ8_Pos (18U)
3326#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
3327#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */
3328#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
3329#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
3330#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
3331#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
3332#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
3333
3334#define ADC_SQR2_SQ9_Pos (24U)
3335#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
3336#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */
3337#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
3338#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
3339#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
3340#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
3341#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
3342
3343/******************** Bit definition for ADC_SQR3 register ********************/
3344#define ADC_SQR3_SQ10_Pos (0U)
3345#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
3346#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */
3347#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
3348#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
3349#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
3350#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
3351#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
3352
3353#define ADC_SQR3_SQ11_Pos (6U)
3354#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
3355#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */
3356#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
3357#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
3358#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
3359#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
3360#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
3361
3362#define ADC_SQR3_SQ12_Pos (12U)
3363#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
3364#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */
3365#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
3366#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
3367#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
3368#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
3369#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
3370
3371#define ADC_SQR3_SQ13_Pos (18U)
3372#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
3373#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */
3374#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
3375#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
3376#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
3377#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
3378#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
3379
3380#define ADC_SQR3_SQ14_Pos (24U)
3381#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
3382#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */
3383#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
3384#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
3385#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
3386#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
3387#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
3388
3389/******************** Bit definition for ADC_SQR4 register ********************/
3390#define ADC_SQR4_SQ15_Pos (0U)
3391#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
3392#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */
3393#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
3394#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
3395#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
3396#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
3397#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
3398
3399#define ADC_SQR4_SQ16_Pos (6U)
3400#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
3401#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */
3402#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
3403#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
3404#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
3405#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
3406#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
3407/******************** Bit definition for ADC_DR register ********************/
3408#define ADC_DR_RDATA_Pos (0U)
3409#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */
3410#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */
3411
3412/******************** Bit definition for ADC_JSQR register ********************/
3413#define ADC_JSQR_JL_Pos (0U)
3414#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
3415#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */
3416#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
3417#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
3418
3419#define ADC_JSQR_JEXTSEL_Pos (2U)
3420#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
3421#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */
3422#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
3423#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
3424#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
3425#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
3426#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
3427
3428#define ADC_JSQR_JEXTEN_Pos (7U)
3429#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
3430#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */
3431#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
3432#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
3433
3434#define ADC_JSQR_JSQ1_Pos (9U)
3435#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
3436#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */
3437#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
3438#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
3439#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
3440#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
3441#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
3442
3443#define ADC_JSQR_JSQ2_Pos (15U)
3444#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */
3445#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */
3446#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
3447#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
3448#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
3449#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
3450#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */
3451
3452#define ADC_JSQR_JSQ3_Pos (21U)
3453#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
3454#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */
3455#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
3456#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
3457#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
3458#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
3459#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
3460
3461#define ADC_JSQR_JSQ4_Pos (27U)
3462#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
3463#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */
3464#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
3465#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
3466#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
3467#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
3468#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
3469
3470/******************** Bit definition for ADC_OFR1 register ********************/
3471#define ADC_OFR1_OFFSET1_Pos (0U)
3472#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
3473#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
3474#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
3475#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
3476#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
3477#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
3478#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
3479#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
3480#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
3481#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
3482#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
3483#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
3484#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
3485#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
3486#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
3487#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
3488#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
3489#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
3490#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
3491#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
3492#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
3493#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
3494#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
3495#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
3496#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
3497#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
3498#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
3499#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
3500
3501#define ADC_OFR1_OFFSET1_CH_Pos (26U)
3502#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
3503#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */
3504#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
3505#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
3506#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
3507#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
3508#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
3509
3510#define ADC_OFR1_SSATE_Pos (31U)
3511#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */
3512#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */
3513
3514
3515/******************** Bit definition for ADC_OFR2 register ********************/
3516#define ADC_OFR2_OFFSET2_Pos (0U)
3517#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
3518#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
3519#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
3520#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
3521#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
3522#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
3523#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
3524#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
3525#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
3526#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
3527#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
3528#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
3529#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
3530#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
3531#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
3532#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
3533#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
3534#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
3535#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
3536#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
3537#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
3538#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
3539#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
3540#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
3541#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
3542#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
3543#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
3544#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
3545
3546#define ADC_OFR2_OFFSET2_CH_Pos (26U)
3547#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
3548#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */
3549#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
3550#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
3551#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
3552#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
3553#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
3554
3555#define ADC_OFR2_SSATE_Pos (31U)
3556#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */
3557#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */
3558
3559
3560/******************** Bit definition for ADC_OFR3 register ********************/
3561#define ADC_OFR3_OFFSET3_Pos (0U)
3562#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
3563#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
3564#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
3565#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
3566#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
3567#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
3568#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
3569#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
3570#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
3571#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
3572#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
3573#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
3574#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
3575#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
3576#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
3577#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
3578#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
3579#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
3580#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
3581#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
3582#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
3583#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
3584#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
3585#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
3586#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
3587#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
3588#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
3589#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
3590
3591#define ADC_OFR3_OFFSET3_CH_Pos (26U)
3592#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
3593#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */
3594#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
3595#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
3596#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
3597#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
3598#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
3599
3600#define ADC_OFR3_SSATE_Pos (31U)
3601#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */
3602#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */
3603
3604
3605/******************** Bit definition for ADC_OFR4 register ********************/
3606#define ADC_OFR4_OFFSET4_Pos (0U)
3607#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
3608#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
3609#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
3610#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
3611#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
3612#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
3613#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
3614#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
3615#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
3616#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
3617#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
3618#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
3619#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
3620#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
3621#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
3622#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
3623#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
3624#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
3625#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
3626#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
3627#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
3628#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
3629#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
3630#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
3631#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
3632#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
3633#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
3634#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
3635
3636#define ADC_OFR4_OFFSET4_CH_Pos (26U)
3637#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
3638#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */
3639#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
3640#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
3641#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
3642#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
3643#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
3644
3645#define ADC_OFR4_SSATE_Pos (31U)
3646#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */
3647#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */
3648
3649
3650/******************** Bit definition for ADC_JDR1 register ********************/
3651#define ADC_JDR1_JDATA_Pos (0U)
3652#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */
3653#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */
3654#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
3655#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
3656#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
3657#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
3658#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
3659#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
3660#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
3661#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
3662#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
3663#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
3664#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
3665#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
3666#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
3667#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
3668#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
3669#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
3670#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */
3671#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */
3672#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */
3673#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */
3674#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */
3675#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */
3676#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */
3677#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */
3678#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */
3679#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */
3680#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */
3681#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */
3682#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */
3683#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */
3684#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */
3685#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */
3686
3687/******************** Bit definition for ADC_JDR2 register ********************/
3688#define ADC_JDR2_JDATA_Pos (0U)
3689#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */
3690#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */
3691#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
3692#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
3693#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
3694#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
3695#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
3696#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
3697#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
3698#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
3699#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
3700#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
3701#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
3702#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
3703#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
3704#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
3705#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
3706#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
3707#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */
3708#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */
3709#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */
3710#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */
3711#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */
3712#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */
3713#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */
3714#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */
3715#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */
3716#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */
3717#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */
3718#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */
3719#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */
3720#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */
3721#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */
3722#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */
3723
3724/******************** Bit definition for ADC_JDR3 register ********************/
3725#define ADC_JDR3_JDATA_Pos (0U)
3726#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */
3727#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */
3728#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
3729#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
3730#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
3731#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
3732#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
3733#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
3734#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
3735#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
3736#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
3737#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
3738#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
3739#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
3740#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
3741#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
3742#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
3743#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
3744#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */
3745#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */
3746#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */
3747#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */
3748#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */
3749#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */
3750#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */
3751#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */
3752#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */
3753#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */
3754#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */
3755#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */
3756#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */
3757#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */
3758#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */
3759#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */
3760
3761/******************** Bit definition for ADC_JDR4 register ********************/
3762#define ADC_JDR4_JDATA_Pos (0U)
3763#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */
3764#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */
3765#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
3766#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
3767#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
3768#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
3769#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
3770#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
3771#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
3772#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
3773#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
3774#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
3775#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
3776#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
3777#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
3778#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
3779#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
3780#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
3781#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */
3782#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */
3783#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */
3784#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */
3785#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */
3786#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */
3787#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */
3788#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */
3789#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */
3790#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */
3791#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */
3792#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */
3793#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */
3794#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */
3795#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */
3796#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */
3797
3798/******************** Bit definition for ADC_AWD2CR register ********************/
3799#define ADC_AWD2CR_AWD2CH_Pos (0U)
3800#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */
3801#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
3802#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
3803#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
3804#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
3805#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
3806#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
3807#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
3808#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
3809#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
3810#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
3811#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
3812#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
3813#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
3814#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
3815#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
3816#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
3817#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
3818#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
3819#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
3820#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
3821#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
3822
3823/******************** Bit definition for ADC_AWD3CR register ********************/
3824#define ADC_AWD3CR_AWD3CH_Pos (0U)
3825#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
3826#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */
3827#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
3828#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
3829#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
3830#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
3831#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
3832#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
3833#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
3834#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
3835#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
3836#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
3837#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
3838#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
3839#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
3840#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
3841#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
3842#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
3843#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
3844#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
3845#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
3846#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
3847
3848/******************** Bit definition for ADC_DIFSEL register ********************/
3849#define ADC_DIFSEL_DIFSEL_Pos (0U)
3850#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
3851#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */
3852#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
3853#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
3854#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
3855#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
3856#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
3857#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
3858#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
3859#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
3860#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
3861#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
3862#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
3863#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
3864#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
3865#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
3866#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
3867#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
3868#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
3869#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
3870#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
3871#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */
3872
3873/******************** Bit definition for ADC_CALFACT register ********************/
3874#define ADC_CALFACT_CALFACT_S_Pos (0U)
3875#define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
3876#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */
3877#define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
3878#define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
3879#define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
3880#define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
3881#define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
3882#define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
3883#define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
3884#define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
3885#define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
3886#define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
3887#define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
3888#define ADC_CALFACT_CALFACT_D_Pos (16U)
3889#define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
3890#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */
3891#define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
3892#define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
3893#define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
3894#define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
3895#define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
3896#define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
3897#define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
3898#define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
3899#define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
3900#define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
3901#define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
3902
3903/******************** Bit definition for ADC_CALFACT2 register ********************/
3904#define ADC_CALFACT2_LINCALFACT_Pos (0U)
3905#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
3906#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */
3907#define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
3908#define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
3909#define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
3910#define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
3911#define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
3912#define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
3913#define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
3914#define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
3915#define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
3916#define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
3917#define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
3918#define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
3919#define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
3920#define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
3921#define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
3922#define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
3923#define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
3924#define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
3925#define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
3926#define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
3927#define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
3928#define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
3929#define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
3930#define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
3931#define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
3932#define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
3933#define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
3934#define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */
3935#define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
3936#define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
3937
3938/************************* ADC Common registers *****************************/
3939/******************** Bit definition for ADC_CSR register ********************/
3940#define ADC_CSR_ADRDY_MST_Pos (0U)
3941#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
3942#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
3943#define ADC_CSR_EOSMP_MST_Pos (1U)
3944#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
3945#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
3946#define ADC_CSR_EOC_MST_Pos (2U)
3947#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
3948#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
3949#define ADC_CSR_EOS_MST_Pos (3U)
3950#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
3951#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
3952#define ADC_CSR_OVR_MST_Pos (4U)
3953#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
3954#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */
3955#define ADC_CSR_JEOC_MST_Pos (5U)
3956#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
3957#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
3958#define ADC_CSR_JEOS_MST_Pos (6U)
3959#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
3960#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
3961#define ADC_CSR_AWD1_MST_Pos (7U)
3962#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
3963#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
3964#define ADC_CSR_AWD2_MST_Pos (8U)
3965#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
3966#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
3967#define ADC_CSR_AWD3_MST_Pos (9U)
3968#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
3969#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
3970#define ADC_CSR_JQOVF_MST_Pos (10U)
3971#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
3972#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
3973#define ADC_CSR_ADRDY_SLV_Pos (16U)
3974#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
3975#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
3976#define ADC_CSR_EOSMP_SLV_Pos (17U)
3977#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
3978#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
3979#define ADC_CSR_EOC_SLV_Pos (18U)
3980#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
3981#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
3982#define ADC_CSR_EOS_SLV_Pos (19U)
3983#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
3984#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
3985#define ADC_CSR_OVR_SLV_Pos (20U)
3986#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
3987#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
3988#define ADC_CSR_JEOC_SLV_Pos (21U)
3989#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
3990#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */
3991#define ADC_CSR_JEOS_SLV_Pos (22U)
3992#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
3993#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */
3994#define ADC_CSR_AWD1_SLV_Pos (23U)
3995#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
3996#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */
3997#define ADC_CSR_AWD2_SLV_Pos (24U)
3998#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
3999#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */
4000#define ADC_CSR_AWD3_SLV_Pos (25U)
4001#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
4002#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */
4003#define ADC_CSR_JQOVF_SLV_Pos (26U)
4004#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
4005#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */
4006
4007/******************** Bit definition for ADC_CCR register ********************/
4008#define ADC_CCR_DUAL_Pos (0U)
4009#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
4010#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */
4011#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
4012#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
4013#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
4014#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
4015#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
4016
4017#define ADC_CCR_DELAY_Pos (8U)
4018#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
4019#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */
4020#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
4021#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
4022#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
4023#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
4024
4025
4026#define ADC_CCR_DAMDF_Pos (14U)
4027#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */
4028#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */
4029#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */
4030#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */
4031
4032#define ADC_CCR_CKMODE_Pos (16U)
4033#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
4034#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */
4035#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
4036#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
4037
4038#define ADC_CCR_PRESC_Pos (18U)
4039#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
4040#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */
4041#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
4042#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
4043#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
4044#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
4045
4046#define ADC_CCR_VREFEN_Pos (22U)
4047#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
4048#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */
4049#define ADC_CCR_TSEN_Pos (23U)
4050#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
4051#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */
4052#define ADC_CCR_VBATEN_Pos (24U)
4053#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
4054#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */
4055
4056/******************** Bit definition for ADC_CDR register *******************/
4057#define ADC_CDR_RDATA_MST_Pos (0U)
4058#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
4059#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
4060
4061#define ADC_CDR_RDATA_SLV_Pos (16U)
4062#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
4063#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
4064
4065/******************** Bit definition for ADC_CDR2 register ******************/
4066#define ADC_CDR2_RDATA_ALT_Pos (0U)
4067#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
4068#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */
4069
4070/******************************************************************************/
4071/* */
4072/* ART accelerator */
4073/* */
4074/******************************************************************************/
4075/******************* Bit definition for ART_CTR register ********************/
4076#define ART_CTR_EN_Pos (0U)
4077#define ART_CTR_EN_Msk (0x1UL << ART_CTR_EN_Pos) /*!< 0x00000001 */
4078#define ART_CTR_EN ART_CTR_EN_Msk /*!< Cache enable*/
4079
4080#define ART_CTR_PCACHEADDR_Pos (8U)
4081#define ART_CTR_PCACHEADDR_Msk (0xFFFUL << ART_CTR_PCACHEADDR_Pos) /*!< 0x000FFF00 */
4082#define ART_CTR_PCACHEADDR ART_CTR_PCACHEADDR_Msk /*!< Cacheable page index */
4083
4084/******************************************************************************/
4085/* */
4086/* VREFBUF */
4087/* */
4088/******************************************************************************/
4089/******************* Bit definition for VREFBUF_CSR register ****************/
4090#define VREFBUF_CSR_ENVR_Pos (0U)
4091#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
4092#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
4093#define VREFBUF_CSR_HIZ_Pos (1U)
4094#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
4095#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
4096#define VREFBUF_CSR_VRR_Pos (3U)
4097#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
4098#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
4099#define VREFBUF_CSR_VRS_Pos (4U)
4100#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
4101#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
4102
4103#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
4104#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
4105#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
4106#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
4107#define VREFBUF_CSR_VRS_OUT3_Pos (5U)
4108#define VREFBUF_CSR_VRS_OUT3_Msk (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos) /*!< 0x00000020 */
4109#define VREFBUF_CSR_VRS_OUT3 VREFBUF_CSR_VRS_OUT3_Msk /*!<Voltage reference VREF_OUT3 */
4110#define VREFBUF_CSR_VRS_OUT4_Pos (4U)
4111#define VREFBUF_CSR_VRS_OUT4_Msk (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos) /*!< 0x00000030 */
4112#define VREFBUF_CSR_VRS_OUT4 VREFBUF_CSR_VRS_OUT4_Msk /*!<Voltage reference VREF_OUT4 */
4113
4114/******************* Bit definition for VREFBUF_CCR register ****************/
4115#define VREFBUF_CCR_TRIM_Pos (0U)
4116#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
4117#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
4118
4119/******************************************************************************/
4120/* */
4121/* Flexible Datarate Controller Area Network */
4122/* */
4123/******************************************************************************/
4124/*!<FDCAN control and status registers */
4125/***************** Bit definition for FDCAN_CREL register *******************/
4126#define FDCAN_CREL_DAY_Pos (0U)
4127#define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */
4128#define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */
4129#define FDCAN_CREL_MON_Pos (8U)
4130#define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */
4131#define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */
4132#define FDCAN_CREL_YEAR_Pos (16U)
4133#define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */
4134#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */
4135#define FDCAN_CREL_SUBSTEP_Pos (20U)
4136#define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
4137#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
4138#define FDCAN_CREL_STEP_Pos (24U)
4139#define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */
4140#define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */
4141#define FDCAN_CREL_REL_Pos (28U)
4142#define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */
4143#define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */
4144
4145/***************** Bit definition for FDCAN_ENDN register *******************/
4146#define FDCAN_ENDN_ETV_Pos (0U)
4147#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
4148#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
4149
4150/***************** Bit definition for FDCAN_DBTP register *******************/
4151#define FDCAN_DBTP_DSJW_Pos (0U)
4152#define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */
4153#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */
4154#define FDCAN_DBTP_DTSEG2_Pos (4U)
4155#define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */
4156#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */
4157#define FDCAN_DBTP_DTSEG1_Pos (8U)
4158#define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */
4159#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */
4160#define FDCAN_DBTP_DBRP_Pos (16U)
4161#define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */
4162#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */
4163#define FDCAN_DBTP_TDC_Pos (23U)
4164#define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */
4165#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */
4166
4167/***************** Bit definition for FDCAN_TEST register *******************/
4168#define FDCAN_TEST_LBCK_Pos (4U)
4169#define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */
4170#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */
4171#define FDCAN_TEST_TX_Pos (5U)
4172#define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */
4173#define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */
4174#define FDCAN_TEST_RX_Pos (7U)
4175#define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */
4176#define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */
4177
4178/***************** Bit definition for FDCAN_RWD register ********************/
4179#define FDCAN_RWD_WDC_Pos (0U)
4180#define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */
4181#define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */
4182#define FDCAN_RWD_WDV_Pos (8U)
4183#define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */
4184#define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */
4185
4186/***************** Bit definition for FDCAN_CCCR register ********************/
4187#define FDCAN_CCCR_INIT_Pos (0U)
4188#define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
4189#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */
4190#define FDCAN_CCCR_CCE_Pos (1U)
4191#define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */
4192#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */
4193#define FDCAN_CCCR_ASM_Pos (2U)
4194#define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */
4195#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */
4196#define FDCAN_CCCR_CSA_Pos (3U)
4197#define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */
4198#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */
4199#define FDCAN_CCCR_CSR_Pos (4U)
4200#define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */
4201#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */
4202#define FDCAN_CCCR_MON_Pos (5U)
4203#define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */
4204#define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */
4205#define FDCAN_CCCR_DAR_Pos (6U)
4206#define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */
4207#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */
4208#define FDCAN_CCCR_TEST_Pos (7U)
4209#define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */
4210#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */
4211#define FDCAN_CCCR_FDOE_Pos (8U)
4212#define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */
4213#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */
4214#define FDCAN_CCCR_BRSE_Pos (9U)
4215#define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */
4216#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */
4217#define FDCAN_CCCR_PXHD_Pos (12U)
4218#define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */
4219#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */
4220#define FDCAN_CCCR_EFBI_Pos (13U)
4221#define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */
4222#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */
4223#define FDCAN_CCCR_TXP_Pos (14U)
4224#define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */
4225#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */
4226#define FDCAN_CCCR_NISO_Pos (15U)
4227#define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */
4228#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */
4229
4230/***************** Bit definition for FDCAN_NBTP register ********************/
4231#define FDCAN_NBTP_NTSEG2_Pos (0U)
4232#define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */
4233#define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */
4234#define FDCAN_NBTP_NTSEG1_Pos (8U)
4235#define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */
4236#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */
4237#define FDCAN_NBTP_NBRP_Pos (16U)
4238#define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */
4239#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */
4240#define FDCAN_NBTP_NSJW_Pos (25U)
4241#define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */
4242#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */
4243
4244/***************** Bit definition for FDCAN_TSCC register ********************/
4245#define FDCAN_TSCC_TSS_Pos (0U)
4246#define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */
4247#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */
4248#define FDCAN_TSCC_TCP_Pos (16U)
4249#define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */
4250#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */
4251
4252/***************** Bit definition for FDCAN_TSCV register ********************/
4253#define FDCAN_TSCV_TSC_Pos (0U)
4254#define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */
4255#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */
4256
4257/***************** Bit definition for FDCAN_TOCC register ********************/
4258#define FDCAN_TOCC_ETOC_Pos (0U)
4259#define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */
4260#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */
4261#define FDCAN_TOCC_TOS_Pos (1U)
4262#define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */
4263#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */
4264#define FDCAN_TOCC_TOP_Pos (16U)
4265#define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */
4266#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */
4267
4268/***************** Bit definition for FDCAN_TOCV register ********************/
4269#define FDCAN_TOCV_TOC_Pos (0U)
4270#define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */
4271#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */
4272
4273/***************** Bit definition for FDCAN_ECR register *********************/
4274#define FDCAN_ECR_TEC_Pos (0U)
4275#define FDCAN_ECR_TEC_Msk (0xFUL << FDCAN_ECR_TEC_Pos) /*!< 0x0000000F */
4276#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
4277#define FDCAN_ECR_REC_Pos (8U)
4278#define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */
4279#define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */
4280#define FDCAN_ECR_RP_Pos (15U)
4281#define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */
4282#define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */
4283#define FDCAN_ECR_CEL_Pos (16U)
4284#define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */
4285#define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */
4286
4287/***************** Bit definition for FDCAN_PSR register *********************/
4288#define FDCAN_PSR_LEC_Pos (0U)
4289#define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */
4290#define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */
4291#define FDCAN_PSR_ACT_Pos (3U)
4292#define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */
4293#define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */
4294#define FDCAN_PSR_EP_Pos (5U)
4295#define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */
4296#define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */
4297#define FDCAN_PSR_EW_Pos (6U)
4298#define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */
4299#define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */
4300#define FDCAN_PSR_BO_Pos (7U)
4301#define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */
4302#define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */
4303#define FDCAN_PSR_DLEC_Pos (8U)
4304#define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */
4305#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */
4306#define FDCAN_PSR_RESI_Pos (11U)
4307#define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */
4308#define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */
4309#define FDCAN_PSR_RBRS_Pos (12U)
4310#define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */
4311#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */
4312#define FDCAN_PSR_REDL_Pos (13U)
4313#define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */
4314#define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */
4315#define FDCAN_PSR_PXE_Pos (14U)
4316#define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */
4317#define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */
4318#define FDCAN_PSR_TDCV_Pos (16U)
4319#define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */
4320#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */
4321
4322/***************** Bit definition for FDCAN_TDCR register ********************/
4323#define FDCAN_TDCR_TDCF_Pos (0U)
4324#define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */
4325#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */
4326#define FDCAN_TDCR_TDCO_Pos (8U)
4327#define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */
4328#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */
4329
4330/***************** Bit definition for FDCAN_IR register **********************/
4331#define FDCAN_IR_RF0N_Pos (0U)
4332#define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */
4333#define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */
4334#define FDCAN_IR_RF0W_Pos (1U)
4335#define FDCAN_IR_RF0W_Msk (0x1UL << FDCAN_IR_RF0W_Pos) /*!< 0x00000002 */
4336#define FDCAN_IR_RF0W FDCAN_IR_RF0W_Msk /*!<Rx FIFO 0 Watermark Reached */
4337#define FDCAN_IR_RF0F_Pos (2U)
4338#define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) /*!< 0x00000004 */
4339#define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */
4340#define FDCAN_IR_RF0L_Pos (3U)
4341#define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) /*!< 0x00000008 */
4342#define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
4343#define FDCAN_IR_RF1N_Pos (4U)
4344#define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) /*!< 0x00000010 */
4345#define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */
4346#define FDCAN_IR_RF1W_Pos (5U)
4347#define FDCAN_IR_RF1W_Msk (0x1UL << FDCAN_IR_RF1W_Pos) /*!< 0x00000020 */
4348#define FDCAN_IR_RF1W FDCAN_IR_RF1W_Msk /*!<Rx FIFO 1 Watermark Reached */
4349#define FDCAN_IR_RF1F_Pos (6U)
4350#define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) /*!< 0x00000040 */
4351#define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */
4352#define FDCAN_IR_RF1L_Pos (7U)
4353#define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) /*!< 0x00000080 */
4354#define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
4355#define FDCAN_IR_HPM_Pos (8U)
4356#define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) /*!< 0x00000100 */
4357#define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */
4358#define FDCAN_IR_TC_Pos (9U)
4359#define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) /*!< 0x00000200 */
4360#define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */
4361#define FDCAN_IR_TCF_Pos (10U)
4362#define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) /*!< 0x00000400 */
4363#define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */
4364#define FDCAN_IR_TFE_Pos (11U)
4365#define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) /*!< 0x00000800 */
4366#define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */
4367#define FDCAN_IR_TEFN_Pos (12U)
4368#define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) /*!< 0x00001000 */
4369#define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */
4370#define FDCAN_IR_TEFW_Pos (13U)
4371#define FDCAN_IR_TEFW_Msk (0x1UL << FDCAN_IR_TEFW_Pos) /*!< 0x00002000 */
4372#define FDCAN_IR_TEFW FDCAN_IR_TEFW_Msk /*!<Tx Event FIFO Watermark Reached */
4373#define FDCAN_IR_TEFF_Pos (14U)
4374#define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) /*!< 0x00004000 */
4375#define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */
4376#define FDCAN_IR_TEFL_Pos (15U)
4377#define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) /*!< 0x00008000 */
4378#define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */
4379#define FDCAN_IR_TSW_Pos (16U)
4380#define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) /*!< 0x00010000 */
4381#define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */
4382#define FDCAN_IR_MRAF_Pos (17U)
4383#define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) /*!< 0x00020000 */
4384#define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */
4385#define FDCAN_IR_TOO_Pos (18U)
4386#define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) /*!< 0x00040000 */
4387#define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */
4388#define FDCAN_IR_DRX_Pos (19U)
4389#define FDCAN_IR_DRX_Msk (0x1UL << FDCAN_IR_DRX_Pos) /*!< 0x00080000 */
4390#define FDCAN_IR_DRX FDCAN_IR_DRX_Msk /*!<Message stored to Dedicated Rx Buffer */
4391#define FDCAN_IR_ELO_Pos (22U)
4392#define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) /*!< 0x00400000 */
4393#define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */
4394#define FDCAN_IR_EP_Pos (23U)
4395#define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) /*!< 0x00800000 */
4396#define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */
4397#define FDCAN_IR_EW_Pos (24U)
4398#define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) /*!< 0x01000000 */
4399#define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */
4400#define FDCAN_IR_BO_Pos (25U)
4401#define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) /*!< 0x02000000 */
4402#define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */
4403#define FDCAN_IR_WDI_Pos (26U)
4404#define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) /*!< 0x04000000 */
4405#define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */
4406#define FDCAN_IR_PEA_Pos (27U)
4407#define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) /*!< 0x08000000 */
4408#define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */
4409#define FDCAN_IR_PED_Pos (28U)
4410#define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) /*!< 0x10000000 */
4411#define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */
4412#define FDCAN_IR_ARA_Pos (29U)
4413#define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) /*!< 0x20000000 */
4414#define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */
4415
4416/***************** Bit definition for FDCAN_IE register **********************/
4417#define FDCAN_IE_RF0NE_Pos (0U)
4418#define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */
4419#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */
4420#define FDCAN_IE_RF0WE_Pos (1U)
4421#define FDCAN_IE_RF0WE_Msk (0x1UL << FDCAN_IE_RF0WE_Pos) /*!< 0x00000002 */
4422#define FDCAN_IE_RF0WE FDCAN_IE_RF0WE_Msk /*!<Rx FIFO 0 Watermark Reached Enable */
4423#define FDCAN_IE_RF0FE_Pos (2U)
4424#define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) /*!< 0x00000004 */
4425#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */
4426#define FDCAN_IE_RF0LE_Pos (3U)
4427#define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) /*!< 0x00000008 */
4428#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */
4429#define FDCAN_IE_RF1NE_Pos (4U)
4430#define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) /*!< 0x00000010 */
4431#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */
4432#define FDCAN_IE_RF1WE_Pos (5U)
4433#define FDCAN_IE_RF1WE_Msk (0x1UL << FDCAN_IE_RF1WE_Pos) /*!< 0x00000020 */
4434#define FDCAN_IE_RF1WE FDCAN_IE_RF1WE_Msk /*!<Rx FIFO 1 Watermark Reached Enable */
4435#define FDCAN_IE_RF1FE_Pos (6U)
4436#define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) /*!< 0x00000040 */
4437#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */
4438#define FDCAN_IE_RF1LE_Pos (7U)
4439#define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) /*!< 0x00000080 */
4440#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */
4441#define FDCAN_IE_HPME_Pos (8U)
4442#define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) /*!< 0x00000100 */
4443#define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */
4444#define FDCAN_IE_TCE_Pos (9U)
4445#define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) /*!< 0x00000200 */
4446#define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */
4447#define FDCAN_IE_TCFE_Pos (10U)
4448#define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) /*!< 0x00000400 */
4449#define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable */
4450#define FDCAN_IE_TFEE_Pos (11U)
4451#define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) /*!< 0x00000800 */
4452#define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */
4453#define FDCAN_IE_TEFNE_Pos (12U)
4454#define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) /*!< 0x00001000 */
4455#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */
4456#define FDCAN_IE_TEFWE_Pos (13U)
4457#define FDCAN_IE_TEFWE_Msk (0x1UL << FDCAN_IE_TEFWE_Pos) /*!< 0x00002000 */
4458#define FDCAN_IE_TEFWE FDCAN_IE_TEFWE_Msk /*!<Tx Event FIFO Watermark Reached Enable */
4459#define FDCAN_IE_TEFFE_Pos (14U)
4460#define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) /*!< 0x00004000 */
4461#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */
4462#define FDCAN_IE_TEFLE_Pos (15U)
4463#define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) /*!< 0x00008000 */
4464#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */
4465#define FDCAN_IE_TSWE_Pos (16U)
4466#define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) /*!< 0x00010000 */
4467#define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */
4468#define FDCAN_IE_MRAFE_Pos (17U)
4469#define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) /*!< 0x00020000 */
4470#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */
4471#define FDCAN_IE_TOOE_Pos (18U)
4472#define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) /*!< 0x00040000 */
4473#define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */
4474#define FDCAN_IE_DRXE_Pos (19U)
4475#define FDCAN_IE_DRXE_Msk (0x1UL << FDCAN_IE_DRXE_Pos) /*!< 0x00080000 */
4476#define FDCAN_IE_DRXE FDCAN_IE_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Enable */
4477#define FDCAN_IE_BECE_Pos (20U)
4478#define FDCAN_IE_BECE_Msk (0x1UL << FDCAN_IE_BECE_Pos) /*!< 0x00100000 */
4479#define FDCAN_IE_BECE FDCAN_IE_BECE_Msk /*!<Bit Error Corrected Interrupt Enable */
4480#define FDCAN_IE_BEUE_Pos (21U)
4481#define FDCAN_IE_BEUE_Msk (0x1UL << FDCAN_IE_BEUE_Pos) /*!< 0x00200000 */
4482#define FDCAN_IE_BEUE FDCAN_IE_BEUE_Msk /*!<Bit Error Uncorrected Interrupt Enable */
4483#define FDCAN_IE_ELOE_Pos (22U)
4484#define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) /*!< 0x00400000 */
4485#define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */
4486#define FDCAN_IE_EPE_Pos (23U)
4487#define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) /*!< 0x00800000 */
4488#define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */
4489#define FDCAN_IE_EWE_Pos (24U)
4490#define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) /*!< 0x01000000 */
4491#define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */
4492#define FDCAN_IE_BOE_Pos (25U)
4493#define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) /*!< 0x02000000 */
4494#define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */
4495#define FDCAN_IE_WDIE_Pos (26U)
4496#define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) /*!< 0x04000000 */
4497#define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */
4498#define FDCAN_IE_PEAE_Pos (27U)
4499#define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) /*!< 0x08000000 */
4500#define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable */
4501#define FDCAN_IE_PEDE_Pos (28U)
4502#define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) /*!< 0x10000000 */
4503#define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */
4504#define FDCAN_IE_ARAE_Pos (29U)
4505#define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) /*!< 0x20000000 */
4506#define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */
4507
4508/***************** Bit definition for FDCAN_ILS register **********************/
4509#define FDCAN_ILS_RF0NL_Pos (0U)
4510#define FDCAN_ILS_RF0NL_Msk (0x1UL << FDCAN_ILS_RF0NL_Pos) /*!< 0x00000001 */
4511#define FDCAN_ILS_RF0NL FDCAN_ILS_RF0NL_Msk /*!<Rx FIFO 0 New Message Line */
4512#define FDCAN_ILS_RF0WL_Pos (1U)
4513#define FDCAN_ILS_RF0WL_Msk (0x1UL << FDCAN_ILS_RF0WL_Pos) /*!< 0x00000002 */
4514#define FDCAN_ILS_RF0WL FDCAN_ILS_RF0WL_Msk /*!<Rx FIFO 0 Watermark Reached Line */
4515#define FDCAN_ILS_RF0FL_Pos (2U)
4516#define FDCAN_ILS_RF0FL_Msk (0x1UL << FDCAN_ILS_RF0FL_Pos) /*!< 0x00000004 */
4517#define FDCAN_ILS_RF0FL FDCAN_ILS_RF0FL_Msk /*!<Rx FIFO 0 Full Line */
4518#define FDCAN_ILS_RF0LL_Pos (3U)
4519#define FDCAN_ILS_RF0LL_Msk (0x1UL << FDCAN_ILS_RF0LL_Pos) /*!< 0x00000008 */
4520#define FDCAN_ILS_RF0LL FDCAN_ILS_RF0LL_Msk /*!<Rx FIFO 0 Message Lost Line */
4521#define FDCAN_ILS_RF1NL_Pos (4U)
4522#define FDCAN_ILS_RF1NL_Msk (0x1UL << FDCAN_ILS_RF1NL_Pos) /*!< 0x00000010 */
4523#define FDCAN_ILS_RF1NL FDCAN_ILS_RF1NL_Msk /*!<Rx FIFO 1 New Message Line */
4524#define FDCAN_ILS_RF1WL_Pos (5U)
4525#define FDCAN_ILS_RF1WL_Msk (0x1UL << FDCAN_ILS_RF1WL_Pos) /*!< 0x00000020 */
4526#define FDCAN_ILS_RF1WL FDCAN_ILS_RF1WL_Msk /*!<Rx FIFO 1 Watermark Reached Line */
4527#define FDCAN_ILS_RF1FL_Pos (6U)
4528#define FDCAN_ILS_RF1FL_Msk (0x1UL << FDCAN_ILS_RF1FL_Pos) /*!< 0x00000040 */
4529#define FDCAN_ILS_RF1FL FDCAN_ILS_RF1FL_Msk /*!<Rx FIFO 1 Full Line */
4530#define FDCAN_ILS_RF1LL_Pos (7U)
4531#define FDCAN_ILS_RF1LL_Msk (0x1UL << FDCAN_ILS_RF1LL_Pos) /*!< 0x00000080 */
4532#define FDCAN_ILS_RF1LL FDCAN_ILS_RF1LL_Msk /*!<Rx FIFO 1 Message Lost Line */
4533#define FDCAN_ILS_HPML_Pos (8U)
4534#define FDCAN_ILS_HPML_Msk (0x1UL << FDCAN_ILS_HPML_Pos) /*!< 0x00000100 */
4535#define FDCAN_ILS_HPML FDCAN_ILS_HPML_Msk /*!<High Priority Message Line */
4536#define FDCAN_ILS_TCL_Pos (9U)
4537#define FDCAN_ILS_TCL_Msk (0x1UL << FDCAN_ILS_TCL_Pos) /*!< 0x00000200 */
4538#define FDCAN_ILS_TCL FDCAN_ILS_TCL_Msk /*!<Transmission Completed Line */
4539#define FDCAN_ILS_TCFL_Pos (10U)
4540#define FDCAN_ILS_TCFL_Msk (0x1UL << FDCAN_ILS_TCFL_Pos) /*!< 0x00000400 */
4541#define FDCAN_ILS_TCFL FDCAN_ILS_TCFL_Msk /*!<Transmission Cancellation Finished Line */
4542#define FDCAN_ILS_TFEL_Pos (11U)
4543#define FDCAN_ILS_TFEL_Msk (0x1UL << FDCAN_ILS_TFEL_Pos) /*!< 0x00000800 */
4544#define FDCAN_ILS_TFEL FDCAN_ILS_TFEL_Msk /*!<Tx FIFO Empty Line */
4545#define FDCAN_ILS_TEFNL_Pos (12U)
4546#define FDCAN_ILS_TEFNL_Msk (0x1UL << FDCAN_ILS_TEFNL_Pos) /*!< 0x00001000 */
4547#define FDCAN_ILS_TEFNL FDCAN_ILS_TEFNL_Msk /*!<Tx Event FIFO New Entry Line */
4548#define FDCAN_ILS_TEFWL_Pos (13U)
4549#define FDCAN_ILS_TEFWL_Msk (0x1UL << FDCAN_ILS_TEFWL_Pos) /*!< 0x00002000 */
4550#define FDCAN_ILS_TEFWL FDCAN_ILS_TEFWL_Msk /*!<Tx Event FIFO Watermark Reached Line */
4551#define FDCAN_ILS_TEFFL_Pos (14U)
4552#define FDCAN_ILS_TEFFL_Msk (0x1UL << FDCAN_ILS_TEFFL_Pos) /*!< 0x00004000 */
4553#define FDCAN_ILS_TEFFL FDCAN_ILS_TEFFL_Msk /*!<Tx Event FIFO Full Line */
4554#define FDCAN_ILS_TEFLL_Pos (15U)
4555#define FDCAN_ILS_TEFLL_Msk (0x1UL << FDCAN_ILS_TEFLL_Pos) /*!< 0x00008000 */
4556#define FDCAN_ILS_TEFLL FDCAN_ILS_TEFLL_Msk /*!<Tx Event FIFO Element Lost Line */
4557#define FDCAN_ILS_TSWL_Pos (16U)
4558#define FDCAN_ILS_TSWL_Msk (0x1UL << FDCAN_ILS_TSWL_Pos) /*!< 0x00010000 */
4559#define FDCAN_ILS_TSWL FDCAN_ILS_TSWL_Msk /*!<Timestamp Wraparound Line */
4560#define FDCAN_ILS_MRAFE_Pos (17U)
4561#define FDCAN_ILS_MRAFE_Msk (0x1UL << FDCAN_ILS_MRAFE_Pos) /*!< 0x00020000 */
4562#define FDCAN_ILS_MRAFE FDCAN_ILS_MRAFE_Msk /*!<Message RAM Access Failure Line */
4563#define FDCAN_ILS_TOOE_Pos (18U)
4564#define FDCAN_ILS_TOOE_Msk (0x1UL << FDCAN_ILS_TOOE_Pos) /*!< 0x00040000 */
4565#define FDCAN_ILS_TOOE FDCAN_ILS_TOOE_Msk /*!<Timeout Occurred Line */
4566#define FDCAN_ILS_DRXE_Pos (19U)
4567#define FDCAN_ILS_DRXE_Msk (0x1UL << FDCAN_ILS_DRXE_Pos) /*!< 0x00080000 */
4568#define FDCAN_ILS_DRXE FDCAN_ILS_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Line */
4569#define FDCAN_ILS_BECE_Pos (20U)
4570#define FDCAN_ILS_BECE_Msk (0x1UL << FDCAN_ILS_BECE_Pos) /*!< 0x00100000 */
4571#define FDCAN_ILS_BECE FDCAN_ILS_BECE_Msk /*!<Bit Error Corrected Interrupt Line */
4572#define FDCAN_ILS_BEUE_Pos (21U)
4573#define FDCAN_ILS_BEUE_Msk (0x1UL << FDCAN_ILS_BEUE_Pos) /*!< 0x00200000 */
4574#define FDCAN_ILS_BEUE FDCAN_ILS_BEUE_Msk /*!<Bit Error Uncorrected Interrupt Line */
4575#define FDCAN_ILS_ELOE_Pos (22U)
4576#define FDCAN_ILS_ELOE_Msk (0x1UL << FDCAN_ILS_ELOE_Pos) /*!< 0x00400000 */
4577#define FDCAN_ILS_ELOE FDCAN_ILS_ELOE_Msk /*!<Error Logging Overflow Line */
4578#define FDCAN_ILS_EPE_Pos (23U)
4579#define FDCAN_ILS_EPE_Msk (0x1UL << FDCAN_ILS_EPE_Pos) /*!< 0x00800000 */
4580#define FDCAN_ILS_EPE FDCAN_ILS_EPE_Msk /*!<Error Passive Line */
4581#define FDCAN_ILS_EWE_Pos (24U)
4582#define FDCAN_ILS_EWE_Msk (0x1UL << FDCAN_ILS_EWE_Pos) /*!< 0x01000000 */
4583#define FDCAN_ILS_EWE FDCAN_ILS_EWE_Msk /*!<Warning Status Line */
4584#define FDCAN_ILS_BOE_Pos (25U)
4585#define FDCAN_ILS_BOE_Msk (0x1UL << FDCAN_ILS_BOE_Pos) /*!< 0x02000000 */
4586#define FDCAN_ILS_BOE FDCAN_ILS_BOE_Msk /*!<Bus_Off Status Line */
4587#define FDCAN_ILS_WDIE_Pos (26U)
4588#define FDCAN_ILS_WDIE_Msk (0x1UL << FDCAN_ILS_WDIE_Pos) /*!< 0x04000000 */
4589#define FDCAN_ILS_WDIE FDCAN_ILS_WDIE_Msk /*!<Watchdog Interrupt Line */
4590#define FDCAN_ILS_PEAE_Pos (27U)
4591#define FDCAN_ILS_PEAE_Msk (0x1UL << FDCAN_ILS_PEAE_Pos) /*!< 0x08000000 */
4592#define FDCAN_ILS_PEAE FDCAN_ILS_PEAE_Msk /*!<Protocol Error in Arbitration Phase Line */
4593#define FDCAN_ILS_PEDE_Pos (28U)
4594#define FDCAN_ILS_PEDE_Msk (0x1UL << FDCAN_ILS_PEDE_Pos) /*!< 0x10000000 */
4595#define FDCAN_ILS_PEDE FDCAN_ILS_PEDE_Msk /*!<Protocol Error in Data Phase Line */
4596#define FDCAN_ILS_ARAE_Pos (29U)
4597#define FDCAN_ILS_ARAE_Msk (0x1UL << FDCAN_ILS_ARAE_Pos) /*!< 0x20000000 */
4598#define FDCAN_ILS_ARAE FDCAN_ILS_ARAE_Msk /*!<Access to Reserved Address Line */
4599
4600/***************** Bit definition for FDCAN_ILE register **********************/
4601#define FDCAN_ILE_EINT0_Pos (0U)
4602#define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */
4603#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */
4604#define FDCAN_ILE_EINT1_Pos (1U)
4605#define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */
4606#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */
4607
4608/***************** Bit definition for FDCAN_GFC register **********************/
4609#define FDCAN_GFC_RRFE_Pos (0U)
4610#define FDCAN_GFC_RRFE_Msk (0x1UL << FDCAN_GFC_RRFE_Pos) /*!< 0x00000001 */
4611#define FDCAN_GFC_RRFE FDCAN_GFC_RRFE_Msk /*!<Reject Remote Frames Extended */
4612#define FDCAN_GFC_RRFS_Pos (1U)
4613#define FDCAN_GFC_RRFS_Msk (0x1UL << FDCAN_GFC_RRFS_Pos) /*!< 0x00000002 */
4614#define FDCAN_GFC_RRFS FDCAN_GFC_RRFS_Msk /*!<Reject Remote Frames Standard */
4615#define FDCAN_GFC_ANFE_Pos (2U)
4616#define FDCAN_GFC_ANFE_Msk (0x3UL << FDCAN_GFC_ANFE_Pos) /*!< 0x0000000C */
4617#define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */
4618#define FDCAN_GFC_ANFS_Pos (4U)
4619#define FDCAN_GFC_ANFS_Msk (0x3UL << FDCAN_GFC_ANFS_Pos) /*!< 0x00000030 */
4620#define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */
4621
4622/***************** Bit definition for FDCAN_SIDFC register ********************/
4623#define FDCAN_SIDFC_FLSSA_Pos (2U)
4624#define FDCAN_SIDFC_FLSSA_Msk (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos) /*!< 0x0000FFFC */
4625#define FDCAN_SIDFC_FLSSA FDCAN_SIDFC_FLSSA_Msk /*!<Filter List Standard Start Address */
4626#define FDCAN_SIDFC_LSS_Pos (16U)
4627#define FDCAN_SIDFC_LSS_Msk (0xFFUL << FDCAN_SIDFC_LSS_Pos) /*!< 0x00FF0000 */
4628#define FDCAN_SIDFC_LSS FDCAN_SIDFC_LSS_Msk /*!<List Size Standard */
4629
4630/***************** Bit definition for FDCAN_XIDFC register ********************/
4631#define FDCAN_XIDFC_FLESA_Pos (2U)
4632#define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
4633#define FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_Msk /*!<Filter List Standard Start Address */
4634#define FDCAN_XIDFC_LSE_Pos (16U)
4635#define FDCAN_XIDFC_LSE_Msk (0x7FUL << FDCAN_XIDFC_LSE_Pos) /*!< 0x007F0000 */
4636#define FDCAN_XIDFC_LSE FDCAN_XIDFC_LSE_Msk /*!<List Size Extended */
4637
4638/***************** Bit definition for FDCAN_XIDAM register ********************/
4639#define FDCAN_XIDAM_EIDM_Pos (0U)
4640#define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */
4641#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */
4642
4643/***************** Bit definition for FDCAN_HPMS register *********************/
4644#define FDCAN_HPMS_BIDX_Pos (0U)
4645#define FDCAN_HPMS_BIDX_Msk (0x3FUL << FDCAN_HPMS_BIDX_Pos) /*!< 0x0000003F */
4646#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */
4647#define FDCAN_HPMS_MSI_Pos (6U)
4648#define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */
4649#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */
4650#define FDCAN_HPMS_FIDX_Pos (8U)
4651#define FDCAN_HPMS_FIDX_Msk (0x7FUL << FDCAN_HPMS_FIDX_Pos) /*!< 0x00007F00 */
4652#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */
4653#define FDCAN_HPMS_FLST_Pos (15U)
4654#define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */
4655#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */
4656
4657/***************** Bit definition for FDCAN_NDAT1 register ********************/
4658#define FDCAN_NDAT1_ND0_Pos (0U)
4659#define FDCAN_NDAT1_ND0_Msk (0x1UL << FDCAN_NDAT1_ND0_Pos) /*!< 0x00000001 */
4660#define FDCAN_NDAT1_ND0 FDCAN_NDAT1_ND0_Msk /*!<New Data flag of Rx Buffer 0 */
4661#define FDCAN_NDAT1_ND1_Pos (1U)
4662#define FDCAN_NDAT1_ND1_Msk (0x1UL << FDCAN_NDAT1_ND1_Pos) /*!< 0x00000002 */
4663#define FDCAN_NDAT1_ND1 FDCAN_NDAT1_ND1_Msk /*!<New Data flag of Rx Buffer 1 */
4664#define FDCAN_NDAT1_ND2_Pos (2U)
4665#define FDCAN_NDAT1_ND2_Msk (0x1UL << FDCAN_NDAT1_ND2_Pos) /*!< 0x00000004 */
4666#define FDCAN_NDAT1_ND2 FDCAN_NDAT1_ND2_Msk /*!<New Data flag of Rx Buffer 2 */
4667#define FDCAN_NDAT1_ND3_Pos (3U)
4668#define FDCAN_NDAT1_ND3_Msk (0x1UL << FDCAN_NDAT1_ND3_Pos) /*!< 0x00000008 */
4669#define FDCAN_NDAT1_ND3 FDCAN_NDAT1_ND3_Msk /*!<New Data flag of Rx Buffer 3 */
4670#define FDCAN_NDAT1_ND4_Pos (4U)
4671#define FDCAN_NDAT1_ND4_Msk (0x1UL << FDCAN_NDAT1_ND4_Pos) /*!< 0x00000010 */
4672#define FDCAN_NDAT1_ND4 FDCAN_NDAT1_ND4_Msk /*!<New Data flag of Rx Buffer 4 */
4673#define FDCAN_NDAT1_ND5_Pos (5U)
4674#define FDCAN_NDAT1_ND5_Msk (0x1UL << FDCAN_NDAT1_ND5_Pos) /*!< 0x00000020 */
4675#define FDCAN_NDAT1_ND5 FDCAN_NDAT1_ND5_Msk /*!<New Data flag of Rx Buffer 5 */
4676#define FDCAN_NDAT1_ND6_Pos (6U)
4677#define FDCAN_NDAT1_ND6_Msk (0x1UL << FDCAN_NDAT1_ND6_Pos) /*!< 0x00000040 */
4678#define FDCAN_NDAT1_ND6 FDCAN_NDAT1_ND6_Msk /*!<New Data flag of Rx Buffer 6 */
4679#define FDCAN_NDAT1_ND7_Pos (7U)
4680#define FDCAN_NDAT1_ND7_Msk (0x1UL << FDCAN_NDAT1_ND7_Pos) /*!< 0x00000080 */
4681#define FDCAN_NDAT1_ND7 FDCAN_NDAT1_ND7_Msk /*!<New Data flag of Rx Buffer 7 */
4682#define FDCAN_NDAT1_ND8_Pos (8U)
4683#define FDCAN_NDAT1_ND8_Msk (0x1UL << FDCAN_NDAT1_ND8_Pos) /*!< 0x00000100 */
4684#define FDCAN_NDAT1_ND8 FDCAN_NDAT1_ND8_Msk /*!<New Data flag of Rx Buffer 8 */
4685#define FDCAN_NDAT1_ND9_Pos (9U)
4686#define FDCAN_NDAT1_ND9_Msk (0x1UL << FDCAN_NDAT1_ND9_Pos) /*!< 0x00000200 */
4687#define FDCAN_NDAT1_ND9 FDCAN_NDAT1_ND9_Msk /*!<New Data flag of Rx Buffer 9 */
4688#define FDCAN_NDAT1_ND10_Pos (10U)
4689#define FDCAN_NDAT1_ND10_Msk (0x1UL << FDCAN_NDAT1_ND10_Pos) /*!< 0x00000400 */
4690#define FDCAN_NDAT1_ND10 FDCAN_NDAT1_ND10_Msk /*!<New Data flag of Rx Buffer 10 */
4691#define FDCAN_NDAT1_ND11_Pos (11U)
4692#define FDCAN_NDAT1_ND11_Msk (0x1UL << FDCAN_NDAT1_ND11_Pos) /*!< 0x00000800 */
4693#define FDCAN_NDAT1_ND11 FDCAN_NDAT1_ND11_Msk /*!<New Data flag of Rx Buffer 11 */
4694#define FDCAN_NDAT1_ND12_Pos (12U)
4695#define FDCAN_NDAT1_ND12_Msk (0x1UL << FDCAN_NDAT1_ND12_Pos) /*!< 0x00001000 */
4696#define FDCAN_NDAT1_ND12 FDCAN_NDAT1_ND12_Msk /*!<New Data flag of Rx Buffer 12 */
4697#define FDCAN_NDAT1_ND13_Pos (13U)
4698#define FDCAN_NDAT1_ND13_Msk (0x1UL << FDCAN_NDAT1_ND13_Pos) /*!< 0x00002000 */
4699#define FDCAN_NDAT1_ND13 FDCAN_NDAT1_ND13_Msk /*!<New Data flag of Rx Buffer 13 */
4700#define FDCAN_NDAT1_ND14_Pos (14U)
4701#define FDCAN_NDAT1_ND14_Msk (0x1UL << FDCAN_NDAT1_ND14_Pos) /*!< 0x00004000 */
4702#define FDCAN_NDAT1_ND14 FDCAN_NDAT1_ND14_Msk /*!<New Data flag of Rx Buffer 14 */
4703#define FDCAN_NDAT1_ND15_Pos (15U)
4704#define FDCAN_NDAT1_ND15_Msk (0x1UL << FDCAN_NDAT1_ND15_Pos) /*!< 0x00008000 */
4705#define FDCAN_NDAT1_ND15 FDCAN_NDAT1_ND15_Msk /*!<New Data flag of Rx Buffer 15 */
4706#define FDCAN_NDAT1_ND16_Pos (16U)
4707#define FDCAN_NDAT1_ND16_Msk (0x1UL << FDCAN_NDAT1_ND16_Pos) /*!< 0x00010000 */
4708#define FDCAN_NDAT1_ND16 FDCAN_NDAT1_ND16_Msk /*!<New Data flag of Rx Buffer 16 */
4709#define FDCAN_NDAT1_ND17_Pos (17U)
4710#define FDCAN_NDAT1_ND17_Msk (0x1UL << FDCAN_NDAT1_ND17_Pos) /*!< 0x00020000 */
4711#define FDCAN_NDAT1_ND17 FDCAN_NDAT1_ND17_Msk /*!<New Data flag of Rx Buffer 17 */
4712#define FDCAN_NDAT1_ND18_Pos (18U)
4713#define FDCAN_NDAT1_ND18_Msk (0x1UL << FDCAN_NDAT1_ND18_Pos) /*!< 0x00040000 */
4714#define FDCAN_NDAT1_ND18 FDCAN_NDAT1_ND18_Msk /*!<New Data flag of Rx Buffer 18 */
4715#define FDCAN_NDAT1_ND19_Pos (19U)
4716#define FDCAN_NDAT1_ND19_Msk (0x1UL << FDCAN_NDAT1_ND19_Pos) /*!< 0x00080000 */
4717#define FDCAN_NDAT1_ND19 FDCAN_NDAT1_ND19_Msk /*!<New Data flag of Rx Buffer 19 */
4718#define FDCAN_NDAT1_ND20_Pos (20U)
4719#define FDCAN_NDAT1_ND20_Msk (0x1UL << FDCAN_NDAT1_ND20_Pos) /*!< 0x00100000 */
4720#define FDCAN_NDAT1_ND20 FDCAN_NDAT1_ND20_Msk /*!<New Data flag of Rx Buffer 20 */
4721#define FDCAN_NDAT1_ND21_Pos (21U)
4722#define FDCAN_NDAT1_ND21_Msk (0x1UL << FDCAN_NDAT1_ND21_Pos) /*!< 0x00200000 */
4723#define FDCAN_NDAT1_ND21 FDCAN_NDAT1_ND21_Msk /*!<New Data flag of Rx Buffer 21 */
4724#define FDCAN_NDAT1_ND22_Pos (22U)
4725#define FDCAN_NDAT1_ND22_Msk (0x1UL << FDCAN_NDAT1_ND22_Pos) /*!< 0x00400000 */
4726#define FDCAN_NDAT1_ND22 FDCAN_NDAT1_ND22_Msk /*!<New Data flag of Rx Buffer 22 */
4727#define FDCAN_NDAT1_ND23_Pos (23U)
4728#define FDCAN_NDAT1_ND23_Msk (0x1UL << FDCAN_NDAT1_ND23_Pos) /*!< 0x00800000 */
4729#define FDCAN_NDAT1_ND23 FDCAN_NDAT1_ND23_Msk /*!<New Data flag of Rx Buffer 23 */
4730#define FDCAN_NDAT1_ND24_Pos (24U)
4731#define FDCAN_NDAT1_ND24_Msk (0x1UL << FDCAN_NDAT1_ND24_Pos) /*!< 0x01000000 */
4732#define FDCAN_NDAT1_ND24 FDCAN_NDAT1_ND24_Msk /*!<New Data flag of Rx Buffer 24 */
4733#define FDCAN_NDAT1_ND25_Pos (25U)
4734#define FDCAN_NDAT1_ND25_Msk (0x1UL << FDCAN_NDAT1_ND25_Pos) /*!< 0x02000000 */
4735#define FDCAN_NDAT1_ND25 FDCAN_NDAT1_ND25_Msk /*!<New Data flag of Rx Buffer 25 */
4736#define FDCAN_NDAT1_ND26_Pos (26U)
4737#define FDCAN_NDAT1_ND26_Msk (0x1UL << FDCAN_NDAT1_ND26_Pos) /*!< 0x04000000 */
4738#define FDCAN_NDAT1_ND26 FDCAN_NDAT1_ND26_Msk /*!<New Data flag of Rx Buffer 26 */
4739#define FDCAN_NDAT1_ND27_Pos (27U)
4740#define FDCAN_NDAT1_ND27_Msk (0x1UL << FDCAN_NDAT1_ND27_Pos) /*!< 0x08000000 */
4741#define FDCAN_NDAT1_ND27 FDCAN_NDAT1_ND27_Msk /*!<New Data flag of Rx Buffer 27 */
4742#define FDCAN_NDAT1_ND28_Pos (28U)
4743#define FDCAN_NDAT1_ND28_Msk (0x1UL << FDCAN_NDAT1_ND28_Pos) /*!< 0x10000000 */
4744#define FDCAN_NDAT1_ND28 FDCAN_NDAT1_ND28_Msk /*!<New Data flag of Rx Buffer 28 */
4745#define FDCAN_NDAT1_ND29_Pos (29U)
4746#define FDCAN_NDAT1_ND29_Msk (0x1UL << FDCAN_NDAT1_ND29_Pos) /*!< 0x20000000 */
4747#define FDCAN_NDAT1_ND29 FDCAN_NDAT1_ND29_Msk /*!<New Data flag of Rx Buffer 29 */
4748#define FDCAN_NDAT1_ND30_Pos (30U)
4749#define FDCAN_NDAT1_ND30_Msk (0x1UL << FDCAN_NDAT1_ND30_Pos) /*!< 0x40000000 */
4750#define FDCAN_NDAT1_ND30 FDCAN_NDAT1_ND30_Msk /*!<New Data flag of Rx Buffer 30 */
4751#define FDCAN_NDAT1_ND31_Pos (31U)
4752#define FDCAN_NDAT1_ND31_Msk (0x1UL << FDCAN_NDAT1_ND31_Pos) /*!< 0x80000000 */
4753#define FDCAN_NDAT1_ND31 FDCAN_NDAT1_ND31_Msk /*!<New Data flag of Rx Buffer 31 */
4754
4755/***************** Bit definition for FDCAN_NDAT2 register ********************/
4756#define FDCAN_NDAT2_ND32_Pos (0U)
4757#define FDCAN_NDAT2_ND32_Msk (0x1UL << FDCAN_NDAT2_ND32_Pos) /*!< 0x00000001 */
4758#define FDCAN_NDAT2_ND32 FDCAN_NDAT2_ND32_Msk /*!<New Data flag of Rx Buffer 32 */
4759#define FDCAN_NDAT2_ND33_Pos (1U)
4760#define FDCAN_NDAT2_ND33_Msk (0x1UL << FDCAN_NDAT2_ND33_Pos) /*!< 0x00000002 */
4761#define FDCAN_NDAT2_ND33 FDCAN_NDAT2_ND33_Msk /*!<New Data flag of Rx Buffer 33 */
4762#define FDCAN_NDAT2_ND34_Pos (2U)
4763#define FDCAN_NDAT2_ND34_Msk (0x1UL << FDCAN_NDAT2_ND34_Pos) /*!< 0x00000004 */
4764#define FDCAN_NDAT2_ND34 FDCAN_NDAT2_ND34_Msk /*!<New Data flag of Rx Buffer 34 */
4765#define FDCAN_NDAT2_ND35_Pos (3U)
4766#define FDCAN_NDAT2_ND35_Msk (0x1UL << FDCAN_NDAT2_ND35_Pos) /*!< 0x00000008 */
4767#define FDCAN_NDAT2_ND35 FDCAN_NDAT2_ND35_Msk /*!<New Data flag of Rx Buffer 35 */
4768#define FDCAN_NDAT2_ND36_Pos (4U)
4769#define FDCAN_NDAT2_ND36_Msk (0x1UL << FDCAN_NDAT2_ND36_Pos) /*!< 0x00000010 */
4770#define FDCAN_NDAT2_ND36 FDCAN_NDAT2_ND36_Msk /*!<New Data flag of Rx Buffer 36 */
4771#define FDCAN_NDAT2_ND37_Pos (5U)
4772#define FDCAN_NDAT2_ND37_Msk (0x1UL << FDCAN_NDAT2_ND37_Pos) /*!< 0x00000020 */
4773#define FDCAN_NDAT2_ND37 FDCAN_NDAT2_ND37_Msk /*!<New Data flag of Rx Buffer 37 */
4774#define FDCAN_NDAT2_ND38_Pos (6U)
4775#define FDCAN_NDAT2_ND38_Msk (0x1UL << FDCAN_NDAT2_ND38_Pos) /*!< 0x00000040 */
4776#define FDCAN_NDAT2_ND38 FDCAN_NDAT2_ND38_Msk /*!<New Data flag of Rx Buffer 38 */
4777#define FDCAN_NDAT2_ND39_Pos (7U)
4778#define FDCAN_NDAT2_ND39_Msk (0x1UL << FDCAN_NDAT2_ND39_Pos) /*!< 0x00000080 */
4779#define FDCAN_NDAT2_ND39 FDCAN_NDAT2_ND39_Msk /*!<New Data flag of Rx Buffer 39 */
4780#define FDCAN_NDAT2_ND40_Pos (8U)
4781#define FDCAN_NDAT2_ND40_Msk (0x1UL << FDCAN_NDAT2_ND40_Pos) /*!< 0x00000100 */
4782#define FDCAN_NDAT2_ND40 FDCAN_NDAT2_ND40_Msk /*!<New Data flag of Rx Buffer 40 */
4783#define FDCAN_NDAT2_ND41_Pos (9U)
4784#define FDCAN_NDAT2_ND41_Msk (0x1UL << FDCAN_NDAT2_ND41_Pos) /*!< 0x00000200 */
4785#define FDCAN_NDAT2_ND41 FDCAN_NDAT2_ND41_Msk /*!<New Data flag of Rx Buffer 41 */
4786#define FDCAN_NDAT2_ND42_Pos (10U)
4787#define FDCAN_NDAT2_ND42_Msk (0x1UL << FDCAN_NDAT2_ND42_Pos) /*!< 0x00000400 */
4788#define FDCAN_NDAT2_ND42 FDCAN_NDAT2_ND42_Msk /*!<New Data flag of Rx Buffer 42 */
4789#define FDCAN_NDAT2_ND43_Pos (11U)
4790#define FDCAN_NDAT2_ND43_Msk (0x1UL << FDCAN_NDAT2_ND43_Pos) /*!< 0x00000800 */
4791#define FDCAN_NDAT2_ND43 FDCAN_NDAT2_ND43_Msk /*!<New Data flag of Rx Buffer 43 */
4792#define FDCAN_NDAT2_ND44_Pos (12U)
4793#define FDCAN_NDAT2_ND44_Msk (0x1UL << FDCAN_NDAT2_ND44_Pos) /*!< 0x00001000 */
4794#define FDCAN_NDAT2_ND44 FDCAN_NDAT2_ND44_Msk /*!<New Data flag of Rx Buffer 44 */
4795#define FDCAN_NDAT2_ND45_Pos (13U)
4796#define FDCAN_NDAT2_ND45_Msk (0x1UL << FDCAN_NDAT2_ND45_Pos) /*!< 0x00002000 */
4797#define FDCAN_NDAT2_ND45 FDCAN_NDAT2_ND45_Msk /*!<New Data flag of Rx Buffer 45 */
4798#define FDCAN_NDAT2_ND46_Pos (14U)
4799#define FDCAN_NDAT2_ND46_Msk (0x1UL << FDCAN_NDAT2_ND46_Pos) /*!< 0x00004000 */
4800#define FDCAN_NDAT2_ND46 FDCAN_NDAT2_ND46_Msk /*!<New Data flag of Rx Buffer 46 */
4801#define FDCAN_NDAT2_ND47_Pos (15U)
4802#define FDCAN_NDAT2_ND47_Msk (0x1UL << FDCAN_NDAT2_ND47_Pos) /*!< 0x00008000 */
4803#define FDCAN_NDAT2_ND47 FDCAN_NDAT2_ND47_Msk /*!<New Data flag of Rx Buffer 47 */
4804#define FDCAN_NDAT2_ND48_Pos (16U)
4805#define FDCAN_NDAT2_ND48_Msk (0x1UL << FDCAN_NDAT2_ND48_Pos) /*!< 0x00010000 */
4806#define FDCAN_NDAT2_ND48 FDCAN_NDAT2_ND48_Msk /*!<New Data flag of Rx Buffer 48 */
4807#define FDCAN_NDAT2_ND49_Pos (17U)
4808#define FDCAN_NDAT2_ND49_Msk (0x1UL << FDCAN_NDAT2_ND49_Pos) /*!< 0x00020000 */
4809#define FDCAN_NDAT2_ND49 FDCAN_NDAT2_ND49_Msk /*!<New Data flag of Rx Buffer 49 */
4810#define FDCAN_NDAT2_ND50_Pos (18U)
4811#define FDCAN_NDAT2_ND50_Msk (0x1UL << FDCAN_NDAT2_ND50_Pos) /*!< 0x00040000 */
4812#define FDCAN_NDAT2_ND50 FDCAN_NDAT2_ND50_Msk /*!<New Data flag of Rx Buffer 50 */
4813#define FDCAN_NDAT2_ND51_Pos (19U)
4814#define FDCAN_NDAT2_ND51_Msk (0x1UL << FDCAN_NDAT2_ND51_Pos) /*!< 0x00080000 */
4815#define FDCAN_NDAT2_ND51 FDCAN_NDAT2_ND51_Msk /*!<New Data flag of Rx Buffer 51 */
4816#define FDCAN_NDAT2_ND52_Pos (20U)
4817#define FDCAN_NDAT2_ND52_Msk (0x1UL << FDCAN_NDAT2_ND52_Pos) /*!< 0x00100000 */
4818#define FDCAN_NDAT2_ND52 FDCAN_NDAT2_ND52_Msk /*!<New Data flag of Rx Buffer 52 */
4819#define FDCAN_NDAT2_ND53_Pos (21U)
4820#define FDCAN_NDAT2_ND53_Msk (0x1UL << FDCAN_NDAT2_ND53_Pos) /*!< 0x00200000 */
4821#define FDCAN_NDAT2_ND53 FDCAN_NDAT2_ND53_Msk /*!<New Data flag of Rx Buffer 53 */
4822#define FDCAN_NDAT2_ND54_Pos (22U)
4823#define FDCAN_NDAT2_ND54_Msk (0x1UL << FDCAN_NDAT2_ND54_Pos) /*!< 0x00400000 */
4824#define FDCAN_NDAT2_ND54 FDCAN_NDAT2_ND54_Msk /*!<New Data flag of Rx Buffer 54 */
4825#define FDCAN_NDAT2_ND55_Pos (23U)
4826#define FDCAN_NDAT2_ND55_Msk (0x1UL << FDCAN_NDAT2_ND55_Pos) /*!< 0x00800000 */
4827#define FDCAN_NDAT2_ND55 FDCAN_NDAT2_ND55_Msk /*!<New Data flag of Rx Buffer 55 */
4828#define FDCAN_NDAT2_ND56_Pos (24U)
4829#define FDCAN_NDAT2_ND56_Msk (0x1UL << FDCAN_NDAT2_ND56_Pos) /*!< 0x01000000 */
4830#define FDCAN_NDAT2_ND56 FDCAN_NDAT2_ND56_Msk /*!<New Data flag of Rx Buffer 56 */
4831#define FDCAN_NDAT2_ND57_Pos (25U)
4832#define FDCAN_NDAT2_ND57_Msk (0x1UL << FDCAN_NDAT2_ND57_Pos) /*!< 0x02000000 */
4833#define FDCAN_NDAT2_ND57 FDCAN_NDAT2_ND57_Msk /*!<New Data flag of Rx Buffer 57 */
4834#define FDCAN_NDAT2_ND58_Pos (26U)
4835#define FDCAN_NDAT2_ND58_Msk (0x1UL << FDCAN_NDAT2_ND58_Pos) /*!< 0x04000000 */
4836#define FDCAN_NDAT2_ND58 FDCAN_NDAT2_ND58_Msk /*!<New Data flag of Rx Buffer 58 */
4837#define FDCAN_NDAT2_ND59_Pos (27U)
4838#define FDCAN_NDAT2_ND59_Msk (0x1UL << FDCAN_NDAT2_ND59_Pos) /*!< 0x08000000 */
4839#define FDCAN_NDAT2_ND59 FDCAN_NDAT2_ND59_Msk /*!<New Data flag of Rx Buffer 59 */
4840#define FDCAN_NDAT2_ND60_Pos (28U)
4841#define FDCAN_NDAT2_ND60_Msk (0x1UL << FDCAN_NDAT2_ND60_Pos) /*!< 0x10000000 */
4842#define FDCAN_NDAT2_ND60 FDCAN_NDAT2_ND60_Msk /*!<New Data flag of Rx Buffer 60 */
4843#define FDCAN_NDAT2_ND61_Pos (29U)
4844#define FDCAN_NDAT2_ND61_Msk (0x1UL << FDCAN_NDAT2_ND61_Pos) /*!< 0x20000000 */
4845#define FDCAN_NDAT2_ND61 FDCAN_NDAT2_ND61_Msk /*!<New Data flag of Rx Buffer 61 */
4846#define FDCAN_NDAT2_ND62_Pos (30U)
4847#define FDCAN_NDAT2_ND62_Msk (0x1UL << FDCAN_NDAT2_ND62_Pos) /*!< 0x40000000 */
4848#define FDCAN_NDAT2_ND62 FDCAN_NDAT2_ND62_Msk /*!<New Data flag of Rx Buffer 62 */
4849#define FDCAN_NDAT2_ND63_Pos (31U)
4850#define FDCAN_NDAT2_ND63_Msk (0x1UL << FDCAN_NDAT2_ND63_Pos) /*!< 0x80000000 */
4851#define FDCAN_NDAT2_ND63 FDCAN_NDAT2_ND63_Msk /*!<New Data flag of Rx Buffer 63 */
4852
4853/***************** Bit definition for FDCAN_RXF0C register ********************/
4854#define FDCAN_RXF0C_F0SA_Pos (2U)
4855#define FDCAN_RXF0C_F0SA_Msk (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos) /*!< 0x0000FFFC */
4856#define FDCAN_RXF0C_F0SA FDCAN_RXF0C_F0SA_Msk /*!<Rx FIFO 0 Start Address */
4857#define FDCAN_RXF0C_F0S_Pos (16U)
4858#define FDCAN_RXF0C_F0S_Msk (0x7FUL << FDCAN_RXF0C_F0S_Pos) /*!< 0x007F0000 */
4859#define FDCAN_RXF0C_F0S FDCAN_RXF0C_F0S_Msk /*!<Number of Rx FIFO 0 elements */
4860#define FDCAN_RXF0C_F0WM_Pos (24U)
4861#define FDCAN_RXF0C_F0WM_Msk (0x7FUL << FDCAN_RXF0C_F0WM_Pos) /*!< 0x7F000000 */
4862#define FDCAN_RXF0C_F0WM FDCAN_RXF0C_F0WM_Msk /*!<FIFO 0 Watermark */
4863#define FDCAN_RXF0C_F0OM_Pos (31U)
4864#define FDCAN_RXF0C_F0OM_Msk (0x1UL << FDCAN_RXF0C_F0OM_Pos) /*!< 0x80000000 */
4865#define FDCAN_RXF0C_F0OM FDCAN_RXF0C_F0OM_Msk /*!<FIFO 0 Operation Mode */
4866
4867/***************** Bit definition for FDCAN_RXF0S register ********************/
4868#define FDCAN_RXF0S_F0FL_Pos (0U)
4869#define FDCAN_RXF0S_F0FL_Msk (0x7FUL << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000007F */
4870#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */
4871#define FDCAN_RXF0S_F0GI_Pos (8U)
4872#define FDCAN_RXF0S_F0GI_Msk (0x3FUL << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00003F00 */
4873#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */
4874#define FDCAN_RXF0S_F0PI_Pos (16U)
4875#define FDCAN_RXF0S_F0PI_Msk (0x3FUL << FDCAN_RXF0S_F0PI_Pos) /*!< 0x003F0000 */
4876#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */
4877#define FDCAN_RXF0S_F0F_Pos (24U)
4878#define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */
4879#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */
4880#define FDCAN_RXF0S_RF0L_Pos (25U)
4881#define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */
4882#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
4883
4884/***************** Bit definition for FDCAN_RXF0A register ********************/
4885#define FDCAN_RXF0A_F0AI_Pos (0U)
4886#define FDCAN_RXF0A_F0AI_Msk (0x3FUL << FDCAN_RXF0A_F0AI_Pos) /*!< 0x0000003F */
4887#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */
4888
4889/***************** Bit definition for FDCAN_RXBC register ********************/
4890#define FDCAN_RXBC_RBSA_Pos (2U)
4891#define FDCAN_RXBC_RBSA_Msk (0x3FFFUL << FDCAN_RXBC_RBSA_Pos) /*!< 0x0000FFFC */
4892#define FDCAN_RXBC_RBSA FDCAN_RXBC_RBSA_Msk /*!<Rx Buffer Start Address */
4893
4894/***************** Bit definition for FDCAN_RXF1C register ********************/
4895#define FDCAN_RXF1C_F1SA_Pos (2U)
4896#define FDCAN_RXF1C_F1SA_Msk (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos) /*!< 0x0000FFFC */
4897#define FDCAN_RXF1C_F1SA FDCAN_RXF1C_F1SA_Msk /*!<Rx FIFO 1 Start Address */
4898#define FDCAN_RXF1C_F1S_Pos (16U)
4899#define FDCAN_RXF1C_F1S_Msk (0x7FUL << FDCAN_RXF1C_F1S_Pos) /*!< 0x007F0000 */
4900#define FDCAN_RXF1C_F1S FDCAN_RXF1C_F1S_Msk /*!<Number of Rx FIFO 1 elements */
4901#define FDCAN_RXF1C_F1WM_Pos (24U)
4902#define FDCAN_RXF1C_F1WM_Msk (0x7FUL << FDCAN_RXF1C_F1WM_Pos) /*!< 0x7F000000 */
4903#define FDCAN_RXF1C_F1WM FDCAN_RXF1C_F1WM_Msk /*!<Rx FIFO 1 Watermark */
4904#define FDCAN_RXF1C_F1OM_Pos (31U)
4905#define FDCAN_RXF1C_F1OM_Msk (0x1UL << FDCAN_RXF1C_F1OM_Pos) /*!< 0x80000000 */
4906#define FDCAN_RXF1C_F1OM FDCAN_RXF1C_F1OM_Msk /*!<FIFO 1 Operation Mode */
4907
4908/***************** Bit definition for FDCAN_RXF1S register ********************/
4909#define FDCAN_RXF1S_F1FL_Pos (0U)
4910#define FDCAN_RXF1S_F1FL_Msk (0x7FUL << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000007F */
4911#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */
4912#define FDCAN_RXF1S_F1GI_Pos (8U)
4913#define FDCAN_RXF1S_F1GI_Msk (0x3FUL << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00003F00 */
4914#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */
4915#define FDCAN_RXF1S_F1PI_Pos (16U)
4916#define FDCAN_RXF1S_F1PI_Msk (0x3FUL << FDCAN_RXF1S_F1PI_Pos) /*!< 0x003F0000 */
4917#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */
4918#define FDCAN_RXF1S_F1F_Pos (24U)
4919#define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */
4920#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */
4921#define FDCAN_RXF1S_RF1L_Pos (25U)
4922#define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */
4923#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
4924
4925/***************** Bit definition for FDCAN_RXF1A register ********************/
4926#define FDCAN_RXF1A_F1AI_Pos (0U)
4927#define FDCAN_RXF1A_F1AI_Msk (0x3FUL << FDCAN_RXF1A_F1AI_Pos) /*!< 0x0000003F */
4928#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */
4929
4930/***************** Bit definition for FDCAN_RXESC register ********************/
4931#define FDCAN_RXESC_F0DS_Pos (0U)
4932#define FDCAN_RXESC_F0DS_Msk (0x7UL << FDCAN_RXESC_F0DS_Pos) /*!< 0x00000007 */
4933#define FDCAN_RXESC_F0DS FDCAN_RXESC_F0DS_Msk /*!<Rx FIFO 1 Data Field Size */
4934#define FDCAN_RXESC_F1DS_Pos (4U)
4935#define FDCAN_RXESC_F1DS_Msk (0x7UL << FDCAN_RXESC_F1DS_Pos) /*!< 0x00000070 */
4936#define FDCAN_RXESC_F1DS FDCAN_RXESC_F1DS_Msk /*!<Rx FIFO 0 Data Field Size */
4937#define FDCAN_RXESC_RBDS_Pos (8U)
4938#define FDCAN_RXESC_RBDS_Msk (0x7UL << FDCAN_RXESC_RBDS_Pos) /*!< 0x00000700 */
4939#define FDCAN_RXESC_RBDS FDCAN_RXESC_RBDS_Msk /*!<Rx Buffer Data Field Size */
4940
4941/***************** Bit definition for FDCAN_TXBC register *********************/
4942#define FDCAN_TXBC_TBSA_Pos (2U)
4943#define FDCAN_TXBC_TBSA_Msk (0x3FFFUL << FDCAN_TXBC_TBSA_Pos) /*!< 0x0000FFFC */
4944#define FDCAN_TXBC_TBSA FDCAN_TXBC_TBSA_Msk /*!<Tx Buffers Start Address */
4945#define FDCAN_TXBC_NDTB_Pos (16U)
4946#define FDCAN_TXBC_NDTB_Msk (0x3FUL << FDCAN_TXBC_NDTB_Pos) /*!< 0x003F0000 */
4947#define FDCAN_TXBC_NDTB FDCAN_TXBC_NDTB_Msk /*!<Number of Dedicated Transmit Buffers */
4948#define FDCAN_TXBC_TFQS_Pos (24U)
4949#define FDCAN_TXBC_TFQS_Msk (0x3FUL << FDCAN_TXBC_TFQS_Pos) /*!< 0x3F000000 */
4950#define FDCAN_TXBC_TFQS FDCAN_TXBC_TFQS_Msk /*!<Transmit FIFO/Queue Size */
4951#define FDCAN_TXBC_TFQM_Pos (30U)
4952#define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) /*!< 0x40000000 */
4953#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */
4954
4955/***************** Bit definition for FDCAN_TXFQS register *********************/
4956#define FDCAN_TXFQS_TFFL_Pos (0U)
4957#define FDCAN_TXFQS_TFFL_Msk (0x3FUL << FDCAN_TXFQS_TFFL_Pos) /*!< 0x0000003F */
4958#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */
4959#define FDCAN_TXFQS_TFGI_Pos (8U)
4960#define FDCAN_TXFQS_TFGI_Msk (0x1FUL << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00001F00 */
4961#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */
4962#define FDCAN_TXFQS_TFQPI_Pos (16U)
4963#define FDCAN_TXFQS_TFQPI_Msk (0x1FUL << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x001F0000 */
4964#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */
4965#define FDCAN_TXFQS_TFQF_Pos (21U)
4966#define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */
4967#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */
4968
4969/***************** Bit definition for FDCAN_TXESC register *********************/
4970#define FDCAN_TXESC_TBDS_Pos (0U)
4971#define FDCAN_TXESC_TBDS_Msk (0x7UL << FDCAN_TXESC_TBDS_Pos) /*!< 0x00000007 */
4972#define FDCAN_TXESC_TBDS FDCAN_TXESC_TBDS_Msk /*!<Tx Buffer Data Field Size */
4973
4974/***************** Bit definition for FDCAN_TXBRP register *********************/
4975#define FDCAN_TXBRP_TRP_Pos (0U)
4976#define FDCAN_TXBRP_TRP_Msk (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos) /*!< 0xFFFFFFFF */
4977#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */
4978
4979/***************** Bit definition for FDCAN_TXBAR register *********************/
4980#define FDCAN_TXBAR_AR_Pos (0U)
4981#define FDCAN_TXBAR_AR_Msk (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos) /*!< 0xFFFFFFFF */
4982#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */
4983
4984/***************** Bit definition for FDCAN_TXBCR register *********************/
4985#define FDCAN_TXBCR_CR_Pos (0U)
4986#define FDCAN_TXBCR_CR_Msk (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos) /*!< 0xFFFFFFFF */
4987#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */
4988
4989/***************** Bit definition for FDCAN_TXBTO register *********************/
4990#define FDCAN_TXBTO_TO_Pos (0U)
4991#define FDCAN_TXBTO_TO_Msk (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos) /*!< 0xFFFFFFFF */
4992#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */
4993
4994/***************** Bit definition for FDCAN_TXBCF register *********************/
4995#define FDCAN_TXBCF_CF_Pos (0U)
4996#define FDCAN_TXBCF_CF_Msk (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos) /*!< 0xFFFFFFFF */
4997#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */
4998
4999/***************** Bit definition for FDCAN_TXBTIE register ********************/
5000#define FDCAN_TXBTIE_TIE_Pos (0U)
5001#define FDCAN_TXBTIE_TIE_Msk (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos) /*!< 0xFFFFFFFF */
5002#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */
5003
5004/***************** Bit definition for FDCAN_ TXBCIE register *******************/
5005#define FDCAN_TXBCIE_CFIE_Pos (0U)
5006#define FDCAN_TXBCIE_CFIE_Msk (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos) /*!< 0xFFFFFFFF */
5007#define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk /*!<Cancellation Finished Interrupt Enable */
5008
5009/***************** Bit definition for FDCAN_TXEFC register *********************/
5010#define FDCAN_TXEFC_EFSA_Pos (2U)
5011#define FDCAN_TXEFC_EFSA_Msk (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos) /*!< 0x0000FFFC */
5012#define FDCAN_TXEFC_EFSA FDCAN_TXEFC_EFSA_Msk /*!<Event FIFO Start Address */
5013#define FDCAN_TXEFC_EFS_Pos (16U)
5014#define FDCAN_TXEFC_EFS_Msk (0x3FUL << FDCAN_TXEFC_EFS_Pos) /*!< 0x003F0000 */
5015#define FDCAN_TXEFC_EFS FDCAN_TXEFC_EFS_Msk /*!<Event FIFO Size */
5016#define FDCAN_TXEFC_EFWM_Pos (24U)
5017#define FDCAN_TXEFC_EFWM_Msk (0x3FUL << FDCAN_TXEFC_EFWM_Pos) /*!< 0x3F000000 */
5018#define FDCAN_TXEFC_EFWM FDCAN_TXEFC_EFWM_Msk /*!<Event FIFO Watermark */
5019
5020/***************** Bit definition for FDCAN_TXEFS register *********************/
5021#define FDCAN_TXEFS_EFFL_Pos (0U)
5022#define FDCAN_TXEFS_EFFL_Msk (0x3FUL << FDCAN_TXEFS_EFFL_Pos) /*!< 0x0000003F */
5023#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */
5024#define FDCAN_TXEFS_EFGI_Pos (8U)
5025#define FDCAN_TXEFS_EFGI_Msk (0x1FUL << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00001F00 */
5026#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */
5027#define FDCAN_TXEFS_EFPI_Pos (16U)
5028#define FDCAN_TXEFS_EFPI_Msk (0x1FUL << FDCAN_TXEFS_EFPI_Pos) /*!< 0x001F0000 */
5029#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */
5030#define FDCAN_TXEFS_EFF_Pos (24U)
5031#define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */
5032#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */
5033#define FDCAN_TXEFS_TEFL_Pos (25U)
5034#define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */
5035#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */
5036
5037/***************** Bit definition for FDCAN_TXEFA register *********************/
5038#define FDCAN_TXEFA_EFAI_Pos (0U)
5039#define FDCAN_TXEFA_EFAI_Msk (0x1FUL << FDCAN_TXEFA_EFAI_Pos) /*!< 0x0000001F */
5040#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */
5041
5042/***************** Bit definition for FDCAN_TTTMC register *********************/
5043#define FDCAN_TTTMC_TMSA_Pos (2U)
5044#define FDCAN_TTTMC_TMSA_Msk (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos) /*!< 0x0000FFFC */
5045#define FDCAN_TTTMC_TMSA FDCAN_TTTMC_TMSA_Msk /*!<Trigger Memory Start Address */
5046#define FDCAN_TTTMC_TME_Pos (16U)
5047#define FDCAN_TTTMC_TME_Msk (0x7FUL << FDCAN_TTTMC_TME_Pos) /*!< 0x007F0000 */
5048#define FDCAN_TTTMC_TME FDCAN_TTTMC_TME_Msk /*!<Trigger Memory Elements */
5049
5050/***************** Bit definition for FDCAN_TTRMC register *********************/
5051#define FDCAN_TTRMC_RID_Pos (0U)
5052#define FDCAN_TTRMC_RID_Msk (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos) /*!< 0x1FFFFFFF */
5053#define FDCAN_TTRMC_RID FDCAN_TTRMC_RID_Msk /*!<Reference Identifier */
5054#define FDCAN_TTRMC_XTD_Pos (30U)
5055#define FDCAN_TTRMC_XTD_Msk (0x1UL << FDCAN_TTRMC_XTD_Pos) /*!< 0x40000000 */
5056#define FDCAN_TTRMC_XTD FDCAN_TTRMC_XTD_Msk /*!< Extended Identifier */
5057#define FDCAN_TTRMC_RMPS_Pos (31U)
5058#define FDCAN_TTRMC_RMPS_Msk (0x1UL << FDCAN_TTRMC_RMPS_Pos) /*!< 0x80000000 */
5059#define FDCAN_TTRMC_RMPS FDCAN_TTRMC_RMPS_Msk /*!<Reference Message Payload Select */
5060
5061/***************** Bit definition for FDCAN_TTOCF register *********************/
5062#define FDCAN_TTOCF_OM_Pos (0U)
5063#define FDCAN_TTOCF_OM_Msk (0x3UL << FDCAN_TTOCF_OM_Pos) /*!< 0x00000003 */
5064#define FDCAN_TTOCF_OM FDCAN_TTOCF_OM_Msk /*!<Operation Mode */
5065#define FDCAN_TTOCF_GEN_Pos (3U)
5066#define FDCAN_TTOCF_GEN_Msk (0x1UL << FDCAN_TTOCF_GEN_Pos) /*!< 0x00000008 */
5067#define FDCAN_TTOCF_GEN FDCAN_TTOCF_GEN_Msk /*!<Gap Enable */
5068#define FDCAN_TTOCF_TM_Pos (4U)
5069#define FDCAN_TTOCF_TM_Msk (0x1UL << FDCAN_TTOCF_TM_Pos) /*!< 0x00000010 */
5070#define FDCAN_TTOCF_TM FDCAN_TTOCF_TM_Msk /*!<Time Master */
5071#define FDCAN_TTOCF_LDSDL_Pos (5U)
5072#define FDCAN_TTOCF_LDSDL_Msk (0x7UL << FDCAN_TTOCF_LDSDL_Pos) /*!< 0x000000E0 */
5073#define FDCAN_TTOCF_LDSDL FDCAN_TTOCF_LDSDL_Msk /*!<LD of Synchronization Deviation Limit */
5074#define FDCAN_TTOCF_IRTO_Pos (8U)
5075#define FDCAN_TTOCF_IRTO_Msk (0x7FUL << FDCAN_TTOCF_IRTO_Pos) /*!< 0x00007F00 */
5076#define FDCAN_TTOCF_IRTO FDCAN_TTOCF_IRTO_Msk /*!<Initial Reference Trigger Offset */
5077#define FDCAN_TTOCF_EECS_Pos (15U)
5078#define FDCAN_TTOCF_EECS_Msk (0x1UL << FDCAN_TTOCF_EECS_Pos) /*!< 0x00008000 */
5079#define FDCAN_TTOCF_EECS FDCAN_TTOCF_EECS_Msk /*!<Enable External Clock Synchronization */
5080#define FDCAN_TTOCF_AWL_Pos (16U)
5081#define FDCAN_TTOCF_AWL_Msk (0xFFUL << FDCAN_TTOCF_AWL_Pos) /*!< 0x00FF0000 */
5082#define FDCAN_TTOCF_AWL FDCAN_TTOCF_AWL_Msk /*!<Application Watchdog Limit */
5083#define FDCAN_TTOCF_EGTF_Pos (24U)
5084#define FDCAN_TTOCF_EGTF_Msk (0x1UL << FDCAN_TTOCF_EGTF_Pos) /*!< 0x01000000 */
5085#define FDCAN_TTOCF_EGTF FDCAN_TTOCF_EGTF_Msk /*!<Enable Global Time Filtering */
5086#define FDCAN_TTOCF_ECC_Pos (25U)
5087#define FDCAN_TTOCF_ECC_Msk (0x1UL << FDCAN_TTOCF_ECC_Pos) /*!< 0x02000000 */
5088#define FDCAN_TTOCF_ECC FDCAN_TTOCF_ECC_Msk /*!<Enable Clock Calibration */
5089#define FDCAN_TTOCF_EVTP_Pos (26U)
5090#define FDCAN_TTOCF_EVTP_Msk (0x1UL << FDCAN_TTOCF_EVTP_Pos) /*!< 0x04000000 */
5091#define FDCAN_TTOCF_EVTP FDCAN_TTOCF_EVTP_Msk /*!<Event Trigger Polarity */
5092
5093/***************** Bit definition for FDCAN_TTMLM register *********************/
5094#define FDCAN_TTMLM_CCM_Pos (0U)
5095#define FDCAN_TTMLM_CCM_Msk (0x3FUL << FDCAN_TTMLM_CCM_Pos) /*!< 0x0000003F */
5096#define FDCAN_TTMLM_CCM FDCAN_TTMLM_CCM_Msk /*!<Cycle Count Max */
5097#define FDCAN_TTMLM_CSS_Pos (6U)
5098#define FDCAN_TTMLM_CSS_Msk (0x3UL << FDCAN_TTMLM_CSS_Pos) /*!< 0x000000C0 */
5099#define FDCAN_TTMLM_CSS FDCAN_TTMLM_CSS_Msk /*!<Cycle Start Synchronization */
5100#define FDCAN_TTMLM_TXEW_Pos (8U)
5101#define FDCAN_TTMLM_TXEW_Msk (0xFUL << FDCAN_TTMLM_TXEW_Pos) /*!< 0x00000F00 */
5102#define FDCAN_TTMLM_TXEW FDCAN_TTMLM_TXEW_Msk /*!<Tx Enable Window */
5103#define FDCAN_TTMLM_ENTT_Pos (16U)
5104#define FDCAN_TTMLM_ENTT_Msk (0xFFFUL << FDCAN_TTMLM_ENTT_Pos) /*!< 0x0FFF0000 */
5105#define FDCAN_TTMLM_ENTT FDCAN_TTMLM_ENTT_Msk /*!<Expected Number of Tx Triggers */
5106
5107/***************** Bit definition for FDCAN_TURCF register *********************/
5108#define FDCAN_TURCF_NCL_Pos (0U)
5109#define FDCAN_TURCF_NCL_Msk (0xFFFFUL << FDCAN_TURCF_NCL_Pos) /*!< 0x0000FFFF */
5110#define FDCAN_TURCF_NCL FDCAN_TURCF_NCL_Msk /*!<Numerator Configuration Low */
5111#define FDCAN_TURCF_DC_Pos (16U)
5112#define FDCAN_TURCF_DC_Msk (0x3FFFUL << FDCAN_TURCF_DC_Pos) /*!< 0x3FFF0000 */
5113#define FDCAN_TURCF_DC FDCAN_TURCF_DC_Msk /*!<Denominator Configuration */
5114#define FDCAN_TURCF_ELT_Pos (31U)
5115#define FDCAN_TURCF_ELT_Msk (0x1UL << FDCAN_TURCF_ELT_Pos) /*!< 0x80000000 */
5116#define FDCAN_TURCF_ELT FDCAN_TURCF_ELT_Msk /*!<Enable Local Time */
5117
5118/***************** Bit definition for FDCAN_TTOCN register ********************/
5119#define FDCAN_TTOCN_SGT_Pos (0U)
5120#define FDCAN_TTOCN_SGT_Msk (0x1UL << FDCAN_TTOCN_SGT_Pos) /*!< 0x00000001 */
5121#define FDCAN_TTOCN_SGT FDCAN_TTOCN_SGT_Msk /*!<Set Global time */
5122#define FDCAN_TTOCN_ECS_Pos (1U)
5123#define FDCAN_TTOCN_ECS_Msk (0x1UL << FDCAN_TTOCN_ECS_Pos) /*!< 0x00000002 */
5124#define FDCAN_TTOCN_ECS FDCAN_TTOCN_ECS_Msk /*!<External Clock Synchronization */
5125#define FDCAN_TTOCN_SWP_Pos (2U)
5126#define FDCAN_TTOCN_SWP_Msk (0x1UL << FDCAN_TTOCN_SWP_Pos) /*!< 0x00000004 */
5127#define FDCAN_TTOCN_SWP FDCAN_TTOCN_SWP_Msk /*!<Stop Watch Polarity */
5128#define FDCAN_TTOCN_SWS_Pos (3U)
5129#define FDCAN_TTOCN_SWS_Msk (0x3UL << FDCAN_TTOCN_SWS_Pos) /*!< 0x00000018 */
5130#define FDCAN_TTOCN_SWS FDCAN_TTOCN_SWS_Msk /*!<Stop Watch Source */
5131#define FDCAN_TTOCN_RTIE_Pos (5U)
5132#define FDCAN_TTOCN_RTIE_Msk (0x1UL << FDCAN_TTOCN_RTIE_Pos) /*!< 0x00000020 */
5133#define FDCAN_TTOCN_RTIE FDCAN_TTOCN_RTIE_Msk /*!<Register Time Mark Interrupt Pulse Enable */
5134#define FDCAN_TTOCN_TMC_Pos (6U)
5135#define FDCAN_TTOCN_TMC_Msk (0x3UL << FDCAN_TTOCN_TMC_Pos) /*!< 0x000000C0 */
5136#define FDCAN_TTOCN_TMC FDCAN_TTOCN_TMC_Msk /*!<Register Time Mark Compare */
5137#define FDCAN_TTOCN_TTIE_Pos (8U)
5138#define FDCAN_TTOCN_TTIE_Msk (0x1UL << FDCAN_TTOCN_TTIE_Pos) /*!< 0x00000100 */
5139#define FDCAN_TTOCN_TTIE FDCAN_TTOCN_TTIE_Msk /*!<Trigger Time Mark Interrupt Pulse Enable */
5140#define FDCAN_TTOCN_GCS_Pos (9U)
5141#define FDCAN_TTOCN_GCS_Msk (0x1UL << FDCAN_TTOCN_GCS_Pos) /*!< 0x00000200 */
5142#define FDCAN_TTOCN_GCS FDCAN_TTOCN_GCS_Msk /*!<Gap Control Select */
5143#define FDCAN_TTOCN_FGP_Pos (10U)
5144#define FDCAN_TTOCN_FGP_Msk (0x1UL << FDCAN_TTOCN_FGP_Pos) /*!< 0x00000400 */
5145#define FDCAN_TTOCN_FGP FDCAN_TTOCN_FGP_Msk /*!<Finish Gap */
5146#define FDCAN_TTOCN_TMG_Pos (11U)
5147#define FDCAN_TTOCN_TMG_Msk (0x1UL << FDCAN_TTOCN_TMG_Pos) /*!< 0x00000800 */
5148#define FDCAN_TTOCN_TMG FDCAN_TTOCN_TMG_Msk /*!<Time Mark Gap */
5149#define FDCAN_TTOCN_NIG_Pos (12U)
5150#define FDCAN_TTOCN_NIG_Msk (0x1UL << FDCAN_TTOCN_NIG_Pos) /*!< 0x00001000 */
5151#define FDCAN_TTOCN_NIG FDCAN_TTOCN_NIG_Msk /*!<Next is Gap */
5152#define FDCAN_TTOCN_ESCN_Pos (13U)
5153#define FDCAN_TTOCN_ESCN_Msk (0x1UL << FDCAN_TTOCN_ESCN_Pos) /*!< 0x00002000 */
5154#define FDCAN_TTOCN_ESCN FDCAN_TTOCN_ESCN_Msk /*!<External Synchronization Control */
5155#define FDCAN_TTOCN_LCKC_Pos (15U)
5156#define FDCAN_TTOCN_LCKC_Msk (0x1UL << FDCAN_TTOCN_LCKC_Pos) /*!< 0x00008000 */
5157#define FDCAN_TTOCN_LCKC FDCAN_TTOCN_LCKC_Msk /*!<TT Operation Control Register Locked */
5158
5159/***************** Bit definition for FDCAN_TTGTP register ********************/
5160#define FDCAN_TTGTP_TP_Pos (0U)
5161#define FDCAN_TTGTP_TP_Msk (0xFFFFUL << FDCAN_TTGTP_TP_Pos) /*!< 0x0000FFFF */
5162#define FDCAN_TTGTP_TP FDCAN_TTGTP_TP_Msk /*!<Time Preset */
5163#define FDCAN_TTGTP_CTP_Pos (16U)
5164#define FDCAN_TTGTP_CTP_Msk (0xFFFFUL << FDCAN_TTGTP_CTP_Pos) /*!< 0xFFFF0000 */
5165#define FDCAN_TTGTP_CTP FDCAN_TTGTP_CTP_Msk /*!<Cycle Time Target Phase */
5166
5167/***************** Bit definition for FDCAN_TTTMK register ********************/
5168#define FDCAN_TTTMK_TM_Pos (0U)
5169#define FDCAN_TTTMK_TM_Msk (0xFFFFUL << FDCAN_TTTMK_TM_Pos) /*!< 0x0000FFFF */
5170#define FDCAN_TTTMK_TM FDCAN_TTTMK_TM_Msk /*!<Time Mark */
5171#define FDCAN_TTTMK_TICC_Pos (16U)
5172#define FDCAN_TTTMK_TICC_Msk (0x7FUL << FDCAN_TTTMK_TICC_Pos) /*!< 0x007F0000 */
5173#define FDCAN_TTTMK_TICC FDCAN_TTTMK_TICC_Msk /*!<Time Mark Cycle Code */
5174#define FDCAN_TTTMK_LCKM_Pos (31U)
5175#define FDCAN_TTTMK_LCKM_Msk (0x1UL << FDCAN_TTTMK_LCKM_Pos) /*!< 0x80000000 */
5176#define FDCAN_TTTMK_LCKM FDCAN_TTTMK_LCKM_Msk /*!<TT Time Mark Register Locked */
5177
5178/***************** Bit definition for FDCAN_TTIR register ********************/
5179#define FDCAN_TTIR_SBC_Pos (0U)
5180#define FDCAN_TTIR_SBC_Msk (0x1UL << FDCAN_TTIR_SBC_Pos) /*!< 0x00000001 */
5181#define FDCAN_TTIR_SBC FDCAN_TTIR_SBC_Msk /*!<Start of Basic Cycle */
5182#define FDCAN_TTIR_SMC_Pos (1U)
5183#define FDCAN_TTIR_SMC_Msk (0x1UL << FDCAN_TTIR_SMC_Pos) /*!< 0x00000002 */
5184#define FDCAN_TTIR_SMC FDCAN_TTIR_SMC_Msk /*!<Start of Matrix Cycle */
5185#define FDCAN_TTIR_CSM_Pos (2U)
5186#define FDCAN_TTIR_CSM_Msk (0x1UL << FDCAN_TTIR_CSM_Pos) /*!< 0x00000004 */
5187#define FDCAN_TTIR_CSM FDCAN_TTIR_CSM_Msk /*!<Change of Synchronization Mode */
5188#define FDCAN_TTIR_SOG_Pos (3U)
5189#define FDCAN_TTIR_SOG_Msk (0x1UL << FDCAN_TTIR_SOG_Pos) /*!< 0x00000008 */
5190#define FDCAN_TTIR_SOG FDCAN_TTIR_SOG_Msk /*!<Start of Gap */
5191#define FDCAN_TTIR_RTMI_Pos (4U)
5192#define FDCAN_TTIR_RTMI_Msk (0x1UL << FDCAN_TTIR_RTMI_Pos) /*!< 0x00000010 */
5193#define FDCAN_TTIR_RTMI FDCAN_TTIR_RTMI_Msk /*!<Register Time Mark Interrupt */
5194#define FDCAN_TTIR_TTMI_Pos (5U)
5195#define FDCAN_TTIR_TTMI_Msk (0x1UL << FDCAN_TTIR_TTMI_Pos) /*!< 0x00000020 */
5196#define FDCAN_TTIR_TTMI FDCAN_TTIR_TTMI_Msk /*!<Trigger Time Mark Event Internal */
5197#define FDCAN_TTIR_SWE_Pos (6U)
5198#define FDCAN_TTIR_SWE_Msk (0x1UL << FDCAN_TTIR_SWE_Pos) /*!< 0x00000040 */
5199#define FDCAN_TTIR_SWE FDCAN_TTIR_SWE_Msk /*!<Stop Watch Event */
5200#define FDCAN_TTIR_GTW_Pos (7U)
5201#define FDCAN_TTIR_GTW_Msk (0x1UL << FDCAN_TTIR_GTW_Pos) /*!< 0x00000080 */
5202#define FDCAN_TTIR_GTW FDCAN_TTIR_GTW_Msk /*!<Global Time Wrap */
5203#define FDCAN_TTIR_GTD_Pos (8U)
5204#define FDCAN_TTIR_GTD_Msk (0x1UL << FDCAN_TTIR_GTD_Pos) /*!< 0x00000100 */
5205#define FDCAN_TTIR_GTD FDCAN_TTIR_GTD_Msk /*!<Global Time Discontinuity */
5206#define FDCAN_TTIR_GTE_Pos (9U)
5207#define FDCAN_TTIR_GTE_Msk (0x1UL << FDCAN_TTIR_GTE_Pos) /*!< 0x00000200 */
5208#define FDCAN_TTIR_GTE FDCAN_TTIR_GTE_Msk /*!<Global Time Error */
5209#define FDCAN_TTIR_TXU_Pos (10U)
5210#define FDCAN_TTIR_TXU_Msk (0x1UL << FDCAN_TTIR_TXU_Pos) /*!< 0x00000400 */
5211#define FDCAN_TTIR_TXU FDCAN_TTIR_TXU_Msk /*!<Tx Count Underflow */
5212#define FDCAN_TTIR_TXO_Pos (11U)
5213#define FDCAN_TTIR_TXO_Msk (0x1UL << FDCAN_TTIR_TXO_Pos) /*!< 0x00000800 */
5214#define FDCAN_TTIR_TXO FDCAN_TTIR_TXO_Msk /*!<Tx Count Overflow */
5215#define FDCAN_TTIR_SE1_Pos (12U)
5216#define FDCAN_TTIR_SE1_Msk (0x1UL << FDCAN_TTIR_SE1_Pos) /*!< 0x00001000 */
5217#define FDCAN_TTIR_SE1 FDCAN_TTIR_SE1_Msk /*!<Scheduling Error 1 */
5218#define FDCAN_TTIR_SE2_Pos (13U)
5219#define FDCAN_TTIR_SE2_Msk (0x1UL << FDCAN_TTIR_SE2_Pos) /*!< 0x00002000 */
5220#define FDCAN_TTIR_SE2 FDCAN_TTIR_SE2_Msk /*!<Scheduling Error 2 */
5221#define FDCAN_TTIR_ELC_Pos (14U)
5222#define FDCAN_TTIR_ELC_Msk (0x1UL << FDCAN_TTIR_ELC_Pos) /*!< 0x00004000 */
5223#define FDCAN_TTIR_ELC FDCAN_TTIR_ELC_Msk /*!<Error Level Changed */
5224#define FDCAN_TTIR_IWT_Pos (15U)
5225#define FDCAN_TTIR_IWT_Msk (0x1UL << FDCAN_TTIR_IWT_Pos) /*!< 0x00008000 */
5226#define FDCAN_TTIR_IWT FDCAN_TTIR_IWT_Msk /*!<Initialization Watch Trigger */
5227#define FDCAN_TTIR_WT_Pos (16U)
5228#define FDCAN_TTIR_WT_Msk (0x1UL << FDCAN_TTIR_WT_Pos) /*!< 0x00010000 */
5229#define FDCAN_TTIR_WT FDCAN_TTIR_WT_Msk /*!<Watch Trigger */
5230#define FDCAN_TTIR_AW_Pos (17U)
5231#define FDCAN_TTIR_AW_Msk (0x1UL << FDCAN_TTIR_AW_Pos) /*!< 0x00020000 */
5232#define FDCAN_TTIR_AW FDCAN_TTIR_AW_Msk /*!<Application Watchdog */
5233#define FDCAN_TTIR_CER_Pos (18U)
5234#define FDCAN_TTIR_CER_Msk (0x1UL << FDCAN_TTIR_CER_Pos) /*!< 0x00040000 */
5235#define FDCAN_TTIR_CER FDCAN_TTIR_CER_Msk /*!<Configuration Error */
5236
5237/***************** Bit definition for FDCAN_TTIE register ********************/
5238#define FDCAN_TTIE_SBCE_Pos (0U)
5239#define FDCAN_TTIE_SBCE_Msk (0x1UL << FDCAN_TTIE_SBCE_Pos) /*!< 0x00000001 */
5240#define FDCAN_TTIE_SBCE FDCAN_TTIE_SBCE_Msk /*!<Start of Basic Cycle Interrupt Enable */
5241#define FDCAN_TTIE_SMCE_Pos (1U)
5242#define FDCAN_TTIE_SMCE_Msk (0x1UL << FDCAN_TTIE_SMCE_Pos) /*!< 0x00000002 */
5243#define FDCAN_TTIE_SMCE FDCAN_TTIE_SMCE_Msk /*!<Start of Matrix Cycle Interrupt Enable */
5244#define FDCAN_TTIE_CSME_Pos (2U)
5245#define FDCAN_TTIE_CSME_Msk (0x1UL << FDCAN_TTIE_CSME_Pos) /*!< 0x00000004 */
5246#define FDCAN_TTIE_CSME FDCAN_TTIE_CSME_Msk /*!<Change of Synchronization Mode Interrupt Enable */
5247#define FDCAN_TTIE_SOGE_Pos (3U)
5248#define FDCAN_TTIE_SOGE_Msk (0x1UL << FDCAN_TTIE_SOGE_Pos) /*!< 0x00000008 */
5249#define FDCAN_TTIE_SOGE FDCAN_TTIE_SOGE_Msk /*!<Start of Gap Interrupt Enable */
5250#define FDCAN_TTIE_RTMIE_Pos (4U)
5251#define FDCAN_TTIE_RTMIE_Msk (0x1UL << FDCAN_TTIE_RTMIE_Pos) /*!< 0x00000010 */
5252#define FDCAN_TTIE_RTMIE FDCAN_TTIE_RTMIE_Msk /*!<Register Time Mark Interrupt Interrupt Enable */
5253#define FDCAN_TTIE_TTMIE_Pos (5U)
5254#define FDCAN_TTIE_TTMIE_Msk (0x1UL << FDCAN_TTIE_TTMIE_Pos) /*!< 0x00000020 */
5255#define FDCAN_TTIE_TTMIE FDCAN_TTIE_TTMIE_Msk /*!<Trigger Time Mark Event Internal Interrupt Enable */
5256#define FDCAN_TTIE_SWEE_Pos (6U)
5257#define FDCAN_TTIE_SWEE_Msk (0x1UL << FDCAN_TTIE_SWEE_Pos) /*!< 0x00000040 */
5258#define FDCAN_TTIE_SWEE FDCAN_TTIE_SWEE_Msk /*!<Stop Watch Event Interrupt Enable */
5259#define FDCAN_TTIE_GTWE_Pos (7U)
5260#define FDCAN_TTIE_GTWE_Msk (0x1UL << FDCAN_TTIE_GTWE_Pos) /*!< 0x00000080 */
5261#define FDCAN_TTIE_GTWE FDCAN_TTIE_GTWE_Msk /*!<Global Time Wrap Interrupt Enable */
5262#define FDCAN_TTIE_GTDE_Pos (8U)
5263#define FDCAN_TTIE_GTDE_Msk (0x1UL << FDCAN_TTIE_GTDE_Pos) /*!< 0x00000100 */
5264#define FDCAN_TTIE_GTDE FDCAN_TTIE_GTDE_Msk /*!<Global Time Discontinuity Interrupt Enable */
5265#define FDCAN_TTIE_GTEE_Pos (9U)
5266#define FDCAN_TTIE_GTEE_Msk (0x1UL << FDCAN_TTIE_GTEE_Pos) /*!< 0x00000200 */
5267#define FDCAN_TTIE_GTEE FDCAN_TTIE_GTEE_Msk /*!<Global Time Error Interrupt Enable */
5268#define FDCAN_TTIE_TXUE_Pos (10U)
5269#define FDCAN_TTIE_TXUE_Msk (0x1UL << FDCAN_TTIE_TXUE_Pos) /*!< 0x00000400 */
5270#define FDCAN_TTIE_TXUE FDCAN_TTIE_TXUE_Msk /*!<Tx Count Underflow Interrupt Enable */
5271#define FDCAN_TTIE_TXOE_Pos (11U)
5272#define FDCAN_TTIE_TXOE_Msk (0x1UL << FDCAN_TTIE_TXOE_Pos) /*!< 0x00000800 */
5273#define FDCAN_TTIE_TXOE FDCAN_TTIE_TXOE_Msk /*!<Tx Count Overflow Interrupt Enable */
5274#define FDCAN_TTIE_SE1E_Pos (12U)
5275#define FDCAN_TTIE_SE1E_Msk (0x1UL << FDCAN_TTIE_SE1E_Pos) /*!< 0x00001000 */
5276#define FDCAN_TTIE_SE1E FDCAN_TTIE_SE1E_Msk /*!<Scheduling Error 1 Interrupt Enable */
5277#define FDCAN_TTIE_SE2E_Pos (13U)
5278#define FDCAN_TTIE_SE2E_Msk (0x1UL << FDCAN_TTIE_SE2E_Pos) /*!< 0x00002000 */
5279#define FDCAN_TTIE_SE2E FDCAN_TTIE_SE2E_Msk /*!<Scheduling Error 2 Interrupt Enable */
5280#define FDCAN_TTIE_ELCE_Pos (14U)
5281#define FDCAN_TTIE_ELCE_Msk (0x1UL << FDCAN_TTIE_ELCE_Pos) /*!< 0x00004000 */
5282#define FDCAN_TTIE_ELCE FDCAN_TTIE_ELCE_Msk /*!<Error Level Changed Interrupt Enable */
5283#define FDCAN_TTIE_IWTE_Pos (15U)
5284#define FDCAN_TTIE_IWTE_Msk (0x1UL << FDCAN_TTIE_IWTE_Pos) /*!< 0x00008000 */
5285#define FDCAN_TTIE_IWTE FDCAN_TTIE_IWTE_Msk /*!<Initialization Watch Trigger Interrupt Enable */
5286#define FDCAN_TTIE_WTE_Pos (16U)
5287#define FDCAN_TTIE_WTE_Msk (0x1UL << FDCAN_TTIE_WTE_Pos) /*!< 0x00010000 */
5288#define FDCAN_TTIE_WTE FDCAN_TTIE_WTE_Msk /*!<Watch Trigger Interrupt Enable */
5289#define FDCAN_TTIE_AWE_Pos (17U)
5290#define FDCAN_TTIE_AWE_Msk (0x1UL << FDCAN_TTIE_AWE_Pos) /*!< 0x00020000 */
5291#define FDCAN_TTIE_AWE FDCAN_TTIE_AWE_Msk /*!<Application Watchdog Interrupt Enable */
5292#define FDCAN_TTIE_CERE_Pos (18U)
5293#define FDCAN_TTIE_CERE_Msk (0x1UL << FDCAN_TTIE_CERE_Pos) /*!< 0x00040000 */
5294#define FDCAN_TTIE_CERE FDCAN_TTIE_CERE_Msk /*!<Configuration Error Interrupt Enable */
5295
5296/***************** Bit definition for FDCAN_TTILS register ********************/
5297#define FDCAN_TTILS_SBCS_Pos (0U)
5298#define FDCAN_TTILS_SBCS_Msk (0x1UL << FDCAN_TTILS_SBCS_Pos) /*!< 0x00000001 */
5299#define FDCAN_TTILS_SBCS FDCAN_TTILS_SBCS_Msk /*!<Start of Basic Cycle Interrupt Line */
5300#define FDCAN_TTILS_SMCS_Pos (1U)
5301#define FDCAN_TTILS_SMCS_Msk (0x1UL << FDCAN_TTILS_SMCS_Pos) /*!< 0x00000002 */
5302#define FDCAN_TTILS_SMCS FDCAN_TTILS_SMCS_Msk /*!<Start of Matrix Cycle Interrupt Line */
5303#define FDCAN_TTILS_CSMS_Pos (2U)
5304#define FDCAN_TTILS_CSMS_Msk (0x1UL << FDCAN_TTILS_CSMS_Pos) /*!< 0x00000004 */
5305#define FDCAN_TTILS_CSMS FDCAN_TTILS_CSMS_Msk /*!<Change of Synchronization Mode Interrupt Line */
5306#define FDCAN_TTILS_SOGS_Pos (3U)
5307#define FDCAN_TTILS_SOGS_Msk (0x1UL << FDCAN_TTILS_SOGS_Pos) /*!< 0x00000008 */
5308#define FDCAN_TTILS_SOGS FDCAN_TTILS_SOGS_Msk /*!<Start of Gap Interrupt Line */
5309#define FDCAN_TTILS_RTMIS_Pos (4U)
5310#define FDCAN_TTILS_RTMIS_Msk (0x1UL << FDCAN_TTILS_RTMIS_Pos) /*!< 0x00000010 */
5311#define FDCAN_TTILS_RTMIS FDCAN_TTILS_RTMIS_Msk /*!<Register Time Mark Interrupt Interrupt Line */
5312#define FDCAN_TTILS_TTMIS_Pos (5U)
5313#define FDCAN_TTILS_TTMIS_Msk (0x1UL << FDCAN_TTILS_TTMIS_Pos) /*!< 0x00000020 */
5314#define FDCAN_TTILS_TTMIS FDCAN_TTILS_TTMIS_Msk /*!<Trigger Time Mark Event Internal Interrupt Line */
5315#define FDCAN_TTILS_SWES_Pos (6U)
5316#define FDCAN_TTILS_SWES_Msk (0x1UL << FDCAN_TTILS_SWES_Pos) /*!< 0x00000040 */
5317#define FDCAN_TTILS_SWES FDCAN_TTILS_SWES_Msk /*!<Stop Watch Event Interrupt Line */
5318#define FDCAN_TTILS_GTWS_Pos (7U)
5319#define FDCAN_TTILS_GTWS_Msk (0x1UL << FDCAN_TTILS_GTWS_Pos) /*!< 0x00000080 */
5320#define FDCAN_TTILS_GTWS FDCAN_TTILS_GTWS_Msk /*!<Global Time Wrap Interrupt Line */
5321#define FDCAN_TTILS_GTDS_Pos (8U)
5322#define FDCAN_TTILS_GTDS_Msk (0x1UL << FDCAN_TTILS_GTDS_Pos) /*!< 0x00000100 */
5323#define FDCAN_TTILS_GTDS FDCAN_TTILS_GTDS_Msk /*!<Global Time Discontinuity Interrupt Line */
5324#define FDCAN_TTILS_GTES_Pos (9U)
5325#define FDCAN_TTILS_GTES_Msk (0x1UL << FDCAN_TTILS_GTES_Pos) /*!< 0x00000200 */
5326#define FDCAN_TTILS_GTES FDCAN_TTILS_GTES_Msk /*!<Global Time Error Interrupt Line */
5327#define FDCAN_TTILS_TXUS_Pos (10U)
5328#define FDCAN_TTILS_TXUS_Msk (0x1UL << FDCAN_TTILS_TXUS_Pos) /*!< 0x00000400 */
5329#define FDCAN_TTILS_TXUS FDCAN_TTILS_TXUS_Msk /*!<Tx Count Underflow Interrupt Line */
5330#define FDCAN_TTILS_TXOS_Pos (11U)
5331#define FDCAN_TTILS_TXOS_Msk (0x1UL << FDCAN_TTILS_TXOS_Pos) /*!< 0x00000800 */
5332#define FDCAN_TTILS_TXOS FDCAN_TTILS_TXOS_Msk /*!<Tx Count Overflow Interrupt Line */
5333#define FDCAN_TTILS_SE1S_Pos (12U)
5334#define FDCAN_TTILS_SE1S_Msk (0x1UL << FDCAN_TTILS_SE1S_Pos) /*!< 0x00001000 */
5335#define FDCAN_TTILS_SE1S FDCAN_TTILS_SE1S_Msk /*!<Scheduling Error 1 Interrupt Line */
5336#define FDCAN_TTILS_SE2S_Pos (13U)
5337#define FDCAN_TTILS_SE2S_Msk (0x1UL << FDCAN_TTILS_SE2S_Pos) /*!< 0x00002000 */
5338#define FDCAN_TTILS_SE2S FDCAN_TTILS_SE2S_Msk /*!<Scheduling Error 2 Interrupt Line */
5339#define FDCAN_TTILS_ELCS_Pos (14U)
5340#define FDCAN_TTILS_ELCS_Msk (0x1UL << FDCAN_TTILS_ELCS_Pos) /*!< 0x00004000 */
5341#define FDCAN_TTILS_ELCS FDCAN_TTILS_ELCS_Msk /*!<Error Level Changed Interrupt Line */
5342#define FDCAN_TTILS_IWTS_Pos (15U)
5343#define FDCAN_TTILS_IWTS_Msk (0x1UL << FDCAN_TTILS_IWTS_Pos) /*!< 0x00008000 */
5344#define FDCAN_TTILS_IWTS FDCAN_TTILS_IWTS_Msk /*!<Initialization Watch Trigger Interrupt Line */
5345#define FDCAN_TTILS_WTS_Pos (16U)
5346#define FDCAN_TTILS_WTS_Msk (0x1UL << FDCAN_TTILS_WTS_Pos) /*!< 0x00010000 */
5347#define FDCAN_TTILS_WTS FDCAN_TTILS_WTS_Msk /*!<Watch Trigger Interrupt Line */
5348#define FDCAN_TTILS_AWS_Pos (17U)
5349#define FDCAN_TTILS_AWS_Msk (0x1UL << FDCAN_TTILS_AWS_Pos) /*!< 0x00020000 */
5350#define FDCAN_TTILS_AWS FDCAN_TTILS_AWS_Msk /*!<Application Watchdog Interrupt Line */
5351#define FDCAN_TTILS_CERS_Pos (18U)
5352#define FDCAN_TTILS_CERS_Msk (0x1UL << FDCAN_TTILS_CERS_Pos) /*!< 0x00040000 */
5353#define FDCAN_TTILS_CERS FDCAN_TTILS_CERS_Msk /*!<Configuration Error Interrupt Line */
5354
5355/***************** Bit definition for FDCAN_TTOST register ********************/
5356#define FDCAN_TTOST_EL_Pos (0U)
5357#define FDCAN_TTOST_EL_Msk (0x3UL << FDCAN_TTOST_EL_Pos) /*!< 0x00000003 */
5358#define FDCAN_TTOST_EL FDCAN_TTOST_EL_Msk /*!<Error Level */
5359#define FDCAN_TTOST_MS_Pos (2U)
5360#define FDCAN_TTOST_MS_Msk (0x3UL << FDCAN_TTOST_MS_Pos) /*!< 0x0000000C */
5361#define FDCAN_TTOST_MS FDCAN_TTOST_MS_Msk /*!<Master State */
5362#define FDCAN_TTOST_SYS_Pos (4U)
5363#define FDCAN_TTOST_SYS_Msk (0x3UL << FDCAN_TTOST_SYS_Pos) /*!< 0x00000030 */
5364#define FDCAN_TTOST_SYS FDCAN_TTOST_SYS_Msk /*!<Synchronization State */
5365#define FDCAN_TTOST_QGTP_Pos (6U)
5366#define FDCAN_TTOST_QGTP_Msk (0x1UL << FDCAN_TTOST_QGTP_Pos) /*!< 0x00000040 */
5367#define FDCAN_TTOST_QGTP FDCAN_TTOST_QGTP_Msk /*!<Quality of Global Time Phase */
5368#define FDCAN_TTOST_QCS_Pos (7U)
5369#define FDCAN_TTOST_QCS_Msk (0x1UL << FDCAN_TTOST_QCS_Pos) /*!< 0x00000080 */
5370#define FDCAN_TTOST_QCS FDCAN_TTOST_QCS_Msk /*!<Quality of Clock Speed */
5371#define FDCAN_TTOST_RTO_Pos (8U)
5372#define FDCAN_TTOST_RTO_Msk (0xFFUL << FDCAN_TTOST_RTO_Pos) /*!< 0x0000FF00 */
5373#define FDCAN_TTOST_RTO FDCAN_TTOST_RTO_Msk /*!<Reference Trigger Offset */
5374#define FDCAN_TTOST_WGTD_Pos (22U)
5375#define FDCAN_TTOST_WGTD_Msk (0x1UL << FDCAN_TTOST_WGTD_Pos) /*!< 0x00400000 */
5376#define FDCAN_TTOST_WGTD FDCAN_TTOST_WGTD_Msk /*!<Wait for Global Time Discontinuity */
5377#define FDCAN_TTOST_GFI_Pos (23U)
5378#define FDCAN_TTOST_GFI_Msk (0x1UL << FDCAN_TTOST_GFI_Pos) /*!< 0x00800000 */
5379#define FDCAN_TTOST_GFI FDCAN_TTOST_GFI_Msk /*!<Gap Finished Indicator */
5380#define FDCAN_TTOST_TMP_Pos (24U)
5381#define FDCAN_TTOST_TMP_Msk (0x7UL << FDCAN_TTOST_TMP_Pos) /*!< 0x07000000 */
5382#define FDCAN_TTOST_TMP FDCAN_TTOST_TMP_Msk /*!<Time Master Priority */
5383#define FDCAN_TTOST_GSI_Pos (27U)
5384#define FDCAN_TTOST_GSI_Msk (0x1UL << FDCAN_TTOST_GSI_Pos) /*!< 0x08000000 */
5385#define FDCAN_TTOST_GSI FDCAN_TTOST_GSI_Msk /*!<Gap Started Indicator */
5386#define FDCAN_TTOST_WFE_Pos (28U)
5387#define FDCAN_TTOST_WFE_Msk (0x1UL << FDCAN_TTOST_WFE_Pos) /*!< 0x10000000 */
5388#define FDCAN_TTOST_WFE FDCAN_TTOST_WFE_Msk /*!<Wait for Event */
5389#define FDCAN_TTOST_AWE_Pos (29U)
5390#define FDCAN_TTOST_AWE_Msk (0x1UL << FDCAN_TTOST_AWE_Pos) /*!< 0x20000000 */
5391#define FDCAN_TTOST_AWE FDCAN_TTOST_AWE_Msk /*!<Application Watchdog Event */
5392#define FDCAN_TTOST_WECS_Pos (30U)
5393#define FDCAN_TTOST_WECS_Msk (0x1UL << FDCAN_TTOST_WECS_Pos) /*!< 0x40000000 */
5394#define FDCAN_TTOST_WECS FDCAN_TTOST_WECS_Msk /*!<Wait for External Clock Synchronization */
5395#define FDCAN_TTOST_SPL_Pos (31U)
5396#define FDCAN_TTOST_SPL_Msk (0x1UL << FDCAN_TTOST_SPL_Pos) /*!< 0x80000000 */
5397#define FDCAN_TTOST_SPL FDCAN_TTOST_SPL_Msk /*!<Schedule Phase Lock */
5398
5399/***************** Bit definition for FDCAN_TURNA register ********************/
5400#define FDCAN_TURNA_NAV_Pos (0U)
5401#define FDCAN_TURNA_NAV_Msk (0x3FFFFUL << FDCAN_TURNA_NAV_Pos) /*!< 0x0003FFFF */
5402#define FDCAN_TURNA_NAV FDCAN_TURNA_NAV_Msk /*!<Numerator Actual Value */
5403
5404/***************** Bit definition for FDCAN_TTLGT register ********************/
5405#define FDCAN_TTLGT_LT_Pos (0U)
5406#define FDCAN_TTLGT_LT_Msk (0xFFFFUL << FDCAN_TTLGT_LT_Pos) /*!< 0x0000FFFF */
5407#define FDCAN_TTLGT_LT FDCAN_TTLGT_LT_Msk /*!<Local Time */
5408#define FDCAN_TTLGT_GT_Pos (16U)
5409#define FDCAN_TTLGT_GT_Msk (0xFFFFUL << FDCAN_TTLGT_GT_Pos) /*!< 0xFFFF0000 */
5410#define FDCAN_TTLGT_GT FDCAN_TTLGT_GT_Msk /*!<Global Time */
5411
5412/***************** Bit definition for FDCAN_TTCTC register ********************/
5413#define FDCAN_TTCTC_CT_Pos (0U)
5414#define FDCAN_TTCTC_CT_Msk (0xFFFFUL << FDCAN_TTCTC_CT_Pos) /*!< 0x0000FFFF */
5415#define FDCAN_TTCTC_CT FDCAN_TTCTC_CT_Msk /*!<Cycle Time */
5416#define FDCAN_TTCTC_CC_Pos (16U)
5417#define FDCAN_TTCTC_CC_Msk (0x3FUL << FDCAN_TTCTC_CC_Pos) /*!< 0x003F0000 */
5418#define FDCAN_TTCTC_CC FDCAN_TTCTC_CC_Msk /*!<Cycle Count */
5419
5420/***************** Bit definition for FDCAN_TTCPT register ********************/
5421#define FDCAN_TTCPT_CCV_Pos (0U)
5422#define FDCAN_TTCPT_CCV_Msk (0x3FUL << FDCAN_TTCPT_CCV_Pos) /*!< 0x0000003F */
5423#define FDCAN_TTCPT_CCV FDCAN_TTCPT_CCV_Msk /*!<Cycle Count Value */
5424#define FDCAN_TTCPT_SWV_Pos (16U)
5425#define FDCAN_TTCPT_SWV_Msk (0xFFFFUL << FDCAN_TTCPT_SWV_Pos) /*!< 0xFFFF0000 */
5426#define FDCAN_TTCPT_SWV FDCAN_TTCPT_SWV_Msk /*!<Stop Watch Value */
5427
5428/***************** Bit definition for FDCAN_TTCSM register ********************/
5429#define FDCAN_TTCSM_CSM_Pos (0U)
5430#define FDCAN_TTCSM_CSM_Msk (0xFFFFUL << FDCAN_TTCSM_CSM_Pos) /*!< 0x0000FFFF */
5431#define FDCAN_TTCSM_CSM FDCAN_TTCSM_CSM_Msk /*!<Cycle Sync Mark */
5432
5433/***************** Bit definition for FDCAN_TTTS register *********************/
5434#define FDCAN_TTTS_SWTSEL_Pos (0U)
5435#define FDCAN_TTTS_SWTSEL_Msk (0x3UL << FDCAN_TTTS_SWTSEL_Pos) /*!< 0x00000003 */
5436#define FDCAN_TTTS_SWTSEL FDCAN_TTTS_SWTSEL_Msk /*!<Stop watch trigger input selection */
5437#define FDCAN_TTTS_EVTSEL_Pos (4U)
5438#define FDCAN_TTTS_EVTSEL_Msk (0x3UL << FDCAN_TTTS_EVTSEL_Pos) /*!< 0x00000030 */
5439#define FDCAN_TTTS_EVTSEL FDCAN_TTTS_EVTSEL_Msk /*!<Event trigger input selection */
5440
5441/********************************************************************************/
5442/* */
5443/* FDCANCCU (Clock Calibration unit) */
5444/* */
5445/********************************************************************************/
5446
5447/***************** Bit definition for FDCANCCU_CREL register ******************/
5448#define FDCANCCU_CREL_DAY_Pos (0U)
5449#define FDCANCCU_CREL_DAY_Msk (0xFFUL << FDCANCCU_CREL_DAY_Pos) /*!< 0x000000FF */
5450#define FDCANCCU_CREL_DAY FDCANCCU_CREL_DAY_Msk /*!<Timestamp Day */
5451#define FDCANCCU_CREL_MON_Pos (8U)
5452#define FDCANCCU_CREL_MON_Msk (0xFFUL << FDCANCCU_CREL_MON_Pos) /*!< 0x0000FF00 */
5453#define FDCANCCU_CREL_MON FDCANCCU_CREL_MON_Msk /*!<Timestamp Month */
5454#define FDCANCCU_CREL_YEAR_Pos (16U)
5455#define FDCANCCU_CREL_YEAR_Msk (0xFUL << FDCANCCU_CREL_YEAR_Pos) /*!< 0x000F0000 */
5456#define FDCANCCU_CREL_YEAR FDCANCCU_CREL_YEAR_Msk /*!<Timestamp Year */
5457#define FDCANCCU_CREL_SUBSTEP_Pos (20U)
5458#define FDCANCCU_CREL_SUBSTEP_Msk (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
5459#define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
5460#define FDCANCCU_CREL_STEP_Pos (24U)
5461#define FDCANCCU_CREL_STEP_Msk (0xFUL << FDCANCCU_CREL_STEP_Pos) /*!< 0x0F000000 */
5462#define FDCANCCU_CREL_STEP FDCANCCU_CREL_STEP_Msk /*!<Step of Core release */
5463#define FDCANCCU_CREL_REL_Pos (28U)
5464#define FDCANCCU_CREL_REL_Msk (0xFUL << FDCANCCU_CREL_REL_Pos) /*!< 0xF0000000 */
5465#define FDCANCCU_CREL_REL FDCANCCU_CREL_REL_Msk /*!<Core release */
5466
5467/***************** Bit definition for FDCANCCU_CCFG register ******************/
5468#define FDCANCCU_CCFG_TQBT_Pos (0U)
5469#define FDCANCCU_CCFG_TQBT_Msk (0x1FUL << FDCANCCU_CCFG_TQBT_Pos) /*!< 0x0000001F */
5470#define FDCANCCU_CCFG_TQBT FDCANCCU_CCFG_TQBT_Msk /*!<Time Quanta per Bit Time */
5471#define FDCANCCU_CCFG_BCC_Pos (6U)
5472#define FDCANCCU_CCFG_BCC_Msk (0x1UL << FDCANCCU_CCFG_BCC_Pos) /*!< 0x00000040 */
5473#define FDCANCCU_CCFG_BCC FDCANCCU_CCFG_BCC_Msk /*!<Bypass Clock Calibration */
5474#define FDCANCCU_CCFG_CFL_Pos (7U)
5475#define FDCANCCU_CCFG_CFL_Msk (0x1UL << FDCANCCU_CCFG_CFL_Pos) /*!< 0x00000080 */
5476#define FDCANCCU_CCFG_CFL FDCANCCU_CCFG_CFL_Msk /*!<Calibration Field Length */
5477#define FDCANCCU_CCFG_OCPM_Pos (8U)
5478#define FDCANCCU_CCFG_OCPM_Msk (0xFFUL << FDCANCCU_CCFG_OCPM_Pos) /*!< 0x0000FF00 */
5479#define FDCANCCU_CCFG_OCPM FDCANCCU_CCFG_OCPM_Msk /*!<Oscillator Clock Periods Minimum */
5480#define FDCANCCU_CCFG_CDIV_Pos (16U)
5481#define FDCANCCU_CCFG_CDIV_Msk (0xFUL << FDCANCCU_CCFG_CDIV_Pos) /*!< 0x000F0000 */
5482#define FDCANCCU_CCFG_CDIV FDCANCCU_CCFG_CDIV_Msk /*!<Clock Divider */
5483#define FDCANCCU_CCFG_SWR_Pos (31U)
5484#define FDCANCCU_CCFG_SWR_Msk (0x1UL << FDCANCCU_CCFG_SWR_Pos) /*!< 0x80000000 */
5485#define FDCANCCU_CCFG_SWR FDCANCCU_CCFG_SWR_Msk /*!<Software Reset */
5486
5487/***************** Bit definition for FDCANCCU_CSTAT register *****************/
5488#define FDCANCCU_CSTAT_OCPC_Pos (0U)
5489#define FDCANCCU_CSTAT_OCPC_Msk (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos) /*!< 0x0003FFFF */
5490#define FDCANCCU_CSTAT_OCPC FDCANCCU_CSTAT_OCPC_Msk /*!<Oscillator Clock Period Counter */
5491#define FDCANCCU_CSTAT_TQC_Pos (18U)
5492#define FDCANCCU_CSTAT_TQC_Msk (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos) /*!< 0x1FFC0000 */
5493#define FDCANCCU_CSTAT_TQC FDCANCCU_CSTAT_TQC_Msk /*!<Time Quanta Counter */
5494#define FDCANCCU_CSTAT_CALS_Pos (30U)
5495#define FDCANCCU_CSTAT_CALS_Msk (0x3UL << FDCANCCU_CSTAT_CALS_Pos) /*!< 0xC0000000 */
5496#define FDCANCCU_CSTAT_CALS FDCANCCU_CSTAT_CALS_Msk /*!<Calibration State */
5497
5498/****************** Bit definition for FDCANCCU_CWD register ******************/
5499#define FDCANCCU_CWD_WDC_Pos (0U)
5500#define FDCANCCU_CWD_WDC_Msk (0xFFFFUL << FDCANCCU_CWD_WDC_Pos) /*!< 0x0000FFFF */
5501#define FDCANCCU_CWD_WDC FDCANCCU_CWD_WDC_Msk /*!<Watchdog Configuration */
5502#define FDCANCCU_CWD_WDV_Pos (16U)
5503#define FDCANCCU_CWD_WDV_Msk (0xFFFFUL << FDCANCCU_CWD_WDV_Pos) /*!< 0xFFFF0000 */
5504#define FDCANCCU_CWD_WDV FDCANCCU_CWD_WDV_Msk /*!<Watchdog Value */
5505
5506/****************** Bit definition for FDCANCCU_IR register *******************/
5507#define FDCANCCU_IR_CWE_Pos (0U)
5508#define FDCANCCU_IR_CWE_Msk (0x1UL << FDCANCCU_IR_CWE_Pos) /*!< 0x00000001 */
5509#define FDCANCCU_IR_CWE FDCANCCU_IR_CWE_Msk /*!<Calibration Watchdog Event */
5510#define FDCANCCU_IR_CSC_Pos (1U)
5511#define FDCANCCU_IR_CSC_Msk (0x1UL << FDCANCCU_IR_CSC_Pos) /*!< 0x00000002 */
5512#define FDCANCCU_IR_CSC FDCANCCU_IR_CSC_Msk /*!<Calibration State Changed */
5513
5514/****************** Bit definition for FDCANCCU_IE register *******************/
5515#define FDCANCCU_IE_CWEE_Pos (0U)
5516#define FDCANCCU_IE_CWEE_Msk (0x1UL << FDCANCCU_IE_CWEE_Pos) /*!< 0x00000001 */
5517#define FDCANCCU_IE_CWEE FDCANCCU_IE_CWEE_Msk /*!<Calibration Watchdog Event Enable */
5518#define FDCANCCU_IE_CSCE_Pos (1U)
5519#define FDCANCCU_IE_CSCE_Msk (0x1UL << FDCANCCU_IE_CSCE_Pos) /*!< 0x00000002 */
5520#define FDCANCCU_IE_CSCE FDCANCCU_IE_CSCE_Msk /*!<Calibration State Changed Enable */
5521
5522/******************************************************************************/
5523/* */
5524/* HDMI-CEC (CEC) */
5525/* */
5526/******************************************************************************/
5527
5528/******************* Bit definition for CEC_CR register *********************/
5529#define CEC_CR_CECEN_Pos (0U)
5530#define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
5531#define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
5532#define CEC_CR_TXSOM_Pos (1U)
5533#define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
5534#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
5535#define CEC_CR_TXEOM_Pos (2U)
5536#define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
5537#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
5538
5539/******************* Bit definition for CEC_CFGR register *******************/
5540#define CEC_CFGR_SFT_Pos (0U)
5541#define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
5542#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
5543#define CEC_CFGR_RXTOL_Pos (3U)
5544#define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
5545#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
5546#define CEC_CFGR_BRESTP_Pos (4U)
5547#define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
5548#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
5549#define CEC_CFGR_BREGEN_Pos (5U)
5550#define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
5551#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
5552#define CEC_CFGR_LBPEGEN_Pos (6U)
5553#define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
5554#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error generation */
5555#define CEC_CFGR_SFTOPT_Pos (8U)
5556#define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
5557#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
5558#define CEC_CFGR_BRDNOGEN_Pos (7U)
5559#define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
5560#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No error generation */
5561#define CEC_CFGR_OAR_Pos (16U)
5562#define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
5563#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
5564#define CEC_CFGR_LSTN_Pos (31U)
5565#define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
5566#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
5567
5568/******************* Bit definition for CEC_TXDR register *******************/
5569#define CEC_TXDR_TXD_Pos (0U)
5570#define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
5571#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
5572
5573/******************* Bit definition for CEC_RXDR register *******************/
5574#define CEC_RXDR_RXD_Pos (0U)
5575#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */
5576#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */
5577
5578/******************* Bit definition for CEC_ISR register ********************/
5579#define CEC_ISR_RXBR_Pos (0U)
5580#define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
5581#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
5582#define CEC_ISR_RXEND_Pos (1U)
5583#define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
5584#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
5585#define CEC_ISR_RXOVR_Pos (2U)
5586#define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
5587#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
5588#define CEC_ISR_BRE_Pos (3U)
5589#define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
5590#define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
5591#define CEC_ISR_SBPE_Pos (4U)
5592#define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
5593#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
5594#define CEC_ISR_LBPE_Pos (5U)
5595#define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
5596#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
5597#define CEC_ISR_RXACKE_Pos (6U)
5598#define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
5599#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
5600#define CEC_ISR_ARBLST_Pos (7U)
5601#define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
5602#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
5603#define CEC_ISR_TXBR_Pos (8U)
5604#define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
5605#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
5606#define CEC_ISR_TXEND_Pos (9U)
5607#define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
5608#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
5609#define CEC_ISR_TXUDR_Pos (10U)
5610#define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
5611#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
5612#define CEC_ISR_TXERR_Pos (11U)
5613#define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
5614#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
5615#define CEC_ISR_TXACKE_Pos (12U)
5616#define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
5617#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
5618
5619/******************* Bit definition for CEC_IER register ********************/
5620#define CEC_IER_RXBRIE_Pos (0U)
5621#define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
5622#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
5623#define CEC_IER_RXENDIE_Pos (1U)
5624#define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
5625#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
5626#define CEC_IER_RXOVRIE_Pos (2U)
5627#define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
5628#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
5629#define CEC_IER_BREIE_Pos (3U)
5630#define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
5631#define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
5632#define CEC_IER_SBPEIE_Pos (4U)
5633#define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
5634#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable */
5635#define CEC_IER_LBPEIE_Pos (5U)
5636#define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
5637#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
5638#define CEC_IER_RXACKEIE_Pos (6U)
5639#define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
5640#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
5641#define CEC_IER_ARBLSTIE_Pos (7U)
5642#define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
5643#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
5644#define CEC_IER_TXBRIE_Pos (8U)
5645#define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
5646#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
5647#define CEC_IER_TXENDIE_Pos (9U)
5648#define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
5649#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
5650#define CEC_IER_TXUDRIE_Pos (10U)
5651#define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
5652#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
5653#define CEC_IER_TXERRIE_Pos (11U)
5654#define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
5655#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
5656#define CEC_IER_TXACKEIE_Pos (12U)
5657#define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
5658#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
5659
5660/******************************************************************************/
5661/* */
5662/* CRC calculation unit */
5663/* */
5664/******************************************************************************/
5665/******************* Bit definition for CRC_DR register *********************/
5666#define CRC_DR_DR_Pos (0U)
5667#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
5668#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
5669
5670/******************* Bit definition for CRC_IDR register ********************/
5671#define CRC_IDR_IDR_Pos (0U)
5672#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
5673#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
5674
5675/******************** Bit definition for CRC_CR register ********************/
5676#define CRC_CR_RESET_Pos (0U)
5677#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
5678#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
5679#define CRC_CR_POLYSIZE_Pos (3U)
5680#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
5681#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
5682#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
5683#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
5684#define CRC_CR_REV_IN_Pos (5U)
5685#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
5686#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
5687#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
5688#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
5689#define CRC_CR_REV_OUT_Pos (7U)
5690#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
5691#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
5692
5693/******************* Bit definition for CRC_INIT register *******************/
5694#define CRC_INIT_INIT_Pos (0U)
5695#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
5696#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
5697
5698/******************* Bit definition for CRC_POL register ********************/
5699#define CRC_POL_POL_Pos (0U)
5700#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
5701#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
5702
5703/******************************************************************************/
5704/* */
5705/* CRS Clock Recovery System */
5706/******************************************************************************/
5707
5708/******************* Bit definition for CRS_CR register *********************/
5709#define CRS_CR_SYNCOKIE_Pos (0U)
5710#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
5711#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
5712#define CRS_CR_SYNCWARNIE_Pos (1U)
5713#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
5714#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
5715#define CRS_CR_ERRIE_Pos (2U)
5716#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
5717#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
5718#define CRS_CR_ESYNCIE_Pos (3U)
5719#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
5720#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
5721#define CRS_CR_CEN_Pos (5U)
5722#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
5723#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
5724#define CRS_CR_AUTOTRIMEN_Pos (6U)
5725#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
5726#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
5727#define CRS_CR_SWSYNC_Pos (7U)
5728#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
5729#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
5730#define CRS_CR_TRIM_Pos (8U)
5731#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
5732#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
5733
5734/******************* Bit definition for CRS_CFGR register *********************/
5735#define CRS_CFGR_RELOAD_Pos (0U)
5736#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
5737#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
5738#define CRS_CFGR_FELIM_Pos (16U)
5739#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
5740#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
5741
5742#define CRS_CFGR_SYNCDIV_Pos (24U)
5743#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
5744#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
5745#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
5746#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
5747#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
5748
5749#define CRS_CFGR_SYNCSRC_Pos (28U)
5750#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
5751#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
5752#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
5753#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
5754
5755#define CRS_CFGR_SYNCPOL_Pos (31U)
5756#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
5757#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
5758
5759/******************* Bit definition for CRS_ISR register *********************/
5760#define CRS_ISR_SYNCOKF_Pos (0U)
5761#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
5762#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
5763#define CRS_ISR_SYNCWARNF_Pos (1U)
5764#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
5765#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
5766#define CRS_ISR_ERRF_Pos (2U)
5767#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
5768#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
5769#define CRS_ISR_ESYNCF_Pos (3U)
5770#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
5771#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
5772#define CRS_ISR_SYNCERR_Pos (8U)
5773#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
5774#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
5775#define CRS_ISR_SYNCMISS_Pos (9U)
5776#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
5777#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
5778#define CRS_ISR_TRIMOVF_Pos (10U)
5779#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
5780#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
5781#define CRS_ISR_FEDIR_Pos (15U)
5782#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
5783#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
5784#define CRS_ISR_FECAP_Pos (16U)
5785#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
5786#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
5787
5788/******************* Bit definition for CRS_ICR register *********************/
5789#define CRS_ICR_SYNCOKC_Pos (0U)
5790#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
5791#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
5792#define CRS_ICR_SYNCWARNC_Pos (1U)
5793#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
5794#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
5795#define CRS_ICR_ERRC_Pos (2U)
5796#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
5797#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
5798#define CRS_ICR_ESYNCC_Pos (3U)
5799#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
5800#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
5801
5802/******************************************************************************/
5803/* */
5804/* Digital to Analog Converter */
5805/* */
5806/******************************************************************************/
5807/******************** Bit definition for DAC_CR register ********************/
5808#define DAC_CR_EN1_Pos (0U)
5809#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
5810#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
5811#define DAC_CR_TEN1_Pos (1U)
5812#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
5813#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
5814
5815#define DAC_CR_TSEL1_Pos (2U)
5816#define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
5817#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5818#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
5819#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
5820#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
5821#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
5822
5823
5824#define DAC_CR_WAVE1_Pos (6U)
5825#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
5826#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5827#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
5828#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
5829
5830#define DAC_CR_MAMP1_Pos (8U)
5831#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
5832#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5833#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
5834#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
5835#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
5836#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
5837
5838#define DAC_CR_DMAEN1_Pos (12U)
5839#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
5840#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
5841#define DAC_CR_DMAUDRIE1_Pos (13U)
5842#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
5843#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
5844#define DAC_CR_CEN1_Pos (14U)
5845#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
5846#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
5847
5848#define DAC_CR_EN2_Pos (16U)
5849#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
5850#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
5851#define DAC_CR_TEN2_Pos (17U)
5852#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
5853#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
5854
5855#define DAC_CR_TSEL2_Pos (18U)
5856#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
5857#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5858#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
5859#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
5860#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
5861#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
5862
5863
5864#define DAC_CR_WAVE2_Pos (22U)
5865#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
5866#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5867#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
5868#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
5869
5870#define DAC_CR_MAMP2_Pos (24U)
5871#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
5872#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5873#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
5874#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
5875#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
5876#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
5877
5878#define DAC_CR_DMAEN2_Pos (28U)
5879#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
5880#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
5881#define DAC_CR_DMAUDRIE2_Pos (29U)
5882#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
5883#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
5884#define DAC_CR_CEN2_Pos (30U)
5885#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
5886#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
5887
5888/***************** Bit definition for DAC_SWTRIGR register ******************/
5889#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5890#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
5891#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
5892#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5893#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
5894#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
5895
5896/***************** Bit definition for DAC_DHR12R1 register ******************/
5897#define DAC_DHR12R1_DACC1DHR_Pos (0U)
5898#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
5899#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5900
5901/***************** Bit definition for DAC_DHR12L1 register ******************/
5902#define DAC_DHR12L1_DACC1DHR_Pos (4U)
5903#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5904#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5905
5906/****************** Bit definition for DAC_DHR8R1 register ******************/
5907#define DAC_DHR8R1_DACC1DHR_Pos (0U)
5908#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
5909#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5910
5911/***************** Bit definition for DAC_DHR12R2 register ******************/
5912#define DAC_DHR12R2_DACC2DHR_Pos (0U)
5913#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
5914#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5915
5916/***************** Bit definition for DAC_DHR12L2 register ******************/
5917#define DAC_DHR12L2_DACC2DHR_Pos (4U)
5918#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
5919#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5920
5921/****************** Bit definition for DAC_DHR8R2 register ******************/
5922#define DAC_DHR8R2_DACC2DHR_Pos (0U)
5923#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
5924#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5925
5926/***************** Bit definition for DAC_DHR12RD register ******************/
5927#define DAC_DHR12RD_DACC1DHR_Pos (0U)
5928#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
5929#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5930#define DAC_DHR12RD_DACC2DHR_Pos (16U)
5931#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
5932#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5933
5934/***************** Bit definition for DAC_DHR12LD register ******************/
5935#define DAC_DHR12LD_DACC1DHR_Pos (4U)
5936#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5937#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5938#define DAC_DHR12LD_DACC2DHR_Pos (20U)
5939#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
5940#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5941
5942/****************** Bit definition for DAC_DHR8RD register ******************/
5943#define DAC_DHR8RD_DACC1DHR_Pos (0U)
5944#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
5945#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5946#define DAC_DHR8RD_DACC2DHR_Pos (8U)
5947#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
5948#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5949
5950/******************* Bit definition for DAC_DOR1 register *******************/
5951#define DAC_DOR1_DACC1DOR_Pos (0U)
5952#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
5953#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
5954
5955/******************* Bit definition for DAC_DOR2 register *******************/
5956#define DAC_DOR2_DACC2DOR_Pos (0U)
5957#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
5958#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
5959
5960/******************** Bit definition for DAC_SR register ********************/
5961#define DAC_SR_DMAUDR1_Pos (13U)
5962#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
5963#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
5964#define DAC_SR_CAL_FLAG1_Pos (14U)
5965#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
5966#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
5967#define DAC_SR_BWST1_Pos (15U)
5968#define DAC_SR_BWST1_Msk (0x4001UL << DAC_SR_BWST1_Pos) /*!< 0x20008000 */
5969#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
5970
5971#define DAC_SR_DMAUDR2_Pos (29U)
5972#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
5973#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
5974#define DAC_SR_CAL_FLAG2_Pos (30U)
5975#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
5976#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
5977#define DAC_SR_BWST2_Pos (31U)
5978#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
5979#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
5980
5981/******************* Bit definition for DAC_CCR register ********************/
5982#define DAC_CCR_OTRIM1_Pos (0U)
5983#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
5984#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
5985#define DAC_CCR_OTRIM2_Pos (16U)
5986#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
5987#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
5988
5989/******************* Bit definition for DAC_MCR register *******************/
5990#define DAC_MCR_MODE1_Pos (0U)
5991#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
5992#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
5993#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
5994#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
5995#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
5996
5997#define DAC_MCR_MODE2_Pos (16U)
5998#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
5999#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
6000#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
6001#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
6002#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
6003
6004/****************** Bit definition for DAC_SHSR1 register ******************/
6005#define DAC_SHSR1_TSAMPLE1_Pos (0U)
6006#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
6007#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
6008
6009/****************** Bit definition for DAC_SHSR2 register ******************/
6010#define DAC_SHSR2_TSAMPLE2_Pos (0U)
6011#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
6012#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
6013
6014/****************** Bit definition for DAC_SHHR register ******************/
6015#define DAC_SHHR_THOLD1_Pos (0U)
6016#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
6017#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
6018#define DAC_SHHR_THOLD2_Pos (16U)
6019#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
6020#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
6021
6022/****************** Bit definition for DAC_SHRR register ******************/
6023#define DAC_SHRR_TREFRESH1_Pos (0U)
6024#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
6025#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
6026#define DAC_SHRR_TREFRESH2_Pos (16U)
6027#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
6028#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
6029
6030/******************************************************************************/
6031/* */
6032/* DCMI */
6033/* */
6034/******************************************************************************/
6035/******************** Bits definition for DCMI_CR register ******************/
6036#define DCMI_CR_CAPTURE_Pos (0U)
6037#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
6038#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
6039#define DCMI_CR_CM_Pos (1U)
6040#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */
6041#define DCMI_CR_CM DCMI_CR_CM_Msk
6042#define DCMI_CR_CROP_Pos (2U)
6043#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
6044#define DCMI_CR_CROP DCMI_CR_CROP_Msk
6045#define DCMI_CR_JPEG_Pos (3U)
6046#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
6047#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
6048#define DCMI_CR_ESS_Pos (4U)
6049#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
6050#define DCMI_CR_ESS DCMI_CR_ESS_Msk
6051#define DCMI_CR_PCKPOL_Pos (5U)
6052#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
6053#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
6054#define DCMI_CR_HSPOL_Pos (6U)
6055#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
6056#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
6057#define DCMI_CR_VSPOL_Pos (7U)
6058#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
6059#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
6060#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
6061#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
6062#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
6063#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
6064#define DCMI_CR_CRE_Pos (12U)
6065#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
6066#define DCMI_CR_CRE DCMI_CR_CRE_Msk
6067#define DCMI_CR_ENABLE_Pos (14U)
6068#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
6069#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
6070#define DCMI_CR_BSM_Pos (16U)
6071#define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) /*!< 0x00030000 */
6072#define DCMI_CR_BSM DCMI_CR_BSM_Msk
6073#define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos) /*!< 0x00010000 */
6074#define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos) /*!< 0x00020000 */
6075#define DCMI_CR_OEBS_Pos (18U)
6076#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
6077#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
6078#define DCMI_CR_LSM_Pos (19U)
6079#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
6080#define DCMI_CR_LSM DCMI_CR_LSM_Msk
6081#define DCMI_CR_OELS_Pos (20U)
6082#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
6083#define DCMI_CR_OELS DCMI_CR_OELS_Msk
6084
6085/******************** Bits definition for DCMI_SR register ******************/
6086#define DCMI_SR_HSYNC_Pos (0U)
6087#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
6088#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
6089#define DCMI_SR_VSYNC_Pos (1U)
6090#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
6091#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
6092#define DCMI_SR_FNE_Pos (2U)
6093#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
6094#define DCMI_SR_FNE DCMI_SR_FNE_Msk
6095
6096/******************** Bits definition for DCMI_RIS register ****************/
6097#define DCMI_RIS_FRAME_RIS_Pos (0U)
6098#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
6099#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
6100#define DCMI_RIS_OVR_RIS_Pos (1U)
6101#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
6102#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
6103#define DCMI_RIS_ERR_RIS_Pos (2U)
6104#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
6105#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
6106#define DCMI_RIS_VSYNC_RIS_Pos (3U)
6107#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
6108#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
6109#define DCMI_RIS_LINE_RIS_Pos (4U)
6110#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
6111#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
6112
6113/******************** Bits definition for DCMI_IER register *****************/
6114#define DCMI_IER_FRAME_IE_Pos (0U)
6115#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
6116#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
6117#define DCMI_IER_OVR_IE_Pos (1U)
6118#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
6119#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
6120#define DCMI_IER_ERR_IE_Pos (2U)
6121#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
6122#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
6123#define DCMI_IER_VSYNC_IE_Pos (3U)
6124#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
6125#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
6126#define DCMI_IER_LINE_IE_Pos (4U)
6127#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
6128#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
6129
6130
6131/******************** Bits definition for DCMI_MIS register *****************/
6132#define DCMI_MIS_FRAME_MIS_Pos (0U)
6133#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
6134#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
6135#define DCMI_MIS_OVR_MIS_Pos (1U)
6136#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
6137#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
6138#define DCMI_MIS_ERR_MIS_Pos (2U)
6139#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
6140#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
6141#define DCMI_MIS_VSYNC_MIS_Pos (3U)
6142#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
6143#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
6144#define DCMI_MIS_LINE_MIS_Pos (4U)
6145#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
6146#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
6147
6148
6149/******************** Bits definition for DCMI_ICR register *****************/
6150#define DCMI_ICR_FRAME_ISC_Pos (0U)
6151#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
6152#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
6153#define DCMI_ICR_OVR_ISC_Pos (1U)
6154#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
6155#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
6156#define DCMI_ICR_ERR_ISC_Pos (2U)
6157#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
6158#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
6159#define DCMI_ICR_VSYNC_ISC_Pos (3U)
6160#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
6161#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
6162#define DCMI_ICR_LINE_ISC_Pos (4U)
6163#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
6164#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
6165
6166
6167/******************** Bits definition for DCMI_ESCR register ******************/
6168#define DCMI_ESCR_FSC_Pos (0U)
6169#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
6170#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
6171#define DCMI_ESCR_LSC_Pos (8U)
6172#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
6173#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
6174#define DCMI_ESCR_LEC_Pos (16U)
6175#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
6176#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
6177#define DCMI_ESCR_FEC_Pos (24U)
6178#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
6179#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
6180
6181/******************** Bits definition for DCMI_ESUR register ******************/
6182#define DCMI_ESUR_FSU_Pos (0U)
6183#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
6184#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
6185#define DCMI_ESUR_LSU_Pos (8U)
6186#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
6187#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
6188#define DCMI_ESUR_LEU_Pos (16U)
6189#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
6190#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
6191#define DCMI_ESUR_FEU_Pos (24U)
6192#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
6193#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
6194
6195/******************** Bits definition for DCMI_CWSTRT register ******************/
6196#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
6197#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
6198#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
6199#define DCMI_CWSTRT_VST_Pos (16U)
6200#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
6201#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
6202
6203/******************** Bits definition for DCMI_CWSIZE register ******************/
6204#define DCMI_CWSIZE_CAPCNT_Pos (0U)
6205#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
6206#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
6207#define DCMI_CWSIZE_VLINE_Pos (16U)
6208#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
6209#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
6210
6211/******************** Bits definition for DCMI_DR register ******************/
6212#define DCMI_DR_BYTE0_Pos (0U)
6213#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
6214#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
6215#define DCMI_DR_BYTE1_Pos (8U)
6216#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
6217#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
6218#define DCMI_DR_BYTE2_Pos (16U)
6219#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
6220#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
6221#define DCMI_DR_BYTE3_Pos (24U)
6222#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
6223#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
6224
6225/******************************************************************************/
6226/* */
6227/* Digital Filter for Sigma Delta Modulators */
6228/* */
6229/******************************************************************************/
6230
6231/**************** DFSDM channel configuration registers ********************/
6232
6233/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
6234#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
6235#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
6236#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
6237#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
6238#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
6239#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
6240#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
6241#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
6242#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
6243#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
6244#define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
6245#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
6246#define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
6247#define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
6248#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
6249#define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
6250#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
6251#define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
6252#define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
6253#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
6254#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
6255#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
6256#define DFSDM_CHCFGR1_CHEN_Pos (7U)
6257#define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
6258#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
6259#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
6260#define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
6261#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
6262#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
6263#define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
6264#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
6265#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
6266#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
6267#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
6268#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
6269#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
6270#define DFSDM_CHCFGR1_SITP_Pos (0U)
6271#define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
6272#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
6273#define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
6274#define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
6275
6276/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
6277#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
6278#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
6279#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
6280#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
6281#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
6282#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
6283
6284/****************** Bit definition for DFSDM_CHAWSCDR register *****************/
6285#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
6286#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
6287#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
6288#define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
6289#define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
6290#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
6291#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
6292#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
6293#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
6294#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
6295#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
6296#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
6297#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
6298#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
6299
6300/**************** Bit definition for DFSDM_CHWDATR register *******************/
6301#define DFSDM_CHWDATR_WDATA_Pos (0U)
6302#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
6303#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
6304
6305/**************** Bit definition for DFSDM_CHDATINR register *****************/
6306#define DFSDM_CHDATINR_INDAT0_Pos (0U)
6307#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
6308#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
6309#define DFSDM_CHDATINR_INDAT1_Pos (16U)
6310#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
6311#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
6312
6313/************************ DFSDM module registers ****************************/
6314
6315/******************** Bit definition for DFSDM_FLTCR1 register *******************/
6316#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
6317#define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
6318#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
6319#define DFSDM_FLTCR1_FAST_Pos (29U)
6320#define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
6321#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
6322#define DFSDM_FLTCR1_RCH_Pos (24U)
6323#define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
6324#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
6325#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
6326#define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
6327#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
6328#define DFSDM_FLTCR1_RSYNC_Pos (19U)
6329#define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
6330#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
6331#define DFSDM_FLTCR1_RCONT_Pos (18U)
6332#define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
6333#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
6334#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
6335#define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
6336#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
6337#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
6338#define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
6339#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
6340#define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
6341#define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
6342#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
6343#define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001F00 */
6344#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
6345#define DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
6346#define DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
6347#define DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
6348#define DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000800 */
6349#define DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001000 */
6350
6351#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
6352#define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
6353#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
6354#define DFSDM_FLTCR1_JSCAN_Pos (4U)
6355#define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
6356#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
6357#define DFSDM_FLTCR1_JSYNC_Pos (3U)
6358#define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
6359#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
6360#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
6361#define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
6362#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
6363#define DFSDM_FLTCR1_DFEN_Pos (0U)
6364#define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
6365#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
6366
6367/******************** Bit definition for DFSDM_FLTCR2 register *******************/
6368#define DFSDM_FLTCR2_AWDCH_Pos (16U)
6369#define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
6370#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
6371#define DFSDM_FLTCR2_EXCH_Pos (8U)
6372#define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
6373#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
6374#define DFSDM_FLTCR2_CKABIE_Pos (6U)
6375#define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
6376#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
6377#define DFSDM_FLTCR2_SCDIE_Pos (5U)
6378#define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
6379#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
6380#define DFSDM_FLTCR2_AWDIE_Pos (4U)
6381#define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
6382#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
6383#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
6384#define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
6385#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
6386#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
6387#define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
6388#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
6389#define DFSDM_FLTCR2_REOCIE_Pos (1U)
6390#define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
6391#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
6392#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
6393#define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
6394#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
6395
6396/******************** Bit definition for DFSDM_FLTISR register *******************/
6397#define DFSDM_FLTISR_SCDF_Pos (24U)
6398#define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
6399#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
6400#define DFSDM_FLTISR_CKABF_Pos (16U)
6401#define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
6402#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
6403#define DFSDM_FLTISR_RCIP_Pos (14U)
6404#define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
6405#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
6406#define DFSDM_FLTISR_JCIP_Pos (13U)
6407#define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
6408#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
6409#define DFSDM_FLTISR_AWDF_Pos (4U)
6410#define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
6411#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
6412#define DFSDM_FLTISR_ROVRF_Pos (3U)
6413#define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
6414#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
6415#define DFSDM_FLTISR_JOVRF_Pos (2U)
6416#define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
6417#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
6418#define DFSDM_FLTISR_REOCF_Pos (1U)
6419#define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
6420#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
6421#define DFSDM_FLTISR_JEOCF_Pos (0U)
6422#define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
6423#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
6424
6425/******************** Bit definition for DFSDM_FLTICR register *******************/
6426#define DFSDM_FLTICR_CLRSCDF_Pos (24U)
6427#define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0xFF000000 */
6428#define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
6429#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
6430#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
6431#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
6432#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
6433#define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
6434#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
6435#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
6436#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
6437#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
6438
6439/******************* Bit definition for DFSDM_FLTJCHGR register ******************/
6440#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
6441#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
6442#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
6443
6444/******************** Bit definition for DFSDM_FLTFCR register *******************/
6445#define DFSDM_FLTFCR_FORD_Pos (29U)
6446#define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
6447#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
6448#define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
6449#define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
6450#define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
6451#define DFSDM_FLTFCR_FOSR_Pos (16U)
6452#define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
6453#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
6454#define DFSDM_FLTFCR_IOSR_Pos (0U)
6455#define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
6456#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
6457
6458/****************** Bit definition for DFSDM_FLTJDATAR register *****************/
6459#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
6460#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
6461#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
6462#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
6463#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
6464#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
6465
6466/****************** Bit definition for DFSDM_FLTRDATAR register *****************/
6467#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
6468#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
6469#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
6470#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
6471#define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
6472#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
6473#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
6474#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
6475#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
6476
6477/****************** Bit definition for DFSDM_FLTAWHTR register ******************/
6478#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
6479#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
6480#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
6481#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
6482#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
6483#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
6484
6485/****************** Bit definition for DFSDM_FLTAWLTR register ******************/
6486#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
6487#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
6488#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWHT[23:0] Analog watchdog low threshold */
6489#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
6490#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
6491#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
6492
6493/****************** Bit definition for DFSDM_FLTAWSR register ******************/
6494#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
6495#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
6496#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
6497#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
6498#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
6499#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
6500
6501/****************** Bit definition for DFSDM_FLTAWCFR) register *****************/
6502#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
6503#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
6504#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
6505#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
6506#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
6507#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
6508
6509/****************** Bit definition for DFSDM_FLTEXMAX register ******************/
6510#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
6511#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
6512#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
6513#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
6514#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
6515#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
6516
6517/****************** Bit definition for DFSDM_FLTEXMIN register ******************/
6518#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
6519#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
6520#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
6521#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
6522#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
6523#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
6524
6525/****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
6526#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
6527#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
6528#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
6529
6530/******************************************************************************/
6531/* */
6532/* BDMA Controller */
6533/* */
6534/******************************************************************************/
6535
6536/******************* Bit definition for BDMA_ISR register ********************/
6537#define BDMA_ISR_GIF0_Pos (0U)
6538#define BDMA_ISR_GIF0_Msk (0x1UL << BDMA_ISR_GIF0_Pos) /*!< 0x00000001 */
6539#define BDMA_ISR_GIF0 BDMA_ISR_GIF0_Msk /*!< Channel 0 Global interrupt flag */
6540#define BDMA_ISR_TCIF0_Pos (1U)
6541#define BDMA_ISR_TCIF0_Msk (0x1UL << BDMA_ISR_TCIF0_Pos) /*!< 0x00000002 */
6542#define BDMA_ISR_TCIF0 BDMA_ISR_TCIF0_Msk /*!< Channel 0 Transfer Complete flag */
6543#define BDMA_ISR_HTIF0_Pos (2U)
6544#define BDMA_ISR_HTIF0_Msk (0x1UL << BDMA_ISR_HTIF0_Pos) /*!< 0x00000004 */
6545#define BDMA_ISR_HTIF0 BDMA_ISR_HTIF0_Msk /*!< Channel 0 Half Transfer flag */
6546#define BDMA_ISR_TEIF0_Pos (3U)
6547#define BDMA_ISR_TEIF0_Msk (0x1UL << BDMA_ISR_TEIF0_Pos) /*!< 0x00000008 */
6548#define BDMA_ISR_TEIF0 BDMA_ISR_TEIF0_Msk /*!< Channel 0 Transfer Error flag */
6549#define BDMA_ISR_GIF1_Pos (4U)
6550#define BDMA_ISR_GIF1_Msk (0x1UL << BDMA_ISR_GIF1_Pos) /*!< 0x00000010 */
6551#define BDMA_ISR_GIF1 BDMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
6552#define BDMA_ISR_TCIF1_Pos (5U)
6553#define BDMA_ISR_TCIF1_Msk (0x1UL << BDMA_ISR_TCIF1_Pos) /*!< 0x00000020 */
6554#define BDMA_ISR_TCIF1 BDMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
6555#define BDMA_ISR_HTIF1_Pos (6U)
6556#define BDMA_ISR_HTIF1_Msk (0x1UL << BDMA_ISR_HTIF1_Pos) /*!< 0x00000040 */
6557#define BDMA_ISR_HTIF1 BDMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
6558#define BDMA_ISR_TEIF1_Pos (7U)
6559#define BDMA_ISR_TEIF1_Msk (0x1UL << BDMA_ISR_TEIF1_Pos) /*!< 0x00000080 */
6560#define BDMA_ISR_TEIF1 BDMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
6561#define BDMA_ISR_GIF2_Pos (8U)
6562#define BDMA_ISR_GIF2_Msk (0x1UL << BDMA_ISR_GIF2_Pos) /*!< 0x00000100 */
6563#define BDMA_ISR_GIF2 BDMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
6564#define BDMA_ISR_TCIF2_Pos (9U)
6565#define BDMA_ISR_TCIF2_Msk (0x1UL << BDMA_ISR_TCIF2_Pos) /*!< 0x00000200 */
6566#define BDMA_ISR_TCIF2 BDMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
6567#define BDMA_ISR_HTIF2_Pos (10U)
6568#define BDMA_ISR_HTIF2_Msk (0x1UL << BDMA_ISR_HTIF2_Pos) /*!< 0x00000400 */
6569#define BDMA_ISR_HTIF2 BDMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
6570#define BDMA_ISR_TEIF2_Pos (11U)
6571#define BDMA_ISR_TEIF2_Msk (0x1UL << BDMA_ISR_TEIF2_Pos) /*!< 0x00000800 */
6572#define BDMA_ISR_TEIF2 BDMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
6573#define BDMA_ISR_GIF3_Pos (12U)
6574#define BDMA_ISR_GIF3_Msk (0x1UL << BDMA_ISR_GIF3_Pos) /*!< 0x00001000 */
6575#define BDMA_ISR_GIF3 BDMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
6576#define BDMA_ISR_TCIF3_Pos (13U)
6577#define BDMA_ISR_TCIF3_Msk (0x1UL << BDMA_ISR_TCIF3_Pos) /*!< 0x00002000 */
6578#define BDMA_ISR_TCIF3 BDMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
6579#define BDMA_ISR_HTIF3_Pos (14U)
6580#define BDMA_ISR_HTIF3_Msk (0x1UL << BDMA_ISR_HTIF3_Pos) /*!< 0x00004000 */
6581#define BDMA_ISR_HTIF3 BDMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
6582#define BDMA_ISR_TEIF3_Pos (15U)
6583#define BDMA_ISR_TEIF3_Msk (0x1UL << BDMA_ISR_TEIF3_Pos) /*!< 0x00008000 */
6584#define BDMA_ISR_TEIF3 BDMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
6585#define BDMA_ISR_GIF4_Pos (16U)
6586#define BDMA_ISR_GIF4_Msk (0x1UL << BDMA_ISR_GIF4_Pos) /*!< 0x00010000 */
6587#define BDMA_ISR_GIF4 BDMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
6588#define BDMA_ISR_TCIF4_Pos (17U)
6589#define BDMA_ISR_TCIF4_Msk (0x1UL << BDMA_ISR_TCIF4_Pos) /*!< 0x00020000 */
6590#define BDMA_ISR_TCIF4 BDMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
6591#define BDMA_ISR_HTIF4_Pos (18U)
6592#define BDMA_ISR_HTIF4_Msk (0x1UL << BDMA_ISR_HTIF4_Pos) /*!< 0x00040000 */
6593#define BDMA_ISR_HTIF4 BDMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
6594#define BDMA_ISR_TEIF4_Pos (19U)
6595#define BDMA_ISR_TEIF4_Msk (0x1UL << BDMA_ISR_TEIF4_Pos) /*!< 0x00080000 */
6596#define BDMA_ISR_TEIF4 BDMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
6597#define BDMA_ISR_GIF5_Pos (20U)
6598#define BDMA_ISR_GIF5_Msk (0x1UL << BDMA_ISR_GIF5_Pos) /*!< 0x00100000 */
6599#define BDMA_ISR_GIF5 BDMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
6600#define BDMA_ISR_TCIF5_Pos (21U)
6601#define BDMA_ISR_TCIF5_Msk (0x1UL << BDMA_ISR_TCIF5_Pos) /*!< 0x00200000 */
6602#define BDMA_ISR_TCIF5 BDMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
6603#define BDMA_ISR_HTIF5_Pos (22U)
6604#define BDMA_ISR_HTIF5_Msk (0x1UL << BDMA_ISR_HTIF5_Pos) /*!< 0x00400000 */
6605#define BDMA_ISR_HTIF5 BDMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
6606#define BDMA_ISR_TEIF5_Pos (23U)
6607#define BDMA_ISR_TEIF5_Msk (0x1UL << BDMA_ISR_TEIF5_Pos) /*!< 0x00800000 */
6608#define BDMA_ISR_TEIF5 BDMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
6609#define BDMA_ISR_GIF6_Pos (24U)
6610#define BDMA_ISR_GIF6_Msk (0x1UL << BDMA_ISR_GIF6_Pos) /*!< 0x01000000 */
6611#define BDMA_ISR_GIF6 BDMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
6612#define BDMA_ISR_TCIF6_Pos (25U)
6613#define BDMA_ISR_TCIF6_Msk (0x1UL << BDMA_ISR_TCIF6_Pos) /*!< 0x02000000 */
6614#define BDMA_ISR_TCIF6 BDMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
6615#define BDMA_ISR_HTIF6_Pos (26U)
6616#define BDMA_ISR_HTIF6_Msk (0x1UL << BDMA_ISR_HTIF6_Pos) /*!< 0x04000000 */
6617#define BDMA_ISR_HTIF6 BDMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
6618#define BDMA_ISR_TEIF6_Pos (27U)
6619#define BDMA_ISR_TEIF6_Msk (0x1UL << BDMA_ISR_TEIF6_Pos) /*!< 0x08000000 */
6620#define BDMA_ISR_TEIF6 BDMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
6621#define BDMA_ISR_GIF7_Pos (28U)
6622#define BDMA_ISR_GIF7_Msk (0x1UL << BDMA_ISR_GIF7_Pos) /*!< 0x10000000 */
6623#define BDMA_ISR_GIF7 BDMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
6624#define BDMA_ISR_TCIF7_Pos (29U)
6625#define BDMA_ISR_TCIF7_Msk (0x1UL << BDMA_ISR_TCIF7_Pos) /*!< 0x20000000 */
6626#define BDMA_ISR_TCIF7 BDMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
6627#define BDMA_ISR_HTIF7_Pos (30U)
6628#define BDMA_ISR_HTIF7_Msk (0x1UL << BDMA_ISR_HTIF7_Pos) /*!< 0x40000000 */
6629#define BDMA_ISR_HTIF7 BDMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
6630#define BDMA_ISR_TEIF7_Pos (31U)
6631#define BDMA_ISR_TEIF7_Msk (0x1UL << BDMA_ISR_TEIF7_Pos) /*!< 0x80000000 */
6632#define BDMA_ISR_TEIF7 BDMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
6633
6634/******************* Bit definition for BDMA_IFCR register *******************/
6635#define BDMA_IFCR_CGIF0_Pos (0U)
6636#define BDMA_IFCR_CGIF0_Msk (0x1UL << BDMA_IFCR_CGIF0_Pos) /*!< 0x00000001 */
6637#define BDMA_IFCR_CGIF0 BDMA_IFCR_CGIF0_Msk /*!< Channel 0 Global interrupt clearr */
6638#define BDMA_IFCR_CTCIF0_Pos (1U)
6639#define BDMA_IFCR_CTCIF0_Msk (0x1UL << BDMA_IFCR_CTCIF0_Pos) /*!< 0x00000002 */
6640#define BDMA_IFCR_CTCIF0 BDMA_IFCR_CTCIF0_Msk /*!< Channel 0 Transfer Complete clear */
6641#define BDMA_IFCR_CHTIF0_Pos (2U)
6642#define BDMA_IFCR_CHTIF0_Msk (0x1UL << BDMA_IFCR_CHTIF0_Pos) /*!< 0x00000004 */
6643#define BDMA_IFCR_CHTIF0 BDMA_IFCR_CHTIF0_Msk /*!< Channel 0 Half Transfer clear */
6644#define BDMA_IFCR_CTEIF0_Pos (3U)
6645#define BDMA_IFCR_CTEIF0_Msk (0x1UL << BDMA_IFCR_CTEIF0_Pos) /*!< 0x00000008 */
6646#define BDMA_IFCR_CTEIF0 BDMA_IFCR_CTEIF0_Msk /*!< Channel 0 Transfer Error clear */
6647#define BDMA_IFCR_CGIF1_Pos (4U)
6648#define BDMA_IFCR_CGIF1_Msk (0x1UL << BDMA_IFCR_CGIF1_Pos) /*!< 0x00000010 */
6649#define BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
6650#define BDMA_IFCR_CTCIF1_Pos (5U)
6651#define BDMA_IFCR_CTCIF1_Msk (0x1UL << BDMA_IFCR_CTCIF1_Pos) /*!< 0x00000020 */
6652#define BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
6653#define BDMA_IFCR_CHTIF1_Pos (6U)
6654#define BDMA_IFCR_CHTIF1_Msk (0x1UL << BDMA_IFCR_CHTIF1_Pos) /*!< 0x00000040 */
6655#define BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
6656#define BDMA_IFCR_CTEIF1_Pos (7U)
6657#define BDMA_IFCR_CTEIF1_Msk (0x1UL << BDMA_IFCR_CTEIF1_Pos) /*!< 0x00000080 */
6658#define BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
6659#define BDMA_IFCR_CGIF2_Pos (8U)
6660#define BDMA_IFCR_CGIF2_Msk (0x1UL << BDMA_IFCR_CGIF2_Pos) /*!< 0x00000100 */
6661#define BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
6662#define BDMA_IFCR_CTCIF2_Pos (9U)
6663#define BDMA_IFCR_CTCIF2_Msk (0x1UL << BDMA_IFCR_CTCIF2_Pos) /*!< 0x00000200 */
6664#define BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
6665#define BDMA_IFCR_CHTIF2_Pos (10U)
6666#define BDMA_IFCR_CHTIF2_Msk (0x1UL << BDMA_IFCR_CHTIF2_Pos) /*!< 0x00000400 */
6667#define BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
6668#define BDMA_IFCR_CTEIF2_Pos (11U)
6669#define BDMA_IFCR_CTEIF2_Msk (0x1UL << BDMA_IFCR_CTEIF2_Pos) /*!< 0x00000800 */
6670#define BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
6671#define BDMA_IFCR_CGIF3_Pos (12U)
6672#define BDMA_IFCR_CGIF3_Msk (0x1UL << BDMA_IFCR_CGIF3_Pos) /*!< 0x00001000 */
6673#define BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
6674#define BDMA_IFCR_CTCIF3_Pos (13U)
6675#define BDMA_IFCR_CTCIF3_Msk (0x1UL << BDMA_IFCR_CTCIF3_Pos) /*!< 0x00002000 */
6676#define BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
6677#define BDMA_IFCR_CHTIF3_Pos (14U)
6678#define BDMA_IFCR_CHTIF3_Msk (0x1UL << BDMA_IFCR_CHTIF3_Pos) /*!< 0x00004000 */
6679#define BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
6680#define BDMA_IFCR_CTEIF3_Pos (15U)
6681#define BDMA_IFCR_CTEIF3_Msk (0x1UL << BDMA_IFCR_CTEIF3_Pos) /*!< 0x00008000 */
6682#define BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
6683#define BDMA_IFCR_CGIF4_Pos (16U)
6684#define BDMA_IFCR_CGIF4_Msk (0x1UL << BDMA_IFCR_CGIF4_Pos) /*!< 0x00010000 */
6685#define BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
6686#define BDMA_IFCR_CTCIF4_Pos (17U)
6687#define BDMA_IFCR_CTCIF4_Msk (0x1UL << BDMA_IFCR_CTCIF4_Pos) /*!< 0x00020000 */
6688#define BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
6689#define BDMA_IFCR_CHTIF4_Pos (18U)
6690#define BDMA_IFCR_CHTIF4_Msk (0x1UL << BDMA_IFCR_CHTIF4_Pos) /*!< 0x00040000 */
6691#define BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
6692#define BDMA_IFCR_CTEIF4_Pos (19U)
6693#define BDMA_IFCR_CTEIF4_Msk (0x1UL << BDMA_IFCR_CTEIF4_Pos) /*!< 0x00080000 */
6694#define BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
6695#define BDMA_IFCR_CGIF5_Pos (20U)
6696#define BDMA_IFCR_CGIF5_Msk (0x1UL << BDMA_IFCR_CGIF5_Pos) /*!< 0x00100000 */
6697#define BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
6698#define BDMA_IFCR_CTCIF5_Pos (21U)
6699#define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
6700#define BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
6701#define BDMA_IFCR_CHTIF5_Pos (22U)
6702#define BDMA_IFCR_CHTIF5_Msk (0x1UL << BDMA_IFCR_CHTIF5_Pos) /*!< 0x00400000 */
6703#define BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
6704#define BDMA_IFCR_CTEIF5_Pos (23U)
6705#define BDMA_IFCR_CTEIF5_Msk (0x1UL << BDMA_IFCR_CTEIF5_Pos) /*!< 0x00800000 */
6706#define BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
6707#define BDMA_IFCR_CGIF6_Pos (24U)
6708#define BDMA_IFCR_CGIF6_Msk (0x1UL << BDMA_IFCR_CGIF6_Pos) /*!< 0x01000000 */
6709#define BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
6710#define BDMA_IFCR_CTCIF6_Pos (25U)
6711#define BDMA_IFCR_CTCIF6_Msk (0x1UL << BDMA_IFCR_CTCIF6_Pos) /*!< 0x02000000 */
6712#define BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
6713#define BDMA_IFCR_CHTIF6_Pos (26U)
6714#define BDMA_IFCR_CHTIF6_Msk (0x1UL << BDMA_IFCR_CHTIF6_Pos) /*!< 0x04000000 */
6715#define BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
6716#define BDMA_IFCR_CTEIF6_Pos (27U)
6717#define BDMA_IFCR_CTEIF6_Msk (0x1UL << BDMA_IFCR_CTEIF6_Pos) /*!< 0x08000000 */
6718#define BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
6719#define BDMA_IFCR_CGIF7_Pos (28U)
6720#define BDMA_IFCR_CGIF7_Msk (0x1UL << BDMA_IFCR_CGIF7_Pos) /*!< 0x10000000 */
6721#define BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
6722#define BDMA_IFCR_CTCIF7_Pos (29U)
6723#define BDMA_IFCR_CTCIF7_Msk (0x1UL << BDMA_IFCR_CTCIF7_Pos) /*!< 0x20000000 */
6724#define BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
6725#define BDMA_IFCR_CHTIF7_Pos (30U)
6726#define BDMA_IFCR_CHTIF7_Msk (0x1UL << BDMA_IFCR_CHTIF7_Pos) /*!< 0x40000000 */
6727#define BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
6728#define BDMA_IFCR_CTEIF7_Pos (31U)
6729#define BDMA_IFCR_CTEIF7_Msk (0x1UL << BDMA_IFCR_CTEIF7_Pos) /*!< 0x80000000 */
6730#define BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
6731
6732/******************* Bit definition for BDMA_CCR register ********************/
6733#define BDMA_CCR_EN_Pos (0U)
6734#define BDMA_CCR_EN_Msk (0x1UL << BDMA_CCR_EN_Pos) /*!< 0x00000001 */
6735#define BDMA_CCR_EN BDMA_CCR_EN_Msk /*!< Channel enable */
6736#define BDMA_CCR_TCIE_Pos (1U)
6737#define BDMA_CCR_TCIE_Msk (0x1UL << BDMA_CCR_TCIE_Pos) /*!< 0x00000002 */
6738#define BDMA_CCR_TCIE BDMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
6739#define BDMA_CCR_HTIE_Pos (2U)
6740#define BDMA_CCR_HTIE_Msk (0x1UL << BDMA_CCR_HTIE_Pos) /*!< 0x00000004 */
6741#define BDMA_CCR_HTIE BDMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
6742#define BDMA_CCR_TEIE_Pos (3U)
6743#define BDMA_CCR_TEIE_Msk (0x1UL << BDMA_CCR_TEIE_Pos) /*!< 0x00000008 */
6744#define BDMA_CCR_TEIE BDMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
6745#define BDMA_CCR_DIR_Pos (4U)
6746#define BDMA_CCR_DIR_Msk (0x1UL << BDMA_CCR_DIR_Pos) /*!< 0x00000010 */
6747#define BDMA_CCR_DIR BDMA_CCR_DIR_Msk /*!< Data transfer direction */
6748#define BDMA_CCR_CIRC_Pos (5U)
6749#define BDMA_CCR_CIRC_Msk (0x1UL << BDMA_CCR_CIRC_Pos) /*!< 0x00000020 */
6750#define BDMA_CCR_CIRC BDMA_CCR_CIRC_Msk /*!< Circular mode */
6751#define BDMA_CCR_PINC_Pos (6U)
6752#define BDMA_CCR_PINC_Msk (0x1UL << BDMA_CCR_PINC_Pos) /*!< 0x00000040 */
6753#define BDMA_CCR_PINC BDMA_CCR_PINC_Msk /*!< Peripheral increment mode */
6754#define BDMA_CCR_MINC_Pos (7U)
6755#define BDMA_CCR_MINC_Msk (0x1UL << BDMA_CCR_MINC_Pos) /*!< 0x00000080 */
6756#define BDMA_CCR_MINC BDMA_CCR_MINC_Msk /*!< Memory increment mode */
6757
6758#define BDMA_CCR_PSIZE_Pos (8U)
6759#define BDMA_CCR_PSIZE_Msk (0x3UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
6760#define BDMA_CCR_PSIZE BDMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
6761#define BDMA_CCR_PSIZE_0 (0x1UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
6762#define BDMA_CCR_PSIZE_1 (0x2UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
6763
6764#define BDMA_CCR_MSIZE_Pos (10U)
6765#define BDMA_CCR_MSIZE_Msk (0x3UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
6766#define BDMA_CCR_MSIZE BDMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
6767#define BDMA_CCR_MSIZE_0 (0x1UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
6768#define BDMA_CCR_MSIZE_1 (0x2UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
6769
6770#define BDMA_CCR_PL_Pos (12U)
6771#define BDMA_CCR_PL_Msk (0x3UL << BDMA_CCR_PL_Pos) /*!< 0x00003000 */
6772#define BDMA_CCR_PL BDMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
6773#define BDMA_CCR_PL_0 (0x1UL << BDMA_CCR_PL_Pos) /*!< 0x00001000 */
6774#define BDMA_CCR_PL_1 (0x2UL << BDMA_CCR_PL_Pos) /*!< 0x00002000 */
6775
6776#define BDMA_CCR_MEM2MEM_Pos (14U)
6777#define BDMA_CCR_MEM2MEM_Msk (0x1UL << BDMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
6778#define BDMA_CCR_MEM2MEM BDMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
6779#define BDMA_CCR_DBM_Pos (15U)
6780#define BDMA_CCR_DBM_Msk (0x1UL << BDMA_CCR_DBM_Pos) /*!< 0x0000A000 */
6781#define BDMA_CCR_DBM BDMA_CCR_DBM_Msk /*!< Memory to memory mode */
6782#define BDMA_CCR_CT_Pos (16U)
6783#define BDMA_CCR_CT_Msk (0x1UL << BDMA_CCR_CT_Pos) /*!< 0x00010000 */
6784#define BDMA_CCR_CT BDMA_CCR_CT_Msk /*!< Memory to memory mode */
6785
6786/****************** Bit definition for BDMA_CNDTR register *******************/
6787#define BDMA_CNDTR_NDT_Pos (0U)
6788#define BDMA_CNDTR_NDT_Msk (0xFFFFUL << BDMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
6789#define BDMA_CNDTR_NDT BDMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
6790
6791/****************** Bit definition for BDMA_CPAR register ********************/
6792#define BDMA_CPAR_PA_Pos (0U)
6793#define BDMA_CPAR_PA_Msk (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
6794#define BDMA_CPAR_PA BDMA_CPAR_PA_Msk /*!< Peripheral Address */
6795
6796/****************** Bit definition for BDMA_CM0AR register ********************/
6797#define BDMA_CM0AR_MA_Pos (0U)
6798#define BDMA_CM0AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos) /*!< 0xFFFFFFFF */
6799#define BDMA_CM0AR_MA BDMA_CM0AR_MA_Msk /*!< Memory Address */
6800
6801/****************** Bit definition for BDMA_CM1AR register ********************/
6802#define BDMA_CM1AR_MA_Pos (0U)
6803#define BDMA_CM1AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos) /*!< 0xFFFFFFFF */
6804#define BDMA_CM1AR_MA BDMA_CM1AR_MA_Msk /*!< Memory Address */
6805
6806/******************************************************************************/
6807/* */
6808/* Ethernet MAC Registers bits definitions */
6809/* */
6810/******************************************************************************/
6811/* Bit definition for Ethernet MAC Configuration Register register */
6812#define ETH_MACCR_ARP_Pos (31U)
6813#define ETH_MACCR_ARP_Msk (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */
6814#define ETH_MACCR_ARP ETH_MACCR_ARP_Msk /* ARP Offload Enable */
6815#define ETH_MACCR_SARC_Pos (28U)
6816#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
6817#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
6818#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
6819#define ETH_MACCR_SARC_INSADDR0_Pos (29U)
6820#define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
6821#define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
6822#define ETH_MACCR_SARC_INSADDR1_Pos (29U)
6823#define ETH_MACCR_SARC_INSADDR1_Msk (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */
6824#define ETH_MACCR_SARC_INSADDR1 ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
6825#define ETH_MACCR_SARC_REPADDR0_Pos (28U)
6826#define ETH_MACCR_SARC_REPADDR0_Msk (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */
6827#define ETH_MACCR_SARC_REPADDR0 ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
6828#define ETH_MACCR_SARC_REPADDR1_Pos (28U)
6829#define ETH_MACCR_SARC_REPADDR1_Msk (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */
6830#define ETH_MACCR_SARC_REPADDR1 ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
6831#define ETH_MACCR_IPC_Pos (27U)
6832#define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */
6833#define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /* Checksum Offload */
6834#define ETH_MACCR_IPG_Pos (24U)
6835#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
6836#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
6837#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */
6838#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */
6839#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */
6840#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */
6841#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */
6842#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */
6843#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */
6844#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */
6845#define ETH_MACCR_GPSLCE_Pos (23U)
6846#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
6847#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
6848#define ETH_MACCR_S2KP_Pos (22U)
6849#define ETH_MACCR_S2KP_Msk (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */
6850#define ETH_MACCR_S2KP ETH_MACCR_S2KP_Msk /* IEEE 802.3as Support for 2K Packets */
6851#define ETH_MACCR_CST_Pos (21U)
6852#define ETH_MACCR_CST_Msk (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */
6853#define ETH_MACCR_CST ETH_MACCR_CST_Msk /* CRC stripping for Type packets */
6854#define ETH_MACCR_ACS_Pos (20U)
6855#define ETH_MACCR_ACS_Msk (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */
6856#define ETH_MACCR_ACS ETH_MACCR_ACS_Msk /* Automatic Pad or CRC Stripping */
6857#define ETH_MACCR_WD_Pos (19U)
6858#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */
6859#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
6860#define ETH_MACCR_JD_Pos (17U)
6861#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */
6862#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
6863#define ETH_MACCR_JE_Pos (16U)
6864#define ETH_MACCR_JE_Msk (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */
6865#define ETH_MACCR_JE ETH_MACCR_JE_Msk /* Jumbo Packet Enable */
6866#define ETH_MACCR_FES_Pos (14U)
6867#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
6868#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
6869#define ETH_MACCR_DM_Pos (13U)
6870#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */
6871#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
6872#define ETH_MACCR_LM_Pos (12U)
6873#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
6874#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
6875#define ETH_MACCR_ECRSFD_Pos (11U)
6876#define ETH_MACCR_ECRSFD_Msk (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */
6877#define ETH_MACCR_ECRSFD ETH_MACCR_ECRSFD_Msk /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
6878#define ETH_MACCR_DO_Pos (10U)
6879#define ETH_MACCR_DO_Msk (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */
6880#define ETH_MACCR_DO ETH_MACCR_DO_Msk /* Disable Receive own */
6881#define ETH_MACCR_DCRS_Pos (9U)
6882#define ETH_MACCR_DCRS_Msk (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */
6883#define ETH_MACCR_DCRS ETH_MACCR_DCRS_Msk /* Disable Carrier Sense During Transmission */
6884#define ETH_MACCR_DR_Pos (8U)
6885#define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */
6886#define ETH_MACCR_DR ETH_MACCR_DR_Msk /* Disable Retry */
6887#define ETH_MACCR_BL_Pos (5U)
6888#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
6889#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit mask */
6890#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */
6891#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */
6892#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */
6893#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
6894#define ETH_MACCR_DC_Pos (4U)
6895#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
6896#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
6897#define ETH_MACCR_PRELEN_Pos (2U)
6898#define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */
6899#define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /* Preamble Length for Transmit packets */
6900#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */
6901#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */
6902#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */
6903#define ETH_MACCR_TE_Pos (1U)
6904#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */
6905#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
6906#define ETH_MACCR_RE_Pos (0U)
6907#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */
6908#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
6909
6910/* Bit definition for Ethernet MAC Extended Configuration Register register */
6911#define ETH_MACECR_EIPG_Pos (25U)
6912#define ETH_MACECR_EIPG_Msk (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */
6913#define ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk /* Extended Inter-Packet Gap */
6914#define ETH_MACECR_EIPGEN_Pos (24U)
6915#define ETH_MACECR_EIPGEN_Msk (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */
6916#define ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk /* Extended Inter-Packet Gap Enable */
6917#define ETH_MACECR_USP_Pos (18U)
6918#define ETH_MACECR_USP_Msk (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */
6919#define ETH_MACECR_USP ETH_MACECR_USP_Msk /* Unicast Slow Protocol Packet Detect */
6920#define ETH_MACECR_SPEN_Pos (17U)
6921#define ETH_MACECR_SPEN_Msk (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */
6922#define ETH_MACECR_SPEN ETH_MACECR_SPEN_Msk /* Slow Protocol Detection Enable */
6923#define ETH_MACECR_DCRCC_Pos (16U)
6924#define ETH_MACECR_DCRCC_Msk (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */
6925#define ETH_MACECR_DCRCC ETH_MACECR_DCRCC_Msk /* Disable CRC Checking for Received Packets */
6926#define ETH_MACECR_GPSL_Pos (0U)
6927#define ETH_MACECR_GPSL_Msk (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */
6928#define ETH_MACECR_GPSL ETH_MACECR_GPSL_Msk /* Giant Packet Size Limit */
6929
6930/* Bit definition for Ethernet MAC Packet Filter Register */
6931#define ETH_MACPFR_RA_Pos (31U)
6932#define ETH_MACPFR_RA_Msk (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */
6933#define ETH_MACPFR_RA ETH_MACPFR_RA_Msk /* Receive all */
6934#define ETH_MACPFR_DNTU_Pos (21U)
6935#define ETH_MACPFR_DNTU_Msk (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */
6936#define ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk /* Drop Non-TCP/UDP over IP Packets */
6937#define ETH_MACPFR_IPFE_Pos (20U)
6938#define ETH_MACPFR_IPFE_Msk (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */
6939#define ETH_MACPFR_IPFE ETH_MACPFR_IPFE_Msk /* Layer 3 and Layer 4 Filter Enable */
6940#define ETH_MACPFR_VTFE_Pos (16U)
6941#define ETH_MACPFR_VTFE_Msk (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */
6942#define ETH_MACPFR_VTFE ETH_MACPFR_VTFE_Msk /* VLAN Tag Filter Enable */
6943#define ETH_MACPFR_HPF_Pos (10U)
6944#define ETH_MACPFR_HPF_Msk (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */
6945#define ETH_MACPFR_HPF ETH_MACPFR_HPF_Msk /* Hash or perfect filter */
6946#define ETH_MACPFR_SAF_Pos (9U)
6947#define ETH_MACPFR_SAF_Msk (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */
6948#define ETH_MACPFR_SAF ETH_MACPFR_SAF_Msk /* Source address filter enable */
6949#define ETH_MACPFR_SAIF_Pos (8U)
6950#define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */
6951#define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /* SA inverse filtering */
6952#define ETH_MACPFR_PCF_Pos (6U)
6953#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
6954#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
6955#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */
6956#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
6957#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
6958#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
6959#define ETH_MACPFR_PCF_FORWARDALL_Pos (7U)
6960#define ETH_MACPFR_PCF_FORWARDALL_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */
6961#define ETH_MACPFR_PCF_FORWARDALL ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
6962#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos (6U)
6963#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */
6964#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
6965#define ETH_MACPFR_DBF_Pos (5U)
6966#define ETH_MACPFR_DBF_Msk (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */
6967#define ETH_MACPFR_DBF ETH_MACPFR_DBF_Msk /* Disable Broadcast Packets */
6968#define ETH_MACPFR_PM_Pos (4U)
6969#define ETH_MACPFR_PM_Msk (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */
6970#define ETH_MACPFR_PM ETH_MACPFR_PM_Msk /* Pass all mutlicast */
6971#define ETH_MACPFR_DAIF_Pos (3U)
6972#define ETH_MACPFR_DAIF_Msk (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */
6973#define ETH_MACPFR_DAIF ETH_MACPFR_DAIF_Msk /* DA Inverse filtering */
6974#define ETH_MACPFR_HMC_Pos (2U)
6975#define ETH_MACPFR_HMC_Msk (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */
6976#define ETH_MACPFR_HMC ETH_MACPFR_HMC_Msk /* Hash multicast */
6977#define ETH_MACPFR_HUC_Pos (1U)
6978#define ETH_MACPFR_HUC_Msk (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */
6979#define ETH_MACPFR_HUC ETH_MACPFR_HUC_Msk /* Hash unicast */
6980#define ETH_MACPFR_PR_Pos (0U)
6981#define ETH_MACPFR_PR_Msk (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */
6982#define ETH_MACPFR_PR ETH_MACPFR_PR_Msk /* Promiscuous mode */
6983
6984/* Bit definition for Ethernet MAC Watchdog Timeout Register */
6985#define ETH_MACWTR_PWE_Pos (8U)
6986#define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */
6987#define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /* Programmable Watchdog Enable */
6988#define ETH_MACWTR_WTO_Pos (0U)
6989#define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
6990#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
6991#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/
6992#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */
6993#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */
6994#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */
6995#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */
6996#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */
6997#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */
6998#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */
6999#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */
7000#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */
7001#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */
7002#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */
7003#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */
7004#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */
7005#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */
7006
7007/* Bit definition for Ethernet MAC Hash Table High Register */
7008#define ETH_MACHTHR_HTH_Pos (0U)
7009#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
7010#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
7011
7012/* Bit definition for Ethernet MAC Hash Table Low Register */
7013#define ETH_MACHTLR_HTL_Pos (0U)
7014#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
7015#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
7016
7017/* Bit definition for Ethernet MAC VLAN Tag Register */
7018#define ETH_MACVTR_EIVLRXS_Pos (31U)
7019#define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */
7020#define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /* Enable Inner VLAN Tag in Rx Status */
7021#define ETH_MACVTR_EIVLS_Pos (28U)
7022#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
7023#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
7024#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
7025#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
7026#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
7027#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
7028#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U)
7029#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */
7030#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
7031#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U)
7032#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */
7033#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
7034#define ETH_MACVTR_ERIVLT_Pos (27U)
7035#define ETH_MACVTR_ERIVLT_Msk (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */
7036#define ETH_MACVTR_ERIVLT ETH_MACVTR_ERIVLT_Msk /* Enable Inner VLAN Tag */
7037#define ETH_MACVTR_EDVLP_Pos (26U)
7038#define ETH_MACVTR_EDVLP_Msk (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */
7039#define ETH_MACVTR_EDVLP ETH_MACVTR_EDVLP_Msk /* Enable Double VLAN Processing */
7040#define ETH_MACVTR_VTHM_Pos (25U)
7041#define ETH_MACVTR_VTHM_Msk (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */
7042#define ETH_MACVTR_VTHM ETH_MACVTR_VTHM_Msk /* VLAN Tag Hash Table Match Enable */
7043#define ETH_MACVTR_EVLRXS_Pos (24U)
7044#define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */
7045#define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /* Enable VLAN Tag in Rx status */
7046#define ETH_MACVTR_EVLS_Pos (21U)
7047#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
7048#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
7049#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
7050#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
7051#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
7052#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
7053#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U)
7054#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */
7055#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
7056#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U)
7057#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */
7058#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
7059#define ETH_MACVTR_DOVLTC_Pos (20U)
7060#define ETH_MACVTR_DOVLTC_Msk (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */
7061#define ETH_MACVTR_DOVLTC ETH_MACVTR_DOVLTC_Msk /* Disable VLAN Type Check */
7062#define ETH_MACVTR_ERSVLM_Pos (19U)
7063#define ETH_MACVTR_ERSVLM_Msk (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */
7064#define ETH_MACVTR_ERSVLM ETH_MACVTR_ERSVLM_Msk /* Enable Receive S-VLAN Match */
7065#define ETH_MACVTR_ESVL_Pos (18U)
7066#define ETH_MACVTR_ESVL_Msk (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */
7067#define ETH_MACVTR_ESVL ETH_MACVTR_ESVL_Msk /* Enable S-VLAN */
7068#define ETH_MACVTR_VTIM_Pos (17U)
7069#define ETH_MACVTR_VTIM_Msk (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */
7070#define ETH_MACVTR_VTIM ETH_MACVTR_VTIM_Msk /* VLAN Tag Inverse Match Enable */
7071#define ETH_MACVTR_ETV_Pos (16U)
7072#define ETH_MACVTR_ETV_Msk (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */
7073#define ETH_MACVTR_ETV ETH_MACVTR_ETV_Msk /* Enable 12-Bit VLAN Tag Comparison */
7074#define ETH_MACVTR_VL_Pos (0U)
7075#define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */
7076#define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /* VLAN Tag Identifier for Receive Packets */
7077#define ETH_MACVTR_VL_UP_Pos (13U)
7078#define ETH_MACVTR_VL_UP_Msk (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */
7079#define ETH_MACVTR_VL_UP ETH_MACVTR_VL_UP_Msk /* User Priority */
7080#define ETH_MACVTR_VL_CFIDEI_Pos (12U)
7081#define ETH_MACVTR_VL_CFIDEI_Msk (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */
7082#define ETH_MACVTR_VL_CFIDEI ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
7083#define ETH_MACVTR_VL_VID_Pos (0U)
7084#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */
7085#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /* VLAN Identifier field of VLAN tag */
7086
7087/* Bit definition for Ethernet MAC VLAN Hash Table Register */
7088#define ETH_MACVHTR_VLHT_Pos (0U)
7089#define ETH_MACVHTR_VLHT_Msk (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */
7090#define ETH_MACVHTR_VLHT ETH_MACVHTR_VLHT_Msk /* VLAN Hash Table */
7091
7092/* Bit definition for Ethernet MAC VLAN Incl Register */
7093#define ETH_MACVIR_VLTI_Pos (20U)
7094#define ETH_MACVIR_VLTI_Msk (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */
7095#define ETH_MACVIR_VLTI ETH_MACVIR_VLTI_Msk /* VLAN Tag Input */
7096#define ETH_MACVIR_CSVL_Pos (19U)
7097#define ETH_MACVIR_CSVL_Msk (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */
7098#define ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk /* C-VLAN or S-VLAN */
7099#define ETH_MACVIR_VLP_Pos (18U)
7100#define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */
7101#define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /* VLAN Priority Control */
7102#define ETH_MACVIR_VLC_Pos (16U)
7103#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
7104#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
7105#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
7106#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
7107#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
7108#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
7109#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U)
7110#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
7111#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
7112#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U)
7113#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
7114#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
7115#define ETH_MACVIR_VLT_Pos (0U)
7116#define ETH_MACVIR_VLT_Msk (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */
7117#define ETH_MACVIR_VLT ETH_MACVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
7118#define ETH_MACVIR_VLT_UP_Pos (13U)
7119#define ETH_MACVIR_VLT_UP_Msk (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */
7120#define ETH_MACVIR_VLT_UP ETH_MACVIR_VLT_UP_Msk /* User Priority */
7121#define ETH_MACVIR_VLT_CFIDEI_Pos (12U)
7122#define ETH_MACVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
7123#define ETH_MACVIR_VLT_CFIDEI ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
7124#define ETH_MACVIR_VLT_VID_Pos (0U)
7125#define ETH_MACVIR_VLT_VID_Msk (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */
7126#define ETH_MACVIR_VLT_VID ETH_MACVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
7127
7128/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */
7129#define ETH_MACIVIR_VLTI_Pos (20U)
7130#define ETH_MACIVIR_VLTI_Msk (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */
7131#define ETH_MACIVIR_VLTI ETH_MACIVIR_VLTI_Msk /* VLAN Tag Input */
7132#define ETH_MACIVIR_CSVL_Pos (19U)
7133#define ETH_MACIVIR_CSVL_Msk (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */
7134#define ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk /* C-VLAN or S-VLAN */
7135#define ETH_MACIVIR_VLP_Pos (18U)
7136#define ETH_MACIVIR_VLP_Msk (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */
7137#define ETH_MACIVIR_VLP ETH_MACIVIR_VLP_Msk /* VLAN Priority Control */
7138#define ETH_MACIVIR_VLC_Pos (16U)
7139#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
7140#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
7141#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
7142#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
7143#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
7144#define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
7145#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos (17U)
7146#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
7147#define ETH_MACIVIR_VLC_VLANTAGINSERT ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
7148#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos (16U)
7149#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
7150#define ETH_MACIVIR_VLC_VLANTAGREPLACE ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
7151#define ETH_MACIVIR_VLT_Pos (0U)
7152#define ETH_MACIVIR_VLT_Msk (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */
7153#define ETH_MACIVIR_VLT ETH_MACIVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
7154#define ETH_MACIVIR_VLT_UP_Pos (13U)
7155#define ETH_MACIVIR_VLT_UP_Msk (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */
7156#define ETH_MACIVIR_VLT_UP ETH_MACIVIR_VLT_UP_Msk /* User Priority */
7157#define ETH_MACIVIR_VLT_CFIDEI_Pos (12U)
7158#define ETH_MACIVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
7159#define ETH_MACIVIR_VLT_CFIDEI ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
7160#define ETH_MACIVIR_VLT_VID_Pos (0U)
7161#define ETH_MACIVIR_VLT_VID_Msk (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */
7162#define ETH_MACIVIR_VLT_VID ETH_MACIVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
7163
7164/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */
7165#define ETH_MACTFCR_PT_Pos (16U)
7166#define ETH_MACTFCR_PT_Msk (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */
7167#define ETH_MACTFCR_PT ETH_MACTFCR_PT_Msk /* Pause Time */
7168#define ETH_MACTFCR_DZPQ_Pos (7U)
7169#define ETH_MACTFCR_DZPQ_Msk (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */
7170#define ETH_MACTFCR_DZPQ ETH_MACTFCR_DZPQ_Msk /* Disable Zero-Quanta Pause */
7171#define ETH_MACTFCR_PLT_Pos (4U)
7172#define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
7173#define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
7174#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
7175#define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
7176#define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
7177#define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
7178#define ETH_MACTFCR_PLT_MINUS36_Pos (5U)
7179#define ETH_MACTFCR_PLT_MINUS36_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */
7180#define ETH_MACTFCR_PLT_MINUS36 ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
7181#define ETH_MACTFCR_PLT_MINUS144_Pos (4U)
7182#define ETH_MACTFCR_PLT_MINUS144_Msk (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */
7183#define ETH_MACTFCR_PLT_MINUS144 ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
7184#define ETH_MACTFCR_PLT_MINUS256_Pos (6U)
7185#define ETH_MACTFCR_PLT_MINUS256_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */
7186#define ETH_MACTFCR_PLT_MINUS256 ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
7187#define ETH_MACTFCR_PLT_MINUS512_Pos (4U)
7188#define ETH_MACTFCR_PLT_MINUS512_Msk (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */
7189#define ETH_MACTFCR_PLT_MINUS512 ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
7190#define ETH_MACTFCR_TFE_Pos (1U)
7191#define ETH_MACTFCR_TFE_Msk (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */
7192#define ETH_MACTFCR_TFE ETH_MACTFCR_TFE_Msk /* Transmit Flow Control Enable */
7193#define ETH_MACTFCR_FCB_Pos (0U)
7194#define ETH_MACTFCR_FCB_Msk (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */
7195#define ETH_MACTFCR_FCB ETH_MACTFCR_FCB_Msk /* Flow Control Busy or Backpressure Activate */
7196
7197/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */
7198#define ETH_MACRFCR_UP_Pos (1U)
7199#define ETH_MACRFCR_UP_Msk (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */
7200#define ETH_MACRFCR_UP ETH_MACRFCR_UP_Msk /* Unicast Pause Packet Detect */
7201#define ETH_MACRFCR_RFE_Pos (0U)
7202#define ETH_MACRFCR_RFE_Msk (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */
7203#define ETH_MACRFCR_RFE ETH_MACRFCR_RFE_Msk /* Receive Flow Control Enable */
7204
7205/* Bit definition for Ethernet MAC Interrupt Status Register */
7206#define ETH_MACISR_RXSTSIS_Pos (14U)
7207#define ETH_MACISR_RXSTSIS_Msk (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */
7208#define ETH_MACISR_RXSTSIS ETH_MACISR_RXSTSIS_Msk /* Receive Status Interrupt */
7209#define ETH_MACISR_TXSTSIS_Pos (13U)
7210#define ETH_MACISR_TXSTSIS_Msk (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */
7211#define ETH_MACISR_TXSTSIS ETH_MACISR_TXSTSIS_Msk /* Transmit Status Interrupt */
7212#define ETH_MACISR_TSIS_Pos (12U)
7213#define ETH_MACISR_TSIS_Msk (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */
7214#define ETH_MACISR_TSIS ETH_MACISR_TSIS_Msk /* Timestamp Interrupt Status */
7215#define ETH_MACISR_MMCTXIS_Pos (10U)
7216#define ETH_MACISR_MMCTXIS_Msk (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */
7217#define ETH_MACISR_MMCTXIS ETH_MACISR_MMCTXIS_Msk /* MMC Transmit Interrupt Status */
7218#define ETH_MACISR_MMCRXIS_Pos (9U)
7219#define ETH_MACISR_MMCRXIS_Msk (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */
7220#define ETH_MACISR_MMCRXIS ETH_MACISR_MMCRXIS_Msk /* MMC Receive Interrupt Status */
7221#define ETH_MACISR_MMCIS_Pos (8U)
7222#define ETH_MACISR_MMCIS_Msk (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */
7223#define ETH_MACISR_MMCIS ETH_MACISR_MMCIS_Msk /* MMC Interrupt Status */
7224#define ETH_MACISR_LPIIS_Pos (5U)
7225#define ETH_MACISR_LPIIS_Msk (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */
7226#define ETH_MACISR_LPIIS ETH_MACISR_LPIIS_Msk /* LPI Interrupt Status */
7227#define ETH_MACISR_PMTIS_Pos (4U)
7228#define ETH_MACISR_PMTIS_Msk (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */
7229#define ETH_MACISR_PMTIS ETH_MACISR_PMTIS_Msk /* PMT Interrupt Status */
7230#define ETH_MACISR_PHYIS_Pos (3U)
7231#define ETH_MACISR_PHYIS_Msk (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */
7232#define ETH_MACISR_PHYIS ETH_MACISR_PHYIS_Msk /* PHY Interrupt */
7233
7234/* Bit definition for Ethernet MAC Interrupt Enable Register */
7235#define ETH_MACIER_RXSTSIE_Pos (14U)
7236#define ETH_MACIER_RXSTSIE_Msk (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */
7237#define ETH_MACIER_RXSTSIE ETH_MACIER_RXSTSIE_Msk /* Receive Status Interrupt Enable */
7238#define ETH_MACIER_TXSTSIE_Pos (13U)
7239#define ETH_MACIER_TXSTSIE_Msk (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */
7240#define ETH_MACIER_TXSTSIE ETH_MACIER_TXSTSIE_Msk /* Transmit Status Interrupt Enable */
7241#define ETH_MACIER_TSIE_Pos (12U)
7242#define ETH_MACIER_TSIE_Msk (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */
7243#define ETH_MACIER_TSIE ETH_MACIER_TSIE_Msk /* Timestamp Interrupt Enable */
7244#define ETH_MACIER_LPIIE_Pos (5U)
7245#define ETH_MACIER_LPIIE_Msk (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */
7246#define ETH_MACIER_LPIIE ETH_MACIER_LPIIE_Msk /* LPI Interrupt Enable */
7247#define ETH_MACIER_PMTIE_Pos (4U)
7248#define ETH_MACIER_PMTIE_Msk (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */
7249#define ETH_MACIER_PMTIE ETH_MACIER_PMTIE_Msk /* PMT Interrupt Enable */
7250#define ETH_MACIER_PHYIE_Pos (3U)
7251#define ETH_MACIER_PHYIE_Msk (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */
7252#define ETH_MACIER_PHYIE ETH_MACIER_PHYIE_Msk /* PHY Interrupt Enable */
7253
7254/* Bit definition for Ethernet MAC Rx Tx Status Register */
7255#define ETH_MACRXTXSR_RWT_Pos (8U)
7256#define ETH_MACRXTXSR_RWT_Msk (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */
7257#define ETH_MACRXTXSR_RWT ETH_MACRXTXSR_RWT_Msk /* Receive Watchdog Timeout */
7258#define ETH_MACRXTXSR_EXCOL_Pos (5U)
7259#define ETH_MACRXTXSR_EXCOL_Msk (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */
7260#define ETH_MACRXTXSR_EXCOL ETH_MACRXTXSR_EXCOL_Msk /* Excessive Collisions */
7261#define ETH_MACRXTXSR_LCOL_Pos (4U)
7262#define ETH_MACRXTXSR_LCOL_Msk (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */
7263#define ETH_MACRXTXSR_LCOL ETH_MACRXTXSR_LCOL_Msk /* Late Collision */
7264#define ETH_MACRXTXSR_EXDEF_Pos (3U)
7265#define ETH_MACRXTXSR_EXDEF_Msk (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */
7266#define ETH_MACRXTXSR_EXDEF ETH_MACRXTXSR_EXDEF_Msk /* Excessive Deferral */
7267#define ETH_MACRXTXSR_LCARR_Pos (2U)
7268#define ETH_MACRXTXSR_LCARR_Msk (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */
7269#define ETH_MACRXTXSR_LCARR ETH_MACRXTXSR_LCARR_Msk /* Loss of Carrier */
7270#define ETH_MACRXTXSR_NCARR_Pos (1U)
7271#define ETH_MACRXTXSR_NCARR_Msk (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */
7272#define ETH_MACRXTXSR_NCARR ETH_MACRXTXSR_NCARR_Msk /* No Carrier */
7273#define ETH_MACRXTXSR_TJT_Pos (0U)
7274#define ETH_MACRXTXSR_TJT_Msk (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */
7275#define ETH_MACRXTXSR_TJT ETH_MACRXTXSR_TJT_Msk /* Transmit Jabber Timeout */
7276
7277/* Bit definition for Ethernet MAC PMT Control Status Register */
7278#define ETH_MACPCSR_RWKFILTRST_Pos (31U)
7279#define ETH_MACPCSR_RWKFILTRST_Msk (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */
7280#define ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
7281#define ETH_MACPCSR_RWKPTR_Pos (24U)
7282#define ETH_MACPCSR_RWKPTR_Msk (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */
7283#define ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk /* Remote Wake-up FIFO Pointer */
7284#define ETH_MACPCSR_RWKPFE_Pos (10U)
7285#define ETH_MACPCSR_RWKPFE_Msk (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */
7286#define ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk /* Remote Wake-up Packet Forwarding Enable */
7287#define ETH_MACPCSR_GLBLUCAST_Pos (9U)
7288#define ETH_MACPCSR_GLBLUCAST_Msk (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */
7289#define ETH_MACPCSR_GLBLUCAST ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
7290#define ETH_MACPCSR_RWKPRCVD_Pos (6U)
7291#define ETH_MACPCSR_RWKPRCVD_Msk (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */
7292#define ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
7293#define ETH_MACPCSR_MGKPRCVD_Pos (5U)
7294#define ETH_MACPCSR_MGKPRCVD_Msk (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */
7295#define ETH_MACPCSR_MGKPRCVD ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
7296#define ETH_MACPCSR_RWKPKTEN_Pos (2U)
7297#define ETH_MACPCSR_RWKPKTEN_Msk (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */
7298#define ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
7299#define ETH_MACPCSR_MGKPKTEN_Pos (1U)
7300#define ETH_MACPCSR_MGKPKTEN_Msk (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */
7301#define ETH_MACPCSR_MGKPKTEN ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
7302#define ETH_MACPCSR_PWRDWN_Pos (0U)
7303#define ETH_MACPCSR_PWRDWN_Msk (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */
7304#define ETH_MACPCSR_PWRDWN ETH_MACPCSR_PWRDWN_Msk /* Power Down */
7305
7306/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */
7307#define ETH_MACRWUPFR_D_Pos (0U)
7308#define ETH_MACRWUPFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */
7309#define ETH_MACRWUPFR_D ETH_MACRWUPFR_D_Msk /* Wake-up Packet filter register data */
7310
7311/* Bit definition for Ethernet MAC LPI Control Status Register */
7312#define ETH_MACLCSR_LPITCSE_Pos (21U)
7313#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */
7314#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */
7315#define ETH_MACLCSR_LPITE_Pos (20U)
7316#define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */
7317#define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /* LPI Timer Enable */
7318#define ETH_MACLCSR_LPITXA_Pos (19U)
7319#define ETH_MACLCSR_LPITXA_Msk (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */
7320#define ETH_MACLCSR_LPITXA ETH_MACLCSR_LPITXA_Msk /* LPI Tx Automate */
7321#define ETH_MACLCSR_PLS_Pos (17U)
7322#define ETH_MACLCSR_PLS_Msk (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */
7323#define ETH_MACLCSR_PLS ETH_MACLCSR_PLS_Msk /* PHY Link Status */
7324#define ETH_MACLCSR_LPIEN_Pos (16U)
7325#define ETH_MACLCSR_LPIEN_Msk (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */
7326#define ETH_MACLCSR_LPIEN ETH_MACLCSR_LPIEN_Msk /* LPI Enable */
7327#define ETH_MACLCSR_RLPIST_Pos (9U)
7328#define ETH_MACLCSR_RLPIST_Msk (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */
7329#define ETH_MACLCSR_RLPIST ETH_MACLCSR_RLPIST_Msk /* Receive LPI State */
7330#define ETH_MACLCSR_TLPIST_Pos (8U)
7331#define ETH_MACLCSR_TLPIST_Msk (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */
7332#define ETH_MACLCSR_TLPIST ETH_MACLCSR_TLPIST_Msk /* Transmit LPI State */
7333#define ETH_MACLCSR_RLPIEX_Pos (3U)
7334#define ETH_MACLCSR_RLPIEX_Msk (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */
7335#define ETH_MACLCSR_RLPIEX ETH_MACLCSR_RLPIEX_Msk /* Receive LPI Exit */
7336#define ETH_MACLCSR_RLPIEN_Pos (2U)
7337#define ETH_MACLCSR_RLPIEN_Msk (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */
7338#define ETH_MACLCSR_RLPIEN ETH_MACLCSR_RLPIEN_Msk /* Receive LPI Entry */
7339#define ETH_MACLCSR_TLPIEX_Pos (1U)
7340#define ETH_MACLCSR_TLPIEX_Msk (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */
7341#define ETH_MACLCSR_TLPIEX ETH_MACLCSR_TLPIEX_Msk /* Transmit LPI Exit */
7342#define ETH_MACLCSR_TLPIEN_Pos (0U)
7343#define ETH_MACLCSR_TLPIEN_Msk (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */
7344#define ETH_MACLCSR_TLPIEN ETH_MACLCSR_TLPIEN_Msk /* Transmit LPI Entry */
7345
7346/* Bit definition for Ethernet MAC LPI Timers Control Register */
7347#define ETH_MACLTCR_LST_Pos (16U)
7348#define ETH_MACLTCR_LST_Msk (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */
7349#define ETH_MACLTCR_LST ETH_MACLTCR_LST_Msk /* LPI LS TIMER */
7350#define ETH_MACLTCR_TWT_Pos (0U)
7351#define ETH_MACLTCR_TWT_Msk (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */
7352#define ETH_MACLTCR_TWT ETH_MACLTCR_TWT_Msk /* LPI TW TIMER */
7353
7354/* Bit definition for Ethernet MAC LPI Entry Timer Register */
7355#define ETH_MACLETR_LPIET_Pos (0U)
7356#define ETH_MACLETR_LPIET_Msk (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */
7357#define ETH_MACLETR_LPIET ETH_MACLETR_LPIET_Msk /* LPI Entry Timer */
7358
7359/* Bit definition for Ethernet MAC 1US Tic Counter Register */
7360#define ETH_MAC1USTCR_TIC1USCNTR_Pos (0U)
7361#define ETH_MAC1USTCR_TIC1USCNTR_Msk (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */
7362#define ETH_MAC1USTCR_TIC1USCNTR ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
7363
7364/* Bit definition for Ethernet MAC Version Register */
7365#define ETH_MACVR_USERVER_Pos (8U)
7366#define ETH_MACVR_USERVER_Msk (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */
7367#define ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk /* User-defined Version */
7368#define ETH_MACVR_SNPSVER_Pos (0U)
7369#define ETH_MACVR_SNPSVER_Msk (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */
7370#define ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk /* Synopsys-defined Version */
7371
7372/* Bit definition for Ethernet MAC Debug Register */
7373#define ETH_MACDR_TFCSTS_Pos (17U)
7374#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
7375#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
7376#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
7377#define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
7378#define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
7379#define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
7380#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos (18U)
7381#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */
7382#define ETH_MACDR_TFCSTS_GENERATEPCP ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
7383#define ETH_MACDR_TFCSTS_TRASFERIP_Pos (17U)
7384#define ETH_MACDR_TFCSTS_TRASFERIP_Msk (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */
7385#define ETH_MACDR_TFCSTS_TRASFERIP ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
7386#define ETH_MACDR_TPESTS_Pos (16U)
7387#define ETH_MACDR_TPESTS_Msk (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */
7388#define ETH_MACDR_TPESTS ETH_MACDR_TPESTS_Msk /* MAC Receive Packet Controller FIFO Status */
7389#define ETH_MACDR_RFCFCSTS_Pos (1U)
7390#define ETH_MACDR_RFCFCSTS_Msk (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */
7391#define ETH_MACDR_RFCFCSTS ETH_MACDR_RFCFCSTS_Msk /* MAC MII Transmit Protocol Engine Status */
7392#define ETH_MACDR_RPESTS_Pos (0U)
7393#define ETH_MACDR_RPESTS_Msk (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */
7394#define ETH_MACDR_RPESTS ETH_MACDR_RPESTS_Msk /* MAC MII Receive Protocol Engine Status */
7395
7396/* Bit definition for Ethernet MAC HW Feature0 Register */
7397#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
7398#define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
7399#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
7400#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */
7401#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
7402#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
7403#define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
7404#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos (28U)
7405#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */
7406#define ETH_MACHWF0R_ACTPHYSEL_REVMII ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */
7407#define ETH_MACHWF0R_SAVLANINS_Pos (27U)
7408#define ETH_MACHWF0R_SAVLANINS_Msk (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */
7409#define ETH_MACHWF0R_SAVLANINS ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
7410#define ETH_MACHWF0R_TSSTSSEL_Pos (25U)
7411#define ETH_MACHWF0R_TSSTSSEL_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */
7412#define ETH_MACHWF0R_TSSTSSEL ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
7413#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos (25U)
7414#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */
7415#define ETH_MACHWF0R_TSSTSSEL_INTERNAL ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
7416#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos (26U)
7417#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */
7418#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
7419#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos (25U)
7420#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */
7421#define ETH_MACHWF0R_TSSTSSEL_BOTH ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
7422#define ETH_MACHWF0R_MACADR64SEL_Pos (24U)
7423#define ETH_MACHWF0R_MACADR64SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */
7424#define ETH_MACHWF0R_MACADR64SEL ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
7425#define ETH_MACHWF0R_MACADR32SEL_Pos (23U)
7426#define ETH_MACHWF0R_MACADR32SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */
7427#define ETH_MACHWF0R_MACADR32SEL ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
7428#define ETH_MACHWF0R_ADDMACADRSEL_Pos (18U)
7429#define ETH_MACHWF0R_ADDMACADRSEL_Msk (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */
7430#define ETH_MACHWF0R_ADDMACADRSEL ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
7431#define ETH_MACHWF0R_RXCOESEL_Pos (16U)
7432#define ETH_MACHWF0R_RXCOESEL_Msk (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */
7433#define ETH_MACHWF0R_RXCOESEL ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
7434#define ETH_MACHWF0R_TXCOESEL_Pos (14U)
7435#define ETH_MACHWF0R_TXCOESEL_Msk (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */
7436#define ETH_MACHWF0R_TXCOESEL ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
7437#define ETH_MACHWF0R_EEESEL_Pos (13U)
7438#define ETH_MACHWF0R_EEESEL_Msk (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */
7439#define ETH_MACHWF0R_EEESEL ETH_MACHWF0R_EEESEL_Msk /* Energy Efficient Ethernet Enabled */
7440#define ETH_MACHWF0R_TSSEL_Pos (12U)
7441#define ETH_MACHWF0R_TSSEL_Msk (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */
7442#define ETH_MACHWF0R_TSSEL ETH_MACHWF0R_TSSEL_Msk /* IEEE 1588-2008 Timestamp Enabled */
7443#define ETH_MACHWF0R_ARPOFFSEL_Pos (9U)
7444#define ETH_MACHWF0R_ARPOFFSEL_Msk (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */
7445#define ETH_MACHWF0R_ARPOFFSEL ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
7446#define ETH_MACHWF0R_MMCSEL_Pos (8U)
7447#define ETH_MACHWF0R_MMCSEL_Msk (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */
7448#define ETH_MACHWF0R_MMCSEL ETH_MACHWF0R_MMCSEL_Msk /* RMON Module Enable */
7449#define ETH_MACHWF0R_MGKSEL_Pos (7U)
7450#define ETH_MACHWF0R_MGKSEL_Msk (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */
7451#define ETH_MACHWF0R_MGKSEL ETH_MACHWF0R_MGKSEL_Msk /* PMT Magic Packet Enable */
7452#define ETH_MACHWF0R_RWKSEL_Pos (6U)
7453#define ETH_MACHWF0R_RWKSEL_Msk (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */
7454#define ETH_MACHWF0R_RWKSEL ETH_MACHWF0R_RWKSEL_Msk /* PMT Remote Wake-up Packet Enable */
7455#define ETH_MACHWF0R_SMASEL_Pos (5U)
7456#define ETH_MACHWF0R_SMASEL_Msk (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */
7457#define ETH_MACHWF0R_SMASEL ETH_MACHWF0R_SMASEL_Msk /* SMA (MDIO) Interface */
7458#define ETH_MACHWF0R_VLHASH_Pos (4U)
7459#define ETH_MACHWF0R_VLHASH_Msk (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */
7460#define ETH_MACHWF0R_VLHASH ETH_MACHWF0R_VLHASH_Msk /* VLAN Hash Filter Selected */
7461#define ETH_MACHWF0R_PCSSEL_Pos (3U)
7462#define ETH_MACHWF0R_PCSSEL_Msk (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */
7463#define ETH_MACHWF0R_PCSSEL ETH_MACHWF0R_PCSSEL_Msk /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
7464#define ETH_MACHWF0R_HDSEL_Pos (2U)
7465#define ETH_MACHWF0R_HDSEL_Msk (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */
7466#define ETH_MACHWF0R_HDSEL ETH_MACHWF0R_HDSEL_Msk /* Half-duplex Support */
7467#define ETH_MACHWF0R_GMIISEL_Pos (1U)
7468#define ETH_MACHWF0R_GMIISEL_Msk (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */
7469#define ETH_MACHWF0R_GMIISEL ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
7470#define ETH_MACHWF0R_MIISEL_Pos (0U)
7471#define ETH_MACHWF0R_MIISEL_Msk (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */
7472#define ETH_MACHWF0R_MIISEL ETH_MACHWF0R_MIISEL_Msk /* 10 or 100 Mbps Support */
7473
7474/* Bit definition for Ethernet MAC HW Feature1 Register */
7475#define ETH_MACHWF1R_L3L4FNUM_Pos (27U)
7476#define ETH_MACHWF1R_L3L4FNUM_Msk (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */
7477#define ETH_MACHWF1R_L3L4FNUM ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
7478#define ETH_MACHWF1R_HASHTBLSZ_Pos (24U)
7479#define ETH_MACHWF1R_HASHTBLSZ_Msk (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */
7480#define ETH_MACHWF1R_HASHTBLSZ ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
7481#define ETH_MACHWF1R_AVSEL_Pos (20U)
7482#define ETH_MACHWF1R_AVSEL_Msk (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */
7483#define ETH_MACHWF1R_AVSEL ETH_MACHWF1R_AVSEL_Msk /* AV Feature Enabled */
7484#define ETH_MACHWF1R_DBGMEMA_Pos (19U)
7485#define ETH_MACHWF1R_DBGMEMA_Msk (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */
7486#define ETH_MACHWF1R_DBGMEMA ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
7487#define ETH_MACHWF1R_TSOEN_Pos (18U)
7488#define ETH_MACHWF1R_TSOEN_Msk (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */
7489#define ETH_MACHWF1R_TSOEN ETH_MACHWF1R_TSOEN_Msk /* TCP Segmentation Offload Enable */
7490#define ETH_MACHWF1R_SPHEN_Pos (17U)
7491#define ETH_MACHWF1R_SPHEN_Msk (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */
7492#define ETH_MACHWF1R_SPHEN ETH_MACHWF1R_SPHEN_Msk /* Split Header Feature Enable */
7493#define ETH_MACHWF1R_DCBEN_Pos (16U)
7494#define ETH_MACHWF1R_DCBEN_Msk (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */
7495#define ETH_MACHWF1R_DCBEN ETH_MACHWF1R_DCBEN_Msk /* DCB Feature Enable */
7496#define ETH_MACHWF1R_ADDR64_Pos (14U)
7497#define ETH_MACHWF1R_ADDR64_Msk (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */
7498#define ETH_MACHWF1R_ADDR64 ETH_MACHWF1R_ADDR64_Msk /* Address Width */
7499#define ETH_MACHWF1R_ADDR64_32 (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */
7500#define ETH_MACHWF1R_ADDR64_40 (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */
7501#define ETH_MACHWF1R_ADDR64_48 (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */
7502#define ETH_MACHWF1R_ADVTHWORD_Pos (13U)
7503#define ETH_MACHWF1R_ADVTHWORD_Msk (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */
7504#define ETH_MACHWF1R_ADVTHWORD ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
7505#define ETH_MACHWF1R_PTOEN_Pos (12U)
7506#define ETH_MACHWF1R_PTOEN_Msk (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */
7507#define ETH_MACHWF1R_PTOEN ETH_MACHWF1R_PTOEN_Msk /* PTP Offload Enable */
7508#define ETH_MACHWF1R_OSTEN_Pos (11U)
7509#define ETH_MACHWF1R_OSTEN_Msk (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */
7510#define ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk /* One-Step Timestamping Enable */
7511#define ETH_MACHWF1R_TXFIFOSIZE_Pos (6U)
7512#define ETH_MACHWF1R_TXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */
7513#define ETH_MACHWF1R_TXFIFOSIZE ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
7514#define ETH_MACHWF1R_RXFIFOSIZE_Pos (0U)
7515#define ETH_MACHWF1R_RXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */
7516#define ETH_MACHWF1R_RXFIFOSIZE ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
7517
7518/* Bit definition for Ethernet MAC HW Feature2 Register */
7519#define ETH_MACHWF2R_AUXSNAPNUM_Pos (28U)