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diff --git a/lib/chibios/os/common/ext/ST/STM32H7xx/stm32h750xx.h b/lib/chibios/os/common/ext/ST/STM32H7xx/stm32h750xx.h
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1/**
2 ******************************************************************************
3 * @file stm32h750xx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32H750xx Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
16 * All rights reserved.</center></h2>
17 *
18 * This software component is licensed by ST under BSD 3-Clause license,
19 * the "License"; You may not use this file except in compliance with the
20 * License. You may obtain a copy of the License at:
21 * opensource.org/licenses/BSD-3-Clause
22 *
23 ******************************************************************************
24 */
25
26/** @addtogroup CMSIS_Device
27 * @{
28 */
29
30/** @addtogroup stm32h750xx
31 * @{
32 */
33
34#ifndef STM32H750xx_H
35#define STM32H750xx_H
36
37#ifdef __cplusplus
38 extern "C" {
39#endif /* __cplusplus */
40
41/** @addtogroup Peripheral_interrupt_number_definition
42 * @{
43 */
44
45/**
46 * @brief STM32H7XX Interrupt Number Definition, according to the selected device
47 * in @ref Library_configuration_section
48 */
49typedef enum
50{
51/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
52 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
53 HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
54 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
55 BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
56 UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
57 SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
58 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */
59 PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
60 SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
61/****** STM32 specific Interrupt Numbers **********************************************************************/
62 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
63 PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */
64 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
65 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
66 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
67 RCC_IRQn = 5, /*!< RCC global Interrupt */
68 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
69 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
70 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
71 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
72 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
73 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
74 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
75 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
76 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
77 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
78 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
79 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
80 ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */
81 FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */
82 FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */
83 FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */
84 FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */
85 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
86 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
87 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
88 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
89 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
90 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
91 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
92 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
93 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
94 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
95 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
96 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
97 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
98 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
99 USART1_IRQn = 37, /*!< USART1 global Interrupt */
100 USART2_IRQn = 38, /*!< USART2 global Interrupt */
101 USART3_IRQn = 39, /*!< USART3 global Interrupt */
102 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
103 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
104 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
105 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
106 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
107 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
108 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
109 FMC_IRQn = 48, /*!< FMC global Interrupt */
110 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
111 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
112 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
113 UART4_IRQn = 52, /*!< UART4 global Interrupt */
114 UART5_IRQn = 53, /*!< UART5 global Interrupt */
115 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
116 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
117 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
118 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
119 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
120 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
121 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
122 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
123 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
124 FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */
125 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
126 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
127 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
128 USART6_IRQn = 71, /*!< USART6 global interrupt */
129 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
130 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
131 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
132 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
133 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
134 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
135 DCMI_IRQn = 78, /*!< DCMI global interrupt */
136 CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
137 HASH_RNG_IRQn = 80, /*!< HASH and RNG global interrupt */
138 FPU_IRQn = 81, /*!< FPU global interrupt */
139 UART7_IRQn = 82, /*!< UART7 global interrupt */
140 UART8_IRQn = 83, /*!< UART8 global interrupt */
141 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
142 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
143 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
144 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
145 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
146 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
147 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
148 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
149 QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
150 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
151 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
152 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
153 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
154 SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
155 OTG_FS_EP1_OUT_IRQn = 98, /*!< USB OTG HS2 global interrupt */
156 OTG_FS_EP1_IN_IRQn = 99, /*!< USB OTG HS2 End Point 1 Out global interrupt */
157 OTG_FS_WKUP_IRQn = 100, /*!< USB OTG HS2 End Point 1 In global interrupt */
158 OTG_FS_IRQn = 101, /*!< USB OTG HS2 Wakeup through EXTI interrupt */
159 DMAMUX1_OVR_IRQn = 102, /*!<DMAMUX1 Overrun interrupt */
160 HRTIM1_Master_IRQn = 103, /*!< HRTIM Master Timer global Interrupts */
161 HRTIM1_TIMA_IRQn = 104, /*!< HRTIM Timer A global Interrupt */
162 HRTIM1_TIMB_IRQn = 105, /*!< HRTIM Timer B global Interrupt */
163 HRTIM1_TIMC_IRQn = 106, /*!< HRTIM Timer C global Interrupt */
164 HRTIM1_TIMD_IRQn = 107, /*!< HRTIM Timer D global Interrupt */
165 HRTIM1_TIME_IRQn = 108, /*!< HRTIM Timer E global Interrupt */
166 HRTIM1_FLT_IRQn = 109, /*!< HRTIM Fault global Interrupt */
167 DFSDM1_FLT0_IRQn = 110, /*!<DFSDM Filter1 Interrupt */
168 DFSDM1_FLT1_IRQn = 111, /*!<DFSDM Filter2 Interrupt */
169 DFSDM1_FLT2_IRQn = 112, /*!<DFSDM Filter3 Interrupt */
170 DFSDM1_FLT3_IRQn = 113, /*!<DFSDM Filter4 Interrupt */
171 SAI3_IRQn = 114, /*!< SAI3 global Interrupt */
172 SWPMI1_IRQn = 115, /*!< Serial Wire Interface 1 global interrupt */
173 TIM15_IRQn = 116, /*!< TIM15 global Interrupt */
174 TIM16_IRQn = 117, /*!< TIM16 global Interrupt */
175 TIM17_IRQn = 118, /*!< TIM17 global Interrupt */
176 MDIOS_WKUP_IRQn = 119, /*!< MDIOS Wakeup Interrupt */
177 MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */
178 JPEG_IRQn = 121, /*!< JPEG global Interrupt */
179 MDMA_IRQn = 122, /*!< MDMA global Interrupt */
180 SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */
181 HSEM1_IRQn = 125, /*!< HSEM1 global Interrupt */
182 ADC3_IRQn = 127, /*!< ADC3 global Interrupt */
183 DMAMUX2_OVR_IRQn = 128, /*!<DMAMUX2 Overrun interrupt */
184 BDMA_Channel0_IRQn = 129, /*!< BDMA Channel 0 global Interrupt */
185 BDMA_Channel1_IRQn = 130, /*!< BDMA Channel 1 global Interrupt */
186 BDMA_Channel2_IRQn = 131, /*!< BDMA Channel 2 global Interrupt */
187 BDMA_Channel3_IRQn = 132, /*!< BDMA Channel 3 global Interrupt */
188 BDMA_Channel4_IRQn = 133, /*!< BDMA Channel 4 global Interrupt */
189 BDMA_Channel5_IRQn = 134, /*!< BDMA Channel 5 global Interrupt */
190 BDMA_Channel6_IRQn = 135, /*!< BDMA Channel 6 global Interrupt */
191 BDMA_Channel7_IRQn = 136, /*!< BDMA Channel 7 global Interrupt */
192 COMP_IRQn = 137 , /*!< COMP global Interrupt */
193 LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */
194 LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */
195 LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */
196 LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */
197 LPUART1_IRQn = 142, /*!< LP UART1 interrupt */
198 CRS_IRQn = 144, /*!< Clock Recovery Global Interrupt */
199 ECC_IRQn = 145, /*!< ECC diagnostic Global Interrupt */
200 SAI4_IRQn = 146, /*!< SAI4 global interrupt */
201 WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */
202} IRQn_Type;
203
204/**
205 * @}
206 */
207
208/** @addtogroup Configuration_section_for_CMSIS
209 * @{
210 */
211
212
213
214
215/**
216 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
217 */
218#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
219#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
220#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
221#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
222#define __FPU_PRESENT 1 /*!< FPU present */
223#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
224#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
225#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
226
227/**
228 * @}
229 */
230
231
232
233
234#include "system_stm32h7xx.h"
235#include <stdint.h>
236
237/** @addtogroup Peripheral_registers_structures
238 * @{
239 */
240
241/**
242 * @brief Analog to Digital Converter
243 */
244
245typedef struct
246{
247 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
248 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
249 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
250 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
251 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
252 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
253 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
254 __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */
255 __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
256 __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
257 uint32_t RESERVED1; /*!< Reserved, 0x028 */
258 uint32_t RESERVED2; /*!< Reserved, 0x02C */
259 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
260 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
261 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
262 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
263 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
264 uint32_t RESERVED3; /*!< Reserved, 0x044 */
265 uint32_t RESERVED4; /*!< Reserved, 0x048 */
266 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
267 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
268 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
269 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
270 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
271 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
272 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
273 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
274 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
275 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
276 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
277 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
278 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
279 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
280 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
281 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
282 __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */
283 __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */
284 __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */
285 __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */
286 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */
287 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */
288 __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */
289} ADC_TypeDef;
290
291
292typedef struct
293{
294__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
295uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
296__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
297__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
298__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
299
300} ADC_Common_TypeDef;
301
302
303/**
304 * @brief VREFBUF
305 */
306
307typedef struct
308{
309 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
310 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
311} VREFBUF_TypeDef;
312
313
314/**
315 * @brief FD Controller Area Network
316 */
317
318typedef struct
319{
320 __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
321 __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
322 __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */
323 __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
324 __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
325 __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
326 __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
327 __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
328 __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
329 __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
330 __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
331 __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
332 __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
333 __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
334 __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
335 __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
336 __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */
337 __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
338 __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
339 __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
340 __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
341 __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
342 __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
343 __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */
344 __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */
345 __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */
346 __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */
347 __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */
348 __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */
349 __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */
350 __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */
351 __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */
352 __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */
353 __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */
354 __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */
355 __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */
356 __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */
357 __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */
358 __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
359 __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
360 __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */
361 __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */
362 __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */
363 __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */
364 __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */
365 __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */
366 __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */
367 __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
368 __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */
369 __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */
370 __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */
371 __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */
372 __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */
373} FDCAN_GlobalTypeDef;
374
375/**
376 * @brief TTFD Controller Area Network
377 */
378
379typedef struct
380{
381 __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */
382 __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */
383 __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */
384 __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */
385 __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */
386 __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */
387 __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */
388 __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */
389 __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */
390 __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */
391 __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */
392 __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */
393 __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */
394 __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */
395 __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */
396 __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */
397 __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */
398 __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */
399 __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */
400} TTCAN_TypeDef;
401
402/**
403 * @brief FD Controller Area Network
404 */
405
406typedef struct
407{
408 __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
409 __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */
410 __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */
411 __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */
412 __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */
413 __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */
414} FDCAN_ClockCalibrationUnit_TypeDef;
415
416
417/**
418 * @brief Consumer Electronics Control
419 */
420
421typedef struct
422{
423 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
424 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
425 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
426 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
427 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
428 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
429}CEC_TypeDef;
430
431/**
432 * @brief CRC calculation unit
433 */
434
435typedef struct
436{
437 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
438 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
439 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
440 uint32_t RESERVED2; /*!< Reserved, 0x0C */
441 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
442 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
443} CRC_TypeDef;
444
445
446/**
447 * @brief Clock Recovery System
448 */
449typedef struct
450{
451__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
452__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
453__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
454__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
455} CRS_TypeDef;
456
457
458/**
459 * @brief Digital to Analog Converter
460 */
461
462typedef struct
463{
464 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
465 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
466 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
467 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
468 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
469 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
470 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
471 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
472 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
473 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
474 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
475 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
476 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
477 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
478 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
479 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
480 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
481 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
482 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
483 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
484} DAC_TypeDef;
485
486/**
487 * @brief DFSDM module registers
488 */
489typedef struct
490{
491 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
492 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
493 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
494 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
495 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
496 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
497 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
498 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
499 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
500 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
501 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
502 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
503 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
504 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
505 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
506} DFSDM_Filter_TypeDef;
507
508/**
509 * @brief DFSDM channel configuration registers
510 */
511typedef struct
512{
513 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
514 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
515 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
516 short circuit detector register, Address offset: 0x08 */
517 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
518 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
519} DFSDM_Channel_TypeDef;
520
521/**
522 * @brief Debug MCU
523 */
524typedef struct
525{
526 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
527 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
528 uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */
529 __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */
530 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x38 */
531 __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */
532 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x40 */
533 __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */
534 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x48 */
535 __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */
536 uint32_t RESERVED8; /*!< Reserved, Address offset: 0x50 */
537 __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */
538}DBGMCU_TypeDef;
539/**
540 * @brief DCMI
541 */
542
543typedef struct
544{
545 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
546 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
547 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
548 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
549 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
550 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
551 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
552 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
553 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
554 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
555 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
556} DCMI_TypeDef;
557
558/**
559 * @brief DMA Controller
560 */
561
562typedef struct
563{
564 __IO uint32_t CR; /*!< DMA stream x configuration register */
565 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
566 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
567 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
568 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
569 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
570} DMA_Stream_TypeDef;
571
572typedef struct
573{
574 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
575 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
576 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
577 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
578} DMA_TypeDef;
579
580typedef struct
581{
582 __IO uint32_t CCR; /*!< DMA channel x configuration register */
583 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
584 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
585 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */
586 __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */
587} BDMA_Channel_TypeDef;
588
589typedef struct
590{
591 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
592 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
593} BDMA_TypeDef;
594
595typedef struct
596{
597 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */
598}DMAMUX_Channel_TypeDef;
599
600typedef struct
601{
602 __IO uint32_t CSR; /*!< DMA Channel Status Register */
603 __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */
604}DMAMUX_ChannelStatus_TypeDef;
605
606typedef struct
607{
608 __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */
609}DMAMUX_RequestGen_TypeDef;
610
611typedef struct
612{
613 __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */
614 __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */
615}DMAMUX_RequestGenStatus_TypeDef;
616
617/**
618 * @brief MDMA Controller
619 */
620typedef struct
621{
622 __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */
623}MDMA_TypeDef;
624
625typedef struct
626{
627 __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */
628 __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */
629 __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */
630 __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */
631 __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */
632 __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */
633 __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */
634 __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */
635 __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
636 __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
637 __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
638 uint32_t RESERVED0; /*!< Reserved, 0x68 */
639 __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
640 __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
641}MDMA_Channel_TypeDef;
642
643/**
644 * @brief DMA2D Controller
645 */
646
647typedef struct
648{
649 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
650 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
651 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
652 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
653 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
654 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
655 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
656 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
657 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
658 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
659 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
660 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
661 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
662 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
663 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
664 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
665 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
666 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
667 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
668 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
669 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
670 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
671 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
672} DMA2D_TypeDef;
673
674
675/**
676 * @brief Ethernet MAC
677 */
678typedef struct
679{
680 __IO uint32_t MACCR;
681 __IO uint32_t MACECR;
682 __IO uint32_t MACPFR;
683 __IO uint32_t MACWTR;
684 __IO uint32_t MACHT0R;
685 __IO uint32_t MACHT1R;
686 uint32_t RESERVED1[14];
687 __IO uint32_t MACVTR;
688 uint32_t RESERVED2;
689 __IO uint32_t MACVHTR;
690 uint32_t RESERVED3;
691 __IO uint32_t MACVIR;
692 __IO uint32_t MACIVIR;
693 uint32_t RESERVED4[2];
694 __IO uint32_t MACTFCR;
695 uint32_t RESERVED5[7];
696 __IO uint32_t MACRFCR;
697 uint32_t RESERVED6[7];
698 __IO uint32_t MACISR;
699 __IO uint32_t MACIER;
700 __IO uint32_t MACRXTXSR;
701 uint32_t RESERVED7;
702 __IO uint32_t MACPCSR;
703 __IO uint32_t MACRWKPFR;
704 uint32_t RESERVED8[2];
705 __IO uint32_t MACLCSR;
706 __IO uint32_t MACLTCR;
707 __IO uint32_t MACLETR;
708 __IO uint32_t MAC1USTCR;
709 uint32_t RESERVED9[12];
710 __IO uint32_t MACVR;
711 __IO uint32_t MACDR;
712 uint32_t RESERVED10;
713 __IO uint32_t MACHWF0R;
714 __IO uint32_t MACHWF1R;
715 __IO uint32_t MACHWF2R;
716 uint32_t RESERVED11[54];
717 __IO uint32_t MACMDIOAR;
718 __IO uint32_t MACMDIODR;
719 uint32_t RESERVED12[2];
720 __IO uint32_t MACARPAR;
721 uint32_t RESERVED13[59];
722 __IO uint32_t MACA0HR;
723 __IO uint32_t MACA0LR;
724 __IO uint32_t MACA1HR;
725 __IO uint32_t MACA1LR;
726 __IO uint32_t MACA2HR;
727 __IO uint32_t MACA2LR;
728 __IO uint32_t MACA3HR;
729 __IO uint32_t MACA3LR;
730 uint32_t RESERVED14[248];
731 __IO uint32_t MMCCR;
732 __IO uint32_t MMCRIR;
733 __IO uint32_t MMCTIR;
734 __IO uint32_t MMCRIMR;
735 __IO uint32_t MMCTIMR;
736 uint32_t RESERVED15[14];
737 __IO uint32_t MMCTSCGPR;
738 __IO uint32_t MMCTMCGPR;
739 uint32_t RESERVED16[5];
740 __IO uint32_t MMCTPCGR;
741 uint32_t RESERVED17[10];
742 __IO uint32_t MMCRCRCEPR;
743 __IO uint32_t MMCRAEPR;
744 uint32_t RESERVED18[10];
745 __IO uint32_t MMCRUPGR;
746 uint32_t RESERVED19[9];
747 __IO uint32_t MMCTLPIMSTR;
748 __IO uint32_t MMCTLPITCR;
749 __IO uint32_t MMCRLPIMSTR;
750 __IO uint32_t MMCRLPITCR;
751 uint32_t RESERVED20[65];
752 __IO uint32_t MACL3L4C0R;
753 __IO uint32_t MACL4A0R;
754 uint32_t RESERVED21[2];
755 __IO uint32_t MACL3A0R0R;
756 __IO uint32_t MACL3A1R0R;
757 __IO uint32_t MACL3A2R0R;
758 __IO uint32_t MACL3A3R0R;
759 uint32_t RESERVED22[4];
760 __IO uint32_t MACL3L4C1R;
761 __IO uint32_t MACL4A1R;
762 uint32_t RESERVED23[2];
763 __IO uint32_t MACL3A0R1R;
764 __IO uint32_t MACL3A1R1R;
765 __IO uint32_t MACL3A2R1R;
766 __IO uint32_t MACL3A3R1R;
767 uint32_t RESERVED24[108];
768 __IO uint32_t MACTSCR;
769 __IO uint32_t MACSSIR;
770 __IO uint32_t MACSTSR;
771 __IO uint32_t MACSTNR;
772 __IO uint32_t MACSTSUR;
773 __IO uint32_t MACSTNUR;
774 __IO uint32_t MACTSAR;
775 uint32_t RESERVED25;
776 __IO uint32_t MACTSSR;
777 uint32_t RESERVED26[3];
778 __IO uint32_t MACTTSSNR;
779 __IO uint32_t MACTTSSSR;
780 uint32_t RESERVED27[2];
781 __IO uint32_t MACACR;
782 uint32_t RESERVED28;
783 __IO uint32_t MACATSNR;
784 __IO uint32_t MACATSSR;
785 __IO uint32_t MACTSIACR;
786 __IO uint32_t MACTSEACR;
787 __IO uint32_t MACTSICNR;
788 __IO uint32_t MACTSECNR;
789 uint32_t RESERVED29[4];
790 __IO uint32_t MACPPSCR;
791 uint32_t RESERVED30[3];
792 __IO uint32_t MACPPSTTSR;
793 __IO uint32_t MACPPSTTNR;
794 __IO uint32_t MACPPSIR;
795 __IO uint32_t MACPPSWR;
796 uint32_t RESERVED31[12];
797 __IO uint32_t MACPOCR;
798 __IO uint32_t MACSPI0R;
799 __IO uint32_t MACSPI1R;
800 __IO uint32_t MACSPI2R;
801 __IO uint32_t MACLMIR;
802 uint32_t RESERVED32[11];
803 __IO uint32_t MTLOMR;
804 uint32_t RESERVED33[7];
805 __IO uint32_t MTLISR;
806 uint32_t RESERVED34[55];
807 __IO uint32_t MTLTQOMR;
808 __IO uint32_t MTLTQUR;
809 __IO uint32_t MTLTQDR;
810 uint32_t RESERVED35[8];
811 __IO uint32_t MTLQICSR;
812 __IO uint32_t MTLRQOMR;
813 __IO uint32_t MTLRQMPOCR;
814 __IO uint32_t MTLRQDR;
815 uint32_t RESERVED36[177];
816 __IO uint32_t DMAMR;
817 __IO uint32_t DMASBMR;
818 __IO uint32_t DMAISR;
819 __IO uint32_t DMADSR;
820 uint32_t RESERVED37[60];
821 __IO uint32_t DMACCR;
822 __IO uint32_t DMACTCR;
823 __IO uint32_t DMACRCR;
824 uint32_t RESERVED38[2];
825 __IO uint32_t DMACTDLAR;
826 uint32_t RESERVED39;
827 __IO uint32_t DMACRDLAR;
828 __IO uint32_t DMACTDTPR;
829 uint32_t RESERVED40;
830 __IO uint32_t DMACRDTPR;
831 __IO uint32_t DMACTDRLR;
832 __IO uint32_t DMACRDRLR;
833 __IO uint32_t DMACIER;
834 __IO uint32_t DMACRIWTR;
835__IO uint32_t DMACSFCSR;
836 uint32_t RESERVED41;
837 __IO uint32_t DMACCATDR;
838 uint32_t RESERVED42;
839 __IO uint32_t DMACCARDR;
840 uint32_t RESERVED43;
841 __IO uint32_t DMACCATBR;
842 uint32_t RESERVED44;
843 __IO uint32_t DMACCARBR;
844 __IO uint32_t DMACSR;
845uint32_t RESERVED45[2];
846__IO uint32_t DMACMFCR;
847}ETH_TypeDef;
848/**
849 * @brief External Interrupt/Event Controller
850 */
851
852typedef struct
853{
854__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */
855__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */
856__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */
857__IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */
858__IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */
859__IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */
860uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */
861__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */
862__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */
863__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */
864__IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */
865__IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */
866__IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */
867uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */
868__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */
869__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */
870__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */
871__IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */
872__IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */
873__IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */
874uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */
875__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */
876__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */
877__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */
878uint32_t RESERVED4; /*!< Reserved, 0x8C */
879__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */
880__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */
881__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */
882uint32_t RESERVED5; /*!< Reserved, 0x9C */
883__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */
884__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */
885__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
886}EXTI_TypeDef;
887
888typedef struct
889{
890__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
891__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */
892__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */
893uint32_t RESERVED1; /*!< Reserved, 0x0C */
894__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */
895__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */
896__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */
897uint32_t RESERVED2; /*!< Reserved, 0x1C */
898__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
899__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */
900__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */
901}EXTI_Core_TypeDef;
902
903
904/**
905 * @brief FLASH Registers
906 */
907
908typedef struct
909{
910 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
911 __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */
912 __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */
913 __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */
914 __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */
915 __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */
916 __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */
917 __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */
918 __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */
919 __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */
920 __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */
921 __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */
922 __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */
923 __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */
924 __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */
925 __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */
926 __IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */
927 __IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */
928 uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */
929 __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */
930 __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */
931 __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */
932 __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */
933 __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */
934 uint32_t RESERVED1[40]; /*!< Reserved, 0x64 to 0x100 */
935 __IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */
936 uint32_t RESERVED2; /*!< Reserved, 0x108 */
937 __IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */
938 __IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */
939 __IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */
940 uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */
941 __IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */
942 __IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */
943 __IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */
944 __IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */
945 __IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */
946 __IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */
947 uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */
948 __IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */
949 __IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */
950 __IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */
951 __IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */
952 __IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */
953} FLASH_TypeDef;
954
955/**
956 * @brief Flexible Memory Controller
957 */
958
959typedef struct
960{
961 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
962} FMC_Bank1_TypeDef;
963
964/**
965 * @brief Flexible Memory Controller Bank1E
966 */
967
968typedef struct
969{
970 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
971} FMC_Bank1E_TypeDef;
972
973/**
974 * @brief Flexible Memory Controller Bank2
975 */
976
977typedef struct
978{
979 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
980 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
981 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
982 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
983 uint32_t RESERVED0; /*!< Reserved, 0x70 */
984 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
985} FMC_Bank2_TypeDef;
986
987/**
988 * @brief Flexible Memory Controller Bank3
989 */
990
991typedef struct
992{
993 __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */
994 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
995 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
996 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
997 uint32_t RESERVED; /*!< Reserved, 0x90 */
998 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
999} FMC_Bank3_TypeDef;
1000
1001/**
1002 * @brief Flexible Memory Controller Bank5 and 6
1003 */
1004
1005
1006typedef struct
1007{
1008 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
1009 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
1010 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
1011 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
1012 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
1013} FMC_Bank5_6_TypeDef;
1014
1015/**
1016 * @brief General Purpose I/O
1017 */
1018
1019typedef struct
1020{
1021 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
1022 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
1023 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
1024 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
1025 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
1026 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
1027 __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */
1028 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
1029 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
1030} GPIO_TypeDef;
1031
1032/**
1033 * @brief Operational Amplifier (OPAMP)
1034 */
1035
1036typedef struct
1037{
1038 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
1039 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
1040 __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
1041} OPAMP_TypeDef;
1042
1043/**
1044 * @brief System configuration controller
1045 */
1046
1047typedef struct
1048{
1049 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */
1050 __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
1051 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
1052 __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */
1053 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
1054 __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */
1055 __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */
1056 __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */
1057 __IO uint32_t PWRCR; /*!< PWR control register, Address offset: 0x2C */
1058 uint32_t RESERVED3[61]; /*!< Reserved, 0x30-0x120 */
1059 __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */
1060 uint32_t RESERVED4[118]; /*!< Reserved, 0x128-0x2FC */
1061 __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */
1062 __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */
1063 __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */
1064 __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */
1065 __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */
1066 __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */
1067 __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */
1068 __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */
1069 __IO uint32_t UR8; /*!< SYSCFG user register 8, Address offset: 0x320 */
1070 __IO uint32_t UR9; /*!< SYSCFG user register 9, Address offset: 0x324 */
1071 __IO uint32_t UR10; /*!< SYSCFG user register 10, Address offset: 0x328 */
1072 __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */
1073 __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */
1074 __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */
1075 __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */
1076 __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */
1077 __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */
1078 __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */
1079
1080} SYSCFG_TypeDef;
1081
1082/**
1083 * @brief Inter-integrated Circuit Interface
1084 */
1085
1086typedef struct
1087{
1088 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
1089 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
1090 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
1091 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
1092 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
1093 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
1094 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
1095 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
1096 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
1097 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
1098 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
1099} I2C_TypeDef;
1100
1101/**
1102 * @brief Independent WATCHDOG
1103 */
1104
1105typedef struct
1106{
1107 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
1108 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
1109 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
1110 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
1111 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
1112} IWDG_TypeDef;
1113
1114
1115/**
1116 * @brief JPEG Codec
1117 */
1118typedef struct
1119{
1120 __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
1121 __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
1122 __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
1123 __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
1124 __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
1125 __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
1126 __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
1127 __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
1128 uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
1129 __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
1130 __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
1131 __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
1132 uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
1133 __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
1134 __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
1135 uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
1136 __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
1137 __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
1138 __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
1139 __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
1140 __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
1141 __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
1142 __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
1143 __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
1144 uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
1145 __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
1146 __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
1147 __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
1148 __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
1149
1150} JPEG_TypeDef;
1151
1152/**
1153 * @brief LCD-TFT Display Controller
1154 */
1155
1156typedef struct
1157{
1158 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
1159 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
1160 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
1161 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
1162 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
1163 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
1164 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
1165 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
1166 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
1167 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
1168 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
1169 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
1170 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
1171 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
1172 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
1173 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
1174 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
1175} LTDC_TypeDef;
1176
1177/**
1178 * @brief LCD-TFT Display layer x Controller
1179 */
1180
1181typedef struct
1182{
1183 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
1184 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
1185 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
1186 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
1187 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
1188 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
1189 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
1190 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
1191 uint32_t RESERVED0[2]; /*!< Reserved */
1192 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
1193 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
1194 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
1195 uint32_t RESERVED1[3]; /*!< Reserved */
1196 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
1197
1198} LTDC_Layer_TypeDef;
1199
1200/**
1201 * @brief Power Control
1202 */
1203
1204typedef struct
1205{
1206 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
1207 __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */
1208 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
1209 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */
1210 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */
1211 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */
1212 __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */
1213 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
1214 __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */
1215 __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */
1216 __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
1217} PWR_TypeDef;
1218
1219/**
1220 * @brief Reset and Clock Control
1221 */
1222
1223typedef struct
1224{
1225 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
1226 __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */
1227 __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */
1228 __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */
1229 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */
1230 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
1231 __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */
1232 __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */
1233 __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */
1234 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
1235 __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */
1236 __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */
1237 __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */
1238 __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */
1239 __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */
1240 __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */
1241 __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */
1242 __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */
1243 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
1244 __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */
1245 __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */
1246 __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */
1247 __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */
1248 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */
1249 __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */
1250 __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */
1251 __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */
1252 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */
1253 __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */
1254 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
1255 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */
1256 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */
1257 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */
1258 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */
1259 __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */
1260 __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */
1261 __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */
1262 __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */
1263 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */
1264 __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */
1265 __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */
1266 uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */
1267 __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */
1268 uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */
1269 __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */
1270 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */
1271 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */
1272 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */
1273 __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */
1274 __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */
1275 __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */
1276 __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */
1277 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */
1278 __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */
1279 uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */
1280 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */
1281 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */
1282 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */
1283 __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */
1284 __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */
1285 __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */
1286 __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */
1287 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */
1288 __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */
1289 uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */
1290
1291} RCC_TypeDef;
1292
1293
1294/**
1295 * @brief Real-Time Clock
1296 */
1297typedef struct
1298{
1299 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
1300 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
1301 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
1302 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
1303 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
1304 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
1305 uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
1306 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
1307 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
1308 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
1309 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
1310 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
1311 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
1312 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
1313 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
1314 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
1315 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
1316 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
1317 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
1318 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
1319 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
1320 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
1321 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
1322 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
1323 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
1324 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
1325 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
1326 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
1327 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
1328 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
1329 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
1330 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
1331 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
1332 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
1333 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
1334 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
1335 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
1336 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
1337 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
1338 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
1339 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
1340 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
1341 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
1342 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
1343 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
1344 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
1345 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
1346 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
1347 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
1348 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
1349 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
1350 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
1351} RTC_TypeDef;
1352
1353/**
1354 * @brief Serial Audio Interface
1355 */
1356
1357typedef struct
1358{
1359 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
1360 uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
1361 __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
1362 __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
1363} SAI_TypeDef;
1364
1365typedef struct
1366{
1367 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
1368 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
1369 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
1370 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
1371 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
1372 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
1373 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
1374 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
1375} SAI_Block_TypeDef;
1376
1377/**
1378 * @brief SPDIF-RX Interface
1379 */
1380
1381typedef struct
1382{
1383 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
1384 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
1385 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
1386 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
1387 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
1388 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
1389 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
1390 uint32_t RESERVED2; /*!< Reserved, 0x1A */
1391} SPDIFRX_TypeDef;
1392
1393
1394/**
1395 * @brief Secure digital input/output Interface
1396 */
1397
1398typedef struct
1399{
1400 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
1401 __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
1402 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
1403 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
1404 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
1405 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
1406 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
1407 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
1408 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
1409 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
1410 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
1411 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
1412 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
1413 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
1414 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
1415 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
1416 __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
1417 uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
1418 __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
1419 __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
1420 __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
1421 __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
1422 uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
1423 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
1424 uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */
1425 __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */
1426} SDMMC_TypeDef;
1427
1428
1429/**
1430 * @brief Delay Block DLYB
1431 */
1432
1433typedef struct
1434{
1435 __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */
1436 __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */
1437} DLYB_TypeDef;
1438
1439/**
1440 * @brief HW Semaphore HSEM
1441 */
1442
1443typedef struct
1444{
1445 __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */
1446 __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */
1447 __IO uint32_t C1IER; /*!< HSEM Interrupt enable register , Address offset: 100h */
1448 __IO uint32_t C1ICR; /*!< HSEM Interrupt clear register , Address offset: 104h */
1449 __IO uint32_t C1ISR; /*!< HSEM Interrupt Status register , Address offset: 108h */
1450 __IO uint32_t C1MISR; /*!< HSEM Interrupt Masked Status register , Address offset: 10Ch */
1451 uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch */
1452 __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */
1453 __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */
1454
1455} HSEM_TypeDef;
1456
1457typedef struct
1458{
1459 __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */
1460 __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */
1461 __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */
1462 __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */
1463} HSEM_Common_TypeDef;
1464
1465/**
1466 * @brief Serial Peripheral Interface
1467 */
1468
1469typedef struct
1470{
1471 __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */
1472 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
1473 __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */
1474 __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */
1475 __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */
1476 __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */
1477 __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */
1478 uint32_t RESERVED0; /*!< Reserved, 0x1C */
1479 __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */
1480 uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */
1481 __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */
1482 uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
1483 __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */
1484 __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */
1485 __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */
1486 __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */
1487 __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */
1488
1489} SPI_TypeDef;
1490/**
1491 * @brief QUAD Serial Peripheral Interface
1492 */
1493
1494typedef struct
1495{
1496 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
1497 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
1498 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
1499 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
1500 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
1501 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
1502 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
1503 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
1504 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
1505 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
1506 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
1507 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
1508 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
1509} QUADSPI_TypeDef;
1510
1511/**
1512 * @brief TIM
1513 */
1514
1515typedef struct
1516{
1517 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
1518 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
1519 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
1520 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
1521 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
1522 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
1523 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
1524 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
1525 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
1526 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
1527 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
1528 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
1529 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
1530 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
1531 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
1532 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
1533 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
1534 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
1535 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
1536 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
1537 uint32_t RESERVED1; /*!< Reserved, 0x50 */
1538 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
1539 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
1540 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
1541 __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
1542 __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
1543 __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
1544} TIM_TypeDef;
1545
1546/**
1547 * @brief LPTIMIMER
1548 */
1549typedef struct
1550{
1551 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
1552 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
1553 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
1554 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
1555 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
1556 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
1557 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
1558 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
1559 uint32_t RESERVED1; /*!< Reserved, 0x20 */
1560 __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */
1561} LPTIM_TypeDef;
1562
1563/**
1564 * @brief Comparator
1565 */
1566typedef struct
1567{
1568 __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */
1569 __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */
1570 __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */
1571} COMPOPT_TypeDef;
1572
1573typedef struct
1574{
1575 __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */
1576} COMP_TypeDef;
1577
1578typedef struct
1579{
1580 __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
1581} COMP_Common_TypeDef;
1582/**
1583 * @brief Universal Synchronous Asynchronous Receiver Transmitter
1584 */
1585
1586typedef struct
1587{
1588 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
1589 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
1590 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
1591 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
1592 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
1593 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
1594 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
1595 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
1596 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
1597 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
1598 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
1599 __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */
1600} USART_TypeDef;
1601
1602/**
1603 * @brief Single Wire Protocol Master Interface SPWMI
1604 */
1605typedef struct
1606{
1607 __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
1608 __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
1609 uint32_t RESERVED1; /*!< Reserved, 0x08 */
1610 __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
1611 __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
1612 __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
1613 __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
1614 __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
1615 __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
1616 __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
1617} SWPMI_TypeDef;
1618
1619/**
1620 * @brief Window WATCHDOG
1621 */
1622
1623typedef struct
1624{
1625 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
1626 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
1627 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
1628} WWDG_TypeDef;
1629
1630
1631/**
1632 * @brief RAM_ECC_Specific_Registers
1633 */
1634typedef struct
1635{
1636 __IO uint32_t CR; /*!< RAMECC monitor configuration register */
1637 __IO uint32_t SR; /*!< RAMECC monitor status register */
1638 __IO uint32_t FAR; /*!< RAMECC monitor failing address register */
1639 __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */
1640 __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */
1641 __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */
1642} RAMECC_MonitorTypeDef;
1643
1644typedef struct
1645{
1646 __IO uint32_t IER; /*!< RAMECC interrupt enable register */
1647} RAMECC_TypeDef;
1648/**
1649 * @}
1650 */
1651
1652
1653/**
1654 * @brief Crypto Processor
1655 */
1656
1657typedef struct
1658{
1659 __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
1660 __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
1661 __IO uint32_t DIN; /*!< CRYP data input register, Address offset: 0x08 */
1662 __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
1663 __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
1664 __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
1665 __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
1666 __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
1667 __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
1668 __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
1669 __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
1670 __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
1671 __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
1672 __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
1673 __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
1674 __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
1675 __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
1676 __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
1677 __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
1678 __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
1679 __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
1680 __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
1681 __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
1682 __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
1683 __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
1684 __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
1685 __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
1686 __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
1687 __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
1688 __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
1689 __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
1690 __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
1691 __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
1692 __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
1693 __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
1694 __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
1695} CRYP_TypeDef;
1696
1697/**
1698 * @brief HASH
1699 */
1700
1701typedef struct
1702{
1703 __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
1704 __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
1705 __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
1706 __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
1707 __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
1708 __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
1709 uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
1710 __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
1711} HASH_TypeDef;
1712
1713/**
1714 * @brief HASH_DIGEST
1715 */
1716
1717typedef struct
1718{
1719 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
1720} HASH_DIGEST_TypeDef;
1721
1722
1723/**
1724 * @brief High resolution Timer (HRTIM)
1725 */
1726/* HRTIM master registers definition */
1727typedef struct
1728{
1729 __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
1730 __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
1731 __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
1732 __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
1733 __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
1734 __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
1735 __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */
1736 __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */
1737 uint32_t RESERVED0; /*!< Reserved, 0x20 */
1738 __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */
1739 __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */
1740 __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */
1741 uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */
1742}HRTIM_Master_TypeDef;
1743
1744/* HRTIM Timer A to E registers definition */
1745typedef struct
1746{
1747 __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */
1748 __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */
1749 __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */
1750 __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */
1751 __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */
1752 __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */
1753 __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */
1754 __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */
1755 __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */
1756 __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */
1757 __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */
1758 __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */
1759 __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */
1760 __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */
1761 __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */
1762 __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */
1763 __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */
1764 __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */
1765 __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */
1766 __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */
1767 __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */
1768 __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */
1769 __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */
1770 __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */
1771 __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */
1772 __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */
1773 __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */
1774 uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */
1775}HRTIM_Timerx_TypeDef;
1776
1777/* HRTIM common register definition */
1778typedef struct
1779{
1780 __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */
1781 __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */
1782 __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */
1783 __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */
1784 __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */
1785 __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */
1786 __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
1787 __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
1788 __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
1789 __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
1790 __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
1791 __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
1792 __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
1793 __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */
1794 __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */
1795 __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */
1796 __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */
1797 __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */
1798 __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */
1799 __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x4C */
1800 __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */
1801 __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */
1802 __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */
1803 __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */
1804 __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */
1805 __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */
1806 __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */
1807 __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */
1808 __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */
1809}HRTIM_Common_TypeDef;
1810
1811/* HRTIM register definition */
1812typedef struct {
1813 HRTIM_Master_TypeDef sMasterRegs;
1814 HRTIM_Timerx_TypeDef sTimerxRegs[5];
1815 uint32_t RESERVED0[32];
1816 HRTIM_Common_TypeDef sCommonRegs;
1817}HRTIM_TypeDef;
1818/**
1819 * @brief RNG
1820 */
1821
1822typedef struct
1823{
1824 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
1825 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
1826 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
1827} RNG_TypeDef;
1828
1829/**
1830 * @brief MDIOS
1831 */
1832
1833typedef struct
1834{
1835 __IO uint32_t CR;
1836 __IO uint32_t WRFR;
1837 __IO uint32_t CWRFR;
1838 __IO uint32_t RDFR;
1839 __IO uint32_t CRDFR;
1840 __IO uint32_t SR;
1841 __IO uint32_t CLRFR;
1842 uint32_t RESERVED[57];
1843 __IO uint32_t DINR0;
1844 __IO uint32_t DINR1;
1845 __IO uint32_t DINR2;
1846 __IO uint32_t DINR3;
1847 __IO uint32_t DINR4;
1848 __IO uint32_t DINR5;
1849 __IO uint32_t DINR6;
1850 __IO uint32_t DINR7;
1851 __IO uint32_t DINR8;
1852 __IO uint32_t DINR9;
1853 __IO uint32_t DINR10;
1854 __IO uint32_t DINR11;
1855 __IO uint32_t DINR12;
1856 __IO uint32_t DINR13;
1857 __IO uint32_t DINR14;
1858 __IO uint32_t DINR15;
1859 __IO uint32_t DINR16;
1860 __IO uint32_t DINR17;
1861 __IO uint32_t DINR18;
1862 __IO uint32_t DINR19;
1863 __IO uint32_t DINR20;
1864 __IO uint32_t DINR21;
1865 __IO uint32_t DINR22;
1866 __IO uint32_t DINR23;
1867 __IO uint32_t DINR24;
1868 __IO uint32_t DINR25;
1869 __IO uint32_t DINR26;
1870 __IO uint32_t DINR27;
1871 __IO uint32_t DINR28;
1872 __IO uint32_t DINR29;
1873 __IO uint32_t DINR30;
1874 __IO uint32_t DINR31;
1875 __IO uint32_t DOUTR0;
1876 __IO uint32_t DOUTR1;
1877 __IO uint32_t DOUTR2;
1878 __IO uint32_t DOUTR3;
1879 __IO uint32_t DOUTR4;
1880 __IO uint32_t DOUTR5;
1881 __IO uint32_t DOUTR6;
1882 __IO uint32_t DOUTR7;
1883 __IO uint32_t DOUTR8;
1884 __IO uint32_t DOUTR9;
1885 __IO uint32_t DOUTR10;
1886 __IO uint32_t DOUTR11;
1887 __IO uint32_t DOUTR12;
1888 __IO uint32_t DOUTR13;
1889 __IO uint32_t DOUTR14;
1890 __IO uint32_t DOUTR15;
1891 __IO uint32_t DOUTR16;
1892 __IO uint32_t DOUTR17;
1893 __IO uint32_t DOUTR18;
1894 __IO uint32_t DOUTR19;
1895 __IO uint32_t DOUTR20;
1896 __IO uint32_t DOUTR21;
1897 __IO uint32_t DOUTR22;
1898 __IO uint32_t DOUTR23;
1899 __IO uint32_t DOUTR24;
1900 __IO uint32_t DOUTR25;
1901 __IO uint32_t DOUTR26;
1902 __IO uint32_t DOUTR27;
1903 __IO uint32_t DOUTR28;
1904 __IO uint32_t DOUTR29;
1905 __IO uint32_t DOUTR30;
1906 __IO uint32_t DOUTR31;
1907} MDIOS_TypeDef;
1908
1909
1910/**
1911 * @brief USB_OTG_Core_Registers
1912 */
1913typedef struct
1914{
1915 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
1916 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
1917 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
1918 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
1919 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
1920 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
1921 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
1922 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
1923 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
1924 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
1925 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
1926 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
1927 uint32_t Reserved30[2]; /*!< Reserved 030h */
1928 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
1929 __IO uint32_t CID; /*!< User ID Register 03Ch */
1930 __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
1931 __IO uint32_t GHWCFG1; /* User HW config1 044h*/
1932 __IO uint32_t GHWCFG2; /* User HW config2 048h*/
1933 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
1934 uint32_t Reserved6; /*!< Reserved 050h */
1935 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
1936 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
1937 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
1938 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
1939 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
1940 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
1941 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
1942} USB_OTG_GlobalTypeDef;
1943
1944
1945/**
1946 * @brief USB_OTG_device_Registers
1947 */
1948typedef struct
1949{
1950 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
1951 __IO uint32_t DCTL; /*!< dev Control Register 804h */
1952 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
1953 uint32_t Reserved0C; /*!< Reserved 80Ch */
1954 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
1955 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
1956 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
1957 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
1958 uint32_t Reserved20; /*!< Reserved 820h */
1959 uint32_t Reserved9; /*!< Reserved 824h */
1960 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
1961 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
1962 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
1963 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
1964 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
1965 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
1966 uint32_t Reserved40; /*!< dedicated EP mask 840h */
1967 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
1968 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
1969 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
1970} USB_OTG_DeviceTypeDef;
1971
1972
1973/**
1974 * @brief USB_OTG_IN_Endpoint-Specific_Register
1975 */
1976typedef struct
1977{
1978 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
1979 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
1980 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
1981 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
1982 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
1983 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
1984 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
1985 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
1986} USB_OTG_INEndpointTypeDef;
1987
1988
1989/**
1990 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1991 */
1992typedef struct
1993{
1994 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
1995 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
1996 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
1997 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
1998 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
1999 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
2000 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
2001} USB_OTG_OUTEndpointTypeDef;
2002
2003
2004/**
2005 * @brief USB_OTG_Host_Mode_Register_Structures
2006 */
2007typedef struct
2008{
2009 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
2010 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
2011 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
2012 uint32_t Reserved40C; /*!< Reserved 40Ch */
2013 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
2014 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
2015 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
2016} USB_OTG_HostTypeDef;
2017
2018/**
2019 * @brief USB_OTG_Host_Channel_Specific_Registers
2020 */
2021typedef struct
2022{
2023 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
2024 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
2025 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
2026 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
2027 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
2028 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
2029 uint32_t Reserved[2]; /*!< Reserved */
2030} USB_OTG_HostChannelTypeDef;
2031/**
2032 * @}
2033 */
2034
2035
2036/** @addtogroup Peripheral_memory_map
2037 * @{
2038 */
2039#define D1_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */
2040#define D1_ITCMICP_BASE (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */
2041#define D1_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM */
2042#define D1_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 128 KB) embedded FLASH memory accessible over AXI */
2043#define D1_AXIICP_BASE (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */
2044#define D1_AXISRAM_BASE (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI */
2045
2046#define D2_AXISRAM_BASE (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI */
2047#define D2_AHBSRAM_BASE (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge */
2048
2049#define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */
2050#define D3_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */
2051
2052#define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/APB Peripherals */
2053#define QSPI_BASE (0x90000000UL) /*!< Base address of : QSPI memories accessible over AXI */
2054
2055#define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 128 KB) Flash Bank1 accessible over AXI */
2056#define FLASH_BANK2_BASE (0x08100000UL) /*!< For legacy only , Flash bank 2 not available on STM32H750xx value line */
2057#define FLASH_END (0x0801FFFFUL) /*!< FLASH end address */
2058
2059/* Legacy define */
2060#define FLASH_BASE FLASH_BANK1_BASE
2061
2062/*!< Device electronic signature memory map */
2063#define UID_BASE (0x1FF1E800UL) /*!< Unique device ID register base address */
2064#define FLASHSIZE_BASE (0x1FF1E880UL) /*!< FLASH Size register base address */
2065
2066
2067/*!< Peripheral memory map */
2068#define D2_APB1PERIPH_BASE PERIPH_BASE
2069#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
2070#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
2071#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL)
2072
2073#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
2074#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL)
2075
2076#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL)
2077#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL)
2078
2079/*!< Legacy Peripheral memory map */
2080#define APB1PERIPH_BASE PERIPH_BASE
2081#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
2082#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
2083#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
2084
2085
2086/*!< D1_AHB1PERIPH peripherals */
2087
2088#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL)
2089#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL)
2090#define JPGDEC_BASE (D1_AHB1PERIPH_BASE + 0x3000UL)
2091#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL)
2092#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL)
2093#define QSPI_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL)
2094#define DLYB_QSPI_BASE (D1_AHB1PERIPH_BASE + 0x6000UL)
2095#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL)
2096#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL)
2097#define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL)
2098
2099/*!< D2_AHB1PERIPH peripherals */
2100
2101#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL)
2102#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL)
2103#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL)
2104#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL)
2105#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL)
2106#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL)
2107#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL)
2108#define ETH_MAC_BASE (ETH_BASE)
2109
2110/*!< USB registers base address */
2111#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL)
2112#define USB2_OTG_FS_PERIPH_BASE (0x40080000UL)
2113#define USB_OTG_GLOBAL_BASE (0x000UL)
2114#define USB_OTG_DEVICE_BASE (0x800UL)
2115#define USB_OTG_IN_ENDPOINT_BASE (0x900UL)
2116#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL)
2117#define USB_OTG_EP_REG_SIZE (0x20UL)
2118#define USB_OTG_HOST_BASE (0x400UL)
2119#define USB_OTG_HOST_PORT_BASE (0x440UL)
2120#define USB_OTG_HOST_CHANNEL_BASE (0x500UL)
2121#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL)
2122#define USB_OTG_PCGCCTL_BASE (0xE00UL)
2123#define USB_OTG_FIFO_BASE (0x1000UL)
2124#define USB_OTG_FIFO_SIZE (0x1000UL)
2125
2126/*!< D2_AHB2PERIPH peripherals */
2127
2128#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL)
2129#define CRYP_BASE (D2_AHB2PERIPH_BASE + 0x1000UL)
2130#define HASH_BASE (D2_AHB2PERIPH_BASE + 0x1400UL)
2131#define HASH_DIGEST_BASE (D2_AHB2PERIPH_BASE + 0x1710UL)
2132#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL)
2133#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL)
2134#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL)
2135#define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL)
2136
2137/*!< D3_AHB1PERIPH peripherals */
2138#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL)
2139#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL)
2140#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL)
2141#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL)
2142#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL)
2143#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL)
2144#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL)
2145#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL)
2146#define GPIOI_BASE (D3_AHB1PERIPH_BASE + 0x2000UL)
2147#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL)
2148#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL)
2149#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL)
2150#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL)
2151#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL)
2152#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL)
2153#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL)
2154#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL)
2155#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL)
2156#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL)
2157#define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL)
2158
2159/*!< D1_APB1PERIPH peripherals */
2160#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL)
2161#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)
2162#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)
2163#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL)
2164
2165/*!< D2_APB1PERIPH peripherals */
2166#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL)
2167#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL)
2168#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL)
2169#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL)
2170#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL)
2171#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL)
2172#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL)
2173#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL)
2174#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL)
2175#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL)
2176
2177
2178#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL)
2179#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL)
2180#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL)
2181#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL)
2182#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL)
2183#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL)
2184#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL)
2185#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL)
2186#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL)
2187#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL)
2188#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL)
2189#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL)
2190#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL)
2191#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL)
2192#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL)
2193#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL)
2194#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
2195#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
2196#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL)
2197#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL)
2198#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL)
2199#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL)
2200#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL)
2201#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL)
2202
2203/*!< D2_APB2PERIPH peripherals */
2204
2205#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL)
2206#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL)
2207#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL)
2208#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL)
2209#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL)
2210#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL)
2211#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL)
2212#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL)
2213#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL)
2214#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL)
2215#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL)
2216#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
2217#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
2218#define SAI2_BASE (D2_APB2PERIPH_BASE + 0x5C00UL)
2219#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
2220#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
2221#define SAI3_BASE (D2_APB2PERIPH_BASE + 0x6000UL)
2222#define SAI3_Block_A_BASE (SAI3_BASE + 0x004UL)
2223#define SAI3_Block_B_BASE (SAI3_BASE + 0x024UL)
2224#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7000UL)
2225#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
2226#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
2227#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
2228#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
2229#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)
2230#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)
2231#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)
2232#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)
2233#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
2234#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
2235#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)
2236#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)
2237#define HRTIM1_BASE (D2_APB2PERIPH_BASE + 0x7400UL)
2238#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080UL)
2239#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100UL)
2240#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180UL)
2241#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200UL)
2242#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280UL)
2243#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380UL)
2244
2245
2246/*!< D3_APB1PERIPH peripherals */
2247#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL)
2248#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL)
2249#define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL)
2250#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL)
2251#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL)
2252#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL)
2253#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL)
2254#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL)
2255#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL)
2256#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL)
2257#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL)
2258#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL)
2259#define COMP1_BASE (COMP12_BASE + 0x0CUL)
2260#define COMP2_BASE (COMP12_BASE + 0x10UL)
2261#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL)
2262#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL)
2263#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL)
2264
2265
2266#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL)
2267#define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL)
2268#define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL)
2269
2270
2271
2272
2273#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL)
2274#define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL)
2275#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL)
2276#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL)
2277#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL)
2278#define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL)
2279#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL)
2280#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL)
2281
2282#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE)
2283#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL)
2284#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL)
2285#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL)
2286#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL)
2287#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL)
2288#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL)
2289#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL)
2290
2291#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL)
2292#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL)
2293#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL)
2294#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL)
2295#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL)
2296#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL)
2297#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL)
2298#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL)
2299
2300#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL)
2301#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL)
2302
2303#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
2304#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
2305#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
2306#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
2307#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
2308#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
2309#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
2310#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
2311
2312#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
2313#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
2314#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
2315#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
2316#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
2317#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
2318#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
2319#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
2320
2321#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
2322#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
2323#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
2324#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
2325#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
2326#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
2327#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
2328#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
2329#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
2330#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
2331#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
2332#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
2333#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
2334#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
2335#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
2336#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
2337
2338#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
2339#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
2340#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
2341#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
2342#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL)
2343#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL)
2344#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL)
2345#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL)
2346
2347#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
2348#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
2349
2350/*!< FMC Banks registers base address */
2351#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
2352#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
2353#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL)
2354#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
2355#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
2356
2357/* Debug MCU registers base address */
2358#define DBGMCU_BASE (0x5C001000UL)
2359
2360#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL)
2361#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL)
2362#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL)
2363#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL)
2364#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL)
2365#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL)
2366#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL)
2367#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL)
2368#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL)
2369#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL)
2370#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL)
2371#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL)
2372#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL)
2373#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
2374#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
2375#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
2376
2377#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)
2378#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)
2379#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)
2380#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)
2381#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)
2382
2383#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)
2384#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)
2385#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)
2386#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)
2387#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)
2388
2389#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)
2390#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
2391
2392
2393/**
2394 * @}
2395 */
2396
2397/** @addtogroup Peripheral_declaration
2398 * @{
2399 */
2400#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
2401#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
2402#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
2403#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
2404#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
2405#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
2406#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
2407#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
2408#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
2409#define RTC ((RTC_TypeDef *) RTC_BASE)
2410#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)
2411
2412
2413#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)
2414#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
2415#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
2416#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
2417#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
2418#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
2419#define USART2 ((USART_TypeDef *) USART2_BASE)
2420#define USART3 ((USART_TypeDef *) USART3_BASE)
2421#define USART6 ((USART_TypeDef *) USART6_BASE)
2422#define UART7 ((USART_TypeDef *) UART7_BASE)
2423#define UART8 ((USART_TypeDef *) UART8_BASE)
2424#define CRS ((CRS_TypeDef *) CRS_BASE)
2425#define UART4 ((USART_TypeDef *) UART4_BASE)
2426#define UART5 ((USART_TypeDef *) UART5_BASE)
2427#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
2428#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
2429#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
2430#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
2431#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
2432#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
2433#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
2434#define CEC ((CEC_TypeDef *) CEC_BASE)
2435#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
2436#define PWR ((PWR_TypeDef *) PWR_BASE)
2437#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
2438#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
2439#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
2440#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
2441#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)
2442#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)
2443#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)
2444
2445#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
2446#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)
2447#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
2448#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
2449#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
2450#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
2451#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
2452#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
2453
2454
2455#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
2456#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
2457#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
2458#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
2459#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
2460#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
2461#define USART1 ((USART_TypeDef *) USART1_BASE)
2462#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
2463#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
2464#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
2465#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
2466#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
2467#define HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)
2468#define HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)
2469#define HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)
2470#define HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)
2471#define HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)
2472#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
2473#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
2474#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
2475#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
2476#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
2477#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
2478#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
2479#define SAI3 ((SAI_TypeDef *) SAI3_BASE)
2480#define SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)
2481#define SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)
2482#define SAI4 ((SAI_TypeDef *) SAI4_BASE)
2483#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
2484#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
2485
2486#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
2487#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
2488#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
2489#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
2490#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
2491#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
2492#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
2493#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
2494#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
2495#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
2496#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
2497#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
2498#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
2499#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)
2500#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
2501#define RCC ((RCC_TypeDef *) RCC_BASE)
2502#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
2503#define CRC ((CRC_TypeDef *) CRC_BASE)
2504
2505#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
2506#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
2507#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
2508#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
2509#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
2510#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
2511#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
2512#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
2513#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
2514#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
2515#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
2516
2517#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
2518#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
2519#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
2520#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)
2521#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
2522
2523#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
2524#define HASH ((HASH_TypeDef *) HASH_BASE)
2525#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
2526#define RNG ((RNG_TypeDef *) RNG_BASE)
2527#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
2528#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
2529
2530#define BDMA ((BDMA_TypeDef *) BDMA_BASE)
2531#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)
2532#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)
2533#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)
2534#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)
2535#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)
2536#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)
2537#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)
2538#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)
2539
2540#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)
2541#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)
2542#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)
2543#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)
2544#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)
2545#define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)
2546
2547#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)
2548#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)
2549#define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)
2550#define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)
2551#define RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)
2552#define RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)
2553
2554#define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)
2555#define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)
2556#define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)
2557
2558#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
2559#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
2560#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
2561#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
2562#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
2563#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
2564#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
2565#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
2566#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
2567
2568
2569#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
2570#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
2571#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
2572#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
2573#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
2574#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
2575#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
2576#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
2577
2578#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
2579#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
2580
2581#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
2582#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
2583#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
2584#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
2585#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
2586#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
2587#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
2588#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
2589#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
2590
2591#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
2592#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
2593#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
2594#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
2595#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
2596#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
2597#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
2598#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
2599#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
2600
2601
2602#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
2603#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
2604#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
2605#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
2606#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
2607#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
2608#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
2609#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
2610#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
2611#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
2612#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
2613#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
2614#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
2615#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
2616#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
2617#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
2618#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
2619
2620#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
2621#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
2622#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
2623#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
2624#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
2625#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
2626#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
2627#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
2628
2629#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
2630#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
2631
2632
2633#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
2634#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
2635#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
2636#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
2637#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
2638
2639
2640#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
2641#define DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)
2642#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
2643#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
2644
2645#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
2646
2647#define JPEG ((JPEG_TypeDef *) JPGDEC_BASE)
2648#define HSEM ((HSEM_TypeDef *) HSEM_BASE)
2649#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
2650
2651#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
2652#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
2653#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
2654
2655#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
2656
2657#define ETH ((ETH_TypeDef *)ETH_BASE)
2658#define MDMA ((MDMA_TypeDef *)MDMA_BASE)
2659#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
2660#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
2661#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
2662#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
2663#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
2664#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
2665#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
2666#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
2667#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
2668#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
2669#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
2670#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
2671#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
2672#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
2673#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
2674#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
2675
2676
2677#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
2678#define USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)
2679
2680/* Legacy defines */
2681#define USB_OTG_HS USB1_OTG_HS
2682#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
2683#define USB_OTG_FS USB2_OTG_FS
2684#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
2685
2686/**
2687 * @}
2688 */
2689
2690/** @addtogroup Exported_constants
2691 * @{
2692 */
2693
2694 /** @addtogroup Peripheral_Registers_Bits_Definition
2695 * @{
2696 */
2697
2698/******************************************************************************/
2699/* Peripheral Registers_Bits_Definition */
2700/******************************************************************************/
2701
2702/******************************************************************************/
2703/* */
2704/* Analog to Digital Converter */
2705/* */
2706/******************************************************************************/
2707/******************************* ADC VERSION ********************************/
2708#define ADC_VER_V5_X
2709/******************** Bit definition for ADC_ISR register ********************/
2710#define ADC_ISR_ADRDY_Pos (0U)
2711#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
2712#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */
2713#define ADC_ISR_EOSMP_Pos (1U)
2714#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
2715#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */
2716#define ADC_ISR_EOC_Pos (2U)
2717#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
2718#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */
2719#define ADC_ISR_EOS_Pos (3U)
2720#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
2721#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */
2722#define ADC_ISR_OVR_Pos (4U)
2723#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
2724#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */
2725#define ADC_ISR_JEOC_Pos (5U)
2726#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
2727#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */
2728#define ADC_ISR_JEOS_Pos (6U)
2729#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
2730#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */
2731#define ADC_ISR_AWD1_Pos (7U)
2732#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
2733#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */
2734#define ADC_ISR_AWD2_Pos (8U)
2735#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
2736#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */
2737#define ADC_ISR_AWD3_Pos (9U)
2738#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
2739#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */
2740#define ADC_ISR_JQOVF_Pos (10U)
2741#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
2742#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
2743
2744/******************** Bit definition for ADC_IER register ********************/
2745#define ADC_IER_ADRDYIE_Pos (0U)
2746#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
2747#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */
2748#define ADC_IER_EOSMPIE_Pos (1U)
2749#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
2750#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */
2751#define ADC_IER_EOCIE_Pos (2U)
2752#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
2753#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */
2754#define ADC_IER_EOSIE_Pos (3U)
2755#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
2756#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */
2757#define ADC_IER_OVRIE_Pos (4U)
2758#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
2759#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */
2760#define ADC_IER_JEOCIE_Pos (5U)
2761#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
2762#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */
2763#define ADC_IER_JEOSIE_Pos (6U)
2764#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
2765#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */
2766#define ADC_IER_AWD1IE_Pos (7U)
2767#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
2768#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */
2769#define ADC_IER_AWD2IE_Pos (8U)
2770#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
2771#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */
2772#define ADC_IER_AWD3IE_Pos (9U)
2773#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
2774#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */
2775#define ADC_IER_JQOVFIE_Pos (10U)
2776#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
2777#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */
2778
2779/******************** Bit definition for ADC_CR register ********************/
2780#define ADC_CR_ADEN_Pos (0U)
2781#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
2782#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */
2783#define ADC_CR_ADDIS_Pos (1U)
2784#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
2785#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */
2786#define ADC_CR_ADSTART_Pos (2U)
2787#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
2788#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */
2789#define ADC_CR_JADSTART_Pos (3U)
2790#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
2791#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */
2792#define ADC_CR_ADSTP_Pos (4U)
2793#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
2794#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */
2795#define ADC_CR_JADSTP_Pos (5U)
2796#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
2797#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */
2798#define ADC_CR_BOOST_Pos (8U)
2799#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */
2800#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */
2801#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */
2802#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */
2803#define ADC_CR_ADCALLIN_Pos (16U)
2804#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */
2805#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */
2806#define ADC_CR_LINCALRDYW1_Pos (22U)
2807#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */
2808#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */
2809#define ADC_CR_LINCALRDYW2_Pos (23U)
2810#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */
2811#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */
2812#define ADC_CR_LINCALRDYW3_Pos (24U)
2813#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */
2814#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */
2815#define ADC_CR_LINCALRDYW4_Pos (25U)
2816#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */
2817#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */
2818#define ADC_CR_LINCALRDYW5_Pos (26U)
2819#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */
2820#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */
2821#define ADC_CR_LINCALRDYW6_Pos (27U)
2822#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */
2823#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */
2824#define ADC_CR_ADVREGEN_Pos (28U)
2825#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
2826#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */
2827#define ADC_CR_DEEPPWD_Pos (29U)
2828#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
2829#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */
2830#define ADC_CR_ADCALDIF_Pos (30U)
2831#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
2832#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */
2833#define ADC_CR_ADCAL_Pos (31U)
2834#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
2835#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */
2836
2837/******************** Bit definition for ADC_CFGR register ********************/
2838#define ADC_CFGR_DMNGT_Pos (0U)
2839#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */
2840#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */
2841#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */
2842#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */
2843
2844#define ADC_CFGR_RES_Pos (2U)
2845#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */
2846#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */
2847#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */
2848#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
2849#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
2850
2851#define ADC_CFGR_EXTSEL_Pos (5U)
2852#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
2853#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */
2854#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
2855#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
2856#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
2857#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
2858#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
2859
2860#define ADC_CFGR_EXTEN_Pos (10U)
2861#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
2862#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */
2863#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
2864#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
2865
2866#define ADC_CFGR_OVRMOD_Pos (12U)
2867#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
2868#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */
2869#define ADC_CFGR_CONT_Pos (13U)
2870#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
2871#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */
2872#define ADC_CFGR_AUTDLY_Pos (14U)
2873#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
2874#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */
2875
2876#define ADC_CFGR_DISCEN_Pos (16U)
2877#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
2878#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */
2879
2880#define ADC_CFGR_DISCNUM_Pos (17U)
2881#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
2882#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
2883#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
2884#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
2885#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
2886
2887#define ADC_CFGR_JDISCEN_Pos (20U)
2888#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
2889#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
2890#define ADC_CFGR_JQM_Pos (21U)
2891#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
2892#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */
2893#define ADC_CFGR_AWD1SGL_Pos (22U)
2894#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
2895#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */
2896#define ADC_CFGR_AWD1EN_Pos (23U)
2897#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
2898#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */
2899#define ADC_CFGR_JAWD1EN_Pos (24U)
2900#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
2901#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */
2902#define ADC_CFGR_JAUTO_Pos (25U)
2903#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
2904#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */
2905
2906#define ADC_CFGR_AWD1CH_Pos (26U)
2907#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
2908#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */
2909#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
2910#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
2911#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
2912#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
2913#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
2914
2915#define ADC_CFGR_JQDIS_Pos (31U)
2916#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
2917#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */
2918
2919/******************** Bit definition for ADC_CFGR2 register ********************/
2920#define ADC_CFGR2_ROVSE_Pos (0U)
2921#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
2922#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */
2923#define ADC_CFGR2_JOVSE_Pos (1U)
2924#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
2925#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */
2926
2927#define ADC_CFGR2_OVSS_Pos (5U)
2928#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
2929#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */
2930#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
2931#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
2932#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
2933#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
2934
2935#define ADC_CFGR2_TROVS_Pos (9U)
2936#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
2937#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */
2938#define ADC_CFGR2_ROVSM_Pos (10U)
2939#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
2940#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */
2941
2942#define ADC_CFGR2_RSHIFT1_Pos (11U)
2943#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */
2944#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */
2945#define ADC_CFGR2_RSHIFT2_Pos (12U)
2946#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */
2947#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */
2948#define ADC_CFGR2_RSHIFT3_Pos (13U)
2949#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */
2950#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */
2951#define ADC_CFGR2_RSHIFT4_Pos (14U)
2952#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */
2953#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */
2954
2955#define ADC_CFGR2_OVSR_Pos (16U)
2956#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */
2957#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */
2958#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */
2959#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */
2960#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */
2961#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */
2962#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */
2963#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */
2964#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */
2965#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */
2966#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */
2967#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */
2968
2969#define ADC_CFGR2_LSHIFT_Pos (28U)
2970#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */
2971#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */
2972#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */
2973#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */
2974#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */
2975#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */
2976
2977/******************** Bit definition for ADC_SMPR1 register ********************/
2978#define ADC_SMPR1_SMP0_Pos (0U)
2979#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
2980#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */
2981#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
2982#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
2983#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
2984
2985#define ADC_SMPR1_SMP1_Pos (3U)
2986#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
2987#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */
2988#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
2989#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
2990#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
2991
2992#define ADC_SMPR1_SMP2_Pos (6U)
2993#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
2994#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */
2995#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
2996#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
2997#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
2998
2999#define ADC_SMPR1_SMP3_Pos (9U)
3000#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
3001#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */
3002#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
3003#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
3004#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
3005
3006#define ADC_SMPR1_SMP4_Pos (12U)
3007#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
3008#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */
3009#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
3010#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
3011#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
3012
3013#define ADC_SMPR1_SMP5_Pos (15U)
3014#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
3015#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */
3016#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
3017#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
3018#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
3019
3020#define ADC_SMPR1_SMP6_Pos (18U)
3021#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
3022#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */
3023#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
3024#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
3025#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
3026
3027#define ADC_SMPR1_SMP7_Pos (21U)
3028#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
3029#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */
3030#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
3031#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
3032#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
3033
3034#define ADC_SMPR1_SMP8_Pos (24U)
3035#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
3036#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */
3037#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
3038#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
3039#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
3040
3041#define ADC_SMPR1_SMP9_Pos (27U)
3042#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
3043#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */
3044#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
3045#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
3046#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
3047
3048/******************** Bit definition for ADC_SMPR2 register ********************/
3049#define ADC_SMPR2_SMP10_Pos (0U)
3050#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
3051#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */
3052#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
3053#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
3054#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
3055
3056#define ADC_SMPR2_SMP11_Pos (3U)
3057#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
3058#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */
3059#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
3060#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
3061#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
3062
3063#define ADC_SMPR2_SMP12_Pos (6U)
3064#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
3065#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */
3066#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
3067#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
3068#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
3069
3070#define ADC_SMPR2_SMP13_Pos (9U)
3071#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
3072#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */
3073#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
3074#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
3075#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
3076
3077#define ADC_SMPR2_SMP14_Pos (12U)
3078#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
3079#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */
3080#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
3081#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
3082#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
3083
3084#define ADC_SMPR2_SMP15_Pos (15U)
3085#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
3086#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */
3087#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
3088#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
3089#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
3090
3091#define ADC_SMPR2_SMP16_Pos (18U)
3092#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
3093#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */
3094#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
3095#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
3096#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
3097
3098#define ADC_SMPR2_SMP17_Pos (21U)
3099#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
3100#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */
3101#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
3102#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
3103#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
3104
3105#define ADC_SMPR2_SMP18_Pos (24U)
3106#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
3107#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */
3108#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
3109#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
3110#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
3111
3112#define ADC_SMPR2_SMP19_Pos (27U)
3113#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
3114#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */
3115#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
3116#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
3117#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
3118
3119/******************** Bit definition for ADC_PCSEL register ********************/
3120#define ADC_PCSEL_PCSEL_Pos (0U)
3121#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */
3122#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */
3123#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */
3124#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */
3125#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */
3126#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */
3127#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */
3128#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */
3129#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */
3130#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */
3131#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */
3132#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */
3133#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */
3134#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */
3135#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */
3136#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */
3137#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */
3138#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */
3139#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */
3140#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */
3141#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */
3142#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */
3143
3144/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/
3145#define ADC_LTR_LT_Pos (0U)
3146#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */
3147#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */
3148
3149/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/
3150#define ADC_HTR_HT_Pos (0U)
3151#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */
3152#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */
3153
3154
3155/******************** Bit definition for ADC_SQR1 register ********************/
3156#define ADC_SQR1_L_Pos (0U)
3157#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
3158#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
3159#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
3160#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
3161#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
3162#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
3163
3164#define ADC_SQR1_SQ1_Pos (6U)
3165#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
3166#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */
3167#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
3168#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
3169#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
3170#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
3171#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
3172
3173#define ADC_SQR1_SQ2_Pos (12U)
3174#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
3175#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */
3176#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
3177#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
3178#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
3179#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
3180#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
3181
3182#define ADC_SQR1_SQ3_Pos (18U)
3183#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
3184#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */
3185#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
3186#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
3187#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
3188#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
3189#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
3190
3191#define ADC_SQR1_SQ4_Pos (24U)
3192#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
3193#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */
3194#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
3195#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
3196#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
3197#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
3198#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
3199
3200/******************** Bit definition for ADC_SQR2 register ********************/
3201#define ADC_SQR2_SQ5_Pos (0U)
3202#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
3203#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */
3204#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
3205#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
3206#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
3207#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
3208#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
3209
3210#define ADC_SQR2_SQ6_Pos (6U)
3211#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
3212#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */
3213#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
3214#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
3215#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
3216#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
3217#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
3218
3219#define ADC_SQR2_SQ7_Pos (12U)
3220#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
3221#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */
3222#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
3223#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
3224#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
3225#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
3226#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
3227
3228#define ADC_SQR2_SQ8_Pos (18U)
3229#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
3230#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */
3231#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
3232#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
3233#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
3234#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
3235#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
3236
3237#define ADC_SQR2_SQ9_Pos (24U)
3238#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
3239#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */
3240#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
3241#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
3242#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
3243#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
3244#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
3245
3246/******************** Bit definition for ADC_SQR3 register ********************/
3247#define ADC_SQR3_SQ10_Pos (0U)
3248#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
3249#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */
3250#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
3251#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
3252#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
3253#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
3254#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
3255
3256#define ADC_SQR3_SQ11_Pos (6U)
3257#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
3258#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */
3259#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
3260#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
3261#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
3262#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
3263#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
3264
3265#define ADC_SQR3_SQ12_Pos (12U)
3266#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
3267#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */
3268#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
3269#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
3270#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
3271#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
3272#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
3273
3274#define ADC_SQR3_SQ13_Pos (18U)
3275#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
3276#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */
3277#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
3278#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
3279#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
3280#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
3281#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
3282
3283#define ADC_SQR3_SQ14_Pos (24U)
3284#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
3285#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */
3286#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
3287#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
3288#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
3289#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
3290#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
3291
3292/******************** Bit definition for ADC_SQR4 register ********************/
3293#define ADC_SQR4_SQ15_Pos (0U)
3294#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
3295#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */
3296#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
3297#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
3298#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
3299#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
3300#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
3301
3302#define ADC_SQR4_SQ16_Pos (6U)
3303#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
3304#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */
3305#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
3306#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
3307#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
3308#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
3309#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
3310/******************** Bit definition for ADC_DR register ********************/
3311#define ADC_DR_RDATA_Pos (0U)
3312#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */
3313#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */
3314
3315/******************** Bit definition for ADC_JSQR register ********************/
3316#define ADC_JSQR_JL_Pos (0U)
3317#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
3318#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */
3319#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
3320#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
3321
3322#define ADC_JSQR_JEXTSEL_Pos (2U)
3323#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
3324#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */
3325#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
3326#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
3327#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
3328#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
3329#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
3330
3331#define ADC_JSQR_JEXTEN_Pos (7U)
3332#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
3333#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */
3334#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
3335#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
3336
3337#define ADC_JSQR_JSQ1_Pos (9U)
3338#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
3339#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */
3340#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
3341#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
3342#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
3343#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
3344#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
3345
3346#define ADC_JSQR_JSQ2_Pos (15U)
3347#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */
3348#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */
3349#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
3350#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
3351#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
3352#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
3353#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */
3354
3355#define ADC_JSQR_JSQ3_Pos (21U)
3356#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
3357#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */
3358#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
3359#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
3360#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
3361#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
3362#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
3363
3364#define ADC_JSQR_JSQ4_Pos (27U)
3365#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
3366#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */
3367#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
3368#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
3369#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
3370#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
3371#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
3372
3373/******************** Bit definition for ADC_OFR1 register ********************/
3374#define ADC_OFR1_OFFSET1_Pos (0U)
3375#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
3376#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
3377#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
3378#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
3379#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
3380#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
3381#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
3382#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
3383#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
3384#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
3385#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
3386#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
3387#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
3388#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
3389#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
3390#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
3391#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
3392#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
3393#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
3394#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
3395#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
3396#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
3397#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
3398#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
3399#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
3400#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
3401#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
3402#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
3403
3404#define ADC_OFR1_OFFSET1_CH_Pos (26U)
3405#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
3406#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */
3407#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
3408#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
3409#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
3410#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
3411#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
3412
3413#define ADC_OFR1_SSATE_Pos (31U)
3414#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */
3415#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */
3416
3417
3418/******************** Bit definition for ADC_OFR2 register ********************/
3419#define ADC_OFR2_OFFSET2_Pos (0U)
3420#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
3421#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
3422#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
3423#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
3424#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
3425#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
3426#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
3427#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
3428#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
3429#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
3430#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
3431#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
3432#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
3433#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
3434#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
3435#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
3436#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
3437#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
3438#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
3439#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
3440#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
3441#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
3442#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
3443#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
3444#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
3445#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
3446#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
3447#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
3448
3449#define ADC_OFR2_OFFSET2_CH_Pos (26U)
3450#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
3451#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */
3452#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
3453#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
3454#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
3455#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
3456#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
3457
3458#define ADC_OFR2_SSATE_Pos (31U)
3459#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */
3460#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */
3461
3462
3463/******************** Bit definition for ADC_OFR3 register ********************/
3464#define ADC_OFR3_OFFSET3_Pos (0U)
3465#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
3466#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
3467#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
3468#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
3469#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
3470#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
3471#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
3472#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
3473#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
3474#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
3475#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
3476#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
3477#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
3478#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
3479#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
3480#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
3481#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
3482#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
3483#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
3484#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
3485#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
3486#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
3487#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
3488#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
3489#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
3490#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
3491#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
3492#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
3493
3494#define ADC_OFR3_OFFSET3_CH_Pos (26U)
3495#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
3496#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */
3497#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
3498#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
3499#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
3500#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
3501#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
3502
3503#define ADC_OFR3_SSATE_Pos (31U)
3504#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */
3505#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */
3506
3507
3508/******************** Bit definition for ADC_OFR4 register ********************/
3509#define ADC_OFR4_OFFSET4_Pos (0U)
3510#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
3511#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
3512#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
3513#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
3514#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
3515#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
3516#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
3517#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
3518#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
3519#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
3520#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
3521#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
3522#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
3523#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
3524#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
3525#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
3526#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
3527#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
3528#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
3529#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
3530#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
3531#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
3532#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
3533#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
3534#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
3535#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
3536#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
3537#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
3538
3539#define ADC_OFR4_OFFSET4_CH_Pos (26U)
3540#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
3541#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */
3542#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
3543#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
3544#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
3545#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
3546#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
3547
3548#define ADC_OFR4_SSATE_Pos (31U)
3549#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */
3550#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */
3551
3552
3553/******************** Bit definition for ADC_JDR1 register ********************/
3554#define ADC_JDR1_JDATA_Pos (0U)
3555#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */
3556#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */
3557#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
3558#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
3559#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
3560#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
3561#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
3562#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
3563#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
3564#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
3565#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
3566#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
3567#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
3568#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
3569#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
3570#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
3571#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
3572#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
3573#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */
3574#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */
3575#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */
3576#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */
3577#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */
3578#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */
3579#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */
3580#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */
3581#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */
3582#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */
3583#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */
3584#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */
3585#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */
3586#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */
3587#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */
3588#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */
3589
3590/******************** Bit definition for ADC_JDR2 register ********************/
3591#define ADC_JDR2_JDATA_Pos (0U)
3592#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */
3593#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */
3594#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
3595#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
3596#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
3597#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
3598#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
3599#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
3600#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
3601#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
3602#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
3603#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
3604#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
3605#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
3606#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
3607#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
3608#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
3609#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
3610#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */
3611#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */
3612#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */
3613#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */
3614#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */
3615#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */
3616#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */
3617#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */
3618#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */
3619#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */
3620#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */
3621#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */
3622#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */
3623#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */
3624#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */
3625#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */
3626
3627/******************** Bit definition for ADC_JDR3 register ********************/
3628#define ADC_JDR3_JDATA_Pos (0U)
3629#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */
3630#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */
3631#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
3632#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
3633#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
3634#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
3635#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
3636#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
3637#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
3638#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
3639#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
3640#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
3641#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
3642#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
3643#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
3644#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
3645#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
3646#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
3647#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */
3648#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */
3649#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */
3650#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */
3651#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */
3652#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */
3653#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */
3654#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */
3655#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */
3656#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */
3657#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */
3658#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */
3659#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */
3660#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */
3661#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */
3662#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */
3663
3664/******************** Bit definition for ADC_JDR4 register ********************/
3665#define ADC_JDR4_JDATA_Pos (0U)
3666#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */
3667#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */
3668#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
3669#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
3670#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
3671#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
3672#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
3673#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
3674#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
3675#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
3676#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
3677#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
3678#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
3679#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
3680#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
3681#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
3682#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
3683#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
3684#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */
3685#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */
3686#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */
3687#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */
3688#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */
3689#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */
3690#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */
3691#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */
3692#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */
3693#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */
3694#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */
3695#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */
3696#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */
3697#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */
3698#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */
3699#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */
3700
3701/******************** Bit definition for ADC_AWD2CR register ********************/
3702#define ADC_AWD2CR_AWD2CH_Pos (0U)
3703#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */
3704#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
3705#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
3706#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
3707#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
3708#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
3709#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
3710#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
3711#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
3712#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
3713#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
3714#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
3715#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
3716#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
3717#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
3718#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
3719#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
3720#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
3721#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
3722#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
3723#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
3724#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
3725
3726/******************** Bit definition for ADC_AWD3CR register ********************/
3727#define ADC_AWD3CR_AWD3CH_Pos (0U)
3728#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
3729#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */
3730#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
3731#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
3732#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
3733#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
3734#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
3735#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
3736#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
3737#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
3738#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
3739#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
3740#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
3741#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
3742#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
3743#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
3744#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
3745#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
3746#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
3747#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
3748#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
3749#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
3750
3751/******************** Bit definition for ADC_DIFSEL register ********************/
3752#define ADC_DIFSEL_DIFSEL_Pos (0U)
3753#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
3754#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */
3755#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
3756#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
3757#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
3758#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
3759#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
3760#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
3761#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
3762#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
3763#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
3764#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
3765#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
3766#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
3767#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
3768#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
3769#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
3770#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
3771#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
3772#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
3773#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
3774#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */
3775
3776/******************** Bit definition for ADC_CALFACT register ********************/
3777#define ADC_CALFACT_CALFACT_S_Pos (0U)
3778#define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
3779#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */
3780#define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
3781#define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
3782#define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
3783#define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
3784#define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
3785#define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
3786#define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
3787#define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
3788#define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
3789#define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
3790#define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
3791#define ADC_CALFACT_CALFACT_D_Pos (16U)
3792#define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
3793#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */
3794#define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
3795#define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
3796#define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
3797#define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
3798#define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
3799#define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
3800#define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
3801#define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
3802#define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
3803#define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
3804#define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
3805
3806/******************** Bit definition for ADC_CALFACT2 register ********************/
3807#define ADC_CALFACT2_LINCALFACT_Pos (0U)
3808#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
3809#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */
3810#define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
3811#define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
3812#define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
3813#define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
3814#define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
3815#define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
3816#define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
3817#define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
3818#define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
3819#define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
3820#define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
3821#define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
3822#define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
3823#define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
3824#define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
3825#define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
3826#define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
3827#define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
3828#define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
3829#define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
3830#define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
3831#define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
3832#define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
3833#define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
3834#define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
3835#define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
3836#define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
3837#define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */
3838#define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
3839#define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
3840
3841/************************* ADC Common registers *****************************/
3842/******************** Bit definition for ADC_CSR register ********************/
3843#define ADC_CSR_ADRDY_MST_Pos (0U)
3844#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
3845#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
3846#define ADC_CSR_EOSMP_MST_Pos (1U)
3847#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
3848#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
3849#define ADC_CSR_EOC_MST_Pos (2U)
3850#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
3851#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
3852#define ADC_CSR_EOS_MST_Pos (3U)
3853#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
3854#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
3855#define ADC_CSR_OVR_MST_Pos (4U)
3856#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
3857#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */
3858#define ADC_CSR_JEOC_MST_Pos (5U)
3859#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
3860#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
3861#define ADC_CSR_JEOS_MST_Pos (6U)
3862#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
3863#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
3864#define ADC_CSR_AWD1_MST_Pos (7U)
3865#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
3866#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
3867#define ADC_CSR_AWD2_MST_Pos (8U)
3868#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
3869#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
3870#define ADC_CSR_AWD3_MST_Pos (9U)
3871#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
3872#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
3873#define ADC_CSR_JQOVF_MST_Pos (10U)
3874#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
3875#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
3876#define ADC_CSR_ADRDY_SLV_Pos (16U)
3877#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
3878#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
3879#define ADC_CSR_EOSMP_SLV_Pos (17U)
3880#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
3881#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
3882#define ADC_CSR_EOC_SLV_Pos (18U)
3883#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
3884#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
3885#define ADC_CSR_EOS_SLV_Pos (19U)
3886#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
3887#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
3888#define ADC_CSR_OVR_SLV_Pos (20U)
3889#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
3890#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
3891#define ADC_CSR_JEOC_SLV_Pos (21U)
3892#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
3893#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */
3894#define ADC_CSR_JEOS_SLV_Pos (22U)
3895#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
3896#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */
3897#define ADC_CSR_AWD1_SLV_Pos (23U)
3898#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
3899#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */
3900#define ADC_CSR_AWD2_SLV_Pos (24U)
3901#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
3902#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */
3903#define ADC_CSR_AWD3_SLV_Pos (25U)
3904#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
3905#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */
3906#define ADC_CSR_JQOVF_SLV_Pos (26U)
3907#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
3908#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */
3909
3910/******************** Bit definition for ADC_CCR register ********************/
3911#define ADC_CCR_DUAL_Pos (0U)
3912#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
3913#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */
3914#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
3915#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
3916#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
3917#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
3918#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
3919
3920#define ADC_CCR_DELAY_Pos (8U)
3921#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
3922#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */
3923#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
3924#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
3925#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
3926#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
3927
3928
3929#define ADC_CCR_DAMDF_Pos (14U)
3930#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */
3931#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */
3932#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */
3933#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */
3934
3935#define ADC_CCR_CKMODE_Pos (16U)
3936#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
3937#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */
3938#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
3939#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
3940
3941#define ADC_CCR_PRESC_Pos (18U)
3942#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
3943#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */
3944#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
3945#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
3946#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
3947#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
3948
3949#define ADC_CCR_VREFEN_Pos (22U)
3950#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
3951#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */
3952#define ADC_CCR_TSEN_Pos (23U)
3953#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
3954#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */
3955#define ADC_CCR_VBATEN_Pos (24U)
3956#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
3957#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */
3958
3959/******************** Bit definition for ADC_CDR register *******************/
3960#define ADC_CDR_RDATA_MST_Pos (0U)
3961#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
3962#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
3963
3964#define ADC_CDR_RDATA_SLV_Pos (16U)
3965#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
3966#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
3967
3968/******************** Bit definition for ADC_CDR2 register ******************/
3969#define ADC_CDR2_RDATA_ALT_Pos (0U)
3970#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
3971#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */
3972
3973
3974/******************************************************************************/
3975/* */
3976/* VREFBUF */
3977/* */
3978/******************************************************************************/
3979/******************* Bit definition for VREFBUF_CSR register ****************/
3980#define VREFBUF_CSR_ENVR_Pos (0U)
3981#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
3982#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
3983#define VREFBUF_CSR_HIZ_Pos (1U)
3984#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
3985#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
3986#define VREFBUF_CSR_VRR_Pos (3U)
3987#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
3988#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
3989#define VREFBUF_CSR_VRS_Pos (4U)
3990#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
3991#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
3992
3993#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
3994#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
3995#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
3996#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
3997#define VREFBUF_CSR_VRS_OUT3_Pos (5U)
3998#define VREFBUF_CSR_VRS_OUT3_Msk (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos) /*!< 0x00000020 */
3999#define VREFBUF_CSR_VRS_OUT3 VREFBUF_CSR_VRS_OUT3_Msk /*!<Voltage reference VREF_OUT3 */
4000#define VREFBUF_CSR_VRS_OUT4_Pos (4U)
4001#define VREFBUF_CSR_VRS_OUT4_Msk (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos) /*!< 0x00000030 */
4002#define VREFBUF_CSR_VRS_OUT4 VREFBUF_CSR_VRS_OUT4_Msk /*!<Voltage reference VREF_OUT4 */
4003
4004/******************* Bit definition for VREFBUF_CCR register ****************/
4005#define VREFBUF_CCR_TRIM_Pos (0U)
4006#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
4007#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
4008
4009/******************************************************************************/
4010/* */
4011/* Flexible Datarate Controller Area Network */
4012/* */
4013/******************************************************************************/
4014/*!<FDCAN control and status registers */
4015/***************** Bit definition for FDCAN_CREL register *******************/
4016#define FDCAN_CREL_DAY_Pos (0U)
4017#define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */
4018#define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */
4019#define FDCAN_CREL_MON_Pos (8U)
4020#define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */
4021#define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */
4022#define FDCAN_CREL_YEAR_Pos (16U)
4023#define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */
4024#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */
4025#define FDCAN_CREL_SUBSTEP_Pos (20U)
4026#define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
4027#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
4028#define FDCAN_CREL_STEP_Pos (24U)
4029#define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */
4030#define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */
4031#define FDCAN_CREL_REL_Pos (28U)
4032#define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */
4033#define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */
4034
4035/***************** Bit definition for FDCAN_ENDN register *******************/
4036#define FDCAN_ENDN_ETV_Pos (0U)
4037#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
4038#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
4039
4040/***************** Bit definition for FDCAN_DBTP register *******************/
4041#define FDCAN_DBTP_DSJW_Pos (0U)
4042#define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */
4043#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */
4044#define FDCAN_DBTP_DTSEG2_Pos (4U)
4045#define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */
4046#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */
4047#define FDCAN_DBTP_DTSEG1_Pos (8U)
4048#define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */
4049#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */
4050#define FDCAN_DBTP_DBRP_Pos (16U)
4051#define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */
4052#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */
4053#define FDCAN_DBTP_TDC_Pos (23U)
4054#define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */
4055#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */
4056
4057/***************** Bit definition for FDCAN_TEST register *******************/
4058#define FDCAN_TEST_LBCK_Pos (4U)
4059#define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */
4060#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */
4061#define FDCAN_TEST_TX_Pos (5U)
4062#define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */
4063#define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */
4064#define FDCAN_TEST_RX_Pos (7U)
4065#define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */
4066#define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */
4067
4068/***************** Bit definition for FDCAN_RWD register ********************/
4069#define FDCAN_RWD_WDC_Pos (0U)
4070#define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */
4071#define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */
4072#define FDCAN_RWD_WDV_Pos (8U)
4073#define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */
4074#define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */
4075
4076/***************** Bit definition for FDCAN_CCCR register ********************/
4077#define FDCAN_CCCR_INIT_Pos (0U)
4078#define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
4079#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */
4080#define FDCAN_CCCR_CCE_Pos (1U)
4081#define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */
4082#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */
4083#define FDCAN_CCCR_ASM_Pos (2U)
4084#define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */
4085#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */
4086#define FDCAN_CCCR_CSA_Pos (3U)
4087#define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */
4088#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */
4089#define FDCAN_CCCR_CSR_Pos (4U)
4090#define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */
4091#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */
4092#define FDCAN_CCCR_MON_Pos (5U)
4093#define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */
4094#define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */
4095#define FDCAN_CCCR_DAR_Pos (6U)
4096#define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */
4097#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */
4098#define FDCAN_CCCR_TEST_Pos (7U)
4099#define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */
4100#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */
4101#define FDCAN_CCCR_FDOE_Pos (8U)
4102#define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */
4103#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */
4104#define FDCAN_CCCR_BRSE_Pos (9U)
4105#define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */
4106#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */
4107#define FDCAN_CCCR_PXHD_Pos (12U)
4108#define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */
4109#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */
4110#define FDCAN_CCCR_EFBI_Pos (13U)
4111#define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */
4112#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */
4113#define FDCAN_CCCR_TXP_Pos (14U)
4114#define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */
4115#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */
4116#define FDCAN_CCCR_NISO_Pos (15U)
4117#define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */
4118#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */
4119
4120/***************** Bit definition for FDCAN_NBTP register ********************/
4121#define FDCAN_NBTP_NTSEG2_Pos (0U)
4122#define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */
4123#define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */
4124#define FDCAN_NBTP_NTSEG1_Pos (8U)
4125#define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */
4126#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */
4127#define FDCAN_NBTP_NBRP_Pos (16U)
4128#define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */
4129#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */
4130#define FDCAN_NBTP_NSJW_Pos (25U)
4131#define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */
4132#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */
4133
4134/***************** Bit definition for FDCAN_TSCC register ********************/
4135#define FDCAN_TSCC_TSS_Pos (0U)
4136#define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */
4137#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */
4138#define FDCAN_TSCC_TCP_Pos (16U)
4139#define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */
4140#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */
4141
4142/***************** Bit definition for FDCAN_TSCV register ********************/
4143#define FDCAN_TSCV_TSC_Pos (0U)
4144#define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */
4145#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */
4146
4147/***************** Bit definition for FDCAN_TOCC register ********************/
4148#define FDCAN_TOCC_ETOC_Pos (0U)
4149#define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */
4150#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */
4151#define FDCAN_TOCC_TOS_Pos (1U)
4152#define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */
4153#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */
4154#define FDCAN_TOCC_TOP_Pos (16U)
4155#define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */
4156#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */
4157
4158/***************** Bit definition for FDCAN_TOCV register ********************/
4159#define FDCAN_TOCV_TOC_Pos (0U)
4160#define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */
4161#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */
4162
4163/***************** Bit definition for FDCAN_ECR register *********************/
4164#define FDCAN_ECR_TEC_Pos (0U)
4165#define FDCAN_ECR_TEC_Msk (0xFUL << FDCAN_ECR_TEC_Pos) /*!< 0x0000000F */
4166#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
4167#define FDCAN_ECR_REC_Pos (8U)
4168#define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */
4169#define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */
4170#define FDCAN_ECR_RP_Pos (15U)
4171#define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */
4172#define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */
4173#define FDCAN_ECR_CEL_Pos (16U)
4174#define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */
4175#define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */
4176
4177/***************** Bit definition for FDCAN_PSR register *********************/
4178#define FDCAN_PSR_LEC_Pos (0U)
4179#define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */
4180#define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */
4181#define FDCAN_PSR_ACT_Pos (3U)
4182#define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */
4183#define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */
4184#define FDCAN_PSR_EP_Pos (5U)
4185#define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */
4186#define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */
4187#define FDCAN_PSR_EW_Pos (6U)
4188#define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */
4189#define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */
4190#define FDCAN_PSR_BO_Pos (7U)
4191#define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */
4192#define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */
4193#define FDCAN_PSR_DLEC_Pos (8U)
4194#define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */
4195#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */
4196#define FDCAN_PSR_RESI_Pos (11U)
4197#define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */
4198#define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */
4199#define FDCAN_PSR_RBRS_Pos (12U)
4200#define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */
4201#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */
4202#define FDCAN_PSR_REDL_Pos (13U)
4203#define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */
4204#define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */
4205#define FDCAN_PSR_PXE_Pos (14U)
4206#define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */
4207#define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */
4208#define FDCAN_PSR_TDCV_Pos (16U)
4209#define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */
4210#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */
4211
4212/***************** Bit definition for FDCAN_TDCR register ********************/
4213#define FDCAN_TDCR_TDCF_Pos (0U)
4214#define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */
4215#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */
4216#define FDCAN_TDCR_TDCO_Pos (8U)
4217#define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */
4218#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */
4219
4220/***************** Bit definition for FDCAN_IR register **********************/
4221#define FDCAN_IR_RF0N_Pos (0U)
4222#define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */
4223#define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */
4224#define FDCAN_IR_RF0W_Pos (1U)
4225#define FDCAN_IR_RF0W_Msk (0x1UL << FDCAN_IR_RF0W_Pos) /*!< 0x00000002 */
4226#define FDCAN_IR_RF0W FDCAN_IR_RF0W_Msk /*!<Rx FIFO 0 Watermark Reached */
4227#define FDCAN_IR_RF0F_Pos (2U)
4228#define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) /*!< 0x00000004 */
4229#define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */
4230#define FDCAN_IR_RF0L_Pos (3U)
4231#define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) /*!< 0x00000008 */
4232#define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
4233#define FDCAN_IR_RF1N_Pos (4U)
4234#define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) /*!< 0x00000010 */
4235#define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */
4236#define FDCAN_IR_RF1W_Pos (5U)
4237#define FDCAN_IR_RF1W_Msk (0x1UL << FDCAN_IR_RF1W_Pos) /*!< 0x00000020 */
4238#define FDCAN_IR_RF1W FDCAN_IR_RF1W_Msk /*!<Rx FIFO 1 Watermark Reached */
4239#define FDCAN_IR_RF1F_Pos (6U)
4240#define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) /*!< 0x00000040 */
4241#define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */
4242#define FDCAN_IR_RF1L_Pos (7U)
4243#define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) /*!< 0x00000080 */
4244#define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
4245#define FDCAN_IR_HPM_Pos (8U)
4246#define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) /*!< 0x00000100 */
4247#define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */
4248#define FDCAN_IR_TC_Pos (9U)
4249#define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) /*!< 0x00000200 */
4250#define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */
4251#define FDCAN_IR_TCF_Pos (10U)
4252#define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) /*!< 0x00000400 */
4253#define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */
4254#define FDCAN_IR_TFE_Pos (11U)
4255#define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) /*!< 0x00000800 */
4256#define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */
4257#define FDCAN_IR_TEFN_Pos (12U)
4258#define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) /*!< 0x00001000 */
4259#define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */
4260#define FDCAN_IR_TEFW_Pos (13U)
4261#define FDCAN_IR_TEFW_Msk (0x1UL << FDCAN_IR_TEFW_Pos) /*!< 0x00002000 */
4262#define FDCAN_IR_TEFW FDCAN_IR_TEFW_Msk /*!<Tx Event FIFO Watermark Reached */
4263#define FDCAN_IR_TEFF_Pos (14U)
4264#define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) /*!< 0x00004000 */
4265#define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */
4266#define FDCAN_IR_TEFL_Pos (15U)
4267#define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) /*!< 0x00008000 */
4268#define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */
4269#define FDCAN_IR_TSW_Pos (16U)
4270#define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) /*!< 0x00010000 */
4271#define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */
4272#define FDCAN_IR_MRAF_Pos (17U)
4273#define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) /*!< 0x00020000 */
4274#define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */
4275#define FDCAN_IR_TOO_Pos (18U)
4276#define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) /*!< 0x00040000 */
4277#define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */
4278#define FDCAN_IR_DRX_Pos (19U)
4279#define FDCAN_IR_DRX_Msk (0x1UL << FDCAN_IR_DRX_Pos) /*!< 0x00080000 */
4280#define FDCAN_IR_DRX FDCAN_IR_DRX_Msk /*!<Message stored to Dedicated Rx Buffer */
4281#define FDCAN_IR_ELO_Pos (22U)
4282#define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) /*!< 0x00400000 */
4283#define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */
4284#define FDCAN_IR_EP_Pos (23U)
4285#define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) /*!< 0x00800000 */
4286#define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */
4287#define FDCAN_IR_EW_Pos (24U)
4288#define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) /*!< 0x01000000 */
4289#define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */
4290#define FDCAN_IR_BO_Pos (25U)
4291#define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) /*!< 0x02000000 */
4292#define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */
4293#define FDCAN_IR_WDI_Pos (26U)
4294#define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) /*!< 0x04000000 */
4295#define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */
4296#define FDCAN_IR_PEA_Pos (27U)
4297#define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) /*!< 0x08000000 */
4298#define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */
4299#define FDCAN_IR_PED_Pos (28U)
4300#define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) /*!< 0x10000000 */
4301#define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */
4302#define FDCAN_IR_ARA_Pos (29U)
4303#define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) /*!< 0x20000000 */
4304#define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */
4305
4306/***************** Bit definition for FDCAN_IE register **********************/
4307#define FDCAN_IE_RF0NE_Pos (0U)
4308#define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */
4309#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */
4310#define FDCAN_IE_RF0WE_Pos (1U)
4311#define FDCAN_IE_RF0WE_Msk (0x1UL << FDCAN_IE_RF0WE_Pos) /*!< 0x00000002 */
4312#define FDCAN_IE_RF0WE FDCAN_IE_RF0WE_Msk /*!<Rx FIFO 0 Watermark Reached Enable */
4313#define FDCAN_IE_RF0FE_Pos (2U)
4314#define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) /*!< 0x00000004 */
4315#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */
4316#define FDCAN_IE_RF0LE_Pos (3U)
4317#define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) /*!< 0x00000008 */
4318#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */
4319#define FDCAN_IE_RF1NE_Pos (4U)
4320#define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) /*!< 0x00000010 */
4321#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */
4322#define FDCAN_IE_RF1WE_Pos (5U)
4323#define FDCAN_IE_RF1WE_Msk (0x1UL << FDCAN_IE_RF1WE_Pos) /*!< 0x00000020 */
4324#define FDCAN_IE_RF1WE FDCAN_IE_RF1WE_Msk /*!<Rx FIFO 1 Watermark Reached Enable */
4325#define FDCAN_IE_RF1FE_Pos (6U)
4326#define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) /*!< 0x00000040 */
4327#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */
4328#define FDCAN_IE_RF1LE_Pos (7U)
4329#define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) /*!< 0x00000080 */
4330#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */
4331#define FDCAN_IE_HPME_Pos (8U)
4332#define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) /*!< 0x00000100 */
4333#define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */
4334#define FDCAN_IE_TCE_Pos (9U)
4335#define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) /*!< 0x00000200 */
4336#define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */
4337#define FDCAN_IE_TCFE_Pos (10U)
4338#define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) /*!< 0x00000400 */
4339#define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable */
4340#define FDCAN_IE_TFEE_Pos (11U)
4341#define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) /*!< 0x00000800 */
4342#define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */
4343#define FDCAN_IE_TEFNE_Pos (12U)
4344#define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) /*!< 0x00001000 */
4345#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */
4346#define FDCAN_IE_TEFWE_Pos (13U)
4347#define FDCAN_IE_TEFWE_Msk (0x1UL << FDCAN_IE_TEFWE_Pos) /*!< 0x00002000 */
4348#define FDCAN_IE_TEFWE FDCAN_IE_TEFWE_Msk /*!<Tx Event FIFO Watermark Reached Enable */
4349#define FDCAN_IE_TEFFE_Pos (14U)
4350#define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) /*!< 0x00004000 */
4351#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */
4352#define FDCAN_IE_TEFLE_Pos (15U)
4353#define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) /*!< 0x00008000 */
4354#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */
4355#define FDCAN_IE_TSWE_Pos (16U)
4356#define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) /*!< 0x00010000 */
4357#define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */
4358#define FDCAN_IE_MRAFE_Pos (17U)
4359#define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) /*!< 0x00020000 */
4360#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */
4361#define FDCAN_IE_TOOE_Pos (18U)
4362#define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) /*!< 0x00040000 */
4363#define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */
4364#define FDCAN_IE_DRXE_Pos (19U)
4365#define FDCAN_IE_DRXE_Msk (0x1UL << FDCAN_IE_DRXE_Pos) /*!< 0x00080000 */
4366#define FDCAN_IE_DRXE FDCAN_IE_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Enable */
4367#define FDCAN_IE_BECE_Pos (20U)
4368#define FDCAN_IE_BECE_Msk (0x1UL << FDCAN_IE_BECE_Pos) /*!< 0x00100000 */
4369#define FDCAN_IE_BECE FDCAN_IE_BECE_Msk /*!<Bit Error Corrected Interrupt Enable */
4370#define FDCAN_IE_BEUE_Pos (21U)
4371#define FDCAN_IE_BEUE_Msk (0x1UL << FDCAN_IE_BEUE_Pos) /*!< 0x00200000 */
4372#define FDCAN_IE_BEUE FDCAN_IE_BEUE_Msk /*!<Bit Error Uncorrected Interrupt Enable */
4373#define FDCAN_IE_ELOE_Pos (22U)
4374#define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) /*!< 0x00400000 */
4375#define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */
4376#define FDCAN_IE_EPE_Pos (23U)
4377#define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) /*!< 0x00800000 */
4378#define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */
4379#define FDCAN_IE_EWE_Pos (24U)
4380#define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) /*!< 0x01000000 */
4381#define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */
4382#define FDCAN_IE_BOE_Pos (25U)
4383#define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) /*!< 0x02000000 */
4384#define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */
4385#define FDCAN_IE_WDIE_Pos (26U)
4386#define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) /*!< 0x04000000 */
4387#define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */
4388#define FDCAN_IE_PEAE_Pos (27U)
4389#define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) /*!< 0x08000000 */
4390#define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable */
4391#define FDCAN_IE_PEDE_Pos (28U)
4392#define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) /*!< 0x10000000 */
4393#define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */
4394#define FDCAN_IE_ARAE_Pos (29U)
4395#define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) /*!< 0x20000000 */
4396#define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */
4397
4398/***************** Bit definition for FDCAN_ILS register **********************/
4399#define FDCAN_ILS_RF0NL_Pos (0U)
4400#define FDCAN_ILS_RF0NL_Msk (0x1UL << FDCAN_ILS_RF0NL_Pos) /*!< 0x00000001 */
4401#define FDCAN_ILS_RF0NL FDCAN_ILS_RF0NL_Msk /*!<Rx FIFO 0 New Message Line */
4402#define FDCAN_ILS_RF0WL_Pos (1U)
4403#define FDCAN_ILS_RF0WL_Msk (0x1UL << FDCAN_ILS_RF0WL_Pos) /*!< 0x00000002 */
4404#define FDCAN_ILS_RF0WL FDCAN_ILS_RF0WL_Msk /*!<Rx FIFO 0 Watermark Reached Line */
4405#define FDCAN_ILS_RF0FL_Pos (2U)
4406#define FDCAN_ILS_RF0FL_Msk (0x1UL << FDCAN_ILS_RF0FL_Pos) /*!< 0x00000004 */
4407#define FDCAN_ILS_RF0FL FDCAN_ILS_RF0FL_Msk /*!<Rx FIFO 0 Full Line */
4408#define FDCAN_ILS_RF0LL_Pos (3U)
4409#define FDCAN_ILS_RF0LL_Msk (0x1UL << FDCAN_ILS_RF0LL_Pos) /*!< 0x00000008 */
4410#define FDCAN_ILS_RF0LL FDCAN_ILS_RF0LL_Msk /*!<Rx FIFO 0 Message Lost Line */
4411#define FDCAN_ILS_RF1NL_Pos (4U)
4412#define FDCAN_ILS_RF1NL_Msk (0x1UL << FDCAN_ILS_RF1NL_Pos) /*!< 0x00000010 */
4413#define FDCAN_ILS_RF1NL FDCAN_ILS_RF1NL_Msk /*!<Rx FIFO 1 New Message Line */
4414#define FDCAN_ILS_RF1WL_Pos (5U)
4415#define FDCAN_ILS_RF1WL_Msk (0x1UL << FDCAN_ILS_RF1WL_Pos) /*!< 0x00000020 */
4416#define FDCAN_ILS_RF1WL FDCAN_ILS_RF1WL_Msk /*!<Rx FIFO 1 Watermark Reached Line */
4417#define FDCAN_ILS_RF1FL_Pos (6U)
4418#define FDCAN_ILS_RF1FL_Msk (0x1UL << FDCAN_ILS_RF1FL_Pos) /*!< 0x00000040 */
4419#define FDCAN_ILS_RF1FL FDCAN_ILS_RF1FL_Msk /*!<Rx FIFO 1 Full Line */
4420#define FDCAN_ILS_RF1LL_Pos (7U)
4421#define FDCAN_ILS_RF1LL_Msk (0x1UL << FDCAN_ILS_RF1LL_Pos) /*!< 0x00000080 */
4422#define FDCAN_ILS_RF1LL FDCAN_ILS_RF1LL_Msk /*!<Rx FIFO 1 Message Lost Line */
4423#define FDCAN_ILS_HPML_Pos (8U)
4424#define FDCAN_ILS_HPML_Msk (0x1UL << FDCAN_ILS_HPML_Pos) /*!< 0x00000100 */
4425#define FDCAN_ILS_HPML FDCAN_ILS_HPML_Msk /*!<High Priority Message Line */
4426#define FDCAN_ILS_TCL_Pos (9U)
4427#define FDCAN_ILS_TCL_Msk (0x1UL << FDCAN_ILS_TCL_Pos) /*!< 0x00000200 */
4428#define FDCAN_ILS_TCL FDCAN_ILS_TCL_Msk /*!<Transmission Completed Line */
4429#define FDCAN_ILS_TCFL_Pos (10U)
4430#define FDCAN_ILS_TCFL_Msk (0x1UL << FDCAN_ILS_TCFL_Pos) /*!< 0x00000400 */
4431#define FDCAN_ILS_TCFL FDCAN_ILS_TCFL_Msk /*!<Transmission Cancellation Finished Line */
4432#define FDCAN_ILS_TFEL_Pos (11U)
4433#define FDCAN_ILS_TFEL_Msk (0x1UL << FDCAN_ILS_TFEL_Pos) /*!< 0x00000800 */
4434#define FDCAN_ILS_TFEL FDCAN_ILS_TFEL_Msk /*!<Tx FIFO Empty Line */
4435#define FDCAN_ILS_TEFNL_Pos (12U)
4436#define FDCAN_ILS_TEFNL_Msk (0x1UL << FDCAN_ILS_TEFNL_Pos) /*!< 0x00001000 */
4437#define FDCAN_ILS_TEFNL FDCAN_ILS_TEFNL_Msk /*!<Tx Event FIFO New Entry Line */
4438#define FDCAN_ILS_TEFWL_Pos (13U)
4439#define FDCAN_ILS_TEFWL_Msk (0x1UL << FDCAN_ILS_TEFWL_Pos) /*!< 0x00002000 */
4440#define FDCAN_ILS_TEFWL FDCAN_ILS_TEFWL_Msk /*!<Tx Event FIFO Watermark Reached Line */
4441#define FDCAN_ILS_TEFFL_Pos (14U)
4442#define FDCAN_ILS_TEFFL_Msk (0x1UL << FDCAN_ILS_TEFFL_Pos) /*!< 0x00004000 */
4443#define FDCAN_ILS_TEFFL FDCAN_ILS_TEFFL_Msk /*!<Tx Event FIFO Full Line */
4444#define FDCAN_ILS_TEFLL_Pos (15U)
4445#define FDCAN_ILS_TEFLL_Msk (0x1UL << FDCAN_ILS_TEFLL_Pos) /*!< 0x00008000 */
4446#define FDCAN_ILS_TEFLL FDCAN_ILS_TEFLL_Msk /*!<Tx Event FIFO Element Lost Line */
4447#define FDCAN_ILS_TSWL_Pos (16U)
4448#define FDCAN_ILS_TSWL_Msk (0x1UL << FDCAN_ILS_TSWL_Pos) /*!< 0x00010000 */
4449#define FDCAN_ILS_TSWL FDCAN_ILS_TSWL_Msk /*!<Timestamp Wraparound Line */
4450#define FDCAN_ILS_MRAFE_Pos (17U)
4451#define FDCAN_ILS_MRAFE_Msk (0x1UL << FDCAN_ILS_MRAFE_Pos) /*!< 0x00020000 */
4452#define FDCAN_ILS_MRAFE FDCAN_ILS_MRAFE_Msk /*!<Message RAM Access Failure Line */
4453#define FDCAN_ILS_TOOE_Pos (18U)
4454#define FDCAN_ILS_TOOE_Msk (0x1UL << FDCAN_ILS_TOOE_Pos) /*!< 0x00040000 */
4455#define FDCAN_ILS_TOOE FDCAN_ILS_TOOE_Msk /*!<Timeout Occurred Line */
4456#define FDCAN_ILS_DRXE_Pos (19U)
4457#define FDCAN_ILS_DRXE_Msk (0x1UL << FDCAN_ILS_DRXE_Pos) /*!< 0x00080000 */
4458#define FDCAN_ILS_DRXE FDCAN_ILS_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Line */
4459#define FDCAN_ILS_BECE_Pos (20U)
4460#define FDCAN_ILS_BECE_Msk (0x1UL << FDCAN_ILS_BECE_Pos) /*!< 0x00100000 */
4461#define FDCAN_ILS_BECE FDCAN_ILS_BECE_Msk /*!<Bit Error Corrected Interrupt Line */
4462#define FDCAN_ILS_BEUE_Pos (21U)
4463#define FDCAN_ILS_BEUE_Msk (0x1UL << FDCAN_ILS_BEUE_Pos) /*!< 0x00200000 */
4464#define FDCAN_ILS_BEUE FDCAN_ILS_BEUE_Msk /*!<Bit Error Uncorrected Interrupt Line */
4465#define FDCAN_ILS_ELOE_Pos (22U)
4466#define FDCAN_ILS_ELOE_Msk (0x1UL << FDCAN_ILS_ELOE_Pos) /*!< 0x00400000 */
4467#define FDCAN_ILS_ELOE FDCAN_ILS_ELOE_Msk /*!<Error Logging Overflow Line */
4468#define FDCAN_ILS_EPE_Pos (23U)
4469#define FDCAN_ILS_EPE_Msk (0x1UL << FDCAN_ILS_EPE_Pos) /*!< 0x00800000 */
4470#define FDCAN_ILS_EPE FDCAN_ILS_EPE_Msk /*!<Error Passive Line */
4471#define FDCAN_ILS_EWE_Pos (24U)
4472#define FDCAN_ILS_EWE_Msk (0x1UL << FDCAN_ILS_EWE_Pos) /*!< 0x01000000 */
4473#define FDCAN_ILS_EWE FDCAN_ILS_EWE_Msk /*!<Warning Status Line */
4474#define FDCAN_ILS_BOE_Pos (25U)
4475#define FDCAN_ILS_BOE_Msk (0x1UL << FDCAN_ILS_BOE_Pos) /*!< 0x02000000 */
4476#define FDCAN_ILS_BOE FDCAN_ILS_BOE_Msk /*!<Bus_Off Status Line */
4477#define FDCAN_ILS_WDIE_Pos (26U)
4478#define FDCAN_ILS_WDIE_Msk (0x1UL << FDCAN_ILS_WDIE_Pos) /*!< 0x04000000 */
4479#define FDCAN_ILS_WDIE FDCAN_ILS_WDIE_Msk /*!<Watchdog Interrupt Line */
4480#define FDCAN_ILS_PEAE_Pos (27U)
4481#define FDCAN_ILS_PEAE_Msk (0x1UL << FDCAN_ILS_PEAE_Pos) /*!< 0x08000000 */
4482#define FDCAN_ILS_PEAE FDCAN_ILS_PEAE_Msk /*!<Protocol Error in Arbitration Phase Line */
4483#define FDCAN_ILS_PEDE_Pos (28U)
4484#define FDCAN_ILS_PEDE_Msk (0x1UL << FDCAN_ILS_PEDE_Pos) /*!< 0x10000000 */
4485#define FDCAN_ILS_PEDE FDCAN_ILS_PEDE_Msk /*!<Protocol Error in Data Phase Line */
4486#define FDCAN_ILS_ARAE_Pos (29U)
4487#define FDCAN_ILS_ARAE_Msk (0x1UL << FDCAN_ILS_ARAE_Pos) /*!< 0x20000000 */
4488#define FDCAN_ILS_ARAE FDCAN_ILS_ARAE_Msk /*!<Access to Reserved Address Line */
4489
4490/***************** Bit definition for FDCAN_ILE register **********************/
4491#define FDCAN_ILE_EINT0_Pos (0U)
4492#define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */
4493#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */
4494#define FDCAN_ILE_EINT1_Pos (1U)
4495#define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */
4496#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */
4497
4498/***************** Bit definition for FDCAN_GFC register **********************/
4499#define FDCAN_GFC_RRFE_Pos (0U)
4500#define FDCAN_GFC_RRFE_Msk (0x1UL << FDCAN_GFC_RRFE_Pos) /*!< 0x00000001 */
4501#define FDCAN_GFC_RRFE FDCAN_GFC_RRFE_Msk /*!<Reject Remote Frames Extended */
4502#define FDCAN_GFC_RRFS_Pos (1U)
4503#define FDCAN_GFC_RRFS_Msk (0x1UL << FDCAN_GFC_RRFS_Pos) /*!< 0x00000002 */
4504#define FDCAN_GFC_RRFS FDCAN_GFC_RRFS_Msk /*!<Reject Remote Frames Standard */
4505#define FDCAN_GFC_ANFE_Pos (2U)
4506#define FDCAN_GFC_ANFE_Msk (0x3UL << FDCAN_GFC_ANFE_Pos) /*!< 0x0000000C */
4507#define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */
4508#define FDCAN_GFC_ANFS_Pos (4U)
4509#define FDCAN_GFC_ANFS_Msk (0x3UL << FDCAN_GFC_ANFS_Pos) /*!< 0x00000030 */
4510#define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */
4511
4512/***************** Bit definition for FDCAN_SIDFC register ********************/
4513#define FDCAN_SIDFC_FLSSA_Pos (2U)
4514#define FDCAN_SIDFC_FLSSA_Msk (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos) /*!< 0x0000FFFC */
4515#define FDCAN_SIDFC_FLSSA FDCAN_SIDFC_FLSSA_Msk /*!<Filter List Standard Start Address */
4516#define FDCAN_SIDFC_LSS_Pos (16U)
4517#define FDCAN_SIDFC_LSS_Msk (0xFFUL << FDCAN_SIDFC_LSS_Pos) /*!< 0x00FF0000 */
4518#define FDCAN_SIDFC_LSS FDCAN_SIDFC_LSS_Msk /*!<List Size Standard */
4519
4520/***************** Bit definition for FDCAN_XIDFC register ********************/
4521#define FDCAN_XIDFC_FLESA_Pos (2U)
4522#define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
4523#define FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_Msk /*!<Filter List Standard Start Address */
4524#define FDCAN_XIDFC_LSE_Pos (16U)
4525#define FDCAN_XIDFC_LSE_Msk (0x7FUL << FDCAN_XIDFC_LSE_Pos) /*!< 0x007F0000 */
4526#define FDCAN_XIDFC_LSE FDCAN_XIDFC_LSE_Msk /*!<List Size Extended */
4527
4528/***************** Bit definition for FDCAN_XIDAM register ********************/
4529#define FDCAN_XIDAM_EIDM_Pos (0U)
4530#define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */
4531#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */
4532
4533/***************** Bit definition for FDCAN_HPMS register *********************/
4534#define FDCAN_HPMS_BIDX_Pos (0U)
4535#define FDCAN_HPMS_BIDX_Msk (0x3FUL << FDCAN_HPMS_BIDX_Pos) /*!< 0x0000003F */
4536#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */
4537#define FDCAN_HPMS_MSI_Pos (6U)
4538#define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */
4539#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */
4540#define FDCAN_HPMS_FIDX_Pos (8U)
4541#define FDCAN_HPMS_FIDX_Msk (0x7FUL << FDCAN_HPMS_FIDX_Pos) /*!< 0x00007F00 */
4542#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */
4543#define FDCAN_HPMS_FLST_Pos (15U)
4544#define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */
4545#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */
4546
4547/***************** Bit definition for FDCAN_NDAT1 register ********************/
4548#define FDCAN_NDAT1_ND0_Pos (0U)
4549#define FDCAN_NDAT1_ND0_Msk (0x1UL << FDCAN_NDAT1_ND0_Pos) /*!< 0x00000001 */
4550#define FDCAN_NDAT1_ND0 FDCAN_NDAT1_ND0_Msk /*!<New Data flag of Rx Buffer 0 */
4551#define FDCAN_NDAT1_ND1_Pos (1U)
4552#define FDCAN_NDAT1_ND1_Msk (0x1UL << FDCAN_NDAT1_ND1_Pos) /*!< 0x00000002 */
4553#define FDCAN_NDAT1_ND1 FDCAN_NDAT1_ND1_Msk /*!<New Data flag of Rx Buffer 1 */
4554#define FDCAN_NDAT1_ND2_Pos (2U)
4555#define FDCAN_NDAT1_ND2_Msk (0x1UL << FDCAN_NDAT1_ND2_Pos) /*!< 0x00000004 */
4556#define FDCAN_NDAT1_ND2 FDCAN_NDAT1_ND2_Msk /*!<New Data flag of Rx Buffer 2 */
4557#define FDCAN_NDAT1_ND3_Pos (3U)
4558#define FDCAN_NDAT1_ND3_Msk (0x1UL << FDCAN_NDAT1_ND3_Pos) /*!< 0x00000008 */
4559#define FDCAN_NDAT1_ND3 FDCAN_NDAT1_ND3_Msk /*!<New Data flag of Rx Buffer 3 */
4560#define FDCAN_NDAT1_ND4_Pos (4U)
4561#define FDCAN_NDAT1_ND4_Msk (0x1UL << FDCAN_NDAT1_ND4_Pos) /*!< 0x00000010 */
4562#define FDCAN_NDAT1_ND4 FDCAN_NDAT1_ND4_Msk /*!<New Data flag of Rx Buffer 4 */
4563#define FDCAN_NDAT1_ND5_Pos (5U)
4564#define FDCAN_NDAT1_ND5_Msk (0x1UL << FDCAN_NDAT1_ND5_Pos) /*!< 0x00000020 */
4565#define FDCAN_NDAT1_ND5 FDCAN_NDAT1_ND5_Msk /*!<New Data flag of Rx Buffer 5 */
4566#define FDCAN_NDAT1_ND6_Pos (6U)
4567#define FDCAN_NDAT1_ND6_Msk (0x1UL << FDCAN_NDAT1_ND6_Pos) /*!< 0x00000040 */
4568#define FDCAN_NDAT1_ND6 FDCAN_NDAT1_ND6_Msk /*!<New Data flag of Rx Buffer 6 */
4569#define FDCAN_NDAT1_ND7_Pos (7U)
4570#define FDCAN_NDAT1_ND7_Msk (0x1UL << FDCAN_NDAT1_ND7_Pos) /*!< 0x00000080 */
4571#define FDCAN_NDAT1_ND7 FDCAN_NDAT1_ND7_Msk /*!<New Data flag of Rx Buffer 7 */
4572#define FDCAN_NDAT1_ND8_Pos (8U)
4573#define FDCAN_NDAT1_ND8_Msk (0x1UL << FDCAN_NDAT1_ND8_Pos) /*!< 0x00000100 */
4574#define FDCAN_NDAT1_ND8 FDCAN_NDAT1_ND8_Msk /*!<New Data flag of Rx Buffer 8 */
4575#define FDCAN_NDAT1_ND9_Pos (9U)
4576#define FDCAN_NDAT1_ND9_Msk (0x1UL << FDCAN_NDAT1_ND9_Pos) /*!< 0x00000200 */
4577#define FDCAN_NDAT1_ND9 FDCAN_NDAT1_ND9_Msk /*!<New Data flag of Rx Buffer 9 */
4578#define FDCAN_NDAT1_ND10_Pos (10U)
4579#define FDCAN_NDAT1_ND10_Msk (0x1UL << FDCAN_NDAT1_ND10_Pos) /*!< 0x00000400 */
4580#define FDCAN_NDAT1_ND10 FDCAN_NDAT1_ND10_Msk /*!<New Data flag of Rx Buffer 10 */
4581#define FDCAN_NDAT1_ND11_Pos (11U)
4582#define FDCAN_NDAT1_ND11_Msk (0x1UL << FDCAN_NDAT1_ND11_Pos) /*!< 0x00000800 */
4583#define FDCAN_NDAT1_ND11 FDCAN_NDAT1_ND11_Msk /*!<New Data flag of Rx Buffer 11 */
4584#define FDCAN_NDAT1_ND12_Pos (12U)
4585#define FDCAN_NDAT1_ND12_Msk (0x1UL << FDCAN_NDAT1_ND12_Pos) /*!< 0x00001000 */
4586#define FDCAN_NDAT1_ND12 FDCAN_NDAT1_ND12_Msk /*!<New Data flag of Rx Buffer 12 */
4587#define FDCAN_NDAT1_ND13_Pos (13U)
4588#define FDCAN_NDAT1_ND13_Msk (0x1UL << FDCAN_NDAT1_ND13_Pos) /*!< 0x00002000 */
4589#define FDCAN_NDAT1_ND13 FDCAN_NDAT1_ND13_Msk /*!<New Data flag of Rx Buffer 13 */
4590#define FDCAN_NDAT1_ND14_Pos (14U)
4591#define FDCAN_NDAT1_ND14_Msk (0x1UL << FDCAN_NDAT1_ND14_Pos) /*!< 0x00004000 */
4592#define FDCAN_NDAT1_ND14 FDCAN_NDAT1_ND14_Msk /*!<New Data flag of Rx Buffer 14 */
4593#define FDCAN_NDAT1_ND15_Pos (15U)
4594#define FDCAN_NDAT1_ND15_Msk (0x1UL << FDCAN_NDAT1_ND15_Pos) /*!< 0x00008000 */
4595#define FDCAN_NDAT1_ND15 FDCAN_NDAT1_ND15_Msk /*!<New Data flag of Rx Buffer 15 */
4596#define FDCAN_NDAT1_ND16_Pos (16U)
4597#define FDCAN_NDAT1_ND16_Msk (0x1UL << FDCAN_NDAT1_ND16_Pos) /*!< 0x00010000 */
4598#define FDCAN_NDAT1_ND16 FDCAN_NDAT1_ND16_Msk /*!<New Data flag of Rx Buffer 16 */
4599#define FDCAN_NDAT1_ND17_Pos (17U)
4600#define FDCAN_NDAT1_ND17_Msk (0x1UL << FDCAN_NDAT1_ND17_Pos) /*!< 0x00020000 */
4601#define FDCAN_NDAT1_ND17 FDCAN_NDAT1_ND17_Msk /*!<New Data flag of Rx Buffer 17 */
4602#define FDCAN_NDAT1_ND18_Pos (18U)
4603#define FDCAN_NDAT1_ND18_Msk (0x1UL << FDCAN_NDAT1_ND18_Pos) /*!< 0x00040000 */
4604#define FDCAN_NDAT1_ND18 FDCAN_NDAT1_ND18_Msk /*!<New Data flag of Rx Buffer 18 */
4605#define FDCAN_NDAT1_ND19_Pos (19U)
4606#define FDCAN_NDAT1_ND19_Msk (0x1UL << FDCAN_NDAT1_ND19_Pos) /*!< 0x00080000 */
4607#define FDCAN_NDAT1_ND19 FDCAN_NDAT1_ND19_Msk /*!<New Data flag of Rx Buffer 19 */
4608#define FDCAN_NDAT1_ND20_Pos (20U)
4609#define FDCAN_NDAT1_ND20_Msk (0x1UL << FDCAN_NDAT1_ND20_Pos) /*!< 0x00100000 */
4610#define FDCAN_NDAT1_ND20 FDCAN_NDAT1_ND20_Msk /*!<New Data flag of Rx Buffer 20 */
4611#define FDCAN_NDAT1_ND21_Pos (21U)
4612#define FDCAN_NDAT1_ND21_Msk (0x1UL << FDCAN_NDAT1_ND21_Pos) /*!< 0x00200000 */
4613#define FDCAN_NDAT1_ND21 FDCAN_NDAT1_ND21_Msk /*!<New Data flag of Rx Buffer 21 */
4614#define FDCAN_NDAT1_ND22_Pos (22U)
4615#define FDCAN_NDAT1_ND22_Msk (0x1UL << FDCAN_NDAT1_ND22_Pos) /*!< 0x00400000 */
4616#define FDCAN_NDAT1_ND22 FDCAN_NDAT1_ND22_Msk /*!<New Data flag of Rx Buffer 22 */
4617#define FDCAN_NDAT1_ND23_Pos (23U)
4618#define FDCAN_NDAT1_ND23_Msk (0x1UL << FDCAN_NDAT1_ND23_Pos) /*!< 0x00800000 */
4619#define FDCAN_NDAT1_ND23 FDCAN_NDAT1_ND23_Msk /*!<New Data flag of Rx Buffer 23 */
4620#define FDCAN_NDAT1_ND24_Pos (24U)
4621#define FDCAN_NDAT1_ND24_Msk (0x1UL << FDCAN_NDAT1_ND24_Pos) /*!< 0x01000000 */
4622#define FDCAN_NDAT1_ND24 FDCAN_NDAT1_ND24_Msk /*!<New Data flag of Rx Buffer 24 */
4623#define FDCAN_NDAT1_ND25_Pos (25U)
4624#define FDCAN_NDAT1_ND25_Msk (0x1UL << FDCAN_NDAT1_ND25_Pos) /*!< 0x02000000 */
4625#define FDCAN_NDAT1_ND25 FDCAN_NDAT1_ND25_Msk /*!<New Data flag of Rx Buffer 25 */
4626#define FDCAN_NDAT1_ND26_Pos (26U)
4627#define FDCAN_NDAT1_ND26_Msk (0x1UL << FDCAN_NDAT1_ND26_Pos) /*!< 0x04000000 */
4628#define FDCAN_NDAT1_ND26 FDCAN_NDAT1_ND26_Msk /*!<New Data flag of Rx Buffer 26 */
4629#define FDCAN_NDAT1_ND27_Pos (27U)
4630#define FDCAN_NDAT1_ND27_Msk (0x1UL << FDCAN_NDAT1_ND27_Pos) /*!< 0x08000000 */
4631#define FDCAN_NDAT1_ND27 FDCAN_NDAT1_ND27_Msk /*!<New Data flag of Rx Buffer 27 */
4632#define FDCAN_NDAT1_ND28_Pos (28U)
4633#define FDCAN_NDAT1_ND28_Msk (0x1UL << FDCAN_NDAT1_ND28_Pos) /*!< 0x10000000 */
4634#define FDCAN_NDAT1_ND28 FDCAN_NDAT1_ND28_Msk /*!<New Data flag of Rx Buffer 28 */
4635#define FDCAN_NDAT1_ND29_Pos (29U)
4636#define FDCAN_NDAT1_ND29_Msk (0x1UL << FDCAN_NDAT1_ND29_Pos) /*!< 0x20000000 */
4637#define FDCAN_NDAT1_ND29 FDCAN_NDAT1_ND29_Msk /*!<New Data flag of Rx Buffer 29 */
4638#define FDCAN_NDAT1_ND30_Pos (30U)
4639#define FDCAN_NDAT1_ND30_Msk (0x1UL << FDCAN_NDAT1_ND30_Pos) /*!< 0x40000000 */
4640#define FDCAN_NDAT1_ND30 FDCAN_NDAT1_ND30_Msk /*!<New Data flag of Rx Buffer 30 */
4641#define FDCAN_NDAT1_ND31_Pos (31U)
4642#define FDCAN_NDAT1_ND31_Msk (0x1UL << FDCAN_NDAT1_ND31_Pos) /*!< 0x80000000 */
4643#define FDCAN_NDAT1_ND31 FDCAN_NDAT1_ND31_Msk /*!<New Data flag of Rx Buffer 31 */
4644
4645/***************** Bit definition for FDCAN_NDAT2 register ********************/
4646#define FDCAN_NDAT2_ND32_Pos (0U)
4647#define FDCAN_NDAT2_ND32_Msk (0x1UL << FDCAN_NDAT2_ND32_Pos) /*!< 0x00000001 */
4648#define FDCAN_NDAT2_ND32 FDCAN_NDAT2_ND32_Msk /*!<New Data flag of Rx Buffer 32 */
4649#define FDCAN_NDAT2_ND33_Pos (1U)
4650#define FDCAN_NDAT2_ND33_Msk (0x1UL << FDCAN_NDAT2_ND33_Pos) /*!< 0x00000002 */
4651#define FDCAN_NDAT2_ND33 FDCAN_NDAT2_ND33_Msk /*!<New Data flag of Rx Buffer 33 */
4652#define FDCAN_NDAT2_ND34_Pos (2U)
4653#define FDCAN_NDAT2_ND34_Msk (0x1UL << FDCAN_NDAT2_ND34_Pos) /*!< 0x00000004 */
4654#define FDCAN_NDAT2_ND34 FDCAN_NDAT2_ND34_Msk /*!<New Data flag of Rx Buffer 34 */
4655#define FDCAN_NDAT2_ND35_Pos (3U)
4656#define FDCAN_NDAT2_ND35_Msk (0x1UL << FDCAN_NDAT2_ND35_Pos) /*!< 0x00000008 */
4657#define FDCAN_NDAT2_ND35 FDCAN_NDAT2_ND35_Msk /*!<New Data flag of Rx Buffer 35 */
4658#define FDCAN_NDAT2_ND36_Pos (4U)
4659#define FDCAN_NDAT2_ND36_Msk (0x1UL << FDCAN_NDAT2_ND36_Pos) /*!< 0x00000010 */
4660#define FDCAN_NDAT2_ND36 FDCAN_NDAT2_ND36_Msk /*!<New Data flag of Rx Buffer 36 */
4661#define FDCAN_NDAT2_ND37_Pos (5U)
4662#define FDCAN_NDAT2_ND37_Msk (0x1UL << FDCAN_NDAT2_ND37_Pos) /*!< 0x00000020 */
4663#define FDCAN_NDAT2_ND37 FDCAN_NDAT2_ND37_Msk /*!<New Data flag of Rx Buffer 37 */
4664#define FDCAN_NDAT2_ND38_Pos (6U)
4665#define FDCAN_NDAT2_ND38_Msk (0x1UL << FDCAN_NDAT2_ND38_Pos) /*!< 0x00000040 */
4666#define FDCAN_NDAT2_ND38 FDCAN_NDAT2_ND38_Msk /*!<New Data flag of Rx Buffer 38 */
4667#define FDCAN_NDAT2_ND39_Pos (7U)
4668#define FDCAN_NDAT2_ND39_Msk (0x1UL << FDCAN_NDAT2_ND39_Pos) /*!< 0x00000080 */
4669#define FDCAN_NDAT2_ND39 FDCAN_NDAT2_ND39_Msk /*!<New Data flag of Rx Buffer 39 */
4670#define FDCAN_NDAT2_ND40_Pos (8U)
4671#define FDCAN_NDAT2_ND40_Msk (0x1UL << FDCAN_NDAT2_ND40_Pos) /*!< 0x00000100 */
4672#define FDCAN_NDAT2_ND40 FDCAN_NDAT2_ND40_Msk /*!<New Data flag of Rx Buffer 40 */
4673#define FDCAN_NDAT2_ND41_Pos (9U)
4674#define FDCAN_NDAT2_ND41_Msk (0x1UL << FDCAN_NDAT2_ND41_Pos) /*!< 0x00000200 */
4675#define FDCAN_NDAT2_ND41 FDCAN_NDAT2_ND41_Msk /*!<New Data flag of Rx Buffer 41 */
4676#define FDCAN_NDAT2_ND42_Pos (10U)
4677#define FDCAN_NDAT2_ND42_Msk (0x1UL << FDCAN_NDAT2_ND42_Pos) /*!< 0x00000400 */
4678#define FDCAN_NDAT2_ND42 FDCAN_NDAT2_ND42_Msk /*!<New Data flag of Rx Buffer 42 */
4679#define FDCAN_NDAT2_ND43_Pos (11U)
4680#define FDCAN_NDAT2_ND43_Msk (0x1UL << FDCAN_NDAT2_ND43_Pos) /*!< 0x00000800 */
4681#define FDCAN_NDAT2_ND43 FDCAN_NDAT2_ND43_Msk /*!<New Data flag of Rx Buffer 43 */
4682#define FDCAN_NDAT2_ND44_Pos (12U)
4683#define FDCAN_NDAT2_ND44_Msk (0x1UL << FDCAN_NDAT2_ND44_Pos) /*!< 0x00001000 */
4684#define FDCAN_NDAT2_ND44 FDCAN_NDAT2_ND44_Msk /*!<New Data flag of Rx Buffer 44 */
4685#define FDCAN_NDAT2_ND45_Pos (13U)
4686#define FDCAN_NDAT2_ND45_Msk (0x1UL << FDCAN_NDAT2_ND45_Pos) /*!< 0x00002000 */
4687#define FDCAN_NDAT2_ND45 FDCAN_NDAT2_ND45_Msk /*!<New Data flag of Rx Buffer 45 */
4688#define FDCAN_NDAT2_ND46_Pos (14U)
4689#define FDCAN_NDAT2_ND46_Msk (0x1UL << FDCAN_NDAT2_ND46_Pos) /*!< 0x00004000 */
4690#define FDCAN_NDAT2_ND46 FDCAN_NDAT2_ND46_Msk /*!<New Data flag of Rx Buffer 46 */
4691#define FDCAN_NDAT2_ND47_Pos (15U)
4692#define FDCAN_NDAT2_ND47_Msk (0x1UL << FDCAN_NDAT2_ND47_Pos) /*!< 0x00008000 */
4693#define FDCAN_NDAT2_ND47 FDCAN_NDAT2_ND47_Msk /*!<New Data flag of Rx Buffer 47 */
4694#define FDCAN_NDAT2_ND48_Pos (16U)
4695#define FDCAN_NDAT2_ND48_Msk (0x1UL << FDCAN_NDAT2_ND48_Pos) /*!< 0x00010000 */
4696#define FDCAN_NDAT2_ND48 FDCAN_NDAT2_ND48_Msk /*!<New Data flag of Rx Buffer 48 */
4697#define FDCAN_NDAT2_ND49_Pos (17U)
4698#define FDCAN_NDAT2_ND49_Msk (0x1UL << FDCAN_NDAT2_ND49_Pos) /*!< 0x00020000 */
4699#define FDCAN_NDAT2_ND49 FDCAN_NDAT2_ND49_Msk /*!<New Data flag of Rx Buffer 49 */
4700#define FDCAN_NDAT2_ND50_Pos (18U)
4701#define FDCAN_NDAT2_ND50_Msk (0x1UL << FDCAN_NDAT2_ND50_Pos) /*!< 0x00040000 */
4702#define FDCAN_NDAT2_ND50 FDCAN_NDAT2_ND50_Msk /*!<New Data flag of Rx Buffer 50 */
4703#define FDCAN_NDAT2_ND51_Pos (19U)
4704#define FDCAN_NDAT2_ND51_Msk (0x1UL << FDCAN_NDAT2_ND51_Pos) /*!< 0x00080000 */
4705#define FDCAN_NDAT2_ND51 FDCAN_NDAT2_ND51_Msk /*!<New Data flag of Rx Buffer 51 */
4706#define FDCAN_NDAT2_ND52_Pos (20U)
4707#define FDCAN_NDAT2_ND52_Msk (0x1UL << FDCAN_NDAT2_ND52_Pos) /*!< 0x00100000 */
4708#define FDCAN_NDAT2_ND52 FDCAN_NDAT2_ND52_Msk /*!<New Data flag of Rx Buffer 52 */
4709#define FDCAN_NDAT2_ND53_Pos (21U)
4710#define FDCAN_NDAT2_ND53_Msk (0x1UL << FDCAN_NDAT2_ND53_Pos) /*!< 0x00200000 */
4711#define FDCAN_NDAT2_ND53 FDCAN_NDAT2_ND53_Msk /*!<New Data flag of Rx Buffer 53 */
4712#define FDCAN_NDAT2_ND54_Pos (22U)
4713#define FDCAN_NDAT2_ND54_Msk (0x1UL << FDCAN_NDAT2_ND54_Pos) /*!< 0x00400000 */
4714#define FDCAN_NDAT2_ND54 FDCAN_NDAT2_ND54_Msk /*!<New Data flag of Rx Buffer 54 */
4715#define FDCAN_NDAT2_ND55_Pos (23U)
4716#define FDCAN_NDAT2_ND55_Msk (0x1UL << FDCAN_NDAT2_ND55_Pos) /*!< 0x00800000 */
4717#define FDCAN_NDAT2_ND55 FDCAN_NDAT2_ND55_Msk /*!<New Data flag of Rx Buffer 55 */
4718#define FDCAN_NDAT2_ND56_Pos (24U)
4719#define FDCAN_NDAT2_ND56_Msk (0x1UL << FDCAN_NDAT2_ND56_Pos) /*!< 0x01000000 */
4720#define FDCAN_NDAT2_ND56 FDCAN_NDAT2_ND56_Msk /*!<New Data flag of Rx Buffer 56 */
4721#define FDCAN_NDAT2_ND57_Pos (25U)
4722#define FDCAN_NDAT2_ND57_Msk (0x1UL << FDCAN_NDAT2_ND57_Pos) /*!< 0x02000000 */
4723#define FDCAN_NDAT2_ND57 FDCAN_NDAT2_ND57_Msk /*!<New Data flag of Rx Buffer 57 */
4724#define FDCAN_NDAT2_ND58_Pos (26U)
4725#define FDCAN_NDAT2_ND58_Msk (0x1UL << FDCAN_NDAT2_ND58_Pos) /*!< 0x04000000 */
4726#define FDCAN_NDAT2_ND58 FDCAN_NDAT2_ND58_Msk /*!<New Data flag of Rx Buffer 58 */
4727#define FDCAN_NDAT2_ND59_Pos (27U)
4728#define FDCAN_NDAT2_ND59_Msk (0x1UL << FDCAN_NDAT2_ND59_Pos) /*!< 0x08000000 */
4729#define FDCAN_NDAT2_ND59 FDCAN_NDAT2_ND59_Msk /*!<New Data flag of Rx Buffer 59 */
4730#define FDCAN_NDAT2_ND60_Pos (28U)
4731#define FDCAN_NDAT2_ND60_Msk (0x1UL << FDCAN_NDAT2_ND60_Pos) /*!< 0x10000000 */
4732#define FDCAN_NDAT2_ND60 FDCAN_NDAT2_ND60_Msk /*!<New Data flag of Rx Buffer 60 */
4733#define FDCAN_NDAT2_ND61_Pos (29U)
4734#define FDCAN_NDAT2_ND61_Msk (0x1UL << FDCAN_NDAT2_ND61_Pos) /*!< 0x20000000 */
4735#define FDCAN_NDAT2_ND61 FDCAN_NDAT2_ND61_Msk /*!<New Data flag of Rx Buffer 61 */
4736#define FDCAN_NDAT2_ND62_Pos (30U)
4737#define FDCAN_NDAT2_ND62_Msk (0x1UL << FDCAN_NDAT2_ND62_Pos) /*!< 0x40000000 */
4738#define FDCAN_NDAT2_ND62 FDCAN_NDAT2_ND62_Msk /*!<New Data flag of Rx Buffer 62 */
4739#define FDCAN_NDAT2_ND63_Pos (31U)
4740#define FDCAN_NDAT2_ND63_Msk (0x1UL << FDCAN_NDAT2_ND63_Pos) /*!< 0x80000000 */
4741#define FDCAN_NDAT2_ND63 FDCAN_NDAT2_ND63_Msk /*!<New Data flag of Rx Buffer 63 */
4742
4743/***************** Bit definition for FDCAN_RXF0C register ********************/
4744#define FDCAN_RXF0C_F0SA_Pos (2U)
4745#define FDCAN_RXF0C_F0SA_Msk (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos) /*!< 0x0000FFFC */
4746#define FDCAN_RXF0C_F0SA FDCAN_RXF0C_F0SA_Msk /*!<Rx FIFO 0 Start Address */
4747#define FDCAN_RXF0C_F0S_Pos (16U)
4748#define FDCAN_RXF0C_F0S_Msk (0x7FUL << FDCAN_RXF0C_F0S_Pos) /*!< 0x007F0000 */
4749#define FDCAN_RXF0C_F0S FDCAN_RXF0C_F0S_Msk /*!<Number of Rx FIFO 0 elements */
4750#define FDCAN_RXF0C_F0WM_Pos (24U)
4751#define FDCAN_RXF0C_F0WM_Msk (0x7FUL << FDCAN_RXF0C_F0WM_Pos) /*!< 0x7F000000 */
4752#define FDCAN_RXF0C_F0WM FDCAN_RXF0C_F0WM_Msk /*!<FIFO 0 Watermark */
4753#define FDCAN_RXF0C_F0OM_Pos (31U)
4754#define FDCAN_RXF0C_F0OM_Msk (0x1UL << FDCAN_RXF0C_F0OM_Pos) /*!< 0x80000000 */
4755#define FDCAN_RXF0C_F0OM FDCAN_RXF0C_F0OM_Msk /*!<FIFO 0 Operation Mode */
4756
4757/***************** Bit definition for FDCAN_RXF0S register ********************/
4758#define FDCAN_RXF0S_F0FL_Pos (0U)
4759#define FDCAN_RXF0S_F0FL_Msk (0x7FUL << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000007F */
4760#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */
4761#define FDCAN_RXF0S_F0GI_Pos (8U)
4762#define FDCAN_RXF0S_F0GI_Msk (0x3FUL << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00003F00 */
4763#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */
4764#define FDCAN_RXF0S_F0PI_Pos (16U)
4765#define FDCAN_RXF0S_F0PI_Msk (0x3FUL << FDCAN_RXF0S_F0PI_Pos) /*!< 0x003F0000 */
4766#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */
4767#define FDCAN_RXF0S_F0F_Pos (24U)
4768#define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */
4769#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */
4770#define FDCAN_RXF0S_RF0L_Pos (25U)
4771#define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */
4772#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
4773
4774/***************** Bit definition for FDCAN_RXF0A register ********************/
4775#define FDCAN_RXF0A_F0AI_Pos (0U)
4776#define FDCAN_RXF0A_F0AI_Msk (0x3FUL << FDCAN_RXF0A_F0AI_Pos) /*!< 0x0000003F */
4777#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */
4778
4779/***************** Bit definition for FDCAN_RXBC register ********************/
4780#define FDCAN_RXBC_RBSA_Pos (2U)
4781#define FDCAN_RXBC_RBSA_Msk (0x3FFFUL << FDCAN_RXBC_RBSA_Pos) /*!< 0x0000FFFC */
4782#define FDCAN_RXBC_RBSA FDCAN_RXBC_RBSA_Msk /*!<Rx Buffer Start Address */
4783
4784/***************** Bit definition for FDCAN_RXF1C register ********************/
4785#define FDCAN_RXF1C_F1SA_Pos (2U)
4786#define FDCAN_RXF1C_F1SA_Msk (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos) /*!< 0x0000FFFC */
4787#define FDCAN_RXF1C_F1SA FDCAN_RXF1C_F1SA_Msk /*!<Rx FIFO 1 Start Address */
4788#define FDCAN_RXF1C_F1S_Pos (16U)
4789#define FDCAN_RXF1C_F1S_Msk (0x7FUL << FDCAN_RXF1C_F1S_Pos) /*!< 0x007F0000 */
4790#define FDCAN_RXF1C_F1S FDCAN_RXF1C_F1S_Msk /*!<Number of Rx FIFO 1 elements */
4791#define FDCAN_RXF1C_F1WM_Pos (24U)
4792#define FDCAN_RXF1C_F1WM_Msk (0x7FUL << FDCAN_RXF1C_F1WM_Pos) /*!< 0x7F000000 */
4793#define FDCAN_RXF1C_F1WM FDCAN_RXF1C_F1WM_Msk /*!<Rx FIFO 1 Watermark */
4794#define FDCAN_RXF1C_F1OM_Pos (31U)
4795#define FDCAN_RXF1C_F1OM_Msk (0x1UL << FDCAN_RXF1C_F1OM_Pos) /*!< 0x80000000 */
4796#define FDCAN_RXF1C_F1OM FDCAN_RXF1C_F1OM_Msk /*!<FIFO 1 Operation Mode */
4797
4798/***************** Bit definition for FDCAN_RXF1S register ********************/
4799#define FDCAN_RXF1S_F1FL_Pos (0U)
4800#define FDCAN_RXF1S_F1FL_Msk (0x7FUL << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000007F */
4801#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */
4802#define FDCAN_RXF1S_F1GI_Pos (8U)
4803#define FDCAN_RXF1S_F1GI_Msk (0x3FUL << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00003F00 */
4804#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */
4805#define FDCAN_RXF1S_F1PI_Pos (16U)
4806#define FDCAN_RXF1S_F1PI_Msk (0x3FUL << FDCAN_RXF1S_F1PI_Pos) /*!< 0x003F0000 */
4807#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */
4808#define FDCAN_RXF1S_F1F_Pos (24U)
4809#define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */
4810#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */
4811#define FDCAN_RXF1S_RF1L_Pos (25U)
4812#define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */
4813#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
4814
4815/***************** Bit definition for FDCAN_RXF1A register ********************/
4816#define FDCAN_RXF1A_F1AI_Pos (0U)
4817#define FDCAN_RXF1A_F1AI_Msk (0x3FUL << FDCAN_RXF1A_F1AI_Pos) /*!< 0x0000003F */
4818#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */
4819
4820/***************** Bit definition for FDCAN_RXESC register ********************/
4821#define FDCAN_RXESC_F0DS_Pos (0U)
4822#define FDCAN_RXESC_F0DS_Msk (0x7UL << FDCAN_RXESC_F0DS_Pos) /*!< 0x00000007 */
4823#define FDCAN_RXESC_F0DS FDCAN_RXESC_F0DS_Msk /*!<Rx FIFO 1 Data Field Size */
4824#define FDCAN_RXESC_F1DS_Pos (4U)
4825#define FDCAN_RXESC_F1DS_Msk (0x7UL << FDCAN_RXESC_F1DS_Pos) /*!< 0x00000070 */
4826#define FDCAN_RXESC_F1DS FDCAN_RXESC_F1DS_Msk /*!<Rx FIFO 0 Data Field Size */
4827#define FDCAN_RXESC_RBDS_Pos (8U)
4828#define FDCAN_RXESC_RBDS_Msk (0x7UL << FDCAN_RXESC_RBDS_Pos) /*!< 0x00000700 */
4829#define FDCAN_RXESC_RBDS FDCAN_RXESC_RBDS_Msk /*!<Rx Buffer Data Field Size */
4830
4831/***************** Bit definition for FDCAN_TXBC register *********************/
4832#define FDCAN_TXBC_TBSA_Pos (2U)
4833#define FDCAN_TXBC_TBSA_Msk (0x3FFFUL << FDCAN_TXBC_TBSA_Pos) /*!< 0x0000FFFC */
4834#define FDCAN_TXBC_TBSA FDCAN_TXBC_TBSA_Msk /*!<Tx Buffers Start Address */
4835#define FDCAN_TXBC_NDTB_Pos (16U)
4836#define FDCAN_TXBC_NDTB_Msk (0x3FUL << FDCAN_TXBC_NDTB_Pos) /*!< 0x003F0000 */
4837#define FDCAN_TXBC_NDTB FDCAN_TXBC_NDTB_Msk /*!<Number of Dedicated Transmit Buffers */
4838#define FDCAN_TXBC_TFQS_Pos (24U)
4839#define FDCAN_TXBC_TFQS_Msk (0x3FUL << FDCAN_TXBC_TFQS_Pos) /*!< 0x3F000000 */
4840#define FDCAN_TXBC_TFQS FDCAN_TXBC_TFQS_Msk /*!<Transmit FIFO/Queue Size */
4841#define FDCAN_TXBC_TFQM_Pos (30U)
4842#define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) /*!< 0x40000000 */
4843#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */
4844
4845/***************** Bit definition for FDCAN_TXFQS register *********************/
4846#define FDCAN_TXFQS_TFFL_Pos (0U)
4847#define FDCAN_TXFQS_TFFL_Msk (0x3FUL << FDCAN_TXFQS_TFFL_Pos) /*!< 0x0000003F */
4848#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */
4849#define FDCAN_TXFQS_TFGI_Pos (8U)
4850#define FDCAN_TXFQS_TFGI_Msk (0x1FUL << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00001F00 */
4851#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */
4852#define FDCAN_TXFQS_TFQPI_Pos (16U)
4853#define FDCAN_TXFQS_TFQPI_Msk (0x1FUL << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x001F0000 */
4854#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */
4855#define FDCAN_TXFQS_TFQF_Pos (21U)
4856#define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */
4857#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */
4858
4859/***************** Bit definition for FDCAN_TXESC register *********************/
4860#define FDCAN_TXESC_TBDS_Pos (0U)
4861#define FDCAN_TXESC_TBDS_Msk (0x7UL << FDCAN_TXESC_TBDS_Pos) /*!< 0x00000007 */
4862#define FDCAN_TXESC_TBDS FDCAN_TXESC_TBDS_Msk /*!<Tx Buffer Data Field Size */
4863
4864/***************** Bit definition for FDCAN_TXBRP register *********************/
4865#define FDCAN_TXBRP_TRP_Pos (0U)
4866#define FDCAN_TXBRP_TRP_Msk (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos) /*!< 0xFFFFFFFF */
4867#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */
4868
4869/***************** Bit definition for FDCAN_TXBAR register *********************/
4870#define FDCAN_TXBAR_AR_Pos (0U)
4871#define FDCAN_TXBAR_AR_Msk (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos) /*!< 0xFFFFFFFF */
4872#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */
4873
4874/***************** Bit definition for FDCAN_TXBCR register *********************/
4875#define FDCAN_TXBCR_CR_Pos (0U)
4876#define FDCAN_TXBCR_CR_Msk (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos) /*!< 0xFFFFFFFF */
4877#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */
4878
4879/***************** Bit definition for FDCAN_TXBTO register *********************/
4880#define FDCAN_TXBTO_TO_Pos (0U)
4881#define FDCAN_TXBTO_TO_Msk (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos) /*!< 0xFFFFFFFF */
4882#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */
4883
4884/***************** Bit definition for FDCAN_TXBCF register *********************/
4885#define FDCAN_TXBCF_CF_Pos (0U)
4886#define FDCAN_TXBCF_CF_Msk (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos) /*!< 0xFFFFFFFF */
4887#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */
4888
4889/***************** Bit definition for FDCAN_TXBTIE register ********************/
4890#define FDCAN_TXBTIE_TIE_Pos (0U)
4891#define FDCAN_TXBTIE_TIE_Msk (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos) /*!< 0xFFFFFFFF */
4892#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */
4893
4894/***************** Bit definition for FDCAN_ TXBCIE register *******************/
4895#define FDCAN_TXBCIE_CFIE_Pos (0U)
4896#define FDCAN_TXBCIE_CFIE_Msk (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos) /*!< 0xFFFFFFFF */
4897#define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk /*!<Cancellation Finished Interrupt Enable */
4898
4899/***************** Bit definition for FDCAN_TXEFC register *********************/
4900#define FDCAN_TXEFC_EFSA_Pos (2U)
4901#define FDCAN_TXEFC_EFSA_Msk (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos) /*!< 0x0000FFFC */
4902#define FDCAN_TXEFC_EFSA FDCAN_TXEFC_EFSA_Msk /*!<Event FIFO Start Address */
4903#define FDCAN_TXEFC_EFS_Pos (16U)
4904#define FDCAN_TXEFC_EFS_Msk (0x3FUL << FDCAN_TXEFC_EFS_Pos) /*!< 0x003F0000 */
4905#define FDCAN_TXEFC_EFS FDCAN_TXEFC_EFS_Msk /*!<Event FIFO Size */
4906#define FDCAN_TXEFC_EFWM_Pos (24U)
4907#define FDCAN_TXEFC_EFWM_Msk (0x3FUL << FDCAN_TXEFC_EFWM_Pos) /*!< 0x3F000000 */
4908#define FDCAN_TXEFC_EFWM FDCAN_TXEFC_EFWM_Msk /*!<Event FIFO Watermark */
4909
4910/***************** Bit definition for FDCAN_TXEFS register *********************/
4911#define FDCAN_TXEFS_EFFL_Pos (0U)
4912#define FDCAN_TXEFS_EFFL_Msk (0x3FUL << FDCAN_TXEFS_EFFL_Pos) /*!< 0x0000003F */
4913#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */
4914#define FDCAN_TXEFS_EFGI_Pos (8U)
4915#define FDCAN_TXEFS_EFGI_Msk (0x1FUL << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00001F00 */
4916#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */
4917#define FDCAN_TXEFS_EFPI_Pos (16U)
4918#define FDCAN_TXEFS_EFPI_Msk (0x1FUL << FDCAN_TXEFS_EFPI_Pos) /*!< 0x001F0000 */
4919#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */
4920#define FDCAN_TXEFS_EFF_Pos (24U)
4921#define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */
4922#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */
4923#define FDCAN_TXEFS_TEFL_Pos (25U)
4924#define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */
4925#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */
4926
4927/***************** Bit definition for FDCAN_TXEFA register *********************/
4928#define FDCAN_TXEFA_EFAI_Pos (0U)
4929#define FDCAN_TXEFA_EFAI_Msk (0x1FUL << FDCAN_TXEFA_EFAI_Pos) /*!< 0x0000001F */
4930#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */
4931
4932/***************** Bit definition for FDCAN_TTTMC register *********************/
4933#define FDCAN_TTTMC_TMSA_Pos (2U)
4934#define FDCAN_TTTMC_TMSA_Msk (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos) /*!< 0x0000FFFC */
4935#define FDCAN_TTTMC_TMSA FDCAN_TTTMC_TMSA_Msk /*!<Trigger Memory Start Address */
4936#define FDCAN_TTTMC_TME_Pos (16U)
4937#define FDCAN_TTTMC_TME_Msk (0x7FUL << FDCAN_TTTMC_TME_Pos) /*!< 0x007F0000 */
4938#define FDCAN_TTTMC_TME FDCAN_TTTMC_TME_Msk /*!<Trigger Memory Elements */
4939
4940/***************** Bit definition for FDCAN_TTRMC register *********************/
4941#define FDCAN_TTRMC_RID_Pos (0U)
4942#define FDCAN_TTRMC_RID_Msk (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos) /*!< 0x1FFFFFFF */
4943#define FDCAN_TTRMC_RID FDCAN_TTRMC_RID_Msk /*!<Reference Identifier */
4944#define FDCAN_TTRMC_XTD_Pos (30U)
4945#define FDCAN_TTRMC_XTD_Msk (0x1UL << FDCAN_TTRMC_XTD_Pos) /*!< 0x40000000 */
4946#define FDCAN_TTRMC_XTD FDCAN_TTRMC_XTD_Msk /*!< Extended Identifier */
4947#define FDCAN_TTRMC_RMPS_Pos (31U)
4948#define FDCAN_TTRMC_RMPS_Msk (0x1UL << FDCAN_TTRMC_RMPS_Pos) /*!< 0x80000000 */
4949#define FDCAN_TTRMC_RMPS FDCAN_TTRMC_RMPS_Msk /*!<Reference Message Payload Select */
4950
4951/***************** Bit definition for FDCAN_TTOCF register *********************/
4952#define FDCAN_TTOCF_OM_Pos (0U)
4953#define FDCAN_TTOCF_OM_Msk (0x3UL << FDCAN_TTOCF_OM_Pos) /*!< 0x00000003 */
4954#define FDCAN_TTOCF_OM FDCAN_TTOCF_OM_Msk /*!<Operation Mode */
4955#define FDCAN_TTOCF_GEN_Pos (3U)
4956#define FDCAN_TTOCF_GEN_Msk (0x1UL << FDCAN_TTOCF_GEN_Pos) /*!< 0x00000008 */
4957#define FDCAN_TTOCF_GEN FDCAN_TTOCF_GEN_Msk /*!<Gap Enable */
4958#define FDCAN_TTOCF_TM_Pos (4U)
4959#define FDCAN_TTOCF_TM_Msk (0x1UL << FDCAN_TTOCF_TM_Pos) /*!< 0x00000010 */
4960#define FDCAN_TTOCF_TM FDCAN_TTOCF_TM_Msk /*!<Time Master */
4961#define FDCAN_TTOCF_LDSDL_Pos (5U)
4962#define FDCAN_TTOCF_LDSDL_Msk (0x7UL << FDCAN_TTOCF_LDSDL_Pos) /*!< 0x000000E0 */
4963#define FDCAN_TTOCF_LDSDL FDCAN_TTOCF_LDSDL_Msk /*!<LD of Synchronization Deviation Limit */
4964#define FDCAN_TTOCF_IRTO_Pos (8U)
4965#define FDCAN_TTOCF_IRTO_Msk (0x7FUL << FDCAN_TTOCF_IRTO_Pos) /*!< 0x00007F00 */
4966#define FDCAN_TTOCF_IRTO FDCAN_TTOCF_IRTO_Msk /*!<Initial Reference Trigger Offset */
4967#define FDCAN_TTOCF_EECS_Pos (15U)
4968#define FDCAN_TTOCF_EECS_Msk (0x1UL << FDCAN_TTOCF_EECS_Pos) /*!< 0x00008000 */
4969#define FDCAN_TTOCF_EECS FDCAN_TTOCF_EECS_Msk /*!<Enable External Clock Synchronization */
4970#define FDCAN_TTOCF_AWL_Pos (16U)
4971#define FDCAN_TTOCF_AWL_Msk (0xFFUL << FDCAN_TTOCF_AWL_Pos) /*!< 0x00FF0000 */
4972#define FDCAN_TTOCF_AWL FDCAN_TTOCF_AWL_Msk /*!<Application Watchdog Limit */
4973#define FDCAN_TTOCF_EGTF_Pos (24U)
4974#define FDCAN_TTOCF_EGTF_Msk (0x1UL << FDCAN_TTOCF_EGTF_Pos) /*!< 0x01000000 */
4975#define FDCAN_TTOCF_EGTF FDCAN_TTOCF_EGTF_Msk /*!<Enable Global Time Filtering */
4976#define FDCAN_TTOCF_ECC_Pos (25U)
4977#define FDCAN_TTOCF_ECC_Msk (0x1UL << FDCAN_TTOCF_ECC_Pos) /*!< 0x02000000 */
4978#define FDCAN_TTOCF_ECC FDCAN_TTOCF_ECC_Msk /*!<Enable Clock Calibration */
4979#define FDCAN_TTOCF_EVTP_Pos (26U)
4980#define FDCAN_TTOCF_EVTP_Msk (0x1UL << FDCAN_TTOCF_EVTP_Pos) /*!< 0x04000000 */
4981#define FDCAN_TTOCF_EVTP FDCAN_TTOCF_EVTP_Msk /*!<Event Trigger Polarity */
4982
4983/***************** Bit definition for FDCAN_TTMLM register *********************/
4984#define FDCAN_TTMLM_CCM_Pos (0U)
4985#define FDCAN_TTMLM_CCM_Msk (0x3FUL << FDCAN_TTMLM_CCM_Pos) /*!< 0x0000003F */
4986#define FDCAN_TTMLM_CCM FDCAN_TTMLM_CCM_Msk /*!<Cycle Count Max */
4987#define FDCAN_TTMLM_CSS_Pos (6U)
4988#define FDCAN_TTMLM_CSS_Msk (0x3UL << FDCAN_TTMLM_CSS_Pos) /*!< 0x000000C0 */
4989#define FDCAN_TTMLM_CSS FDCAN_TTMLM_CSS_Msk /*!<Cycle Start Synchronization */
4990#define FDCAN_TTMLM_TXEW_Pos (8U)
4991#define FDCAN_TTMLM_TXEW_Msk (0xFUL << FDCAN_TTMLM_TXEW_Pos) /*!< 0x00000F00 */
4992#define FDCAN_TTMLM_TXEW FDCAN_TTMLM_TXEW_Msk /*!<Tx Enable Window */
4993#define FDCAN_TTMLM_ENTT_Pos (16U)
4994#define FDCAN_TTMLM_ENTT_Msk (0xFFFUL << FDCAN_TTMLM_ENTT_Pos) /*!< 0x0FFF0000 */
4995#define FDCAN_TTMLM_ENTT FDCAN_TTMLM_ENTT_Msk /*!<Expected Number of Tx Triggers */
4996
4997/***************** Bit definition for FDCAN_TURCF register *********************/
4998#define FDCAN_TURCF_NCL_Pos (0U)
4999#define FDCAN_TURCF_NCL_Msk (0xFFFFUL << FDCAN_TURCF_NCL_Pos) /*!< 0x0000FFFF */
5000#define FDCAN_TURCF_NCL FDCAN_TURCF_NCL_Msk /*!<Numerator Configuration Low */
5001#define FDCAN_TURCF_DC_Pos (16U)
5002#define FDCAN_TURCF_DC_Msk (0x3FFFUL << FDCAN_TURCF_DC_Pos) /*!< 0x3FFF0000 */
5003#define FDCAN_TURCF_DC FDCAN_TURCF_DC_Msk /*!<Denominator Configuration */
5004#define FDCAN_TURCF_ELT_Pos (31U)
5005#define FDCAN_TURCF_ELT_Msk (0x1UL << FDCAN_TURCF_ELT_Pos) /*!< 0x80000000 */
5006#define FDCAN_TURCF_ELT FDCAN_TURCF_ELT_Msk /*!<Enable Local Time */
5007
5008/***************** Bit definition for FDCAN_TTOCN register ********************/
5009#define FDCAN_TTOCN_SGT_Pos (0U)
5010#define FDCAN_TTOCN_SGT_Msk (0x1UL << FDCAN_TTOCN_SGT_Pos) /*!< 0x00000001 */
5011#define FDCAN_TTOCN_SGT FDCAN_TTOCN_SGT_Msk /*!<Set Global time */
5012#define FDCAN_TTOCN_ECS_Pos (1U)
5013#define FDCAN_TTOCN_ECS_Msk (0x1UL << FDCAN_TTOCN_ECS_Pos) /*!< 0x00000002 */
5014#define FDCAN_TTOCN_ECS FDCAN_TTOCN_ECS_Msk /*!<External Clock Synchronization */
5015#define FDCAN_TTOCN_SWP_Pos (2U)
5016#define FDCAN_TTOCN_SWP_Msk (0x1UL << FDCAN_TTOCN_SWP_Pos) /*!< 0x00000004 */
5017#define FDCAN_TTOCN_SWP FDCAN_TTOCN_SWP_Msk /*!<Stop Watch Polarity */
5018#define FDCAN_TTOCN_SWS_Pos (3U)
5019#define FDCAN_TTOCN_SWS_Msk (0x3UL << FDCAN_TTOCN_SWS_Pos) /*!< 0x00000018 */
5020#define FDCAN_TTOCN_SWS FDCAN_TTOCN_SWS_Msk /*!<Stop Watch Source */
5021#define FDCAN_TTOCN_RTIE_Pos (5U)
5022#define FDCAN_TTOCN_RTIE_Msk (0x1UL << FDCAN_TTOCN_RTIE_Pos) /*!< 0x00000020 */
5023#define FDCAN_TTOCN_RTIE FDCAN_TTOCN_RTIE_Msk /*!<Register Time Mark Interrupt Pulse Enable */
5024#define FDCAN_TTOCN_TMC_Pos (6U)
5025#define FDCAN_TTOCN_TMC_Msk (0x3UL << FDCAN_TTOCN_TMC_Pos) /*!< 0x000000C0 */
5026#define FDCAN_TTOCN_TMC FDCAN_TTOCN_TMC_Msk /*!<Register Time Mark Compare */
5027#define FDCAN_TTOCN_TTIE_Pos (8U)
5028#define FDCAN_TTOCN_TTIE_Msk (0x1UL << FDCAN_TTOCN_TTIE_Pos) /*!< 0x00000100 */
5029#define FDCAN_TTOCN_TTIE FDCAN_TTOCN_TTIE_Msk /*!<Trigger Time Mark Interrupt Pulse Enable */
5030#define FDCAN_TTOCN_GCS_Pos (9U)
5031#define FDCAN_TTOCN_GCS_Msk (0x1UL << FDCAN_TTOCN_GCS_Pos) /*!< 0x00000200 */
5032#define FDCAN_TTOCN_GCS FDCAN_TTOCN_GCS_Msk /*!<Gap Control Select */
5033#define FDCAN_TTOCN_FGP_Pos (10U)
5034#define FDCAN_TTOCN_FGP_Msk (0x1UL << FDCAN_TTOCN_FGP_Pos) /*!< 0x00000400 */
5035#define FDCAN_TTOCN_FGP FDCAN_TTOCN_FGP_Msk /*!<Finish Gap */
5036#define FDCAN_TTOCN_TMG_Pos (11U)
5037#define FDCAN_TTOCN_TMG_Msk (0x1UL << FDCAN_TTOCN_TMG_Pos) /*!< 0x00000800 */
5038#define FDCAN_TTOCN_TMG FDCAN_TTOCN_TMG_Msk /*!<Time Mark Gap */
5039#define FDCAN_TTOCN_NIG_Pos (12U)
5040#define FDCAN_TTOCN_NIG_Msk (0x1UL << FDCAN_TTOCN_NIG_Pos) /*!< 0x00001000 */
5041#define FDCAN_TTOCN_NIG FDCAN_TTOCN_NIG_Msk /*!<Next is Gap */
5042#define FDCAN_TTOCN_ESCN_Pos (13U)
5043#define FDCAN_TTOCN_ESCN_Msk (0x1UL << FDCAN_TTOCN_ESCN_Pos) /*!< 0x00002000 */
5044#define FDCAN_TTOCN_ESCN FDCAN_TTOCN_ESCN_Msk /*!<External Synchronization Control */
5045#define FDCAN_TTOCN_LCKC_Pos (15U)
5046#define FDCAN_TTOCN_LCKC_Msk (0x1UL << FDCAN_TTOCN_LCKC_Pos) /*!< 0x00008000 */
5047#define FDCAN_TTOCN_LCKC FDCAN_TTOCN_LCKC_Msk /*!<TT Operation Control Register Locked */
5048
5049/***************** Bit definition fo