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diff --git a/lib/chibios/os/common/ext/ST/STM32H7xx/stm32h757xx.h b/lib/chibios/os/common/ext/ST/STM32H7xx/stm32h757xx.h
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1/**
2 ******************************************************************************
3 * @file stm32h757xx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32H757xx Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
16 * All rights reserved.</center></h2>
17 *
18 * This software component is licensed by ST under BSD 3-Clause license,
19 * the "License"; You may not use this file except in compliance with the
20 * License. You may obtain a copy of the License at:
21 * opensource.org/licenses/BSD-3-Clause
22 *
23 ******************************************************************************
24 */
25
26/** @addtogroup CMSIS_Device
27 * @{
28 */
29
30/** @addtogroup stm32h757xx
31 * @{
32 */
33
34#ifndef STM32H757xx_H
35#define STM32H757xx_H
36
37#ifdef __cplusplus
38 extern "C" {
39#endif /* __cplusplus */
40
41/** @addtogroup Peripheral_interrupt_number_definition
42 * @{
43 */
44
45/**
46 * @brief STM32H7XX Interrupt Number Definition, according to the selected device
47 * in @ref Library_configuration_section
48 */
49typedef enum
50{
51/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
52 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
53 HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
54 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
55 BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
56 UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
57 SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
58 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */
59 PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
60 SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
61/****** STM32 specific Interrupt Numbers **********************************************************************/
62 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
63 PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */
64 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
65 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
66 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
67 RCC_IRQn = 5, /*!< RCC global Interrupt */
68 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
69 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
70 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
71 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
72 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
73 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
74 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
75 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
76 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
77 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
78 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
79 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
80 ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */
81 FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */
82 FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */
83 FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */
84 FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */
85 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
86 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
87 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
88 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
89 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
90 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
91 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
92 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
93 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
94 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
95 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
96 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
97 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
98 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
99 USART1_IRQn = 37, /*!< USART1 global Interrupt */
100 USART2_IRQn = 38, /*!< USART2 global Interrupt */
101 USART3_IRQn = 39, /*!< USART3 global Interrupt */
102 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
103 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
104 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
105 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
106 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
107 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
108 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
109 FMC_IRQn = 48, /*!< FMC global Interrupt */
110 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
111 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
112 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
113 UART4_IRQn = 52, /*!< UART4 global Interrupt */
114 UART5_IRQn = 53, /*!< UART5 global Interrupt */
115 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
116 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
117 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
118 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
119 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
120 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
121 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
122 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
123 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
124 FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */
125 CM7_SEV_IRQn = 64, /*!< CM7 Send event interrupt for CM4 */
126 CM4_SEV_IRQn = 65, /*!< CM4 Send event interrupt for CM7 */
127 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
128 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
129 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
130 USART6_IRQn = 71, /*!< USART6 global interrupt */
131 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
132 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
133 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
134 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
135 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
136 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
137 DCMI_IRQn = 78, /*!< DCMI global interrupt */
138 CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
139 HASH_RNG_IRQn = 80, /*!< HASH and RNG global interrupt */
140 FPU_IRQn = 81, /*!< FPU global interrupt */
141 UART7_IRQn = 82, /*!< UART7 global interrupt */
142 UART8_IRQn = 83, /*!< UART8 global interrupt */
143 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
144 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
145 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
146 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
147 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
148 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
149 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
150 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
151 QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
152 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
153 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
154 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
155 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
156 SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
157 OTG_FS_EP1_OUT_IRQn = 98, /*!< USB OTG HS2 global interrupt */
158 OTG_FS_EP1_IN_IRQn = 99, /*!< USB OTG HS2 End Point 1 Out global interrupt */
159 OTG_FS_WKUP_IRQn = 100, /*!< USB OTG HS2 End Point 1 In global interrupt */
160 OTG_FS_IRQn = 101, /*!< USB OTG HS2 Wakeup through EXTI interrupt */
161 DMAMUX1_OVR_IRQn = 102, /*!<DMAMUX1 Overrun interrupt */
162 HRTIM1_Master_IRQn = 103, /*!< HRTIM Master Timer global Interrupts */
163 HRTIM1_TIMA_IRQn = 104, /*!< HRTIM Timer A global Interrupt */
164 HRTIM1_TIMB_IRQn = 105, /*!< HRTIM Timer B global Interrupt */
165 HRTIM1_TIMC_IRQn = 106, /*!< HRTIM Timer C global Interrupt */
166 HRTIM1_TIMD_IRQn = 107, /*!< HRTIM Timer D global Interrupt */
167 HRTIM1_TIME_IRQn = 108, /*!< HRTIM Timer E global Interrupt */
168 HRTIM1_FLT_IRQn = 109, /*!< HRTIM Fault global Interrupt */
169 DFSDM1_FLT0_IRQn = 110, /*!<DFSDM Filter1 Interrupt */
170 DFSDM1_FLT1_IRQn = 111, /*!<DFSDM Filter2 Interrupt */
171 DFSDM1_FLT2_IRQn = 112, /*!<DFSDM Filter3 Interrupt */
172 DFSDM1_FLT3_IRQn = 113, /*!<DFSDM Filter4 Interrupt */
173 SAI3_IRQn = 114, /*!< SAI3 global Interrupt */
174 SWPMI1_IRQn = 115, /*!< Serial Wire Interface 1 global interrupt */
175 TIM15_IRQn = 116, /*!< TIM15 global Interrupt */
176 TIM16_IRQn = 117, /*!< TIM16 global Interrupt */
177 TIM17_IRQn = 118, /*!< TIM17 global Interrupt */
178 MDIOS_WKUP_IRQn = 119, /*!< MDIOS Wakeup Interrupt */
179 MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */
180 JPEG_IRQn = 121, /*!< JPEG global Interrupt */
181 MDMA_IRQn = 122, /*!< MDMA global Interrupt */
182 DSI_IRQn = 123, /*!< DSI global Interrupt */
183 SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */
184 HSEM1_IRQn = 125, /*!< HSEM1 global Interrupt */
185 HSEM2_IRQn = 126, /*!< HSEM2 global Interrupt */
186 ADC3_IRQn = 127, /*!< ADC3 global Interrupt */
187 DMAMUX2_OVR_IRQn = 128, /*!<DMAMUX2 Overrun interrupt */
188 BDMA_Channel0_IRQn = 129, /*!< BDMA Channel 0 global Interrupt */
189 BDMA_Channel1_IRQn = 130, /*!< BDMA Channel 1 global Interrupt */
190 BDMA_Channel2_IRQn = 131, /*!< BDMA Channel 2 global Interrupt */
191 BDMA_Channel3_IRQn = 132, /*!< BDMA Channel 3 global Interrupt */
192 BDMA_Channel4_IRQn = 133, /*!< BDMA Channel 4 global Interrupt */
193 BDMA_Channel5_IRQn = 134, /*!< BDMA Channel 5 global Interrupt */
194 BDMA_Channel6_IRQn = 135, /*!< BDMA Channel 6 global Interrupt */
195 BDMA_Channel7_IRQn = 136, /*!< BDMA Channel 7 global Interrupt */
196 COMP_IRQn = 137 , /*!< COMP global Interrupt */
197 LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */
198 LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */
199 LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */
200 LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */
201 LPUART1_IRQn = 142, /*!< LP UART1 interrupt */
202 WWDG_RST_IRQn = 143, /*!<Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */
203 CRS_IRQn = 144, /*!< Clock Recovery Global Interrupt */
204 ECC_IRQn = 145, /*!< ECC diagnostic Global Interrupt */
205 SAI4_IRQn = 146, /*!< SAI4 global interrupt */
206 HOLD_CORE_IRQn = 148, /*!< Hold core interrupt */
207 WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */
208} IRQn_Type;
209
210/**
211 * @}
212 */
213
214/** @addtogroup Configuration_section_for_CMSIS
215 * @{
216 */
217#define DUAL_CORE /*!< Dual core line feature */
218
219#define SMPS /*!< Switched mode power supply feature */
220
221
222
223/**
224 * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals
225 */
226#ifdef CORE_CM4
227#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
228#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */
229#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */
230#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
231#define __FPU_PRESENT 1 /*!< FPU present */
232
233#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
234#else /* CORE_CM7 */
235#ifdef CORE_CM7
236#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
237#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
238#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
239#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
240#define __FPU_PRESENT 1 /*!< FPU present */
241#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
242#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
243#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
244#else /* UNKNOWN_CORE */
245#error Please #define CORE_CM4 or CORE_CM7
246#endif /* CORE_CM7 */
247#endif /* CORE_CM4 */
248
249/**
250 * @}
251 */
252
253
254
255
256
257#include "system_stm32h7xx.h"
258#include <stdint.h>
259
260/** @addtogroup Peripheral_registers_structures
261 * @{
262 */
263
264/**
265 * @brief Analog to Digital Converter
266 */
267
268typedef struct
269{
270 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
271 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
272 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
273 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
274 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
275 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
276 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
277 __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */
278 __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
279 __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
280 uint32_t RESERVED1; /*!< Reserved, 0x028 */
281 uint32_t RESERVED2; /*!< Reserved, 0x02C */
282 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
283 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
284 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
285 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
286 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
287 uint32_t RESERVED3; /*!< Reserved, 0x044 */
288 uint32_t RESERVED4; /*!< Reserved, 0x048 */
289 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
290 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
291 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
292 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
293 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
294 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
295 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
296 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
297 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
298 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
299 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
300 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
301 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
302 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
303 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
304 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
305 __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */
306 __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */
307 __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */
308 __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */
309 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */
310 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */
311 __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */
312} ADC_TypeDef;
313
314
315typedef struct
316{
317__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
318uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
319__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
320__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
321__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
322
323} ADC_Common_TypeDef;
324
325/**
326 * @brief ART
327 */
328
329typedef struct
330{
331 __IO uint32_t CTR; /*!< ART accelerator - control register */
332}ART_TypeDef;
333
334/**
335 * @brief VREFBUF
336 */
337
338typedef struct
339{
340 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
341 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
342} VREFBUF_TypeDef;
343
344
345/**
346 * @brief FD Controller Area Network
347 */
348
349typedef struct
350{
351 __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
352 __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
353 __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */
354 __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
355 __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
356 __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
357 __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
358 __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
359 __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
360 __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
361 __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
362 __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
363 __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
364 __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
365 __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
366 __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
367 __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */
368 __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
369 __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
370 __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
371 __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
372 __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
373 __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
374 __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */
375 __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */
376 __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */
377 __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */
378 __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */
379 __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */
380 __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */
381 __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */
382 __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */
383 __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */
384 __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */
385 __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */
386 __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */
387 __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */
388 __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */
389 __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
390 __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
391 __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */
392 __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */
393 __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */
394 __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */
395 __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */
396 __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */
397 __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */
398 __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
399 __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */
400 __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */
401 __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */
402 __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */
403 __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */
404} FDCAN_GlobalTypeDef;
405
406/**
407 * @brief TTFD Controller Area Network
408 */
409
410typedef struct
411{
412 __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */
413 __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */
414 __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */
415 __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */
416 __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */
417 __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */
418 __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */
419 __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */
420 __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */
421 __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */
422 __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */
423 __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */
424 __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */
425 __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */
426 __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */
427 __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */
428 __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */
429 __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */
430 __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */
431} TTCAN_TypeDef;
432
433/**
434 * @brief FD Controller Area Network
435 */
436
437typedef struct
438{
439 __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
440 __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */
441 __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */
442 __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */
443 __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */
444 __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */
445} FDCAN_ClockCalibrationUnit_TypeDef;
446
447
448/**
449 * @brief Consumer Electronics Control
450 */
451
452typedef struct
453{
454 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
455 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
456 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
457 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
458 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
459 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
460}CEC_TypeDef;
461
462/**
463 * @brief CRC calculation unit
464 */
465
466typedef struct
467{
468 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
469 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
470 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
471 uint32_t RESERVED2; /*!< Reserved, 0x0C */
472 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
473 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
474} CRC_TypeDef;
475
476
477/**
478 * @brief Clock Recovery System
479 */
480typedef struct
481{
482__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
483__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
484__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
485__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
486} CRS_TypeDef;
487
488
489/**
490 * @brief Digital to Analog Converter
491 */
492
493typedef struct
494{
495 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
496 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
497 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
498 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
499 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
500 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
501 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
502 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
503 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
504 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
505 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
506 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
507 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
508 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
509 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
510 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
511 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
512 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
513 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
514 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
515} DAC_TypeDef;
516
517/**
518 * @brief DFSDM module registers
519 */
520typedef struct
521{
522 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
523 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
524 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
525 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
526 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
527 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
528 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
529 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
530 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
531 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
532 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
533 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
534 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
535 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
536 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
537} DFSDM_Filter_TypeDef;
538
539/**
540 * @brief DFSDM channel configuration registers
541 */
542typedef struct
543{
544 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
545 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
546 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
547 short circuit detector register, Address offset: 0x08 */
548 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
549 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
550} DFSDM_Channel_TypeDef;
551
552/**
553 * @brief Debug MCU
554 */
555typedef struct
556{
557 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
558 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
559 __IO uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */
560 __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */
561 __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register, Address offset: 0x38 */
562 __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */
563 __IO uint32_t APB1LFZ2; /*!< Debug MCU APB1LFZ2 freeze register, Address offset: 0x40 */
564 __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */
565 __IO uint32_t APB1HFZ2; /*!< Debug MCU APB1LFZ2 freeze register, Address offset: 0x48 */
566 __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */
567 __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register, Address offset: 0x50 */
568 __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */
569 __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register, Address offset: 0x58 */
570
571}DBGMCU_TypeDef;
572/**
573 * @brief DCMI
574 */
575
576typedef struct
577{
578 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
579 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
580 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
581 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
582 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
583 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
584 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
585 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
586 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
587 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
588 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
589} DCMI_TypeDef;
590
591/**
592 * @brief DMA Controller
593 */
594
595typedef struct
596{
597 __IO uint32_t CR; /*!< DMA stream x configuration register */
598 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
599 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
600 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
601 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
602 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
603} DMA_Stream_TypeDef;
604
605typedef struct
606{
607 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
608 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
609 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
610 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
611} DMA_TypeDef;
612
613typedef struct
614{
615 __IO uint32_t CCR; /*!< DMA channel x configuration register */
616 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
617 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
618 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */
619 __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */
620} BDMA_Channel_TypeDef;
621
622typedef struct
623{
624 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
625 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
626} BDMA_TypeDef;
627
628typedef struct
629{
630 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */
631}DMAMUX_Channel_TypeDef;
632
633typedef struct
634{
635 __IO uint32_t CSR; /*!< DMA Channel Status Register */
636 __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */
637}DMAMUX_ChannelStatus_TypeDef;
638
639typedef struct
640{
641 __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */
642}DMAMUX_RequestGen_TypeDef;
643
644typedef struct
645{
646 __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */
647 __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */
648}DMAMUX_RequestGenStatus_TypeDef;
649
650/**
651 * @brief MDMA Controller
652 */
653typedef struct
654{
655 __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */
656}MDMA_TypeDef;
657
658typedef struct
659{
660 __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */
661 __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */
662 __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */
663 __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */
664 __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */
665 __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */
666 __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */
667 __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */
668 __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
669 __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
670 __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
671 uint32_t RESERVED0; /*!< Reserved, 0x68 */
672 __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
673 __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
674}MDMA_Channel_TypeDef;
675
676/**
677 * @brief DMA2D Controller
678 */
679
680typedef struct
681{
682 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
683 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
684 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
685 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
686 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
687 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
688 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
689 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
690 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
691 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
692 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
693 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
694 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
695 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
696 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
697 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
698 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
699 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
700 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
701 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
702 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
703 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
704 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
705} DMA2D_TypeDef;
706
707/**
708 * @brief DSI Controller
709 */
710
711typedef struct
712{
713 __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */
714 __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */
715 __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */
716 __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */
717 __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */
718 __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */
719 __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */
720 uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */
721 __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */
722 __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */
723 __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */
724 __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */
725 __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */
726 __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */
727 __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */
728 __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */
729 __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */
730 __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */
731 __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */
732 __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */
733 __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */
734 __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */
735 __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */
736 __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */
737 __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */
738 __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */
739 __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */
740 __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
741 __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */
742 __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */
743 __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */
744 __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */
745 __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */
746 __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */
747 __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */
748 __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */
749 __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */
750 uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */
751 __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
752 __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
753 uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */
754 __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
755 uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */
756 __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */
757 uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */
758 __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */
759 __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */
760 uint32_t RESERVED5; /*!< Reserved, 0x114 */
761 __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */
762 uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
763 __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
764 __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
765 __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
766 __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
767 __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
768 __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
769 __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */
770 __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */
771 __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */
772 __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */
773 __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */
774 uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */
775 __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */
776 uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */
777 __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */
778 __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */
779 __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */
780 __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */
781 __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */
782 uint32_t RESERVED9; /*!< Reserved, 0x414 */
783 __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */
784 uint32_t RESERVED10; /*!< Reserved, 0x42C */
785 __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */
786} DSI_TypeDef;
787
788/**
789 * @brief Ethernet MAC
790 */
791typedef struct
792{
793 __IO uint32_t MACCR;
794 __IO uint32_t MACECR;
795 __IO uint32_t MACPFR;
796 __IO uint32_t MACWTR;
797 __IO uint32_t MACHT0R;
798 __IO uint32_t MACHT1R;
799 uint32_t RESERVED1[14];
800 __IO uint32_t MACVTR;
801 uint32_t RESERVED2;
802 __IO uint32_t MACVHTR;
803 uint32_t RESERVED3;
804 __IO uint32_t MACVIR;
805 __IO uint32_t MACIVIR;
806 uint32_t RESERVED4[2];
807 __IO uint32_t MACTFCR;
808 uint32_t RESERVED5[7];
809 __IO uint32_t MACRFCR;
810 uint32_t RESERVED6[7];
811 __IO uint32_t MACISR;
812 __IO uint32_t MACIER;
813 __IO uint32_t MACRXTXSR;
814 uint32_t RESERVED7;
815 __IO uint32_t MACPCSR;
816 __IO uint32_t MACRWKPFR;
817 uint32_t RESERVED8[2];
818 __IO uint32_t MACLCSR;
819 __IO uint32_t MACLTCR;
820 __IO uint32_t MACLETR;
821 __IO uint32_t MAC1USTCR;
822 uint32_t RESERVED9[12];
823 __IO uint32_t MACVR;
824 __IO uint32_t MACDR;
825 uint32_t RESERVED10;
826 __IO uint32_t MACHWF0R;
827 __IO uint32_t MACHWF1R;
828 __IO uint32_t MACHWF2R;
829 uint32_t RESERVED11[54];
830 __IO uint32_t MACMDIOAR;
831 __IO uint32_t MACMDIODR;
832 uint32_t RESERVED12[2];
833 __IO uint32_t MACARPAR;
834 uint32_t RESERVED13[59];
835 __IO uint32_t MACA0HR;
836 __IO uint32_t MACA0LR;
837 __IO uint32_t MACA1HR;
838 __IO uint32_t MACA1LR;
839 __IO uint32_t MACA2HR;
840 __IO uint32_t MACA2LR;
841 __IO uint32_t MACA3HR;
842 __IO uint32_t MACA3LR;
843 uint32_t RESERVED14[248];
844 __IO uint32_t MMCCR;
845 __IO uint32_t MMCRIR;
846 __IO uint32_t MMCTIR;
847 __IO uint32_t MMCRIMR;
848 __IO uint32_t MMCTIMR;
849 uint32_t RESERVED15[14];
850 __IO uint32_t MMCTSCGPR;
851 __IO uint32_t MMCTMCGPR;
852 uint32_t RESERVED16[5];
853 __IO uint32_t MMCTPCGR;
854 uint32_t RESERVED17[10];
855 __IO uint32_t MMCRCRCEPR;
856 __IO uint32_t MMCRAEPR;
857 uint32_t RESERVED18[10];
858 __IO uint32_t MMCRUPGR;
859 uint32_t RESERVED19[9];
860 __IO uint32_t MMCTLPIMSTR;
861 __IO uint32_t MMCTLPITCR;
862 __IO uint32_t MMCRLPIMSTR;
863 __IO uint32_t MMCRLPITCR;
864 uint32_t RESERVED20[65];
865 __IO uint32_t MACL3L4C0R;
866 __IO uint32_t MACL4A0R;
867 uint32_t RESERVED21[2];
868 __IO uint32_t MACL3A0R0R;
869 __IO uint32_t MACL3A1R0R;
870 __IO uint32_t MACL3A2R0R;
871 __IO uint32_t MACL3A3R0R;
872 uint32_t RESERVED22[4];
873 __IO uint32_t MACL3L4C1R;
874 __IO uint32_t MACL4A1R;
875 uint32_t RESERVED23[2];
876 __IO uint32_t MACL3A0R1R;
877 __IO uint32_t MACL3A1R1R;
878 __IO uint32_t MACL3A2R1R;
879 __IO uint32_t MACL3A3R1R;
880 uint32_t RESERVED24[108];
881 __IO uint32_t MACTSCR;
882 __IO uint32_t MACSSIR;
883 __IO uint32_t MACSTSR;
884 __IO uint32_t MACSTNR;
885 __IO uint32_t MACSTSUR;
886 __IO uint32_t MACSTNUR;
887 __IO uint32_t MACTSAR;
888 uint32_t RESERVED25;
889 __IO uint32_t MACTSSR;
890 uint32_t RESERVED26[3];
891 __IO uint32_t MACTTSSNR;
892 __IO uint32_t MACTTSSSR;
893 uint32_t RESERVED27[2];
894 __IO uint32_t MACACR;
895 uint32_t RESERVED28;
896 __IO uint32_t MACATSNR;
897 __IO uint32_t MACATSSR;
898 __IO uint32_t MACTSIACR;
899 __IO uint32_t MACTSEACR;
900 __IO uint32_t MACTSICNR;
901 __IO uint32_t MACTSECNR;
902 uint32_t RESERVED29[4];
903 __IO uint32_t MACPPSCR;
904 uint32_t RESERVED30[3];
905 __IO uint32_t MACPPSTTSR;
906 __IO uint32_t MACPPSTTNR;
907 __IO uint32_t MACPPSIR;
908 __IO uint32_t MACPPSWR;
909 uint32_t RESERVED31[12];
910 __IO uint32_t MACPOCR;
911 __IO uint32_t MACSPI0R;
912 __IO uint32_t MACSPI1R;
913 __IO uint32_t MACSPI2R;
914 __IO uint32_t MACLMIR;
915 uint32_t RESERVED32[11];
916 __IO uint32_t MTLOMR;
917 uint32_t RESERVED33[7];
918 __IO uint32_t MTLISR;
919 uint32_t RESERVED34[55];
920 __IO uint32_t MTLTQOMR;
921 __IO uint32_t MTLTQUR;
922 __IO uint32_t MTLTQDR;
923 uint32_t RESERVED35[8];
924 __IO uint32_t MTLQICSR;
925 __IO uint32_t MTLRQOMR;
926 __IO uint32_t MTLRQMPOCR;
927 __IO uint32_t MTLRQDR;
928 uint32_t RESERVED36[177];
929 __IO uint32_t DMAMR;
930 __IO uint32_t DMASBMR;
931 __IO uint32_t DMAISR;
932 __IO uint32_t DMADSR;
933 uint32_t RESERVED37[60];
934 __IO uint32_t DMACCR;
935 __IO uint32_t DMACTCR;
936 __IO uint32_t DMACRCR;
937 uint32_t RESERVED38[2];
938 __IO uint32_t DMACTDLAR;
939 uint32_t RESERVED39;
940 __IO uint32_t DMACRDLAR;
941 __IO uint32_t DMACTDTPR;
942 uint32_t RESERVED40;
943 __IO uint32_t DMACRDTPR;
944 __IO uint32_t DMACTDRLR;
945 __IO uint32_t DMACRDRLR;
946 __IO uint32_t DMACIER;
947 __IO uint32_t DMACRIWTR;
948__IO uint32_t DMACSFCSR;
949 uint32_t RESERVED41;
950 __IO uint32_t DMACCATDR;
951 uint32_t RESERVED42;
952 __IO uint32_t DMACCARDR;
953 uint32_t RESERVED43;
954 __IO uint32_t DMACCATBR;
955 uint32_t RESERVED44;
956 __IO uint32_t DMACCARBR;
957 __IO uint32_t DMACSR;
958uint32_t RESERVED45[2];
959__IO uint32_t DMACMFCR;
960}ETH_TypeDef;
961/**
962 * @brief External Interrupt/Event Controller
963 */
964
965typedef struct
966{
967__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */
968__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */
969__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */
970__IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */
971__IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */
972__IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */
973uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */
974__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */
975__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */
976__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */
977__IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */
978__IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */
979__IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */
980uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */
981__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */
982__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */
983__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */
984__IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */
985__IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */
986__IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */
987uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */
988__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */
989__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */
990__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */
991uint32_t RESERVED4; /*!< Reserved, 0x8C */
992__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */
993__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */
994__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */
995uint32_t RESERVED5; /*!< Reserved, 0x9C */
996__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */
997__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */
998__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
999uint32_t RESERVED6[5]; /*!< Reserved, 0xAC to 0xBC */
1000__IO uint32_t C2IMR1; /*!< EXTI Interrupt mask register, Address offset: 0xC0 */
1001__IO uint32_t C2EMR1; /*!< EXTI Event mask register, Address offset: 0xC4 */
1002__IO uint32_t C2PR1; /*!< EXTI Pending register, Address offset: 0xC8 */
1003uint32_t RESERVED7; /*!< Reserved, 0xCC */
1004__IO uint32_t C2IMR2; /*!< EXTI Interrupt mask register, Address offset: 0xD0 */
1005__IO uint32_t C2EMR2; /*!< EXTI Event mask register, Address offset: 0xD4 */
1006__IO uint32_t C2PR2; /*!< EXTI Pending register, Address offset: 0xD8 */
1007uint32_t RESERVED8; /*!< Reserved, 0xDC */
1008__IO uint32_t C2IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xE0 */
1009__IO uint32_t C2EMR3; /*!< EXTI Event mask register, Address offset: 0xE4 */
1010__IO uint32_t C2PR3; /*!< EXTI Pending register, Address offset: 0xE8 */
1011
1012}EXTI_TypeDef;
1013
1014typedef struct
1015{
1016__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
1017__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */
1018__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */
1019uint32_t RESERVED1; /*!< Reserved, 0x0C */
1020__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */
1021__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */
1022__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */
1023uint32_t RESERVED2; /*!< Reserved, 0x1C */
1024__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
1025__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */
1026__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */
1027}EXTI_Core_TypeDef;
1028
1029
1030/**
1031 * @brief FLASH Registers
1032 */
1033
1034typedef struct
1035{
1036 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
1037 __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */
1038 __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */
1039 __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */
1040 __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */
1041 __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */
1042 __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */
1043 __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */
1044 __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */
1045 __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */
1046 __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */
1047 __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */
1048 __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */
1049 __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */
1050 __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */
1051 __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */
1052 __IO uint32_t BOOT7_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */
1053 __IO uint32_t BOOT7_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */
1054 __IO uint32_t BOOT4_CUR; /*!< Flash Current Boot Address for M4 Core Register, Address offset: 0x48 */
1055 __IO uint32_t BOOT4_PRG; /*!< Flash Boot Address to Program for M4 Core Register, Address offset: 0x4C */
1056 __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */
1057 __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */
1058 __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */
1059 __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */
1060 __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */
1061 uint32_t RESERVED1[40]; /*!< Reserved, 0x64 to 0x100 */
1062 __IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */
1063 uint32_t RESERVED2; /*!< Reserved, 0x108 */
1064 __IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */
1065 __IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */
1066 __IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */
1067 uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */
1068 __IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */
1069 __IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */
1070 __IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */
1071 __IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */
1072 __IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */
1073 __IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */
1074 uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */
1075 __IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */
1076 __IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */
1077 __IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */
1078 __IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */
1079 __IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */
1080} FLASH_TypeDef;
1081
1082/**
1083 * @brief Flexible Memory Controller
1084 */
1085
1086typedef struct
1087{
1088 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
1089} FMC_Bank1_TypeDef;
1090
1091/**
1092 * @brief Flexible Memory Controller Bank1E
1093 */
1094
1095typedef struct
1096{
1097 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
1098} FMC_Bank1E_TypeDef;
1099
1100/**
1101 * @brief Flexible Memory Controller Bank2
1102 */
1103
1104typedef struct
1105{
1106 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
1107 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
1108 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
1109 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
1110 uint32_t RESERVED0; /*!< Reserved, 0x70 */
1111 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
1112} FMC_Bank2_TypeDef;
1113
1114/**
1115 * @brief Flexible Memory Controller Bank3
1116 */
1117
1118typedef struct
1119{
1120 __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */
1121 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
1122 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
1123 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
1124 uint32_t RESERVED; /*!< Reserved, 0x90 */
1125 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
1126} FMC_Bank3_TypeDef;
1127
1128/**
1129 * @brief Flexible Memory Controller Bank5 and 6
1130 */
1131
1132
1133typedef struct
1134{
1135 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
1136 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
1137 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
1138 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
1139 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
1140} FMC_Bank5_6_TypeDef;
1141
1142/**
1143 * @brief General Purpose I/O
1144 */
1145
1146typedef struct
1147{
1148 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
1149 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
1150 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
1151 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
1152 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
1153 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
1154 __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */
1155 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
1156 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
1157} GPIO_TypeDef;
1158
1159/**
1160 * @brief Operational Amplifier (OPAMP)
1161 */
1162
1163typedef struct
1164{
1165 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
1166 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
1167 __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
1168} OPAMP_TypeDef;
1169
1170/**
1171 * @brief System configuration controller
1172 */
1173
1174typedef struct
1175{
1176 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */
1177 __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
1178 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
1179 __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */
1180 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
1181 __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */
1182 __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */
1183 __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */
1184 __IO uint32_t PWRCR; /*!< PWR control register, Address offset: 0x2C */
1185 uint32_t RESERVED3[61]; /*!< Reserved, 0x30-0x120 */
1186 __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */
1187 uint32_t RESERVED4[118]; /*!< Reserved, 0x128-0x2FC */
1188 __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */
1189 __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */
1190 __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */
1191 __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */
1192 __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */
1193 __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */
1194 __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */
1195 __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */
1196 __IO uint32_t UR8; /*!< SYSCFG user register 8, Address offset: 0x320 */
1197 __IO uint32_t UR9; /*!< SYSCFG user register 9, Address offset: 0x324 */
1198 __IO uint32_t UR10; /*!< SYSCFG user register 10, Address offset: 0x328 */
1199 __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */
1200 __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */
1201 __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */
1202 __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */
1203 __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */
1204 __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */
1205 __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */
1206
1207} SYSCFG_TypeDef;
1208
1209/**
1210 * @brief Inter-integrated Circuit Interface
1211 */
1212
1213typedef struct
1214{
1215 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
1216 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
1217 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
1218 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
1219 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
1220 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
1221 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
1222 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
1223 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
1224 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
1225 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
1226} I2C_TypeDef;
1227
1228/**
1229 * @brief Independent WATCHDOG
1230 */
1231
1232typedef struct
1233{
1234 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
1235 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
1236 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
1237 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
1238 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
1239} IWDG_TypeDef;
1240
1241
1242/**
1243 * @brief JPEG Codec
1244 */
1245typedef struct
1246{
1247 __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
1248 __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
1249 __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
1250 __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
1251 __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
1252 __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
1253 __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
1254 __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
1255 uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
1256 __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
1257 __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
1258 __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
1259 uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
1260 __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
1261 __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
1262 uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
1263 __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
1264 __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
1265 __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
1266 __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
1267 __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
1268 __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
1269 __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
1270 __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
1271 uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
1272 __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
1273 __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
1274 __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
1275 __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
1276
1277} JPEG_TypeDef;
1278
1279/**
1280 * @brief LCD-TFT Display Controller
1281 */
1282
1283typedef struct
1284{
1285 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
1286 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
1287 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
1288 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
1289 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
1290 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
1291 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
1292 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
1293 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
1294 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
1295 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
1296 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
1297 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
1298 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
1299 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
1300 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
1301 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
1302} LTDC_TypeDef;
1303
1304/**
1305 * @brief LCD-TFT Display layer x Controller
1306 */
1307
1308typedef struct
1309{
1310 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
1311 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
1312 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
1313 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
1314 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
1315 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
1316 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
1317 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
1318 uint32_t RESERVED0[2]; /*!< Reserved */
1319 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
1320 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
1321 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
1322 uint32_t RESERVED1[3]; /*!< Reserved */
1323 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
1324
1325} LTDC_Layer_TypeDef;
1326
1327/**
1328 * @brief Power Control
1329 */
1330
1331typedef struct
1332{
1333 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
1334 __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */
1335 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
1336 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */
1337 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */
1338 __IO uint32_t CPU2CR; /*!< PWR CPU2 control register, Address offset: 0x14 */
1339 __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */
1340 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
1341 __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */
1342 __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */
1343 __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
1344} PWR_TypeDef;
1345
1346/**
1347 * @brief Reset and Clock Control
1348 */
1349
1350typedef struct
1351{
1352 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
1353 __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */
1354 __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */
1355 __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */
1356 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */
1357 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
1358 __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */
1359 __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */
1360 __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */
1361 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
1362 __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */
1363 __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */
1364 __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */
1365 __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */
1366 __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */
1367 __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */
1368 __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */
1369 __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */
1370 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
1371 __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */
1372 __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */
1373 __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */
1374 __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */
1375 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */
1376 __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */
1377 __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */
1378 __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */
1379 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */
1380 __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */
1381 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
1382 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */
1383 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */
1384 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */
1385 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */
1386 __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */
1387 __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */
1388 __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */
1389 __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */
1390 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */
1391 __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */
1392 __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */
1393 uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */
1394 __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */
1395 uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */
1396 __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */
1397 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */
1398 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */
1399 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */
1400 __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */
1401 __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */
1402 __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */
1403 __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */
1404 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */
1405 __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */
1406 uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */
1407 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */
1408 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */
1409 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */
1410 __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */
1411 __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */
1412 __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */
1413 __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */
1414 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */
1415 __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */
1416 uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */
1417
1418} RCC_TypeDef;
1419
1420typedef struct
1421{
1422 __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0x00 */
1423 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x04 */
1424 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x08 */
1425 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x0C */
1426 __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0x10 */
1427 __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0x14 */
1428 __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0x18 */
1429 __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0x1C */
1430 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0x20 */
1431 __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0x24 */
1432 uint32_t RESERVED9; /*!< Reserved, Address offset: 0x28 */
1433 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0x3C */
1434 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x40 */
1435 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x44 */
1436 __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x48 */
1437 __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x4C */
1438 __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x50 */
1439 __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x54 */
1440 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x58 */
1441 __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x5C */
1442 uint32_t RESERVED10[4]; /*!< Reserved, 0x60-0x6C Address offset: 0x60 */
1443
1444} RCC_Core_TypeDef;
1445
1446/**
1447 * @brief Real-Time Clock
1448 */
1449typedef struct
1450{
1451 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
1452 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
1453 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
1454 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
1455 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
1456 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
1457 uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
1458 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
1459 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
1460 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
1461 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
1462 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
1463 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
1464 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
1465 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
1466 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
1467 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
1468 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
1469 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
1470 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
1471 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
1472 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
1473 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
1474 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
1475 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
1476 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
1477 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
1478 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
1479 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
1480 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
1481 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
1482 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
1483 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
1484 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
1485 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
1486 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
1487 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
1488 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
1489 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
1490 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
1491 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
1492 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
1493 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
1494 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
1495 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
1496 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
1497 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
1498 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
1499 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
1500 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
1501 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
1502 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
1503} RTC_TypeDef;
1504
1505/**
1506 * @brief Serial Audio Interface
1507 */
1508
1509typedef struct
1510{
1511 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
1512 uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
1513 __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
1514 __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
1515} SAI_TypeDef;
1516
1517typedef struct
1518{
1519 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
1520 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
1521 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
1522 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
1523 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
1524 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
1525 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
1526 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
1527} SAI_Block_TypeDef;
1528
1529/**
1530 * @brief SPDIF-RX Interface
1531 */
1532
1533typedef struct
1534{
1535 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
1536 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
1537 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
1538 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
1539 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
1540 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
1541 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
1542 uint32_t RESERVED2; /*!< Reserved, 0x1A */
1543} SPDIFRX_TypeDef;
1544
1545
1546/**
1547 * @brief Secure digital input/output Interface
1548 */
1549
1550typedef struct
1551{
1552 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
1553 __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
1554 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
1555 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
1556 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
1557 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
1558 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
1559 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
1560 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
1561 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
1562 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
1563 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
1564 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
1565 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
1566 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
1567 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
1568 __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
1569 uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
1570 __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
1571 __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
1572 __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
1573 __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
1574 uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
1575 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
1576 uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */
1577 __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */
1578} SDMMC_TypeDef;
1579
1580
1581/**
1582 * @brief Delay Block DLYB
1583 */
1584
1585typedef struct
1586{
1587 __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */
1588 __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */
1589} DLYB_TypeDef;
1590
1591/**
1592 * @brief HW Semaphore HSEM
1593 */
1594
1595typedef struct
1596{
1597 __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */
1598 __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */
1599 __IO uint32_t C1IER; /*!< HSEM Interrupt 0 enable register , Address offset: 100h */
1600 __IO uint32_t C1ICR; /*!< HSEM Interrupt 0 clear register , Address offset: 104h */
1601 __IO uint32_t C1ISR; /*!< HSEM Interrupt 0 Status register , Address offset: 108h */
1602 __IO uint32_t C1MISR; /*!< HSEM Interrupt 0 Masked Status register , Address offset: 10Ch */
1603 __IO uint32_t C2IER; /*!< HSEM Interrupt 1 enable register , Address offset: 110h */
1604 __IO uint32_t C2ICR; /*!< HSEM Interrupt 1 clear register , Address offset: 114h */
1605 __IO uint32_t C2ISR; /*!< HSEM Interrupt 1 Status register , Address offset: 118h */
1606 __IO uint32_t C2MISR; /*!< HSEM Interrupt 1 Masked Status register , Address offset: 11Ch */
1607 uint32_t Reserved[8]; /* Reserved Address offset: 120h-13Ch*/
1608 __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */
1609 __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */
1610
1611} HSEM_TypeDef;
1612
1613typedef struct
1614{
1615 __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */
1616 __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */
1617 __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */
1618 __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */
1619} HSEM_Common_TypeDef;
1620
1621/**
1622 * @brief Serial Peripheral Interface
1623 */
1624
1625typedef struct
1626{
1627 __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */
1628 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
1629 __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */
1630 __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */
1631 __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */
1632 __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */
1633 __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */
1634 uint32_t RESERVED0; /*!< Reserved, 0x1C */
1635 __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */
1636 uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */
1637 __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */
1638 uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
1639 __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */
1640 __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */
1641 __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */
1642 __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */
1643 __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */
1644
1645} SPI_TypeDef;
1646/**
1647 * @brief QUAD Serial Peripheral Interface
1648 */
1649
1650typedef struct
1651{
1652 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
1653 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
1654 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
1655 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
1656 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
1657 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
1658 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
1659 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
1660 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
1661 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
1662 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
1663 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
1664 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
1665} QUADSPI_TypeDef;
1666
1667/**
1668 * @brief TIM
1669 */
1670
1671typedef struct
1672{
1673 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
1674 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
1675 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
1676 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
1677 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
1678 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
1679 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
1680 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
1681 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
1682 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
1683 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
1684 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
1685 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
1686 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
1687 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
1688 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
1689 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
1690 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
1691 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
1692 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
1693 uint32_t RESERVED1; /*!< Reserved, 0x50 */
1694 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
1695 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
1696 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
1697 __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
1698 __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
1699 __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
1700} TIM_TypeDef;
1701
1702/**
1703 * @brief LPTIMIMER
1704 */
1705typedef struct
1706{
1707 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
1708 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
1709 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
1710 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
1711 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
1712 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
1713 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
1714 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
1715 uint32_t RESERVED1; /*!< Reserved, 0x20 */
1716 __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */
1717} LPTIM_TypeDef;
1718
1719/**
1720 * @brief Comparator
1721 */
1722typedef struct
1723{
1724 __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */
1725 __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */
1726 __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */
1727} COMPOPT_TypeDef;
1728
1729typedef struct
1730{
1731 __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */
1732} COMP_TypeDef;
1733
1734typedef struct
1735{
1736 __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
1737} COMP_Common_TypeDef;
1738/**
1739 * @brief Universal Synchronous Asynchronous Receiver Transmitter
1740 */
1741
1742typedef struct
1743{
1744 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
1745 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
1746 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
1747 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
1748 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
1749 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
1750 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
1751 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
1752 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
1753 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
1754 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
1755 __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */
1756} USART_TypeDef;
1757
1758/**
1759 * @brief Single Wire Protocol Master Interface SPWMI
1760 */
1761typedef struct
1762{
1763 __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
1764 __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
1765 uint32_t RESERVED1; /*!< Reserved, 0x08 */
1766 __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
1767 __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
1768 __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
1769 __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
1770 __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
1771 __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
1772 __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
1773} SWPMI_TypeDef;
1774
1775/**
1776 * @brief Window WATCHDOG
1777 */
1778
1779typedef struct
1780{
1781 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
1782 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
1783 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
1784} WWDG_TypeDef;
1785
1786
1787/**
1788 * @brief RAM_ECC_Specific_Registers
1789 */
1790typedef struct
1791{
1792 __IO uint32_t CR; /*!< RAMECC monitor configuration register */
1793 __IO uint32_t SR; /*!< RAMECC monitor status register */
1794 __IO uint32_t FAR; /*!< RAMECC monitor failing address register */
1795 __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */
1796 __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */
1797 __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */
1798} RAMECC_MonitorTypeDef;
1799
1800typedef struct
1801{
1802 __IO uint32_t IER; /*!< RAMECC interrupt enable register */
1803} RAMECC_TypeDef;
1804/**
1805 * @}
1806 */
1807
1808
1809/**
1810 * @brief Crypto Processor
1811 */
1812
1813typedef struct
1814{
1815 __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
1816 __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
1817 __IO uint32_t DIN; /*!< CRYP data input register, Address offset: 0x08 */
1818 __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
1819 __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
1820 __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
1821 __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
1822 __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
1823 __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
1824 __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
1825 __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
1826 __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
1827 __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
1828 __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
1829 __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
1830 __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
1831 __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
1832 __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
1833 __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
1834 __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
1835 __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
1836 __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
1837 __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
1838 __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
1839 __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
1840 __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
1841 __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
1842 __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
1843 __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
1844 __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
1845 __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
1846 __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
1847 __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
1848 __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
1849 __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
1850 __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
1851} CRYP_TypeDef;
1852
1853/**
1854 * @brief HASH
1855 */
1856
1857typedef struct
1858{
1859 __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
1860 __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
1861 __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
1862 __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
1863 __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
1864 __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
1865 uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
1866 __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
1867} HASH_TypeDef;
1868
1869/**
1870 * @brief HASH_DIGEST
1871 */
1872
1873typedef struct
1874{
1875 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
1876} HASH_DIGEST_TypeDef;
1877
1878
1879/**
1880 * @brief High resolution Timer (HRTIM)
1881 */
1882/* HRTIM master registers definition */
1883typedef struct
1884{
1885 __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
1886 __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
1887 __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
1888 __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
1889 __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
1890 __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
1891 __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */
1892 __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */
1893 uint32_t RESERVED0; /*!< Reserved, 0x20 */
1894 __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */
1895 __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */
1896 __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */
1897 uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */
1898}HRTIM_Master_TypeDef;
1899
1900/* HRTIM Timer A to E registers definition */
1901typedef struct
1902{
1903 __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */
1904 __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */
1905 __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */
1906 __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */
1907 __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */
1908 __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */
1909 __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */
1910 __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */
1911 __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */
1912 __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */
1913 __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */
1914 __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */
1915 __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */
1916 __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */
1917 __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */
1918 __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */
1919 __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */
1920 __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */
1921 __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */
1922 __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */
1923 __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */
1924 __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */
1925 __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */
1926 __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */
1927 __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */
1928 __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */
1929 __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */
1930 uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */
1931}HRTIM_Timerx_TypeDef;
1932
1933/* HRTIM common register definition */
1934typedef struct
1935{
1936 __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */
1937 __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */
1938 __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */
1939 __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */
1940 __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */
1941 __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */
1942 __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
1943 __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
1944 __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
1945 __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
1946 __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
1947 __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
1948 __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
1949 __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */
1950 __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */
1951 __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */
1952 __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */
1953 __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */
1954 __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */
1955 __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x4C */
1956 __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */
1957 __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */
1958 __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */
1959 __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */
1960 __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */
1961 __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */
1962 __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */
1963 __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */
1964 __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */
1965}HRTIM_Common_TypeDef;
1966
1967/* HRTIM register definition */
1968typedef struct {
1969 HRTIM_Master_TypeDef sMasterRegs;
1970 HRTIM_Timerx_TypeDef sTimerxRegs[5];
1971 uint32_t RESERVED0[32];
1972 HRTIM_Common_TypeDef sCommonRegs;
1973}HRTIM_TypeDef;
1974/**
1975 * @brief RNG
1976 */
1977
1978typedef struct
1979{
1980 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
1981 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
1982 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
1983} RNG_TypeDef;
1984
1985/**
1986 * @brief MDIOS
1987 */
1988
1989typedef struct
1990{
1991 __IO uint32_t CR;
1992 __IO uint32_t WRFR;
1993 __IO uint32_t CWRFR;
1994 __IO uint32_t RDFR;
1995 __IO uint32_t CRDFR;
1996 __IO uint32_t SR;
1997 __IO uint32_t CLRFR;
1998 uint32_t RESERVED[57];
1999 __IO uint32_t DINR0;
2000 __IO uint32_t DINR1;
2001 __IO uint32_t DINR2;
2002 __IO uint32_t DINR3;
2003 __IO uint32_t DINR4;
2004 __IO uint32_t DINR5;
2005 __IO uint32_t DINR6;
2006 __IO uint32_t DINR7;
2007 __IO uint32_t DINR8;
2008 __IO uint32_t DINR9;
2009 __IO uint32_t DINR10;
2010 __IO uint32_t DINR11;
2011 __IO uint32_t DINR12;
2012 __IO uint32_t DINR13;
2013 __IO uint32_t DINR14;
2014 __IO uint32_t DINR15;
2015 __IO uint32_t DINR16;
2016 __IO uint32_t DINR17;
2017 __IO uint32_t DINR18;
2018 __IO uint32_t DINR19;
2019 __IO uint32_t DINR20;
2020 __IO uint32_t DINR21;
2021 __IO uint32_t DINR22;
2022 __IO uint32_t DINR23;
2023 __IO uint32_t DINR24;
2024 __IO uint32_t DINR25;
2025 __IO uint32_t DINR26;
2026 __IO uint32_t DINR27;
2027 __IO uint32_t DINR28;
2028 __IO uint32_t DINR29;
2029 __IO uint32_t DINR30;
2030 __IO uint32_t DINR31;
2031 __IO uint32_t DOUTR0;
2032 __IO uint32_t DOUTR1;
2033 __IO uint32_t DOUTR2;
2034 __IO uint32_t DOUTR3;
2035 __IO uint32_t DOUTR4;
2036 __IO uint32_t DOUTR5;
2037 __IO uint32_t DOUTR6;
2038 __IO uint32_t DOUTR7;
2039 __IO uint32_t DOUTR8;
2040 __IO uint32_t DOUTR9;
2041 __IO uint32_t DOUTR10;
2042 __IO uint32_t DOUTR11;
2043 __IO uint32_t DOUTR12;
2044 __IO uint32_t DOUTR13;
2045 __IO uint32_t DOUTR14;
2046 __IO uint32_t DOUTR15;
2047 __IO uint32_t DOUTR16;
2048 __IO uint32_t DOUTR17;
2049 __IO uint32_t DOUTR18;
2050 __IO uint32_t DOUTR19;
2051 __IO uint32_t DOUTR20;
2052 __IO uint32_t DOUTR21;
2053 __IO uint32_t DOUTR22;
2054 __IO uint32_t DOUTR23;
2055 __IO uint32_t DOUTR24;
2056 __IO uint32_t DOUTR25;
2057 __IO uint32_t DOUTR26;
2058 __IO uint32_t DOUTR27;
2059 __IO uint32_t DOUTR28;
2060 __IO uint32_t DOUTR29;
2061 __IO uint32_t DOUTR30;
2062 __IO uint32_t DOUTR31;
2063} MDIOS_TypeDef;
2064
2065
2066/**
2067 * @brief USB_OTG_Core_Registers
2068 */
2069typedef struct
2070{
2071 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
2072 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
2073 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
2074 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
2075 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
2076 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
2077 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
2078 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
2079 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
2080 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
2081 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
2082 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
2083 uint32_t Reserved30[2]; /*!< Reserved 030h */
2084 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
2085 __IO uint32_t CID; /*!< User ID Register 03Ch */
2086 __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
2087 __IO uint32_t GHWCFG1; /* User HW config1 044h*/
2088 __IO uint32_t GHWCFG2; /* User HW config2 048h*/
2089 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
2090 uint32_t Reserved6; /*!< Reserved 050h */
2091 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
2092 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
2093 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
2094 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
2095 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
2096 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
2097 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
2098} USB_OTG_GlobalTypeDef;
2099
2100
2101/**
2102 * @brief USB_OTG_device_Registers
2103 */
2104typedef struct
2105{
2106 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
2107 __IO uint32_t DCTL; /*!< dev Control Register 804h */
2108 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
2109 uint32_t Reserved0C; /*!< Reserved 80Ch */
2110 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
2111 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
2112 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
2113 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
2114 uint32_t Reserved20; /*!< Reserved 820h */
2115 uint32_t Reserved9; /*!< Reserved 824h */
2116 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
2117 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
2118 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
2119 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
2120 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
2121 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
2122 uint32_t Reserved40; /*!< dedicated EP mask 840h */
2123 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
2124 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
2125 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
2126} USB_OTG_DeviceTypeDef;
2127
2128
2129/**
2130 * @brief USB_OTG_IN_Endpoint-Specific_Register
2131 */
2132typedef struct
2133{
2134 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
2135 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
2136 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
2137 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
2138 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
2139 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
2140 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
2141 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
2142} USB_OTG_INEndpointTypeDef;
2143
2144
2145/**
2146 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
2147 */
2148typedef struct
2149{
2150 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
2151 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
2152 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
2153 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
2154 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
2155 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
2156 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
2157} USB_OTG_OUTEndpointTypeDef;
2158
2159
2160/**
2161 * @brief USB_OTG_Host_Mode_Register_Structures
2162 */
2163typedef struct
2164{
2165 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
2166 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
2167 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
2168 uint32_t Reserved40C; /*!< Reserved 40Ch */
2169 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
2170 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
2171 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
2172} USB_OTG_HostTypeDef;
2173
2174/**
2175 * @brief USB_OTG_Host_Channel_Specific_Registers
2176 */
2177typedef struct
2178{
2179 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
2180 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
2181 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
2182 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
2183 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
2184 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
2185 uint32_t Reserved[2]; /*!< Reserved */
2186} USB_OTG_HostChannelTypeDef;
2187/**
2188 * @}
2189 */
2190
2191
2192/** @addtogroup Peripheral_memory_map
2193 * @{
2194 */
2195#define D1_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */
2196#define D1_ITCMICP_BASE (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */
2197#define D1_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM */
2198#define D1_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
2199#define D1_AXIICP_BASE (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */
2200#define D1_AXISRAM_BASE (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI */
2201
2202#define D2_AXISRAM_BASE (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI */
2203#define D2_AHBSRAM_BASE (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge */
2204
2205#define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */
2206#define D3_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */
2207
2208#define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/APB Peripherals */
2209#define QSPI_BASE (0x90000000UL) /*!< Base address of : QSPI memories accessible over AXI */
2210
2211#define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */
2212#define FLASH_BANK2_BASE (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI */
2213#define FLASH_END (0x081FFFFFUL) /*!< FLASH end address */
2214
2215/* Legacy define */
2216#define FLASH_BASE FLASH_BANK1_BASE
2217
2218/*!< Device electronic signature memory map */
2219#define UID_BASE (0x1FF1E800UL) /*!< Unique device ID register base address */
2220#define FLASHSIZE_BASE (0x1FF1E880UL) /*!< FLASH Size register base address */
2221
2222
2223/*!< Peripheral memory map */
2224#define D2_APB1PERIPH_BASE PERIPH_BASE
2225#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
2226#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
2227#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL)
2228
2229#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
2230#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL)
2231
2232#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL)
2233#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL)
2234
2235/*!< Legacy Peripheral memory map */
2236#define APB1PERIPH_BASE PERIPH_BASE
2237#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
2238#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
2239#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
2240
2241
2242/*!< D1_AHB1PERIPH peripherals */
2243
2244#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL)
2245#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL)
2246#define JPGDEC_BASE (D1_AHB1PERIPH_BASE + 0x3000UL)
2247#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL)
2248#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL)
2249#define QSPI_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL)
2250#define DLYB_QSPI_BASE (D1_AHB1PERIPH_BASE + 0x6000UL)
2251#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL)
2252#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL)
2253#define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL)
2254
2255/*!< D2_AHB1PERIPH peripherals */
2256
2257#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL)
2258#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL)
2259#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL)
2260#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL)
2261#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL)
2262#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL)
2263#define ART_BASE (D2_AHB1PERIPH_BASE + 0x4400UL)
2264#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL)
2265#define ETH_MAC_BASE (ETH_BASE)
2266
2267/*!< USB registers base address */
2268#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL)
2269#define USB2_OTG_FS_PERIPH_BASE (0x40080000UL)
2270#define USB_OTG_GLOBAL_BASE (0x000UL)
2271#define USB_OTG_DEVICE_BASE (0x800UL)
2272#define USB_OTG_IN_ENDPOINT_BASE (0x900UL)
2273#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL)
2274#define USB_OTG_EP_REG_SIZE (0x20UL)
2275#define USB_OTG_HOST_BASE (0x400UL)
2276#define USB_OTG_HOST_PORT_BASE (0x440UL)
2277#define USB_OTG_HOST_CHANNEL_BASE (0x500UL)
2278#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL)
2279#define USB_OTG_PCGCCTL_BASE (0xE00UL)
2280#define USB_OTG_FIFO_BASE (0x1000UL)
2281#define USB_OTG_FIFO_SIZE (0x1000UL)
2282
2283/*!< D2_AHB2PERIPH peripherals */
2284
2285#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL)
2286#define CRYP_BASE (D2_AHB2PERIPH_BASE + 0x1000UL)
2287#define HASH_BASE (D2_AHB2PERIPH_BASE + 0x1400UL)
2288#define HASH_DIGEST_BASE (D2_AHB2PERIPH_BASE + 0x1710UL)
2289#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL)
2290#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL)
2291#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL)
2292#define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL)
2293
2294/*!< D3_AHB1PERIPH peripherals */
2295#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL)
2296#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL)
2297#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL)
2298#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL)
2299#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL)
2300#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL)
2301#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL)
2302#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL)
2303#define GPIOI_BASE (D3_AHB1PERIPH_BASE + 0x2000UL)
2304#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL)
2305#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL)
2306#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL)
2307#define RCC_C1_BASE (RCC_BASE + 0x130UL)
2308#define RCC_C2_BASE (RCC_BASE + 0x190UL)
2309#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL)
2310#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL)
2311#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL)
2312#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL)
2313#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL)
2314#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL)
2315#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL)
2316#define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL)
2317
2318/*!< D1_APB1PERIPH peripherals */
2319#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL)
2320#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)
2321#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)
2322#define DSI_BASE (D1_APB1PERIPH_BASE)
2323#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL)
2324
2325/*!< D2_APB1PERIPH peripherals */
2326#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL)
2327#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL)
2328#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL)
2329#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL)
2330#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL)
2331#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL)
2332#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL)
2333#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL)
2334#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL)
2335#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL)
2336
2337#define WWDG2_BASE (D2_APB1PERIPH_BASE + 0x2C00UL)
2338
2339#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL)
2340#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL)
2341#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL)
2342#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL)
2343#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL)
2344#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL)
2345#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL)
2346#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL)
2347#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL)
2348#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL)
2349#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL)
2350#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL)
2351#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL)
2352#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL)
2353#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL)
2354#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL)
2355#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
2356#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
2357#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL)
2358#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL)
2359#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL)
2360#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL)
2361#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL)
2362#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL)
2363
2364/*!< D2_APB2PERIPH peripherals */
2365
2366#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL)
2367#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL)
2368#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL)
2369#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL)
2370#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL)
2371#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL)
2372#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL)
2373#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL)
2374#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL)
2375#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL)
2376#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL)
2377#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
2378#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
2379#define SAI2_BASE (D2_APB2PERIPH_BASE + 0x5C00UL)
2380#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
2381#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
2382#define SAI3_BASE (D2_APB2PERIPH_BASE + 0x6000UL)
2383#define SAI3_Block_A_BASE (SAI3_BASE + 0x004UL)
2384#define SAI3_Block_B_BASE (SAI3_BASE + 0x024UL)
2385#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7000UL)
2386#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
2387#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
2388#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
2389#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
2390#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)
2391#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)
2392#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)
2393#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)
2394#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
2395#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
2396#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)
2397#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)
2398#define HRTIM1_BASE (D2_APB2PERIPH_BASE + 0x7400UL)
2399#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080UL)
2400#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100UL)
2401#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180UL)
2402#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200UL)
2403#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280UL)
2404#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380UL)
2405
2406
2407/*!< D3_APB1PERIPH peripherals */
2408#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL)
2409#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL)
2410#define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL)
2411#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL)
2412#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL)
2413#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL)
2414#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL)
2415#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL)
2416#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL)
2417#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL)
2418#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL)
2419#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL)
2420#define COMP1_BASE (COMP12_BASE + 0x0CUL)
2421#define COMP2_BASE (COMP12_BASE + 0x10UL)
2422#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL)
2423#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL)
2424#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL)
2425
2426#define IWDG2_BASE (D3_APB1PERIPH_BASE + 0x4C00UL)
2427
2428#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL)
2429#define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL)
2430#define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL)
2431
2432
2433
2434
2435#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL)
2436#define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL)
2437#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL)
2438#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL)
2439#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL)
2440#define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL)
2441#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL)
2442#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL)
2443
2444#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE)
2445#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL)
2446#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL)
2447#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL)
2448#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL)
2449#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL)
2450#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL)
2451#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL)
2452
2453#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL)
2454#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL)
2455#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL)
2456#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL)
2457#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL)
2458#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL)
2459#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL)
2460#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL)
2461
2462#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL)
2463#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL)
2464
2465#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
2466#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
2467#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
2468#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
2469#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
2470#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
2471#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
2472#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
2473
2474#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
2475#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
2476#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
2477#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
2478#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
2479#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
2480#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
2481#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
2482
2483#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
2484#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
2485#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
2486#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
2487#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
2488#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
2489#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
2490#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
2491#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
2492#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
2493#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
2494#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
2495#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
2496#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
2497#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
2498#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
2499
2500#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
2501#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
2502#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
2503#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
2504#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL)
2505#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL)
2506#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL)
2507#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL)
2508
2509#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
2510#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
2511
2512/*!< FMC Banks registers base address */
2513#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
2514#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
2515#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL)
2516#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
2517#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
2518
2519/* Debug MCU registers base address */
2520#define DBGMCU_BASE (0x5C001000UL)
2521
2522#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL)
2523#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL)
2524#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL)
2525#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL)
2526#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL)
2527#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL)
2528#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL)
2529#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL)
2530#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL)
2531#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL)
2532#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL)
2533#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL)
2534#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL)
2535#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
2536#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
2537#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
2538
2539#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)
2540#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)
2541#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)
2542#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)
2543#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)
2544
2545#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)
2546#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)
2547#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)
2548#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)
2549#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)
2550
2551#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)
2552#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
2553
2554
2555/**
2556 * @}
2557 */
2558
2559/** @addtogroup Peripheral_declaration
2560 * @{
2561 */
2562#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
2563#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
2564#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
2565#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
2566#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
2567#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
2568#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
2569#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
2570#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
2571#define RTC ((RTC_TypeDef *) RTC_BASE)
2572#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)
2573
2574#define WWDG2 ((WWDG_TypeDef *) WWDG2_BASE)
2575#define IWDG2 ((IWDG_TypeDef *) IWDG2_BASE)
2576
2577#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)
2578#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
2579#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
2580#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
2581#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
2582#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
2583#define USART2 ((USART_TypeDef *) USART2_BASE)
2584#define USART3 ((USART_TypeDef *) USART3_BASE)
2585#define USART6 ((USART_TypeDef *) USART6_BASE)
2586#define UART7 ((USART_TypeDef *) UART7_BASE)
2587#define UART8 ((USART_TypeDef *) UART8_BASE)
2588#define CRS ((CRS_TypeDef *) CRS_BASE)
2589#define UART4 ((USART_TypeDef *) UART4_BASE)
2590#define UART5 ((USART_TypeDef *) UART5_BASE)
2591#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
2592#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
2593#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
2594#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
2595#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
2596#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
2597#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
2598#define CEC ((CEC_TypeDef *) CEC_BASE)
2599#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
2600#define PWR ((PWR_TypeDef *) PWR_BASE)
2601#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
2602#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
2603#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
2604#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
2605#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)
2606#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)
2607#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)
2608
2609#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
2610#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)
2611#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
2612#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
2613#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
2614#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
2615#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
2616#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
2617
2618
2619#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
2620#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
2621#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
2622#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
2623#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
2624#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
2625#define USART1 ((USART_TypeDef *) USART1_BASE)
2626#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
2627#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
2628#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
2629#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
2630#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
2631#define HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)
2632#define HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)
2633#define HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)
2634#define HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)
2635#define HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)
2636#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
2637#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
2638#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
2639#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
2640#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
2641#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
2642#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
2643#define SAI3 ((SAI_TypeDef *) SAI3_BASE)
2644#define SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)
2645#define SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)
2646#define SAI4 ((SAI_TypeDef *) SAI4_BASE)
2647#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
2648#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
2649
2650#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
2651#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
2652#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
2653#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
2654#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
2655#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
2656#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
2657#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
2658#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
2659#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
2660#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
2661#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
2662#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
2663#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)
2664#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
2665#define RCC ((RCC_TypeDef *) RCC_BASE)
2666#define RCC_C1 ((RCC_Core_TypeDef *) RCC_C1_BASE)
2667#define RCC_C2 ((RCC_Core_TypeDef *) RCC_C2_BASE)
2668
2669#define ART ((ART_TypeDef *) ART_BASE)
2670#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
2671#define CRC ((CRC_TypeDef *) CRC_BASE)
2672
2673#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
2674#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
2675#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
2676#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
2677#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
2678#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
2679#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
2680#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
2681#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
2682#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
2683#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
2684
2685#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
2686#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
2687#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
2688#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)
2689#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
2690
2691#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
2692#define HASH ((HASH_TypeDef *) HASH_BASE)
2693#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
2694#define RNG ((RNG_TypeDef *) RNG_BASE)
2695#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
2696#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
2697
2698#define BDMA ((BDMA_TypeDef *) BDMA_BASE)
2699#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)
2700#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)
2701#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)
2702#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)
2703#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)
2704#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)
2705#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)
2706#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)
2707
2708#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)
2709#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)
2710#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)
2711#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)
2712#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)
2713#define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)
2714
2715#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)
2716#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)
2717#define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)
2718#define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)
2719#define RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)
2720#define RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)
2721
2722#define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)
2723#define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)
2724#define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)
2725
2726#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
2727#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
2728#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
2729#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
2730#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
2731#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
2732#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
2733#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
2734#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
2735
2736
2737#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
2738#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
2739#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
2740#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
2741#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
2742#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
2743#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
2744#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
2745
2746#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
2747#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
2748
2749#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
2750#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
2751#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
2752#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
2753#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
2754#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
2755#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
2756#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
2757#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
2758
2759#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
2760#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
2761#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
2762#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
2763#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
2764#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
2765#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
2766#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
2767#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
2768
2769
2770#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
2771#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
2772#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
2773#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
2774#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
2775#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
2776#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
2777#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
2778#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
2779#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
2780#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
2781#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
2782#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
2783#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
2784#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
2785#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
2786#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
2787
2788#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
2789#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
2790#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
2791#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
2792#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
2793#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
2794#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
2795#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
2796
2797#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
2798#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
2799
2800
2801#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
2802#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
2803#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
2804#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
2805#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
2806
2807
2808#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
2809#define DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)
2810#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
2811#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
2812
2813#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
2814
2815#define JPEG ((JPEG_TypeDef *) JPGDEC_BASE)
2816#define HSEM ((HSEM_TypeDef *) HSEM_BASE)
2817#if defined(CORE_CM4)
2818#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x110UL))
2819#else /* CORE_CM7 */
2820#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
2821#endif /* CORE_CM4 */
2822
2823#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
2824#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
2825#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
2826#define DSI ((DSI_TypeDef *)DSI_BASE)
2827
2828#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
2829
2830#define ETH ((ETH_TypeDef *)ETH_BASE)
2831#define MDMA ((MDMA_TypeDef *)MDMA_BASE)
2832#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
2833#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
2834#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
2835#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
2836#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
2837#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
2838#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
2839#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
2840#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
2841#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
2842#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
2843#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
2844#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
2845#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
2846#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
2847#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
2848
2849
2850#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
2851#define USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)
2852
2853/* Legacy defines */
2854#define USB_OTG_HS USB1_OTG_HS
2855#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
2856#define USB_OTG_FS USB2_OTG_FS
2857#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
2858
2859/**
2860 * @}
2861 */
2862
2863/** @addtogroup Exported_constants
2864 * @{
2865 */
2866
2867 /** @addtogroup Peripheral_Registers_Bits_Definition
2868 * @{
2869 */
2870
2871/******************************************************************************/
2872/* Peripheral Registers_Bits_Definition */
2873/******************************************************************************/
2874
2875/******************************************************************************/
2876/* */
2877/* Analog to Digital Converter */
2878/* */
2879/******************************************************************************/
2880/******************************* ADC VERSION ********************************/
2881#define ADC_VER_V5_X
2882/******************** Bit definition for ADC_ISR register ********************/
2883#define ADC_ISR_ADRDY_Pos (0U)
2884#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
2885#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */
2886#define ADC_ISR_EOSMP_Pos (1U)
2887#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
2888#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */
2889#define ADC_ISR_EOC_Pos (2U)
2890#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
2891#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */
2892#define ADC_ISR_EOS_Pos (3U)
2893#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
2894#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */
2895#define ADC_ISR_OVR_Pos (4U)
2896#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
2897#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */
2898#define ADC_ISR_JEOC_Pos (5U)
2899#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
2900#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */
2901#define ADC_ISR_JEOS_Pos (6U)
2902#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
2903#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */
2904#define ADC_ISR_AWD1_Pos (7U)
2905#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
2906#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */
2907#define ADC_ISR_AWD2_Pos (8U)
2908#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
2909#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */
2910#define ADC_ISR_AWD3_Pos (9U)
2911#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
2912#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */
2913#define ADC_ISR_JQOVF_Pos (10U)
2914#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
2915#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
2916
2917/******************** Bit definition for ADC_IER register ********************/
2918#define ADC_IER_ADRDYIE_Pos (0U)
2919#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
2920#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */
2921#define ADC_IER_EOSMPIE_Pos (1U)
2922#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
2923#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */
2924#define ADC_IER_EOCIE_Pos (2U)
2925#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
2926#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */
2927#define ADC_IER_EOSIE_Pos (3U)
2928#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
2929#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */
2930#define ADC_IER_OVRIE_Pos (4U)
2931#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
2932#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */
2933#define ADC_IER_JEOCIE_Pos (5U)
2934#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
2935#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */
2936#define ADC_IER_JEOSIE_Pos (6U)
2937#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
2938#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */
2939#define ADC_IER_AWD1IE_Pos (7U)
2940#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
2941#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */
2942#define ADC_IER_AWD2IE_Pos (8U)
2943#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
2944#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */
2945#define ADC_IER_AWD3IE_Pos (9U)
2946#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
2947#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */
2948#define ADC_IER_JQOVFIE_Pos (10U)
2949#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
2950#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */
2951
2952/******************** Bit definition for ADC_CR register ********************/
2953#define ADC_CR_ADEN_Pos (0U)
2954#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
2955#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */
2956#define ADC_CR_ADDIS_Pos (1U)
2957#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
2958#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */
2959#define ADC_CR_ADSTART_Pos (2U)
2960#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
2961#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */
2962#define ADC_CR_JADSTART_Pos (3U)
2963#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
2964#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */
2965#define ADC_CR_ADSTP_Pos (4U)
2966#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
2967#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */
2968#define ADC_CR_JADSTP_Pos (5U)
2969#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
2970#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */
2971#define ADC_CR_BOOST_Pos (8U)
2972#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */
2973#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */
2974#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */
2975#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */
2976#define ADC_CR_ADCALLIN_Pos (16U)
2977#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */
2978#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */
2979#define ADC_CR_LINCALRDYW1_Pos (22U)
2980#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */
2981#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */
2982#define ADC_CR_LINCALRDYW2_Pos (23U)
2983#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */
2984#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */
2985#define ADC_CR_LINCALRDYW3_Pos (24U)
2986#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */
2987#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */
2988#define ADC_CR_LINCALRDYW4_Pos (25U)
2989#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */
2990#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */
2991#define ADC_CR_LINCALRDYW5_Pos (26U)
2992#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */
2993#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */
2994#define ADC_CR_LINCALRDYW6_Pos (27U)
2995#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */
2996#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */
2997#define ADC_CR_ADVREGEN_Pos (28U)
2998#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
2999#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */
3000#define ADC_CR_DEEPPWD_Pos (29U)
3001#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
3002#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */
3003#define ADC_CR_ADCALDIF_Pos (30U)
3004#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
3005#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */
3006#define ADC_CR_ADCAL_Pos (31U)
3007#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
3008#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */
3009
3010/******************** Bit definition for ADC_CFGR register ********************/
3011#define ADC_CFGR_DMNGT_Pos (0U)
3012#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */
3013#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */
3014#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */
3015#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */
3016
3017#define ADC_CFGR_RES_Pos (2U)
3018#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */
3019#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */
3020#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */
3021#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
3022#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
3023
3024#define ADC_CFGR_EXTSEL_Pos (5U)
3025#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
3026#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */
3027#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
3028#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
3029#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
3030#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
3031#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
3032
3033#define ADC_CFGR_EXTEN_Pos (10U)
3034#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
3035#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */
3036#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
3037#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
3038
3039#define ADC_CFGR_OVRMOD_Pos (12U)
3040#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
3041#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */
3042#define ADC_CFGR_CONT_Pos (13U)
3043#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
3044#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */
3045#define ADC_CFGR_AUTDLY_Pos (14U)
3046#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
3047#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */
3048
3049#define ADC_CFGR_DISCEN_Pos (16U)
3050#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
3051#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */
3052
3053#define ADC_CFGR_DISCNUM_Pos (17U)
3054#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
3055#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
3056#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
3057#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
3058#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
3059
3060#define ADC_CFGR_JDISCEN_Pos (20U)
3061#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
3062#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
3063#define ADC_CFGR_JQM_Pos (21U)
3064#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
3065#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */
3066#define ADC_CFGR_AWD1SGL_Pos (22U)
3067#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
3068#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */
3069#define ADC_CFGR_AWD1EN_Pos (23U)
3070#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
3071#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */
3072#define ADC_CFGR_JAWD1EN_Pos (24U)
3073#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
3074#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */
3075#define ADC_CFGR_JAUTO_Pos (25U)
3076#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
3077#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */
3078
3079#define ADC_CFGR_AWD1CH_Pos (26U)
3080#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
3081#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */
3082#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
3083#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
3084#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
3085#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
3086#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
3087
3088#define ADC_CFGR_JQDIS_Pos (31U)
3089#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
3090#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */
3091
3092/******************** Bit definition for ADC_CFGR2 register ********************/
3093#define ADC_CFGR2_ROVSE_Pos (0U)
3094#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
3095#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */
3096#define ADC_CFGR2_JOVSE_Pos (1U)
3097#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
3098#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */
3099
3100#define ADC_CFGR2_OVSS_Pos (5U)
3101#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
3102#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */
3103#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
3104#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
3105#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
3106#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
3107
3108#define ADC_CFGR2_TROVS_Pos (9U)
3109#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
3110#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */
3111#define ADC_CFGR2_ROVSM_Pos (10U)
3112#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
3113#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */
3114
3115#define ADC_CFGR2_RSHIFT1_Pos (11U)
3116#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */
3117#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */
3118#define ADC_CFGR2_RSHIFT2_Pos (12U)
3119#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */
3120#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */
3121#define ADC_CFGR2_RSHIFT3_Pos (13U)
3122#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */
3123#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */
3124#define ADC_CFGR2_RSHIFT4_Pos (14U)
3125#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */
3126#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */
3127
3128#define ADC_CFGR2_OVSR_Pos (16U)
3129#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */
3130#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */
3131#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */
3132#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */
3133#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */
3134#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */
3135#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */
3136#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */
3137#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */
3138#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */
3139#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */
3140#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */
3141
3142#define ADC_CFGR2_LSHIFT_Pos (28U)
3143#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */
3144#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */
3145#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */
3146#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */
3147#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */
3148#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */
3149
3150/******************** Bit definition for ADC_SMPR1 register ********************/
3151#define ADC_SMPR1_SMP0_Pos (0U)
3152#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
3153#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */
3154#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
3155#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
3156#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
3157
3158#define ADC_SMPR1_SMP1_Pos (3U)
3159#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
3160#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */
3161#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
3162#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
3163#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
3164
3165#define ADC_SMPR1_SMP2_Pos (6U)
3166#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
3167#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */
3168#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
3169#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
3170#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
3171
3172#define ADC_SMPR1_SMP3_Pos (9U)
3173#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
3174#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */
3175#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
3176#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
3177#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
3178
3179#define ADC_SMPR1_SMP4_Pos (12U)
3180#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
3181#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */
3182#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
3183#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
3184#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
3185
3186#define ADC_SMPR1_SMP5_Pos (15U)
3187#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
3188#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */
3189#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
3190#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
3191#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
3192
3193#define ADC_SMPR1_SMP6_Pos (18U)
3194#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
3195#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */
3196#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
3197#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
3198#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
3199
3200#define ADC_SMPR1_SMP7_Pos (21U)
3201#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
3202#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */
3203#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
3204#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
3205#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
3206
3207#define ADC_SMPR1_SMP8_Pos (24U)
3208#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
3209#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */
3210#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
3211#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
3212#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
3213
3214#define ADC_SMPR1_SMP9_Pos (27U)
3215#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
3216#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */
3217#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
3218#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
3219#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
3220
3221/******************** Bit definition for ADC_SMPR2 register ********************/
3222#define ADC_SMPR2_SMP10_Pos (0U)
3223#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
3224#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */
3225#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
3226#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
3227#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
3228
3229#define ADC_SMPR2_SMP11_Pos (3U)
3230#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
3231#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */
3232#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
3233#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
3234#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
3235
3236#define ADC_SMPR2_SMP12_Pos (6U)
3237#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
3238#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */
3239#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
3240#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
3241#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
3242
3243#define ADC_SMPR2_SMP13_Pos (9U)
3244#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
3245#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */
3246#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
3247#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
3248#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
3249
3250#define ADC_SMPR2_SMP14_Pos (12U)
3251#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
3252#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */
3253#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
3254#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
3255#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
3256
3257#define ADC_SMPR2_SMP15_Pos (15U)
3258#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
3259#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */
3260#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
3261#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
3262#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
3263
3264#define ADC_SMPR2_SMP16_Pos (18U)
3265#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
3266#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */
3267#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
3268#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
3269#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
3270
3271#define ADC_SMPR2_SMP17_Pos (21U)
3272#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
3273#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */
3274#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
3275#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
3276#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
3277
3278#define ADC_SMPR2_SMP18_Pos (24U)
3279#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
3280#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */
3281#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
3282#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
3283#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
3284
3285#define ADC_SMPR2_SMP19_Pos (27U)
3286#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
3287#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */
3288#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
3289#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
3290#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
3291
3292/******************** Bit definition for ADC_PCSEL register ********************/
3293#define ADC_PCSEL_PCSEL_Pos (0U)
3294#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */
3295#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */
3296#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */
3297#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */
3298#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */
3299#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */
3300#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */
3301#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */
3302#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */
3303#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */
3304#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */
3305#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */
3306#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */
3307#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */
3308#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */
3309#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */
3310#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */
3311#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */
3312#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */
3313#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */
3314#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */
3315#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */
3316
3317/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/
3318#define ADC_LTR_LT_Pos (0U)
3319#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */
3320#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */
3321
3322/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/
3323#define ADC_HTR_HT_Pos (0U)
3324#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */
3325#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */
3326
3327
3328/******************** Bit definition for ADC_SQR1 register ********************/
3329#define ADC_SQR1_L_Pos (0U)
3330#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
3331#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
3332#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
3333#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
3334#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
3335#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
3336
3337#define ADC_SQR1_SQ1_Pos (6U)
3338#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
3339#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */
3340#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
3341#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
3342#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
3343#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
3344#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
3345
3346#define ADC_SQR1_SQ2_Pos (12U)
3347#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
3348#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */
3349#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
3350#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
3351#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
3352#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
3353#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
3354
3355#define ADC_SQR1_SQ3_Pos (18U)
3356#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
3357#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */
3358#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
3359#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
3360#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
3361#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
3362#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
3363
3364#define ADC_SQR1_SQ4_Pos (24U)
3365#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
3366#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */
3367#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
3368#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
3369#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
3370#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
3371#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
3372
3373/******************** Bit definition for ADC_SQR2 register ********************/
3374#define ADC_SQR2_SQ5_Pos (0U)
3375#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
3376#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */
3377#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
3378#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
3379#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
3380#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
3381#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
3382
3383#define ADC_SQR2_SQ6_Pos (6U)
3384#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
3385#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */
3386#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
3387#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
3388#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
3389#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
3390#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
3391
3392#define ADC_SQR2_SQ7_Pos (12U)
3393#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
3394#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */
3395#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
3396#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
3397#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
3398#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
3399#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
3400
3401#define ADC_SQR2_SQ8_Pos (18U)
3402#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
3403#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */
3404#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
3405#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
3406#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
3407#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
3408#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
3409
3410#define ADC_SQR2_SQ9_Pos (24U)
3411#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
3412#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */
3413#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
3414#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
3415#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
3416#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
3417#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
3418
3419/******************** Bit definition for ADC_SQR3 register ********************/
3420#define ADC_SQR3_SQ10_Pos (0U)
3421#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
3422#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */
3423#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
3424#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
3425#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
3426#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
3427#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
3428
3429#define ADC_SQR3_SQ11_Pos (6U)
3430#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
3431#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */
3432#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
3433#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
3434#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
3435#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
3436#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
3437
3438#define ADC_SQR3_SQ12_Pos (12U)
3439#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
3440#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */
3441#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
3442#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
3443#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
3444#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
3445#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
3446
3447#define ADC_SQR3_SQ13_Pos (18U)
3448#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
3449#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */
3450#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
3451#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
3452#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
3453#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
3454#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
3455
3456#define ADC_SQR3_SQ14_Pos (24U)
3457#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
3458#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */
3459#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
3460#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
3461#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
3462#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
3463#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
3464
3465/******************** Bit definition for ADC_SQR4 register ********************/
3466#define ADC_SQR4_SQ15_Pos (0U)
3467#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
3468#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */
3469#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
3470#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
3471#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
3472#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
3473#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
3474
3475#define ADC_SQR4_SQ16_Pos (6U)
3476#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
3477#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */
3478#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
3479#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
3480#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
3481#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
3482#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
3483/******************** Bit definition for ADC_DR register ********************/
3484#define ADC_DR_RDATA_Pos (0U)
3485#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */
3486#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */
3487
3488/******************** Bit definition for ADC_JSQR register ********************/
3489#define ADC_JSQR_JL_Pos (0U)
3490#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
3491#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */
3492#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
3493#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
3494
3495#define ADC_JSQR_JEXTSEL_Pos (2U)
3496#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
3497#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */
3498#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
3499#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
3500#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
3501#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
3502#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
3503
3504#define ADC_JSQR_JEXTEN_Pos (7U)
3505#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
3506#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */
3507#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
3508#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
3509
3510#define ADC_JSQR_JSQ1_Pos (9U)
3511#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
3512#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */
3513#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
3514#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
3515#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
3516#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
3517#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
3518
3519#define ADC_JSQR_JSQ2_Pos (15U)
3520#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */
3521#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */
3522#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
3523#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
3524#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
3525#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
3526#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */
3527
3528#define ADC_JSQR_JSQ3_Pos (21U)
3529#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
3530#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */
3531#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
3532#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
3533#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
3534#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
3535#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
3536
3537#define ADC_JSQR_JSQ4_Pos (27U)
3538#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
3539#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */
3540#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
3541#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
3542#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
3543#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
3544#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
3545
3546/******************** Bit definition for ADC_OFR1 register ********************/
3547#define ADC_OFR1_OFFSET1_Pos (0U)
3548#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
3549#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
3550#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
3551#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
3552#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
3553#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
3554#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
3555#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
3556#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
3557#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
3558#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
3559#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
3560#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
3561#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
3562#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
3563#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
3564#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
3565#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
3566#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
3567#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
3568#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
3569#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
3570#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
3571#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
3572#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
3573#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
3574#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
3575#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
3576
3577#define ADC_OFR1_OFFSET1_CH_Pos (26U)
3578#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
3579#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */
3580#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
3581#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
3582#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
3583#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
3584#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
3585
3586#define ADC_OFR1_SSATE_Pos (31U)
3587#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */
3588#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */
3589
3590
3591/******************** Bit definition for ADC_OFR2 register ********************/
3592#define ADC_OFR2_OFFSET2_Pos (0U)
3593#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
3594#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
3595#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
3596#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
3597#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
3598#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
3599#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
3600#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
3601#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
3602#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
3603#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
3604#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
3605#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
3606#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
3607#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
3608#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
3609#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
3610#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
3611#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
3612#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
3613#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
3614#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
3615#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
3616#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
3617#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
3618#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
3619#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
3620#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
3621
3622#define ADC_OFR2_OFFSET2_CH_Pos (26U)
3623#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
3624#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */
3625#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
3626#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
3627#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
3628#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
3629#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
3630
3631#define ADC_OFR2_SSATE_Pos (31U)
3632#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */
3633#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */
3634
3635
3636/******************** Bit definition for ADC_OFR3 register ********************/
3637#define ADC_OFR3_OFFSET3_Pos (0U)
3638#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
3639#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
3640#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
3641#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
3642#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
3643#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
3644#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
3645#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
3646#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
3647#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
3648#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
3649#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
3650#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
3651#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
3652#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
3653#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
3654#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
3655#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
3656#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
3657#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
3658#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
3659#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
3660#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
3661#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
3662#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
3663#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
3664#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
3665#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
3666
3667#define ADC_OFR3_OFFSET3_CH_Pos (26U)
3668#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
3669#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */
3670#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
3671#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
3672#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
3673#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
3674#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
3675
3676#define ADC_OFR3_SSATE_Pos (31U)
3677#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */
3678#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */
3679
3680
3681/******************** Bit definition for ADC_OFR4 register ********************/
3682#define ADC_OFR4_OFFSET4_Pos (0U)
3683#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
3684#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
3685#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
3686#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
3687#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
3688#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
3689#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
3690#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
3691#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
3692#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
3693#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
3694#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
3695#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
3696#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
3697#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
3698#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
3699#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
3700#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
3701#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
3702#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
3703#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
3704#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
3705#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
3706#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
3707#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
3708#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
3709#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
3710#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
3711
3712#define ADC_OFR4_OFFSET4_CH_Pos (26U)
3713#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
3714#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */
3715#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
3716#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
3717#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
3718#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
3719#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
3720
3721#define ADC_OFR4_SSATE_Pos (31U)
3722#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */
3723#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */
3724
3725
3726/******************** Bit definition for ADC_JDR1 register ********************/
3727#define ADC_JDR1_JDATA_Pos (0U)
3728#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */
3729#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */
3730#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */