aboutsummaryrefslogtreecommitdiff
path: root/lib/chibios/os/common/ext/ST/STM32H7xx/stm32h7a3xxq.h
diff options
context:
space:
mode:
Diffstat (limited to 'lib/chibios/os/common/ext/ST/STM32H7xx/stm32h7a3xxq.h')
-rw-r--r--lib/chibios/os/common/ext/ST/STM32H7xx/stm32h7a3xxq.h22447
1 files changed, 22447 insertions, 0 deletions
diff --git a/lib/chibios/os/common/ext/ST/STM32H7xx/stm32h7a3xxq.h b/lib/chibios/os/common/ext/ST/STM32H7xx/stm32h7a3xxq.h
new file mode 100644
index 000000000..1b428ccda
--- /dev/null
+++ b/lib/chibios/os/common/ext/ST/STM32H7xx/stm32h7a3xxq.h
@@ -0,0 +1,22447 @@
1/**
2 ******************************************************************************
3 * @file stm32h7a3xxq.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32H7A3xxQ Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
16 * All rights reserved.</center></h2>
17 *
18 * This software component is licensed by ST under BSD 3-Clause license,
19 * the "License"; You may not use this file except in compliance with the
20 * License. You may obtain a copy of the License at:
21 * opensource.org/licenses/BSD-3-Clause
22 *
23 ******************************************************************************
24 */
25
26/** @addtogroup CMSIS_Device
27 * @{
28 */
29
30/** @addtogroup stm32h7a3xxq
31 * @{
32 */
33
34#ifndef STM32H7A3xxQ_H
35#define STM32H7A3xxQ_H
36
37#ifdef __cplusplus
38 extern "C" {
39#endif /* __cplusplus */
40
41/** @addtogroup Peripheral_interrupt_number_definition
42 * @{
43 */
44
45/**
46 * @brief STM32H7XX Interrupt Number Definition, according to the selected device
47 * in @ref Library_configuration_section
48 */
49typedef enum
50{
51/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
52 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
53 HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
54 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
55 BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
56 UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
57 SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
58 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */
59 PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
60 SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
61/****** STM32 specific Interrupt Numbers **********************************************************************/
62 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
63 PVD_PVM_IRQn = 1, /*!< PVD/PVM through EXTI Line detection Interrupt */
64 RTC_TAMP_STAMP_CSS_LSE_IRQn = 2, /*!< Tamper, TimeStamp, CSS and LSE interrupts through the EXTI line */
65 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
66 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
67 RCC_IRQn = 5, /*!< RCC global Interrupt */
68 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
69 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
70 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
71 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
72 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
73 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
74 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
75 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
76 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
77 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
78 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
79 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
80 ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */
81 FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */
82 FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */
83 FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */
84 FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */
85 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
86 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
87 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
88 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
89 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
90 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
91 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
92 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
93 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
94 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
95 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
96 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
97 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
98 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
99 USART1_IRQn = 37, /*!< USART1 global Interrupt */
100 USART2_IRQn = 38, /*!< USART2 global Interrupt */
101 USART3_IRQn = 39, /*!< USART3 global Interrupt */
102 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
103 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
104 DFSDM2_IRQn = 42, /*!< DFSDM2 global Interrupt */
105 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
106 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
107 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
108 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
109 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
110 FMC_IRQn = 48, /*!< FMC global Interrupt */
111 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
112 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
113 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
114 UART4_IRQn = 52, /*!< UART4 global Interrupt */
115 UART5_IRQn = 53, /*!< UART5 global Interrupt */
116 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
117 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
118 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
119 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
120 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
121 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
122 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
123 FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */
124 DFSDM1_FLT4_IRQn = 64, /*!< DFSDM Filter4 Interrupt */
125 DFSDM1_FLT5_IRQn = 65, /*!< DFSDM Filter5 Interrupt */
126 DFSDM1_FLT6_IRQn = 66, /*!< DFSDM Filter6 Interrupt */
127 DFSDM1_FLT7_IRQn = 67, /*!< DFSDM Filter7 Interrupt */
128 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
129 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
130 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
131 USART6_IRQn = 71, /*!< USART6 global interrupt */
132 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
133 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
134 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
135 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
136 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
137 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
138 DCMI_PSSI_IRQn = 78, /*!< DCMI and PSSI global interrupt */
139 RNG_IRQn = 80, /*!< RNG global interrupt */
140 FPU_IRQn = 81, /*!< FPU global interrupt */
141 UART7_IRQn = 82, /*!< UART7 global interrupt */
142 UART8_IRQn = 83, /*!< UART8 global interrupt */
143 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
144 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
145 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
146 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
147 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
148 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
149 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
150 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
151 OCTOSPI1_IRQn = 92, /*!< OCTOSPI1 global interrupt */
152 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
153 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
154 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
155 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
156 SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
157 DMAMUX1_OVR_IRQn = 102, /*!<DMAMUX1 Overrun interrupt */
158 DFSDM1_FLT0_IRQn = 110, /*!<DFSDM Filter1 Interrupt */
159 DFSDM1_FLT1_IRQn = 111, /*!<DFSDM Filter2 Interrupt */
160 DFSDM1_FLT2_IRQn = 112, /*!<DFSDM Filter3 Interrupt */
161 DFSDM1_FLT3_IRQn = 113, /*!<DFSDM Filter4 Interrupt */
162 SWPMI1_IRQn = 115, /*!< Serial Wire Interface 1 global interrupt */
163 TIM15_IRQn = 116, /*!< TIM15 global Interrupt */
164 TIM16_IRQn = 117, /*!< TIM16 global Interrupt */
165 TIM17_IRQn = 118, /*!< TIM17 global Interrupt */
166 MDIOS_WKUP_IRQn = 119, /*!< MDIOS Wakeup Interrupt */
167 MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */
168 JPEG_IRQn = 121, /*!< JPEG global Interrupt */
169 MDMA_IRQn = 122, /*!< MDMA global Interrupt */
170 SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */
171 HSEM1_IRQn = 125, /*!< HSEM1 global Interrupt */
172 DAC2_IRQn = 127, /*!< DAC2 global Interrupt */
173 DMAMUX2_OVR_IRQn = 128, /*!<DMAMUX2 Overrun interrupt */
174 BDMA2_Channel0_IRQn = 129, /*!< BDMA2 Channel 0 global Interrupt */
175 BDMA2_Channel1_IRQn = 130, /*!< BDMA2 Channel 1 global Interrupt */
176 BDMA2_Channel2_IRQn = 131, /*!< BDMA2 Channel 2 global Interrupt */
177 BDMA2_Channel3_IRQn = 132, /*!< BDMA2 Channel 3 global Interrupt */
178 BDMA2_Channel4_IRQn = 133, /*!< BDMA2 Channel 4 global Interrupt */
179 BDMA2_Channel5_IRQn = 134, /*!< BDMA2 Channel 5 global Interrupt */
180 BDMA2_Channel6_IRQn = 135, /*!< BDMA2 Channel 6 global Interrupt */
181 BDMA2_Channel7_IRQn = 136, /*!< BDMA2 Channel 7 global Interrupt */
182 COMP_IRQn = 137 , /*!< COMP global Interrupt */
183 LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */
184 LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */
185 UART9_IRQn = 140, /*!< UART9 global interrupt */
186 USART10_IRQn = 141, /*!< USART10 global interrupt */
187 LPUART1_IRQn = 142, /*!< LP UART1 interrupt */
188 WWDG_RST_IRQn = 143, /*!<Window Watchdog Event interrupt */
189 CRS_IRQn = 144, /*!< Clock Recovery Global Interrupt */
190 ECC_IRQn = 145, /*!< ECC diagnostic Global Interrupt */
191 DTS_IRQn = 147, /*!< Digital Temperature Sensor Global Interrupt */
192 WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */
193 OCTOSPI2_IRQn = 150, /*!< OctoSPI2 global interrupt */
194 GFXMMU_IRQn = 153, /*!< GFXMMU global interrupt */
195 BDMA1_IRQn = 154, /*!< BDMA1 for DFSM global interrupt */
196} IRQn_Type;
197
198/**
199 * @}
200 */
201
202/** @addtogroup Configuration_section_for_CMSIS
203 * @{
204 */
205
206#define SMPS /*!< Switched mode power supply feature */
207
208
209
210/**
211 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
212 */
213#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
214#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
215#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
216#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
217#define __FPU_PRESENT 1 /*!< FPU present */
218#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
219#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
220#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
221
222/**
223 * @}
224 */
225
226
227
228
229#include "system_stm32h7xx.h"
230#include <stdint.h>
231
232/** @addtogroup Peripheral_registers_structures
233 * @{
234 */
235
236/**
237 * @brief Analog to Digital Converter
238 */
239
240typedef struct
241{
242 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
243 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
244 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
245 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
246 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
247 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
248 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
249 __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */
250 __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
251 __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
252 uint32_t RESERVED1; /*!< Reserved, 0x028 */
253 uint32_t RESERVED2; /*!< Reserved, 0x02C */
254 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
255 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
256 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
257 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
258 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
259 uint32_t RESERVED3; /*!< Reserved, 0x044 */
260 uint32_t RESERVED4; /*!< Reserved, 0x048 */
261 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
262 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
263 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
264 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
265 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
266 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
267 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
268 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
269 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
270 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
271 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
272 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
273 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
274 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
275 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
276 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
277 __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */
278 __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */
279 __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */
280 __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */
281 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */
282 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */
283 __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */
284} ADC_TypeDef;
285
286
287typedef struct
288{
289__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
290uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
291__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
292__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
293__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
294
295} ADC_Common_TypeDef;
296
297
298/**
299 * @brief VREFBUF
300 */
301
302typedef struct
303{
304 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
305 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
306} VREFBUF_TypeDef;
307
308
309/**
310 * @brief FD Controller Area Network
311 */
312
313typedef struct
314{
315 __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
316 __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
317 __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */
318 __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
319 __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
320 __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
321 __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
322 __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
323 __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
324 __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
325 __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
326 __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
327 __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
328 __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
329 __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
330 __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
331 __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */
332 __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
333 __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
334 __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
335 __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
336 __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
337 __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
338 __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */
339 __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */
340 __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */
341 __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */
342 __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */
343 __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */
344 __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */
345 __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */
346 __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */
347 __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */
348 __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */
349 __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */
350 __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */
351 __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */
352 __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */
353 __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
354 __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
355 __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */
356 __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */
357 __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */
358 __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */
359 __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */
360 __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */
361 __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */
362 __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
363 __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */
364 __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */
365 __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */
366 __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */
367 __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */
368} FDCAN_GlobalTypeDef;
369
370/**
371 * @brief TTFD Controller Area Network
372 */
373
374typedef struct
375{
376 __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */
377 __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */
378 __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */
379 __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */
380 __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */
381 __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */
382 __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */
383 __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */
384 __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */
385 __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */
386 __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */
387 __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */
388 __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */
389 __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */
390 __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */
391 __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */
392 __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */
393 __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */
394 __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */
395} TTCAN_TypeDef;
396
397/**
398 * @brief FD Controller Area Network
399 */
400
401typedef struct
402{
403 __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
404 __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */
405 __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */
406 __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */
407 __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */
408 __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */
409} FDCAN_ClockCalibrationUnit_TypeDef;
410
411
412/**
413 * @brief Consumer Electronics Control
414 */
415
416typedef struct
417{
418 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
419 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
420 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
421 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
422 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
423 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
424}CEC_TypeDef;
425
426/**
427 * @brief CRC calculation unit
428 */
429
430typedef struct
431{
432 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
433 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
434 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
435 uint32_t RESERVED2; /*!< Reserved, 0x0C */
436 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
437 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
438} CRC_TypeDef;
439
440
441/**
442 * @brief Clock Recovery System
443 */
444typedef struct
445{
446__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
447__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
448__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
449__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
450} CRS_TypeDef;
451
452
453/**
454 * @brief Digital to Analog Converter
455 */
456
457typedef struct
458{
459 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
460 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
461 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
462 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
463 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
464 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
465 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
466 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
467 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
468 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
469 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
470 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
471 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
472 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
473 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
474 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
475 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
476 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
477 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
478 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
479} DAC_TypeDef;
480
481/**
482 * @brief DFSDM module registers
483 */
484typedef struct
485{
486 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
487 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
488 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
489 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
490 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
491 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
492 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
493 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
494 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
495 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
496 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
497 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
498 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
499 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
500 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
501} DFSDM_Filter_TypeDef;
502
503/**
504 * @brief DFSDM channel configuration registers
505 */
506typedef struct
507{
508 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
509 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
510 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
511 short circuit detector register, Address offset: 0x08 */
512 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
513 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
514 __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */
515} DFSDM_Channel_TypeDef;
516
517/**
518 * @brief Debug MCU
519 */
520typedef struct
521{
522 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
523 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
524 uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */
525 __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */
526 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x38 */
527 __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */
528 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x40 */
529 __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */
530 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x48 */
531 __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */
532 uint32_t RESERVED8; /*!< Reserved, Address offset: 0x50 */
533 __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */
534}DBGMCU_TypeDef;
535/**
536 * @brief DCMI
537 */
538
539typedef struct
540{
541 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
542 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
543 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
544 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
545 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
546 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
547 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
548 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
549 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
550 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
551 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
552} DCMI_TypeDef;
553
554/**
555 * @brief PSSI
556 */
557
558typedef struct
559{
560 __IO uint32_t CR; /*!< PSSI control register 1, Address offset: 0x000 */
561 __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */
562 __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */
563 __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */
564 __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */
565 __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */
566 __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */
567 __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */
568 __IO uint32_t RESERVED2[241]; /*!< Reserved, 0x02C - 0x3EC */
569 __IO uint32_t HWCFGR; /*!< PSSI IP HW configuration register, Address offset: 0x3F0 */
570 __IO uint32_t VERR; /*!< PSSI IP version register, Address offset: 0x3F4 */
571 __IO uint32_t IPIDR; /*!< PSSI IP ID register, Address offset: 0x3F8 */
572 __IO uint32_t SIDR; /*!< PSSI SIZE ID register, Address offset: 0x3FC */
573} PSSI_TypeDef;
574
575/**
576 * @brief DMA Controller
577 */
578
579typedef struct
580{
581 __IO uint32_t CR; /*!< DMA stream x configuration register */
582 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
583 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
584 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
585 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
586 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
587} DMA_Stream_TypeDef;
588
589typedef struct
590{
591 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
592 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
593 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
594 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
595} DMA_TypeDef;
596
597typedef struct
598{
599 __IO uint32_t CCR; /*!< DMA channel x configuration register */
600 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
601 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
602 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */
603 __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */
604} BDMA_Channel_TypeDef;
605
606typedef struct
607{
608 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
609 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
610} BDMA_TypeDef;
611
612typedef struct
613{
614 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */
615}DMAMUX_Channel_TypeDef;
616
617typedef struct
618{
619 __IO uint32_t CSR; /*!< DMA Channel Status Register */
620 __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */
621}DMAMUX_ChannelStatus_TypeDef;
622
623typedef struct
624{
625 __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */
626}DMAMUX_RequestGen_TypeDef;
627
628typedef struct
629{
630 __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */
631 __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */
632}DMAMUX_RequestGenStatus_TypeDef;
633
634/**
635 * @brief MDMA Controller
636 */
637typedef struct
638{
639 __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */
640}MDMA_TypeDef;
641
642typedef struct
643{
644 __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */
645 __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */
646 __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */
647 __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */
648 __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */
649 __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */
650 __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */
651 __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */
652 __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
653 __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
654 __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
655 uint32_t RESERVED0; /*!< Reserved, 0x68 */
656 __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
657 __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
658}MDMA_Channel_TypeDef;
659
660/**
661 * @brief DMA2D Controller
662 */
663
664typedef struct
665{
666 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
667 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
668 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
669 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
670 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
671 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
672 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
673 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
674 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
675 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
676 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
677 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
678 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
679 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
680 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
681 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
682 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
683 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
684 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
685 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
686 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
687 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
688 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
689} DMA2D_TypeDef;
690
691
692/**
693 * @brief External Interrupt/Event Controller
694 */
695
696typedef struct
697{
698__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */
699__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */
700__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */
701__IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */
702__IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */
703__IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */
704uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */
705__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */
706__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */
707__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */
708__IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */
709__IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */
710__IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */
711uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */
712__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */
713__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */
714__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */
715__IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */
716__IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */
717__IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */
718uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */
719__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */
720__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */
721__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */
722uint32_t RESERVED4; /*!< Reserved, 0x8C */
723__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */
724__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */
725__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */
726uint32_t RESERVED5; /*!< Reserved, 0x9C */
727__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */
728__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */
729__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
730}EXTI_TypeDef;
731
732typedef struct
733{
734__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
735__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */
736__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */
737uint32_t RESERVED1; /*!< Reserved, 0x0C */
738__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */
739__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */
740__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */
741uint32_t RESERVED2; /*!< Reserved, 0x1C */
742__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
743__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */
744__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */
745}EXTI_Core_TypeDef;
746
747
748/**
749 * @brief FLASH Registers
750 */
751
752typedef struct
753{
754 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
755 __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */
756 __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */
757 __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */
758 __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */
759 __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */
760 __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */
761 __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */
762 __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */
763 __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */
764 __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */
765 __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */
766 __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */
767 __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */
768 __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */
769 __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */
770 __IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */
771 __IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */
772 uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */
773 __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */
774 __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */
775 __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */
776 __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */
777 __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */
778 uint32_t RESERVED; /*!< Reserved, 0x64 */
779 __IO uint32_t OTPBL_CUR; /*!< Flash Current OTP Block Lock Register, Address offset: 0x68 */
780 __IO uint32_t OTPBL_PRG; /*!< Flash OTP Block Lock to Program Register, Address offset: 0x6C */
781 uint32_t RESERVED1[37]; /*!< Reserved, 0x70 to 0x100 */
782 __IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */
783 uint32_t RESERVED2; /*!< Reserved, 0x108 */
784 __IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */
785 __IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */
786 __IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */
787 uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */
788 __IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */
789 __IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */
790 __IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */
791 __IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */
792 __IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */
793 __IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */
794 uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */
795 __IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */
796 __IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */
797 __IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */
798 __IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */
799 __IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */
800} FLASH_TypeDef;
801
802/**
803 * @brief Flexible Memory Controller
804 */
805
806typedef struct
807{
808 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
809} FMC_Bank1_TypeDef;
810
811/**
812 * @brief Flexible Memory Controller Bank1E
813 */
814
815typedef struct
816{
817 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
818} FMC_Bank1E_TypeDef;
819
820/**
821 * @brief Flexible Memory Controller Bank2
822 */
823
824typedef struct
825{
826 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
827 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
828 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
829 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
830 uint32_t RESERVED0; /*!< Reserved, 0x70 */
831 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
832} FMC_Bank2_TypeDef;
833
834/**
835 * @brief Flexible Memory Controller Bank3
836 */
837
838typedef struct
839{
840 __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */
841 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
842 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
843 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
844 uint32_t RESERVED; /*!< Reserved, 0x90 */
845 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
846} FMC_Bank3_TypeDef;
847
848/**
849 * @brief Flexible Memory Controller Bank5 and 6
850 */
851
852
853typedef struct
854{
855 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
856 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
857 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
858 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
859 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
860} FMC_Bank5_6_TypeDef;
861
862/**
863 * @brief GFXMMU registers
864 */
865
866typedef struct
867{
868 __IO uint32_t CR; /*!< GFXMMU configuration register, Address offset: 0x00 */
869 __IO uint32_t SR; /*!< GFXMMU status register, Address offset: 0x04 */
870 __IO uint32_t FCR; /*!< GFXMMU flag clear register, Address offset: 0x08 */
871 __IO uint32_t CCR; /*!< GFXMMU Cache Control Register, Address offset: 0x0C */
872 __IO uint32_t DVR; /*!< GFXMMU default value register, Address offset: 0x10 */
873 uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x14 to 0x1C */
874 __IO uint32_t B0CR; /*!< GFXMMU buffer 0 configuration register, Address offset: 0x20 */
875 __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */
876 __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */
877 __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */
878 uint32_t RESERVED2[1008]; /*!< Reserved2, Address offset: 0x30 to 0xFEC */
879 __IO uint32_t HWCFGR; /*!< GFXMMU hardware configuration register, Address offset: 0xFF0 */
880 __IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */
881 __IO uint32_t IPIDR; /*!< GFXMMU identification register, Address offset: 0xFF8 */
882 __IO uint32_t SIDR; /*!< GFXMMU size identification register, Address offset: 0xFFC */
883 __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC
884 For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */
885} GFXMMU_TypeDef;
886/**
887 * @brief General Purpose I/O
888 */
889
890typedef struct
891{
892 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
893 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
894 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
895 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
896 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
897 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
898 __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */
899 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
900 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
901} GPIO_TypeDef;
902
903/**
904 * @brief Operational Amplifier (OPAMP)
905 */
906
907typedef struct
908{
909 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
910 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
911 __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
912} OPAMP_TypeDef;
913
914/**
915 * @brief System configuration controller
916 */
917
918typedef struct
919{
920 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */
921 __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
922 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
923 __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */
924 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
925 __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */
926 __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */
927 __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */
928
929} SYSCFG_TypeDef;
930
931/**
932 * @brief Inter-integrated Circuit Interface
933 */
934
935typedef struct
936{
937 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
938 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
939 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
940 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
941 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
942 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
943 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
944 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
945 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
946 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
947 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
948} I2C_TypeDef;
949
950/**
951 * @brief Independent WATCHDOG
952 */
953
954typedef struct
955{
956 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
957 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
958 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
959 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
960 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
961} IWDG_TypeDef;
962
963
964/**
965 * @brief JPEG Codec
966 */
967typedef struct
968{
969 __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
970 __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
971 __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
972 __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
973 __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
974 __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
975 __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
976 __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
977 uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
978 __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
979 __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
980 __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
981 uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
982 __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
983 __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
984 uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
985 __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
986 __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
987 __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
988 __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
989 __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
990 __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
991 __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
992 __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
993 uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
994 __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
995 __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
996 __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
997 __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
998
999} JPEG_TypeDef;
1000
1001/**
1002 * @brief LCD-TFT Display Controller
1003 */
1004
1005typedef struct
1006{
1007 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
1008 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
1009 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
1010 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
1011 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
1012 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
1013 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
1014 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
1015 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
1016 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
1017 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
1018 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
1019 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
1020 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
1021 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
1022 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
1023 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
1024} LTDC_TypeDef;
1025
1026/**
1027 * @brief LCD-TFT Display layer x Controller
1028 */
1029
1030typedef struct
1031{
1032 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
1033 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
1034 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
1035 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
1036 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
1037 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
1038 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
1039 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
1040 uint32_t RESERVED0[2]; /*!< Reserved */
1041 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
1042 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
1043 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
1044 uint32_t RESERVED1[3]; /*!< Reserved */
1045 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
1046
1047} LTDC_Layer_TypeDef;
1048
1049/**
1050 * @brief Power Control
1051 */
1052
1053typedef struct
1054{
1055 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
1056 __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */
1057 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
1058 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */
1059 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */
1060 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */
1061 __IO uint32_t SRDCR; /*!< PWR SRD domain control register, Address offset: 0x18 */
1062 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
1063 __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */
1064 __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */
1065 __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
1066} PWR_TypeDef;
1067
1068/**
1069 * @brief Reset and Clock Control
1070 */
1071
1072typedef struct
1073{
1074 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
1075 __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */
1076 __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */
1077 __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */
1078 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */
1079 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
1080 __IO uint32_t CDCFGR1; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */
1081 __IO uint32_t CDCFGR2; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */
1082 __IO uint32_t SRDCFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */
1083 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
1084 __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */
1085 __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */
1086 __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */
1087 __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */
1088 __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */
1089 __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */
1090 __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */
1091 __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */
1092 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
1093 __IO uint32_t CDCCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */
1094 __IO uint32_t CDCCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */
1095 __IO uint32_t CDCCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */
1096 __IO uint32_t SRDCCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */
1097 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */
1098 __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */
1099 __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */
1100 __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */
1101 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */
1102 __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */
1103 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
1104 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */
1105 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */
1106 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */
1107 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */
1108 __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */
1109 __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */
1110 __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */
1111 __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */
1112 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */
1113 __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */
1114 uint32_t RESERVED7; /*!< Reserved, Address offset: 0xA0 */
1115 uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */
1116 __IO uint32_t SRDAMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */
1117 uint32_t RESERVED9; /*!< Reserved, 0xAC-0xAF Address offset: 0xAC */
1118 __IO uint32_t CKGAENR; /*!< AXI Clocks Gating Enable Register, Address offset: 0xB0 */
1119 uint32_t RESERVED10[31]; /*!< Reserved, 0xAC-0xAF Address offset: 0xAC */
1120 __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */
1121 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */
1122 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */
1123 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */
1124 __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */
1125 __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */
1126 __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */
1127 __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */
1128 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */
1129 __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */
1130 uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */
1131 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */
1132 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */
1133 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */
1134 __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */
1135 __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */
1136 __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */
1137 __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */
1138 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */
1139 __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */
1140 uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */
1141
1142} RCC_TypeDef;
1143
1144
1145/**
1146 * @brief Real-Time Clock
1147 */
1148typedef struct
1149{
1150 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
1151 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
1152 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
1153 __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
1154 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
1155 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
1156 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
1157 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x1C */
1158 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */
1159 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
1160 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
1161 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
1162 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
1163 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
1164 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
1165 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x3C */
1166 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
1167 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
1168 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
1169 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
1170 __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
1171 __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */
1172 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x58 */
1173 __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */
1174 __IO uint32_t CFGR; /*!< RTC configuration register, Address offset: 0x60 */
1175} RTC_TypeDef;
1176
1177/**
1178 * @brief Tamper and backup registers
1179 */
1180typedef struct
1181{
1182 __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */
1183 __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */
1184 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x08 */
1185 __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */
1186 __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */
1187 __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */
1188 __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */
1189 uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x1C -- 0x28 */
1190 __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */
1191 __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */
1192 __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */
1193 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x38 */
1194 __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */
1195 __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */
1196 uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x44 -- 0x4C */
1197 __IO uint32_t CFGR; /*!< TAMP configuration register, Address offset: 0x50 */
1198 uint32_t RESERVED4[43]; /*!< Reserved, Address offset: 0x54 -- 0xFC */
1199 __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
1200 __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
1201 __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
1202 __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
1203 __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
1204 __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */
1205 __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */
1206 __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */
1207 __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */
1208 __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */
1209 __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */
1210 __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */
1211 __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */
1212 __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */
1213 __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */
1214 __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */
1215 __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */
1216 __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */
1217 __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */
1218 __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */
1219 __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */
1220 __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */
1221 __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */
1222 __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */
1223 __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */
1224 __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */
1225 __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */
1226 __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */
1227 __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */
1228 __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */
1229 __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */
1230 __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */
1231} TAMP_TypeDef;
1232
1233/**
1234 * @brief Serial Audio Interface
1235 */
1236
1237typedef struct
1238{
1239 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
1240 uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
1241 __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
1242 __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
1243} SAI_TypeDef;
1244
1245typedef struct
1246{
1247 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
1248 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
1249 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
1250 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
1251 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
1252 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
1253 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
1254 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
1255} SAI_Block_TypeDef;
1256
1257/**
1258 * @brief SPDIF-RX Interface
1259 */
1260
1261typedef struct
1262{
1263 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
1264 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
1265 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
1266 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
1267 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
1268 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
1269 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
1270 uint32_t RESERVED2; /*!< Reserved, 0x1A */
1271} SPDIFRX_TypeDef;
1272
1273
1274/**
1275 * @brief Secure digital input/output Interface
1276 */
1277
1278typedef struct
1279{
1280 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
1281 __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
1282 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
1283 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
1284 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
1285 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
1286 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
1287 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
1288 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
1289 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
1290 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
1291 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
1292 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
1293 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
1294 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
1295 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
1296 __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
1297 uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
1298 __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
1299 __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
1300 __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
1301 __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
1302 uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
1303 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
1304 uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */
1305 __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */
1306} SDMMC_TypeDef;
1307
1308
1309/**
1310 * @brief Delay Block DLYB
1311 */
1312
1313typedef struct
1314{
1315 __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */
1316 __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */
1317} DLYB_TypeDef;
1318
1319/**
1320 * @brief HW Semaphore HSEM
1321 */
1322
1323typedef struct
1324{
1325 __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */
1326 __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */
1327 __IO uint32_t C1IER; /*!< HSEM Interrupt enable register , Address offset: 100h */
1328 __IO uint32_t C1ICR; /*!< HSEM Interrupt clear register , Address offset: 104h */
1329 __IO uint32_t C1ISR; /*!< HSEM Interrupt Status register , Address offset: 108h */
1330 __IO uint32_t C1MISR; /*!< HSEM Interrupt Masked Status register , Address offset: 10Ch */
1331 uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch */
1332 __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */
1333 __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */
1334
1335} HSEM_TypeDef;
1336
1337typedef struct
1338{
1339 __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */
1340 __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */
1341 __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */
1342 __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */
1343} HSEM_Common_TypeDef;
1344
1345/**
1346 * @brief Serial Peripheral Interface
1347 */
1348
1349typedef struct
1350{
1351 __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */
1352 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
1353 __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */
1354 __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */
1355 __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */
1356 __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */
1357 __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */
1358 uint32_t RESERVED0; /*!< Reserved, 0x1C */
1359 __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */
1360 uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */
1361 __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */
1362 uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
1363 __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */
1364 __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */
1365 __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */
1366 __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */
1367 __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */
1368
1369} SPI_TypeDef;
1370
1371/**
1372 * @brief DTS
1373 */
1374typedef struct
1375{
1376 __IO uint32_t CFGR1; /*!< DTS configuration register, Address offset: 0x00 */
1377 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */
1378 __IO uint32_t T0VALR1; /*!< DTS T0 Value register, Address offset: 0x08 */
1379 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */
1380 __IO uint32_t RAMPVALR; /*!< DTS Ramp value register, Address offset: 0x10 */
1381 __IO uint32_t ITR1; /*!< DTS Interrupt threshold register, Address offset: 0x14 */
1382 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
1383 __IO uint32_t DR; /*!< DTS data register, Address offset: 0x1C */
1384 __IO uint32_t SR; /*!< DTS status register Address offset: 0x20 */
1385 __IO uint32_t ITENR; /*!< DTS Interrupt enable register, Address offset: 0x24 */
1386 __IO uint32_t ICIFR; /*!< DTS Clear Interrupt flag register, Address offset: 0x28 */
1387 __IO uint32_t OR; /*!< DTS option register 1, Address offset: 0x2C */
1388}
1389DTS_TypeDef;
1390
1391/**
1392 * @brief TIM
1393 */
1394
1395typedef struct
1396{
1397 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
1398 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
1399 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
1400 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
1401 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
1402 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
1403 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
1404 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
1405 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
1406 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
1407 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
1408 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
1409 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
1410 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
1411 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
1412 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
1413 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
1414 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
1415 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
1416 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
1417 uint32_t RESERVED1; /*!< Reserved, 0x50 */
1418 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
1419 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
1420 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
1421 __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
1422 __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
1423 __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
1424} TIM_TypeDef;
1425
1426/**
1427 * @brief LPTIMIMER
1428 */
1429typedef struct
1430{
1431 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
1432 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
1433 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
1434 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
1435 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
1436 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
1437 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
1438 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
1439 uint32_t RESERVED1; /*!< Reserved, 0x20 */
1440 __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */
1441} LPTIM_TypeDef;
1442
1443/**
1444 * @brief Comparator
1445 */
1446typedef struct
1447{
1448 __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */
1449 __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */
1450 __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */
1451} COMPOPT_TypeDef;
1452
1453typedef struct
1454{
1455 __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */
1456} COMP_TypeDef;
1457
1458typedef struct
1459{
1460 __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
1461} COMP_Common_TypeDef;
1462/**
1463 * @brief Universal Synchronous Asynchronous Receiver Transmitter
1464 */
1465
1466typedef struct
1467{
1468 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
1469 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
1470 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
1471 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
1472 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
1473 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
1474 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
1475 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
1476 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
1477 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
1478 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
1479 __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */
1480} USART_TypeDef;
1481
1482/**
1483 * @brief Single Wire Protocol Master Interface SPWMI
1484 */
1485typedef struct
1486{
1487 __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
1488 __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
1489 uint32_t RESERVED1; /*!< Reserved, 0x08 */
1490 __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
1491 __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
1492 __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
1493 __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
1494 __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
1495 __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
1496 __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
1497} SWPMI_TypeDef;
1498
1499/**
1500 * @brief Window WATCHDOG
1501 */
1502
1503typedef struct
1504{
1505 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
1506 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
1507 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
1508} WWDG_TypeDef;
1509
1510
1511/**
1512 * @brief RAM_ECC_Specific_Registers
1513 */
1514typedef struct
1515{
1516 __IO uint32_t CR; /*!< RAMECC monitor configuration register */
1517 __IO uint32_t SR; /*!< RAMECC monitor status register */
1518 __IO uint32_t FAR; /*!< RAMECC monitor failing address register */
1519 __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */
1520 __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */
1521 __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */
1522} RAMECC_MonitorTypeDef;
1523
1524typedef struct
1525{
1526 __IO uint32_t IER; /*!< RAMECC interrupt enable register */
1527} RAMECC_TypeDef;
1528/**
1529 * @}
1530 */
1531
1532
1533
1534/**
1535 * @brief RNG
1536 */
1537
1538typedef struct
1539{
1540 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
1541 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
1542 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
1543 uint32_t RESERVED;
1544 __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
1545} RNG_TypeDef;
1546
1547/**
1548 * @brief MDIOS
1549 */
1550
1551typedef struct
1552{
1553 __IO uint32_t CR;
1554 __IO uint32_t WRFR;
1555 __IO uint32_t CWRFR;
1556 __IO uint32_t RDFR;
1557 __IO uint32_t CRDFR;
1558 __IO uint32_t SR;
1559 __IO uint32_t CLRFR;
1560 uint32_t RESERVED[57];
1561 __IO uint32_t DINR0;
1562 __IO uint32_t DINR1;
1563 __IO uint32_t DINR2;
1564 __IO uint32_t DINR3;
1565 __IO uint32_t DINR4;
1566 __IO uint32_t DINR5;
1567 __IO uint32_t DINR6;
1568 __IO uint32_t DINR7;
1569 __IO uint32_t DINR8;
1570 __IO uint32_t DINR9;
1571 __IO uint32_t DINR10;
1572 __IO uint32_t DINR11;
1573 __IO uint32_t DINR12;
1574 __IO uint32_t DINR13;
1575 __IO uint32_t DINR14;
1576 __IO uint32_t DINR15;
1577 __IO uint32_t DINR16;
1578 __IO uint32_t DINR17;
1579 __IO uint32_t DINR18;
1580 __IO uint32_t DINR19;
1581 __IO uint32_t DINR20;
1582 __IO uint32_t DINR21;
1583 __IO uint32_t DINR22;
1584 __IO uint32_t DINR23;
1585 __IO uint32_t DINR24;
1586 __IO uint32_t DINR25;
1587 __IO uint32_t DINR26;
1588 __IO uint32_t DINR27;
1589 __IO uint32_t DINR28;
1590 __IO uint32_t DINR29;
1591 __IO uint32_t DINR30;
1592 __IO uint32_t DINR31;
1593 __IO uint32_t DOUTR0;
1594 __IO uint32_t DOUTR1;
1595 __IO uint32_t DOUTR2;
1596 __IO uint32_t DOUTR3;
1597 __IO uint32_t DOUTR4;
1598 __IO uint32_t DOUTR5;
1599 __IO uint32_t DOUTR6;
1600 __IO uint32_t DOUTR7;
1601 __IO uint32_t DOUTR8;
1602 __IO uint32_t DOUTR9;
1603 __IO uint32_t DOUTR10;
1604 __IO uint32_t DOUTR11;
1605 __IO uint32_t DOUTR12;
1606 __IO uint32_t DOUTR13;
1607 __IO uint32_t DOUTR14;
1608 __IO uint32_t DOUTR15;
1609 __IO uint32_t DOUTR16;
1610 __IO uint32_t DOUTR17;
1611 __IO uint32_t DOUTR18;
1612 __IO uint32_t DOUTR19;
1613 __IO uint32_t DOUTR20;
1614 __IO uint32_t DOUTR21;
1615 __IO uint32_t DOUTR22;
1616 __IO uint32_t DOUTR23;
1617 __IO uint32_t DOUTR24;
1618 __IO uint32_t DOUTR25;
1619 __IO uint32_t DOUTR26;
1620 __IO uint32_t DOUTR27;
1621 __IO uint32_t DOUTR28;
1622 __IO uint32_t DOUTR29;
1623 __IO uint32_t DOUTR30;
1624 __IO uint32_t DOUTR31;
1625} MDIOS_TypeDef;
1626
1627
1628/**
1629 * @brief USB_OTG_Core_Registers
1630 */
1631typedef struct
1632{
1633 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
1634 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
1635 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
1636 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
1637 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
1638 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
1639 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
1640 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
1641 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
1642 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
1643 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
1644 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
1645 uint32_t Reserved30[2]; /*!< Reserved 030h */
1646 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
1647 __IO uint32_t CID; /*!< User ID Register 03Ch */
1648 __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
1649 __IO uint32_t GHWCFG1; /* User HW config1 044h*/
1650 __IO uint32_t GHWCFG2; /* User HW config2 048h*/
1651 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
1652 uint32_t Reserved6; /*!< Reserved 050h */
1653 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
1654 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
1655 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
1656 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
1657 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
1658 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
1659 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
1660} USB_OTG_GlobalTypeDef;
1661
1662
1663/**
1664 * @brief USB_OTG_device_Registers
1665 */
1666typedef struct
1667{
1668 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
1669 __IO uint32_t DCTL; /*!< dev Control Register 804h */
1670 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
1671 uint32_t Reserved0C; /*!< Reserved 80Ch */
1672 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
1673 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
1674 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
1675 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
1676 uint32_t Reserved20; /*!< Reserved 820h */
1677 uint32_t Reserved9; /*!< Reserved 824h */
1678 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
1679 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
1680 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
1681 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
1682 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
1683 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
1684 uint32_t Reserved40; /*!< dedicated EP mask 840h */
1685 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
1686 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
1687 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
1688} USB_OTG_DeviceTypeDef;
1689
1690
1691/**
1692 * @brief USB_OTG_IN_Endpoint-Specific_Register
1693 */
1694typedef struct
1695{
1696 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
1697 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
1698 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
1699 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
1700 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
1701 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
1702 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
1703 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
1704} USB_OTG_INEndpointTypeDef;
1705
1706
1707/**
1708 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1709 */
1710typedef struct
1711{
1712 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
1713 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
1714 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
1715 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
1716 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
1717 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
1718 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
1719} USB_OTG_OUTEndpointTypeDef;
1720
1721
1722/**
1723 * @brief USB_OTG_Host_Mode_Register_Structures
1724 */
1725typedef struct
1726{
1727 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
1728 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
1729 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
1730 uint32_t Reserved40C; /*!< Reserved 40Ch */
1731 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
1732 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
1733 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
1734} USB_OTG_HostTypeDef;
1735
1736/**
1737 * @brief USB_OTG_Host_Channel_Specific_Registers
1738 */
1739typedef struct
1740{
1741 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
1742 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
1743 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
1744 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
1745 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
1746 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
1747 uint32_t Reserved[2]; /*!< Reserved */
1748} USB_OTG_HostChannelTypeDef;
1749/**
1750 * @}
1751 */
1752
1753/**
1754 * @brief OCTO Serial Peripheral Interface
1755 */
1756
1757typedef struct
1758{
1759 __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */
1760 uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */
1761 __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */
1762 __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */
1763 __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */
1764 __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */
1765 uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */
1766 __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */
1767 __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */
1768 uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */
1769 __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */
1770 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */
1771 __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */
1772 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */
1773 __IO uint32_t DR; /*!< OCTOSPI Data register, Address offset: 0x050 */
1774 uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */
1775 __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */
1776 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */
1777 __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */
1778 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */
1779 __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */
1780 uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */
1781 __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */
1782 uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */
1783 __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */
1784 uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */
1785 __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */
1786 uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */
1787 __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */
1788 uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */
1789 __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */
1790 uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */
1791 __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */
1792 uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */
1793 __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */
1794 uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */
1795 __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */
1796 uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */
1797 __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */
1798 uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */
1799 __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */
1800 uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */
1801 __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */
1802 uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */
1803 __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */
1804 uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */
1805 __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */
1806 uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
1807 __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */
1808 uint32_t RESERVED22[122]; /*!< Reserved, Address offset: 0x204-0x3EC */
1809 __IO uint32_t HWCFGR; /*!< OCTOSPI HW Configuration register, Address offset: 0x3F0 */
1810 __IO uint32_t VER; /*!< OCTOSPI Version register, Address offset: 0x3F4 */
1811 __IO uint32_t ID; /*!< OCTOSPI Identification register, Address offset: 0x3F8 */
1812 __IO uint32_t MID; /*!< OCTOPSI HW Magic ID register, Address offset: 0x3FC */
1813} OCTOSPI_TypeDef;
1814
1815/**
1816 * @}
1817 */
1818/**
1819 * @brief OCTO Serial Peripheral Interface IO Manager
1820 */
1821
1822typedef struct
1823{
1824 __IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */
1825 __IO uint32_t PCR[8]; /*!< OCTOSPI IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */
1826} OCTOSPIM_TypeDef;
1827
1828/**
1829 * @}
1830 */
1831
1832/** @addtogroup Peripheral_memory_map
1833 * @{
1834 */
1835#define CD_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */
1836#define CD_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB (2x64KB) system data RAM accessible over DTCM */
1837#define CD_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
1838
1839#define CD_AXISRAM1_BASE (0x24000000UL) /*!< Base address of : (up to 256KB) system data RAM1 accessible over over AXI */
1840#define CD_AXISRAM2_BASE (0x24040000UL) /*!< Base address of : (up to 384KB) system data RAM2 accessible over over AXI */
1841#define CD_AXISRAM3_BASE (0x240A0000UL) /*!< Base address of : (up to 384KB) system data RAM3 accessible over over AXI */
1842#define CD_AHBSRAM1_BASE (0x30000000UL) /*!< Base address of : (up to 64KB) system data RAM1 accessible over over AXI->AHB Bridge */
1843#define CD_AHBSRAM2_BASE (0x30010000UL) /*!< Base address of : (up to 64KB) system data RAM2 accessible over over AXI->AHB Bridge */
1844
1845#define SRD_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */
1846#define SRD_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(32 KB) over AXI->AHB Bridge */
1847
1848#define OCTOSPI1_BASE (0x90000000UL) /*!< Base address of : OCTOSPI1 memories accessible over AXI */
1849#define OCTOSPI2_BASE (0x70000000UL) /*!< Base address of : OCTOSPI2 memories accessible over AXI */
1850
1851#define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */
1852#define FLASH_BANK2_BASE (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI */
1853#define FLASH_END (0x081FFFFFUL) /*!< FLASH end address */
1854
1855/* Legacy define */
1856#define FLASH_BASE FLASH_BANK1_BASE
1857#define D1_AXISRAM_BASE CD_AXISRAM1_BASE
1858
1859#define FLASH_OTP_BASE (0x08FFF000UL) /*!< Base address of : (up to 1KB) embedded FLASH Bank1 OTP Area */
1860#define FLASH_OTP_END (0x08FFF3FFUL) /*!< End address of : (up to 1KB) embedded FLASH Bank1 OTP Area */
1861
1862
1863/*!< Device electronic signature memory map */
1864#define UID_BASE (0x08FFF800UL) /*!< Unique device ID register base address */
1865#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< FLASH Size register base address */
1866#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package Data register base address */
1867
1868#define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/ABP Peripherals */
1869/*!< Peripheral memory map */
1870#define CD_APB1PERIPH_BASE PERIPH_BASE /*!< D2_APB1PERIPH_BASE PERIPH_BASE */
1871#define CD_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) /*!< D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) */
1872#define CD_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) /*!< D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) */
1873#define CD_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL) /*!< D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL) */
1874
1875#define CD_APB3PERIPH_BASE (PERIPH_BASE + 0x10000000UL) /*!< D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL) */
1876#define CD_AHB3PERIPH_BASE (PERIPH_BASE + 0x12000000UL) /*!< D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL) */
1877
1878#define SRD_APB4PERIPH_BASE (PERIPH_BASE + 0x18000000UL) /*!< D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL) */
1879#define SRD_AHB4PERIPH_BASE (PERIPH_BASE + 0x18020000UL) /*!< D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL) */
1880
1881/*!< Legacy Peripheral memory map */
1882#define APB1PERIPH_BASE PERIPH_BASE
1883#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
1884#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
1885#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL)
1886
1887/*!< CD_AHB3PERIPH peripherals */
1888#define MDMA_BASE (CD_AHB3PERIPH_BASE + 0x0000UL)
1889#define DMA2D_BASE (CD_AHB3PERIPH_BASE + 0x1000UL)
1890#define FLASH_R_BASE (CD_AHB3PERIPH_BASE + 0x2000UL)
1891#define JPGDEC_BASE (CD_AHB3PERIPH_BASE + 0x3000UL)
1892#define FMC_R_BASE (CD_AHB3PERIPH_BASE + 0x4000UL)
1893#define OCTOSPI1_R_BASE (CD_AHB3PERIPH_BASE + 0x5000UL)
1894#define DLYB_OCTOSPI1_BASE (CD_AHB3PERIPH_BASE + 0x6000UL)
1895#define SDMMC1_BASE (CD_AHB3PERIPH_BASE + 0x7000UL)
1896#define DLYB_SDMMC1_BASE (CD_AHB3PERIPH_BASE + 0x8000UL)
1897#define RAMECC_BASE (CD_AHB3PERIPH_BASE + 0x9000UL)
1898#define OCTOSPI2_R_BASE (CD_AHB3PERIPH_BASE + 0xA000UL)
1899#define DLYB_OCTOSPI2_BASE (CD_AHB3PERIPH_BASE + 0xB000UL)
1900#define OCTOSPIM_BASE (CD_AHB3PERIPH_BASE + 0xB400UL)
1901
1902/*!< CD_AHB1PERIPH peripherals */
1903
1904#define DMA1_BASE (CD_AHB1PERIPH_BASE + 0x0000UL)
1905#define DMA2_BASE (CD_AHB1PERIPH_BASE + 0x0400UL)
1906#define DMAMUX1_BASE (CD_AHB1PERIPH_BASE + 0x0800UL)
1907#define ADC1_BASE (CD_AHB1PERIPH_BASE + 0x2000UL)
1908#define ADC2_BASE (CD_AHB1PERIPH_BASE + 0x2100UL)
1909#define ADC12_COMMON_BASE (CD_AHB1PERIPH_BASE + 0x2300UL)
1910#define CRC_BASE (CD_AHB1PERIPH_BASE + 0x3000UL)
1911
1912/*!< USB registers base address */
1913#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL)
1914#define USB_OTG_GLOBAL_BASE (0x000UL)
1915#define USB_OTG_DEVICE_BASE (0x800UL)
1916#define USB_OTG_IN_ENDPOINT_BASE (0x900UL)
1917#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL)
1918#define USB_OTG_EP_REG_SIZE (0x20UL)
1919#define USB_OTG_HOST_BASE (0x400UL)
1920#define USB_OTG_HOST_PORT_BASE (0x440UL)
1921#define USB_OTG_HOST_CHANNEL_BASE (0x500UL)
1922#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL)
1923#define USB_OTG_PCGCCTL_BASE (0xE00UL)
1924#define USB_OTG_FIFO_BASE (0x1000UL)
1925#define USB_OTG_FIFO_SIZE (0x1000UL)
1926
1927/*!< CD_AHB2PERIPH peripherals */
1928
1929#define DCMI_BASE (CD_AHB2PERIPH_BASE + 0x0000UL)
1930#define PSSI_BASE (CD_AHB2PERIPH_BASE + 0x0400UL)
1931#define HSEM_BASE (CD_AHB2PERIPH_BASE + 0x0800UL)
1932#define RNG_BASE (CD_AHB2PERIPH_BASE + 0x1800UL)
1933#define SDMMC2_BASE (CD_AHB2PERIPH_BASE + 0x2400UL)
1934#define DLYB_SDMMC2_BASE (CD_AHB2PERIPH_BASE + 0x2800UL)
1935#define BDMA1_BASE (CD_AHB2PERIPH_BASE + 0x2C00UL)
1936
1937/*!< SRD_AHB4PERIPH peripherals */
1938#define GPIOA_BASE (SRD_AHB4PERIPH_BASE + 0x0000UL)
1939#define GPIOB_BASE (SRD_AHB4PERIPH_BASE + 0x0400UL)
1940#define GPIOC_BASE (SRD_AHB4PERIPH_BASE + 0x0800UL)
1941#define GPIOD_BASE (SRD_AHB4PERIPH_BASE + 0x0C00UL)
1942#define GPIOE_BASE (SRD_AHB4PERIPH_BASE + 0x1000UL)
1943#define GPIOF_BASE (SRD_AHB4PERIPH_BASE + 0x1400UL)
1944#define GPIOG_BASE (SRD_AHB4PERIPH_BASE + 0x1800UL)
1945#define GPIOH_BASE (SRD_AHB4PERIPH_BASE + 0x1C00UL)
1946#define GPIOI_BASE (SRD_AHB4PERIPH_BASE + 0x2000UL)
1947#define GPIOJ_BASE (SRD_AHB4PERIPH_BASE + 0x2400UL)
1948#define GPIOK_BASE (SRD_AHB4PERIPH_BASE + 0x2800UL)
1949#define RCC_BASE (SRD_AHB4PERIPH_BASE + 0x4400UL)
1950#define PWR_BASE (SRD_AHB4PERIPH_BASE + 0x4800UL)
1951#define BDMA2_BASE (SRD_AHB4PERIPH_BASE + 0x5400UL)
1952#define DMAMUX2_BASE (SRD_AHB4PERIPH_BASE + 0x5800UL)
1953
1954/*!< CD_APB3PERIPH peripherals */
1955#define LTDC_BASE (CD_APB3PERIPH_BASE + 0x1000UL)
1956#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)
1957#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)
1958#define WWDG1_BASE (CD_APB3PERIPH_BASE + 0x3000UL)
1959
1960/*!< CD_APB1PERIPH peripherals */
1961#define TIM2_BASE (CD_APB1PERIPH_BASE + 0x0000UL)
1962#define TIM3_BASE (CD_APB1PERIPH_BASE + 0x0400UL)
1963#define TIM4_BASE (CD_APB1PERIPH_BASE + 0x0800UL)
1964#define TIM5_BASE (CD_APB1PERIPH_BASE + 0x0C00UL)
1965#define TIM6_BASE (CD_APB1PERIPH_BASE + 0x1000UL)
1966#define TIM7_BASE (CD_APB1PERIPH_BASE + 0x1400UL)
1967#define TIM12_BASE (CD_APB1PERIPH_BASE + 0x1800UL)
1968#define TIM13_BASE (CD_APB1PERIPH_BASE + 0x1C00UL)
1969#define TIM14_BASE (CD_APB1PERIPH_BASE + 0x2000UL)
1970#define LPTIM1_BASE (CD_APB1PERIPH_BASE + 0x2400UL)
1971
1972#define SPI2_BASE (CD_APB1PERIPH_BASE + 0x3800UL)
1973#define SPI3_BASE (CD_APB1PERIPH_BASE + 0x3C00UL)
1974#define SPDIFRX_BASE (CD_APB1PERIPH_BASE + 0x4000UL)
1975#define USART2_BASE (CD_APB1PERIPH_BASE + 0x4400UL)
1976#define USART3_BASE (CD_APB1PERIPH_BASE + 0x4800UL)
1977#define UART4_BASE (CD_APB1PERIPH_BASE + 0x4C00UL)
1978#define UART5_BASE (CD_APB1PERIPH_BASE + 0x5000UL)
1979#define I2C1_BASE (CD_APB1PERIPH_BASE + 0x5400UL)
1980#define I2C2_BASE (CD_APB1PERIPH_BASE + 0x5800UL)
1981#define I2C3_BASE (CD_APB1PERIPH_BASE + 0x5C00UL)
1982#define CEC_BASE (CD_APB1PERIPH_BASE + 0x6C00UL)
1983#define DAC1_BASE (CD_APB1PERIPH_BASE + 0x7400UL)
1984#define UART7_BASE (CD_APB1PERIPH_BASE + 0x7800UL)
1985#define UART8_BASE (CD_APB1PERIPH_BASE + 0x7C00UL)
1986#define CRS_BASE (CD_APB1PERIPH_BASE + 0x8400UL)
1987#define SWPMI1_BASE (CD_APB1PERIPH_BASE + 0x8800UL)
1988#define OPAMP_BASE (CD_APB1PERIPH_BASE + 0x9000UL)
1989#define OPAMP1_BASE (CD_APB1PERIPH_BASE + 0x9000UL)
1990#define OPAMP2_BASE (CD_APB1PERIPH_BASE + 0x9010UL)
1991#define MDIOS_BASE (CD_APB1PERIPH_BASE + 0x9400UL)
1992#define FDCAN1_BASE (CD_APB1PERIPH_BASE + 0xA000UL)
1993#define FDCAN2_BASE (CD_APB1PERIPH_BASE + 0xA400UL)
1994#define FDCAN_CCU_BASE (CD_APB1PERIPH_BASE + 0xA800UL)
1995#define SRAMCAN_BASE (CD_APB1PERIPH_BASE + 0xAC00UL)
1996
1997/*!< CD_APB2PERIPH peripherals */
1998
1999#define TIM1_BASE (CD_APB2PERIPH_BASE + 0x0000UL)
2000#define TIM8_BASE (CD_APB2PERIPH_BASE + 0x0400UL)
2001#define USART1_BASE (CD_APB2PERIPH_BASE + 0x1000UL)
2002#define USART6_BASE (CD_APB2PERIPH_BASE + 0x1400UL)
2003#define UART9_BASE (CD_APB2PERIPH_BASE + 0x1800UL)
2004#define USART10_BASE (CD_APB2PERIPH_BASE + 0x1C00UL)
2005#define SPI1_BASE (CD_APB2PERIPH_BASE + 0x3000UL)
2006#define SPI4_BASE (CD_APB2PERIPH_BASE + 0x3400UL)
2007#define TIM15_BASE (CD_APB2PERIPH_BASE + 0x4000UL)
2008#define TIM16_BASE (CD_APB2PERIPH_BASE + 0x4400UL)
2009#define TIM17_BASE (CD_APB2PERIPH_BASE + 0x4800UL)
2010#define SPI5_BASE (CD_APB2PERIPH_BASE + 0x5000UL)
2011#define SAI1_BASE (CD_APB2PERIPH_BASE + 0x5800UL)
2012#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
2013#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
2014#define SAI2_BASE (CD_APB2PERIPH_BASE + 0x5C00UL)
2015#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
2016#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
2017#define DFSDM1_BASE (CD_APB2PERIPH_BASE + 0x7800UL)
2018#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
2019#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
2020#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
2021#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
2022#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)
2023#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)
2024#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)
2025#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)
2026#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
2027#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
2028#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)
2029#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)
2030#define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300UL)
2031#define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380UL)
2032#define DFSDM1_Filter6_BASE (DFSDM1_BASE + 0x400UL)
2033#define DFSDM1_Filter7_BASE (DFSDM1_BASE + 0x480UL)
2034/*!< SRD_APB4PERIPH peripherals */
2035#define EXTI_BASE (SRD_APB4PERIPH_BASE + 0x0000UL)
2036#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL)
2037#define SYSCFG_BASE (SRD_APB4PERIPH_BASE + 0x0400UL)
2038#define LPUART1_BASE (SRD_APB4PERIPH_BASE + 0x0C00UL)
2039#define SPI6_BASE (SRD_APB4PERIPH_BASE + 0x1400UL)
2040#define I2C4_BASE (SRD_APB4PERIPH_BASE + 0x1C00UL)
2041#define LPTIM2_BASE (SRD_APB4PERIPH_BASE + 0x2400UL)
2042#define LPTIM3_BASE (SRD_APB4PERIPH_BASE + 0x2800UL)
2043#define DAC2_BASE (SRD_APB4PERIPH_BASE + 0x3400UL)
2044#define COMP12_BASE (SRD_APB4PERIPH_BASE + 0x3800UL)
2045#define COMP1_BASE (COMP12_BASE + 0x0CUL)
2046#define COMP2_BASE (COMP12_BASE + 0x10UL)
2047#define VREFBUF_BASE (SRD_APB4PERIPH_BASE + 0x3C00UL)
2048#define RTC_BASE (SRD_APB4PERIPH_BASE + 0x4000UL)
2049#define TAMP_BASE (SRD_APB4PERIPH_BASE + 0x4400UL)
2050#define IWDG1_BASE (SRD_APB4PERIPH_BASE + 0x4800UL)
2051
2052#define DTS_BASE (SRD_APB4PERIPH_BASE + 0x6800UL)
2053
2054#define DFSDM2_BASE (SRD_APB4PERIPH_BASE + 0x6C00UL)
2055#define DFSDM2_Channel0_BASE (DFSDM2_BASE + 0x00UL)
2056#define DFSDM2_Channel1_BASE (DFSDM2_BASE + 0x20UL)
2057#define DFSDM2_FLT0_BASE (DFSDM2_BASE + 0x100UL)
2058
2059/*!< CD_AHB3PERIPH peripherals */
2060#define GFXMMU_BASE (CD_AHB3PERIPH_BASE + 0xC000UL)
2061
2062#define BDMA1_Channel0_BASE (BDMA1_BASE + 0x0008UL)
2063#define BDMA1_Channel1_BASE (BDMA1_BASE + 0x001CUL)
2064#define BDMA1_Channel2_BASE (BDMA1_BASE + 0x0030UL)
2065#define BDMA1_Channel3_BASE (BDMA1_BASE + 0x0044UL)
2066#define BDMA1_Channel4_BASE (BDMA1_BASE + 0x0058UL)
2067#define BDMA1_Channel5_BASE (BDMA1_BASE + 0x006CUL)
2068#define BDMA1_Channel6_BASE (BDMA1_BASE + 0x0080UL)
2069#define BDMA1_Channel7_BASE (BDMA1_BASE + 0x0094UL)
2070
2071#define BDMA2_Channel0_BASE (BDMA2_BASE + 0x0008UL)
2072#define BDMA2_Channel1_BASE (BDMA2_BASE + 0x001CUL)
2073#define BDMA2_Channel2_BASE (BDMA2_BASE + 0x0030UL)
2074#define BDMA2_Channel3_BASE (BDMA2_BASE + 0x0044UL)
2075#define BDMA2_Channel4_BASE (BDMA2_BASE + 0x0058UL)
2076#define BDMA2_Channel5_BASE (BDMA2_BASE + 0x006CUL)
2077#define BDMA2_Channel6_BASE (BDMA2_BASE + 0x0080UL)
2078#define BDMA2_Channel7_BASE (BDMA2_BASE + 0x0094UL)
2079
2080
2081#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE)
2082#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL)
2083#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL)
2084#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL)
2085#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL)
2086#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL)
2087#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL)
2088#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL)
2089
2090#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL)
2091#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL)
2092#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL)
2093#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL)
2094#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL)
2095#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL)
2096#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL)
2097#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL)
2098
2099#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL)
2100#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL)
2101
2102#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
2103#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
2104#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
2105#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
2106#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
2107#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
2108#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
2109#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
2110
2111#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
2112#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
2113#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
2114#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
2115#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
2116#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
2117#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
2118#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
2119
2120
2121#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
2122#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
2123#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
2124#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
2125#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
2126#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
2127#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
2128#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
2129#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
2130#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
2131#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
2132#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
2133#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
2134#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
2135#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
2136#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
2137
2138#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
2139#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
2140#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
2141#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
2142#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL)
2143#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL)
2144#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL)
2145#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL)
2146
2147#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
2148#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
2149
2150/*!< FMC Banks registers base address */
2151#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
2152#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
2153#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL)
2154#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
2155#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
2156
2157/* Debug MCU registers base address */
2158#define DBGMCU_BASE (0x5C001000UL)
2159
2160#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL)
2161#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL)
2162#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL)
2163#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL)
2164#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL)
2165#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL)
2166#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL)
2167#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL)
2168#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL)
2169#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL)
2170#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL)
2171#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL)
2172#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL)
2173#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
2174#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
2175#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
2176#define MDMA_Channel16_BASE (MDMA_BASE + 0x00000440UL)
2177
2178/* GFXMMU virtual buffers base address */
2179#define GFXMMU_VIRTUAL_BUFFERS_BASE (0x25000000UL)
2180#define GFXMMU_VIRTUAL_BUFFER0_BASE (GFXMMU_VIRTUAL_BUFFERS_BASE)
2181#define GFXMMU_VIRTUAL_BUFFER1_BASE (GFXMMU_VIRTUAL_BUFFERS_BASE + 0x400000UL)
2182#define GFXMMU_VIRTUAL_BUFFER2_BASE (GFXMMU_VIRTUAL_BUFFERS_BASE + 0x800000UL)
2183#define GFXMMU_VIRTUAL_BUFFER3_BASE (GFXMMU_VIRTUAL_BUFFERS_BASE + 0xC00000UL)
2184
2185#define RAMECC_Monitor1_BASE (RAMECC_BASE + 0x20UL)
2186#define RAMECC_Monitor2_BASE (RAMECC_BASE + 0x40UL)
2187#define RAMECC_Monitor3_BASE (RAMECC_BASE + 0x60UL)
2188
2189/**
2190 * @}
2191 */
2192
2193/** @addtogroup Peripheral_declaration
2194 * @{
2195 */
2196#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
2197#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
2198#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
2199#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
2200#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
2201#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
2202#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
2203#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
2204#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
2205#define RTC ((RTC_TypeDef *) RTC_BASE)
2206#define TAMP ((TAMP_TypeDef *) TAMP_BASE)
2207#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)
2208
2209
2210#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)
2211#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
2212#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
2213#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
2214#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
2215#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
2216#define USART2 ((USART_TypeDef *) USART2_BASE)
2217#define USART3 ((USART_TypeDef *) USART3_BASE)
2218#define USART6 ((USART_TypeDef *) USART6_BASE)
2219#define USART10 ((USART_TypeDef *) USART10_BASE)
2220#define UART7 ((USART_TypeDef *) UART7_BASE)
2221#define UART8 ((USART_TypeDef *) UART8_BASE)
2222#define UART9 ((USART_TypeDef *) UART9_BASE)
2223#define CRS ((CRS_TypeDef *) CRS_BASE)
2224#define UART4 ((USART_TypeDef *) UART4_BASE)
2225#define UART5 ((USART_TypeDef *) UART5_BASE)
2226#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
2227#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
2228#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
2229#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
2230#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
2231#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
2232#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
2233#define CEC ((CEC_TypeDef *) CEC_BASE)
2234#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
2235#define PWR ((PWR_TypeDef *) PWR_BASE)
2236#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
2237#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
2238#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
2239#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
2240#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)
2241#define DTS ((DTS_TypeDef *) DTS_BASE)
2242
2243#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
2244#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)
2245#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
2246#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
2247#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
2248#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
2249#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
2250#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
2251
2252
2253#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
2254#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
2255#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
2256#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
2257#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
2258#define USART1 ((USART_TypeDef *) USART1_BASE)
2259#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
2260#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
2261#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
2262#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
2263#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
2264#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
2265#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
2266#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
2267#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
2268#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
2269
2270#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
2271#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
2272#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
2273#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
2274#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
2275#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
2276#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
2277#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
2278#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
2279#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
2280#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
2281#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
2282#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
2283#define DFSDM1_Filter4 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter4_BASE)
2284#define DFSDM1_Filter5 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter5_BASE)
2285#define DFSDM1_Filter6 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter6_BASE)
2286#define DFSDM1_Filter7 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter7_BASE)
2287#define DFSDM2_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)
2288#define DFSDM2_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)
2289#define DFSDM2_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM2_FLT0_BASE)
2290#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)
2291#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
2292#define PSSI ((PSSI_TypeDef *) PSSI_BASE)
2293#define RCC ((RCC_TypeDef *) RCC_BASE)
2294#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
2295#define CRC ((CRC_TypeDef *) CRC_BASE)
2296
2297#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
2298#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
2299#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
2300#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
2301#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
2302#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
2303#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
2304#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
2305#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
2306#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
2307#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
2308
2309#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
2310#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
2311#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
2312
2313#define RNG ((RNG_TypeDef *) RNG_BASE)
2314#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
2315#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
2316
2317#define BDMA1 ((BDMA_TypeDef *) BDMA1_BASE)
2318#define BDMA1_Channel0 ((BDMA_Channel_TypeDef *) BDMA1_Channel0_BASE)
2319#define BDMA1_Channel1 ((BDMA_Channel_TypeDef *) BDMA1_Channel1_BASE)
2320#define BDMA1_Channel2 ((BDMA_Channel_TypeDef *) BDMA1_Channel2_BASE)
2321#define BDMA1_Channel3 ((BDMA_Channel_TypeDef *) BDMA1_Channel3_BASE)
2322#define BDMA1_Channel4 ((BDMA_Channel_TypeDef *) BDMA1_Channel4_BASE)
2323#define BDMA1_Channel5 ((BDMA_Channel_TypeDef *) BDMA1_Channel5_BASE)
2324#define BDMA1_Channel6 ((BDMA_Channel_TypeDef *) BDMA1_Channel6_BASE)
2325#define BDMA1_Channel7 ((BDMA_Channel_TypeDef *) BDMA1_Channel7_BASE)
2326
2327#define BDMA2 ((BDMA_TypeDef *) BDMA2_BASE)
2328#define BDMA2_Channel0 ((BDMA_Channel_TypeDef *) BDMA2_Channel0_BASE)
2329#define BDMA2_Channel1 ((BDMA_Channel_TypeDef *) BDMA2_Channel1_BASE)
2330#define BDMA2_Channel2 ((BDMA_Channel_TypeDef *) BDMA2_Channel2_BASE)
2331#define BDMA2_Channel3 ((BDMA_Channel_TypeDef *) BDMA2_Channel3_BASE)
2332#define BDMA2_Channel4 ((BDMA_Channel_TypeDef *) BDMA2_Channel4_BASE)
2333#define BDMA2_Channel5 ((BDMA_Channel_TypeDef *) BDMA2_Channel5_BASE)
2334#define BDMA2_Channel6 ((BDMA_Channel_TypeDef *) BDMA2_Channel6_BASE)
2335#define BDMA2_Channel7 ((BDMA_Channel_TypeDef *) BDMA2_Channel7_BASE)
2336
2337#define RAMECC ((RAMECC_TypeDef *)RAMECC_BASE)
2338#define RAMECC_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor1_BASE)
2339#define RAMECC_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor2_BASE)
2340#define RAMECC_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor3_BASE)
2341
2342#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
2343#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
2344#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
2345#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
2346#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
2347#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
2348#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
2349#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
2350#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
2351
2352
2353#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
2354#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
2355#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
2356#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
2357#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
2358#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
2359#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
2360#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
2361
2362#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
2363#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
2364
2365#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
2366#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
2367#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
2368#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
2369#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
2370#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
2371#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
2372#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
2373#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
2374
2375#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
2376#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
2377#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
2378#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
2379#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
2380#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
2381#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
2382#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
2383#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
2384
2385
2386#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
2387#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
2388#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
2389#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
2390#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
2391#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
2392#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
2393#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
2394#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
2395#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
2396#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
2397#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
2398#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
2399#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
2400#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
2401#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
2402#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
2403
2404#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
2405#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
2406#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
2407#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
2408#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
2409#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
2410#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
2411#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
2412
2413#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
2414#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
2415
2416
2417#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
2418#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
2419#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
2420#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
2421#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
2422
2423#define DAC2 ((DAC_TypeDef *) DAC2_BASE)
2424#define OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)
2425#define DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)
2426#define OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)
2427#define DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)
2428#define OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)
2429#define GFXMMU ((GFXMMU_TypeDef *) GFXMMU_BASE)
2430
2431#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
2432#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
2433
2434#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
2435
2436#define JPEG ((JPEG_TypeDef *) JPGDEC_BASE)
2437#define HSEM ((HSEM_TypeDef *) HSEM_BASE)
2438#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
2439
2440#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
2441#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
2442#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
2443
2444#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
2445
2446#define MDMA ((MDMA_TypeDef *)MDMA_BASE)
2447#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
2448#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
2449#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
2450#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
2451#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
2452#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
2453#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
2454#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
2455#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
2456#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
2457#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
2458#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
2459#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
2460#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
2461#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
2462#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
2463
2464
2465#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
2466
2467/* Legacy defines */
2468#define USB_OTG_HS USB1_OTG_HS
2469#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
2470
2471/**
2472 * @}
2473 */
2474
2475/** @addtogroup Exported_constants
2476 * @{
2477 */
2478
2479 /** @addtogroup Peripheral_Registers_Bits_Definition
2480 * @{
2481 */
2482
2483/******************************************************************************/
2484/* Peripheral Registers_Bits_Definition */
2485/******************************************************************************/
2486
2487/******************************************************************************/
2488/* */
2489/* Analog to Digital Converter */
2490/* */
2491/******************************************************************************/
2492/******************************* ADC VERSION ********************************/
2493#define ADC_VER_V5_3
2494/******************** Bit definition for ADC_ISR register ********************/
2495#define ADC_ISR_ADRDY_Pos (0U)
2496#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
2497#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */
2498#define ADC_ISR_EOSMP_Pos (1U)
2499#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
2500#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */
2501#define ADC_ISR_EOC_Pos (2U)
2502#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
2503#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */
2504#define ADC_ISR_EOS_Pos (3U)
2505#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
2506#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */
2507#define ADC_ISR_OVR_Pos (4U)
2508#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
2509#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */
2510#define ADC_ISR_JEOC_Pos (5U)
2511#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
2512#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */
2513#define ADC_ISR_JEOS_Pos (6U)
2514#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
2515#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */
2516#define ADC_ISR_AWD1_Pos (7U)
2517#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
2518#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */
2519#define ADC_ISR_AWD2_Pos (8U)
2520#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
2521#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */
2522#define ADC_ISR_AWD3_Pos (9U)
2523#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
2524#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */
2525#define ADC_ISR_JQOVF_Pos (10U)
2526#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
2527#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
2528
2529/******************** Bit definition for ADC_IER register ********************/
2530#define ADC_IER_ADRDYIE_Pos (0U)
2531#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
2532#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */
2533#define ADC_IER_EOSMPIE_Pos (1U)
2534#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
2535#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */
2536#define ADC_IER_EOCIE_Pos (2U)
2537#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
2538#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */
2539#define ADC_IER_EOSIE_Pos (3U)
2540#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
2541#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */
2542#define ADC_IER_OVRIE_Pos (4U)
2543#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
2544#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */
2545#define ADC_IER_JEOCIE_Pos (5U)
2546#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
2547#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */
2548#define ADC_IER_JEOSIE_Pos (6U)
2549#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
2550#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */
2551#define ADC_IER_AWD1IE_Pos (7U)
2552#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
2553#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */
2554#define ADC_IER_AWD2IE_Pos (8U)
2555#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
2556#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */
2557#define ADC_IER_AWD3IE_Pos (9U)
2558#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
2559#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */
2560#define ADC_IER_JQOVFIE_Pos (10U)
2561#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
2562#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */
2563
2564/******************** Bit definition for ADC_CR register ********************/
2565#define ADC_CR_ADEN_Pos (0U)
2566#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
2567#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */
2568#define ADC_CR_ADDIS_Pos (1U)
2569#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
2570#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */
2571#define ADC_CR_ADSTART_Pos (2U)
2572#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
2573#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */
2574#define ADC_CR_JADSTART_Pos (3U)
2575#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
2576#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */
2577#define ADC_CR_ADSTP_Pos (4U)
2578#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
2579#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */
2580#define ADC_CR_JADSTP_Pos (5U)
2581#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
2582#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */
2583#define ADC_CR_BOOST_Pos (8U)
2584#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */
2585#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */
2586#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */
2587#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */
2588#define ADC_CR_ADCALLIN_Pos (16U)
2589#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */
2590#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */
2591#define ADC_CR_LINCALRDYW1_Pos (22U)
2592#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */
2593#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */
2594#define ADC_CR_LINCALRDYW2_Pos (23U)
2595#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */
2596#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */
2597#define ADC_CR_LINCALRDYW3_Pos (24U)
2598#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */
2599#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */
2600#define ADC_CR_LINCALRDYW4_Pos (25U)
2601#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */
2602#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */
2603#define ADC_CR_LINCALRDYW5_Pos (26U)
2604#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */
2605#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */
2606#define ADC_CR_LINCALRDYW6_Pos (27U)
2607#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */
2608#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */
2609#define ADC_CR_ADVREGEN_Pos (28U)
2610#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
2611#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */
2612#define ADC_CR_DEEPPWD_Pos (29U)
2613#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
2614#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */
2615#define ADC_CR_ADCALDIF_Pos (30U)
2616#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
2617#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */
2618#define ADC_CR_ADCAL_Pos (31U)
2619#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
2620#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */
2621
2622/******************** Bit definition for ADC_CFGR register ********************/
2623#define ADC_CFGR_DMNGT_Pos (0U)
2624#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */
2625#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */
2626#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */
2627#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */
2628
2629#define ADC_CFGR_RES_Pos (2U)
2630#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */
2631#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */
2632#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */
2633#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
2634#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
2635
2636#define ADC_CFGR_EXTSEL_Pos (5U)
2637#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
2638#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */
2639#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
2640#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
2641#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
2642#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
2643#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
2644
2645#define ADC_CFGR_EXTEN_Pos (10U)
2646#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
2647#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */
2648#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
2649#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
2650
2651#define ADC_CFGR_OVRMOD_Pos (12U)
2652#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
2653#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */
2654#define ADC_CFGR_CONT_Pos (13U)
2655#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
2656#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */
2657#define ADC_CFGR_AUTDLY_Pos (14U)
2658#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
2659#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */
2660
2661#define ADC_CFGR_DISCEN_Pos (16U)
2662#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
2663#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */
2664
2665#define ADC_CFGR_DISCNUM_Pos (17U)
2666#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
2667#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
2668#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
2669#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
2670#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
2671
2672#define ADC_CFGR_JDISCEN_Pos (20U)
2673#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
2674#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
2675#define ADC_CFGR_JQM_Pos (21U)
2676#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
2677#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */
2678#define ADC_CFGR_AWD1SGL_Pos (22U)
2679#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
2680#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */
2681#define ADC_CFGR_AWD1EN_Pos (23U)
2682#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
2683#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */
2684#define ADC_CFGR_JAWD1EN_Pos (24U)
2685#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
2686#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */
2687#define ADC_CFGR_JAUTO_Pos (25U)
2688#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
2689#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */
2690
2691#define ADC_CFGR_AWD1CH_Pos (26U)
2692#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
2693#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */
2694#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
2695#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
2696#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
2697#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
2698#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
2699
2700#define ADC_CFGR_JQDIS_Pos (31U)
2701#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
2702#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */
2703
2704/******************** Bit definition for ADC_CFGR2 register ********************/
2705#define ADC_CFGR2_ROVSE_Pos (0U)
2706#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
2707#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */
2708#define ADC_CFGR2_JOVSE_Pos (1U)
2709#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
2710#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */
2711
2712#define ADC_CFGR2_OVSS_Pos (5U)
2713#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
2714#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */
2715#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
2716#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
2717#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
2718#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
2719
2720#define ADC_CFGR2_TROVS_Pos (9U)
2721#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
2722#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */
2723#define ADC_CFGR2_ROVSM_Pos (10U)
2724#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
2725#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */
2726
2727#define ADC_CFGR2_RSHIFT1_Pos (11U)
2728#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */
2729#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */
2730#define ADC_CFGR2_RSHIFT2_Pos (12U)
2731#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */
2732#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */
2733#define ADC_CFGR2_RSHIFT3_Pos (13U)
2734#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */
2735#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */
2736#define ADC_CFGR2_RSHIFT4_Pos (14U)
2737#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */
2738#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */
2739
2740#define ADC_CFGR2_OVSR_Pos (16U)
2741#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */
2742#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */
2743#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */
2744#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */
2745#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */
2746#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */
2747#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */
2748#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */
2749#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */
2750#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */
2751#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */
2752#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */
2753
2754#define ADC_CFGR2_LSHIFT_Pos (28U)
2755#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */
2756#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */
2757#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */
2758#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */
2759#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */
2760#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */
2761
2762/******************** Bit definition for ADC_SMPR1 register ********************/
2763#define ADC_SMPR1_SMP0_Pos (0U)
2764#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
2765#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */
2766#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
2767#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
2768#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
2769
2770#define ADC_SMPR1_SMP1_Pos (3U)
2771#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
2772#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */
2773#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
2774#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
2775#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
2776
2777#define ADC_SMPR1_SMP2_Pos (6U)
2778#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
2779#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */
2780#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
2781#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
2782#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
2783
2784#define ADC_SMPR1_SMP3_Pos (9U)
2785#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
2786#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */
2787#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
2788#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
2789#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
2790
2791#define ADC_SMPR1_SMP4_Pos (12U)
2792#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
2793#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */
2794#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
2795#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
2796#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
2797
2798#define ADC_SMPR1_SMP5_Pos (15U)
2799#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
2800#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */
2801#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
2802#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
2803#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
2804
2805#define ADC_SMPR1_SMP6_Pos (18U)
2806#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
2807#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */
2808#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
2809#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
2810#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
2811
2812#define ADC_SMPR1_SMP7_Pos (21U)
2813#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
2814#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */
2815#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
2816#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
2817#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
2818
2819#define ADC_SMPR1_SMP8_Pos (24U)
2820#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
2821#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */
2822#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
2823#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
2824#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
2825
2826#define ADC_SMPR1_SMP9_Pos (27U)
2827#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
2828#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */
2829#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
2830#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
2831#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
2832
2833/******************** Bit definition for ADC_SMPR2 register ********************/
2834#define ADC_SMPR2_SMP10_Pos (0U)
2835#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
2836#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */
2837#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
2838#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
2839#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
2840
2841#define ADC_SMPR2_SMP11_Pos (3U)
2842#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
2843#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */
2844#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
2845#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
2846#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
2847
2848#define ADC_SMPR2_SMP12_Pos (6U)
2849#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
2850#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */
2851#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
2852#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
2853#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
2854
2855#define ADC_SMPR2_SMP13_Pos (9U)
2856#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
2857#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */
2858#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
2859#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
2860#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
2861
2862#define ADC_SMPR2_SMP14_Pos (12U)
2863#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
2864#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */
2865#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
2866#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
2867#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
2868
2869#define ADC_SMPR2_SMP15_Pos (15U)
2870#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
2871#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */
2872#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
2873#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
2874#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
2875
2876#define ADC_SMPR2_SMP16_Pos (18U)
2877#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
2878#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */
2879#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
2880#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
2881#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
2882
2883#define ADC_SMPR2_SMP17_Pos (21U)
2884#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
2885#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */
2886#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
2887#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
2888#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
2889
2890#define ADC_SMPR2_SMP18_Pos (24U)
2891#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
2892#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */
2893#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
2894#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
2895#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
2896
2897#define ADC_SMPR2_SMP19_Pos (27U)
2898#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
2899#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */
2900#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
2901#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
2902#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
2903
2904/******************** Bit definition for ADC_PCSEL register ********************/
2905#define ADC_PCSEL_PCSEL_Pos (0U)
2906#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */
2907#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */
2908#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */
2909#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */
2910#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */
2911#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */
2912#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */
2913#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */
2914#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */
2915#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */
2916#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */
2917#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */
2918#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */
2919#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */
2920#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */
2921#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */
2922#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */
2923#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */
2924#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */
2925#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */
2926#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */
2927#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */
2928
2929/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/
2930#define ADC_LTR_LT_Pos (0U)
2931#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */
2932#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */
2933
2934/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/
2935#define ADC_HTR_HT_Pos (0U)
2936#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */
2937#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */
2938
2939
2940/******************** Bit definition for ADC_SQR1 register ********************/
2941#define ADC_SQR1_L_Pos (0U)
2942#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
2943#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
2944#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
2945#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
2946#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
2947#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
2948
2949#define ADC_SQR1_SQ1_Pos (6U)
2950#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
2951#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */
2952#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
2953#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
2954#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
2955#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
2956#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
2957
2958#define ADC_SQR1_SQ2_Pos (12U)
2959#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
2960#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */
2961#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
2962#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
2963#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
2964#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
2965#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
2966
2967#define ADC_SQR1_SQ3_Pos (18U)
2968#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
2969#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */
2970#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
2971#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
2972#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
2973#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
2974#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
2975
2976#define ADC_SQR1_SQ4_Pos (24U)
2977#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
2978#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */
2979#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
2980#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
2981#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
2982#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
2983#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
2984
2985/******************** Bit definition for ADC_SQR2 register ********************/
2986#define ADC_SQR2_SQ5_Pos (0U)
2987#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
2988#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */
2989#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
2990#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
2991#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
2992#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
2993#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
2994
2995#define ADC_SQR2_SQ6_Pos (6U)
2996#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
2997#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */
2998#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
2999#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
3000#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
3001#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
3002#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
3003
3004#define ADC_SQR2_SQ7_Pos (12U)
3005#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
3006#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */
3007#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
3008#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
3009#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
3010#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
3011#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
3012
3013#define ADC_SQR2_SQ8_Pos (18U)
3014#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
3015#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */
3016#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
3017#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
3018#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
3019#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
3020#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
3021
3022#define ADC_SQR2_SQ9_Pos (24U)
3023#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
3024#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */
3025#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
3026#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
3027#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
3028#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
3029#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
3030
3031/******************** Bit definition for ADC_SQR3 register ********************/
3032#define ADC_SQR3_SQ10_Pos (0U)
3033#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
3034#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */
3035#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
3036#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
3037#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
3038#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
3039#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
3040
3041#define ADC_SQR3_SQ11_Pos (6U)
3042#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
3043#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */
3044#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
3045#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
3046#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
3047#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
3048#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
3049
3050#define ADC_SQR3_SQ12_Pos (12U)
3051#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
3052#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */
3053#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
3054#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
3055#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
3056#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
3057#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
3058
3059#define ADC_SQR3_SQ13_Pos (18U)
3060#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
3061#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */
3062#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
3063#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
3064#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
3065#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
3066#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
3067
3068#define ADC_SQR3_SQ14_Pos (24U)
3069#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
3070#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */
3071#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
3072#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
3073#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
3074#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
3075#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
3076
3077/******************** Bit definition for ADC_SQR4 register ********************/
3078#define ADC_SQR4_SQ15_Pos (0U)
3079#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
3080#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */
3081#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
3082#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
3083#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
3084#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
3085#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
3086
3087#define ADC_SQR4_SQ16_Pos (6U)
3088#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
3089#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */
3090#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
3091#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
3092#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
3093#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
3094#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
3095/******************** Bit definition for ADC_DR register ********************/
3096#define ADC_DR_RDATA_Pos (0U)
3097#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */
3098#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */
3099
3100/******************** Bit definition for ADC_JSQR register ********************/
3101#define ADC_JSQR_JL_Pos (0U)
3102#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
3103#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */
3104#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
3105#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
3106
3107#define ADC_JSQR_JEXTSEL_Pos (2U)
3108#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
3109#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */
3110#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
3111#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
3112#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
3113#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
3114#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
3115
3116#define ADC_JSQR_JEXTEN_Pos (7U)
3117#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
3118#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */
3119#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
3120#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
3121
3122#define ADC_JSQR_JSQ1_Pos (9U)
3123#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
3124#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */
3125#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
3126#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
3127#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
3128#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
3129#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
3130
3131#define ADC_JSQR_JSQ2_Pos (15U)
3132#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */
3133#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */
3134#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
3135#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
3136#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
3137#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
3138#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */
3139
3140#define ADC_JSQR_JSQ3_Pos (21U)
3141#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
3142#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */
3143#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
3144#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
3145#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
3146#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
3147#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
3148
3149#define ADC_JSQR_JSQ4_Pos (27U)
3150#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
3151#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */
3152#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
3153#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
3154#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
3155#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
3156#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
3157
3158/******************** Bit definition for ADC_OFR1 register ********************/
3159#define ADC_OFR1_OFFSET1_Pos (0U)
3160#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
3161#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
3162#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
3163#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
3164#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
3165#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
3166#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
3167#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
3168#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
3169#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
3170#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
3171#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
3172#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
3173#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
3174#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
3175#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
3176#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
3177#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
3178#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
3179#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
3180#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
3181#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
3182#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
3183#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
3184#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
3185#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
3186#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
3187#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
3188
3189#define ADC_OFR1_OFFSET1_CH_Pos (26U)
3190#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
3191#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */
3192#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
3193#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
3194#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
3195#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
3196#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
3197
3198#define ADC_OFR1_SSATE_Pos (31U)
3199#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */
3200#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */
3201
3202
3203/******************** Bit definition for ADC_OFR2 register ********************/
3204#define ADC_OFR2_OFFSET2_Pos (0U)
3205#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
3206#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
3207#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
3208#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
3209#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
3210#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
3211#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
3212#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
3213#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
3214#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
3215#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
3216#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
3217#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
3218#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
3219#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
3220#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
3221#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
3222#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
3223#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
3224#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
3225#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
3226#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
3227#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
3228#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
3229#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
3230#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
3231#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
3232#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
3233
3234#define ADC_OFR2_OFFSET2_CH_Pos (26U)
3235#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
3236#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */
3237#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
3238#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
3239#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
3240#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
3241#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
3242
3243#define ADC_OFR2_SSATE_Pos (31U)
3244#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */
3245#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */
3246
3247
3248/******************** Bit definition for ADC_OFR3 register ********************/
3249#define ADC_OFR3_OFFSET3_Pos (0U)
3250#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
3251#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
3252#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
3253#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
3254#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
3255#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
3256#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
3257#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
3258#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
3259#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
3260#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
3261#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
3262#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
3263#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
3264#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
3265#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
3266#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
3267#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
3268#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
3269#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
3270#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
3271#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
3272#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
3273#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
3274#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
3275#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
3276#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
3277#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
3278
3279#define ADC_OFR3_OFFSET3_CH_Pos (26U)
3280#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
3281#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */
3282#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
3283#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
3284#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
3285#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
3286#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
3287
3288#define ADC_OFR3_SSATE_Pos (31U)
3289#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */
3290#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */
3291
3292
3293/******************** Bit definition for ADC_OFR4 register ********************/
3294#define ADC_OFR4_OFFSET4_Pos (0U)
3295#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
3296#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
3297#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
3298#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
3299#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
3300#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
3301#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
3302#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
3303#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
3304#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
3305#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
3306#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
3307#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
3308#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
3309#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
3310#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
3311#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
3312#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
3313#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
3314#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
3315#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
3316#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
3317#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
3318#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
3319#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
3320#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
3321#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
3322#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
3323
3324#define ADC_OFR4_OFFSET4_CH_Pos (26U)
3325#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
3326#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */
3327#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
3328#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
3329#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
3330#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
3331#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
3332
3333#define ADC_OFR4_SSATE_Pos (31U)
3334#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */
3335#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */
3336
3337
3338/******************** Bit definition for ADC_JDR1 register ********************/
3339#define ADC_JDR1_JDATA_Pos (0U)
3340#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */
3341#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */
3342#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
3343#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
3344#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
3345#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
3346#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
3347#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
3348#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
3349#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
3350#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
3351#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
3352#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
3353#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
3354#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
3355#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
3356#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
3357#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
3358#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */
3359#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */
3360#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */
3361#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */
3362#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */
3363#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */
3364#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */
3365#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */
3366#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */
3367#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */
3368#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */
3369#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */
3370#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */
3371#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */
3372#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */
3373#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */
3374
3375/******************** Bit definition for ADC_JDR2 register ********************/
3376#define ADC_JDR2_JDATA_Pos (0U)
3377#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */
3378#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */
3379#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
3380#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
3381#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
3382#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
3383#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
3384#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
3385#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
3386#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
3387#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
3388#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
3389#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
3390#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
3391#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
3392#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
3393#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
3394#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
3395#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */
3396#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */
3397#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */
3398#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */
3399#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */
3400#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */
3401#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */
3402#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */
3403#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */
3404#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */
3405#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */
3406#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */
3407#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */
3408#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */
3409#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */
3410#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */
3411
3412/******************** Bit definition for ADC_JDR3 register ********************/
3413#define ADC_JDR3_JDATA_Pos (0U)
3414#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */
3415#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */
3416#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
3417#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
3418#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
3419#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
3420#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
3421#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
3422#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
3423#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
3424#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
3425#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
3426#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
3427#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
3428#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
3429#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
3430#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
3431#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
3432#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */
3433#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */
3434#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */
3435#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */
3436#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */
3437#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */
3438#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */
3439#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */
3440#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */
3441#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */
3442#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */
3443#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */
3444#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */
3445#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */
3446#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */
3447#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */
3448
3449/******************** Bit definition for ADC_JDR4 register ********************/
3450#define ADC_JDR4_JDATA_Pos (0U)
3451#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */
3452#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */
3453#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
3454#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
3455#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
3456#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
3457#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
3458#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
3459#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
3460#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
3461#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
3462#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
3463#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
3464#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
3465#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
3466#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
3467#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
3468#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
3469#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */
3470#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */
3471#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */
3472#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */
3473#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */
3474#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */
3475#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */
3476#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */
3477#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */
3478#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */
3479#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */
3480#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */
3481#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */
3482#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */
3483#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */
3484#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */
3485
3486/******************** Bit definition for ADC_AWD2CR register ********************/
3487#define ADC_AWD2CR_AWD2CH_Pos (0U)
3488#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */
3489#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
3490#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
3491#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
3492#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
3493#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
3494#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
3495#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
3496#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
3497#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
3498#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
3499#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
3500#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
3501#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
3502#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
3503#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
3504#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
3505#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
3506#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
3507#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
3508#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
3509#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
3510
3511/******************** Bit definition for ADC_AWD3CR register ********************/
3512#define ADC_AWD3CR_AWD3CH_Pos (0U)
3513#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
3514#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */
3515#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
3516#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
3517#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
3518#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
3519#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
3520#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
3521#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
3522#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
3523#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
3524#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
3525#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
3526#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
3527#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
3528#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
3529#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
3530#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
3531#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
3532#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
3533#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
3534#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
3535
3536/******************** Bit definition for ADC_DIFSEL register ********************/
3537#define ADC_DIFSEL_DIFSEL_Pos (0U)
3538#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
3539#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */
3540#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
3541#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
3542#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
3543#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
3544#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
3545#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
3546#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
3547#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
3548#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
3549#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
3550#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
3551#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
3552#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
3553#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
3554#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
3555#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
3556#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
3557#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
3558#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
3559#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */
3560
3561/******************** Bit definition for ADC_CALFACT register ********************/
3562#define ADC_CALFACT_CALFACT_S_Pos (0U)
3563#define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
3564#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */
3565#define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
3566#define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
3567#define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
3568#define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
3569#define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
3570#define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
3571#define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
3572#define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
3573#define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
3574#define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
3575#define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
3576#define ADC_CALFACT_CALFACT_D_Pos (16U)
3577#define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
3578#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */
3579#define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
3580#define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
3581#define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
3582#define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
3583#define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
3584#define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
3585#define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
3586#define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
3587#define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
3588#define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
3589#define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
3590
3591/******************** Bit definition for ADC_CALFACT2 register ********************/
3592#define ADC_CALFACT2_LINCALFACT_Pos (0U)
3593#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
3594#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */
3595#define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
3596#define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
3597#define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
3598#define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
3599#define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
3600#define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
3601#define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
3602#define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
3603#define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
3604#define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
3605#define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
3606#define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
3607#define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
3608#define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
3609#define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
3610#define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
3611#define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
3612#define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
3613#define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
3614#define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
3615#define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
3616#define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
3617#define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
3618#define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
3619#define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
3620#define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
3621#define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
3622#define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */
3623#define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
3624#define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
3625
3626/************************* ADC Common registers *****************************/
3627/******************** Bit definition for ADC_CSR register ********************/
3628#define ADC_CSR_ADRDY_MST_Pos (0U)
3629#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
3630#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
3631#define ADC_CSR_EOSMP_MST_Pos (1U)
3632#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
3633#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
3634#define ADC_CSR_EOC_MST_Pos (2U)
3635#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
3636#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
3637#define ADC_CSR_EOS_MST_Pos (3U)
3638#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
3639#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
3640#define ADC_CSR_OVR_MST_Pos (4U)
3641#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
3642#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */
3643#define ADC_CSR_JEOC_MST_Pos (5U)
3644#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
3645#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
3646#define ADC_CSR_JEOS_MST_Pos (6U)
3647#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
3648#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
3649#define ADC_CSR_AWD1_MST_Pos (7U)
3650#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
3651#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
3652#define ADC_CSR_AWD2_MST_Pos (8U)
3653#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
3654#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
3655#define ADC_CSR_AWD3_MST_Pos (9U)
3656#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
3657#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
3658#define ADC_CSR_JQOVF_MST_Pos (10U)
3659#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
3660#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
3661#define ADC_CSR_ADRDY_SLV_Pos (16U)
3662#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
3663#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
3664#define ADC_CSR_EOSMP_SLV_Pos (17U)
3665#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
3666#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
3667#define ADC_CSR_EOC_SLV_Pos (18U)
3668#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
3669#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
3670#define ADC_CSR_EOS_SLV_Pos (19U)
3671#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
3672#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
3673#define ADC_CSR_OVR_SLV_Pos (20U)
3674#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
3675#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
3676#define ADC_CSR_JEOC_SLV_Pos (21U)
3677#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
3678#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */